# DP: Changes for the Linaro 4.7-2014.01 release (documentation).
--- a/src/gcc/doc/extend.texi
+++ b/src/gcc/doc/extend.texi
@@ -8575,12 +8575,17 @@
are @code{long double}.
@end deftypefn
-@deftypefn {Built-in Function} int32_t __builtin_bswap32 (int32_t x)
+@deftypefn {Built-in Function} int16_t __builtin_bswap16 (int16_t x)
Returns @var{x} with the order of the bytes reversed; for example,
-@code{0xaabbccdd} becomes @code{0xddccbbaa}. Byte here always means
+@code{0xaabb} becomes @code{0xbbaa}. Byte here always means
exactly 8 bits.
@end deftypefn
+@deftypefn {Built-in Function} int32_t __builtin_bswap32 (int32_t x)
+Similar to @code{__builtin_bswap16}, except the argument and return types
+are 32-bit.
+@end deftypefn
+
@deftypefn {Built-in Function} int64_t __builtin_bswap64 (int64_t x)
Similar to @code{__builtin_bswap32}, except the argument and return types
are 64-bit.
@@ -13466,7 +13471,6 @@
double __builtin_recipdiv (double, double);
double __builtin_rsqrt (double);
long __builtin_bpermd (long, long);
-int __builtin_bswap16 (int);
@end smallexample
The @code{vec_rsqrt}, @code{__builtin_rsqrt}, and
--- a/src/gcc/doc/fragments.texi
+++ b/src/gcc/doc/fragments.texi
@@ -127,6 +127,29 @@
*mthumb/*mhard-float*
@end smallexample
+@findex MULTILIB_REQUIRED
+@item MULTILIB_REQUIRED
+Sometimes when there are only a few combinations are required, it would
+be a big effort to come up with a @code{MULTILIB_EXCEPTIONS} list to
+cover all undesired ones. In such a case, just listing all the required
+combinations in @code{MULTILIB_REQUIRED} would be more straightforward.
+
+The way to specify the entries in @code{MULTILIB_REQUIRED} is same with
+the way used for @code{MULTILIB_EXCEPTIONS}, only this time what are
+required will be specified. Suppose there are multiple sets of
+@code{MULTILIB_OPTIONS} and only two combinations are required, one
+for ARMv7-M and one for ARMv7-R with hard floating-point ABI and FPU, the
+@code{MULTILIB_REQUIRED} can be set to:
+@smallexample
+@code{MULTILIB_REQUIRED} = mthumb/march=armv7-m
+@code{MULTILIB_REQUIRED} += march=armv7-r/mfloat-abi=hard/mfpu=vfpv3-d16
+@end smallexample
+
+The @code{MULTILIB_REQUIRED} can be used together with
+@code{MULTILIB_EXCEPTIONS}. The option combinations generated from
+@code{MULTILIB_OPTIONS} will be filtered by @code{MULTILIB_EXCEPTIONS}
+and then by @code{MULTILIB_REQUIRED}.
+
@findex MULTILIB_EXTRA_OPTS
@item MULTILIB_EXTRA_OPTS
Sometimes it is desirable that when building multiple versions of
--- a/src/gcc/doc/fsf-funding.7
+++ b/src/gcc/doc/fsf-funding.7
@@ -1,15 +1,7 @@
-.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05)
+.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16)
.\"
.\" Standard preamble:
.\" ========================================================================
-.de Sh \" Subsection heading
-.br
-.if t .Sp
-.ne 5
-.PP
-\fB\\$1\fR
-.PP
-..
.de Sp \" Vertical space (when we can't use .PP)
.if t .sp .5v
.if n .sp
@@ -53,7 +45,7 @@
.el .ds Aq '
.\"
.\" If the F register is turned on, we'll generate index entries on stderr for
-.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index
+.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
.\" entries marked with X<> in POD. Of course, you'll have to process the
.\" output yourself in some meaningful fashion.
.ie \nF \{\
@@ -132,7 +124,7 @@
.\" ========================================================================
.\"
.IX Title "FSF-FUNDING 7"
-.TH FSF-FUNDING 7 "2013-04-11" "gcc-4.7.3" "GNU"
+.TH FSF-FUNDING 7 "2014-01-07" "gcc-4.7.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l
@@ -141,7 +133,7 @@
fsf\-funding \- Funding Free Software
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
-.Sh "Funding Free Software"
+.SS "Funding Free Software"
.IX Subsection "Funding Free Software"
If you want to have more free software a few years from now, it makes
sense for you to help encourage people to contribute funds for its
--- a/src/gcc/doc/gfdl.7
+++ b/src/gcc/doc/gfdl.7
@@ -1,15 +1,7 @@
-.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05)
+.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16)
.\"
.\" Standard preamble:
.\" ========================================================================
-.de Sh \" Subsection heading
-.br
-.if t .Sp
-.ne 5
-.PP
-\fB\\$1\fR
-.PP
-..
.de Sp \" Vertical space (when we can't use .PP)
.if t .sp .5v
.if n .sp
@@ -53,7 +45,7 @@
.el .ds Aq '
.\"
.\" If the F register is turned on, we'll generate index entries on stderr for
-.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index
+.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
.\" entries marked with X<> in POD. Of course, you'll have to process the
.\" output yourself in some meaningful fashion.
.ie \nF \{\
@@ -132,7 +124,7 @@
.\" ========================================================================
.\"
.IX Title "GFDL 7"
-.TH GFDL 7 "2013-04-11" "gcc-4.7.3" "GNU"
+.TH GFDL 7 "2014-01-07" "gcc-4.7.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l
@@ -141,9 +133,9 @@
gfdl \- GNU Free Documentation License
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
-.Sh "\s-1GNU\s0 Free Documentation License"
+.SS "\s-1GNU\s0 Free Documentation License"
.IX Subsection "GNU Free Documentation License"
-.Sh "Version 1.3, 3 November 2008"
+.SS "Version 1.3, 3 November 2008"
.IX Subsection "Version 1.3, 3 November 2008"
.Vb 2
\& Copyright (c) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc.
@@ -600,7 +592,7 @@
The operator of an \s-1MMC\s0 Site may republish an \s-1MMC\s0 contained in the site
under CC-BY-SA on the same site at any time before August 1, 2009,
provided the \s-1MMC\s0 is eligible for relicensing.
-.Sh "\s-1ADDENDUM:\s0 How to use this License for your documents"
+.SS "\s-1ADDENDUM:\s0 How to use this License for your documents"
.IX Subsection "ADDENDUM: How to use this License for your documents"
To use this License in a document you have written, include a copy of
the License in the document and put the following copyright and
--- a/src/gcc/doc/gpl.7
+++ b/src/gcc/doc/gpl.7
@@ -1,15 +1,7 @@
-.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05)
+.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16)
.\"
.\" Standard preamble:
.\" ========================================================================
-.de Sh \" Subsection heading
-.br
-.if t .Sp
-.ne 5
-.PP
-\fB\\$1\fR
-.PP
-..
.de Sp \" Vertical space (when we can't use .PP)
.if t .sp .5v
.if n .sp
@@ -53,7 +45,7 @@
.el .ds Aq '
.\"
.\" If the F register is turned on, we'll generate index entries on stderr for
-.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index
+.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
.\" entries marked with X<> in POD. Of course, you'll have to process the
.\" output yourself in some meaningful fashion.
.ie \nF \{\
@@ -132,7 +124,7 @@
.\" ========================================================================
.\"
.IX Title "GPL 7"
-.TH GPL 7 "2013-04-11" "gcc-4.7.3" "GNU"
+.TH GPL 7 "2014-01-07" "gcc-4.7.4" "GNU"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l
@@ -141,9 +133,9 @@
gpl \- GNU General Public License
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
-.Sh "\s-1GNU\s0 General Public License"
+.SS "\s-1GNU\s0 General Public License"
.IX Subsection "GNU General Public License"
-.Sh "Version 3, 29 June 2007"
+.SS "Version 3, 29 June 2007"
.IX Subsection "Version 3, 29 June 2007"
.Vb 1
\& Copyright (c) 2007 Free Software Foundation, Inc.
@@ -151,7 +143,7 @@
\& Everyone is permitted to copy and distribute verbatim copies of this
\& license document, but changing it is not allowed.
.Ve
-.Sh "Preamble"
+.SS "Preamble"
.IX Subsection "Preamble"
The \s-1GNU\s0 General Public License is a free, copyleft license for
software and other kinds of works.
@@ -215,7 +207,7 @@
.PP
The precise terms and conditions for copying, distribution and
modification follow.
-.Sh "\s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0"
+.SS "\s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0"
.IX Subsection "TERMS AND CONDITIONS"
.IP "0. Definitions." 4
.IX Item "0. Definitions."
@@ -778,9 +770,9 @@
an absolute waiver of all civil liability in connection with the
Program, unless a warranty or assumption of liability accompanies a
copy of the Program in return for a fee.
-.Sh "\s-1END\s0 \s-1OF\s0 \s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0"
+.SS "\s-1END\s0 \s-1OF\s0 \s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0"
.IX Subsection "END OF TERMS AND CONDITIONS"
-.Sh "How to Apply These Terms to Your New Programs"
+.SS "How to Apply These Terms to Your New Programs"
.IX Subsection "How to Apply These Terms to Your New Programs"
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
--- a/src/gcc/doc/implement-cxx.texi
+++ b/src/gcc/doc/implement-cxx.texi
@@ -10,8 +10,8 @@
A conforming implementation of ISO C++ is required to document its
choice of behavior in each of the areas that are designated
``implementation defined''. The following lists all such areas,
-along with the section numbers from the ISO/IEC 14822:1998 and ISO/IEC
-14822:2003 standards. Some areas are only implementation-defined in
+along with the section numbers from the ISO/IEC 14882:1998 and ISO/IEC
+14882:2003 standards. Some areas are only implementation-defined in
one version of the standard.
Some choices depend on the externally determined ABI for the platform
--- a/src/gcc/doc/install.texi
+++ b/src/gcc/doc/install.texi
@@ -1047,6 +1047,15 @@
conventions, etc.@: should not be built. The default is to build a
predefined set of them.
+@item --enable-multiarch
+Specify whether to enable or disable multiarch support. The default is
+to check for glibc start files in a multiarch location, and enable it
+if the files are found. The auto detection is enabled for native builds,
+and for cross builds configured with @option{--with-sysroot}, and without
+@option{--with-native-system-header-dir}.
+More documentation about multiarch can be found at
+@uref{http://wiki.debian.org/Multiarch}.
+
Some targets provide finer-grained control over which multilibs are built
(e.g., @option{--disable-softfloat}):
@table @code
--- a/src/gcc/doc/invoke.texi
+++ b/src/gcc/doc/invoke.texi
@@ -403,13 +403,15 @@
-fsplit-ivs-in-unroller -fsplit-wide-types -fstack-protector @gol
-fstack-protector-all -fstrict-aliasing -fstrict-overflow @gol
-fthread-jumps -ftracer -ftree-bit-ccp @gol
--ftree-builtin-call-dce -ftree-ccp -ftree-ch -ftree-copy-prop @gol
+-ftree-builtin-call-dce -ftree-ccp -ftree-ch @gol
+-ftree-coalesce-inline-vars -ftree-coalesce-vars -ftree-copy-prop @gol
-ftree-copyrename -ftree-dce -ftree-dominator-opts -ftree-dse @gol
-ftree-forwprop -ftree-fre -ftree-loop-if-convert @gol
-ftree-loop-if-convert-stores -ftree-loop-im @gol
-ftree-phiprop -ftree-loop-distribution -ftree-loop-distribute-patterns @gol
-ftree-loop-ivcanon -ftree-loop-linear -ftree-loop-optimize @gol
--ftree-parallelize-loops=@var{n} -ftree-pre -ftree-pta -ftree-reassoc @gol
+-ftree-parallelize-loops=@var{n} -ftree-pre -ftree-partial-pre -ftree-pta @gol
+-ftree-reassoc @gol
-ftree-sink -ftree-sra -ftree-switch-conversion -ftree-tail-merge @gol
-ftree-ter -ftree-vect-loop-version -ftree-vectorize -ftree-vrp @gol
-funit-at-a-time -funroll-all-loops -funroll-loops @gol
@@ -460,6 +462,15 @@
@c Try and put the significant identifier (CPU or system) first,
@c so users have a clue at guessing where the ones they want will be.
+@emph{AArch64 Options}
+@gccoptlist{-mbig-endian -mlittle-endian @gol
+-mgeneral-regs-only @gol
+-mcmodel=tiny -mcmodel=small -mcmodel=large @gol
+-mstrict-align @gol
+-momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol
+-mtls-dialect=desc -mtls-dialect=traditional @gol
+-march=@var{name} -mcpu=@var{name} -mtune=@var{name}}
+
@emph{Adapteva Epiphany Options}
@gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol
-mbranch-cost=@var{num} -mcmove -mnops=@var{num} -msoft-cmpsf @gol
@@ -494,7 +505,8 @@
-mtp=@var{name} -mtls-dialect=@var{dialect} @gol
-mword-relocations @gol
-mfix-cortex-m3-ldrd @gol
--munaligned-access}
+-munaligned-access @gol
+-mneon-for-64bits}
@emph{AVR Options}
@gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
@@ -1429,11 +1441,13 @@
for the plugin called @var{name}.
@item -fdump-ada-spec@r{[}-slim@r{]}
-For C and C++ source and include files, generate corresponding Ada
-specs. @xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn,
+@opindex fdump-ada-spec
+For C and C++ source and include files, generate corresponding Ada specs.
+@xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn,
GNAT User's Guide}, which provides detailed documentation on this feature.
@item -fdump-go-spec=@var{file}
+@opindex fdump-go-spec
For input files in any language, generate corresponding Go
declarations in @var{file}. This generates Go @code{const},
@code{type}, @code{var}, and @code{func} declarations which may be a
@@ -6237,8 +6251,8 @@
Optimize yet more. @option{-O3} turns on all optimizations specified
by @option{-O2} and also turns on the @option{-finline-functions},
@option{-funswitch-loops}, @option{-fpredictive-commoning},
-@option{-fgcse-after-reload}, @option{-ftree-vectorize} and
-@option{-fipa-cp-clone} options.
+@option{-fgcse-after-reload}, @option{-ftree-vectorize},
+@option{-ftree-partial-pre} and @option{-fipa-cp-clone} options.
@item -O0
@opindex O0
@@ -7033,6 +7047,11 @@
Perform partial redundancy elimination (PRE) on trees. This flag is
enabled by default at @option{-O2} and @option{-O3}.
+@item -ftree-partial-pre
+@opindex ftree-partial-pre
+Make partial redundancy elimination (PRE) more aggressive. This flag is
+enabled by default at @option{-O3}.
+
@item -ftree-forwprop
@opindex ftree-forwprop
Perform forward propagation on trees. This flag is enabled by default
@@ -7428,6 +7447,24 @@
variable names which more closely resemble the original variables. This flag
is enabled by default at @option{-O} and higher.
+@item -ftree-coalesce-inlined-vars
+Tell the copyrename pass (see @option{-ftree-copyrename}) to attempt to
+combine small user-defined variables too, but only if they were inlined
+from other functions. It is a more limited form of
+@option{-ftree-coalesce-vars}. This may harm debug information of such
+inlined variables, but it will keep variables of the inlined-into
+function apart from each other, such that they are more likely to
+contain the expected values in a debugging session. This was the
+default in GCC versions older than 4.7.
+
+@item -ftree-coalesce-vars
+Tell the copyrename pass (see @option{-ftree-copyrename}) to attempt to
+combine small user-defined variables too, instead of just compiler
+temporaries. This may severely limit the ability to debug an optimized
+program compiled with @option{-fno-var-tracking-assignments}. In the
+negated form, this flag prevents SSA coalescing of user variables,
+including inlined ones. This option is enabled by default.
+
@item -ftree-ter
@opindex ftree-ter
Perform temporary expression replacement during the SSA->normal phase. Single
@@ -10329,6 +10366,7 @@
@c in Machine Dependent Options
@menu
+* AArch64 Options::
* Adapteva Epiphany Options::
* ARM Options::
* AVR Options::
@@ -10537,6 +10575,125 @@
@end table
+@node AArch64 Options
+@subsection AArch64 Options
+@cindex AArch64 Options
+
+These options are defined for AArch64 implementations:
+
+@table @gcctabopt
+
+@item -mbig-endian
+@opindex mbig-endian
+Generate big-endian code. This is the default when GCC is configured for an
+@samp{aarch64_be-*-*} target.
+
+@item -mgeneral-regs-only
+@opindex mgeneral-regs-only
+Generate code which uses only the general registers.
+
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate little-endian code. This is the default when GCC is configured for an
+@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target.
+
+@item -mcmodel=tiny
+@opindex mcmodel=tiny
+Generate code for the tiny code model. The program and its statically defined
+symbols must be within 1GB of each other. Pointers are 64 bits. Programs can
+be statically or dynamically linked. This model is not fully implemented and
+mostly treated as "small".
+
+@item -mcmodel=small
+@opindex mcmodel=small
+Generate code for the small code model. The program and its statically defined
+symbols must be within 4GB of each other. Pointers are 64 bits. Programs can
+be statically or dynamically linked. This is the default code model.
+
+@item -mcmodel=large
+@opindex mcmodel=large
+Generate code for the large code model. This makes no assumptions about
+addresses and sizes of sections. Pointers are 64 bits. Programs can be
+statically linked only.
+
+@item -mstrict-align
+@opindex mstrict-align
+Do not assume that unaligned memory references will be handled by the system.
+
+@item -momit-leaf-frame-pointer
+@item -mno-omit-leaf-frame-pointer
+@opindex momit-leaf-frame-pointer
+@opindex mno-omit-leaf-frame-pointer
+Omit or keep the frame pointer in leaf functions. The former behaviour is the
+default.
+
+@item -mtls-dialect=desc
+@opindex mtls-dialect=desc
+Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
+of TLS variables. This is the default.
+
+@item -mtls-dialect=traditional
+@opindex mtls-dialect=traditional
+Use traditional TLS as the thread-local storage mechanism for dynamic accesses
+of TLS variables.
+
+@item -march=@var{name}
+@opindex march
+Specify the name of the target architecture, optionally suffixed by one or
+more feature modifiers. This option has the form
+@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the
+only value for @var{arch} is @samp{armv8-a}. The possible values for
+@var{feature} are documented in the sub-section below.
+
+Where conflicting feature modifiers are specified, the right-most feature is
+used.
+
+GCC uses this name to determine what kind of instructions it can emit when
+generating assembly code. This option can be used in conjunction with or
+instead of the @option{-mcpu=} option.
+
+@item -mcpu=@var{name}
+@opindex mcpu
+Specify the name of the target processor, optionally suffixed by one or more
+feature modifiers. This option has the form
+@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where the
+possible values for @var{cpu} are @samp{generic}, @samp{large}. The
+possible values for @var{feature} are documented in the sub-section
+below.
+
+Where conflicting feature modifiers are specified, the right-most feature is
+used.
+
+GCC uses this name to determine what kind of instructions it can emit when
+generating assembly code.
+
+@item -mtune=@var{name}
+@opindex mtune
+Specify the name of the processor to tune the performance for. The code will
+be tuned as if the target processor were of the type specified in this option,
+but still using instructions compatible with the target processor specified
+by a @option{-mcpu=} option. This option cannot be suffixed by feature
+modifiers.
+
+@end table
+
+@subsubsection @option{-march} and @option{-mcpu} feature modifiers
+@cindex @option{-march} feature modifiers
+@cindex @option{-mcpu} feature modifiers
+Feature modifiers used with @option{-march} and @option{-mcpu} can be one
+the following:
+
+@table @samp
+@item crypto
+Enable Crypto extension. This implies Advanced SIMD is enabled.
+@item fp
+Enable floating-point instructions.
+@item simd
+Enable Advanced SIMD instructions. This implies floating-point instructions
+are enabled. This is the default for all current possible values for options
+@option{-march} and @option{-mcpu=}.
+@end table
+
@node ARM Options
@subsection ARM Options
@cindex ARM options
@@ -10948,6 +11105,11 @@
preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} will also be
defined.
+@item -mneon-for-64bits
+@opindex mneon-for-64bits
+Enables using Neon to handle scalar 64-bits operations. This is
+disabled by default since the cost of moving data from core registers
+to Neon is high.
@end table
@node AVR Options
--- a/src/gcc/doc/md.texi
+++ b/src/gcc/doc/md.texi
@@ -1653,6 +1653,62 @@
the meanings of that architecture's constraints.
@table @emph
+@item AArch64 family---@file{config/aarch64/constraints.md}
+@table @code
+@item k
+The stack pointer register (@code{SP})
+
+@item w
+Floating point or SIMD vector register
+
+@item I
+Integer constant that is valid as an immediate operand in an @code{ADD}
+instruction
+
+@item J
+Integer constant that is valid as an immediate operand in a @code{SUB}
+instruction (once negated)
+
+@item K
+Integer constant that can be used with a 32-bit logical instruction
+
+@item L
+Integer constant that can be used with a 64-bit logical instruction
+
+@item M
+Integer constant that is valid as an immediate operand in a 32-bit @code{MOV}
+pseudo instruction. The @code{MOV} may be assembled to one of several different
+machine instructions depending on the value
+
+@item N
+Integer constant that is valid as an immediate operand in a 64-bit @code{MOV}
+pseudo instruction
+
+@item S
+An absolute symbolic address or a label reference
+
+@item Y
+Floating point constant zero
+
+@item Z
+Integer constant zero
+
+@item Usa
+An absolute symbolic address
+
+@item Ush
+The high part (bits 12 and upwards) of the pc-relative address of a symbol
+within 4GB of the instruction
+
+@item Q
+A memory address which uses a single base register with no offset
+
+@item Ump
+A memory address suitable for a load/store pair instruction in SI, DI, SF and
+DF modes
+
+@end table
+
@item ARM family---@file{config/arm/arm.h}
@table @code
@item f
@@ -4736,6 +4792,10 @@
Vector shift and rotate instructions that take vectors as operand 2
instead of a scalar type.
+@cindex @code{bswap@var{m}2} instruction pattern
+@item @samp{bswap@var{m}2}
+Reverse the order of bytes of operand 1 and store the result in operand 0.
+
@cindex @code{neg@var{m}2} instruction pattern
@cindex @code{ssneg@var{m}2} instruction pattern
@cindex @code{usneg@var{m}2} instruction pattern
@@ -8888,6 +8948,7 @@
@menu
* Mode Iterators:: Generating variations of patterns for different modes.
* Code Iterators:: Doing the same for codes.
+* Int Iterators:: Doing the same for integers.
@end menu
@node Mode Iterators
@@ -9159,4 +9220,81 @@
@dots{}
@end smallexample
+@node Int Iterators
+@subsection Int Iterators
+@cindex int iterators in @file{.md} files
+@findex define_int_iterator
+@findex define_int_attr
+
+Int iterators operate in a similar way to code iterators. @xref{Code Iterators}.
+
+The construct:
+
+@smallexample
+(define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")])
+@end smallexample
+
+defines a pseudo integer constant @var{name} that can be instantiated as
+@var{inti} if condition @var{condi} is true. Each @var{int}
+must have the same rtx format. @xref{RTL Classes}. Int iterators can appear
+in only those rtx fields that have 'i' as the specifier. This means that
+each @var{int} has to be a constant defined using define_constant or
+define_c_enum.
+
+As with mode and code iterators, each pattern that uses @var{name} will be
+expanded @var{n} times, once with all uses of @var{name} replaced by
+@var{int1}, once with all uses replaced by @var{int2}, and so on.
+@xref{Defining Mode Iterators}.
+
+It is possible to define attributes for ints as well as for codes and modes.
+Attributes are defined using:
+
+@smallexample
+(define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")])
+@end smallexample
+
+Here's an example of int iterators in action, taken from the ARM port:
+
+@smallexample
+(define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG])
+
+(define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")])
+
+(define_insn "neon_vq"
+ [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+ (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
+ (match_operand:SI 2 "immediate_operand" "i")]
+ QABSNEG))]
+ "TARGET_NEON"
+ "vq.\t%0, %1"
+ [(set_attr "neon_type" "neon_vqneg_vqabs")]
+)
+
+@end smallexample
+
+This is equivalent to:
+
+@smallexample
+(define_insn "neon_vqabs"
+ [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+ (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
+ (match_operand:SI 2 "immediate_operand" "i")]
+ UNSPEC_VQABS))]
+ "TARGET_NEON"
+ "vqabs.\t%0, %1"
+ [(set_attr "neon_type" "neon_vqneg_vqabs")]
+)
+
+(define_insn "neon_vqneg"
+ [(set (match_operand:VDQIW 0 "s_register_operand" "=w")
+ (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w")
+ (match_operand:SI 2 "immediate_operand" "i")]
+ UNSPEC_VQNEG))]
+ "TARGET_NEON"
+ "vqneg.\t%0, %1"
+ [(set_attr "neon_type" "neon_vqneg_vqabs")]
+)
+
+@end smallexample
+
@end ifset
--- a/src/gcc/doc/sourcebuild.texi
+++ b/src/gcc/doc/sourcebuild.texi
@@ -1502,11 +1502,19 @@
@item arm_neon_hw
Test system supports executing NEON instructions.
+@item arm_neonv2_hw
+Test system supports executing NEON v2 instructions.
+
@item arm_neon_ok
@anchor{arm_neon_ok}
ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp} or compatible
options. Some multilibs may be incompatible with these options.
+@item arm_neonv2_ok
+@anchor{arm_neon2_ok}
+ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp} or compatible
+options. Some multilibs may be incompatible with these options.
+
@item arm_neon_fp16_ok
@anchor{arm_neon_fp16_ok}
ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or compatible
--- a/src/gcc/doc/tm.texi
+++ b/src/gcc/doc/tm.texi
@@ -700,6 +700,14 @@
Targets may provide a string object type that can be used within and between C, C++ and their respective Objective-C dialects. A string object might, for example, embed encoding and length information. These objects are considered opaque to the compiler and handled as references. An ideal implementation makes the composition of the string object match that of the Objective-C @code{NSString} (@code{NXString} for GNUStep), allowing efficient interworking between C-only and Objective-C code. If a target implements string objects then this hook should return a reference to such an object constructed from the normal `C' string representation provided in @var{string}. At present, the hook is used by Objective-C only, to obtain a common-format string object when the target provides one.
@end deftypefn
+@deftypefn {C Target Hook} void TARGET_OBJC_DECLARE_UNRESOLVED_CLASS_REFERENCE (const char *@var{classname})
+Declare that Objective C class @var{classname} is referenced by the current TU.
+@end deftypefn
+
+@deftypefn {C Target Hook} void TARGET_OBJC_DECLARE_CLASS_DEFINITION (const char *@var{classname})
+Declare that Objective C class @var{classname} is defined by the current TU.
+@end deftypefn
+
@deftypefn {C Target Hook} bool TARGET_STRING_OBJECT_REF_TYPE_P (const_tree @var{stringref})
If a target implements string objects then this hook should return @code{true} if @var{stringref} is a valid reference to such an object.
@end deftypefn
@@ -8258,20 +8266,6 @@
macro to provide more human-readable names.
@end defmac
-@defmac ASM_DECLARE_CLASS_REFERENCE (@var{stream}, @var{name})
-A C statement (sans semicolon) to output to the stdio stream
-@var{stream} commands to declare that the label @var{name} is an
-Objective-C class reference. This is only needed for targets whose
-linkers have special support for NeXT-style runtimes.
-@end defmac
-
-@defmac ASM_DECLARE_UNRESOLVED_REFERENCE (@var{stream}, @var{name})
-A C statement (sans semicolon) to output to the stdio stream
-@var{stream} commands to declare that the label @var{name} is an
-unresolved Objective-C class reference. This is only needed for targets
-whose linkers have special support for NeXT-style runtimes.
-@end defmac
-
@node Initialization
@subsection How Initialization Functions Are Handled
@cindex initialization routines
@@ -9495,6 +9489,10 @@
True if the @code{.debug_pubtypes} and @code{.debug_pubnames} sections should be emitted. These sections are not used on most platforms, and in particular GDB does not use them.
@end deftypevr
+@deftypevr {Target Hook} bool TARGET_FORCE_AT_COMP_DIR
+True if the @code{DW_AT_comp_dir} attribute should be emitted for each compilation unit. This attribute is required for the darwin linker to emit debug information.
+@end deftypevr
+
@deftypevr {Target Hook} bool TARGET_DELAY_SCHED2
True if sched2 is not to be run at its normal place. This usually means it will be run as part of machine-specific reorg.
@end deftypevr
--- a/src/gcc/doc/tm.texi.in
+++ b/src/gcc/doc/tm.texi.in
@@ -696,6 +696,10 @@
@hook TARGET_OBJC_CONSTRUCT_STRING_OBJECT
+@hook TARGET_OBJC_DECLARE_UNRESOLVED_CLASS_REFERENCE
+
+@hook TARGET_OBJC_DECLARE_CLASS_DEFINITION
+
@hook TARGET_STRING_OBJECT_REF_TYPE_P
@hook TARGET_CHECK_STRING_OBJECT_FORMAT_ARG
@@ -8157,20 +8161,6 @@
macro to provide more human-readable names.
@end defmac
-@defmac ASM_DECLARE_CLASS_REFERENCE (@var{stream}, @var{name})
-A C statement (sans semicolon) to output to the stdio stream
-@var{stream} commands to declare that the label @var{name} is an
-Objective-C class reference. This is only needed for targets whose
-linkers have special support for NeXT-style runtimes.
-@end defmac
-
-@defmac ASM_DECLARE_UNRESOLVED_REFERENCE (@var{stream}, @var{name})
-A C statement (sans semicolon) to output to the stdio stream
-@var{stream} commands to declare that the label @var{name} is an
-unresolved Objective-C class reference. This is only needed for targets
-whose linkers have special support for NeXT-style runtimes.
-@end defmac
-
@node Initialization
@subsection How Initialization Functions Are Handled
@cindex initialization routines
@@ -9388,6 +9378,8 @@
@hook TARGET_WANT_DEBUG_PUB_SECTIONS
+@hook TARGET_FORCE_AT_COMP_DIR
+
@hook TARGET_DELAY_SCHED2
@hook TARGET_DELAY_VARTRACK
--- a/src/gcc/fortran/intrinsic.texi
+++ b/src/gcc/fortran/intrinsic.texi
@@ -9209,7 +9209,7 @@
@item @emph{Arguments}:
@multitable @columnfractions .15 .70
@item @var{X} @tab Shall be of type @code{REAL}.
-@item @var{S} @tab (Optional) shall be of type @code{REAL} and
+@item @var{S} @tab Shall be of type @code{REAL} and
not equal to zero.
@end multitable
@@ -10134,9 +10134,12 @@
Restarts or queries the state of the pseudorandom number generator used by
@code{RANDOM_NUMBER}.
-If @code{RANDOM_SEED} is called without arguments, it is initialized to
-a default state. The example below shows how to initialize the random
-seed based on the system's time.
+If @code{RANDOM_SEED} is called without arguments, it is initialized
+to a default state. The example below shows how to initialize the
+random seed with a varying seed in order to ensure a different random
+number sequence for each invocation of the program. Note that setting
+any of the seed values to zero should be avoided as it can result in
+poor quality random numbers being generated.
@item @emph{Standard}:
Fortran 95 and later
@@ -10164,20 +10167,53 @@
@item @emph{Example}:
@smallexample
-SUBROUTINE init_random_seed()
- INTEGER :: i, n, clock
- INTEGER, DIMENSION(:), ALLOCATABLE :: seed
-
- CALL RANDOM_SEED(size = n)
- ALLOCATE(seed(n))
-
- CALL SYSTEM_CLOCK(COUNT=clock)
-
- seed = clock + 37 * (/ (i - 1, i = 1, n) /)
- CALL RANDOM_SEED(PUT = seed)
-
- DEALLOCATE(seed)
-END SUBROUTINE
+subroutine init_random_seed()
+ implicit none
+ integer, allocatable :: seed(:)
+ integer :: i, n, un, istat, dt(8), pid, t(2), s
+ integer(8) :: count, tms
+
+ call random_seed(size = n)
+ allocate(seed(n))
+ ! First try if the OS provides a random number generator
+ open(newunit=un, file="/dev/urandom", access="stream", &
+ form="unformatted", action="read", status="old", iostat=istat)
+ if (istat == 0) then
+ read(un) seed
+ close(un)
+ else
+ ! Fallback to XOR:ing the current time and pid. The PID is
+ ! useful in case one launches multiple instances of the same
+ ! program in parallel.
+ call system_clock(count)
+ if (count /= 0) then
+ t = transfer(count, t)
+ else
+ call date_and_time(values=dt)
+ tms = (dt(1) - 1970) * 365_8 * 24 * 60 * 60 * 1000 &
+ + dt(2) * 31_8 * 24 * 60 * 60 * 1000 &
+ + dt(3) * 24 * 60 * 60 * 60 * 1000 &
+ + dt(5) * 60 * 60 * 1000 &
+ + dt(6) * 60 * 1000 + dt(7) * 1000 &
+ + dt(8)
+ t = transfer(tms, t)
+ end if
+ s = ieor(t(1), t(2))
+ pid = getpid() + 1099279 ! Add a prime
+ s = ieor(s, pid)
+ if (n >= 3) then
+ seed(1) = t(1) + 36269
+ seed(2) = t(2) + 72551
+ seed(3) = pid
+ if (n > 3) then
+ seed(4:) = s + 37 * (/ (i, i = 0, n - 4) /)
+ end if
+ else
+ seed = s + 37 * (/ (i, i = 0, n - 1 ) /)
+ end if
+ end if
+ call random_seed(put=seed)
+end subroutine init_random_seed
@end smallexample
@item @emph{See also}: