diff options
| -rw-r--r-- | debian/changelog | 3 | ||||
| -rw-r--r-- | debian/patches/svn-updates.diff | 4120 |
2 files changed, 3458 insertions, 665 deletions
diff --git a/debian/changelog b/debian/changelog index a42dcd6..da1ecbe 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,5 +1,6 @@ gcc-4.8 (4.8.2-22) UNRELEASED; urgency=medium + * Update to SVN 20140505 (r210076) from the gcc-4_8-branch. * Disable the libsanitizer build on sparc, still fails to build. * Install only versioned gcc-ar gcc-nm gcc-ranlib binaries for the hppa64 cross compiler, update hppa64 alternatives. Closes: #745967. @@ -7,7 +8,7 @@ gcc-4.8 (4.8.2-22) UNRELEASED; urgency=medium * Ensure that the common libs (built from the next GCC version) are available when building without common libs. - -- Matthias Klose <doko@debian.org> Sun, 27 Apr 2014 12:43:30 +0200 + -- Matthias Klose <doko@debian.org> Mon, 05 May 2014 20:29:25 +0200 gcc-4.8 (4.8.2-21) unstable; urgency=medium diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff index febea6e..139ea0f 100644 --- a/debian/patches/svn-updates.diff +++ b/debian/patches/svn-updates.diff @@ -1,10 +1,10 @@ -# DP: updates from the 4.8 branch upto 20140424 (r209749). +# DP: updates from the 4.8 branch upto 20140505 (r210076). last_updated() { cat > ${dir}LAST_UPDATED <<EOF -Thu Apr 24 16:38:34 CEST 2014 -Thu Apr 24 14:38:34 UTC 2014 (revision 209749) +Mon May 5 20:24:06 CEST 2014 +Mon May 5 18:24:06 UTC 2014 (revision 210076) EOF } @@ -3977,6 +3977,28 @@ Index: libstdc++-v3/include/debug/macros.h _M_message(__gnu_debug::__msg_unpartitioned_pred) \ ._M_iterator(_First, #_First) \ ._M_iterator(_Last, #_Last) \ +Index: libstdc++-v3/include/std/tuple +=================================================================== +--- a/src/libstdc++-v3/include/std/tuple (.../tags/gcc_4_8_2_release) ++++ b/src/libstdc++-v3/include/std/tuple (.../branches/gcc-4_8-branch) +@@ -755,7 +755,7 @@ + typename tuple_element<__i, tuple<_Elements...>>::type + >::type + get(tuple<_Elements...>& __t) noexcept +- { return __get_helper<__i>(__t); } ++ { return std::__get_helper<__i>(__t); } + + template<std::size_t __i, typename... _Elements> + constexpr typename __add_c_ref< +@@ -762,7 +762,7 @@ + typename tuple_element<__i, tuple<_Elements...>>::type + >::type + get(const tuple<_Elements...>& __t) noexcept +- { return __get_helper<__i>(__t); } ++ { return std::__get_helper<__i>(__t); } + + template<std::size_t __i, typename... _Elements> + constexpr typename __add_r_ref< Index: libstdc++-v3/include/std/future =================================================================== --- a/src/libstdc++-v3/include/std/future (.../tags/gcc_4_8_2_release) @@ -4138,7 +4160,13 @@ Index: libstdc++-v3/ChangeLog =================================================================== --- a/src/libstdc++-v3/ChangeLog (.../tags/gcc_4_8_2_release) +++ b/src/libstdc++-v3/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,172 @@ +@@ -1,3 +1,178 @@ ++2014-04-27 Jonathan Wakely <jwakely@redhat.com> ++ ++ PR libstdc++/60497 ++ * include/std/tuple (get): Qualify calls to prevent ADL. ++ * testsuite/20_util/tuple/60497.cc: New. ++ +2012-04-05 Dominique d'Humieres <dominiq@lps.ens.fr> + Jack Howarth <howarth@bromo.med.uc.edu> + @@ -4787,6 +4815,46 @@ Index: libstdc++-v3/testsuite/23_containers/vector/allocator/move_assign.cc + test03(); return 0; } +Index: libstdc++-v3/testsuite/20_util/tuple/60497.cc +=================================================================== +--- a/src/libstdc++-v3/testsuite/20_util/tuple/60497.cc (.../tags/gcc_4_8_2_release) ++++ b/src/libstdc++-v3/testsuite/20_util/tuple/60497.cc (.../branches/gcc-4_8-branch) +@@ -0,0 +1,35 @@ ++// { dg-options "-std=gnu++11" } ++// { dg-do compile } ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// ++// This file is part of the GNU ISO C++ Library. This library is free ++// software; you can redistribute it and/or modify it under the ++// terms of the GNU General Public License as published by the ++// Free Software Foundation; either version 3, or (at your option) ++// any later version. ++ ++// This library is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License along ++// with this library; see the file COPYING3. If not see ++// <http://www.gnu.org/licenses/>. ++ ++// libstdc++/60497 ++ ++#include <tuple> ++ ++struct A; ++template<typename T> struct B { T t; }; ++ ++using element_type = B<A>*; ++using tuple_type = std::tuple<element_type>; ++ ++tuple_type t; ++const tuple_type ct; ++ ++auto a = std::get<0>(t); ++auto b = std::get<0>(ct); Index: libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc =================================================================== --- a/src/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc (.../tags/gcc_4_8_2_release) @@ -8951,7 +9019,7 @@ Index: gcc/DATESTAMP +++ b/src/gcc/DATESTAMP (.../branches/gcc-4_8-branch) @@ -1 +1 @@ -20131016 -+20140424 ++20140505 Index: gcc/value-prof.c =================================================================== --- a/src/gcc/value-prof.c (.../tags/gcc_4_8_2_release) @@ -9327,7 +9395,7 @@ Index: gcc/configure + .align 4 + smac %g2, %g3, %g1 + umac %g2, %g3, %g1 -+ cas [%g2], %g3, %g1' > conftest.s ++ casa [%g2] 0xb, %g3, %g1' > conftest.s + if { ac_try='$gcc_cv_as $gcc_cv_as_flags -Aleon -o conftest.o conftest.s >&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 @@ -9893,7 +9961,269 @@ Index: gcc/ChangeLog =================================================================== --- a/src/gcc/ChangeLog (.../tags/gcc_4_8_2_release) +++ b/src/gcc/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,5067 @@ +@@ -1,3 +1,5329 @@ ++2014-05-05 Richard Biener <rguenther@suse.de> ++ ++ Backport from mainline ++ 2014-04-23 Richard Biener <rguenther@suse.de> ++ ++ PR middle-end/60895 ++ * tree-inline.c (declare_return_variable): Use mark_addressable. ++ ++ 2014-04-07 Richard Biener <rguenther@suse.de> ++ ++ PR middle-end/60750 ++ * tree-ssa-operands.c (maybe_add_call_vops): Also add VDEFs ++ for noreturn calls. ++ * tree-cfgcleanup.c (fixup_noreturn_call): Do not remove VDEFs. ++ ++ 2014-04-14 Richard Biener <rguenther@suse.de> ++ ++ PR tree-optimization/59817 ++ PR tree-optimization/60453 ++ * graphite-scop-detection.c (graphite_can_represent_scev): Complete ++ recursion to catch all CHRECs in the scalar evolution and restrict ++ the predicate for the remains appropriately. ++ ++ 2014-04-17 Richard Biener <rguenther@suse.de> ++ ++ PR tree-optimization/60836 ++ * tree-vect-loop.c (vect_create_epilog_for_reduction): Force ++ initial PHI args to be gimple values. ++ ++2014-05-05 Jakub Jelinek <jakub@redhat.com> ++ ++ Backported from mainline ++ 2014-04-25 Jakub Jelinek <jakub@redhat.com> ++ ++ PR tree-optimization/60960 ++ * tree-vect-generic.c (expand_vector_operation): Only call ++ expand_vector_divmod if type's mode satisfies VECTOR_MODE_P. ++ ++2014-05-04 Peter Bergner <bergner@vnet.ibm.com> ++ ++ * config/rs6000/rs6000.h (RS6000_BTM_HARD_FLOAT): New define. ++ (RS6000_BTM_COMMON): Add RS6000_BTM_HARD_FLOAT. ++ (TARGET_EXTRA_BUILTINS): Add TARGET_HARD_FLOAT. ++ * config/rs6000/rs6000-builtin.def (BU_MISC_1): ++ Use RS6000_BTM_HARD_FLOAT. ++ (BU_MISC_2): Likewise. ++ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Handle ++ RS6000_BTM_HARD_FLOAT. ++ (rs6000_option_override_internal): Enforce -mhard-float if -mhard-dfp ++ is explicitly used. ++ (rs6000_invalid_builtin): Add hard floating builtin support. ++ (rs6000_expand_builtin): Relax the gcc_assert to allow the new ++ hard float builtins. ++ (rs6000_builtin_mask_names): Add RS6000_BTM_HARD_FLOAT. ++ ++2014-05-03 Joey Ye <joey.ye@arm.com> ++ ++ Backport from mainline r209463 ++ 2014-04-17 Joey Ye <joey.ye@arm.com> ++ ++ * opts.c (OPT_fif_conversion, OPT_fif_conversion2): Disable for Og. ++ ++2014-05-03 Oleg Endo <olegendo@gcc.gnu.org> ++ ++ Back port from mainline ++ PR target/61026 ++ * config/sh/sh.c: Include stdlib headers before everything else. ++ ++2014-05-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com> ++ ++ PR tree-optimization/60930 ++ * gimple-ssa-strength-reduction.c (create_mul_imm_cand): Reject ++ creating a multiply candidate by folding two constant ++ multiplicands when the result overflows. ++ ++2014-05-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com> ++ ++ * config/aarch64/aarch64.h (TARGET_SIMD): Take AARCH64_ISA_SIMD ++ into account. ++ (TARGET_FLOAT): Take AARCH64_ISA_FP into account. ++ ++2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com> ++ ++ Back port from mainline ++ 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com> ++ ++ * doc/extend.texi (PowerPC Built-in Functions): Document new ++ powerpc extended divide, bcd, pack/unpack 128-bit, builtin ++ functions. ++ (PowerPC AltiVec/VSX Built-in Functions): Likewise. ++ ++ * config/rs6000/predicates.md (const_0_to_3_operand): New ++ predicate to match 0..3 integer constants. ++ ++ * config/rs6000/rs6000-builtin.def (BU_DFP_MISC_1): Add new macros ++ to support adding miscellaneous builtin functions. ++ (BU_DFP_MISC_2): Likewise. ++ (BU_P7_MISC_1): Likewise. ++ (BU_P7_MISC_2): Likewise. ++ (BU_P8V_MISC_3): Likewise. ++ (BU_MISC_1): Likewise. ++ (BU_MISC_2): Likewise. ++ (DIVWE): Add extended divide builtin functions. ++ (DIVWEO): Likewise. ++ (DIVWEU): Likewise. ++ (DIVWEUO): Likewise. ++ (DIVDE): Likewise. ++ (DIVDEO): Likewise. ++ (DIVDEU): Likewise. ++ (DIVDEUO): Likewise. ++ (DXEX): Add decimal floating-point builtin functions. ++ (DXEXQ): Likewise. ++ (DDEDPD): Likewise. ++ (DDEDPDQ): Likewise. ++ (DENBCD): Likewise. ++ (DENBCDQ): Likewise. ++ (DIEX): Likewise. ++ (DIEXQ): Likewise. ++ (DSCLI): Likewise. ++ (DSCLIQ): Likewise. ++ (DSCRI): Likewise. ++ (DSCRIQ): Likewise. ++ (CDTBCD): Add new BCD builtin functions. ++ (CBCDTD): Likewise. ++ (ADDG6S): Likewise. ++ (BCDADD): Likewise. ++ (BCDADD_LT): Likewise. ++ (BCDADD_EQ): Likewise. ++ (BCDADD_GT): Likewise. ++ (BCDADD_OV): Likewise. ++ (BCDSUB): Likewise. ++ (BCDSUB_LT): Likewise. ++ (BCDSUB_EQ): Likewise. ++ (BCDSUB_GT): Likewise. ++ (BCDSUB_OV): Likewise. ++ (PACK_TD): Add new pack/unpack 128-bit type builtin functions. ++ (UNPACK_TD): Likewise. ++ (PACK_TF): Likewise. ++ (UNPACK_TF): Likewise. ++ (UNPACK_TF_0): Likewise. ++ (UNPACK_TF_1): Likewise. ++ (PACK_V1TI): Likewise. ++ (UNPACK_V1TI): Likewise. ++ ++ * config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add ++ support for decimal floating point builtin functions. ++ (rs6000_expand_ternop_builtin): Add checks for the new builtin ++ functions that take constant arguments. ++ (rs6000_invalid_builtin): Add decimal floating point builtin ++ support. ++ (rs6000_init_builtins): Setup long double, _Decimal64, and ++ _Decimal128 types for new builtin functions. ++ (builtin_function_type): Set the unsigned flags appropriately for ++ the new builtin functions. ++ (rs6000_opt_masks): Add support for decimal floating point builtin ++ functions. ++ ++ * config/rs6000/rs6000.h (RS6000_BTM_DFP): Add support for decimal ++ floating point builtin functions. ++ (RS6000_BTM_COMMON): Likewise. ++ (RS6000_BTI_long_double): Likewise. ++ (RS6000_BTI_dfloat64): Likewise. ++ (RS6000_BTI_dfloat128): Likewise. ++ (long_double_type_internal_node): Likewise. ++ (dfloat64_type_internal_node): Likewise. ++ (dfloat128_type_internal_node): Likewise. ++ ++ * config/rs6000/altivec.h (UNSPEC_BCDADD): Add support for ISA ++ 2.07 bcd arithmetic instructions. ++ (UNSPEC_BCDSUB): Likewise. ++ (UNSPEC_BCD_OVERFLOW): Likewise. ++ (UNSPEC_BCD_ADD_SUB): Likewise. ++ (bcd_add_sub): Likewise. ++ (BCD_TEST): Likewise. ++ (bcd<bcd_add_sub>): Likewise. ++ (bcd<bcd_add_sub>_test): Likewise. ++ (bcd<bcd_add_sub>_test2): Likewise. ++ (bcd<bcd_add_sub>_<code>): Likewise. ++ (peephole2 for combined bcd ops): Likewise. ++ ++ * config/rs6000/dfp.md (UNSPEC_DDEDPD): Add support for new ++ decimal floating point builtin functions. ++ (UNSPEC_DENBCD): Likewise. ++ (UNSPEC_DXEX): Likewise. ++ (UNSPEC_DIEX): Likewise. ++ (UNSPEC_DSCLI): Likewise. ++ (UNSPEC_DSCRI): Likewise. ++ (D64_D128): Likewise. ++ (dfp_suffix): Likewise. ++ (dfp_ddedpd_<mode>): Likewise. ++ (dfp_denbcd_<mode>): Likewise. ++ (dfp_dxex_<mode>): Likewise. ++ (dfp_diex_<mode>): Likewise. ++ (dfp_dscli_<mode>): Likewise. ++ (dfp_dscri_<mode>): Likewise. ++ ++ * config/rs6000/rs6000.md (UNSPEC_ADDG6S): Add support for new BCD ++ builtin functions. ++ (UNSPEC_CDTBCD): Likewise. ++ (UNSPEC_CBCDTD): Likewise. ++ (UNSPEC_DIVE): Add support for new extended divide builtin ++ functions. ++ (UNSPEC_DIVEO): Likewise. ++ (UNSPEC_DIVEU): Likewise. ++ (UNSPEC_DIVEUO): Likewise. ++ (UNSPEC_UNPACK_128BIT): Add support for new builtin functions to ++ pack/unpack 128-bit types. ++ (UNSPEC_PACK_128BIT): Likewise. ++ (idiv_ldiv): New mode attribute to set the 32/64-bit divide type. ++ (udiv<mode>3): Use idiv_ldiv mode attribute. ++ (div<mode>3): Likewise. ++ (addg6s): Add new BCD builtin functions. ++ (cdtbcd): Likewise. ++ (cbcdtd): Likewise. ++ (UNSPEC_DIV_EXTEND): Add support for new extended divide ++ instructions. ++ (div_extend): Likewise. ++ (div<div_extend>_<mode>"): Likewise. ++ (FP128_64): Add support for new builtin functions to pack/unpack ++ 128-bit types. ++ (unpack<mode>): Likewise. ++ (unpacktf_0): Likewise. ++ (unpacktf_1): Likewise. ++ (unpack<mode>_dm): Likewise. ++ (unpack<mode>_nodm): Likewise. ++ (pack<mode>): Likewise. ++ (unpackv1ti): Likewise. ++ (packv1ti): Likewise. ++ ++2014-04-29 Pat Haugen <pthaugen@us.ibm.com> ++ ++ Backport from mainline ++ 2014-04-17 Pat Haugen <pthaugen@us.ibm.com> ++ ++ * config/rs6000/rs6000.md (addti3, subti3): New. ++ ++2014-04-28 Pat Haugen <pthaugen@us.ibm.com> ++ ++ Backport from mainline ++ 2014-04-28 Pat Haugen <pthaugen@us.ibm.com> ++ ++ * config/rs6000/sync.md (AINT mode_iterator): Move definition. ++ (loadsync_<mode>): Change mode. ++ (load_quadpti, store_quadpti): New. ++ (atomic_load<mode>, atomic_store<mode>): Add support for TI mode. ++ * config/rs6000/rs6000.md (unspec enum): Add UNSPEC_LSQ. ++ ++2014-04-28 Eric Botcazou <ebotcazou@adacore.com> ++ ++ * configure.ac: Tweak GAS check for LEON instructions on SPARC. ++ * configure: Regenerate. ++ * config/sparc/sparc.opt (muser-mode): New option. ++ * config/sparc/sync.md (atomic_compare_and_swap<mode>_1): Do not enable ++ for LEON3. ++ (atomic_compare_and_swap_leon3_1): New instruction for LEON3. ++ * doc/invoke.texi (SPARC options): Document -muser-mode. ++ ++2014-04-25 Eric Botcazou <ebotcazou@adacore.com> ++ ++ PR target/60941 ++ * config/sparc/sparc.md (ashlsi3_extend): Delete. ++ +2014-04-22 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from main line: @@ -14961,7 +15291,7 @@ Index: gcc/ChangeLog 2013-10-16 Release Manager * GCC 4.8.2 released. -@@ -639,7 +5708,7 @@ +@@ -639,7 +5970,7 @@ 2013-07-31 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Backport from mainline @@ -15417,6 +15747,99 @@ Index: gcc/testsuite/gcc.target/powerpc/ppc-target-2.c /* fabs/fnabs/fsel */ double normal1 (double a, double b) { return __builtin_copysign (a, b); } +Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,88 @@ ++/* { dg-do compile { target { powerpc*-*-linux* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-mcpu=power7 -O2" } */ ++/* { dg-final { scan-assembler-times "ddedpd " 4 } } */ ++/* { dg-final { scan-assembler-times "denbcd " 2 } } */ ++/* { dg-final { scan-assembler-times "dxex " 1 } } */ ++/* { dg-final { scan-assembler-times "diex " 1 } } */ ++/* { dg-final { scan-assembler-times "dscli " 2 } } */ ++/* { dg-final { scan-assembler-times "dscri " 2 } } */ ++/* { dg-final { scan-assembler-not "bl __builtin" } } */ ++/* { dg-final { scan-assembler-not "dctqpq" } } */ ++/* { dg-final { scan-assembler-not "drdpq" } } */ ++/* { dg-final { scan-assembler-not "stfd" } } */ ++/* { dg-final { scan-assembler-not "lfd" } } */ ++ ++_Decimal64 ++do_dedpd_0 (_Decimal64 a) ++{ ++ return __builtin_ddedpd (0, a); ++} ++ ++_Decimal64 ++do_dedpd_1 (_Decimal64 a) ++{ ++ return __builtin_ddedpd (1, a); ++} ++ ++_Decimal64 ++do_dedpd_2 (_Decimal64 a) ++{ ++ return __builtin_ddedpd (2, a); ++} ++ ++_Decimal64 ++do_dedpd_3 (_Decimal64 a) ++{ ++ return __builtin_ddedpd (3, a); ++} ++ ++_Decimal64 ++do_enbcd_0 (_Decimal64 a) ++{ ++ return __builtin_denbcd (0, a); ++} ++ ++_Decimal64 ++do_enbcd_1 (_Decimal64 a) ++{ ++ return __builtin_denbcd (1, a); ++} ++ ++_Decimal64 ++do_xex (_Decimal64 a) ++{ ++ return __builtin_dxex (a); ++} ++ ++_Decimal64 ++do_iex (_Decimal64 a, _Decimal64 b) ++{ ++ return __builtin_diex (a, b); ++} ++ ++_Decimal64 ++do_scli_1 (_Decimal64 a) ++{ ++ return __builtin_dscli (a, 1); ++} ++ ++_Decimal64 ++do_scli_10 (_Decimal64 a) ++{ ++ return __builtin_dscli (a, 10); ++} ++ ++_Decimal64 ++do_scri_1 (_Decimal64 a) ++{ ++ return __builtin_dscri (a, 1); ++} ++ ++_Decimal64 ++do_scri_10 (_Decimal64 a) ++{ ++ return __builtin_dscri (a, 10); ++} Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c (.../tags/gcc_4_8_2_release) @@ -15957,6 +16380,99 @@ Index: gcc/testsuite/gcc.target/powerpc/pr59054.c + +/* { dg-final { scan-assembler-not "xxlor" } } */ +/* { dg-final { scan-assembler-not "stfd" } } */ +Index: gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,88 @@ ++/* { dg-do compile { target { powerpc*-*-linux* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-mcpu=power7 -O2" } */ ++/* { dg-final { scan-assembler-times "ddedpdq " 4 } } */ ++/* { dg-final { scan-assembler-times "denbcdq " 2 } } */ ++/* { dg-final { scan-assembler-times "dxexq " 1 } } */ ++/* { dg-final { scan-assembler-times "diexq " 1 } } */ ++/* { dg-final { scan-assembler-times "dscliq " 2 } } */ ++/* { dg-final { scan-assembler-times "dscriq " 2 } } */ ++/* { dg-final { scan-assembler-not "bl __builtin" } } */ ++/* { dg-final { scan-assembler-not "dctqpq" } } */ ++/* { dg-final { scan-assembler-not "drdpq" } } */ ++/* { dg-final { scan-assembler-not "stfd" } } */ ++/* { dg-final { scan-assembler-not "lfd" } } */ ++ ++_Decimal128 ++do_dedpdq_0 (_Decimal128 a) ++{ ++ return __builtin_ddedpdq (0, a); ++} ++ ++_Decimal128 ++do_dedpdq_1 (_Decimal128 a) ++{ ++ return __builtin_ddedpdq (1, a); ++} ++ ++_Decimal128 ++do_dedpdq_2 (_Decimal128 a) ++{ ++ return __builtin_ddedpdq (2, a); ++} ++ ++_Decimal128 ++do_dedpdq_3 (_Decimal128 a) ++{ ++ return __builtin_ddedpdq (3, a); ++} ++ ++_Decimal128 ++do_enbcdq_0 (_Decimal128 a) ++{ ++ return __builtin_denbcdq (0, a); ++} ++ ++_Decimal128 ++do_enbcdq_1 (_Decimal128 a) ++{ ++ return __builtin_denbcdq (1, a); ++} ++ ++_Decimal128 ++do_xexq (_Decimal128 a) ++{ ++ return __builtin_dxexq (a); ++} ++ ++_Decimal128 ++do_iexq (_Decimal128 a, _Decimal128 b) ++{ ++ return __builtin_diexq (a, b); ++} ++ ++_Decimal128 ++do_scliq_1 (_Decimal128 a) ++{ ++ return __builtin_dscliq (a, 1); ++} ++ ++_Decimal128 ++do_scliq_10 (_Decimal128 a) ++{ ++ return __builtin_dscliq (a, 10); ++} ++ ++_Decimal128 ++do_scriq_1 (_Decimal128 a) ++{ ++ return __builtin_dscriq (a, 1); ++} ++ ++_Decimal128 ++do_scriq_10 (_Decimal128 a) ++{ ++ return __builtin_dscriq (a, 10); ++} Index: gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c (.../tags/gcc_4_8_2_release) @@ -16233,6 +16749,38 @@ Index: gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c + return vec_extract (vec_vbpermq (a, b), OFFSET); +} + +Index: gcc/testsuite/gcc.target/powerpc/bcd-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-1.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-1.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,27 @@ ++/* { dg-do compile { target { powerpc*-*-linux* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-mcpu=power7 -O2" } */ ++/* { dg-final { scan-assembler-times "cdtbcd " 1 } } */ ++/* { dg-final { scan-assembler-times "cbcdtd " 1 } } */ ++/* { dg-final { scan-assembler-times "addg6s " 1 } } */ ++/* { dg-final { scan-assembler-not "bl __builtin" } } */ ++ ++unsigned int ++to_bcd (unsigned int a) ++{ ++ return __builtin_cdtbcd (a); ++} ++ ++unsigned int ++from_bcd (unsigned int a) ++{ ++ return __builtin_cbcdtd (a); ++} ++ ++unsigned int ++bcd_arith (unsigned int a, unsigned int b) ++{ ++ return __builtin_addg6s (a, b); ++} Index: gcc/testsuite/gcc.target/powerpc/pr60735.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/pr60735.c (.../tags/gcc_4_8_2_release) @@ -16249,6 +16797,45 @@ Index: gcc/testsuite/gcc.target/powerpc/pr60735.c +{ + *p = *q; +} +Index: gcc/testsuite/gcc.target/powerpc/extend-divide-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,34 @@ ++/* { dg-do compile { target { powerpc*-*-linux* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-mcpu=power7 -O2" } */ ++/* { dg-final { scan-assembler-times "divwe " 1 } } */ ++/* { dg-final { scan-assembler-times "divweo " 1 } } */ ++/* { dg-final { scan-assembler-times "divweu " 1 } } */ ++/* { dg-final { scan-assembler-times "divweuo " 1 } } */ ++/* { dg-final { scan-assembler-not "bl __builtin" } } */ ++ ++int ++div_we (int a, int b) ++{ ++ return __builtin_divwe (a, b); ++} ++ ++int ++div_weo (int a, int b) ++{ ++ return __builtin_divweo (a, b); ++} ++ ++unsigned int ++div_weu (unsigned int a, unsigned int b) ++{ ++ return __builtin_divweu (a, b); ++} ++ ++unsigned int ++div_weuo (unsigned int a, unsigned int b) ++{ ++ return __builtin_divweuo (a, b); ++} Index: gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c (.../tags/gcc_4_8_2_release) @@ -17026,6 +17613,94 @@ Index: gcc/testsuite/gcc.target/powerpc/sd-vsx.c +{ + a += (_Decimal32) 1.0; +} +Index: gcc/testsuite/gcc.target/powerpc/bcd-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-2.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-2.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,44 @@ ++/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++/* { dg-final { scan-assembler-times "bcdadd\[.\] " 2 } } */ ++/* { dg-final { scan-assembler-times "bcdsub\[.\] " 2 } } */ ++/* { dg-final { scan-assembler-not "bl __builtin" } } */ ++/* { dg-final { scan-assembler-not "mtvsr" } } */ ++/* { dg-final { scan-assembler-not "mfvsr" } } */ ++/* { dg-final { scan-assembler-not "lvx" } } */ ++/* { dg-final { scan-assembler-not "lxvw4x" } } */ ++/* { dg-final { scan-assembler-not "lxvd2x" } } */ ++/* { dg-final { scan-assembler-not "stvx" } } */ ++/* { dg-final { scan-assembler-not "stxvw4x" } } */ ++/* { dg-final { scan-assembler-not "stxvd2x" } } */ ++ ++typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t; ++typedef __int128_t scalar_128_t; ++typedef unsigned long long scalar_64_t; ++ ++vector_128_t ++do_add_0 (vector_128_t a, vector_128_t b) ++{ ++ return __builtin_bcdadd (a, b, 0); ++} ++ ++vector_128_t ++do_add_1 (vector_128_t a, vector_128_t b) ++{ ++ return __builtin_bcdadd (a, b, 1); ++} ++ ++vector_128_t ++do_sub_0 (vector_128_t a, vector_128_t b) ++{ ++ return __builtin_bcdsub (a, b, 0); ++} ++ ++vector_128_t ++do_sub_1 (vector_128_t a, vector_128_t b) ++{ ++ return __builtin_bcdsub (a, b, 1); ++} +Index: gcc/testsuite/gcc.target/powerpc/extend-divide-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,34 @@ ++/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_vsx_ok } */ ++/* { dg-options "-mcpu=power7 -O2" } */ ++/* { dg-final { scan-assembler-times "divde " 1 } } */ ++/* { dg-final { scan-assembler-times "divdeo " 1 } } */ ++/* { dg-final { scan-assembler-times "divdeu " 1 } } */ ++/* { dg-final { scan-assembler-times "divdeuo " 1 } } */ ++/* { dg-final { scan-assembler-not "bl __builtin" } } */ ++ ++long ++div_de (long a, long b) ++{ ++ return __builtin_divde (a, b); ++} ++ ++long ++div_deo (long a, long b) ++{ ++ return __builtin_divdeo (a, b); ++} ++ ++unsigned long ++div_deu (unsigned long a, unsigned long b) ++{ ++ return __builtin_divdeu (a, b); ++} ++ ++unsigned long ++div_deuo (unsigned long a, unsigned long b) ++{ ++ return __builtin_divdeuo (a, b); ++} Index: gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c (.../tags/gcc_4_8_2_release) @@ -17749,6 +18424,102 @@ Index: gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c +/* { dg-final { scan-assembler "lxsdx" } } */ +/* { dg-final { scan-assembler "stxsspx" } } */ +/* { dg-final { scan-assembler "stxsdx" } } */ +Index: gcc/testsuite/gcc.target/powerpc/pack01.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/pack01.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/pack01.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,91 @@ ++/* { dg-do run { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target p8vector_hw } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++ ++#include <stddef.h> ++#include <stdlib.h> ++#include <altivec.h> ++ ++#ifdef DEBUG ++#include <stdio.h> ++#endif ++ ++typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t; ++typedef __int128_t scalar_128_t; ++typedef unsigned long long scalar_64_t; ++ ++volatile scalar_64_t one = 1; ++volatile scalar_64_t two = 2; ++ ++int ++main (void) ++{ ++ scalar_128_t a = (((scalar_128_t)one) << 64) | ((scalar_128_t)two); ++ vector_128_t v1 = (vector_128_t) { a }; ++ vector_128_t v2 = __builtin_pack_vector_int128 (one, two); ++ scalar_64_t x0 = __builtin_unpack_vector_int128 (v1, 0); ++ scalar_64_t x1 = __builtin_unpack_vector_int128 (v1, 1); ++ vector_128_t v3 = __builtin_pack_vector_int128 (x0, x1); ++ ++ size_t i; ++ union { ++ scalar_128_t i128; ++ vector_128_t v128; ++ scalar_64_t u64; ++ unsigned char uc[sizeof (scalar_128_t)]; ++ char c[sizeof (scalar_128_t)]; ++ } u, u2; ++ ++#ifdef DEBUG ++ { ++ printf ("a = 0x"); ++ u.i128 = a; ++ for (i = 0; i < sizeof (scalar_128_t); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf ("\nv1 = 0x"); ++ u.v128 = v1; ++ for (i = 0; i < sizeof (scalar_128_t); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf ("\nv2 = 0x"); ++ u.v128 = v2; ++ for (i = 0; i < sizeof (scalar_128_t); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf ("\nv3 = 0x"); ++ u.v128 = v3; ++ for (i = 0; i < sizeof (scalar_128_t); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf ("\nx0 = 0x"); ++ u.u64 = x0; ++ for (i = 0; i < sizeof (scalar_64_t); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf ("\nx1 = 0x"); ++ u.u64 = x1; ++ for (i = 0; i < sizeof (scalar_64_t); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf ("\n"); ++ } ++#endif ++ ++ u2.i128 = a; ++ u.v128 = v1; ++ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0) ++ abort (); ++ ++ u.v128 = v2; ++ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0) ++ abort (); ++ ++ u.v128 = v3; ++ if (memcmp (u.c, u2.c, sizeof (scalar_128_t)) != 0) ++ abort (); ++ ++ return 0; ++} Index: gcc/testsuite/gcc.target/powerpc/bool3-p8.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/bool3-p8.c (.../tags/gcc_4_8_2_release) @@ -18223,6 +18994,114 @@ Index: gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c + +/* { dg-final { scan-assembler-times "vclzw" 2 } } */ +/* { dg-final { scan-assembler-times "vpopcntw" 2 } } */ +Index: gcc/testsuite/gcc.target/powerpc/bcd-3.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/bcd-3.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/bcd-3.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,103 @@ ++/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++/* { dg-final { scan-assembler-times "bcdadd\[.\] " 4 } } */ ++/* { dg-final { scan-assembler-times "bcdsub\[.\] " 4 } } */ ++/* { dg-final { scan-assembler-not "bl __builtin" } } */ ++/* { dg-final { scan-assembler-not "mtvsr" } } */ ++/* { dg-final { scan-assembler-not "mfvsr" } } */ ++/* { dg-final { scan-assembler-not "lvx" } } */ ++/* { dg-final { scan-assembler-not "lxvw4x" } } */ ++/* { dg-final { scan-assembler-not "lxvd2x" } } */ ++/* { dg-final { scan-assembler-not "stvx" } } */ ++/* { dg-final { scan-assembler-not "stxvw4x" } } */ ++/* { dg-final { scan-assembler-not "stxvd2x" } } */ ++ ++typedef __int128_t __attribute__((__vector_size__(16))) vector_128_t; ++typedef __int128_t scalar_128_t; ++typedef unsigned long long scalar_64_t; ++ ++/* Test whether the peephole works to allow folding a bcdadd, with a ++ bcdadd_<test> into a single instruction. */ ++ ++vector_128_t ++do_add_lt (vector_128_t a, vector_128_t b, int *p) ++{ ++ vector_128_t ret = __builtin_bcdadd (a, b, 0); ++ if (__builtin_bcdadd_lt (a, b, 0)) ++ *p = 1; ++ ++ return ret; ++} ++ ++vector_128_t ++do_add_eq (vector_128_t a, vector_128_t b, int *p) ++{ ++ vector_128_t ret = __builtin_bcdadd (a, b, 0); ++ if (__builtin_bcdadd_eq (a, b, 0)) ++ *p = 1; ++ ++ return ret; ++} ++ ++vector_128_t ++do_add_gt (vector_128_t a, vector_128_t b, int *p) ++{ ++ vector_128_t ret = __builtin_bcdadd (a, b, 0); ++ if (__builtin_bcdadd_gt (a, b, 0)) ++ *p = 1; ++ ++ return ret; ++} ++ ++vector_128_t ++do_add_ov (vector_128_t a, vector_128_t b, int *p) ++{ ++ vector_128_t ret = __builtin_bcdadd (a, b, 0); ++ if (__builtin_bcdadd_ov (a, b, 0)) ++ *p = 1; ++ ++ return ret; ++} ++ ++vector_128_t ++do_sub_lt (vector_128_t a, vector_128_t b, int *p) ++{ ++ vector_128_t ret = __builtin_bcdsub (a, b, 0); ++ if (__builtin_bcdsub_lt (a, b, 0)) ++ *p = 1; ++ ++ return ret; ++} ++ ++vector_128_t ++do_sub_eq (vector_128_t a, vector_128_t b, int *p) ++{ ++ vector_128_t ret = __builtin_bcdsub (a, b, 0); ++ if (__builtin_bcdsub_eq (a, b, 0)) ++ *p = 1; ++ ++ return ret; ++} ++ ++vector_128_t ++do_sub_gt (vector_128_t a, vector_128_t b, int *p) ++{ ++ vector_128_t ret = __builtin_bcdsub (a, b, 0); ++ if (__builtin_bcdsub_gt (a, b, 0)) ++ *p = 1; ++ ++ return ret; ++} ++ ++vector_128_t ++do_sub_ov (vector_128_t a, vector_128_t b, int *p) ++{ ++ vector_128_t ret = __builtin_bcdsub (a, b, 0); ++ if (__builtin_bcdsub_ov (a, b, 0)) ++ *p = 1; ++ ++ return ret; ++} Index: gcc/testsuite/gcc.target/powerpc/pr57949-1.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/pr57949-1.c (.../tags/gcc_4_8_2_release) @@ -18540,6 +19419,106 @@ Index: gcc/testsuite/gcc.target/powerpc/no-r11-3.c /* { dg-options "-O2 -mno-pointers-to-nested-functions" } */ extern void ext_call (int (func) (void)); +Index: gcc/testsuite/gcc.target/powerpc/pack02.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/pack02.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/pack02.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,95 @@ ++/* { dg-do run { target { powerpc*-*-linux* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_fprs } */ ++/* { dg-options "-O2 -mhard-float" } */ ++ ++#include <stddef.h> ++#include <stdlib.h> ++#include <math.h> ++ ++#ifdef DEBUG ++#include <stdio.h> ++#endif ++ ++int ++main (void) ++{ ++ double high = pow (2.0, 60); ++ double low = 2.0; ++ long double a = ((long double)high) + ((long double)low); ++ double x0 = __builtin_unpack_longdouble (a, 0); ++ double x1 = __builtin_unpack_longdouble (a, 1); ++ long double b = __builtin_pack_longdouble (x0, x1); ++ ++#ifdef DEBUG ++ { ++ size_t i; ++ union { ++ long double ld; ++ double d; ++ unsigned char uc[sizeof (long double)]; ++ char c[sizeof (long double)]; ++ } u; ++ ++ printf ("a = 0x"); ++ u.ld = a; ++ for (i = 0; i < sizeof (long double); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf (", %Lg\n", a); ++ ++ printf ("b = 0x"); ++ u.ld = b; ++ for (i = 0; i < sizeof (long double); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf (", %Lg\n", b); ++ ++ printf ("hi = 0x"); ++ u.d = high; ++ for (i = 0; i < sizeof (double); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", high); ++ ++ printf ("lo = 0x"); ++ u.d = low; ++ for (i = 0; i < sizeof (double); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", low); ++ ++ printf ("x0 = 0x"); ++ u.d = x0; ++ for (i = 0; i < sizeof (double); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x0); ++ ++ printf ("x1 = 0x"); ++ u.d = x1; ++ for (i = 0; i < sizeof (double); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf (",%*s %g\n", (int)(2 * (sizeof (long double) - sizeof (double))), "", x1); ++ } ++#endif ++ ++ if (high != x0) ++ abort (); ++ ++ if (low != x1) ++ abort (); ++ ++ if (a != b) ++ abort (); ++ ++ if (x0 != high) ++ abort (); ++ ++ if (x1 != low) ++ abort (); ++ ++ return 0; ++} Index: gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c (.../tags/gcc_4_8_2_release) @@ -19023,6 +20002,99 @@ Index: gcc/testsuite/gcc.target/powerpc/recip-5.c #include <altivec.h> +Index: gcc/testsuite/gcc.target/powerpc/pack03.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/pack03.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/pack03.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,88 @@ ++/* { dg-do run { target { powerpc*-*-linux* } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-skip-if "" { powerpc*-*-*spe* } { "*" } { "" } } */ ++/* { dg-require-effective-target dfprt } */ ++/* { dg-options "-O2 -mhard-dfp" } */ ++ ++#include <stddef.h> ++#include <stdlib.h> ++#include <math.h> ++ ++#ifdef DEBUG ++#include <stdio.h> ++#endif ++ ++int ++main (void) ++{ ++ _Decimal128 one = (_Decimal128)1.0; ++ _Decimal128 two = (_Decimal128)2.0; ++ _Decimal128 ten = (_Decimal128)10.0; ++ _Decimal128 a = one; ++ _Decimal128 b; ++ _Decimal128 c; ++ unsigned long long x0; ++ unsigned long long x1; ++ size_t i; ++ ++ for (i = 0; i < 25; i++) ++ a *= ten; ++ ++ a += two; ++ ++ x0 = __builtin_unpack_dec128 (a, 0); ++ x1 = __builtin_unpack_dec128 (a, 1); ++ b = __builtin_pack_dec128 (x0, x1); ++ c = __builtin_dscliq (one, 25) + two; ++ ++#ifdef DEBUG ++ { ++ union { ++ _Decimal128 d; ++ unsigned long long ull; ++ unsigned char uc[sizeof (_Decimal128)]; ++ } u; ++ ++ printf ("a = 0x"); ++ u.d = a; ++ for (i = 0; i < sizeof (_Decimal128); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf (", %Lg\n", (long double)a); ++ ++ printf ("b = 0x"); ++ u.d = b; ++ for (i = 0; i < sizeof (_Decimal128); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf (", %Lg\n", (long double)b); ++ ++ printf ("c = 0x"); ++ u.d = c; ++ for (i = 0; i < sizeof (_Decimal128); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf (", %Lg\n", (long double)c); ++ ++ printf ("x0 = 0x"); ++ u.ull = x0; ++ for (i = 0; i < sizeof (unsigned long long); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf ("\nx1 = 0x"); ++ u.ull = x1; ++ for (i = 0; i < sizeof (unsigned long long); i++) ++ printf ("%.2x", u.uc[i]); ++ ++ printf ("\n"); ++ } ++#endif ++ ++ if (a != b) ++ abort (); ++ ++ if (a != c) ++ abort (); ++ ++ return 0; ++} Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c (.../tags/gcc_4_8_2_release) @@ -19542,8 +20614,58 @@ Index: gcc/testsuite/gcc.target/powerpc/quad-atomic.c + return 0; +} + +Index: gcc/testsuite/gcc.target/powerpc/ti_math1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ti_math1.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ti_math1.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,20 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-options "-O2" } */ ++/* { dg-final { scan-assembler-times "addc" 1 } } */ ++/* { dg-final { scan-assembler-times "adde" 1 } } */ ++/* { dg-final { scan-assembler-times "subfc" 1 } } */ ++/* { dg-final { scan-assembler-times "subfe" 1 } } */ ++/* { dg-final { scan-assembler-not "subf " } } */ ++ ++__int128 ++add_128 (__int128 *ptr, __int128 val) ++{ ++ return (*ptr + val); ++} ++ ++__int128 ++sub_128 (__int128 *ptr, __int128 val) ++{ ++ return (*ptr - val); ++} ++ Index: gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c =================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,22 @@ ++/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ ++/* { dg-require-effective-target powerpc_p8vector_ok } */ ++/* { dg-options "-mcpu=power8 -O2" } */ ++/* { dg-final { scan-assembler-times "lq" 1 } } */ ++/* { dg-final { scan-assembler-times "stq" 1 } } */ ++/* { dg-final { scan-assembler-not "bl __atomic" } } */ ++/* { dg-final { scan-assembler-not "lqarx" } } */ ++/* { dg-final { scan-assembler-not "stqcx" } } */ ++ ++__int128 ++atomic_load_128_relaxed (__int128 *ptr) ++{ ++ return __atomic_load_n (ptr, __ATOMIC_RELAXED); ++} ++ ++void ++atomic_store_128_relaxed (__int128 *ptr, __int128 val) ++{ ++ __atomic_store_n (ptr, val, __ATOMIC_RELAXED); ++} ++ Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c =================================================================== --- a/src/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (.../tags/gcc_4_8_2_release) @@ -19929,6 +21051,84 @@ Index: gcc/testsuite/gcc.target/powerpc/bool2-p7.c +#endif + +#include "bool2.h" +Index: gcc/testsuite/gcc.target/powerpc/ti_math2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.target/powerpc/ti_math2.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.target/powerpc/ti_math2.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,73 @@ ++/* { dg-do run { target { powerpc*-*-* && lp64 } } } */ ++/* { dg-options "-O2 -fno-inline" } */ ++ ++union U { ++ __int128 i128; ++ struct { ++ long l1; ++ long l2; ++ } s; ++}; ++ ++union U u1,u2; ++ ++__int128 ++create_128 (long most_sig, long least_sig) ++{ ++ union U u; ++ ++#if __LITTLE_ENDIAN__ ++ u.s.l1 = least_sig; ++ u.s.l2 = most_sig; ++#else ++ u.s.l1 = most_sig; ++ u.s.l2 = least_sig; ++#endif ++ return u.i128; ++} ++ ++long most_sig (union U * u) ++{ ++#if __LITTLE_ENDIAN__ ++ return (*u).s.l2; ++#else ++ return (*u).s.l1; ++#endif ++} ++ ++long least_sig (union U * u) ++{ ++#if __LITTLE_ENDIAN__ ++ return (*u).s.l1; ++#else ++ return (*u).s.l2; ++#endif ++} ++ ++__int128 ++add_128 (__int128 *ptr, __int128 val) ++{ ++ return (*ptr + val); ++} ++ ++__int128 ++sub_128 (__int128 *ptr, __int128 val) ++{ ++ return (*ptr - val); ++} ++ ++int ++main (void) ++{ ++ /* Do a simple add/sub to make sure carry is happening between the dwords ++ and that dwords are in correct endian order. */ ++ u1.i128 = create_128 (1, -1); ++ u2.i128 = add_128 (&u1.i128, 1); ++ if ((most_sig (&u2) != 2) || (least_sig (&u2) != 0)) ++ __builtin_abort (); ++ u2.i128 = sub_128 (&u2.i128, 1); ++ if ((most_sig (&u2) != 1) || (least_sig (&u2) != -1)) ++ __builtin_abort (); ++ return 0; ++} ++ Index: gcc/testsuite/gcc.target/microblaze/others/mem_reload.c =================================================================== --- a/src/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c (.../tags/gcc_4_8_2_release) @@ -25279,6 +26479,25 @@ Index: gcc/testsuite/gfortran.dg/pr52370.f90 + real :: a + call foo(a) +end program prg52370 +Index: gcc/testsuite/gfortran.dg/graphite/pr59817.f +=================================================================== +--- a/src/gcc/testsuite/gfortran.dg/graphite/pr59817.f (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gfortran.dg/graphite/pr59817.f (.../branches/gcc-4_8-branch) +@@ -0,0 +1,14 @@ ++! { dg-do compile } ++! { dg-options "-O2 -floop-interchange" } ++ SUBROUTINE PREPD(ICAST,ICAS,ICASX,ICAS1,ICAS2,NDET,NM,III,IMP, ++ * CASMIN) ++ LOGICAL CASMIN ++ DIMENSION ICAST(NDET,NM),IMP(NM) ++ IF(CASMIN) THEN ++ DO K=1,NDET ++ DO L=1,NM ++ IF(L.EQ.K-1) ICAST(K,L) = 1 ++ END DO ++ END DO ++ END IF ++ END SUBROUTINE Index: gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90 =================================================================== --- a/src/gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90 (.../tags/gcc_4_8_2_release) @@ -26145,6 +27364,34 @@ Index: gcc/testsuite/gcc.c-torture/execute/pr60062.c + bar ("hello"); + return 0; +} +Index: gcc/testsuite/gcc.c-torture/execute/20140425-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.c-torture/execute/20140425-1.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.c-torture/execute/20140425-1.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,23 @@ ++/* PR target/60941 */ ++/* Reported by Martin Husemann <martin@netbsd.org> */ ++ ++extern void abort (void); ++ ++static void __attribute__((noinline)) ++set (unsigned long *l) ++{ ++ *l = 31; ++} ++ ++int main (void) ++{ ++ unsigned long l; ++ int i; ++ ++ set (&l); ++ i = (int) l; ++ l = (unsigned long)(2U << i); ++ if (l != 0) ++ abort (); ++ return 0; ++} Index: gcc/testsuite/gcc.c-torture/execute/pr59014-2.c =================================================================== --- a/src/gcc/testsuite/gcc.c-torture/execute/pr59014-2.c (.../tags/gcc_4_8_2_release) @@ -26299,6 +27546,49 @@ Index: gcc/testsuite/gcc.c-torture/execute/pr59014.c + __builtin_abort (); + return 0; +} +Index: gcc/testsuite/gcc.c-torture/execute/pr60960.c +=================================================================== +--- a/src/gcc/testsuite/gcc.c-torture/execute/pr60960.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr60960.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,38 @@ ++/* PR tree-optimization/60960 */ ++ ++typedef unsigned char v4qi __attribute__ ((vector_size (4))); ++ ++__attribute__((noinline, noclone)) v4qi ++f1 (v4qi v) ++{ ++ return v / 2; ++} ++ ++__attribute__((noinline, noclone)) v4qi ++f2 (v4qi v) ++{ ++ return v / (v4qi) { 2, 2, 2, 2 }; ++} ++ ++__attribute__((noinline, noclone)) v4qi ++f3 (v4qi x, v4qi y) ++{ ++ return x / y; ++} ++ ++int ++main () ++{ ++ v4qi x = { 5, 5, 5, 5 }; ++ v4qi y = { 2, 2, 2, 2 }; ++ v4qi z = f1 (x); ++ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0) ++ __builtin_abort (); ++ z = f2 (x); ++ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0) ++ __builtin_abort (); ++ z = f3 (x, y); ++ if (__builtin_memcmp (&y, &z, sizeof (y)) != 0) ++ __builtin_abort (); ++ return 0; ++} Index: gcc/testsuite/gcc.c-torture/execute/pr60072.c =================================================================== --- a/src/gcc/testsuite/gcc.c-torture/execute/pr60072.c (.../tags/gcc_4_8_2_release) @@ -26423,6 +27713,29 @@ Index: gcc/testsuite/gcc.c-torture/compile/pr58997.c + ; + } +} +Index: gcc/testsuite/gcc.c-torture/compile/pr60502.c +=================================================================== +--- a/src/gcc/testsuite/gcc.c-torture/compile/pr60502.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr60502.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,18 @@ ++/* PR tree-optimization/60502 */ ++ ++typedef signed char v16i8 __attribute__ ((vector_size (16))); ++typedef unsigned char v16u8 __attribute__ ((vector_size (16))); ++ ++void ++foo (v16i8 *x) ++{ ++ v16i8 m1 = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 }; ++ *x |= *x ^ m1; ++} ++ ++void ++bar (v16u8 *x) ++{ ++ v16u8 m1 = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 }; ++ *x |= *x ^ m1; ++} Index: gcc/testsuite/gcc.c-torture/compile/pr58970-2.c =================================================================== --- a/src/gcc/testsuite/gcc.c-torture/compile/pr58970-2.c (.../tags/gcc_4_8_2_release) @@ -29854,6 +31167,26 @@ Index: gcc/testsuite/gcc.dg/20050922-2.c #if __INT_MAX__ == 2147483647 typedef unsigned int uint32_t; +Index: gcc/testsuite/gcc.dg/graphite/pr59817-2.c +=================================================================== +--- a/src/gcc/testsuite/gcc.dg/graphite/pr59817-2.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.dg/graphite/pr59817-2.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,15 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -floop-interchange" } */ ++ ++void ++xl(void) ++{ ++ static int j3; ++ for (j3 = 0; j3 < 1; ++j3) { ++ static int f2; ++ static int w7; ++ short int b5; ++ int ok; ++ f2 = (b5 += ok) ? (w7 = 0): (w7 ? 0 : (f2 = ok)); ++ } ++} Index: gcc/testsuite/gcc.dg/graphite/pr60740.c =================================================================== --- a/src/gcc/testsuite/gcc.dg/graphite/pr60740.c (.../tags/gcc_4_8_2_release) @@ -29875,6 +31208,27 @@ Index: gcc/testsuite/gcc.dg/graphite/pr60740.c + *c4b = (db6 == l30) && (*a22)--; +} + +Index: gcc/testsuite/gcc.dg/graphite/pr59817-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.dg/graphite/pr59817-1.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.dg/graphite/pr59817-1.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2 -floop-interchange" } */ ++ ++int kd; ++ ++void ++n2(void) ++{ ++ static int so; ++ static short int i5; ++ int wj; ++ int *il; ++ int *nk = &so; ++ for (wj = 0; wj < 2; ++wj) ++ *nk = ((i5 += *il) || kd ); ++} Index: gcc/testsuite/gcc.dg/pr59860.c =================================================================== --- a/src/gcc/testsuite/gcc.dg/pr59860.c (.../tags/gcc_4_8_2_release) @@ -30448,6 +31802,33 @@ Index: gcc/testsuite/gcc.dg/torture/pr58830.c + abort (); + return 0; +} +Index: gcc/testsuite/gcc.dg/torture/pr60930.c +=================================================================== +--- a/src/gcc/testsuite/gcc.dg/torture/pr60930.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.dg/torture/pr60930.c (.../branches/gcc-4_8-branch) +@@ -0,0 +1,22 @@ ++/* { dg-do run } */ ++ ++int x = 1; ++ ++__attribute__((noinline, noclone)) void ++foo (unsigned long long t) ++{ ++ asm volatile ("" : : "r" (&t)); ++ if (t == 1) ++ __builtin_abort (); ++} ++ ++int ++main () ++{ ++#if __SIZEOF_LONG_LONG__ >= 8 ++ unsigned long long t = 0xffffffffffffffffULL * (0xffffffffUL * x); ++ if (t != 0xffffffff00000001ULL) ++ foo (t);; ++#endif ++ return 0; ++} Index: gcc/testsuite/gcc.dg/torture/pr59715.c =================================================================== --- a/src/gcc/testsuite/gcc.dg/torture/pr59715.c (.../tags/gcc_4_8_2_release) @@ -30905,6 +32286,20 @@ Index: gcc/testsuite/gcc.dg/torture/pr59330.c + free(p); + return 0; +} +Index: gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c +=================================================================== +--- a/src/gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/20040517-1.c (.../branches/gcc-4_8-branch) +@@ -16,6 +16,7 @@ + /* We used to treat malloc functions like pure and const functions, but + malloc functions may clobber global memory. Only the function result + does not alias any other pointer. +- Hence, we must have a VDEF for a before and after the call to foo(). */ +-/* { dg-final { scan-tree-dump-times "VDEF" 2 "alias"} } */ ++ Hence, we must have a VDEF for a before and after the call to foo(). ++ And one after the call to abort(). */ ++/* { dg-final { scan-tree-dump-times "VDEF" 3 "alias"} } */ + /* { dg-final { cleanup-tree-dump "alias" } } */ Index: gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c =================================================================== --- a/src/gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c (.../tags/gcc_4_8_2_release) @@ -31259,7 +32654,86 @@ Index: gcc/testsuite/ChangeLog =================================================================== --- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_4_8_2_release) +++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,1717 @@ +@@ -1,3 +1,1796 @@ ++2014-05-05 Richard Biener <rguenther@suse.de> ++ ++ Backport from mainline ++ 2014-04-23 Richard Biener <rguenther@suse.de> ++ ++ PR middle-end/60895 ++ * g++.dg/torture/pr60895.C: New testcase. ++ ++ 2014-04-07 Richard Biener <rguenther@suse.de> ++ ++ PR middle-end/60750 ++ * g++.dg/torture/pr60750.C: New testcase. ++ * gcc.dg/tree-ssa/20040517-1.c: Adjust. ++ ++ 2014-04-14 Richard Biener <rguenther@suse.de> ++ ++ PR tree-optimization/59817 ++ PR tree-optimization/60453 ++ * gfortran.dg/graphite/pr59817.f: New testcase. ++ * gcc.dg/graphite/pr59817-1.c: Likewise. ++ * gcc.dg/graphite/pr59817-2.c: Likewise. ++ ++ 2014-04-17 Richard Biener <rguenther@suse.de> ++ ++ PR tree-optimization/60836 ++ * g++.dg/vect/pr60836.cc: New testcase. ++ ++2014-05-05 Jakub Jelinek <jakub@redhat.com> ++ ++ Backported from mainline ++ 2014-04-25 Jakub Jelinek <jakub@redhat.com> ++ ++ PR tree-optimization/60960 ++ * gcc.c-torture/execute/pr60960.c: New test. ++ ++2014-05-04 Peter Bergner <bergner@vnet.ibm.com> ++ ++ * gcc.target/powerpc/pack02.c (dg-options): Add -mhard-float. ++ (dg-require-effective-target): Change target to powerpc_fprs. ++ * gcc.target/powerpc/pack03.c (dg-options): Add -mhard-dfp. ++ (dg-require-effective-target): Change target to dfprt. ++ ++2014-05-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com> ++ ++ PR tree-optimization/60930 ++ * gcc.dg/torture/pr60930.c: New test. ++ ++2014-04-30 Michael Meissner <meissner@linux.vnet.ibm.com> ++ ++ Back port from mainline ++ 2014-04-24 Michael Meissner <meissner@linux.vnet.ibm.com> ++ ++ * gcc.target/powerpc/pack01.c: New test to test the new pack and ++ unpack builtin functionss for 128-bit types. ++ * gcc.target/powerpc/pack02.c: Likewise. ++ * gcc.target/powerpc/pack03.c: Likewise. ++ * gcc.target/powerpc/extend-divide-1.c: New test to test extended ++ divide builtin functionss. ++ * gcc.target/powerpc/extend-divide-2.c: Likewise. ++ * gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin ++ functions. ++ * gcc.target/powerpc/bcd-2.c: Likewise. ++ * gcc.target/powerpc/bcd-3.c: Likewise. ++ * gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP ++ builtin functionss. ++ * gcc.target/powerpc/dfp-builtin-2.c: Likewise. ++ ++2014-04-29 Pat Haugen <pthaugen@us.ibm.com> ++ ++ Backport from mainline ++ 2014-04-17 Pat Haugen <pthaugen@us.ibm.com> ++ ++ * gcc.target/powerpc/ti_math1.c: New. ++ * gcc.target/powerpc/ti_math2.c: New. ++ ++2014-04-25 Eric Botcazou <ebotcazou@adacore.com> ++ ++ * gcc.c-torture/execute/20140425-1.c: New test. ++ +2014-04-23 Michael Meissner <meissner@linux.vnet.ibm.com> + + Back port from main line: @@ -32977,7 +34451,7 @@ Index: gcc/testsuite/ChangeLog 2013-10-16 Release Manager * GCC 4.8.2 released. -@@ -39,9 +1753,9 @@ +@@ -39,9 +1832,9 @@ Backport from mainline 2013-06-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> @@ -32990,7 +34464,7 @@ Index: gcc/testsuite/ChangeLog 2013-10-04 Tobias Burnus <burnus@net-b.de> -@@ -307,8 +2021,8 @@ +@@ -307,8 +2100,8 @@ Backport from mainline 2013-08-12 Perez Read <netfirewall@gmail.com> @@ -33001,7 +34475,7 @@ Index: gcc/testsuite/ChangeLog 2013-08-11 Janus Weil <janus@gcc.gnu.org> -@@ -494,7 +2208,7 @@ +@@ -494,7 +2287,7 @@ 2013-06-19 Wei Mi <wmi@google.com> PR rtl-optimization/57518 @@ -33010,7 +34484,7 @@ Index: gcc/testsuite/ChangeLog 2013-06-11 Tobias Burnus <burnus@net-b.de> -@@ -623,8 +2337,8 @@ +@@ -623,8 +2416,8 @@ 2013-05-09 Martin Jambor <mjambor@suse.cz> @@ -33021,7 +34495,7 @@ Index: gcc/testsuite/ChangeLog 2013-05-08 Marc Glisse <marc.glisse@inria.fr> -@@ -701,7 +2415,7 @@ +@@ -701,7 +2494,7 @@ 2013-04-25 Marek Polacek <polacek@redhat.com> PR tree-optimization/57066 @@ -33030,7 +34504,7 @@ Index: gcc/testsuite/ChangeLog 2013-05-02 Jakub Jelinek <jakub@redhat.com> -@@ -727,8 +2441,8 @@ +@@ -727,8 +2520,8 @@ Backport from mainline 2013-04-24 Vladimir Makarov <vmakarov@redhat.com> @@ -33041,7 +34515,7 @@ Index: gcc/testsuite/ChangeLog 2013-05-02 Vladimir Makarov <vmakarov@redhat.com> -@@ -735,8 +2449,8 @@ +@@ -735,8 +2528,8 @@ Backport from mainline 2013-04-22 Vladimir Makarov <vmakarov@redhat.com> @@ -33052,7 +34526,7 @@ Index: gcc/testsuite/ChangeLog 2013-05-02 Vladimir Makarov <vmakarov@redhat.com> -@@ -743,8 +2457,8 @@ +@@ -743,8 +2536,8 @@ Backport from mainline 2013-04-18 Jakub Jelinek <jakub@redhat.com> @@ -33063,7 +34537,7 @@ Index: gcc/testsuite/ChangeLog 2013-05-02 Vladimir Makarov <vmakarov@redhat.com> -@@ -751,8 +2465,8 @@ +@@ -751,8 +2544,8 @@ Backport from mainline 2013-04-19 Vladimir Makarov <vmakarov@redhat.com> @@ -33074,7 +34548,7 @@ Index: gcc/testsuite/ChangeLog 2013-05-02 Ian Bolton <ian.bolton@arm.com> -@@ -1102,7 +2816,7 @@ +@@ -1102,7 +2895,7 @@ 2013-03-29 Tobias Burnus <burnus@net-b.de> PR fortran/56737 @@ -33083,7 +34557,7 @@ Index: gcc/testsuite/ChangeLog 2013-04-02 Richard Biener <rguenther@suse.de> -@@ -1636,7 +3350,7 @@ +@@ -1636,7 +3429,7 @@ 2013-02-20 Jan Hubicka <jh@suse.cz> PR tree-optimization/56265 @@ -33092,7 +34566,7 @@ Index: gcc/testsuite/ChangeLog 2013-02-20 Richard Biener <rguenther@suse.de> -@@ -1823,11 +3537,9 @@ +@@ -1823,11 +3616,9 @@ Avoid instrumenting duplicated memory access in the same basic block * c-c++-common/asan/no-redundant-instrumentation-1.c: New test. @@ -33262,6 +34736,50 @@ Index: gcc/testsuite/g++.dg/ext/attribute-test-1.C /* Ignore a warning that is irrelevant to the purpose of this test. */ /* { dg-prune-output ".*GCC vector returned by reference.*" } */ +/* { dg-prune-output "changes the ABI" } */ +Index: gcc/testsuite/g++.dg/vect/pr60836.cc +=================================================================== +--- a/src/gcc/testsuite/g++.dg/vect/pr60836.cc (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/g++.dg/vect/pr60836.cc (.../branches/gcc-4_8-branch) +@@ -0,0 +1,39 @@ ++// { dg-do compile } ++ ++int a, b; ++typedef double (*NormFunc) (const int &); ++int & ++max (int &p1, int &p2) ++{ ++ if (p1 < p2) ++ return p2; ++ return p1; ++} ++ ++struct A ++{ ++ int operator () (int p1, int p2) ++ { ++ return max (p1, p2); ++ } ++}; ++template < class, class > double ++norm_ (const int &) ++{ ++ char c, d; ++ A e; ++ for (; a; a++) ++ { ++ b = e (b, d); ++ b = e (b, c); ++ } ++} ++ ++void ++norm () ++{ ++ static NormFunc f = norm_ < int, A >; ++ f = 0; ++} ++ ++// { dg-final { cleanup-tree-dump "vect" } } Index: gcc/testsuite/g++.dg/vect/pr60729.cc =================================================================== --- a/src/gcc/testsuite/g++.dg/vect/pr60729.cc (.../tags/gcc_4_8_2_release) @@ -33627,6 +35145,22 @@ Index: gcc/testsuite/g++.dg/diagnostic/pr59838.C +// { dg-do compile } + +enum E { a, b = (E) a }; // { dg-error "conversion to incomplete type" } +Index: gcc/testsuite/g++.dg/diagnostic/pedantic.C +=================================================================== +--- a/src/gcc/testsuite/g++.dg/diagnostic/pedantic.C (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/g++.dg/diagnostic/pedantic.C (.../branches/gcc-4_8-branch) +@@ -0,0 +1,11 @@ ++// { dg-do compile } ++// { dg-options "-pedantic" } ++typedef void F(void); ++ ++void foo() ++{ ++ void* p = 0; ++ F* f1 = reinterpret_cast<F*>(p); // { dg-warning "ISO" } ++#pragma GCC diagnostic ignored "-pedantic" ++ F* f2 = reinterpret_cast<F*>(p); ++} Index: gcc/testsuite/g++.dg/diagnostic/pr58979.C =================================================================== --- a/src/gcc/testsuite/g++.dg/diagnostic/pr58979.C (.../tags/gcc_4_8_2_release) @@ -34465,6 +35999,32 @@ Index: gcc/testsuite/g++.dg/torture/pr57499.C + S s; + throw 1; +} +Index: gcc/testsuite/g++.dg/torture/pr60750.C +=================================================================== +--- a/src/gcc/testsuite/g++.dg/torture/pr60750.C (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/g++.dg/torture/pr60750.C (.../branches/gcc-4_8-branch) +@@ -0,0 +1,21 @@ ++// { dg-do run } ++// { dg-options "-std=c++11" } ++ ++#include <string> ++#include <stdexcept> ++ ++const std::string err_prefix = "Problem: "; ++void thrower (std::string msg) ++{ ++ throw std::runtime_error(err_prefix + std::move(msg)); ++} ++ ++int main(int argc, char **argv) ++{ ++ try { ++ std::string base = "hello"; ++ thrower(std::move(base)); ++ } catch (const std::runtime_error &e) { ++ } ++ return 0; ++} Index: gcc/testsuite/g++.dg/torture/pr59163.C =================================================================== --- a/src/gcc/testsuite/g++.dg/torture/pr59163.C (.../tags/gcc_4_8_2_release) @@ -34500,6 +36060,43 @@ Index: gcc/testsuite/g++.dg/torture/pr59163.C + B b = { 5, { 6, 7, 8, 9 } }; + foo (b.a); +} +Index: gcc/testsuite/g++.dg/torture/pr60895.C +=================================================================== +--- a/src/gcc/testsuite/g++.dg/torture/pr60895.C (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/testsuite/g++.dg/torture/pr60895.C (.../branches/gcc-4_8-branch) +@@ -0,0 +1,32 @@ ++// { dg-do compile } ++ ++struct C ++{ ++ double elems[3]; ++}; ++ ++C ++foo () ++{ ++ C a; ++ double *f = a.elems; ++ int b; ++ for (; b;) ++ { ++ *f = 0; ++ ++f; ++ } ++ return a; ++} ++ ++struct J ++{ ++ C c; ++ __attribute__((always_inline)) J () : c (foo ()) {} ++}; ++ ++void ++bar () ++{ ++ J (); ++} Index: gcc/testsuite/g++.dg/ipa/pr60640-1.C =================================================================== --- a/src/gcc/testsuite/g++.dg/ipa/pr60640-1.C (.../tags/gcc_4_8_2_release) @@ -35537,6 +37134,15 @@ Index: gcc/cp/typeck.c inc = cp_convert (argtype, inc, complain); +@@ -6639,7 +6649,7 @@ + where possible, and it is necessary in some cases. DR 195 + addresses this issue, but as of 2004/10/26 is still in + drafting. */ +- warning (0, "ISO C++ forbids casting between pointer-to-function and pointer-to-object"); ++ warning (OPT_Wpedantic, "ISO C++ forbids casting between pointer-to-function and pointer-to-object"); + return fold_if_not_in_template (build_nop (type, expr)); + } + else if (TREE_CODE (type) == VECTOR_TYPE) @@ -7194,8 +7204,7 @@ side effect associated with any single compound assignment operator. -- end note ] */ @@ -35614,7 +37220,12 @@ Index: gcc/cp/ChangeLog =================================================================== --- a/src/gcc/cp/ChangeLog (.../tags/gcc_4_8_2_release) +++ b/src/gcc/cp/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,246 @@ +@@ -1,3 +1,251 @@ ++2014-04-28 Daniel Gutson <daniel.gutson@tallertechnologies.com> ++ ++ * typeck.c (build_reinterpret_cast_1): Pass proper argument to ++ warn() in pedantic. ++ +2014-02-28 Jason Merrill <jason@redhat.com> + + PR c++/58845 @@ -38983,6 +40594,21 @@ Index: gcc/go/gofrontend/expressions.cc this->report_error(_("slice end must be integer")); std::string sval; +Index: gcc/opts.c +=================================================================== +--- a/src/gcc/opts.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/opts.c (.../branches/gcc-4_8-branch) +@@ -425,8 +425,8 @@ + { OPT_LEVELS_1_PLUS, OPT_fguess_branch_probability, NULL, 1 }, + { OPT_LEVELS_1_PLUS, OPT_fcprop_registers, NULL, 1 }, + { OPT_LEVELS_1_PLUS, OPT_fforward_propagate, NULL, 1 }, +- { OPT_LEVELS_1_PLUS, OPT_fif_conversion, NULL, 1 }, +- { OPT_LEVELS_1_PLUS, OPT_fif_conversion2, NULL, 1 }, ++ { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion, NULL, 1 }, ++ { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion2, NULL, 1 }, + { OPT_LEVELS_1_PLUS, OPT_fipa_pure_const, NULL, 1 }, + { OPT_LEVELS_1_PLUS, OPT_fipa_reference, NULL, 1 }, + { OPT_LEVELS_1_PLUS, OPT_fipa_profile, NULL, 1 }, Index: gcc/recog.c =================================================================== --- a/src/gcc/recog.c (.../tags/gcc_4_8_2_release) @@ -39923,6 +41549,36 @@ Index: gcc/ada/system-rtems.ads Null_Address : constant Address; Storage_Unit : constant := Standard'Storage_Unit; +Index: gcc/gimple-ssa-strength-reduction.c +=================================================================== +--- a/src/gcc/gimple-ssa-strength-reduction.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/gimple-ssa-strength-reduction.c (.../branches/gcc-4_8-branch) +@@ -735,15 +735,18 @@ + X = Y * c + ============================ + X = (B + i') * (S * c) */ +- base = base_cand->base_expr; +- index = base_cand->index; + temp = tree_to_double_int (base_cand->stride) + * tree_to_double_int (stride_in); +- stride = double_int_to_tree (TREE_TYPE (stride_in), temp); +- ctype = base_cand->cand_type; +- if (has_single_use (base_in)) +- savings = (base_cand->dead_savings +- + stmt_cost (base_cand->cand_stmt, speed)); ++ if (double_int_fits_to_tree_p (TREE_TYPE (stride_in), temp)) ++ { ++ base = base_cand->base_expr; ++ index = base_cand->index; ++ stride = double_int_to_tree (TREE_TYPE (stride_in), temp); ++ ctype = base_cand->cand_type; ++ if (has_single_use (base_in)) ++ savings = (base_cand->dead_savings ++ + stmt_cost (base_cand->cand_stmt, speed)); ++ } + } + else if (base_cand->kind == CAND_ADD + && operand_equal_p (base_cand->stride, integer_one_node, 0)) Index: gcc/tree-eh.c =================================================================== --- a/src/gcc/tree-eh.c (.../tags/gcc_4_8_2_release) @@ -41636,7 +43292,7 @@ Index: gcc/configure.ac + .align 4 + smac %g2, %g3, %g1 + umac %g2, %g3, %g1 -+ cas [[%g2]], %g3, %g1],, ++ casa [[%g2]] 0xb, %g3, %g1],, + [AC_DEFINE(HAVE_AS_LEON, 1, + [Define if your assembler supports LEON instructions.])]) ;; @@ -42243,7 +43899,22 @@ Index: gcc/tree-vect-loop.c new_name, step_expr); new_name = make_ssa_name (new_var, init_stmt); gimple_assign_set_lhs (init_stmt, new_name); -@@ -5564,8 +5574,9 @@ +@@ -3781,8 +3791,12 @@ + /* Set phi nodes arguments. */ + FOR_EACH_VEC_ELT (reduction_phis, i, phi) + { +- tree vec_init_def = vec_initial_defs[i]; +- tree def = vect_defs[i]; ++ tree vec_init_def, def; ++ gimple_seq stmts; ++ vec_init_def = force_gimple_operand (vec_initial_defs[i], &stmts, ++ true, NULL_TREE); ++ gsi_insert_seq_on_edge_immediate (loop_preheader_edge (loop), stmts); ++ def = vect_defs[i]; + for (j = 0; j < ncopies; j++) + { + /* Set the loop-entry arg of the reduction-phi. */ +@@ -5564,8 +5578,9 @@ && !STMT_VINFO_LIVE_P (stmt_info)) continue; @@ -42475,7 +44146,40 @@ Index: gcc/graphite-scop-detection.c =================================================================== --- a/src/gcc/graphite-scop-detection.c (.../tags/gcc_4_8_2_release) +++ b/src/gcc/graphite-scop-detection.c (.../branches/gcc-4_8-branch) -@@ -330,13 +330,10 @@ +@@ -203,7 +203,14 @@ + + switch (TREE_CODE (scev)) + { ++ case NEGATE_EXPR: ++ case BIT_NOT_EXPR: ++ CASE_CONVERT: ++ case NON_LVALUE_EXPR: ++ return graphite_can_represent_scev (TREE_OPERAND (scev, 0)); ++ + case PLUS_EXPR: ++ case POINTER_PLUS_EXPR: + case MINUS_EXPR: + return graphite_can_represent_scev (TREE_OPERAND (scev, 0)) + && graphite_can_represent_scev (TREE_OPERAND (scev, 1)); +@@ -225,6 +232,7 @@ + if (!evolution_function_right_is_integer_cst (scev) + || !graphite_can_represent_init (scev)) + return false; ++ return graphite_can_represent_scev (CHREC_LEFT (scev)); + + default: + break; +@@ -231,7 +239,8 @@ + } + + /* Only affine functions can be represented. */ +- if (!scev_is_linear_expression (scev)) ++ if (tree_contains_chrecs (scev, NULL) ++ || !scev_is_linear_expression (scev)) + return false; + + return true; +@@ -330,13 +339,10 @@ case GIMPLE_COND: { @@ -42490,7 +44194,7 @@ Index: gcc/graphite-scop-detection.c if (!(code == LT_EXPR || code == GT_EXPR || code == LE_EXPR -@@ -345,11 +342,14 @@ +@@ -345,11 +351,14 @@ || code == NE_EXPR)) return false; @@ -42883,6 +44587,20 @@ Index: gcc/cselib.c { has_mem = true; num_mems++; +Index: gcc/tree-cfgcleanup.c +=================================================================== +--- a/src/gcc/tree-cfgcleanup.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/tree-cfgcleanup.c (.../branches/gcc-4_8-branch) +@@ -539,9 +539,6 @@ + update_stmt (stmt); + changed = true; + } +- /* Similarly remove VDEF if there is any. */ +- else if (gimple_vdef (stmt)) +- update_stmt (stmt); + return changed; + } + Index: gcc/tree-ssa-pre.c =================================================================== --- a/src/gcc/tree-ssa-pre.c (.../tags/gcc_4_8_2_release) @@ -43632,6 +45350,20 @@ Index: gcc/tree-vect-stmts.c scalar_type = lang_hooks.types.type_for_mode (inner_mode, 1); /* We can't build a vector type of elements with alignment bigger than +Index: gcc/tree-inline.c +=================================================================== +--- a/src/gcc/tree-inline.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/tree-inline.c (.../branches/gcc-4_8-branch) +@@ -2841,7 +2841,8 @@ + { + var = return_slot; + gcc_assert (TREE_CODE (var) != SSA_NAME); +- TREE_ADDRESSABLE (var) |= TREE_ADDRESSABLE (result); ++ if (TREE_ADDRESSABLE (result)) ++ mark_addressable (var); + } + if ((TREE_CODE (TREE_TYPE (result)) == COMPLEX_TYPE + || TREE_CODE (TREE_TYPE (result)) == VECTOR_TYPE) Index: gcc/tree-ssa-phiprop.c =================================================================== --- a/src/gcc/tree-ssa-phiprop.c (.../tags/gcc_4_8_2_release) @@ -43893,6 +45625,20 @@ Index: gcc/bb-reorder.c { fall_thru = e; break; +Index: gcc/tree-vect-generic.c +=================================================================== +--- a/src/gcc/tree-vect-generic.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/tree-vect-generic.c (.../branches/gcc-4_8-branch) +@@ -1006,7 +1006,8 @@ + + if (!optimize + || !VECTOR_INTEGER_TYPE_P (type) +- || TREE_CODE (rhs2) != VECTOR_CST) ++ || TREE_CODE (rhs2) != VECTOR_CST ++ || !VECTOR_MODE_P (TYPE_MODE (type))) + break; + + ret = expand_vector_divmod (gsi, type, rhs1, rhs2, code); Index: gcc/tree-flow.h =================================================================== --- a/src/gcc/tree-flow.h (.../tags/gcc_4_8_2_release) @@ -45719,6 +47465,26 @@ Index: gcc/config/sparc/sparc.md "fsqrts\t%1, %0" [(set_attr "type" "fpsqrts")]) +@@ -5821,19 +5838,6 @@ + } + [(set_attr "type" "shift")]) + +-(define_insn "*ashlsi3_extend" +- [(set (match_operand:DI 0 "register_operand" "=r") +- (zero_extend:DI +- (ashift:SI (match_operand:SI 1 "register_operand" "r") +- (match_operand:SI 2 "arith_operand" "rI"))))] +- "TARGET_ARCH64" +-{ +- if (GET_CODE (operands[2]) == CONST_INT) +- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); +- return "sll\t%1, %2, %0"; +-} +- [(set_attr "type" "shift")]) +- + (define_expand "ashldi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (ashift:DI (match_operand:DI 1 "register_operand" "r") Index: gcc/config/sparc/t-sparc =================================================================== --- a/src/gcc/config/sparc/t-sparc (.../tags/gcc_4_8_2_release) @@ -45736,7 +47502,18 @@ Index: gcc/config/sparc/sparc.opt =================================================================== --- a/src/gcc/config/sparc/sparc.opt (.../tags/gcc_4_8_2_release) +++ b/src/gcc/config/sparc/sparc.opt (.../branches/gcc-4_8-branch) -@@ -146,6 +146,9 @@ +@@ -113,6 +113,10 @@ + Target + Optimize tail call instructions in assembler and linker + ++muser-mode ++Target Report Mask(USER_MODE) ++Do not generate code that can only run in supervisor mode ++ + mcpu= + Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7) + Use features of and schedule code for given CPU +@@ -146,6 +150,9 @@ Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON) EnumValue @@ -45746,7 +47523,7 @@ Index: gcc/config/sparc/sparc.opt Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE) EnumValue -@@ -201,9 +204,19 @@ +@@ -201,9 +208,19 @@ Enable workaround for single erratum of AT697F processor (corresponding to erratum #13 of AT697E processor) @@ -45789,16 +47566,36 @@ Index: gcc/config/sparc/sync.md "") (define_insn "*atomic_compare_and_swap<mode>_1" -@@ -187,7 +188,7 @@ +@@ -187,10 +188,27 @@ [(match_operand:I48MODE 2 "register_operand" "r") (match_operand:I48MODE 3 "register_operand" "0")] UNSPECV_CAS))] - "TARGET_V9 && (<MODE>mode == SImode || TARGET_ARCH64)" -+ "(TARGET_V9 || TARGET_LEON3) && (<MODE>mode != DImode || TARGET_ARCH64)" ++ "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)" "cas<modesuffix>\t%1, %2, %0" [(set_attr "type" "multi")]) -@@ -220,7 +221,7 @@ ++(define_insn "*atomic_compare_and_swap_leon3_1" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (match_operand:SI 1 "mem_noofs_operand" "+w")) ++ (set (match_dup 1) ++ (unspec_volatile:SI ++ [(match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CAS))] ++ "TARGET_LEON3" ++{ ++ if (TARGET_USER_MODE) ++ return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */ ++ else ++ return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */ ++} ++ [(set_attr "type" "multi")]) ++ + (define_insn "*atomic_compare_and_swapdi_v8plus" + [(set (match_operand:DI 0 "register_operand" "=h") + (match_operand:DI 1 "mem_noofs_operand" "+w")) +@@ -220,7 +238,7 @@ (match_operand:SI 1 "memory_operand" "") (match_operand:SI 2 "register_operand" "") (match_operand:SI 3 "const_int_operand" "")] @@ -45807,7 +47604,7 @@ Index: gcc/config/sparc/sync.md { enum memmodel model = (enum memmodel) INTVAL (operands[3]); -@@ -236,7 +237,7 @@ +@@ -236,7 +254,7 @@ UNSPECV_SWAP)) (set (match_dup 1) (match_operand:SI 2 "register_operand" "0"))] @@ -45816,7 +47613,7 @@ Index: gcc/config/sparc/sync.md "swap\t%1, %0" [(set_attr "type" "multi")]) -@@ -244,7 +245,7 @@ +@@ -244,7 +262,7 @@ [(match_operand:QI 0 "register_operand" "") (match_operand:QI 1 "memory_operand" "") (match_operand:SI 2 "const_int_operand" "")] @@ -45825,7 +47622,7 @@ Index: gcc/config/sparc/sync.md { enum memmodel model = (enum memmodel) INTVAL (operands[2]); rtx ret; -@@ -268,6 +269,6 @@ +@@ -268,6 +286,6 @@ (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")] UNSPECV_LDSTUB)) (set (match_dup 1) (const_int -1))] @@ -48883,7 +50680,28 @@ Index: gcc/config/sh/sh.c =================================================================== --- a/src/gcc/config/sh/sh.c (.../tags/gcc_4_8_2_release) +++ b/src/gcc/config/sh/sh.c (.../branches/gcc-4_8-branch) -@@ -310,9 +310,7 @@ +@@ -24,6 +24,9 @@ + malloc & co, which are poisoned by "system.h". The proper solution is + to include <cstdlib> in "system.h" instead of <stdlib.h>. */ + #include <cstdlib> ++#include <sstream> ++#include <vector> ++#include <algorithm> + + #include "config.h" + #include "system.h" +@@ -60,10 +63,6 @@ + #include "tm-constrs.h" + #include "opts.h" + +-#include <sstream> +-#include <vector> +-#include <algorithm> +- + int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch; + + #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0) +@@ -310,9 +309,7 @@ static void sh_conditional_register_usage (void); static bool sh_legitimate_constant_p (enum machine_mode, rtx); static int mov_insn_size (enum machine_mode, bool); @@ -48893,7 +50711,7 @@ Index: gcc/config/sh/sh.c static bool sequence_insn_p (rtx); static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool); static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&, -@@ -3628,8 +3626,8 @@ +@@ -3628,8 +3625,8 @@ /* Determine the maximum possible displacement for a move insn for the specified mode. */ @@ -48904,7 +50722,7 @@ Index: gcc/config/sh/sh.c { /* The 4 byte displacement move insns are the same as the 2 byte versions but take a 12 bit displacement. All we need to do is to -@@ -3665,8 +3663,8 @@ +@@ -3665,8 +3662,8 @@ } /* Return the displacement value of a displacement address. */ @@ -48915,7 +50733,7 @@ Index: gcc/config/sh/sh.c { gcc_assert (satisfies_constraint_Sdd (x)); return INTVAL (XEXP (XEXP (x, 0), 1)); -@@ -3703,12 +3701,12 @@ +@@ -3703,12 +3700,12 @@ HImode and QImode loads/stores with displacement put pressure on R0 which will most likely require another reg copy. Thus account a higher cost for that. */ @@ -48930,7 +50748,7 @@ Index: gcc/config/sh/sh.c return 2; /* The displacement is probably out of range and will require extra -@@ -10218,7 +10216,7 @@ +@@ -10218,7 +10215,7 @@ else { const HOST_WIDE_INT offset = INTVAL (op); @@ -48939,7 +50757,7 @@ Index: gcc/config/sh/sh.c const int align_mask = mov_insn_alignment_mask (mode, consider_sh2a); /* If the mode does not support any displacement always return false. -@@ -10404,7 +10402,7 @@ +@@ -10404,7 +10401,7 @@ effectively disable the small displacement insns. */ const int mode_sz = GET_MODE_SIZE (mode); const int mov_insn_sz = mov_insn_size (mode, false); @@ -48948,7 +50766,7 @@ Index: gcc/config/sh/sh.c const int max_disp_next = max_disp + mov_insn_sz; HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_sz : 0; HOST_WIDE_INT offset_adjust; -@@ -13165,7 +13163,8 @@ +@@ -13165,7 +13162,8 @@ the insns must have the appropriate alternatives. */ if ((mode == QImode || mode == HImode) && rclass != R0_REGS && satisfies_constraint_Sdd (x) @@ -50560,6 +52378,23 @@ Index: gcc/config/aarch64/iterators.md (define_int_attr offsetlr [(UNSPEC_SSLI "1") (UNSPEC_USLI "1") (UNSPEC_SSRI "0") (UNSPEC_USRI "0")]) +Index: gcc/config/aarch64/aarch64.h +=================================================================== +--- a/src/gcc/config/aarch64/aarch64.h (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/config/aarch64/aarch64.h (.../branches/gcc-4_8-branch) +@@ -73,9 +73,9 @@ + #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) + + /* AdvSIMD is supported in the default configuration, unless disabled by +- -mgeneral-regs-only. */ +-#define TARGET_SIMD !TARGET_GENERAL_REGS_ONLY +-#define TARGET_FLOAT !TARGET_GENERAL_REGS_ONLY ++ -mgeneral-regs-only or the +nosimd extension. */ ++#define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) ++#define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) + + #define UNITS_PER_WORD 8 + Index: gcc/config/rs6000/power8.md =================================================================== --- a/src/gcc/config/rs6000/power8.md (.../tags/gcc_4_8_2_release) @@ -51364,7 +53199,17 @@ Index: gcc/config/rs6000/predicates.md ;; Return 1 if op is a constant integer that can fit in a D field. (define_predicate "short_cint_operand" (and (match_code "const_int") -@@ -166,6 +176,11 @@ +@@ -161,11 +171,21 @@ + (and (match_code "const_int") + (match_test "IN_RANGE (INTVAL (op), 0, 1)"))) + ++;; Match op = 0..3. ++(define_predicate "const_0_to_3_operand" ++ (and (match_code "const_int") ++ (match_test "IN_RANGE (INTVAL (op), 0, 3)"))) ++ + ;; Match op = 2 or op = 3. + (define_predicate "const_2_to_3_operand" (and (match_code "const_int") (match_test "IN_RANGE (INTVAL (op), 2, 3)"))) @@ -51376,7 +53221,7 @@ Index: gcc/config/rs6000/predicates.md ;; Return 1 if op is a register that is not special. (define_predicate "gpc_reg_operand" (match_operand 0 "register_operand") -@@ -182,9 +197,95 @@ +@@ -182,9 +202,95 @@ if (REGNO (op) >= ARG_POINTER_REGNUM && !CA_REGNO_P (REGNO (op))) return 1; @@ -51472,7 +53317,7 @@ Index: gcc/config/rs6000/predicates.md ;; Return 1 if op is a register that is a condition register field. (define_predicate "cc_reg_operand" (match_operand 0 "register_operand") -@@ -315,6 +416,11 @@ +@@ -315,6 +421,11 @@ && CONST_DOUBLE_HIGH (op) == 0") (match_operand 0 "gpc_reg_operand")))) @@ -51484,7 +53329,7 @@ Index: gcc/config/rs6000/predicates.md ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register ;; with no more than one instruction per word. (define_predicate "easy_fp_constant" -@@ -333,6 +439,11 @@ +@@ -333,6 +444,11 @@ && mode != DImode) return 1; @@ -51496,19 +53341,19 @@ Index: gcc/config/rs6000/predicates.md if (DECIMAL_FLOAT_MODE_P (mode)) return 0; -@@ -521,6 +632,55 @@ +@@ -521,6 +637,55 @@ (and (match_operand 0 "memory_operand") (match_test "offsettable_nonstrict_memref_p (op)"))) +;; Return 1 if the operand is suitable for load/store quad memory. -+;; This predicate only checks for non-atomic loads/stores. ++;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). +(define_predicate "quad_memory_operand" + (match_code "mem") +{ + rtx addr, op0, op1; + int ret; + -+ if (!TARGET_QUAD_MEMORY) ++ if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI) + ret = 0; + + else if (!memory_operand (op, mode)) @@ -51552,7 +53397,7 @@ Index: gcc/config/rs6000/predicates.md ;; Return 1 if the operand is an indexed or indirect memory operand. (define_predicate "indexed_or_indirect_operand" (match_code "mem") -@@ -535,6 +695,19 @@ +@@ -535,6 +700,19 @@ return indexed_or_indirect_address (op, mode); }) @@ -51572,7 +53417,7 @@ Index: gcc/config/rs6000/predicates.md ;; Return 1 if the operand is an indexed or indirect memory operand with an ;; AND -16 in it, used to recognize when we need to switch to Altivec loads ;; to realign loops instead of VSX (altivec silently ignores the bottom bits, -@@ -560,6 +733,28 @@ +@@ -560,6 +738,28 @@ && REG_P (XEXP (op, 1)))") (match_operand 0 "address_operand"))) @@ -51601,7 +53446,7 @@ Index: gcc/config/rs6000/predicates.md ;; Used for the destination of the fix_truncdfsi2 expander. ;; If stfiwx will be used, the result goes to memory; otherwise, ;; we're going to emit a store and a load of a subreg, so the dest is a -@@ -883,7 +1078,8 @@ +@@ -883,7 +1083,8 @@ (and (match_code "symbol_ref") (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)) && ((SYMBOL_REF_LOCAL_P (op) @@ -51611,7 +53456,7 @@ Index: gcc/config/rs6000/predicates.md || !SYMBOL_REF_EXTERNAL_P (op))) || (op == XEXP (DECL_RTL (current_function_decl), 0)))"))) -@@ -1364,6 +1560,26 @@ +@@ -1364,6 +1565,26 @@ return 1; }) @@ -51638,7 +53483,7 @@ Index: gcc/config/rs6000/predicates.md ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL. (define_predicate "lmw_operation" (match_code "parallel") -@@ -1534,3 +1750,99 @@ +@@ -1534,3 +1755,99 @@ return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL; }) @@ -52901,7 +54746,83 @@ Index: gcc/config/rs6000/rs6000-builtin.def /* SPE convenience macros. */ #define BU_SPE_1(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_1 (SPE_BUILTIN_ ## ENUM, /* ENUM */ \ -@@ -414,6 +587,7 @@ +@@ -397,6 +570,75 @@ + MASK, /* MASK */ \ + (ATTR | RS6000_BTC_SPECIAL), /* ATTR */ \ + CODE_FOR_nothing) /* ICODE */ ++ ++ ++/* Decimal floating point builtins for instructions. */ ++#define BU_DFP_MISC_1(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_DFP, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_UNARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_DFP_MISC_2(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_DFP, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_BINARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++ ++/* Miscellaneous builtins for instructions added in ISA 2.06. These ++ instructions don't require either the DFP or VSX options, just the basic ISA ++ 2.06 (popcntd) enablement since they operate on general purpose ++ registers. */ ++#define BU_P7_MISC_1(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_POPCNTD, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_UNARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_P7_MISC_2(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_POPCNTD, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_BINARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++ ++/* Miscellaneous builtins for instructions added in ISA 2.07. These ++ instructions do require the ISA 2.07 vector support, but they aren't vector ++ instructions. */ ++#define BU_P8V_MISC_3(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_P8_VECTOR, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_TERNARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++/* Miscellaneous builtins. */ ++#define BU_MISC_1(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_HARD_FLOAT, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_UNARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ ++#define BU_MISC_2(ENUM, NAME, ATTR, ICODE) \ ++ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \ ++ "__builtin_" NAME, /* NAME */ \ ++ RS6000_BTM_HARD_FLOAT, /* MASK */ \ ++ (RS6000_BTC_ ## ATTR /* ATTR */ \ ++ | RS6000_BTC_BINARY), \ ++ CODE_FOR_ ## ICODE) /* ICODE */ ++ + #endif + + /* Insure 0 is not a legitimate index. */ +@@ -414,6 +656,7 @@ BU_ALTIVEC_3 (VMSUMUHS, "vmsumuhs", SAT, altivec_vmsumuhs) BU_ALTIVEC_3 (VMSUMSHS, "vmsumshs", SAT, altivec_vmsumshs) BU_ALTIVEC_3 (VNMSUBFP, "vnmsubfp", FP, nfmsv4sf4) @@ -52909,7 +54830,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_ALTIVEC_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df) BU_ALTIVEC_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di) BU_ALTIVEC_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf) -@@ -420,6 +594,7 @@ +@@ -420,6 +663,7 @@ BU_ALTIVEC_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si) BU_ALTIVEC_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi) BU_ALTIVEC_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi_uns) @@ -52917,7 +54838,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_ALTIVEC_3 (VPERM_2DI_UNS, "vperm_2di_uns", CONST, altivec_vperm_v2di_uns) BU_ALTIVEC_3 (VPERM_4SI_UNS, "vperm_4si_uns", CONST, altivec_vperm_v4si_uns) BU_ALTIVEC_3 (VPERM_8HI_UNS, "vperm_8hi_uns", CONST, altivec_vperm_v8hi_uns) -@@ -430,10 +605,12 @@ +@@ -430,10 +674,12 @@ BU_ALTIVEC_3 (VSEL_16QI, "vsel_16qi", CONST, vector_select_v16qi) BU_ALTIVEC_3 (VSEL_2DF, "vsel_2df", CONST, vector_select_v2df) BU_ALTIVEC_3 (VSEL_2DI, "vsel_2di", CONST, vector_select_v2di) @@ -52930,7 +54851,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_ALTIVEC_3 (VSLDOI_16QI, "vsldoi_16qi", CONST, altivec_vsldoi_v16qi) BU_ALTIVEC_3 (VSLDOI_8HI, "vsldoi_8hi", CONST, altivec_vsldoi_v8hi) BU_ALTIVEC_3 (VSLDOI_4SI, "vsldoi_4si", CONST, altivec_vsldoi_v4si) -@@ -626,6 +803,8 @@ +@@ -626,6 +872,8 @@ BU_ALTIVEC_X (LD_INTERNAL_2df, "ld_internal_2df", MEM) BU_ALTIVEC_X (ST_INTERNAL_2di, "st_internal_2di", MEM) BU_ALTIVEC_X (LD_INTERNAL_2di, "ld_internal_2di", MEM) @@ -52939,7 +54860,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_ALTIVEC_X (MTVSCR, "mtvscr", MISC) BU_ALTIVEC_X (MFVSCR, "mfvscr", MISC) BU_ALTIVEC_X (DSSALL, "dssall", MISC) -@@ -636,8 +815,26 @@ +@@ -636,8 +884,26 @@ BU_ALTIVEC_X (LVEHX, "lvehx", MEM) BU_ALTIVEC_X (LVEWX, "lvewx", MEM) BU_ALTIVEC_X (LVXL, "lvxl", MEM) @@ -52966,7 +54887,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_ALTIVEC_C (LVLX, "lvlx", MEM) BU_ALTIVEC_C (LVLXL, "lvlxl", MEM) BU_ALTIVEC_C (LVRX, "lvrx", MEM) -@@ -646,6 +843,12 @@ +@@ -646,6 +912,12 @@ BU_ALTIVEC_X (STVEHX, "stvehx", MEM) BU_ALTIVEC_X (STVEWX, "stvewx", MEM) BU_ALTIVEC_X (STVXL, "stvxl", MEM) @@ -52979,7 +54900,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_ALTIVEC_C (STVLX, "stvlx", MEM) BU_ALTIVEC_C (STVLXL, "stvlxl", MEM) BU_ALTIVEC_C (STVRX, "stvrx", MEM) -@@ -904,6 +1107,7 @@ +@@ -904,6 +1176,7 @@ BU_VSX_3 (XVNMADDDP, "xvnmadddp", CONST, nfmav2df4) BU_VSX_3 (XVNMSUBDP, "xvnmsubdp", CONST, nfmsv2df4) @@ -52987,7 +54908,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_VSX_3 (XXSEL_2DI, "xxsel_2di", CONST, vector_select_v2di) BU_VSX_3 (XXSEL_2DF, "xxsel_2df", CONST, vector_select_v2df) BU_VSX_3 (XXSEL_4SF, "xxsel_4sf", CONST, vector_select_v4sf) -@@ -910,11 +1114,13 @@ +@@ -910,11 +1183,13 @@ BU_VSX_3 (XXSEL_4SI, "xxsel_4si", CONST, vector_select_v4si) BU_VSX_3 (XXSEL_8HI, "xxsel_8hi", CONST, vector_select_v8hi) BU_VSX_3 (XXSEL_16QI, "xxsel_16qi", CONST, vector_select_v16qi) @@ -53001,7 +54922,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_VSX_3 (VPERM_2DI, "vperm_2di", CONST, altivec_vperm_v2di) BU_VSX_3 (VPERM_2DF, "vperm_2df", CONST, altivec_vperm_v2df) BU_VSX_3 (VPERM_4SF, "vperm_4sf", CONST, altivec_vperm_v4sf) -@@ -921,11 +1127,13 @@ +@@ -921,11 +1196,13 @@ BU_VSX_3 (VPERM_4SI, "vperm_4si", CONST, altivec_vperm_v4si) BU_VSX_3 (VPERM_8HI, "vperm_8hi", CONST, altivec_vperm_v8hi) BU_VSX_3 (VPERM_16QI, "vperm_16qi", CONST, altivec_vperm_v16qi) @@ -53015,7 +54936,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_VSX_3 (XXPERMDI_2DF, "xxpermdi_2df", CONST, vsx_xxpermdi_v2df) BU_VSX_3 (XXPERMDI_2DI, "xxpermdi_2di", CONST, vsx_xxpermdi_v2di) BU_VSX_3 (XXPERMDI_4SF, "xxpermdi_4sf", CONST, vsx_xxpermdi_v4sf) -@@ -932,6 +1140,7 @@ +@@ -932,6 +1209,7 @@ BU_VSX_3 (XXPERMDI_4SI, "xxpermdi_4si", CONST, vsx_xxpermdi_v4si) BU_VSX_3 (XXPERMDI_8HI, "xxpermdi_8hi", CONST, vsx_xxpermdi_v8hi) BU_VSX_3 (XXPERMDI_16QI, "xxpermdi_16qi", CONST, vsx_xxpermdi_v16qi) @@ -53023,7 +54944,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_VSX_3 (SET_2DF, "set_2df", CONST, vsx_set_v2df) BU_VSX_3 (SET_2DI, "set_2di", CONST, vsx_set_v2di) BU_VSX_3 (XXSLDWI_2DI, "xxsldwi_2di", CONST, vsx_xxsldwi_v2di) -@@ -1012,7 +1221,7 @@ +@@ -1012,7 +1290,7 @@ BU_VSX_1 (XVRESP, "xvresp", CONST, vsx_frev4sf2) BU_VSX_1 (XSCVDPSP, "xscvdpsp", CONST, vsx_xscvdpsp) @@ -53032,7 +54953,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_VSX_1 (XVCVDPSP, "xvcvdpsp", CONST, vsx_xvcvdpsp) BU_VSX_1 (XVCVSPDP, "xvcvspdp", CONST, vsx_xvcvspdp) BU_VSX_1 (XSTSQRTDP_FE, "xstsqrtdp_fe", CONST, vsx_tsqrtdf2_fe) -@@ -1052,9 +1261,9 @@ +@@ -1052,9 +1330,9 @@ BU_VSX_1 (XSRDPI, "xsrdpi", CONST, vsx_xsrdpi) BU_VSX_1 (XSRDPIC, "xsrdpic", CONST, vsx_xsrdpic) @@ -53045,7 +54966,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def /* VSX predicate functions. */ BU_VSX_P (XVCMPEQSP_P, "xvcmpeqsp_p", CONST, vector_eq_v4sf_p) -@@ -1066,6 +1275,7 @@ +@@ -1066,6 +1344,7 @@ /* VSX builtins that are handled as special cases. */ BU_VSX_X (LXSDX, "lxsdx", MEM) @@ -53053,7 +54974,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_VSX_X (LXVD2X_V2DF, "lxvd2x_v2df", MEM) BU_VSX_X (LXVD2X_V2DI, "lxvd2x_v2di", MEM) BU_VSX_X (LXVDSX, "lxvdsx", MEM) -@@ -1074,6 +1284,7 @@ +@@ -1074,6 +1353,7 @@ BU_VSX_X (LXVW4X_V8HI, "lxvw4x_v8hi", MEM) BU_VSX_X (LXVW4X_V16QI, "lxvw4x_v16qi", MEM) BU_VSX_X (STXSDX, "stxsdx", MEM) @@ -53061,7 +54982,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_VSX_X (STXVD2X_V2DF, "stxsdx_v2df", MEM) BU_VSX_X (STXVD2X_V2DI, "stxsdx_v2di", MEM) BU_VSX_X (STXVW4X_V4SF, "stxsdx_v4sf", MEM) -@@ -1104,10 +1315,13 @@ +@@ -1104,10 +1384,13 @@ BU_VSX_X (XSNMSUBADP, "xsnmsubadp", FP) BU_VSX_X (XSNMSUBMDP, "xsnmsubmdp", FP) BU_VSX_X (XSSUBDP, "xssubdp", FP) @@ -53075,7 +54996,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def BU_VSX_X (VEC_EXT_V2DF, "vec_ext_v2df", CONST) BU_VSX_X (VEC_EXT_V2DI, "vec_ext_v2di", CONST) -@@ -1132,6 +1346,191 @@ +@@ -1132,6 +1415,249 @@ BU_VSX_OVERLOAD_X (LD, "ld") BU_VSX_OVERLOAD_X (ST, "st") @@ -53145,10 +55066,10 @@ Index: gcc/config/rs6000/rs6000-builtin.def +BU_P8V_AV_2 (ORC_V2DF, "orc_v2df", CONST, orcv2df3) + +/* 3 argument altivec instructions added in ISA 2.07. */ -+BU_P8V_AV_3 (VADDEUQM, "vaddeuqm", CONST, altivec_vaddeuqm) -+BU_P8V_AV_3 (VADDECUQ, "vaddecuq", CONST, altivec_vaddecuq) -+BU_P8V_AV_3 (VSUBEUQM, "vsubeuqm", CONST, altivec_vsubeuqm) -+BU_P8V_AV_3 (VSUBECUQ, "vsubecuq", CONST, altivec_vsubecuq) ++BU_P8V_AV_3 (VADDEUQM, "vaddeuqm", CONST, altivec_vaddeuqm) ++BU_P8V_AV_3 (VADDECUQ, "vaddecuq", CONST, altivec_vaddecuq) ++BU_P8V_AV_3 (VSUBEUQM, "vsubeuqm", CONST, altivec_vsubeuqm) ++BU_P8V_AV_3 (VSUBECUQ, "vsubecuq", CONST, altivec_vsubecuq) + +/* Vector comparison instructions added in ISA 2.07. */ +BU_P8V_AV_2 (VCMPEQUD, "vcmpequd", CONST, vector_eqv2di) @@ -53208,6 +55129,64 @@ Index: gcc/config/rs6000/rs6000-builtin.def +BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm") + + ++/* 2 argument extended divide functions added in ISA 2.06. */ ++BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si) ++BU_P7_MISC_2 (DIVWEO, "divweo", CONST, diveo_si) ++BU_P7_MISC_2 (DIVWEU, "divweu", CONST, diveu_si) ++BU_P7_MISC_2 (DIVWEUO, "divweuo", CONST, diveuo_si) ++BU_P7_MISC_2 (DIVDE, "divde", CONST, dive_di) ++BU_P7_MISC_2 (DIVDEO, "divdeo", CONST, diveo_di) ++BU_P7_MISC_2 (DIVDEU, "divdeu", CONST, diveu_di) ++BU_P7_MISC_2 (DIVDEUO, "divdeuo", CONST, diveuo_di) ++ ++/* 1 argument DFP (decimal floating point) functions added in ISA 2.05. */ ++BU_DFP_MISC_1 (DXEX, "dxex", CONST, dfp_dxex_dd) ++BU_DFP_MISC_1 (DXEXQ, "dxexq", CONST, dfp_dxex_td) ++ ++/* 2 argument DFP (decimal floating point) functions added in ISA 2.05. */ ++BU_DFP_MISC_2 (DDEDPD, "ddedpd", CONST, dfp_ddedpd_dd) ++BU_DFP_MISC_2 (DDEDPDQ, "ddedpdq", CONST, dfp_ddedpd_td) ++BU_DFP_MISC_2 (DENBCD, "denbcd", CONST, dfp_denbcd_dd) ++BU_DFP_MISC_2 (DENBCDQ, "denbcdq", CONST, dfp_denbcd_td) ++BU_DFP_MISC_2 (DIEX, "diex", CONST, dfp_diex_dd) ++BU_DFP_MISC_2 (DIEXQ, "diexq", CONST, dfp_diex_td) ++BU_DFP_MISC_2 (DSCLI, "dscli", CONST, dfp_dscli_dd) ++BU_DFP_MISC_2 (DSCLIQ, "dscliq", CONST, dfp_dscli_td) ++BU_DFP_MISC_2 (DSCRI, "dscri", CONST, dfp_dscri_dd) ++BU_DFP_MISC_2 (DSCRIQ, "dscriq", CONST, dfp_dscri_td) ++ ++/* 1 argument BCD functions added in ISA 2.06. */ ++BU_P7_MISC_1 (CDTBCD, "cdtbcd", CONST, cdtbcd) ++BU_P7_MISC_1 (CBCDTD, "cbcdtd", CONST, cbcdtd) ++ ++/* 2 argument BCD functions added in ISA 2.06. */ ++BU_P7_MISC_2 (ADDG6S, "addg6s", CONST, addg6s) ++ ++/* 3 argument BCD functions added in ISA 2.07. */ ++BU_P8V_MISC_3 (BCDADD, "bcdadd", CONST, bcdadd) ++BU_P8V_MISC_3 (BCDADD_LT, "bcdadd_lt", CONST, bcdadd_lt) ++BU_P8V_MISC_3 (BCDADD_EQ, "bcdadd_eq", CONST, bcdadd_eq) ++BU_P8V_MISC_3 (BCDADD_GT, "bcdadd_gt", CONST, bcdadd_gt) ++BU_P8V_MISC_3 (BCDADD_OV, "bcdadd_ov", CONST, bcdadd_unordered) ++BU_P8V_MISC_3 (BCDSUB, "bcdsub", CONST, bcdsub) ++BU_P8V_MISC_3 (BCDSUB_LT, "bcdsub_lt", CONST, bcdsub_lt) ++BU_P8V_MISC_3 (BCDSUB_EQ, "bcdsub_eq", CONST, bcdsub_eq) ++BU_P8V_MISC_3 (BCDSUB_GT, "bcdsub_gt", CONST, bcdsub_gt) ++BU_P8V_MISC_3 (BCDSUB_OV, "bcdsub_ov", CONST, bcdsub_unordered) ++ ++/* 2 argument pack/unpack 128-bit floating point types. */ ++BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd) ++BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd) ++ ++BU_MISC_2 (PACK_TF, "pack_longdouble", CONST, packtf) ++BU_MISC_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf) ++BU_MISC_1 (UNPACK_TF_0, "longdouble_dw0", CONST, unpacktf_0) ++BU_MISC_1 (UNPACK_TF_1, "longdouble_dw1", CONST, unpacktf_1) ++ ++BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti) ++BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti) ++ ++ +/* 1 argument crypto functions. */ +BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox) + @@ -53267,7 +55246,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def /* 3 argument paired floating point builtins. */ BU_PAIRED_3 (MSUB, "msub", FP, fmsv2sf4) BU_PAIRED_3 (MADD, "madd", FP, fmav2sf4) -@@ -1430,10 +1829,10 @@ +@@ -1430,10 +1956,10 @@ RS6000_BTC_FP) BU_SPECIAL_X (RS6000_BUILTIN_GET_TB, "__builtin_ppc_get_timebase", @@ -55965,7 +57944,7 @@ Index: gcc/config/rs6000/rs6000.c if (global_init_p || TARGET_DEBUG_TARGET) { if (TARGET_DEBUG_REG) -@@ -2369,16 +3000,19 @@ +@@ -2369,16 +3000,21 @@ HOST_WIDE_INT rs6000_builtin_mask_calculate (void) { @@ -55991,11 +57970,13 @@ Index: gcc/config/rs6000/rs6000.c + | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0) + | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0) + | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0) -+ | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)); ++ | ((TARGET_HTM) ? RS6000_BTM_HTM : 0) ++ | ((TARGET_DFP) ? RS6000_BTM_DFP : 0) ++ | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)); } /* Override command line options. Mostly we process the processor type and -@@ -2415,7 +3049,8 @@ +@@ -2415,7 +3051,8 @@ calculation works better for RTL loop invariant motion on targets with enough (>= 32) registers. It is an expensive optimization. So it is on only for peak performance. */ @@ -56005,7 +57986,7 @@ Index: gcc/config/rs6000/rs6000.c flag_ira_loop_pressure = 1; /* Set the pointer size. */ -@@ -2609,6 +3244,24 @@ +@@ -2609,6 +3246,24 @@ } } @@ -56030,7 +58011,7 @@ Index: gcc/config/rs6000/rs6000.c /* Add some warnings for VSX. */ if (TARGET_VSX) { -@@ -2619,15 +3272,13 @@ +@@ -2619,15 +3274,13 @@ if (rs6000_isa_flags_explicit & OPTION_MASK_VSX) msg = N_("-mvsx requires hardware floating point"); else @@ -56050,7 +58031,7 @@ Index: gcc/config/rs6000/rs6000.c else if (TARGET_AVOID_XFORM > 0) msg = N_("-mvsx needs indexed addressing"); else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit -@@ -2647,9 +3298,24 @@ +@@ -2647,9 +3300,24 @@ } } @@ -56076,7 +58057,7 @@ Index: gcc/config/rs6000/rs6000.c rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit); else if (TARGET_POPCNTD) rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit); -@@ -2664,6 +3330,92 @@ +@@ -2664,6 +3332,99 @@ else if (TARGET_ALTIVEC) rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit); @@ -56115,6 +58096,13 @@ Index: gcc/config/rs6000/rs6000.c + rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE; + } + ++ if (TARGET_DFP && !TARGET_HARD_FLOAT) ++ { ++ if (rs6000_isa_flags_explicit & OPTION_MASK_DFP) ++ error ("-mhard-dfp requires -mhard-float"); ++ rs6000_isa_flags &= ~OPTION_MASK_DFP; ++ } ++ + /* The quad memory instructions only works in 64-bit mode. In 32-bit mode, + silently turn off quad memory mode. */ + if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64) @@ -56169,7 +58157,7 @@ Index: gcc/config/rs6000/rs6000.c /* E500mc does "better" if we inline more aggressively. Respect the user's opinion, though. */ if (rs6000_block_move_inline_limit == 0 -@@ -2787,9 +3539,13 @@ +@@ -2787,9 +3548,13 @@ /* Place FP constants in the constant pool instead of TOC if section anchors enabled. */ @@ -56184,7 +58172,7 @@ Index: gcc/config/rs6000/rs6000.c #ifdef SUBTARGET_OVERRIDE_OPTIONS SUBTARGET_OVERRIDE_OPTIONS; #endif -@@ -2800,6 +3556,9 @@ +@@ -2800,6 +3565,9 @@ SUB3TARGET_OVERRIDE_OPTIONS; #endif @@ -56194,7 +58182,7 @@ Index: gcc/config/rs6000/rs6000.c /* For the E500 family of cores, reset the single/double FP flags to let us check that they remain constant across attributes or pragmas. Also, clear a possible request for string instructions, not supported and which -@@ -2849,16 +3608,19 @@ +@@ -2849,16 +3617,19 @@ && rs6000_cpu != PROCESSOR_POWER5 && rs6000_cpu != PROCESSOR_POWER6 && rs6000_cpu != PROCESSOR_POWER7 @@ -56215,7 +58203,7 @@ Index: gcc/config/rs6000/rs6000.c || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64 || rs6000_cpu == PROCESSOR_PPCE5500 -@@ -2988,7 +3750,7 @@ +@@ -2988,7 +3759,7 @@ /* We should always be splitting complex arguments, but we can't break Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */ @@ -56224,7 +58212,7 @@ Index: gcc/config/rs6000/rs6000.c targetm.calls.split_complex_arg = NULL; } -@@ -3102,6 +3864,10 @@ +@@ -3102,6 +3873,10 @@ rs6000_cost = &power7_cost; break; @@ -56235,7 +58223,7 @@ Index: gcc/config/rs6000/rs6000.c case PROCESSOR_PPCA2: rs6000_cost = &ppca2_cost; break; -@@ -3274,7 +4040,8 @@ +@@ -3274,7 +4049,8 @@ && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5 || rs6000_cpu == PROCESSOR_POWER6 @@ -56245,7 +58233,7 @@ Index: gcc/config/rs6000/rs6000.c return 5; else return align_loops_log; -@@ -3493,6 +4260,8 @@ +@@ -3493,6 +4269,8 @@ { case SFmode: return V4SFmode; @@ -56254,7 +58242,7 @@ Index: gcc/config/rs6000/rs6000.c case DImode: return V2DImode; case SImode: -@@ -3813,6 +4582,22 @@ +@@ -3813,6 +4591,22 @@ enum built_in_function fn = DECL_FUNCTION_CODE (fndecl); switch (fn) { @@ -56277,7 +58265,7 @@ Index: gcc/config/rs6000/rs6000.c case BUILT_IN_COPYSIGN: if (VECTOR_UNIT_VSX_P (V2DFmode) && out_mode == DFmode && out_n == 2 -@@ -3828,6 +4613,22 @@ +@@ -3828,6 +4622,22 @@ if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)) return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF]; break; @@ -56300,7 +58288,7 @@ Index: gcc/config/rs6000/rs6000.c case BUILT_IN_SQRT: if (VECTOR_UNIT_VSX_P (V2DFmode) && out_mode == DFmode && out_n == 2 -@@ -4043,7 +4844,11 @@ +@@ -4043,7 +4853,11 @@ putc ('\n', file); } @@ -56313,7 +58301,7 @@ Index: gcc/config/rs6000/rs6000.c { switch_to_section (toc_section); switch_to_section (text_section); -@@ -4230,7 +5035,7 @@ +@@ -4230,7 +5044,7 @@ HOST_WIDE_INT splat_val; HOST_WIDE_INT msb_val; @@ -56322,7 +58310,7 @@ Index: gcc/config/rs6000/rs6000.c return false; nunits = GET_MODE_NUNITS (mode); -@@ -4239,7 +5044,7 @@ +@@ -4239,7 +5053,7 @@ val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0); splat_val = val; @@ -56331,7 +58319,7 @@ Index: gcc/config/rs6000/rs6000.c /* Construct the value to be splatted, if possible. If not, return 0. */ for (i = 2; i <= copies; i *= 2) -@@ -4274,15 +5079,16 @@ +@@ -4274,15 +5088,16 @@ /* Check if VAL is present in every STEP-th element, and the other elements are filled with its most significant bit. */ @@ -56351,7 +58339,7 @@ Index: gcc/config/rs6000/rs6000.c return false; } -@@ -4308,7 +5114,7 @@ +@@ -4308,7 +5123,7 @@ if (mode == V2DFmode) return zero_constant (op, mode); @@ -56360,7 +58348,7 @@ Index: gcc/config/rs6000/rs6000.c { /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not easy. */ -@@ -4326,6 +5132,10 @@ +@@ -4326,6 +5141,10 @@ return false; } @@ -56371,7 +58359,7 @@ Index: gcc/config/rs6000/rs6000.c /* Start with a vspltisw. */ step = GET_MODE_NUNITS (mode) / 4; copies = 1; -@@ -4407,7 +5217,7 @@ +@@ -4407,7 +5226,7 @@ if (zero_constant (vec, mode)) return "xxlxor %x0,%x0,%x0"; @@ -56380,7 +58368,7 @@ Index: gcc/config/rs6000/rs6000.c && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1 && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1) return "vspltisw %0,-1"; -@@ -4698,9 +5508,12 @@ +@@ -4698,9 +5517,12 @@ { rtx freg = gen_reg_rtx (V4SFmode); rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0)); @@ -56395,7 +58383,7 @@ Index: gcc/config/rs6000/rs6000.c } else { -@@ -4790,6 +5603,13 @@ +@@ -4790,6 +5612,13 @@ return; } @@ -56409,7 +58397,7 @@ Index: gcc/config/rs6000/rs6000.c /* Load single variable value. */ mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode)); emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val); -@@ -4811,10 +5631,29 @@ +@@ -4811,10 +5640,29 @@ XVECEXP (mask, 0, elt*width + i) = GEN_INT (i + 0x10); x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0)); @@ -56443,7 +58431,7 @@ Index: gcc/config/rs6000/rs6000.c emit_insn (gen_rtx_SET (VOIDmode, target, x)); } -@@ -4833,6 +5672,10 @@ +@@ -4833,6 +5681,10 @@ { default: break; @@ -56454,7 +58442,7 @@ Index: gcc/config/rs6000/rs6000.c case V2DFmode: emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt))); return; -@@ -4938,7 +5781,7 @@ +@@ -4938,7 +5790,7 @@ purpose. */ if (GET_CODE (op) == SUBREG && (mode == SImode || mode == DImode || mode == TImode @@ -56463,7 +58451,7 @@ Index: gcc/config/rs6000/rs6000.c && REG_P (SUBREG_REG (op)) && (GET_MODE (SUBREG_REG (op)) == DFmode || GET_MODE (SUBREG_REG (op)) == TFmode)) -@@ -4951,6 +5794,7 @@ +@@ -4951,6 +5803,7 @@ && REG_P (SUBREG_REG (op)) && (GET_MODE (SUBREG_REG (op)) == DImode || GET_MODE (SUBREG_REG (op)) == TImode @@ -56471,7 +58459,7 @@ Index: gcc/config/rs6000/rs6000.c || GET_MODE (SUBREG_REG (op)) == DDmode || GET_MODE (SUBREG_REG (op)) == TDmode)) return true; -@@ -4966,6 +5810,48 @@ +@@ -4966,6 +5819,48 @@ return false; } @@ -56520,7 +58508,7 @@ Index: gcc/config/rs6000/rs6000.c /* AIX increases natural record alignment to doubleword if the first field is an FP double while the FP fields remain word aligned. */ -@@ -5087,6 +5973,73 @@ +@@ -5087,6 +5982,73 @@ || (REG_P (op1) && INT_REGNO_P (REGNO (op1)))); } @@ -56594,7 +58582,7 @@ Index: gcc/config/rs6000/rs6000.c /* Given an address, return a constant offset term if one exists. */ static rtx -@@ -5170,7 +6123,12 @@ +@@ -5170,7 +6132,12 @@ case V4SImode: case V2DFmode: case V2DImode: @@ -56608,7 +58596,7 @@ Index: gcc/config/rs6000/rs6000.c if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)) return false; break; -@@ -5184,6 +6142,13 @@ +@@ -5184,6 +6151,13 @@ return false; break; @@ -56622,7 +58610,7 @@ Index: gcc/config/rs6000/rs6000.c default: break; } -@@ -5211,8 +6176,8 @@ +@@ -5211,8 +6185,8 @@ && regnum <= LAST_VIRTUAL_POINTER_REGISTER); } @@ -56633,7 +58621,7 @@ Index: gcc/config/rs6000/rs6000.c static bool offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset, -@@ -5219,15 +6184,16 @@ +@@ -5219,15 +6193,16 @@ enum machine_mode mode) { tree decl, type; @@ -56652,7 +58640,7 @@ Index: gcc/config/rs6000/rs6000.c return false; /* -fsection-anchors loses the original SYMBOL_REF_DECL when -@@ -5234,68 +6200,78 @@ +@@ -5234,68 +6209,78 @@ replacing memory addresses with an anchor plus offset. We could find the decl by rummaging around in the block->objects VEC for the given offset but that seems like too much work. */ @@ -56773,7 +58761,7 @@ Index: gcc/config/rs6000/rs6000.c return dalign >= dsize; } -@@ -5387,7 +6363,7 @@ +@@ -5387,7 +6372,7 @@ return false; if (!reg_offset_addressing_ok_p (mode)) return virtual_stack_registers_memory_p (x); @@ -56782,7 +58770,7 @@ Index: gcc/config/rs6000/rs6000.c return true; if (GET_CODE (XEXP (x, 1)) != CONST_INT) return false; -@@ -5416,7 +6392,7 @@ +@@ -5416,7 +6401,7 @@ /* If we are using VSX scalar loads, restrict ourselves to reg+reg addressing. */ @@ -56791,7 +58779,7 @@ Index: gcc/config/rs6000/rs6000.c return false; if (!worst_case) -@@ -5428,12 +6404,14 @@ +@@ -5428,12 +6413,14 @@ break; case TFmode: @@ -56808,7 +58796,7 @@ Index: gcc/config/rs6000/rs6000.c extra = 8; if (!worst_case) break; -@@ -5526,9 +6504,21 @@ +@@ -5526,9 +6513,21 @@ if (TARGET_ELF || TARGET_MACHO) { @@ -56832,7 +58820,7 @@ Index: gcc/config/rs6000/rs6000.c return false; if (GET_MODE_NUNITS (mode) != 1) return false; -@@ -5538,7 +6528,7 @@ +@@ -5538,7 +6537,7 @@ && (mode == DFmode || mode == DDmode))) return false; @@ -56841,7 +58829,7 @@ Index: gcc/config/rs6000/rs6000.c } return false; -@@ -5582,8 +6572,11 @@ +@@ -5582,8 +6581,11 @@ if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx) return force_reg (Pmode, XEXP (x, 0)); @@ -56854,7 +58842,7 @@ Index: gcc/config/rs6000/rs6000.c return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)), force_reg (Pmode, XEXP (x, 1))); -@@ -5603,11 +6596,12 @@ +@@ -5603,11 +6605,12 @@ case TFmode: case TDmode: case TImode: @@ -56868,7 +58856,7 @@ Index: gcc/config/rs6000/rs6000.c extra = 8; break; default: -@@ -6099,10 +7093,13 @@ +@@ -6099,10 +7102,13 @@ 1, const0_rtx, Pmode); r3 = gen_rtx_REG (Pmode, 3); @@ -56886,7 +58874,7 @@ Index: gcc/config/rs6000/rs6000.c else if (DEFAULT_ABI == ABI_V4) insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx); else -@@ -6121,10 +7118,13 @@ +@@ -6121,10 +7127,13 @@ 1, const0_rtx, Pmode); r3 = gen_rtx_REG (Pmode, 3); @@ -56904,7 +58892,7 @@ Index: gcc/config/rs6000/rs6000.c else if (DEFAULT_ABI == ABI_V4) insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx); else -@@ -6239,7 +7239,6 @@ +@@ -6239,7 +7248,6 @@ && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym), get_pool_mode (sym))) || (TARGET_CMODEL == CMODEL_MEDIUM @@ -56912,7 +58900,7 @@ Index: gcc/config/rs6000/rs6000.c && SYMBOL_REF_LOCAL_P (sym))); } -@@ -6338,7 +7337,7 @@ +@@ -6338,7 +7346,7 @@ && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode || mode == DImode)) @@ -56921,7 +58909,7 @@ Index: gcc/config/rs6000/rs6000.c { HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; -@@ -6369,7 +7368,7 @@ +@@ -6369,7 +7377,7 @@ if (GET_CODE (x) == SYMBOL_REF && reg_offset_p @@ -56930,7 +58918,7 @@ Index: gcc/config/rs6000/rs6000.c && !SPE_VECTOR_MODE (mode) #if TARGET_MACHO && DEFAULT_ABI == ABI_DARWIN -@@ -6395,6 +7394,8 @@ +@@ -6395,6 +7403,8 @@ mem is sufficiently aligned. */ && mode != TFmode && mode != TDmode @@ -56939,7 +58927,7 @@ Index: gcc/config/rs6000/rs6000.c && (mode != DImode || TARGET_POWERPC64) && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64 || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT))) -@@ -6515,15 +7516,9 @@ +@@ -6515,15 +7525,9 @@ return 0; if (legitimate_indirect_address_p (x, reg_ok_strict)) return 1; @@ -56958,7 +58946,7 @@ Index: gcc/config/rs6000/rs6000.c && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)) return 1; if (virtual_stack_registers_memory_p (x)) -@@ -6531,8 +7526,16 @@ +@@ -6531,8 +7535,16 @@ if (reg_offset_p && legitimate_small_data_p (mode, x)) return 1; if (reg_offset_p @@ -56976,7 +58964,7 @@ Index: gcc/config/rs6000/rs6000.c /* If not REG_OK_STRICT (before reload) let pass any stack offset. */ if (! reg_ok_strict && reg_offset_p -@@ -6544,8 +7547,7 @@ +@@ -6544,8 +7556,7 @@ return 1; if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false)) return 1; @@ -56986,7 +58974,7 @@ Index: gcc/config/rs6000/rs6000.c && mode != TDmode && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_POWERPC64 -@@ -6552,23 +7554,13 @@ +@@ -6552,23 +7563,13 @@ || (mode != DFmode && mode != DDmode) || (TARGET_E500_DOUBLE && mode != DDmode)) && (TARGET_POWERPC64 || mode != DImode) @@ -57014,7 +59002,7 @@ Index: gcc/config/rs6000/rs6000.c && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict) && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict, false) -@@ -6589,10 +7581,13 @@ +@@ -6589,10 +7590,13 @@ bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict); fprintf (stderr, "\nrs6000_legitimate_address_p: return = %s, mode = %s, " @@ -57029,7 +59017,7 @@ Index: gcc/config/rs6000/rs6000.c GET_RTX_NAME (GET_CODE (x))); debug_rtx (x); -@@ -6758,7 +7753,7 @@ +@@ -6758,7 +7762,7 @@ /* The TOC register is not killed across calls in a way that is visible to the compiler. */ @@ -57038,7 +59026,7 @@ Index: gcc/config/rs6000/rs6000.c call_really_used_regs[2] = 0; if (DEFAULT_ABI == ABI_V4 -@@ -6818,6 +7813,7 @@ +@@ -6818,6 +7822,7 @@ fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; } } @@ -57046,7 +59034,7 @@ Index: gcc/config/rs6000/rs6000.c /* Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns. Do all computations in MODE. -@@ -7006,7 +8002,7 @@ +@@ -7006,7 +8011,7 @@ } /* Helper for the following. Get rid of [r+r] memory refs @@ -57055,7 +59043,7 @@ Index: gcc/config/rs6000/rs6000.c static void rs6000_eliminate_indexed_memrefs (rtx operands[2]) -@@ -7031,6 +8027,131 @@ +@@ -7031,6 +8036,131 @@ copy_addr_to_reg (XEXP (operands[1], 0))); } @@ -57187,7 +59175,7 @@ Index: gcc/config/rs6000/rs6000.c /* Emit a move from SOURCE to DEST in mode MODE. */ void rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode) -@@ -7149,8 +8270,71 @@ +@@ -7149,8 +8279,71 @@ cfun->machine->sdmode_stack_slot = eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX); @@ -57259,7 +59247,7 @@ Index: gcc/config/rs6000/rs6000.c && MEM_P (operands[0]) && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot) && REG_P (operands[1])) -@@ -7163,7 +8347,9 @@ +@@ -7163,7 +8356,9 @@ } else if (INT_REGNO_P (REGNO (operands[1]))) { @@ -57270,7 +59258,7 @@ Index: gcc/config/rs6000/rs6000.c mem = eliminate_regs (mem, VOIDmode, NULL_RTX); emit_insn (gen_movsd_hardfloat (mem, operands[1])); } -@@ -7175,6 +8361,7 @@ +@@ -7175,6 +8370,7 @@ && mode == SDmode && REG_P (operands[0]) && MEM_P (operands[1]) @@ -57278,7 +59266,7 @@ Index: gcc/config/rs6000/rs6000.c && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot)) { if (FP_REGNO_P (REGNO (operands[0]))) -@@ -7185,7 +8372,9 @@ +@@ -7185,7 +8381,9 @@ } else if (INT_REGNO_P (REGNO (operands[0]))) { @@ -57289,7 +59277,7 @@ Index: gcc/config/rs6000/rs6000.c mem = eliminate_regs (mem, VOIDmode, NULL_RTX); emit_insn (gen_movsd_hardfloat (operands[0], mem)); } -@@ -7230,6 +8419,7 @@ +@@ -7230,6 +8428,7 @@ case V1DImode: case V2DFmode: case V2DImode: @@ -57297,7 +59285,7 @@ Index: gcc/config/rs6000/rs6000.c if (CONSTANT_P (operands[1]) && !easy_vector_constant (operands[1], mode)) operands[1] = force_const_mem (mode, operands[1]); -@@ -7388,6 +8578,11 @@ +@@ -7388,6 +8587,11 @@ break; case TImode: @@ -57309,7 +59297,7 @@ Index: gcc/config/rs6000/rs6000.c rs6000_eliminate_indexed_memrefs (operands); break; -@@ -7426,18 +8621,231 @@ +@@ -7426,18 +8630,231 @@ } /* Nonzero if we can use a floating-point register to pass this arg. */ @@ -57543,7 +59531,7 @@ Index: gcc/config/rs6000/rs6000.c /* Return a nonzero value to say to return the function value in memory, just as large structures are always returned. TYPE will be the data type of the value, and FNTYPE will be the type of the -@@ -7490,6 +8898,16 @@ +@@ -7490,6 +8907,16 @@ /* Otherwise fall through to more conventional ABI rules. */ } @@ -57560,7 +59548,7 @@ Index: gcc/config/rs6000/rs6000.c if (AGGREGATE_TYPE_P (type) && (aix_struct_return || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)) -@@ -7521,6 +8939,19 @@ +@@ -7521,6 +8948,19 @@ return false; } @@ -57580,7 +59568,7 @@ Index: gcc/config/rs6000/rs6000.c #ifdef HAVE_AS_GNU_ATTRIBUTE /* Return TRUE if a call to function FNDECL may be one that potentially affects the function calling ABI of the object file. */ -@@ -7657,7 +9088,7 @@ +@@ -7657,7 +9097,7 @@ static bool rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type) { @@ -57589,7 +59577,7 @@ Index: gcc/config/rs6000/rs6000.c return must_pass_in_stack_var_size (mode, type); else return must_pass_in_stack_var_size_or_pad (mode, type); -@@ -7738,6 +9169,11 @@ +@@ -7738,6 +9178,11 @@ static unsigned int rs6000_function_arg_boundary (enum machine_mode mode, const_tree type) { @@ -57601,7 +59589,7 @@ Index: gcc/config/rs6000/rs6000.c if (DEFAULT_ABI == ABI_V4 && (GET_MODE_SIZE (mode) == 8 || (TARGET_HARD_FLOAT -@@ -7749,12 +9185,13 @@ +@@ -7749,12 +9194,13 @@ && int_size_in_bytes (type) >= 8 && int_size_in_bytes (type) < 16)) return 64; @@ -57618,7 +59606,7 @@ Index: gcc/config/rs6000/rs6000.c && mode == BLKmode && type && TYPE_ALIGN (type) > 64) return 128; -@@ -7762,6 +9199,16 @@ +@@ -7762,6 +9208,16 @@ return PARM_BOUNDARY; } @@ -57635,7 +59623,7 @@ Index: gcc/config/rs6000/rs6000.c /* For a function parm of MODE and TYPE, return the starting word in the parameter area. NWORDS of the parameter area are already used. */ -@@ -7770,11 +9217,9 @@ +@@ -7770,11 +9226,9 @@ unsigned int nwords) { unsigned int align; @@ -57648,7 +59636,7 @@ Index: gcc/config/rs6000/rs6000.c } /* Compute the size (in words) of a function argument. */ -@@ -7881,7 +9326,7 @@ +@@ -7881,7 +9335,7 @@ if (TREE_CODE (ftype) == RECORD_TYPE) rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos); @@ -57657,7 +59645,7 @@ Index: gcc/config/rs6000/rs6000.c { unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3; rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0); -@@ -7922,7 +9367,7 @@ +@@ -7922,7 +9376,7 @@ else cum->words += n_fpregs; } @@ -57666,7 +59654,7 @@ Index: gcc/config/rs6000/rs6000.c { rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0); cum->vregno++; -@@ -7959,6 +9404,11 @@ +@@ -7959,6 +9413,11 @@ rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode, const_tree type, bool named, int depth) { @@ -57678,7 +59666,7 @@ Index: gcc/config/rs6000/rs6000.c /* Only tick off an argument if we're not recursing. */ if (depth == 0) cum->nargs_prototype--; -@@ -7979,15 +9429,16 @@ +@@ -7979,15 +9438,16 @@ #endif if (TARGET_ALTIVEC_ABI @@ -57698,7 +59686,7 @@ Index: gcc/config/rs6000/rs6000.c if (!TARGET_ALTIVEC) error ("cannot pass argument in vector register because" " altivec instructions are disabled, use -maltivec" -@@ -7996,7 +9447,8 @@ +@@ -7996,7 +9456,8 @@ /* PowerPC64 Linux and AIX allocate GPRs for a vector argument even if it is going to be passed in a vector register. Darwin does the same for variable-argument functions. */ @@ -57708,7 +59696,7 @@ Index: gcc/config/rs6000/rs6000.c || (cum->stdarg && DEFAULT_ABI != ABI_V4)) stack = true; } -@@ -8007,15 +9459,13 @@ +@@ -8007,15 +9468,13 @@ { int align; @@ -57730,7 +59718,7 @@ Index: gcc/config/rs6000/rs6000.c else align = cum->words & 1; cum->words += align + rs6000_arg_size (mode, type); -@@ -8140,15 +9590,15 @@ +@@ -8140,15 +9599,15 @@ cum->words = align_words + n_words; @@ -57749,7 +59737,7 @@ Index: gcc/config/rs6000/rs6000.c } if (TARGET_DEBUG_ARG) -@@ -8358,7 +9808,7 @@ +@@ -8358,7 +9817,7 @@ if (TREE_CODE (ftype) == RECORD_TYPE) rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k); @@ -57758,7 +59746,7 @@ Index: gcc/config/rs6000/rs6000.c { unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3; #if 0 -@@ -8386,7 +9836,7 @@ +@@ -8386,7 +9845,7 @@ if (mode == TFmode || mode == TDmode) cum->fregno++; } @@ -57767,7 +59755,7 @@ Index: gcc/config/rs6000/rs6000.c { rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k); rvec[(*k)++] -@@ -8503,6 +9953,84 @@ +@@ -8503,6 +9962,84 @@ return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec)); } @@ -57852,7 +59840,7 @@ Index: gcc/config/rs6000/rs6000.c /* Determine where to put an argument to a function. Value is zero to push the argument on the stack, or a hard register in which to store the argument. -@@ -8537,6 +10065,8 @@ +@@ -8537,6 +10074,8 @@ { CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); enum rs6000_abi abi = DEFAULT_ABI; @@ -57861,7 +59849,7 @@ Index: gcc/config/rs6000/rs6000.c /* Return a marker to indicate whether CR1 needs to set or clear the bit that V.4 uses to say fp args were passed in registers. -@@ -8563,6 +10093,8 @@ +@@ -8563,6 +10102,8 @@ return GEN_INT (cum->call_cookie & ~CALL_LIBCALL); } @@ -57870,7 +59858,7 @@ Index: gcc/config/rs6000/rs6000.c if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type)) { rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false); -@@ -8571,33 +10103,30 @@ +@@ -8571,33 +10112,30 @@ /* Else fall through to usual handling. */ } @@ -57927,7 +59915,7 @@ Index: gcc/config/rs6000/rs6000.c else if (TARGET_ALTIVEC_ABI && (ALTIVEC_OR_VSX_VECTOR_MODE (mode) || (type && TREE_CODE (type) == VECTOR_TYPE -@@ -8612,13 +10141,13 @@ +@@ -8612,13 +10150,13 @@ int align, align_words, n_words; enum machine_mode part_mode; @@ -57947,7 +59935,7 @@ Index: gcc/config/rs6000/rs6000.c else align = cum->words & 1; align_words = cum->words + align; -@@ -8696,92 +10225,44 @@ +@@ -8696,92 +10234,44 @@ /* _Decimal128 must be passed in an even/odd float register pair. This assumes that the register number is odd when fregno is odd. */ @@ -58068,7 +60056,7 @@ Index: gcc/config/rs6000/rs6000.c } else if (align_words < GP_ARG_NUM_REG) { -@@ -8788,9 +10269,6 @@ +@@ -8788,9 +10278,6 @@ if (TARGET_32BIT && TARGET_POWERPC64) return rs6000_mixed_function_arg (mode, type, align_words); @@ -58078,7 +60066,7 @@ Index: gcc/config/rs6000/rs6000.c return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words); } else -@@ -8809,16 +10287,32 @@ +@@ -8809,16 +10296,32 @@ tree type, bool named) { CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); @@ -58114,7 +60102,7 @@ Index: gcc/config/rs6000/rs6000.c /* In this complicated case we just disable the partial_nregs code. */ if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type)) return 0; -@@ -8825,26 +10319,30 @@ +@@ -8825,26 +10328,30 @@ align_words = rs6000_parm_start (mode, type, cum->words); @@ -58156,7 +60144,7 @@ Index: gcc/config/rs6000/rs6000.c && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type)) ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8); -@@ -8925,6 +10423,139 @@ +@@ -8925,6 +10432,139 @@ return 0; } @@ -58296,7 +60284,7 @@ Index: gcc/config/rs6000/rs6000.c static void rs6000_move_block_from_reg (int regno, rtx x, int nregs) { -@@ -9306,8 +10937,10 @@ +@@ -9306,8 +10946,10 @@ We don't need to check for pass-by-reference because of the test above. We can return a simplifed answer, since we know there's no offset to add. */ @@ -58309,7 +60297,7 @@ Index: gcc/config/rs6000/rs6000.c && integer_zerop (TYPE_SIZE (type))) { unsigned HOST_WIDE_INT align, boundary; -@@ -9602,6 +11235,7 @@ +@@ -9602,6 +11244,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -58317,7 +60305,7 @@ Index: gcc/config/rs6000/rs6000.c #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9615,6 +11249,7 @@ +@@ -9615,6 +11258,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -58325,7 +60313,7 @@ Index: gcc/config/rs6000/rs6000.c #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9633,6 +11268,7 @@ +@@ -9633,6 +11277,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -58333,7 +60321,7 @@ Index: gcc/config/rs6000/rs6000.c #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9646,6 +11282,7 @@ +@@ -9646,6 +11291,7 @@ { MASK, ICODE, NAME, ENUM }, #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -58341,7 +60329,7 @@ Index: gcc/config/rs6000/rs6000.c #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9664,6 +11301,7 @@ +@@ -9664,6 +11310,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -58349,7 +60337,7 @@ Index: gcc/config/rs6000/rs6000.c #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9677,6 +11315,7 @@ +@@ -9677,6 +11324,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -58357,7 +60345,7 @@ Index: gcc/config/rs6000/rs6000.c #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9693,6 +11332,7 @@ +@@ -9693,6 +11341,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -58365,7 +60353,7 @@ Index: gcc/config/rs6000/rs6000.c #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9704,6 +11344,7 @@ +@@ -9704,6 +11353,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -58373,7 +60361,7 @@ Index: gcc/config/rs6000/rs6000.c #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, -@@ -9725,6 +11366,7 @@ +@@ -9725,6 +11375,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -58381,7 +60369,7 @@ Index: gcc/config/rs6000/rs6000.c #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9736,6 +11378,7 @@ +@@ -9736,6 +11387,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -58389,7 +60377,7 @@ Index: gcc/config/rs6000/rs6000.c #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \ -@@ -9755,6 +11398,7 @@ +@@ -9755,6 +11407,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -58397,7 +60385,7 @@ Index: gcc/config/rs6000/rs6000.c #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9768,6 +11412,7 @@ +@@ -9768,6 +11421,7 @@ #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, @@ -58405,7 +60393,7 @@ Index: gcc/config/rs6000/rs6000.c #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9785,6 +11430,7 @@ +@@ -9785,6 +11439,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -58413,7 +60401,7 @@ Index: gcc/config/rs6000/rs6000.c #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9796,6 +11442,7 @@ +@@ -9796,6 +11451,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -58421,7 +60409,7 @@ Index: gcc/config/rs6000/rs6000.c #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \ { MASK, ICODE, NAME, ENUM }, -@@ -9816,6 +11463,7 @@ +@@ -9816,6 +11472,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -58429,7 +60417,7 @@ Index: gcc/config/rs6000/rs6000.c #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9829,6 +11477,7 @@ +@@ -9829,6 +11486,7 @@ #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -58437,7 +60425,7 @@ Index: gcc/config/rs6000/rs6000.c #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9846,8 +11495,9 @@ +@@ -9846,8 +11504,9 @@ #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 #undef RS6000_BUILTIN_A @@ -58448,7 +60436,7 @@ Index: gcc/config/rs6000/rs6000.c #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -9861,6 +11511,7 @@ +@@ -9861,6 +11520,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) @@ -58456,7 +60444,7 @@ Index: gcc/config/rs6000/rs6000.c #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) -@@ -9871,6 +11522,7 @@ +@@ -9871,6 +11531,7 @@ #include "rs6000-builtin.def" }; @@ -58464,7 +60452,7 @@ Index: gcc/config/rs6000/rs6000.c #undef RS6000_BUILTIN_1 #undef RS6000_BUILTIN_2 #undef RS6000_BUILTIN_3 -@@ -9877,11 +11529,42 @@ +@@ -9877,11 +11538,42 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -58507,7 +60495,7 @@ Index: gcc/config/rs6000/rs6000.c /* Return true if a builtin function is overloaded. */ bool rs6000_overloaded_builtin_p (enum rs6000_builtins fncode) -@@ -10189,7 +11872,101 @@ +@@ -10189,7 +11881,101 @@ return target; } @@ -58609,7 +60597,7 @@ Index: gcc/config/rs6000/rs6000.c altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk) { rtx pat, addr; -@@ -10351,7 +12128,198 @@ +@@ -10351,7 +12137,198 @@ return NULL_RTX; } @@ -58808,10 +60796,65 @@ Index: gcc/config/rs6000/rs6000.c rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target) { rtx pat; -@@ -10427,7 +12395,28 @@ +@@ -10416,7 +12393,15 @@ + } + } + else if (icode == CODE_FOR_vsx_set_v2df +- || icode == CODE_FOR_vsx_set_v2di) ++ || icode == CODE_FOR_vsx_set_v2di ++ || icode == CODE_FOR_bcdadd ++ || icode == CODE_FOR_bcdadd_lt ++ || icode == CODE_FOR_bcdadd_eq ++ || icode == CODE_FOR_bcdadd_gt ++ || icode == CODE_FOR_bcdsub ++ || icode == CODE_FOR_bcdsub_lt ++ || icode == CODE_FOR_bcdsub_eq ++ || icode == CODE_FOR_bcdsub_gt) + { + /* Only allow 1-bit unsigned literals. */ + STRIP_NOPS (arg2); +@@ -10427,7 +12412,66 @@ return const0_rtx; } } ++ else if (icode == CODE_FOR_dfp_ddedpd_dd ++ || icode == CODE_FOR_dfp_ddedpd_td) ++ { ++ /* Only allow 2-bit unsigned literals where the value is 0 or 2. */ ++ STRIP_NOPS (arg0); ++ if (TREE_CODE (arg0) != INTEGER_CST ++ || TREE_INT_CST_LOW (arg2) & ~0x3) ++ { ++ error ("argument 1 must be 0 or 2"); ++ return const0_rtx; ++ } ++ } ++ else if (icode == CODE_FOR_dfp_denbcd_dd ++ || icode == CODE_FOR_dfp_denbcd_td) ++ { ++ /* Only allow 1-bit unsigned literals. */ ++ STRIP_NOPS (arg0); ++ if (TREE_CODE (arg0) != INTEGER_CST ++ || TREE_INT_CST_LOW (arg0) & ~0x1) ++ { ++ error ("argument 1 must be a 1-bit unsigned literal"); ++ return const0_rtx; ++ } ++ } ++ else if (icode == CODE_FOR_dfp_dscli_dd ++ || icode == CODE_FOR_dfp_dscli_td ++ || icode == CODE_FOR_dfp_dscri_dd ++ || icode == CODE_FOR_dfp_dscri_td) ++ { ++ /* Only allow 6-bit unsigned literals. */ ++ STRIP_NOPS (arg1); ++ if (TREE_CODE (arg1) != INTEGER_CST ++ || TREE_INT_CST_LOW (arg1) & ~0x3f) ++ { ++ error ("argument 2 must be a 6-bit unsigned literal"); ++ return const0_rtx; ++ } ++ } + else if (icode == CODE_FOR_crypto_vshasigmaw + || icode == CODE_FOR_crypto_vshasigmad) + { @@ -58837,7 +60880,7 @@ Index: gcc/config/rs6000/rs6000.c if (target == 0 || GET_MODE (target) != tmode || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) -@@ -10481,6 +12470,8 @@ +@@ -10481,6 +12525,8 @@ break; case ALTIVEC_BUILTIN_LD_INTERNAL_2di: icode = CODE_FOR_vector_altivec_load_v2di; @@ -58846,7 +60889,7 @@ Index: gcc/config/rs6000/rs6000.c break; default: *expandedp = false; -@@ -10540,6 +12531,8 @@ +@@ -10540,6 +12586,8 @@ break; case ALTIVEC_BUILTIN_ST_INTERNAL_2di: icode = CODE_FOR_vector_altivec_store_v2di; @@ -58855,7 +60898,7 @@ Index: gcc/config/rs6000/rs6000.c break; default: *expandedp = false; -@@ -10632,21 +12625,33 @@ +@@ -10632,21 +12680,33 @@ enum machine_mode tmode = TYPE_MODE (type); enum machine_mode inner_mode = GET_MODE_INNER (tmode); int i, n_elt = GET_MODE_NUNITS (tmode); @@ -58896,7 +60939,7 @@ Index: gcc/config/rs6000/rs6000.c return target; } -@@ -10769,8 +12774,19 @@ +@@ -10769,8 +12829,19 @@ switch (fcode) { @@ -58916,7 +60959,7 @@ Index: gcc/config/rs6000/rs6000.c case ALTIVEC_BUILTIN_STVEBX: return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp); case ALTIVEC_BUILTIN_STVEHX: -@@ -10777,8 +12793,19 @@ +@@ -10777,8 +12848,19 @@ return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp); case ALTIVEC_BUILTIN_STVEWX: return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp); @@ -58937,7 +60980,7 @@ Index: gcc/config/rs6000/rs6000.c case ALTIVEC_BUILTIN_STVLX: return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp); -@@ -10789,6 +12816,8 @@ +@@ -10789,6 +12871,8 @@ case ALTIVEC_BUILTIN_STVRXL: return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp); @@ -58946,7 +60989,7 @@ Index: gcc/config/rs6000/rs6000.c case VSX_BUILTIN_STXVD2X_V2DF: return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp); case VSX_BUILTIN_STXVD2X_V2DI: -@@ -10869,6 +12898,7 @@ +@@ -10869,6 +12953,7 @@ case ALTIVEC_BUILTIN_VEC_INIT_V4SF: case VSX_BUILTIN_VEC_INIT_V2DF: case VSX_BUILTIN_VEC_INIT_V2DI: @@ -58954,7 +60997,7 @@ Index: gcc/config/rs6000/rs6000.c return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target); case ALTIVEC_BUILTIN_VEC_SET_V4SI: -@@ -10877,6 +12907,7 @@ +@@ -10877,6 +12962,7 @@ case ALTIVEC_BUILTIN_VEC_SET_V4SF: case VSX_BUILTIN_VEC_SET_V2DF: case VSX_BUILTIN_VEC_SET_V2DI: @@ -58962,7 +61005,7 @@ Index: gcc/config/rs6000/rs6000.c return altivec_expand_vec_set_builtin (exp); case ALTIVEC_BUILTIN_VEC_EXT_V4SI: -@@ -10885,6 +12916,7 @@ +@@ -10885,6 +12971,7 @@ case ALTIVEC_BUILTIN_VEC_EXT_V4SF: case VSX_BUILTIN_VEC_EXT_V2DF: case VSX_BUILTIN_VEC_EXT_V2DI: @@ -58970,7 +61013,7 @@ Index: gcc/config/rs6000/rs6000.c return altivec_expand_vec_ext_builtin (exp, target); default: -@@ -10922,12 +12954,44 @@ +@@ -10922,12 +13009,44 @@ case ALTIVEC_BUILTIN_LVEWX: return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx, exp, target, false); @@ -59016,7 +61059,7 @@ Index: gcc/config/rs6000/rs6000.c case ALTIVEC_BUILTIN_LVLX: return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx, exp, target, true); -@@ -10940,6 +13004,9 @@ +@@ -10940,6 +13059,9 @@ case ALTIVEC_BUILTIN_LVRXL: return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl, exp, target, true); @@ -59026,7 +61069,7 @@ Index: gcc/config/rs6000/rs6000.c case VSX_BUILTIN_LXVD2X_V2DF: return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df, exp, target, false); -@@ -11411,6 +13478,8 @@ +@@ -11411,6 +13533,8 @@ error ("Builtin function %s is only valid for the cell processor", name); else if ((fnmask & RS6000_BTM_VSX) != 0) error ("Builtin function %s requires the -mvsx option", name); @@ -59035,7 +61078,24 @@ Index: gcc/config/rs6000/rs6000.c else if ((fnmask & RS6000_BTM_ALTIVEC) != 0) error ("Builtin function %s requires the -maltivec option", name); else if ((fnmask & RS6000_BTM_PAIRED) != 0) -@@ -11515,7 +13584,8 @@ +@@ -11417,6 +13541,16 @@ + error ("Builtin function %s requires the -mpaired option", name); + else if ((fnmask & RS6000_BTM_SPE) != 0) + error ("Builtin function %s requires the -mspe option", name); ++ else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR)) ++ == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR)) ++ error ("Builtin function %s requires the -mhard-dfp and" ++ "-mpower8-vector options", name); ++ else if ((fnmask & RS6000_BTM_DFP) != 0) ++ error ("Builtin function %s requires the -mhard-dfp option", name); ++ else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0) ++ error ("Builtin function %s requires the -mpower8-vector option", name); ++ else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0) ++ error ("Builtin function %s requires the -mhard-float option", name); + else + error ("Builtin function %s is not supported with the current options", + name); +@@ -11515,7 +13649,8 @@ case ALTIVEC_BUILTIN_MASK_FOR_LOAD: case ALTIVEC_BUILTIN_MASK_FOR_STORE: { @@ -59045,7 +61105,7 @@ Index: gcc/config/rs6000/rs6000.c enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode = insn_data[icode].operand[1].mode; tree arg; -@@ -11590,7 +13660,14 @@ +@@ -11590,9 +13725,19 @@ if (success) return ret; } @@ -59053,14 +61113,20 @@ Index: gcc/config/rs6000/rs6000.c + { + ret = htm_expand_builtin (exp, target, &success); +- gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT); + if (success) + return ret; + } -+ - gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT); ++ unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK; ++ gcc_assert (attr == RS6000_BTC_UNARY ++ || attr == RS6000_BTC_BINARY ++ || attr == RS6000_BTC_TERNARY); ++ /* Handle simple unary operations. */ -@@ -11648,6 +13725,14 @@ + d = bdesc_1arg; + for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) +@@ -11648,6 +13793,14 @@ opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node); opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4); @@ -59075,7 +61141,7 @@ Index: gcc/config/rs6000/rs6000.c /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...' types, especially in C++ land. Similarly, 'vector pixel' is distinct from 'vector unsigned short'. */ -@@ -11670,6 +13755,8 @@ +@@ -11670,8 +13823,13 @@ uintSI_type_internal_node = unsigned_intSI_type_node; intDI_type_internal_node = intDI_type_node; uintDI_type_internal_node = unsigned_intDI_type_node; @@ -59083,8 +61149,13 @@ Index: gcc/config/rs6000/rs6000.c + uintTI_type_internal_node = unsigned_intTI_type_node; float_type_internal_node = float_type_node; double_type_internal_node = double_type_node; ++ long_double_type_internal_node = long_double_type_node; ++ dfloat64_type_internal_node = dfloat64_type_node; ++ dfloat128_type_internal_node = dfloat128_type_node; void_type_internal_node = void_type_node; -@@ -11682,8 +13769,12 @@ + + /* Initialize the modes for builtin_function_type, mapping a machine mode to +@@ -11682,8 +13840,15 @@ builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node; builtin_mode_to_type[DImode][0] = intDI_type_node; builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node; @@ -59092,12 +61163,15 @@ Index: gcc/config/rs6000/rs6000.c + builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node; builtin_mode_to_type[SFmode][0] = float_type_node; builtin_mode_to_type[DFmode][0] = double_type_node; ++ builtin_mode_to_type[TFmode][0] = long_double_type_node; ++ builtin_mode_to_type[DDmode][0] = dfloat64_type_node; ++ builtin_mode_to_type[TDmode][0] = dfloat128_type_node; + builtin_mode_to_type[V1TImode][0] = V1TI_type_node; + builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node; builtin_mode_to_type[V2SImode][0] = V2SI_type_node; builtin_mode_to_type[V2SFmode][0] = V2SF_type_node; builtin_mode_to_type[V2DImode][0] = V2DI_type_node; -@@ -11752,15 +13843,42 @@ +@@ -11752,15 +13917,42 @@ tdecl = add_builtin_type ("__vector double", V2DF_type_node); TYPE_NAME (V2DF_type_node) = tdecl; @@ -59146,7 +61220,7 @@ Index: gcc/config/rs6000/rs6000.c /* Paired and SPE builtins are only available if you build a compiler with the appropriate options, so only create those builtins with the appropriate compiler option. Create Altivec and VSX builtins on machines -@@ -11772,6 +13890,9 @@ +@@ -11772,6 +13964,9 @@ spe_init_builtins (); if (TARGET_EXTRA_BUILTINS) altivec_init_builtins (); @@ -59156,7 +61230,7 @@ Index: gcc/config/rs6000/rs6000.c if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT) rs6000_common_init_builtins (); -@@ -12117,6 +14238,10 @@ +@@ -12117,6 +14312,10 @@ = build_function_type_list (integer_type_node, integer_type_node, V4SI_type_node, V4SI_type_node, NULL_TREE); @@ -59167,7 +61241,7 @@ Index: gcc/config/rs6000/rs6000.c tree void_ftype_v4si = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); tree v8hi_ftype_void -@@ -12199,6 +14324,8 @@ +@@ -12199,6 +14398,8 @@ = build_function_type_list (integer_type_node, integer_type_node, V2DF_type_node, V2DF_type_node, NULL_TREE); @@ -59176,7 +61250,7 @@ Index: gcc/config/rs6000/rs6000.c tree v4si_ftype_v4si = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); tree v8hi_ftype_v8hi -@@ -12224,10 +14351,58 @@ +@@ -12224,10 +14425,58 @@ def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX); def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX); def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL); @@ -59235,7 +61309,7 @@ Index: gcc/config/rs6000/rs6000.c def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX); def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX); def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD); -@@ -12334,6 +14509,9 @@ +@@ -12334,6 +14583,9 @@ case VOIDmode: type = int_ftype_int_opaque_opaque; break; @@ -59245,7 +61319,7 @@ Index: gcc/config/rs6000/rs6000.c case V4SImode: type = int_ftype_int_v4si_v4si; break; -@@ -12367,6 +14545,9 @@ +@@ -12367,6 +14619,9 @@ switch (mode0) { @@ -59255,7 +61329,7 @@ Index: gcc/config/rs6000/rs6000.c case V4SImode: type = v4si_ftype_v4si; break; -@@ -12497,8 +14678,109 @@ +@@ -12497,8 +14752,109 @@ ftype = build_function_type_list (intDI_type_node, V2DI_type_node, integer_type_node, NULL_TREE); def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI); @@ -59365,13 +61439,15 @@ Index: gcc/config/rs6000/rs6000.c /* Hash function for builtin functions with up to 3 arguments and a return type. */ static unsigned -@@ -12572,11 +14854,27 @@ +@@ -12572,11 +14928,34 @@ are type correct. */ switch (builtin) { + /* unsigned 1 argument functions. */ + case CRYPTO_BUILTIN_VSBOX: + case P8V_BUILTIN_VGBBD: ++ case MISC_BUILTIN_CDTBCD: ++ case MISC_BUILTIN_CBCDTD: + h.uns_p[0] = 1; + h.uns_p[1] = 1; + break; @@ -59390,10 +61466,15 @@ Index: gcc/config/rs6000/rs6000.c + case CRYPTO_BUILTIN_VPMSUMW: + case CRYPTO_BUILTIN_VPMSUMD: + case CRYPTO_BUILTIN_VPMSUM: ++ case MISC_BUILTIN_ADDG6S: ++ case MISC_BUILTIN_DIVWEU: ++ case MISC_BUILTIN_DIVWEUO: ++ case MISC_BUILTIN_DIVDEU: ++ case MISC_BUILTIN_DIVDEUO: h.uns_p[0] = 1; h.uns_p[1] = 1; h.uns_p[2] = 1; -@@ -12599,6 +14897,14 @@ +@@ -12599,6 +14978,14 @@ case VSX_BUILTIN_XXSEL_8HI_UNS: case VSX_BUILTIN_XXSEL_4SI_UNS: case VSX_BUILTIN_XXSEL_2DI_UNS: @@ -59408,7 +61489,26 @@ Index: gcc/config/rs6000/rs6000.c h.uns_p[0] = 1; h.uns_p[1] = 1; h.uns_p[2] = 1; -@@ -12740,9 +15046,24 @@ +@@ -12630,9 +15017,18 @@ + /* signed args, unsigned return. */ + case VSX_BUILTIN_XVCVDPUXDS_UNS: + case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI: ++ case MISC_BUILTIN_UNPACK_TD: ++ case MISC_BUILTIN_UNPACK_V1TI: + h.uns_p[0] = 1; + break; + ++ /* unsigned arguments for 128-bit pack instructions. */ ++ case MISC_BUILTIN_PACK_TD: ++ case MISC_BUILTIN_PACK_V1TI: ++ h.uns_p[1] = 1; ++ h.uns_p[2] = 1; ++ break; ++ + default: + break; + } +@@ -12740,9 +15136,24 @@ else { enum insn_code icode = d->icode; @@ -59435,7 +61535,7 @@ Index: gcc/config/rs6000/rs6000.c type = builtin_function_type (insn_data[icode].operand[0].mode, insn_data[icode].operand[1].mode, insn_data[icode].operand[2].mode, -@@ -12780,9 +15101,24 @@ +@@ -12780,9 +15191,24 @@ else { enum insn_code icode = d->icode; @@ -59462,7 +61562,7 @@ Index: gcc/config/rs6000/rs6000.c mode0 = insn_data[icode].operand[0].mode; mode1 = insn_data[icode].operand[1].mode; mode2 = insn_data[icode].operand[2].mode; -@@ -12842,9 +15178,24 @@ +@@ -12842,9 +15268,24 @@ else { enum insn_code icode = d->icode; @@ -59489,7 +61589,7 @@ Index: gcc/config/rs6000/rs6000.c mode0 = insn_data[icode].operand[0].mode; mode1 = insn_data[icode].operand[1].mode; -@@ -13631,7 +15982,7 @@ +@@ -13631,7 +16072,7 @@ static bool eliminated = false; rtx ret; @@ -59498,7 +61598,7 @@ Index: gcc/config/rs6000/rs6000.c ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); else { -@@ -13660,6 +16011,17 @@ +@@ -13660,6 +16101,17 @@ return ret; } @@ -59516,7 +61616,7 @@ Index: gcc/config/rs6000/rs6000.c static tree rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED) { -@@ -13690,31 +16052,228 @@ +@@ -13690,31 +16142,228 @@ return NULL_TREE; } @@ -59762,7 +61862,7 @@ Index: gcc/config/rs6000/rs6000.c /* Inform reload about cases where moving X with a mode MODE to a register in RCLASS requires an extra scratch or immediate register. Return the class needed for the immediate register. -@@ -13738,12 +16297,36 @@ +@@ -13738,12 +16387,36 @@ bool default_p = false; sri->icode = CODE_FOR_nothing; @@ -59803,7 +61903,7 @@ Index: gcc/config/rs6000/rs6000.c ret = NO_REGS; sri->icode = CODE_FOR_nothing; sri->extra_cost = 0; -@@ -13754,14 +16337,23 @@ +@@ -13754,14 +16427,23 @@ /* Loads to and stores from gprs can do reg+offset, and wouldn't need an extra register in that case, but it would need an extra @@ -59831,7 +61931,7 @@ Index: gcc/config/rs6000/rs6000.c /* account for splitting the loads, and converting the address from reg+reg to reg. */ sri->extra_cost = (((TARGET_64BIT) ? 3 : 5) -@@ -13768,8 +16360,20 @@ +@@ -13768,8 +16450,20 @@ + ((GET_CODE (addr) == AND) ? 1 : 0)); } } @@ -59854,7 +61954,7 @@ Index: gcc/config/rs6000/rs6000.c else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS || rclass == FLOAT_REGS || rclass == NO_REGS) { -@@ -13813,12 +16417,12 @@ +@@ -13813,12 +16507,12 @@ else { enum reg_class xclass = REGNO_REG_CLASS (regno); @@ -59870,7 +61970,7 @@ Index: gcc/config/rs6000/rs6000.c default_p = true; else ret = NO_REGS; -@@ -13828,7 +16432,7 @@ +@@ -13828,7 +16522,7 @@ default_p = true; } else if (TARGET_POWERPC64 @@ -59879,7 +61979,7 @@ Index: gcc/config/rs6000/rs6000.c && MEM_P (x) && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD) { -@@ -13867,7 +16471,7 @@ +@@ -13867,7 +16561,7 @@ default_p = true; } else if (!TARGET_POWERPC64 @@ -59888,7 +61988,7 @@ Index: gcc/config/rs6000/rs6000.c && MEM_P (x) && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) { -@@ -13945,6 +16549,36 @@ +@@ -13945,6 +16639,36 @@ return ret; } @@ -59925,7 +62025,7 @@ Index: gcc/config/rs6000/rs6000.c /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset to SP+reg addressing. */ -@@ -13963,21 +16597,16 @@ +@@ -13963,21 +16687,16 @@ rtx cc_clobber; if (TARGET_DEBUG_ADDR) @@ -59955,7 +62055,7 @@ Index: gcc/config/rs6000/rs6000.c switch (rclass) { -@@ -13988,25 +16617,31 @@ +@@ -13988,25 +16707,31 @@ if (GET_CODE (addr) == AND) { and_op2 = XEXP (addr, 1); @@ -59994,7 +62094,7 @@ Index: gcc/config/rs6000/rs6000.c if (!REG_P (addr_op2) && (GET_CODE (addr_op2) != CONST_INT -@@ -14034,7 +16669,7 @@ +@@ -14034,7 +16759,7 @@ scratch_or_premodify = scratch; } else if (!legitimate_indirect_address_p (addr, false) @@ -60003,7 +62103,7 @@ Index: gcc/config/rs6000/rs6000.c false, true)) { if (TARGET_DEBUG_ADDR) -@@ -14050,9 +16685,21 @@ +@@ -14050,9 +16775,21 @@ } break; @@ -60027,7 +62127,7 @@ Index: gcc/config/rs6000/rs6000.c case VSX_REGS: case ALTIVEC_REGS: -@@ -14066,35 +16713,35 @@ +@@ -14066,35 +16803,35 @@ || !VECTOR_MEM_ALTIVEC_P (mode))) { and_op2 = XEXP (addr, 1); @@ -60077,7 +62177,7 @@ Index: gcc/config/rs6000/rs6000.c ; else if (GET_CODE (addr) == PLUS) -@@ -14101,7 +16748,8 @@ +@@ -14101,7 +16838,8 @@ { addr_op1 = XEXP (addr, 0); addr_op2 = XEXP (addr, 1); @@ -60087,7 +62187,7 @@ Index: gcc/config/rs6000/rs6000.c if (TARGET_DEBUG_ADDR) { -@@ -14120,7 +16768,8 @@ +@@ -14120,7 +16858,8 @@ } else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST @@ -60097,7 +62197,7 @@ Index: gcc/config/rs6000/rs6000.c { if (TARGET_DEBUG_ADDR) { -@@ -14136,12 +16785,12 @@ +@@ -14136,12 +16875,12 @@ } else @@ -60112,7 +62212,7 @@ Index: gcc/config/rs6000/rs6000.c } /* If the original address involved a pre-modify that we couldn't use the VSX -@@ -14188,7 +16837,7 @@ +@@ -14188,7 +16927,7 @@ /* Adjust the address if it changed. */ if (addr != XEXP (mem, 0)) { @@ -60121,7 +62221,7 @@ Index: gcc/config/rs6000/rs6000.c if (TARGET_DEBUG_ADDR) fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n"); } -@@ -14253,8 +16902,10 @@ +@@ -14253,8 +16992,10 @@ return; } @@ -60134,7 +62234,7 @@ Index: gcc/config/rs6000/rs6000.c static void rs6000_alloc_sdmode_stack_slot (void) -@@ -14264,7 +16915,14 @@ +@@ -14264,7 +17005,14 @@ gimple_stmt_iterator gsi; gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX); @@ -60149,7 +62249,7 @@ Index: gcc/config/rs6000/rs6000.c FOR_EACH_BB (bb) for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi)) { -@@ -14325,8 +16983,7 @@ +@@ -14325,8 +17073,7 @@ { enum machine_mode mode = GET_MODE (x); @@ -60159,7 +62259,7 @@ Index: gcc/config/rs6000/rs6000.c return rclass; if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) -@@ -14334,8 +16991,14 @@ +@@ -14334,8 +17081,14 @@ && easy_vector_constant (x, mode)) return ALTIVEC_REGS; @@ -60176,7 +62276,7 @@ Index: gcc/config/rs6000/rs6000.c if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS) return GENERAL_REGS; -@@ -14349,7 +17012,8 @@ +@@ -14349,7 +17102,8 @@ if (GET_MODE_SIZE (mode) <= 8) return FLOAT_REGS; @@ -60186,7 +62286,7 @@ Index: gcc/config/rs6000/rs6000.c return ALTIVEC_REGS; return rclass; -@@ -14381,60 +17045,45 @@ +@@ -14381,60 +17135,45 @@ set and vice versa. */ static bool @@ -60270,7 +62370,7 @@ Index: gcc/config/rs6000/rs6000.c return ret; } -@@ -14498,15 +17147,21 @@ +@@ -14498,15 +17237,21 @@ /* Constants, memory, and FP registers can go into FP registers. */ if ((regno == -1 || FP_REGNO_P (regno)) && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS)) @@ -60295,7 +62395,7 @@ Index: gcc/config/rs6000/rs6000.c /* Memory, and AltiVec registers can go into AltiVec registers. */ if ((regno == -1 || ALTIVEC_REGNO_P (regno)) && rclass == ALTIVEC_REGS) -@@ -14550,8 +17205,42 @@ +@@ -14550,8 +17295,42 @@ if (from_size != to_size) { enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS; @@ -60340,7 +62440,7 @@ Index: gcc/config/rs6000/rs6000.c } if (TARGET_E500_DOUBLE -@@ -14565,10 +17254,19 @@ +@@ -14565,10 +17344,19 @@ /* Since the VSX register set includes traditional floating point registers and altivec registers, just check for the size being different instead of trying to check whether the modes are vector modes. Otherwise it won't @@ -60362,7 +62462,7 @@ Index: gcc/config/rs6000/rs6000.c if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1) return true; -@@ -14598,6 +17296,186 @@ +@@ -14598,6 +17386,186 @@ return ret; } @@ -60549,7 +62649,7 @@ Index: gcc/config/rs6000/rs6000.c /* Given a comparison operation, return the bit number in CCR to test. We know this is a valid comparison. -@@ -14823,6 +17701,7 @@ +@@ -14823,6 +17791,7 @@ ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L."); break; @@ -60557,7 +62657,7 @@ Index: gcc/config/rs6000/rs6000.c case ABI_V4: case ABI_DARWIN: break; -@@ -15302,7 +18181,7 @@ +@@ -15302,7 +18271,7 @@ return; case 'Y': @@ -60566,7 +62666,7 @@ Index: gcc/config/rs6000/rs6000.c if (REG_P (x)) fputs (reg_names[REGNO (x) + 2], file); else if (MEM_P (x)) -@@ -15352,7 +18231,7 @@ +@@ -15352,7 +18321,7 @@ return; case 'Z': @@ -60575,7 +62675,7 @@ Index: gcc/config/rs6000/rs6000.c if (REG_P (x)) fputs (reg_names[REGNO (x) + 3], file); else if (MEM_P (x)) -@@ -15383,7 +18262,8 @@ +@@ -15383,7 +18352,8 @@ if ((TARGET_SPE || TARGET_E500_DOUBLE) && (GET_MODE_SIZE (GET_MODE (x)) == 8 || GET_MODE (x) == TFmode @@ -60585,7 +62685,7 @@ Index: gcc/config/rs6000/rs6000.c { /* Handle [reg]. */ if (REG_P (tmp)) -@@ -16766,7 +19646,8 @@ +@@ -16766,7 +19736,8 @@ } /* A subroutine of the atomic operation splitters. Emit a load-locked @@ -60595,7 +62695,7 @@ Index: gcc/config/rs6000/rs6000.c static void emit_load_locked (enum machine_mode mode, rtx reg, rtx mem) -@@ -16775,12 +19656,26 @@ +@@ -16775,12 +19746,26 @@ switch (mode) { @@ -60623,7 +62723,7 @@ Index: gcc/config/rs6000/rs6000.c default: gcc_unreachable (); } -@@ -16797,6 +19692,12 @@ +@@ -16797,6 +19782,12 @@ switch (mode) { @@ -60636,7 +62736,7 @@ Index: gcc/config/rs6000/rs6000.c case SImode: fn = gen_store_conditionalsi; break; -@@ -16803,6 +19704,9 @@ +@@ -16803,6 +19794,9 @@ case DImode: fn = gen_store_conditionaldi; break; @@ -60646,7 +62746,7 @@ Index: gcc/config/rs6000/rs6000.c default: gcc_unreachable (); } -@@ -16949,7 +19853,7 @@ +@@ -16949,7 +19943,7 @@ { rtx boolval, retval, mem, oldval, newval, cond; rtx label1, label2, x, mask, shift; @@ -60655,7 +62755,7 @@ Index: gcc/config/rs6000/rs6000.c enum memmodel mod_s, mod_f; bool is_weak; -@@ -16961,23 +19865,30 @@ +@@ -16961,23 +19955,30 @@ is_weak = (INTVAL (operands[5]) != 0); mod_s = (enum memmodel) INTVAL (operands[6]); mod_f = (enum memmodel) INTVAL (operands[7]); @@ -60696,7 +62796,7 @@ Index: gcc/config/rs6000/rs6000.c /* Prepare to adjust the return value. */ retval = gen_reg_rtx (SImode); mode = SImode; -@@ -17005,7 +19916,25 @@ +@@ -17005,7 +20006,25 @@ } cond = gen_reg_rtx (CCmode); @@ -60723,7 +62823,7 @@ Index: gcc/config/rs6000/rs6000.c emit_insn (gen_rtx_SET (VOIDmode, cond, x)); x = gen_rtx_NE (VOIDmode, cond, const0_rtx); -@@ -17015,7 +19944,7 @@ +@@ -17015,7 +20034,7 @@ if (mask) x = rs6000_mask_atomic_subword (retval, newval, mask); @@ -60732,7 +62832,7 @@ Index: gcc/config/rs6000/rs6000.c if (!is_weak) { -@@ -17033,6 +19962,8 @@ +@@ -17033,6 +20052,8 @@ if (shift) rs6000_finish_atomic_subword (operands[1], retval, shift); @@ -60741,7 +62841,7 @@ Index: gcc/config/rs6000/rs6000.c /* In all cases, CR0 contains EQ on success, and NE on failure. */ x = gen_rtx_EQ (SImode, cond, const0_rtx); -@@ -17056,7 +19987,7 @@ +@@ -17056,7 +20077,7 @@ mode = GET_MODE (mem); mask = shift = NULL_RTX; @@ -60750,7 +62850,7 @@ Index: gcc/config/rs6000/rs6000.c { mem = rs6000_adjust_atomic_subword (mem, &shift, &mask); -@@ -17105,53 +20036,70 @@ +@@ -17105,53 +20126,70 @@ { enum memmodel model = (enum memmodel) INTVAL (model_rtx); enum machine_mode mode = GET_MODE (mem); @@ -60856,7 +62956,7 @@ Index: gcc/config/rs6000/rs6000.c } mem = rs6000_pre_atomic_barrier (mem, model); -@@ -17184,9 +20132,11 @@ +@@ -17184,9 +20222,11 @@ NULL_RTX, 1, OPTAB_LIB_WIDEN); x = rs6000_mask_atomic_subword (before, x, mask); } @@ -60869,7 +62969,7 @@ Index: gcc/config/rs6000/rs6000.c x = gen_rtx_NE (VOIDmode, cond, const0_rtx); emit_unlikely_jump (x, label); -@@ -17195,11 +20145,22 @@ +@@ -17195,11 +20235,22 @@ if (shift) { @@ -60892,7 +62992,7 @@ Index: gcc/config/rs6000/rs6000.c else if (orig_after && after != orig_after) emit_move_insn (orig_after, after); } -@@ -17239,6 +20200,39 @@ +@@ -17239,6 +20290,39 @@ gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode)); @@ -60932,7 +63032,7 @@ Index: gcc/config/rs6000/rs6000.c if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) { /* Move register range backwards, if we might have destructive -@@ -17693,7 +20687,7 @@ +@@ -17693,7 +20777,7 @@ } else { @@ -60941,7 +63041,7 @@ Index: gcc/config/rs6000/rs6000.c if (info->first_fp_reg_save > 61) strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS; strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS; -@@ -17704,7 +20698,8 @@ +@@ -17704,7 +20788,8 @@ by the static chain. It would require too much fiddling and the static chain is rarely used anyway. FPRs are saved w.r.t the stack pointer on Darwin, and AIX uses r1 or r12. */ @@ -60951,7 +63051,7 @@ Index: gcc/config/rs6000/rs6000.c strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS) | SAVE_INLINE_GPRS | SAVE_INLINE_VRS | REST_INLINE_VRS); -@@ -17837,7 +20832,35 @@ +@@ -17837,7 +20922,35 @@ The required alignment for AIX configurations is two words (i.e., 8 or 16 bytes). @@ -60987,7 +63087,7 @@ Index: gcc/config/rs6000/rs6000.c V.4 stack frames look like: SP----> +---------------------------------------+ -@@ -17897,6 +20920,7 @@ +@@ -17897,6 +21010,7 @@ rs6000_stack_t *info_ptr = &stack_info; int reg_size = TARGET_32BIT ? 4 : 8; int ehrd_size; @@ -60995,7 +63095,7 @@ Index: gcc/config/rs6000/rs6000.c int save_align; int first_gp; HOST_WIDE_INT non_fixed_size; -@@ -17990,6 +21014,18 @@ +@@ -17990,6 +21104,18 @@ else ehrd_size = 0; @@ -61014,7 +63114,7 @@ Index: gcc/config/rs6000/rs6000.c /* Determine various sizes. */ info_ptr->reg_size = reg_size; info_ptr->fixed_size = RS6000_SAVE_AREA; -@@ -18029,6 +21065,7 @@ +@@ -18029,6 +21155,7 @@ gcc_unreachable (); case ABI_AIX: @@ -61022,7 +63122,7 @@ Index: gcc/config/rs6000/rs6000.c case ABI_DARWIN: info_ptr->fp_save_offset = - info_ptr->fp_size; info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; -@@ -18058,6 +21095,8 @@ +@@ -18058,6 +21185,8 @@ } else info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; @@ -61031,7 +63131,7 @@ Index: gcc/config/rs6000/rs6000.c info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ info_ptr->lr_save_offset = 2*reg_size; break; -@@ -18120,6 +21159,7 @@ +@@ -18120,6 +21249,7 @@ + info_ptr->spe_gp_size + info_ptr->spe_padding_size + ehrd_size @@ -61039,7 +63139,7 @@ Index: gcc/config/rs6000/rs6000.c + info_ptr->cr_size + info_ptr->vrsave_size, save_align); -@@ -18133,7 +21173,7 @@ +@@ -18133,7 +21263,7 @@ /* Determine if we need to save the link register. */ if (info_ptr->calls_p @@ -61048,7 +63148,7 @@ Index: gcc/config/rs6000/rs6000.c && crtl->profile && !TARGET_PROFILE_KERNEL) || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca) -@@ -18279,6 +21319,7 @@ +@@ -18279,6 +21409,7 @@ default: abi_string = "Unknown"; break; case ABI_NONE: abi_string = "NONE"; break; case ABI_AIX: abi_string = "AIX"; break; @@ -61056,7 +63156,7 @@ Index: gcc/config/rs6000/rs6000.c case ABI_DARWIN: abi_string = "Darwin"; break; case ABI_V4: abi_string = "V.4"; break; } -@@ -18400,7 +21441,8 @@ +@@ -18400,7 +21531,8 @@ /* Currently we don't optimize very well between prolog and body code and for PIC code the code can be actually quite bad, so don't try to be too clever here. */ @@ -61066,7 +63166,7 @@ Index: gcc/config/rs6000/rs6000.c { cfun->machine->ra_needs_full_frame = 1; -@@ -18459,13 +21501,13 @@ +@@ -18459,13 +21591,13 @@ return false; } @@ -61085,7 +63185,7 @@ Index: gcc/config/rs6000/rs6000.c && decl && !DECL_EXTERNAL (decl) && (*targetm.binds_local_p) (decl)) -@@ -18566,7 +21608,7 @@ +@@ -18566,7 +21698,7 @@ rtx dest; dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); @@ -61094,7 +63194,7 @@ Index: gcc/config/rs6000/rs6000.c { char buf[30]; rtx lab, tmp1, tmp2, got; -@@ -18594,7 +21636,7 @@ +@@ -18594,7 +21726,7 @@ emit_insn (gen_load_toc_v4_pic_si ()); emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO)); } @@ -61103,7 +63203,7 @@ Index: gcc/config/rs6000/rs6000.c { char buf[30]; rtx temp0 = (fromprolog -@@ -18642,7 +21684,7 @@ +@@ -18642,7 +21774,7 @@ } else { @@ -61112,7 +63212,7 @@ Index: gcc/config/rs6000/rs6000.c if (TARGET_32BIT) emit_insn (gen_load_toc_aix_si (dest)); -@@ -19047,7 +22089,7 @@ +@@ -19047,7 +22179,7 @@ static rtx rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, @@ -61121,7 +63221,7 @@ Index: gcc/config/rs6000/rs6000.c { rtx real, temp; -@@ -19138,6 +22180,11 @@ +@@ -19138,6 +22270,11 @@ } } @@ -61133,7 +63233,7 @@ Index: gcc/config/rs6000/rs6000.c RTX_FRAME_RELATED_P (insn) = 1; add_reg_note (insn, REG_FRAME_RELATED_EXPR, real); -@@ -19245,7 +22292,7 @@ +@@ -19245,7 +22382,7 @@ reg = gen_rtx_REG (mode, regno); insn = emit_insn (gen_frame_store (reg, frame_reg, offset)); return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp, @@ -61142,7 +63242,7 @@ Index: gcc/config/rs6000/rs6000.c } /* Emit an offset memory reference suitable for a frame store, while -@@ -19361,7 +22408,7 @@ +@@ -19361,7 +22498,7 @@ if ((sel & SAVRES_LR)) suffix = "_x"; } @@ -61151,7 +63251,7 @@ Index: gcc/config/rs6000/rs6000.c { #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD) /* No out-of-line save/restore routines for GPRs on AIX. */ -@@ -19502,7 +22549,7 @@ +@@ -19502,7 +22639,7 @@ static inline unsigned ptr_regno_for_savres (int sel) { @@ -61160,7 +63260,7 @@ Index: gcc/config/rs6000/rs6000.c return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12; return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11; } -@@ -19587,6 +22634,43 @@ +@@ -19587,6 +22724,43 @@ return insn; } @@ -61204,7 +63304,7 @@ Index: gcc/config/rs6000/rs6000.c /* Determine whether the gp REG is really used. */ static bool -@@ -19652,6 +22736,17 @@ +@@ -19652,6 +22826,17 @@ #define NOT_INUSE(R) do {} while (0) #endif @@ -61222,7 +63322,7 @@ Index: gcc/config/rs6000/rs6000.c if (flag_stack_usage_info) current_function_static_stack_size = info->total_size; -@@ -19766,7 +22861,7 @@ +@@ -19766,7 +22951,7 @@ insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, @@ -61231,7 +63331,7 @@ Index: gcc/config/rs6000/rs6000.c sp_off = frame_off = info->total_size; } -@@ -19851,7 +22946,7 @@ +@@ -19851,7 +23036,7 @@ insn = emit_move_insn (mem, reg); rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, @@ -61240,7 +63340,7 @@ Index: gcc/config/rs6000/rs6000.c END_USE (0); } } -@@ -19858,7 +22953,7 @@ +@@ -19858,7 +23043,7 @@ /* If we need to save CR, put it into r12 or r11. Choose r12 except when r12 will be needed by out-of-line gpr restore. */ @@ -61249,7 +63349,7 @@ Index: gcc/config/rs6000/rs6000.c && !(strategy & (SAVE_INLINE_GPRS | SAVE_NOINLINE_GPRS_SAVES_LR)) ? 11 : 12); -@@ -19867,21 +22962,9 @@ +@@ -19867,21 +23052,9 @@ && REGNO (frame_reg_rtx) != cr_save_regno && !(using_static_chain_p && cr_save_regno == 11)) { @@ -61272,7 +63372,7 @@ Index: gcc/config/rs6000/rs6000.c } /* Do any required saving of fpr's. If only one or two to save, do -@@ -19919,7 +23002,7 @@ +@@ -19919,7 +23092,7 @@ info->lr_save_offset, DFmode, sel); rs6000_frame_related (insn, ptr_reg, sp_off, @@ -61281,7 +63381,7 @@ Index: gcc/config/rs6000/rs6000.c if (lr) END_USE (0); } -@@ -19998,7 +23081,7 @@ +@@ -19998,7 +23171,7 @@ SAVRES_SAVE | SAVRES_GPR); rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off, @@ -61290,7 +63390,7 @@ Index: gcc/config/rs6000/rs6000.c } /* Move the static chain pointer back. */ -@@ -20048,7 +23131,7 @@ +@@ -20048,7 +23221,7 @@ info->lr_save_offset + ptr_off, reg_mode, sel); rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off, @@ -61299,7 +63399,7 @@ Index: gcc/config/rs6000/rs6000.c if (lr) END_USE (0); } -@@ -20064,7 +23147,7 @@ +@@ -20064,7 +23237,7 @@ info->gp_save_offset + frame_off + reg_size * i); insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, @@ -61308,7 +63408,7 @@ Index: gcc/config/rs6000/rs6000.c } else if (!WORLD_SAVE_P (info)) { -@@ -20133,7 +23216,8 @@ +@@ -20133,7 +23306,8 @@ be updated if we arrived at this function via a plt call or toc adjusting stub. */ emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg)); @@ -61318,7 +63418,7 @@ Index: gcc/config/rs6000/rs6000.c hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode); emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi)); compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO); -@@ -20152,7 +23236,7 @@ +@@ -20152,7 +23326,7 @@ LABEL_NUSES (toc_save_done) += 1; save_insn = emit_frame_save (frame_reg_rtx, reg_mode, @@ -61327,7 +63427,7 @@ Index: gcc/config/rs6000/rs6000.c sp_off - frame_off); emit_label (toc_save_done); -@@ -20192,28 +23276,123 @@ +@@ -20192,28 +23366,123 @@ rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (info->cr_save_offset + frame_off)); rtx mem = gen_frame_mem (SImode, addr); @@ -61462,7 +63562,7 @@ Index: gcc/config/rs6000/rs6000.c /* Update stack and set back pointer unless this is V.4, for which it was done previously. */ if (!WORLD_SAVE_P (info) && info->push_p -@@ -20291,7 +23470,7 @@ +@@ -20291,7 +23560,7 @@ info->altivec_save_offset + ptr_off, 0, V4SImode, SAVRES_SAVE | SAVRES_VR); rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off, @@ -61471,7 +63571,7 @@ Index: gcc/config/rs6000/rs6000.c if (REGNO (frame_reg_rtx) == REGNO (scratch_reg)) { /* The oddity mentioned above clobbered our frame reg. */ -@@ -20307,7 +23486,7 @@ +@@ -20307,7 +23576,7 @@ for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) { @@ -61480,7 +63580,7 @@ Index: gcc/config/rs6000/rs6000.c int offset; offset = (info->altivec_save_offset + frame_off -@@ -20325,8 +23504,18 @@ +@@ -20325,8 +23594,18 @@ insn = emit_move_insn (mem, savereg); @@ -61500,7 +63600,7 @@ Index: gcc/config/rs6000/rs6000.c } } -@@ -20350,7 +23539,8 @@ +@@ -20350,7 +23629,8 @@ be using r12 as frame_reg_rtx and r11 as the static chain pointer for nested functions. */ save_regno = 12; @@ -61510,7 +63610,7 @@ Index: gcc/config/rs6000/rs6000.c save_regno = 11; else if (REGNO (frame_reg_rtx) == 12) { -@@ -20389,7 +23579,7 @@ +@@ -20389,7 +23669,7 @@ can use register 0. This allows us to use a plain 'blr' to return from the procedure more often. */ int save_LR_around_toc_setup = (TARGET_ELF @@ -61519,7 +63619,7 @@ Index: gcc/config/rs6000/rs6000.c && flag_pic && ! info->lr_save_p && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); -@@ -20451,7 +23641,7 @@ +@@ -20451,7 +23731,7 @@ if (rs6000_save_toc_in_prologue_p ()) { rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM); @@ -61528,7 +63628,7 @@ Index: gcc/config/rs6000/rs6000.c } } -@@ -20492,6 +23682,49 @@ +@@ -20492,6 +23772,49 @@ } } @@ -61578,7 +63678,7 @@ Index: gcc/config/rs6000/rs6000.c rs6000_pic_labelno++; } -@@ -20544,6 +23777,7 @@ +@@ -20544,6 +23867,7 @@ if (using_mfcr_multiple && count > 1) { @@ -61586,7 +63686,7 @@ Index: gcc/config/rs6000/rs6000.c rtvec p; int ndx; -@@ -20561,16 +23795,43 @@ +@@ -20561,16 +23885,43 @@ gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); ndx++; } @@ -61634,7 +63734,7 @@ Index: gcc/config/rs6000/rs6000.c { rtx insn = get_last_insn (); rtx cr = gen_rtx_REG (SImode, CR2_REGNO); -@@ -20611,10 +23872,22 @@ +@@ -20611,10 +23962,22 @@ static rtx add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores) { @@ -61658,7 +63758,7 @@ Index: gcc/config/rs6000/rs6000.c if (info->lr_save_p) cfa_restores = alloc_reg_note (REG_CFA_RESTORE, gen_rtx_REG (Pmode, LR_REGNO), -@@ -21112,6 +24385,35 @@ +@@ -21112,6 +24475,35 @@ || (!restoring_GPRs_inline && info->first_fp_reg_save == 64)); @@ -61694,7 +63794,7 @@ Index: gcc/config/rs6000/rs6000.c /* Get the old lr if we saved it. If we are restoring registers out-of-line, then the out-of-line routines can do this for us. */ if (restore_lr && restoring_GPRs_inline) -@@ -21155,7 +24457,7 @@ +@@ -21155,7 +24547,7 @@ { rtx reg = gen_rtx_REG (reg_mode, 2); emit_insn (gen_frame_load (reg, frame_reg_rtx, @@ -61703,7 +63803,7 @@ Index: gcc/config/rs6000/rs6000.c } for (i = 0; ; ++i) -@@ -21441,6 +24743,7 @@ +@@ -21441,6 +24833,7 @@ if (! restoring_FPRs_inline) { int i; @@ -61711,7 +63811,7 @@ Index: gcc/config/rs6000/rs6000.c rtx sym; if (flag_shrink_wrap) -@@ -21449,10 +24752,9 @@ +@@ -21449,10 +24842,9 @@ sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0)); RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym); @@ -61725,7 +63825,7 @@ Index: gcc/config/rs6000/rs6000.c for (i = 0; i < 64 - info->first_fp_reg_save; i++) { rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); -@@ -21530,7 +24832,8 @@ +@@ -21530,7 +24922,8 @@ System V.4 Powerpc's (and the embedded ABI derived from it) use a different traceback table. */ @@ -61735,7 +63835,7 @@ Index: gcc/config/rs6000/rs6000.c && rs6000_traceback != traceback_none && !cfun->is_thunk) { const char *fname = NULL; -@@ -21858,6 +25161,12 @@ +@@ -21858,6 +25251,12 @@ SIBLING_CALL_P (insn) = 1; emit_barrier (); @@ -61748,7 +63848,7 @@ Index: gcc/config/rs6000/rs6000.c /* Run just enough of rest_of_compilation to get the insns emitted. There's not really enough bulk here to make other passes such as instruction scheduling worth while. Note that use_thunk calls -@@ -22554,7 +25863,7 @@ +@@ -22554,7 +25953,7 @@ if (TARGET_PROFILE_KERNEL) return; @@ -61757,7 +63857,7 @@ Index: gcc/config/rs6000/rs6000.c { #ifndef NO_PROFILE_COUNTERS # define NO_PROFILE_COUNTERS 0 -@@ -22698,29 +26007,9 @@ +@@ -22698,29 +26097,9 @@ break; case ABI_AIX: @@ -61789,7 +63889,7 @@ Index: gcc/config/rs6000/rs6000.c break; } } -@@ -22846,6 +26135,7 @@ +@@ -22846,6 +26225,7 @@ || rs6000_cpu_attr == CPU_POWER4 || rs6000_cpu_attr == CPU_POWER5 || rs6000_cpu_attr == CPU_POWER7 @@ -61797,7 +63897,7 @@ Index: gcc/config/rs6000/rs6000.c || rs6000_cpu_attr == CPU_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) -@@ -23128,7 +26418,8 @@ +@@ -23128,7 +26508,8 @@ if (rs6000_cpu_attr == CPU_CELL) return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS; @@ -61807,7 +63907,7 @@ Index: gcc/config/rs6000/rs6000.c { enum attr_type type = get_attr_type (insn); if (type == TYPE_LOAD_EXT_U -@@ -23153,7 +26444,8 @@ +@@ -23153,7 +26534,8 @@ || GET_CODE (PATTERN (insn)) == CLOBBER) return false; @@ -61817,7 +63917,7 @@ Index: gcc/config/rs6000/rs6000.c { enum attr_type type = get_attr_type (insn); if (type == TYPE_LOAD_U || type == TYPE_STORE_U -@@ -23432,6 +26724,8 @@ +@@ -23432,6 +26814,8 @@ case CPU_POWER6: case CPU_POWER7: return 5; @@ -61826,7 +63926,7 @@ Index: gcc/config/rs6000/rs6000.c default: return 1; } -@@ -24059,6 +27353,39 @@ +@@ -24059,6 +27443,39 @@ break; } break; @@ -61866,7 +63966,7 @@ Index: gcc/config/rs6000/rs6000.c default: break; } -@@ -24137,6 +27464,25 @@ +@@ -24137,6 +27554,25 @@ break; } break; @@ -61892,7 +63992,7 @@ Index: gcc/config/rs6000/rs6000.c default: break; } -@@ -24226,8 +27572,9 @@ +@@ -24226,8 +27662,9 @@ if (can_issue_more && !is_branch_slot_insn (next_insn)) can_issue_more--; @@ -61904,7 +64004,7 @@ Index: gcc/config/rs6000/rs6000.c { nop = gen_group_ending_nop (); emit_insn_before (nop, next_insn); -@@ -24598,6 +27945,11 @@ +@@ -24598,6 +28035,11 @@ ret = (TARGET_32BIT) ? 12 : 24; break; @@ -61916,7 +64016,7 @@ Index: gcc/config/rs6000/rs6000.c case ABI_DARWIN: case ABI_V4: ret = (TARGET_32BIT) ? 40 : 48; -@@ -24653,6 +28005,7 @@ +@@ -24653,6 +28095,7 @@ break; /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ @@ -61924,7 +64024,7 @@ Index: gcc/config/rs6000/rs6000.c case ABI_DARWIN: case ABI_V4: emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"), -@@ -24743,6 +28096,9 @@ +@@ -24743,6 +28186,9 @@ unsigned_p = TYPE_UNSIGNED (type); switch (mode) { @@ -61934,7 +64034,7 @@ Index: gcc/config/rs6000/rs6000.c case DImode: result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node); break; -@@ -24947,7 +28303,7 @@ +@@ -24947,7 +28393,7 @@ static void rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED) { @@ -61943,7 +64043,7 @@ Index: gcc/config/rs6000/rs6000.c && TARGET_MINIMAL_TOC && !TARGET_RELOCATABLE) { -@@ -24968,7 +28324,8 @@ +@@ -24968,7 +28414,8 @@ else fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); } @@ -61953,7 +64053,7 @@ Index: gcc/config/rs6000/rs6000.c fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP); else { -@@ -25518,7 +28875,7 @@ +@@ -25518,7 +28965,7 @@ { if (flag_pic) return 3; @@ -61962,7 +64062,7 @@ Index: gcc/config/rs6000/rs6000.c return 2; else return 0; -@@ -25594,7 +28951,7 @@ +@@ -25594,7 +29041,7 @@ void rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) { @@ -61971,7 +64071,7 @@ Index: gcc/config/rs6000/rs6000.c { fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); ASM_OUTPUT_LABEL (file, name); -@@ -25660,8 +29017,7 @@ +@@ -25660,8 +29107,7 @@ fprintf (file, "%s:\n", desc_name); fprintf (file, "\t.long %s\n", orig_name); fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); @@ -61981,7 +64081,7 @@ Index: gcc/config/rs6000/rs6000.c fprintf (file, "\t.previous\n"); } ASM_OUTPUT_LABEL (file, name); -@@ -25690,7 +29046,7 @@ +@@ -25690,7 +29136,7 @@ } #endif #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD) @@ -61990,7 +64090,7 @@ Index: gcc/config/rs6000/rs6000.c file_end_indicate_exec_stack (); #endif } -@@ -25829,10 +29185,23 @@ +@@ -25829,10 +29275,23 @@ name, suffix[smclass], flags & SECTION_ENTSIZE); } @@ -62015,7 +64115,7 @@ Index: gcc/config/rs6000/rs6000.c if (decl_readonly_section (decl, reloc)) { if (TREE_PUBLIC (decl)) -@@ -25870,10 +29239,12 @@ +@@ -25870,10 +29329,12 @@ { const char *name; @@ -62030,7 +64130,7 @@ Index: gcc/config/rs6000/rs6000.c || DECL_INITIAL (decl) == error_mark_node || (flag_zero_initialized_in_bss && initializer_zerop (DECL_INITIAL (decl)))) -@@ -26430,7 +29801,8 @@ +@@ -26430,7 +29891,8 @@ /* For those processors that have slow LR/CTR moves, make them more expensive than memory in order to bias spills to memory .*/ else if ((rs6000_cpu == PROCESSOR_POWER6 @@ -62040,7 +64140,7 @@ Index: gcc/config/rs6000/rs6000.c && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS)) ret = 6 * hard_regno_nregs[0][mode]; -@@ -26440,7 +29812,7 @@ +@@ -26440,7 +29902,7 @@ } /* If we have VSX, we can easily move between FPR or Altivec registers. */ @@ -62049,7 +64149,7 @@ Index: gcc/config/rs6000/rs6000.c && reg_classes_intersect_p (to, VSX_REGS) && reg_classes_intersect_p (from, VSX_REGS)) ret = 2 * hard_regno_nregs[32][mode]; -@@ -26481,7 +29853,8 @@ +@@ -26481,7 +29943,8 @@ if (reg_classes_intersect_p (rclass, GENERAL_REGS)) ret = 4 * hard_regno_nregs[0][mode]; @@ -62059,7 +64159,7 @@ Index: gcc/config/rs6000/rs6000.c ret = 4 * hard_regno_nregs[32][mode]; else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS)) ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode]; -@@ -26643,54 +30016,26 @@ +@@ -26643,54 +30106,26 @@ emit_insn (gen_rtx_SET (VOIDmode, dst, r)); } @@ -62129,7 +64229,7 @@ Index: gcc/config/rs6000/rs6000.c enum insn_code code = optab_handler (smul_optab, mode); insn_gen_fn gen_mul = GEN_FCN (code); -@@ -26704,47 +30049,45 @@ +@@ -26704,47 +30139,45 @@ gen_rtx_UNSPEC (mode, gen_rtvec (1, d), UNSPEC_FRES))); @@ -62206,7 +64306,7 @@ Index: gcc/config/rs6000/rs6000.c if (note_p) add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d)); } -@@ -26758,7 +30101,16 @@ +@@ -26758,7 +30191,16 @@ enum machine_mode mode = GET_MODE (src); rtx x0 = gen_reg_rtx (mode); rtx y = gen_reg_rtx (mode); @@ -62224,7 +64324,7 @@ Index: gcc/config/rs6000/rs6000.c REAL_VALUE_TYPE dconst3_2; int i; rtx halfthree; -@@ -26920,6 +30272,136 @@ +@@ -26920,6 +30362,136 @@ } } @@ -62361,7 +64461,7 @@ Index: gcc/config/rs6000/rs6000.c /* Expand an Altivec constant permutation. Return true if we match an efficient implementation; false to fall back to VPERM. */ -@@ -26927,26 +30409,43 @@ +@@ -26927,26 +30499,43 @@ altivec_expand_vec_perm_const (rtx operands[4]) { struct altivec_perm_insn { @@ -62414,7 +64514,7 @@ Index: gcc/config/rs6000/rs6000.c }; unsigned int i, j, elt, which; -@@ -27003,7 +30502,9 @@ +@@ -27003,7 +30592,9 @@ break; if (i == 16) { @@ -62425,7 +64525,7 @@ Index: gcc/config/rs6000/rs6000.c return true; } -@@ -27014,9 +30515,10 @@ +@@ -27014,9 +30605,10 @@ break; if (i == 16) { @@ -62438,7 +64538,7 @@ Index: gcc/config/rs6000/rs6000.c emit_move_insn (target, gen_lowpart (V16QImode, x)); return true; } -@@ -27032,9 +30534,10 @@ +@@ -27032,9 +30624,10 @@ break; if (i == 16) { @@ -62451,7 +64551,7 @@ Index: gcc/config/rs6000/rs6000.c emit_move_insn (target, gen_lowpart (V16QImode, x)); return true; } -@@ -27046,6 +30549,9 @@ +@@ -27046,6 +30639,9 @@ { bool swapped; @@ -62461,7 +64561,7 @@ Index: gcc/config/rs6000/rs6000.c elt = patterns[j].perm[0]; if (perm[0] == elt) swapped = false; -@@ -27069,7 +30575,30 @@ +@@ -27069,7 +30665,30 @@ enum machine_mode omode = insn_data[icode].operand[0].mode; enum machine_mode imode = insn_data[icode].operand[1].mode; @@ -62493,7 +64593,7 @@ Index: gcc/config/rs6000/rs6000.c x = op0, op0 = op1, op1 = x; if (imode != V16QImode) { -@@ -27087,6 +30616,12 @@ +@@ -27087,6 +30706,12 @@ } } @@ -62506,7 +64606,7 @@ Index: gcc/config/rs6000/rs6000.c return false; } -@@ -27135,7 +30670,6 @@ +@@ -27135,7 +30760,6 @@ vmode = GET_MODE (target); gcc_assert (GET_MODE_NUNITS (vmode) == 2); dmode = mode_for_vector (GET_MODE_INNER (vmode), 4); @@ -62514,7 +64614,7 @@ Index: gcc/config/rs6000/rs6000.c x = gen_rtx_VEC_CONCAT (dmode, op0, op1); v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1)); x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v)); -@@ -27231,7 +30765,7 @@ +@@ -27231,7 +30855,7 @@ unsigned i, high, nelt = GET_MODE_NUNITS (vmode); rtx perm[16]; @@ -62523,7 +64623,7 @@ Index: gcc/config/rs6000/rs6000.c for (i = 0; i < nelt / 2; i++) { perm[i * 2] = GEN_INT (i + high); -@@ -27286,6 +30820,8 @@ +@@ -27286,6 +30910,8 @@ { enum machine_mode mode; unsigned int regno; @@ -62532,7 +64632,7 @@ Index: gcc/config/rs6000/rs6000.c /* Special handling for structs in darwin64. */ if (TARGET_MACHO -@@ -27305,6 +30841,36 @@ +@@ -27305,6 +30931,36 @@ /* Otherwise fall through to standard ABI rules. */ } @@ -62569,7 +64669,7 @@ Index: gcc/config/rs6000/rs6000.c if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) { /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ -@@ -27417,6 +30983,13 @@ +@@ -27417,6 +31073,13 @@ } @@ -62583,7 +64683,7 @@ Index: gcc/config/rs6000/rs6000.c /* Given FROM and TO register numbers, say whether this elimination is allowed. Frame pointer elimination is automatically handled. -@@ -27679,22 +31252,33 @@ +@@ -27679,22 +31342,33 @@ { { "altivec", OPTION_MASK_ALTIVEC, false, true }, { "cmpb", OPTION_MASK_CMPB, false, true }, @@ -62618,17 +64718,19 @@ Index: gcc/config/rs6000/rs6000.c #ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS { "aix64", OPTION_MASK_64BIT, false, false }, -@@ -27734,6 +31318,9 @@ +@@ -27734,6 +31408,11 @@ { "frsqrtes", RS6000_BTM_FRSQRTES, false, false }, { "popcntd", RS6000_BTM_POPCNTD, false, false }, { "cell", RS6000_BTM_CELL, false, false }, + { "power8-vector", RS6000_BTM_P8_VECTOR, false, false }, + { "crypto", RS6000_BTM_CRYPTO, false, false }, + { "htm", RS6000_BTM_HTM, false, false }, ++ { "hard-dfp", RS6000_BTM_DFP, false, false }, ++ { "hard-float", RS6000_BTM_HARD_FLOAT, false, false }, }; /* Option variables that we want to support inside attribute((target)) and -@@ -28250,7 +31837,6 @@ +@@ -28250,7 +31929,6 @@ size_t cur_column; size_t max_column = 76; const char *comma = ""; @@ -62636,7 +64738,7 @@ Index: gcc/config/rs6000/rs6000.c if (indent) start_column += fprintf (file, "%*s", indent, ""); -@@ -28281,7 +31867,6 @@ +@@ -28281,7 +31959,6 @@ fprintf (stderr, ", \\\n%*s", (int)start_column, ""); cur_column = start_column + len; comma = ""; @@ -62644,7 +64746,7 @@ Index: gcc/config/rs6000/rs6000.c } fprintf (file, "%s%s%s%s", comma, prefix, no_str, -@@ -28291,7 +31876,7 @@ +@@ -28291,7 +31968,7 @@ } } @@ -62653,7 +64755,7 @@ Index: gcc/config/rs6000/rs6000.c } /* Helper function to print the current isa options on a line. */ -@@ -28467,118 +32052,149 @@ +@@ -28467,118 +32144,149 @@ } @@ -62887,7 +64989,7 @@ Index: gcc/config/rs6000/rs6000.c } /* Return whether we need to always update the saved TOC pointer when we update -@@ -28679,6 +32295,661 @@ +@@ -28679,6 +32387,661 @@ add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); } @@ -65300,7 +67402,17 @@ Index: gcc/config/rs6000/rs6000.h #ifndef IN_LIBGCC2 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 -@@ -558,6 +630,25 @@ +@@ -551,7 +623,8 @@ + || TARGET_CMPB /* ISA 2.05 */ \ + || TARGET_POPCNTD /* ISA 2.06 */ \ + || TARGET_ALTIVEC \ +- || TARGET_VSX))) ++ || TARGET_VSX \ ++ || TARGET_HARD_FLOAT))) + + /* E500 cores only support plain "sync", not lwsync. */ + #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ +@@ -558,6 +631,25 @@ || rs6000_cpu == PROCESSOR_PPC8548) @@ -65326,7 +67438,7 @@ Index: gcc/config/rs6000/rs6000.h /* Which machine supports the various reciprocal estimate instructions. */ #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && TARGET_FPRS && TARGET_SINGLE_FLOAT) -@@ -595,9 +686,6 @@ +@@ -595,9 +687,6 @@ #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) @@ -65336,7 +67448,7 @@ Index: gcc/config/rs6000/rs6000.h /* The default CPU for TARGET_OPTION_OVERRIDE. */ #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT -@@ -760,12 +848,6 @@ +@@ -760,12 +849,6 @@ /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 128 @@ -65349,7 +67461,7 @@ Index: gcc/config/rs6000/rs6000.h /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 -@@ -775,8 +857,15 @@ +@@ -775,8 +858,15 @@ /* A bit-field declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 @@ -65367,7 +67479,7 @@ Index: gcc/config/rs6000/rs6000.h #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ (TREE_CODE (EXP) == STRING_CST \ && (STRICT_ALIGNMENT || !optimize_size) \ -@@ -784,21 +873,14 @@ +@@ -784,21 +874,14 @@ ? BITS_PER_WORD \ : (ALIGN)) @@ -65396,7 +67508,7 @@ Index: gcc/config/rs6000/rs6000.h /* Nonzero if move instructions will actually fail to work when given unaligned data. */ -@@ -842,15 +924,17 @@ +@@ -842,15 +925,17 @@ in inline functions. Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame @@ -65417,7 +67529,7 @@ Index: gcc/config/rs6000/rs6000.h /* The SPE has an additional 32 synthetic registers, with DWARF debug info numbering for these registers starting at 1200. While eh_frame -@@ -866,7 +950,7 @@ +@@ -866,7 +951,7 @@ We must map them here to avoid huge unwinder tables mostly consisting of unused space. */ #define DWARF_REG_TO_UNWIND_COLUMN(r) \ @@ -65426,7 +67538,7 @@ Index: gcc/config/rs6000/rs6000.h /* Use standard DWARF numbering for DWARF debugging information. */ #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) -@@ -906,7 +990,7 @@ +@@ -906,7 +991,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ @@ -65435,7 +67547,7 @@ Index: gcc/config/rs6000/rs6000.h } /* 1 for registers not available across function calls. -@@ -926,7 +1010,7 @@ +@@ -926,7 +1011,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ @@ -65444,7 +67556,7 @@ Index: gcc/config/rs6000/rs6000.h } /* Like `CALL_USED_REGISTERS' except this macro doesn't require that -@@ -945,7 +1029,7 @@ +@@ -945,7 +1030,7 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 \ @@ -65453,7 +67565,7 @@ Index: gcc/config/rs6000/rs6000.h } #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) -@@ -984,6 +1068,9 @@ +@@ -984,6 +1069,9 @@ vrsave, vscr (fixed) spe_acc, spefscr (fixed) sfp (fixed) @@ -65463,7 +67575,7 @@ Index: gcc/config/rs6000/rs6000.h */ #if FIXED_R2 == 1 -@@ -1004,7 +1091,9 @@ +@@ -1004,7 +1092,9 @@ #define REG_ALLOC_ORDER \ {32, \ @@ -65474,7 +67586,7 @@ Index: gcc/config/rs6000/rs6000.h 33, \ 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 50, 49, 48, 47, 46, \ -@@ -1023,7 +1112,7 @@ +@@ -1023,7 +1113,7 @@ 96, 95, 94, 93, 92, 91, \ 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 109, 110, \ @@ -65483,7 +67595,7 @@ Index: gcc/config/rs6000/rs6000.h } /* True if register is floating-point. */ -@@ -1064,8 +1153,11 @@ +@@ -1064,8 +1154,11 @@ #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) /* Alternate name for any vector register supporting logical operations, no @@ -65497,7 +67609,7 @@ Index: gcc/config/rs6000/rs6000.h /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. */ -@@ -1106,7 +1198,7 @@ +@@ -1106,7 +1199,7 @@ #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ @@ -65506,7 +67618,7 @@ Index: gcc/config/rs6000/rs6000.h #define SPE_VECTOR_MODE(MODE) \ ((MODE) == V4HImode \ -@@ -1125,28 +1217,32 @@ +@@ -1125,28 +1218,32 @@ /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, @@ -65550,7 +67662,7 @@ Index: gcc/config/rs6000/rs6000.h : 1) /* Post-reload, we can't use any new AltiVec registers, as we already -@@ -1240,6 +1336,7 @@ +@@ -1240,6 +1337,7 @@ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, @@ -65558,7 +67670,7 @@ Index: gcc/config/rs6000/rs6000.h NON_SPECIAL_REGS, LINK_REGS, CTR_REGS, -@@ -1270,6 +1367,7 @@ +@@ -1270,6 +1368,7 @@ "VSCR_REGS", \ "SPE_ACC_REGS", \ "SPEFSCR_REGS", \ @@ -65566,7 +67678,7 @@ Index: gcc/config/rs6000/rs6000.h "NON_SPECIAL_REGS", \ "LINK_REGS", \ "CTR_REGS", \ -@@ -1299,6 +1397,7 @@ +@@ -1299,6 +1398,7 @@ { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ @@ -65574,7 +67686,7 @@ Index: gcc/config/rs6000/rs6000.h { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ -@@ -1309,7 +1408,7 @@ +@@ -1309,7 +1409,7 @@ { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ @@ -65583,7 +67695,7 @@ Index: gcc/config/rs6000/rs6000.h } /* The same information, inverted: -@@ -1337,7 +1436,18 @@ +@@ -1337,7 +1437,18 @@ RS6000_CONSTRAINT_wa, /* Any VSX register */ RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ @@ -65602,7 +67714,7 @@ Index: gcc/config/rs6000/rs6000.h RS6000_CONSTRAINT_MAX }; -@@ -1425,21 +1535,14 @@ +@@ -1425,21 +1536,14 @@ arguments. */ #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 || flag_asan != 0) @@ -65628,7 +67740,7 @@ Index: gcc/config/rs6000/rs6000.h /* Align an address */ #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) -@@ -1489,7 +1592,7 @@ +@@ -1489,7 +1593,7 @@ /* Define this if stack space is still allocated for a parameter passed in a register. The value is the number of bytes allocated to this area. */ @@ -65637,7 +67749,7 @@ Index: gcc/config/rs6000/rs6000.h /* Define this if the above stack space is to be considered part of the space allocated by the caller. */ -@@ -1522,7 +1625,7 @@ +@@ -1522,7 +1626,7 @@ NONLOCAL needs twice Pmode to maintain both backchain and SP. */ #define STACK_SAVEAREA_MODE(LEVEL) \ (LEVEL == SAVE_FUNCTION ? VOIDmode \ @@ -65646,7 +67758,7 @@ Index: gcc/config/rs6000/rs6000.h /* Minimum and maximum general purpose registers used to hold arguments. */ #define GP_ARG_MIN_REG 3 -@@ -1533,9 +1636,8 @@ +@@ -1533,9 +1637,8 @@ #define FP_ARG_MIN_REG 33 #define FP_ARG_AIX_MAX_REG 45 #define FP_ARG_V4_MAX_REG 40 @@ -65658,7 +67770,7 @@ Index: gcc/config/rs6000/rs6000.h #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) /* Minimum and maximum AltiVec registers used to hold arguments. */ -@@ -1543,10 +1645,17 @@ +@@ -1543,10 +1646,17 @@ #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) @@ -65676,7 +67788,7 @@ Index: gcc/config/rs6000/rs6000.h /* Flags for the call/call_value rtl operations set up by function_arg */ #define CALL_NORMAL 0x00000000 /* no special processing */ -@@ -1566,8 +1675,10 @@ +@@ -1566,8 +1676,10 @@ On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ #define FUNCTION_VALUE_REGNO_P(N) \ ((N) == GP_ARG_RETURN \ @@ -65689,7 +67801,7 @@ Index: gcc/config/rs6000/rs6000.h /* 1 if N is a possible register number for function argument passing. On RS/6000, these are r3-r10 and fp1-fp13. -@@ -1691,11 +1802,8 @@ +@@ -1691,11 +1803,8 @@ /* Number of bytes into the frame return addresses can be found. See rs6000_stack_info in rs6000.c for more information on how the different abi's store the return address. */ @@ -65703,7 +67815,7 @@ Index: gcc/config/rs6000/rs6000.h /* The current return address is in link register (65). The return address of anything farther back is accessed normally at an offset of 8 from the -@@ -2215,6 +2323,9 @@ +@@ -2215,6 +2324,9 @@ &rs6000_reg_names[111][0], /* spe_acc */ \ &rs6000_reg_names[112][0], /* spefscr */ \ &rs6000_reg_names[113][0], /* sfp */ \ @@ -65713,7 +67825,7 @@ Index: gcc/config/rs6000/rs6000.h } /* Table of additional register names to use in user input. */ -@@ -2268,7 +2379,9 @@ +@@ -2268,7 +2380,9 @@ {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ @@ -65724,7 +67836,7 @@ Index: gcc/config/rs6000/rs6000.h /* This is how to output an element of a case-vector that is relative. */ -@@ -2357,7 +2470,12 @@ +@@ -2357,7 +2471,12 @@ #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ /* Miscellaneous information. */ @@ -65738,7 +67850,7 @@ Index: gcc/config/rs6000/rs6000.h /* Convenience macros to document the instruction type. */ #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ -@@ -2369,6 +2487,9 @@ +@@ -2369,6 +2488,9 @@ #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ @@ -65748,7 +67860,12 @@ Index: gcc/config/rs6000/rs6000.h #define RS6000_BTM_SPE MASK_STRING /* E500 */ #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ -@@ -2380,10 +2501,13 @@ +@@ -2377,15 +2499,22 @@ + #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ + #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ + #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ ++#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ ++#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | RS6000_BTM_VSX \ @@ -65760,9 +67877,14 @@ Index: gcc/config/rs6000/rs6000.h | RS6000_BTM_FRSQRTES \ + | RS6000_BTM_HTM \ | RS6000_BTM_POPCNTD \ - | RS6000_BTM_CELL) +- | RS6000_BTM_CELL) ++ | RS6000_BTM_CELL \ ++ | RS6000_BTM_DFP \ ++ | RS6000_BTM_HARD_FLOAT) + + /* Define builtin enum index. */ -@@ -2395,6 +2519,7 @@ +@@ -2395,6 +2524,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -65770,7 +67892,7 @@ Index: gcc/config/rs6000/rs6000.h #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -2406,6 +2531,7 @@ +@@ -2406,6 +2536,7 @@ #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM, @@ -65778,7 +67900,7 @@ Index: gcc/config/rs6000/rs6000.h #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM, -@@ -2424,6 +2550,7 @@ +@@ -2424,6 +2555,7 @@ #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E @@ -65786,7 +67908,7 @@ Index: gcc/config/rs6000/rs6000.h #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S -@@ -2437,6 +2564,7 @@ +@@ -2437,6 +2569,7 @@ RS6000_BTI_opaque_p_V2SI, RS6000_BTI_opaque_V4SI, RS6000_BTI_V16QI, @@ -65794,7 +67916,7 @@ Index: gcc/config/rs6000/rs6000.h RS6000_BTI_V2SI, RS6000_BTI_V2SF, RS6000_BTI_V2DI, -@@ -2446,6 +2574,7 @@ +@@ -2446,6 +2579,7 @@ RS6000_BTI_V4SF, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, @@ -65802,7 +67924,7 @@ Index: gcc/config/rs6000/rs6000.h RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, -@@ -2471,6 +2600,8 @@ +@@ -2471,8 +2605,13 @@ RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ RS6000_BTI_INTDI, /* intDI_type_node */ RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ @@ -65810,8 +67932,13 @@ Index: gcc/config/rs6000/rs6000.h + RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ RS6000_BTI_float, /* float_type_node */ RS6000_BTI_double, /* double_type_node */ ++ RS6000_BTI_long_double, /* long_double_type_node */ ++ RS6000_BTI_dfloat64, /* dfloat64_type_node */ ++ RS6000_BTI_dfloat128, /* dfloat128_type_node */ RS6000_BTI_void, /* void_type_node */ -@@ -2483,6 +2614,7 @@ + RS6000_BTI_MAX + }; +@@ -2483,6 +2622,7 @@ #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) @@ -65819,7 +67946,7 @@ Index: gcc/config/rs6000/rs6000.h #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) -@@ -2492,6 +2624,7 @@ +@@ -2492,6 +2632,7 @@ #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) @@ -65827,7 +67954,7 @@ Index: gcc/config/rs6000/rs6000.h #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) -@@ -2518,6 +2651,8 @@ +@@ -2518,8 +2659,13 @@ #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) @@ -65835,7 +67962,12 @@ Index: gcc/config/rs6000/rs6000.h +#define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) ++#define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) ++#define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) ++#define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) + + extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; Index: gcc/config/rs6000/altivec.md =================================================================== --- a/src/gcc/config/rs6000/altivec.md (.../tags/gcc_4_8_2_release) @@ -65878,7 +68010,7 @@ Index: gcc/config/rs6000/altivec.md UNSPEC_DST UNSPEC_DSTT UNSPEC_DSTST -@@ -134,6 +131,18 @@ +@@ -134,6 +131,21 @@ UNSPEC_VUPKLS_V4SF UNSPEC_VUPKHU_V4SF UNSPEC_VUPKLU_V4SF @@ -65894,10 +68026,13 @@ Index: gcc/config/rs6000/altivec.md + UNSPEC_VSUBEUQM + UNSPEC_VSUBECUQ + UNSPEC_VBPERMQ ++ UNSPEC_BCDADD ++ UNSPEC_BCDSUB ++ UNSPEC_BCD_OVERFLOW ]) (define_c_enum "unspecv" -@@ -146,6 +155,8 @@ +@@ -146,6 +158,8 @@ ;; Vec int modes (define_mode_iterator VI [V4SI V8HI V16QI]) @@ -65906,7 +68041,7 @@ Index: gcc/config/rs6000/altivec.md ;; Short vec in modes (define_mode_iterator VIshort [V8HI V16QI]) ;; Vec float modes -@@ -154,14 +165,25 @@ +@@ -154,14 +168,25 @@ (define_mode_iterator V [V4SI V8HI V16QI V4SF]) ;; Vec modes for move/logical/permute ops, include vector types for move not ;; otherwise handled by altivec (v2df, v2di, ti) @@ -65936,7 +68071,7 @@ Index: gcc/config/rs6000/altivec.md ;; Vector move instructions. (define_insn "*altivec_mov<mode>" [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v") -@@ -378,10 +400,10 @@ +@@ -378,10 +403,10 @@ ;; add (define_insn "add<mode>3" @@ -65951,7 +68086,7 @@ Index: gcc/config/rs6000/altivec.md "vaddu<VI_char>m %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -398,7 +420,7 @@ +@@ -398,7 +423,7 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VADDCUW))] @@ -65960,7 +68095,7 @@ Index: gcc/config/rs6000/altivec.md "vaddcuw %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -405,10 +427,10 @@ +@@ -405,10 +430,10 @@ (define_insn "altivec_vaddu<VI_char>s" [(set (match_operand:VI 0 "register_operand" "=v") (unspec:VI [(match_operand:VI 1 "register_operand" "v") @@ -65973,7 +68108,7 @@ Index: gcc/config/rs6000/altivec.md "vaddu<VI_char>s %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -418,16 +440,16 @@ +@@ -418,16 +443,16 @@ (match_operand:VI 2 "register_operand" "v")] UNSPEC_VADDS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] @@ -65995,7 +68130,7 @@ Index: gcc/config/rs6000/altivec.md "vsubu<VI_char>m %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -444,7 +466,7 @@ +@@ -444,7 +469,7 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUBCUW))] @@ -66004,7 +68139,7 @@ Index: gcc/config/rs6000/altivec.md "vsubcuw %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -454,7 +476,7 @@ +@@ -454,7 +479,7 @@ (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBU)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] @@ -66013,7 +68148,7 @@ Index: gcc/config/rs6000/altivec.md "vsubu<VI_char>s %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -464,7 +486,7 @@ +@@ -464,7 +489,7 @@ (match_operand:VI 2 "register_operand" "v")] UNSPEC_VSUBS)) (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] @@ -66022,7 +68157,7 @@ Index: gcc/config/rs6000/altivec.md "vsubs<VI_char>s %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -483,7 +505,7 @@ +@@ -483,7 +508,7 @@ (unspec:VI [(match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")] UNSPEC_VAVGS))] @@ -66031,7 +68166,7 @@ Index: gcc/config/rs6000/altivec.md "vavgs<VI_char> %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -492,31 +514,31 @@ +@@ -492,31 +517,31 @@ (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v")] UNSPEC_VCMPBFP))] @@ -66076,7 +68211,7 @@ Index: gcc/config/rs6000/altivec.md "vcmpgtu<VI_char> %0,%1,%2" [(set_attr "type" "veccmp")]) -@@ -642,7 +664,7 @@ +@@ -642,7 +667,7 @@ convert_move (small_swap, swap, 0); low_product = gen_reg_rtx (V4SImode); @@ -66085,7 +68220,7 @@ Index: gcc/config/rs6000/altivec.md high_product = gen_reg_rtx (V4SImode); emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero)); -@@ -666,14 +688,23 @@ +@@ -666,14 +691,23 @@ rtx high = gen_reg_rtx (V4SImode); rtx low = gen_reg_rtx (V4SImode); @@ -66116,7 +68251,7 @@ Index: gcc/config/rs6000/altivec.md DONE; }") -@@ -744,18 +775,18 @@ +@@ -744,18 +778,18 @@ ;; max (define_insn "umax<mode>3" @@ -66143,7 +68278,7 @@ Index: gcc/config/rs6000/altivec.md "vmaxs<VI_char> %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -768,18 +799,18 @@ +@@ -768,18 +802,18 @@ [(set_attr "type" "veccmp")]) (define_insn "umin<mode>3" @@ -66170,7 +68305,7 @@ Index: gcc/config/rs6000/altivec.md "vmins<VI_char> %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -823,9 +854,41 @@ +@@ -823,9 +857,41 @@ "vmladduhm %0,%1,%2,%3" [(set_attr "type" "veccomplex")]) @@ -66214,7 +68349,7 @@ Index: gcc/config/rs6000/altivec.md (vec_concat:V32QI (match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")) -@@ -838,12 +901,54 @@ +@@ -838,12 +904,54 @@ (const_int 6) (const_int 22) (const_int 7) (const_int 23)])))] "TARGET_ALTIVEC" @@ -66271,7 +68406,7 @@ Index: gcc/config/rs6000/altivec.md (vec_concat:V16HI (match_operand:V8HI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v")) -@@ -852,10 +957,50 @@ +@@ -852,10 +960,50 @@ (const_int 2) (const_int 10) (const_int 3) (const_int 11)])))] "TARGET_ALTIVEC" @@ -66323,7 +68458,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_select:V4SI (vec_concat:V8SI -@@ -864,6 +1009,20 @@ +@@ -864,6 +1012,20 @@ (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_ALTIVEC_P (V4SImode)" @@ -66344,7 +68479,7 @@ Index: gcc/config/rs6000/altivec.md "vmrghw %0,%1,%2" [(set_attr "type" "vecperm")]) -@@ -876,10 +1035,47 @@ +@@ -876,10 +1038,47 @@ (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_ALTIVEC_P (V4SFmode)" @@ -66394,7 +68529,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:V16QI 0 "register_operand" "=v") (vec_select:V16QI (vec_concat:V32QI -@@ -894,10 +1090,52 @@ +@@ -894,10 +1093,52 @@ (const_int 14) (const_int 30) (const_int 15) (const_int 31)])))] "TARGET_ALTIVEC" @@ -66448,7 +68583,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_select:V8HI (vec_concat:V16HI -@@ -908,10 +1146,50 @@ +@@ -908,10 +1149,50 @@ (const_int 6) (const_int 14) (const_int 7) (const_int 15)])))] "TARGET_ALTIVEC" @@ -66500,7 +68635,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_select:V4SI (vec_concat:V8SI -@@ -920,6 +1198,20 @@ +@@ -920,6 +1201,20 @@ (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_ALTIVEC_P (V4SImode)" @@ -66521,7 +68656,7 @@ Index: gcc/config/rs6000/altivec.md "vmrglw %0,%1,%2" [(set_attr "type" "vecperm")]) -@@ -932,10 +1224,154 @@ +@@ -932,10 +1227,154 @@ (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_ALTIVEC_P (V4SFmode)" @@ -66678,7 +68813,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] -@@ -944,43 +1380,25 @@ +@@ -944,43 +1383,25 @@ "vmuleub %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -66729,7 +68864,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") (match_operand:V16QI 2 "register_operand" "v")] -@@ -989,19 +1407,37 @@ +@@ -989,19 +1410,37 @@ "vmulosb %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -66769,7 +68904,7 @@ Index: gcc/config/rs6000/altivec.md UNSPEC_VMULOSH))] "TARGET_ALTIVEC" "vmulosh %0,%1,%2" -@@ -1008,74 +1444,7 @@ +@@ -1008,74 +1447,7 @@ [(set_attr "type" "veccomplex")]) @@ -66845,7 +68980,7 @@ Index: gcc/config/rs6000/altivec.md (define_insn "altivec_vpkpx" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") -@@ -1082,74 +1451,95 @@ +@@ -1082,74 +1454,95 @@ (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VPKPX))] "TARGET_ALTIVEC" @@ -66996,7 +69131,7 @@ Index: gcc/config/rs6000/altivec.md "vrl<VI_char> %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -1172,26 +1562,26 @@ +@@ -1172,26 +1565,26 @@ [(set_attr "type" "vecperm")]) (define_insn "*altivec_vsl<VI_char>" @@ -67035,7 +69170,7 @@ Index: gcc/config/rs6000/altivec.md "vsra<VI_char> %0,%1,%2" [(set_attr "type" "vecsimple")]) -@@ -1233,15 +1623,29 @@ +@@ -1233,15 +1626,29 @@ "vsum4s<VI_char>s %0,%1,%2" [(set_attr "type" "veccomplex")]) @@ -67068,7 +69203,7 @@ Index: gcc/config/rs6000/altivec.md (define_insn "altivec_vsumsws" [(set (match_operand:V4SI 0 "register_operand" "=v") -@@ -1248,12 +1652,54 @@ +@@ -1248,12 +1655,54 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SI 2 "register_operand" "v")] UNSPEC_VSUMSWS)) @@ -67124,7 +69259,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:V16QI 0 "register_operand" "=v") (vec_duplicate:V16QI (vec_select:QI (match_operand:V16QI 1 "register_operand" "v") -@@ -1260,10 +1706,48 @@ +@@ -1260,10 +1709,48 @@ (parallel [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] "TARGET_ALTIVEC" @@ -67174,7 +69309,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_duplicate:V8HI (vec_select:HI (match_operand:V8HI 1 "register_operand" "v") -@@ -1270,10 +1754,48 @@ +@@ -1270,10 +1757,48 @@ (parallel [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] "TARGET_ALTIVEC" @@ -67224,7 +69359,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:V4SI 0 "register_operand" "=v") (vec_duplicate:V4SI (vec_select:SI (match_operand:V4SI 1 "register_operand" "v") -@@ -1280,10 +1802,48 @@ +@@ -1280,10 +1805,48 @@ (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] "TARGET_ALTIVEC" @@ -67274,7 +69409,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_duplicate:V4SF (vec_select:SF (match_operand:V4SF 1 "register_operand" "v") -@@ -1290,7 +1850,15 @@ +@@ -1290,7 +1853,15 @@ (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] "VECTOR_UNIT_ALTIVEC_P (V4SFmode)" @@ -67291,7 +69426,7 @@ Index: gcc/config/rs6000/altivec.md [(set_attr "type" "vecperm")]) (define_insn "altivec_vspltis<VI_char>" -@@ -1308,7 +1876,7 @@ +@@ -1308,7 +1879,7 @@ "vrfiz %0,%1" [(set_attr "type" "vecfloat")]) @@ -67300,7 +69435,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:VM 0 "register_operand" "=v") (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") -@@ -1315,10 +1883,25 @@ +@@ -1315,10 +1886,25 @@ (match_operand:V16QI 3 "register_operand" "v")] UNSPEC_VPERM))] "TARGET_ALTIVEC" @@ -67327,7 +69462,7 @@ Index: gcc/config/rs6000/altivec.md [(set (match_operand:VM 0 "register_operand" "=v") (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") -@@ -1325,6 +1908,21 @@ +@@ -1325,6 +1911,21 @@ (match_operand:V16QI 3 "register_operand" "v")] UNSPEC_VPERM_UNS))] "TARGET_ALTIVEC" @@ -67349,7 +69484,7 @@ Index: gcc/config/rs6000/altivec.md "vperm %0,%1,%2,%3" [(set_attr "type" "vecperm")]) -@@ -1335,7 +1933,12 @@ +@@ -1335,7 +1936,12 @@ (match_operand:V16QI 3 "register_operand" "")] UNSPEC_VPERM))] "TARGET_ALTIVEC" @@ -67363,7 +69498,7 @@ Index: gcc/config/rs6000/altivec.md (define_expand "vec_perm_constv16qi" [(match_operand:V16QI 0 "register_operand" "") -@@ -1476,52 +2079,72 @@ +@@ -1476,52 +2082,72 @@ "vsldoi %0,%1,%2,%3" [(set_attr "type" "vecperm")]) @@ -67466,7 +69601,7 @@ Index: gcc/config/rs6000/altivec.md [(set_attr "type" "vecperm")]) ;; Compare vectors producing a vector result and a predicate, setting CR6 to -@@ -1528,37 +2151,37 @@ +@@ -1528,37 +2154,37 @@ ;; indicate a combined status (define_insn "*altivec_vcmpequ<VI_char>_p" [(set (reg:CC 74) @@ -67522,7 +69657,7 @@ Index: gcc/config/rs6000/altivec.md "vcmpgtu<VI_char>. %0,%1,%2" [(set_attr "type" "veccmp")]) -@@ -1710,12 +2333,26 @@ +@@ -1710,12 +2336,26 @@ ;; Parallel some of the LVE* and STV*'s with unspecs because some have ;; identical rtl but different instructions-- and gcc gets confused. @@ -67550,7 +69685,7 @@ Index: gcc/config/rs6000/altivec.md "lve<VI_char>x %0,%y1" [(set_attr "type" "vecload")]) -@@ -1728,46 +2365,114 @@ +@@ -1728,46 +2368,114 @@ "lvewx %0,%y1" [(set_attr "type" "vecload")]) @@ -67675,7 +69810,7 @@ Index: gcc/config/rs6000/altivec.md "stve<VI_char>x %1,%y0" [(set_attr "type" "vecstore")]) -@@ -1779,20 +2484,28 @@ +@@ -1779,20 +2487,28 @@ [(set_attr "type" "vecstore")]) ;; Generate @@ -67714,7 +69849,7 @@ Index: gcc/config/rs6000/altivec.md }) ;; Generate -@@ -1844,7 +2557,7 @@ +@@ -1844,7 +2560,7 @@ emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero)); @@ -67723,7 +69858,7 @@ Index: gcc/config/rs6000/altivec.md DONE; }) -@@ -1860,7 +2573,7 @@ +@@ -1860,7 +2576,7 @@ emit_insn (gen_altivec_vspltisw (vzero, const0_rtx)); emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero)); @@ -67732,7 +69867,7 @@ Index: gcc/config/rs6000/altivec.md DONE; }) -@@ -1950,50 +2663,20 @@ +@@ -1950,50 +2666,20 @@ DONE; }") @@ -67795,7 +69930,7 @@ Index: gcc/config/rs6000/altivec.md (define_insn "vperm_v8hiv4si" [(set (match_operand:V4SI 0 "register_operand" "=v") (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") -@@ -2025,25 +2708,26 @@ +@@ -2025,25 +2711,26 @@ rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); @@ -67838,7 +69973,7 @@ Index: gcc/config/rs6000/altivec.md emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask)); -@@ -2060,25 +2744,26 @@ +@@ -2060,25 +2747,26 @@ rtx vzero = gen_reg_rtx (V4SImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); @@ -67881,7 +70016,7 @@ Index: gcc/config/rs6000/altivec.md emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask)); -@@ -2095,25 +2780,26 @@ +@@ -2095,25 +2783,26 @@ rtx vzero = gen_reg_rtx (V8HImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); @@ -67924,7 +70059,7 @@ Index: gcc/config/rs6000/altivec.md emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask)); -@@ -2130,25 +2816,26 @@ +@@ -2130,25 +2819,26 @@ rtx vzero = gen_reg_rtx (V4SImode); rtx mask = gen_reg_rtx (V16QImode); rtvec v = rtvec_alloc (16); @@ -67967,7 +70102,7 @@ Index: gcc/config/rs6000/altivec.md emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v))); emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask)); -@@ -2166,9 +2853,18 @@ +@@ -2166,9 +2856,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); @@ -67989,7 +70124,7 @@ Index: gcc/config/rs6000/altivec.md DONE; }") -@@ -2183,9 +2879,18 @@ +@@ -2183,9 +2882,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); @@ -68011,7 +70146,7 @@ Index: gcc/config/rs6000/altivec.md DONE; }") -@@ -2200,9 +2905,18 @@ +@@ -2200,9 +2908,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); @@ -68033,7 +70168,7 @@ Index: gcc/config/rs6000/altivec.md DONE; }") -@@ -2217,9 +2931,18 @@ +@@ -2217,9 +2934,18 @@ rtx ve = gen_reg_rtx (V8HImode); rtx vo = gen_reg_rtx (V8HImode); @@ -68055,7 +70190,7 @@ Index: gcc/config/rs6000/altivec.md DONE; }") -@@ -2234,9 +2957,18 @@ +@@ -2234,9 +2960,18 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); @@ -68077,7 +70212,7 @@ Index: gcc/config/rs6000/altivec.md DONE; }") -@@ -2251,9 +2983,18 @@ +@@ -2251,9 +2986,18 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); @@ -68099,7 +70234,7 @@ Index: gcc/config/rs6000/altivec.md DONE; }") -@@ -2268,9 +3009,18 @@ +@@ -2268,9 +3012,18 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); @@ -68121,7 +70256,7 @@ Index: gcc/config/rs6000/altivec.md DONE; }") -@@ -2285,35 +3035,28 @@ +@@ -2285,35 +3038,28 @@ rtx ve = gen_reg_rtx (V4SImode); rtx vo = gen_reg_rtx (V4SImode); @@ -68176,7 +70311,7 @@ Index: gcc/config/rs6000/altivec.md (define_expand "altivec_negv4sf2" [(use (match_operand:V4SF 0 "register_operand" "")) -@@ -2460,3 +3203,134 @@ +@@ -2460,3 +3206,243 @@ emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx)); DONE; }") @@ -68311,6 +70446,115 @@ Index: gcc/config/rs6000/altivec.md + "vbpermq %0,%1,%2" + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) ++ ++;; Decimal Integer operations ++(define_int_iterator UNSPEC_BCD_ADD_SUB [UNSPEC_BCDADD UNSPEC_BCDSUB]) ++ ++(define_int_attr bcd_add_sub [(UNSPEC_BCDADD "add") ++ (UNSPEC_BCDSUB "sub")]) ++ ++(define_code_iterator BCD_TEST [eq lt gt unordered]) ++ ++(define_insn "bcd<bcd_add_sub>" ++ [(set (match_operand:V1TI 0 "register_operand" "") ++ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "") ++ (match_operand:V1TI 2 "register_operand" "") ++ (match_operand:QI 3 "const_0_to_1_operand" "")] ++ UNSPEC_BCD_ADD_SUB)) ++ (clobber (reg:CCFP 74))] ++ "TARGET_P8_VECTOR" ++ "bcd<bcd_add_sub>. %0,%1,%2,%3" ++ [(set_attr "length" "4") ++ (set_attr "type" "vecsimple")]) ++ ++;; Use a floating point type (V2DFmode) for the compare to set CR6 so that we ++;; can use the unordered test for BCD nans and add/subtracts that overflow. An ++;; UNORDERED test on an integer type (like V1TImode) is not defined. The type ++;; probably should be one that can go in the VMX (Altivec) registers, so we ++;; can't use DDmode or DFmode. ++(define_insn "*bcd<bcd_add_sub>_test" ++ [(set (reg:CCFP 74) ++ (compare:CCFP ++ (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "v") ++ (match_operand:V1TI 2 "register_operand" "v") ++ (match_operand:QI 3 "const_0_to_1_operand" "i")] ++ UNSPEC_BCD_ADD_SUB) ++ (match_operand:V2DF 4 "zero_constant" "j"))) ++ (clobber (match_scratch:V1TI 0 "=v"))] ++ "TARGET_P8_VECTOR" ++ "bcd<bcd_add_sub>. %0,%1,%2,%3" ++ [(set_attr "length" "4") ++ (set_attr "type" "vecsimple")]) ++ ++(define_insn "*bcd<bcd_add_sub>_test2" ++ [(set (match_operand:V1TI 0 "register_operand" "=v") ++ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "v") ++ (match_operand:V1TI 2 "register_operand" "v") ++ (match_operand:QI 3 "const_0_to_1_operand" "i")] ++ UNSPEC_BCD_ADD_SUB)) ++ (set (reg:CCFP 74) ++ (compare:CCFP ++ (unspec:V2DF [(match_dup 1) ++ (match_dup 2) ++ (match_dup 3)] ++ UNSPEC_BCD_ADD_SUB) ++ (match_operand:V2DF 4 "zero_constant" "j")))] ++ "TARGET_P8_VECTOR" ++ "bcd<bcd_add_sub>. %0,%1,%2,%3" ++ [(set_attr "length" "4") ++ (set_attr "type" "vecsimple")]) ++ ++(define_expand "bcd<bcd_add_sub>_<code>" ++ [(parallel [(set (reg:CCFP 74) ++ (compare:CCFP ++ (unspec:V2DF [(match_operand:V1TI 1 "register_operand" "") ++ (match_operand:V1TI 2 "register_operand" "") ++ (match_operand:QI 3 "const_0_to_1_operand" "")] ++ UNSPEC_BCD_ADD_SUB) ++ (match_dup 4))) ++ (clobber (match_scratch:V1TI 5 ""))]) ++ (set (match_operand:SI 0 "register_operand" "") ++ (BCD_TEST:SI (reg:CCFP 74) ++ (const_int 0)))] ++ "TARGET_P8_VECTOR" ++{ ++ operands[4] = CONST0_RTX (V2DFmode); ++}) ++ ++;; Peephole2 pattern to combine a bcdadd/bcdsub that calculates the value and ++;; the bcdadd/bcdsub that tests the value. The combiner won't work since ++;; CR6 is a hard coded register. Unfortunately, all of the Altivec predicate ++;; support is hard coded to use the fixed register CR6 instead of creating ++;; a register class for CR6. ++ ++(define_peephole2 ++ [(parallel [(set (match_operand:V1TI 0 "register_operand" "") ++ (unspec:V1TI [(match_operand:V1TI 1 "register_operand" "") ++ (match_operand:V1TI 2 "register_operand" "") ++ (match_operand:QI 3 "const_0_to_1_operand" "")] ++ UNSPEC_BCD_ADD_SUB)) ++ (clobber (reg:CCFP 74))]) ++ (parallel [(set (reg:CCFP 74) ++ (compare:CCFP ++ (unspec:V2DF [(match_dup 1) ++ (match_dup 2) ++ (match_dup 3)] ++ UNSPEC_BCD_ADD_SUB) ++ (match_operand:V2DF 4 "zero_constant" ""))) ++ (clobber (match_operand:V1TI 5 "register_operand" ""))])] ++ "TARGET_P8_VECTOR" ++ [(parallel [(set (match_dup 0) ++ (unspec:V1TI [(match_dup 1) ++ (match_dup 2) ++ (match_dup 3)] ++ UNSPEC_BCD_ADD_SUB)) ++ (set (reg:CCFP 74) ++ (compare:CCFP ++ (unspec:V2DF [(match_dup 1) ++ (match_dup 2) ++ (match_dup 3)] ++ UNSPEC_BCD_ADD_SUB) ++ (match_dup 4)))])]) Index: gcc/config/rs6000/sysv4le.h =================================================================== --- a/src/gcc/config/rs6000/sysv4le.h (.../tags/gcc_4_8_2_release) @@ -68714,6 +70958,79 @@ Index: gcc/config/rs6000/dfp.md ;; Hardware support for decimal floating point operations. (define_insn "extendddtd2" +@@ -599,3 +322,72 @@ + "TARGET_DFP" + "dctfixq %0,%1" + [(set_attr "type" "fp")]) ++ ++ ++;; Decimal builtin support ++ ++(define_c_enum "unspec" ++ [UNSPEC_DDEDPD ++ UNSPEC_DENBCD ++ UNSPEC_DXEX ++ UNSPEC_DIEX ++ UNSPEC_DSCLI ++ UNSPEC_DSCRI]) ++ ++(define_mode_iterator D64_D128 [DD TD]) ++ ++(define_mode_attr dfp_suffix [(DD "") ++ (TD "q")]) ++ ++(define_insn "dfp_ddedpd_<mode>" ++ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") ++ (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i") ++ (match_operand:D64_D128 2 "gpc_reg_operand" "d")] ++ UNSPEC_DDEDPD))] ++ "TARGET_DFP" ++ "ddedpd<dfp_suffix> %1,%0,%2" ++ [(set_attr "type" "fp")]) ++ ++(define_insn "dfp_denbcd_<mode>" ++ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") ++ (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i") ++ (match_operand:D64_D128 2 "gpc_reg_operand" "d")] ++ UNSPEC_DENBCD))] ++ "TARGET_DFP" ++ "denbcd<dfp_suffix> %1,%0,%2" ++ [(set_attr "type" "fp")]) ++ ++(define_insn "dfp_dxex_<mode>" ++ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") ++ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")] ++ UNSPEC_DXEX))] ++ "TARGET_DFP" ++ "dxex<dfp_suffix> %0,%1" ++ [(set_attr "type" "fp")]) ++ ++(define_insn "dfp_diex_<mode>" ++ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") ++ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") ++ (match_operand:D64_D128 2 "gpc_reg_operand" "d")] ++ UNSPEC_DXEX))] ++ "TARGET_DFP" ++ "diex<dfp_suffix> %0,%1,%2" ++ [(set_attr "type" "fp")]) ++ ++(define_insn "dfp_dscli_<mode>" ++ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") ++ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") ++ (match_operand:QI 2 "immediate_operand" "i")] ++ UNSPEC_DSCLI))] ++ "TARGET_DFP" ++ "dscli<dfp_suffix> %0,%1,%2" ++ [(set_attr "type" "fp")]) ++ ++(define_insn "dfp_dscri_<mode>" ++ [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") ++ (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") ++ (match_operand:QI 2 "immediate_operand" "i")] ++ UNSPEC_DSCRI))] ++ "TARGET_DFP" ++ "dscri<dfp_suffix> %0,%1,%2" ++ [(set_attr "type" "fp")]) Index: gcc/config/rs6000/t-linux64 =================================================================== --- a/src/gcc/config/rs6000/t-linux64 (.../tags/gcc_4_8_2_release) @@ -68770,7 +71087,104 @@ Index: gcc/config/rs6000/sync.md (ior "logical_operand") (xor "logical_operand") (and "and_operand")]) (define_expand "mem_thread_fence" -@@ -129,16 +138,7 @@ +@@ -98,10 +107,17 @@ + "isync" + [(set_attr "type" "isync")]) + ++;; Types that we should provide atomic instructions for. ++(define_mode_iterator AINT [QI ++ HI ++ SI ++ (DI "TARGET_POWERPC64") ++ (TI "TARGET_SYNC_TI")]) ++ + ;; The control dependency used for load dependency described + ;; in B.2.3 of the Power ISA 2.06B. + (define_insn "loadsync_<mode>" +- [(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")] ++ [(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")] + UNSPECV_ISYNC) + (clobber (match_scratch:CC 1 "=y"))] + "" +@@ -109,19 +125,74 @@ + [(set_attr "type" "isync") + (set_attr "length" "12")]) + ++(define_insn "load_quadpti" ++ [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r") ++ (unspec:PTI ++ [(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))] ++ "TARGET_SYNC_TI ++ && !reg_mentioned_p (operands[0], operands[1])" ++ "lq %0,%1" ++ [(set_attr "type" "load") ++ (set_attr "length" "4")]) ++ + (define_expand "atomic_load<mode>" +- [(set (match_operand:INT1 0 "register_operand" "") ;; output +- (match_operand:INT1 1 "memory_operand" "")) ;; memory ++ [(set (match_operand:AINT 0 "register_operand" "") ;; output ++ (match_operand:AINT 1 "memory_operand" "")) ;; memory + (use (match_operand:SI 2 "const_int_operand" ""))] ;; model + "" + { ++ if (<MODE>mode == TImode && !TARGET_SYNC_TI) ++ FAIL; ++ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + + if (model == MEMMODEL_SEQ_CST) + emit_insn (gen_hwsync ()); + +- emit_move_insn (operands[0], operands[1]); ++ if (<MODE>mode != TImode) ++ emit_move_insn (operands[0], operands[1]); ++ else ++ { ++ rtx op0 = operands[0]; ++ rtx op1 = operands[1]; ++ rtx pti_reg = gen_reg_rtx (PTImode); + ++ // Can't have indexed address for 'lq' ++ if (indexed_address (XEXP (op1, 0), TImode)) ++ { ++ rtx old_addr = XEXP (op1, 0); ++ rtx new_addr = force_reg (Pmode, old_addr); ++ operands[1] = op1 = replace_equiv_address (op1, new_addr); ++ } ++ ++ emit_insn (gen_load_quadpti (pti_reg, op1)); ++ ++ /* For 4.8 we need to do explicit dword copies, even in big endian mode, ++ unless we are using the LRA register allocator. The 4.9 register ++ allocator is smart enough to assign an even/odd pair. */ ++ if (WORDS_BIG_ENDIAN && rs6000_lra_flag) ++ emit_move_insn (op0, gen_lowpart (TImode, pti_reg)); ++ else ++ { ++ rtx op0_lo = gen_lowpart (DImode, op0); ++ rtx op0_hi = gen_highpart (DImode, op0); ++ rtx pti_lo = gen_lowpart (DImode, pti_reg); ++ rtx pti_hi = gen_highpart (DImode, pti_reg); ++ ++ emit_insn (gen_rtx_CLOBBER (VOIDmode, op0)); ++ if (WORDS_BIG_ENDIAN) ++ { ++ emit_move_insn (op0_hi, pti_hi); ++ emit_move_insn (op0_lo, pti_lo); ++ } ++ else ++ { ++ emit_move_insn (op0_hi, pti_lo); ++ emit_move_insn (op0_lo, pti_hi); ++ } ++ } ++ } ++ + switch (model) + { + case MEMMODEL_RELAXED: +@@ -129,16 +200,7 @@ case MEMMODEL_CONSUME: case MEMMODEL_ACQUIRE: case MEMMODEL_SEQ_CST: @@ -68788,7 +71202,82 @@ Index: gcc/config/rs6000/sync.md break; default: gcc_unreachable (); -@@ -170,14 +170,26 @@ +@@ -146,12 +208,24 @@ + DONE; + }) + ++(define_insn "store_quadpti" ++ [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ") ++ (unspec:PTI ++ [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))] ++ "TARGET_SYNC_TI" ++ "stq %1,%0" ++ [(set_attr "type" "store") ++ (set_attr "length" "4")]) ++ + (define_expand "atomic_store<mode>" +- [(set (match_operand:INT1 0 "memory_operand" "") ;; memory +- (match_operand:INT1 1 "register_operand" "")) ;; input ++ [(set (match_operand:AINT 0 "memory_operand" "") ;; memory ++ (match_operand:AINT 1 "register_operand" "")) ;; input + (use (match_operand:SI 2 "const_int_operand" ""))] ;; model + "" + { ++ if (<MODE>mode == TImode && !TARGET_SYNC_TI) ++ FAIL; ++ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + switch (model) + { +@@ -166,18 +240,65 @@ + default: + gcc_unreachable (); + } +- emit_move_insn (operands[0], operands[1]); ++ if (<MODE>mode != TImode) ++ emit_move_insn (operands[0], operands[1]); ++ else ++ { ++ rtx op0 = operands[0]; ++ rtx op1 = operands[1]; ++ rtx pti_reg = gen_reg_rtx (PTImode); ++ ++ // Can't have indexed address for 'stq' ++ if (indexed_address (XEXP (op0, 0), TImode)) ++ { ++ rtx old_addr = XEXP (op0, 0); ++ rtx new_addr = force_reg (Pmode, old_addr); ++ operands[0] = op0 = replace_equiv_address (op0, new_addr); ++ } ++ ++ /* For 4.8 we need to do explicit dword copies, even in big endian mode, ++ unless we are using the LRA register allocator. The 4.9 register ++ allocator is smart enough to assign an even/odd pair. */ ++ if (WORDS_BIG_ENDIAN && rs6000_lra_flag) ++ emit_move_insn (pti_reg, gen_lowpart (PTImode, op1)); ++ else ++ { ++ rtx op1_lo = gen_lowpart (DImode, op1); ++ rtx op1_hi = gen_highpart (DImode, op1); ++ rtx pti_lo = gen_lowpart (DImode, pti_reg); ++ rtx pti_hi = gen_highpart (DImode, pti_reg); ++ ++ emit_insn (gen_rtx_CLOBBER (VOIDmode, pti_reg)); ++ if (WORDS_BIG_ENDIAN) ++ { ++ emit_move_insn (pti_hi, op1_hi); ++ emit_move_insn (pti_lo, op1_lo); ++ } ++ else ++ { ++ emit_move_insn (pti_hi, op1_lo); ++ emit_move_insn (pti_lo, op1_hi); ++ } ++ } ++ ++ emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg)); ++ } ++ DONE; }) @@ -68806,21 +71295,14 @@ Index: gcc/config/rs6000/sync.md + (DI "TARGET_POWERPC64")]) -(define_mode_iterator ATOMIC [SI (DI "TARGET_POWERPC64")]) -+;; Types that we should provide atomic instructions for. - -+(define_mode_iterator AINT [QI -+ HI -+ SI -+ (DI "TARGET_POWERPC64") -+ (TI "TARGET_SYNC_TI")]) -+ +- (define_insn "load_locked<mode>" - [(set (match_operand:ATOMIC 0 "gpc_reg_operand" "=r") + [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r") (unspec_volatile:ATOMIC [(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))] "" -@@ -184,21 +196,159 @@ +@@ -184,21 +305,159 @@ "<larx> %0,%y1" [(set_attr "type" "load_l")]) @@ -68986,7 +71468,7 @@ Index: gcc/config/rs6000/sync.md (match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 6 "const_int_operand" "") ;; model succ (match_operand:SI 7 "const_int_operand" "")] ;; model fail -@@ -209,9 +359,9 @@ +@@ -209,9 +468,9 @@ }) (define_expand "atomic_exchange<mode>" @@ -68999,7 +71481,7 @@ Index: gcc/config/rs6000/sync.md (match_operand:SI 3 "const_int_operand" "")] ;; model "" { -@@ -220,9 +370,9 @@ +@@ -220,9 +479,9 @@ }) (define_expand "atomic_<fetchop_name><mode>" @@ -69012,7 +71494,7 @@ Index: gcc/config/rs6000/sync.md (match_operand:SI 2 "const_int_operand" "")] ;; model "" { -@@ -232,8 +382,8 @@ +@@ -232,8 +491,8 @@ }) (define_expand "atomic_nand<mode>" @@ -69023,7 +71505,7 @@ Index: gcc/config/rs6000/sync.md (match_operand:SI 2 "const_int_operand" "")] ;; model "" { -@@ -243,10 +393,10 @@ +@@ -243,10 +502,10 @@ }) (define_expand "atomic_fetch_<fetchop_name><mode>" @@ -69038,7 +71520,7 @@ Index: gcc/config/rs6000/sync.md (match_operand:SI 3 "const_int_operand" "")] ;; model "" { -@@ -256,9 +406,9 @@ +@@ -256,9 +515,9 @@ }) (define_expand "atomic_fetch_nand<mode>" @@ -69051,7 +71533,7 @@ Index: gcc/config/rs6000/sync.md (match_operand:SI 3 "const_int_operand" "")] ;; model "" { -@@ -268,10 +418,10 @@ +@@ -268,10 +527,10 @@ }) (define_expand "atomic_<fetchop_name>_fetch<mode>" @@ -69066,7 +71548,7 @@ Index: gcc/config/rs6000/sync.md (match_operand:SI 3 "const_int_operand" "")] ;; model "" { -@@ -281,9 +431,9 @@ +@@ -281,9 +540,9 @@ }) (define_expand "atomic_nand_fetch<mode>" @@ -69227,7 +71709,7 @@ Index: gcc/config/rs6000/rs6000.md ]) ;; -@@ -123,6 +118,12 @@ +@@ -123,6 +118,22 @@ UNSPEC_LFIWZX UNSPEC_FCTIWUZ UNSPEC_GRP_END_NOP @@ -69237,10 +71719,20 @@ Index: gcc/config/rs6000/rs6000.md + UNSPEC_P8V_MTVSRD + UNSPEC_P8V_XXPERMDI + UNSPEC_P8V_RELOAD_FROM_VSX ++ UNSPEC_ADDG6S ++ UNSPEC_CDTBCD ++ UNSPEC_CBCDTD ++ UNSPEC_DIVE ++ UNSPEC_DIVEO ++ UNSPEC_DIVEU ++ UNSPEC_DIVEUO ++ UNSPEC_UNPACK_128BIT ++ UNSPEC_PACK_128BIT ++ UNSPEC_LSQ ]) ;; -@@ -142,7 +143,7 @@ +@@ -142,7 +153,7 @@ ;; Define an insn type attribute. This is used in function unit delay ;; computations. @@ -69249,7 +71741,7 @@ Index: gcc/config/rs6000/rs6000.md (const_string "integer")) ;; Define floating point instruction sub-types for use with Xfpu.md -@@ -164,7 +165,7 @@ +@@ -164,7 +175,7 @@ ;; Processor type -- this attribute must exactly match the processor_type ;; enumeration in rs6000.h. @@ -69258,7 +71750,7 @@ Index: gcc/config/rs6000/rs6000.md (const (symbol_ref "rs6000_cpu_attr"))) -@@ -197,6 +198,7 @@ +@@ -197,6 +208,7 @@ (include "power5.md") (include "power6.md") (include "power7.md") @@ -69266,7 +71758,7 @@ Index: gcc/config/rs6000/rs6000.md (include "cell.md") (include "xfpu.md") (include "a2.md") -@@ -215,7 +217,7 @@ +@@ -215,7 +227,7 @@ (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")]) ; Any supported integer mode. @@ -69275,7 +71767,7 @@ Index: gcc/config/rs6000/rs6000.md ; Any supported integer mode that fits in one register. (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")]) -@@ -223,6 +225,12 @@ +@@ -223,6 +235,12 @@ ; extend modes for DImode (define_mode_iterator QHSI [QI HI SI]) @@ -69288,7 +71780,7 @@ Index: gcc/config/rs6000/rs6000.md ; SImode or DImode, even if DImode doesn't fit in GPRs. (define_mode_iterator SDI [SI DI]) -@@ -230,6 +238,10 @@ +@@ -230,6 +248,10 @@ ; (one with a '.') will compare; and the size used for arithmetic carries. (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) @@ -69299,7 +71791,7 @@ Index: gcc/config/rs6000/rs6000.md ; Any hardware-supported floating-point mode (define_mode_iterator FP [ (SF "TARGET_HARD_FLOAT -@@ -253,6 +265,50 @@ +@@ -253,6 +275,50 @@ (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)") ]) @@ -69350,7 +71842,7 @@ Index: gcc/config/rs6000/rs6000.md ; These modes do not fit in integer registers in 32-bit mode. ; but on e500v2, the gpr are 64 bit registers (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD]) -@@ -263,6 +319,25 @@ +@@ -263,6 +329,25 @@ ; Iterator for just SF/DF (define_mode_iterator SFDF [SF DF]) @@ -69376,7 +71868,7 @@ Index: gcc/config/rs6000/rs6000.md ; Conditional returns. (define_code_iterator any_return [return simple_return]) (define_code_attr return_pred [(return "direct_return ()") -@@ -271,7 +346,14 @@ +@@ -271,7 +356,14 @@ ; Various instructions that come in SI and DI forms. ; A generic w/d attribute, for things like cmpw/cmpd. @@ -69392,7 +71884,7 @@ Index: gcc/config/rs6000/rs6000.md ; DImode bits (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) -@@ -297,6 +379,8 @@ +@@ -297,6 +389,8 @@ (define_mode_attr rreg [(SF "f") (DF "ws") @@ -69401,7 +71893,7 @@ Index: gcc/config/rs6000/rs6000.md (V4SF "wf") (V2DF "wd")]) -@@ -311,6 +395,83 @@ +@@ -311,6 +405,87 @@ (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT") (DF "TARGET_DOUBLE_FLOAT")]) @@ -69482,10 +71974,14 @@ Index: gcc/config/rs6000/rs6000.md + (V2DF "X,X,X,X,X") + (V1TI "X,X,X,X,X")]) + ++;; Mode attribute to give the correct type for integer divides ++(define_mode_attr idiv_ldiv [(SI "idiv") ++ (DI "ldiv")]) ++ ;; Start with fixed-point load and store insns. Here we put only the more ;; complex forms. Basic data transfer is done later. -@@ -324,11 +485,19 @@ +@@ -324,11 +499,19 @@ (define_insn "*zero_extend<mode>di2_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))] @@ -69507,7 +72003,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "*zero_extend<mode>di2_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") -@@ -382,6 +551,29 @@ +@@ -382,6 +565,29 @@ (const_int 0)))] "") @@ -69537,7 +72033,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "extendqidi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] -@@ -454,7 +646,15 @@ +@@ -454,7 +660,15 @@ "@ lha%U1%X1 %0,%1 extsh %0,%1" @@ -69554,7 +72050,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") -@@ -521,16 +721,47 @@ +@@ -521,16 +735,47 @@ "TARGET_POWERPC64" "") @@ -69606,7 +72102,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))] "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" -@@ -602,7 +833,15 @@ +@@ -602,7 +847,15 @@ "@ lbz%U1%X1 %0,%1 rlwinm %0,%1,0,0xff" @@ -69623,7 +72119,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") -@@ -722,7 +961,15 @@ +@@ -722,7 +975,15 @@ "@ lbz%U1%X1 %0,%1 rlwinm %0,%1,0,0xff" @@ -69640,7 +72136,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") -@@ -848,7 +1095,15 @@ +@@ -848,7 +1109,15 @@ "@ lhz%U1%X1 %0,%1 rlwinm %0,%1,0,0xffff" @@ -69657,7 +72153,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") -@@ -915,7 +1170,15 @@ +@@ -915,7 +1184,15 @@ "@ lha%U1%X1 %0,%1 extsh %0,%1" @@ -69674,7 +72170,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") -@@ -1658,7 +1921,19 @@ +@@ -1658,7 +1935,19 @@ FAIL; }) @@ -69695,7 +72191,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] "" -@@ -1935,7 +2210,9 @@ +@@ -1935,7 +2224,9 @@ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))] "TARGET_CMPB && TARGET_POPCNTB" @@ -69706,7 +72202,7 @@ Index: gcc/config/rs6000/rs6000.md (define_expand "parity<mode>2" [(set (match_operand:GPR 0 "gpc_reg_operand" "") -@@ -2412,7 +2689,7 @@ +@@ -2412,7 +2703,7 @@ (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] @@ -69715,7 +72211,7 @@ Index: gcc/config/rs6000/rs6000.md "@ mullw. %3,%1,%2 #" -@@ -2425,7 +2702,7 @@ +@@ -2425,7 +2716,7 @@ (match_operand:SI 2 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 3 ""))] @@ -69724,7 +72220,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 3) (mult:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) -@@ -2440,7 +2717,7 @@ +@@ -2440,7 +2731,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (mult:SI (match_dup 1) (match_dup 2)))] @@ -69733,7 +72229,7 @@ Index: gcc/config/rs6000/rs6000.md "@ mullw. %0,%1,%2 #" -@@ -2454,7 +2731,7 @@ +@@ -2454,7 +2745,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (mult:SI (match_dup 1) (match_dup 2)))] @@ -69742,7 +72238,31 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 0) (mult:SI (match_dup 1) (match_dup 2))) (set (match_dup 3) -@@ -3698,13 +3975,13 @@ +@@ -2469,10 +2760,7 @@ + (match_operand:GPR 2 "gpc_reg_operand" "r")))] + "" + "div<wd>u %0,%1,%2" +- [(set (attr "type") +- (cond [(match_operand:SI 0 "" "") +- (const_string "idiv")] +- (const_string "ldiv")))]) ++ [(set_attr "type" "<idiv_ldiv>")]) + + + ;; For powers of two we can do srai/aze for divide and then adjust for +@@ -2496,10 +2784,7 @@ + (match_operand:GPR 2 "gpc_reg_operand" "r")))] + "" + "div<wd> %0,%1,%2" +- [(set (attr "type") +- (cond [(match_operand:SI 0 "" "") +- (const_string "idiv")] +- (const_string "ldiv")))]) ++ [(set_attr "type" "<idiv_ldiv>")]) + + (define_expand "mod<mode>3" + [(use (match_operand:GPR 0 "gpc_reg_operand" "")) +@@ -3698,13 +3983,13 @@ (const_int 0)))] "") @@ -69758,7 +72278,7 @@ Index: gcc/config/rs6000/rs6000.md "rlw%I2nm %0,%1,%h2,0xff" [(set (attr "cell_micro") (if_then_else (match_operand:SI 2 "const_int_operand" "") -@@ -3711,7 +3988,20 @@ +@@ -3711,7 +3996,20 @@ (const_string "not") (const_string "always")))]) @@ -69780,7 +72300,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:SI (subreg:QI -@@ -3719,7 +4009,7 @@ +@@ -3719,7 +4017,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r"))] @@ -69789,7 +72309,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rlwnm. %3,%1,%2,0xff rlwinm. %3,%1,%h2,0xff -@@ -3728,6 +4018,23 @@ +@@ -3728,6 +4026,23 @@ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,8,8")]) @@ -69813,7 +72333,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI -@@ -3736,7 +4043,7 @@ +@@ -3736,7 +4051,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 ""))] @@ -69822,7 +72342,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 3) (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) -@@ -3746,7 +4053,25 @@ +@@ -3746,7 +4061,25 @@ (const_int 0)))] "") @@ -69849,7 +72369,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:SI (subreg:QI -@@ -3755,7 +4080,7 @@ +@@ -3755,7 +4088,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] @@ -69858,7 +72378,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rlwnm. %0,%1,%2,0xff rlwinm. %0,%1,%h2,0xff -@@ -3764,6 +4089,24 @@ +@@ -3764,6 +4097,24 @@ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,8,8")]) @@ -69883,7 +72403,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI -@@ -3773,7 +4116,7 @@ +@@ -3773,7 +4124,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] @@ -69892,7 +72412,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 0) (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) -@@ -3781,20 +4124,48 @@ +@@ -3781,20 +4132,48 @@ (const_int 0)))] "") @@ -69944,7 +72464,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:SI (subreg:HI -@@ -3802,7 +4173,7 @@ +@@ -3802,7 +4181,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r"))] @@ -69953,7 +72473,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rlwnm. %3,%1,%2,0xffff rlwinm. %3,%1,%h2,0xffff -@@ -3811,6 +4182,23 @@ +@@ -3811,6 +4190,23 @@ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,8,8")]) @@ -69977,7 +72497,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI -@@ -3819,7 +4207,7 @@ +@@ -3819,7 +4215,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 ""))] @@ -69986,7 +72506,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 3) (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) -@@ -3829,7 +4217,25 @@ +@@ -3829,7 +4225,25 @@ (const_int 0)))] "") @@ -70013,7 +72533,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:SI (subreg:HI -@@ -3838,7 +4244,7 @@ +@@ -3838,7 +4252,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] @@ -70022,7 +72542,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rlwnm. %0,%1,%2,0xffff rlwinm. %0,%1,%h2,0xffff -@@ -3847,6 +4253,24 @@ +@@ -3847,6 +4261,24 @@ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,8,8")]) @@ -70047,7 +72567,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:SI -@@ -3856,7 +4280,7 @@ +@@ -3856,7 +4288,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] @@ -70056,7 +72576,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 0) (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) -@@ -3864,6 +4288,23 @@ +@@ -3864,6 +4296,23 @@ (const_int 0)))] "") @@ -70080,7 +72600,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "ashlsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") -@@ -4054,7 +4495,7 @@ +@@ -4054,7 +4503,7 @@ # # #" @@ -70089,7 +72609,7 @@ Index: gcc/config/rs6000/rs6000.md (set_attr "length" "4,4,4,8,8,8")]) (define_split -@@ -4086,7 +4527,7 @@ +@@ -4086,7 +4535,7 @@ # # #" @@ -70098,7 +72618,7 @@ Index: gcc/config/rs6000/rs6000.md (set_attr "length" "4,4,4,8,8,8")]) (define_split -@@ -4177,16 +4618,25 @@ +@@ -4177,16 +4626,25 @@ (const_int 0)))] "") @@ -70127,7 +72647,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI -@@ -4195,7 +4645,7 @@ +@@ -4195,7 +4653,7 @@ (match_operand:SI 2 "const_int_operand" "i,i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] @@ -70136,7 +72656,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rlwinm. %3,%1,%s2,0xff #" -@@ -4202,6 +4652,22 @@ +@@ -4202,6 +4660,22 @@ [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -70159,7 +72679,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC -@@ -4211,7 +4677,7 @@ +@@ -4211,7 +4685,7 @@ (match_operand:SI 2 "const_int_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 ""))] @@ -70168,7 +72688,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 3) (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) -@@ -4221,7 +4687,26 @@ +@@ -4221,7 +4695,26 @@ (const_int 0)))] "") @@ -70196,7 +72716,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI -@@ -4231,7 +4716,7 @@ +@@ -4231,7 +4724,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] @@ -70205,7 +72725,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rlwinm. %0,%1,%s2,0xff #" -@@ -4238,6 +4723,23 @@ +@@ -4238,6 +4731,23 @@ [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -70229,7 +72749,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC -@@ -4248,7 +4750,7 @@ +@@ -4248,7 +4758,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] @@ -70238,7 +72758,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 0) (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) -@@ -4256,16 +4758,43 @@ +@@ -4256,16 +4766,43 @@ (const_int 0)))] "") @@ -70285,7 +72805,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI -@@ -4274,7 +4803,7 @@ +@@ -4274,7 +4811,7 @@ (match_operand:SI 2 "const_int_operand" "i,i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] @@ -70294,7 +72814,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rlwinm. %3,%1,%s2,0xffff #" -@@ -4281,6 +4810,22 @@ +@@ -4281,6 +4818,22 @@ [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -70317,7 +72837,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC -@@ -4290,7 +4835,7 @@ +@@ -4290,7 +4843,7 @@ (match_operand:SI 2 "const_int_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 ""))] @@ -70326,7 +72846,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 3) (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) -@@ -4300,7 +4845,26 @@ +@@ -4300,7 +4853,26 @@ (const_int 0)))] "") @@ -70354,7 +72874,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI -@@ -4310,7 +4874,7 @@ +@@ -4310,7 +4882,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] @@ -70363,7 +72883,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rlwinm. %0,%1,%s2,0xffff #" -@@ -4317,6 +4881,23 @@ +@@ -4317,6 +4889,23 @@ [(set_attr "type" "delayed_compare") (set_attr "length" "4,8")]) @@ -70387,7 +72907,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC -@@ -4327,7 +4908,7 @@ +@@ -4327,7 +4916,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] @@ -70396,7 +72916,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 0) (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) -@@ -4335,6 +4916,24 @@ +@@ -4335,6 +4924,24 @@ (const_int 0)))] "") @@ -70421,7 +72941,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "ashrsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") -@@ -4455,224 +5054,226 @@ +@@ -4455,224 +5062,226 @@ (const_int 0)))] "") @@ -70833,7 +73353,7 @@ Index: gcc/config/rs6000/rs6000.md [(set_attr "type" "fp")]) ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in -@@ -4742,12 +5343,14 @@ +@@ -4742,12 +5351,14 @@ ;; Use an unspec rather providing an if-then-else in RTL, to prevent the ;; compiler from optimizing -0.0 (define_insn "copysign<mode>3_fcpsgn" @@ -70853,7 +73373,7 @@ Index: gcc/config/rs6000/rs6000.md [(set_attr "type" "fp")]) ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a -@@ -4754,27 +5357,70 @@ +@@ -4754,27 +5365,70 @@ ;; fsel instruction and some auxiliary computations. Then we just have a ;; single DEFINE_INSN for fsel and the define_splits to make them if made by ;; combine. @@ -70942,7 +73462,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:SF 0 "gpc_reg_operand" "") (match_operator:SF 3 "min_max_operator" [(match_operand:SF 1 "gpc_reg_operand" "") -@@ -4904,208 +5550,9 @@ +@@ -4904,208 +5558,9 @@ "fsel %0,%1,%2,%3" [(set_attr "type" "fp")]) @@ -71151,7 +73671,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:DF 0 "gpc_reg_operand" "") (match_operator:DF 3 "min_max_operator" -@@ -5159,12 +5606,15 @@ +@@ -5159,12 +5614,15 @@ ; We don't define lfiwax/lfiwzx with the normal definition, because we ; don't want to support putting SImode in FPR registers. (define_insn "lfiwax" @@ -71171,7 +73691,7 @@ Index: gcc/config/rs6000/rs6000.md ; This split must be run before register allocation because it allocates the ; memory slot that is needed to move values to/from the FPR. We don't allocate -@@ -5186,7 +5636,8 @@ +@@ -5186,7 +5644,8 @@ rtx src = operands[1]; rtx tmp; @@ -71181,7 +73701,7 @@ Index: gcc/config/rs6000/rs6000.md tmp = convert_to_mode (DImode, src, false); else { -@@ -5235,12 +5686,15 @@ +@@ -5235,12 +5694,15 @@ (set_attr "type" "fpload")]) (define_insn "lfiwzx" @@ -71201,7 +73721,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn_and_split "floatunssi<mode>2_lfiwzx" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d") -@@ -5257,7 +5711,8 @@ +@@ -5257,7 +5719,8 @@ rtx src = operands[1]; rtx tmp; @@ -71211,7 +73731,7 @@ Index: gcc/config/rs6000/rs6000.md tmp = convert_to_mode (DImode, src, true); else { -@@ -5548,7 +6003,7 @@ +@@ -5548,7 +6011,7 @@ emit_insn (gen_stfiwx (dest, tmp)); DONE; } @@ -71220,7 +73740,7 @@ Index: gcc/config/rs6000/rs6000.md { dest = gen_lowpart (DImode, dest); emit_move_insn (dest, tmp); -@@ -5642,7 +6097,7 @@ +@@ -5642,7 +6105,7 @@ emit_insn (gen_stfiwx (dest, tmp)); DONE; } @@ -71229,7 +73749,7 @@ Index: gcc/config/rs6000/rs6000.md { dest = gen_lowpart (DImode, dest); emit_move_insn (dest, tmp); -@@ -5781,66 +6236,52 @@ +@@ -5781,66 +6244,52 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "=d") (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")] UNSPEC_FCTID))] @@ -71327,7 +73847,57 @@ Index: gcc/config/rs6000/rs6000.md ; An UNSPEC is used so we don't have to support SImode in FP registers. (define_insn "stfiwx" -@@ -6260,11 +6701,11 @@ +@@ -6084,6 +6533,49 @@ + [(set_attr "length" "8") + (set_attr "type" "fpload")]) + ++;; Define the TImode operations that can be done in a small number ++;; of instructions. The & constraints are to prevent the register ++;; allocator from allocating registers that overlap with the inputs ++;; (for example, having an input in 7,8 and an output in 6,7). We ++;; also allow for the output being the same as one of the inputs. ++ ++(define_insn "addti3" ++ [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r") ++ (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0") ++ (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))] ++ "TARGET_64BIT" ++{ ++ if (WORDS_BIG_ENDIAN) ++ return (GET_CODE (operands[2])) != CONST_INT ++ ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\" ++ : \"addic %L0,%L1,%2\;add%G2e %0,%1\"; ++ else ++ return (GET_CODE (operands[2])) != CONST_INT ++ ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\" ++ : \"addic %0,%1,%2\;add%G2e %L0,%L1\"; ++} ++ [(set_attr "type" "two") ++ (set_attr "length" "8")]) ++ ++(define_insn "subti3" ++ [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r") ++ (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I") ++ (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))] ++ "TARGET_64BIT" ++{ ++ if (WORDS_BIG_ENDIAN) ++ return (GET_CODE (operands[1]) != CONST_INT) ++ ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\" ++ : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\"; ++ else ++ return (GET_CODE (operands[1]) != CONST_INT) ++ ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\" ++ : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\"; ++} ++ [(set_attr "type" "two") ++ (set_attr "length" "8")]) ++ ++ + ;; Define the DImode operations that can be done in a small number + ;; of instructions. The & constraints are to prevent the register + ;; allocator from allocating registers that overlap with the inputs +@@ -6260,11 +6752,11 @@ [(set_attr "type" "two,three") (set_attr "length" "8,12")]) @@ -71341,7 +73911,7 @@ Index: gcc/config/rs6000/rs6000.md "* { if (REGNO (operands[0]) == REGNO (operands[1])) -@@ -6551,19 +6992,31 @@ +@@ -6551,19 +7043,31 @@ (const_int 0)))] "") @@ -71376,7 +73946,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:QI -@@ -6571,7 +7024,7 @@ +@@ -6571,7 +7075,7 @@ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 "=r,r,r,r"))] @@ -71385,7 +73955,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rldcl. %3,%1,%2,56 rldicl. %3,%1,%H2,56 -@@ -6580,6 +7033,23 @@ +@@ -6580,6 +7084,23 @@ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,8,8")]) @@ -71409,7 +73979,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI -@@ -6588,7 +7058,7 @@ +@@ -6588,7 +7109,7 @@ (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 ""))] @@ -71418,7 +73988,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 3) (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) -@@ -6598,7 +7068,25 @@ +@@ -6598,7 +7119,25 @@ (const_int 0)))] "") @@ -71445,7 +74015,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:QI -@@ -6607,7 +7095,7 @@ +@@ -6607,7 +7146,7 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] @@ -71454,7 +74024,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rldcl. %0,%1,%2,56 rldicl. %0,%1,%H2,56 -@@ -6616,6 +7104,24 @@ +@@ -6616,6 +7155,24 @@ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,8,8")]) @@ -71479,7 +74049,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI -@@ -6625,7 +7131,7 @@ +@@ -6625,7 +7182,7 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] @@ -71488,7 +74058,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 0) (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) -@@ -6633,19 +7139,48 @@ +@@ -6633,19 +7190,48 @@ (const_int 0)))] "") @@ -71540,7 +74110,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:HI -@@ -6653,7 +7188,7 @@ +@@ -6653,7 +7239,7 @@ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 "=r,r,r,r"))] @@ -71549,7 +74119,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rldcl. %3,%1,%2,48 rldicl. %3,%1,%H2,48 -@@ -6662,6 +7197,23 @@ +@@ -6662,6 +7248,23 @@ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,8,8")]) @@ -71573,7 +74143,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI -@@ -6670,7 +7222,7 @@ +@@ -6670,7 +7273,7 @@ (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 ""))] @@ -71582,7 +74152,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 3) (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) -@@ -6680,7 +7232,25 @@ +@@ -6680,7 +7283,25 @@ (const_int 0)))] "") @@ -71609,7 +74179,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:HI -@@ -6689,7 +7259,7 @@ +@@ -6689,7 +7310,7 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] @@ -71618,7 +74188,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rldcl. %0,%1,%2,48 rldicl. %0,%1,%H2,48 -@@ -6698,6 +7268,24 @@ +@@ -6698,6 +7319,24 @@ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,8,8")]) @@ -71643,7 +74213,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI -@@ -6707,7 +7295,7 @@ +@@ -6707,7 +7346,7 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] @@ -71652,7 +74222,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 0) (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) -@@ -6715,19 +7303,48 @@ +@@ -6715,19 +7354,48 @@ (const_int 0)))] "") @@ -71704,7 +74274,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:SI -@@ -6735,7 +7352,7 @@ +@@ -6735,7 +7403,7 @@ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 "=r,r,r,r"))] @@ -71713,7 +74283,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rldcl. %3,%1,%2,32 rldicl. %3,%1,%H2,32 -@@ -6744,6 +7361,23 @@ +@@ -6744,6 +7412,23 @@ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,8,8")]) @@ -71737,7 +74307,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI -@@ -6752,7 +7386,7 @@ +@@ -6752,7 +7437,7 @@ (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 ""))] @@ -71746,7 +74316,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 3) (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) -@@ -6762,7 +7396,25 @@ +@@ -6762,7 +7447,25 @@ (const_int 0)))] "") @@ -71773,7 +74343,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:SI -@@ -6771,7 +7423,7 @@ +@@ -6771,7 +7474,7 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] @@ -71782,7 +74352,7 @@ Index: gcc/config/rs6000/rs6000.md "@ rldcl. %0,%1,%2,32 rldicl. %0,%1,%H2,32 -@@ -6780,6 +7432,24 @@ +@@ -6780,6 +7483,24 @@ [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,8,8")]) @@ -71807,7 +74377,7 @@ Index: gcc/config/rs6000/rs6000.md (define_split [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") (compare:CC (zero_extend:DI -@@ -6789,7 +7459,7 @@ +@@ -6789,7 +7510,7 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] @@ -71816,7 +74386,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 0) (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) -@@ -6797,6 +7467,23 @@ +@@ -6797,6 +7518,23 @@ (const_int 0)))] "") @@ -71840,7 +74410,7 @@ Index: gcc/config/rs6000/rs6000.md (define_expand "ashldi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") -@@ -7195,10 +7882,19 @@ +@@ -7195,10 +7933,19 @@ [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "") (and:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -71863,7 +74433,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "anddi3_mc" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") -@@ -7379,12 +8075,18 @@ +@@ -7379,12 +8126,18 @@ (define_expand "iordi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -71886,7 +74456,7 @@ Index: gcc/config/rs6000/rs6000.md HOST_WIDE_INT value; rtx tmp = ((!can_create_pseudo_p () || rtx_equal_p (operands[0], operands[1])) -@@ -7408,15 +8110,21 @@ +@@ -7408,15 +8161,21 @@ emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; } @@ -71912,7 +74482,7 @@ Index: gcc/config/rs6000/rs6000.md if (non_logical_cint_operand (operands[2], DImode)) { HOST_WIDE_INT value; -@@ -7442,7 +8150,7 @@ +@@ -7442,7 +8201,7 @@ emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; } @@ -71921,7 +74491,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "*booldi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") -@@ -7678,7 +8386,385 @@ +@@ -7678,7 +8437,385 @@ (compare:CC (match_dup 0) (const_int 0)))] "") @@ -72307,7 +74877,7 @@ Index: gcc/config/rs6000/rs6000.md ;; Now define ways of moving data around. ;; Set up a register with a value from the GOT table -@@ -7765,7 +8851,31 @@ +@@ -7765,7 +8902,31 @@ mt%0 %1 mt%0 %1 nop" @@ -72340,7 +74910,7 @@ Index: gcc/config/rs6000/rs6000.md (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")]) (define_insn "*movsi_internal1_single" -@@ -7787,7 +8897,44 @@ +@@ -7787,7 +8948,44 @@ nop stfs%U0%X0 %1,%0 lfs%U1%X1 %0,%1" @@ -72386,7 +74956,7 @@ Index: gcc/config/rs6000/rs6000.md (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) ;; Split a load of a large constant into the appropriate two-insn -@@ -7822,7 +8969,7 @@ +@@ -7822,7 +9020,7 @@ cmp<wd>i %2,%0,0 mr. %0,%1 #" @@ -72395,7 +74965,7 @@ Index: gcc/config/rs6000/rs6000.md (set_attr "length" "4,4,8")]) (define_split -@@ -7850,7 +8997,26 @@ +@@ -7850,7 +9048,26 @@ mf%1 %0 mt%0 %1 nop" @@ -72423,7 +74993,7 @@ Index: gcc/config/rs6000/rs6000.md (define_expand "mov<mode>" [(set (match_operand:INT 0 "general_operand" "") -@@ -7871,7 +9037,26 @@ +@@ -7871,7 +9088,26 @@ mf%1 %0 mt%0 %1 nop" @@ -72451,7 +75021,7 @@ Index: gcc/config/rs6000/rs6000.md ;; Here is how to move condition codes around. When we store CC data in ;; an integer register or memory, we store just the high-order 4 bits. -@@ -7899,7 +9084,7 @@ +@@ -7899,7 +9135,7 @@ mf%1 %0 mt%0 %1 lwz%U1%X1 %0,%1 @@ -72460,7 +75030,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (attr "type") (cond [(eq_attr "alternative" "0,3") (const_string "cr_logical") -@@ -7912,9 +9097,23 @@ +@@ -7912,9 +9148,23 @@ (eq_attr "alternative" "9") (const_string "mtjmpr") (eq_attr "alternative" "10") @@ -72486,7 +75056,7 @@ Index: gcc/config/rs6000/rs6000.md (match_test "TARGET_MFCRF") (const_string "mfcrf") ] -@@ -7926,15 +9125,17 @@ +@@ -7926,15 +9176,17 @@ ;; can produce floating-point values in fixed-point registers. Unless the ;; value is a simple constant or already in memory, we deal with this by ;; allocating memory and copying the value explicitly via that memory location. @@ -72511,7 +75081,7 @@ Index: gcc/config/rs6000/rs6000.md "reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG -@@ -7947,10 +9148,10 @@ +@@ -7947,10 +9199,10 @@ REAL_VALUE_TYPE rv; REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); @@ -72524,7 +75094,7 @@ Index: gcc/config/rs6000/rs6000.md else operands[2] = gen_lowpart (SImode, operands[0]); -@@ -7957,11 +9158,11 @@ +@@ -7957,11 +9209,11 @@ operands[3] = gen_int_mode (l, SImode); }") @@ -72541,7 +75111,7 @@ Index: gcc/config/rs6000/rs6000.md && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)" "@ mr %0,%1 -@@ -7968,21 +9169,68 @@ +@@ -7968,21 +9220,68 @@ lwz%U1%X1 %0,%1 stw%U0%X0 %1,%0 fmr %0,%1 @@ -72619,7 +75189,7 @@ Index: gcc/config/rs6000/rs6000.md && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" "@ mr %0,%1 -@@ -7995,19 +9243,42 @@ +@@ -7995,19 +9294,42 @@ # # nop" @@ -72669,7 +75239,7 @@ Index: gcc/config/rs6000/rs6000.md "! TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG -@@ -8020,8 +9291,8 @@ +@@ -8020,8 +9342,8 @@ int endian = (WORDS_BIG_ENDIAN == 0); HOST_WIDE_INT value = INTVAL (operands[1]); @@ -72680,7 +75250,7 @@ Index: gcc/config/rs6000/rs6000.md #if HOST_BITS_PER_WIDE_INT == 32 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; #else -@@ -8031,8 +9302,8 @@ +@@ -8031,8 +9353,8 @@ }") (define_split @@ -72691,7 +75261,7 @@ Index: gcc/config/rs6000/rs6000.md "! TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG -@@ -8047,17 +9318,17 @@ +@@ -8047,17 +9369,17 @@ REAL_VALUE_TYPE rv; REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); @@ -72714,7 +75284,7 @@ Index: gcc/config/rs6000/rs6000.md "TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG -@@ -8074,7 +9345,7 @@ +@@ -8074,7 +9396,7 @@ #endif REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); @@ -72723,7 +75293,7 @@ Index: gcc/config/rs6000/rs6000.md operands[2] = gen_lowpart (DImode, operands[0]); /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ -@@ -8099,22 +9370,19 @@ +@@ -8099,22 +9421,19 @@ ;; since the D-form version of the memory instructions does not need a GPR for ;; reloading. @@ -72751,7 +75321,7 @@ Index: gcc/config/rs6000/rs6000.md xxlxor %x0,%x0,%x0 # # -@@ -8122,115 +9390,141 @@ +@@ -8122,115 +9441,141 @@ # # #" @@ -72978,7 +75548,7 @@ Index: gcc/config/rs6000/rs6000.md "@ std%U0%X0 %1,%0 ld%U1%X1 %0,%1 -@@ -8241,38 +9535,87 @@ +@@ -8241,38 +9586,87 @@ # # nop" @@ -73086,7 +75656,7 @@ Index: gcc/config/rs6000/rs6000.md "#" "&& reload_completed" [(pc)] -@@ -8557,6 +9900,252 @@ +@@ -8557,6 +9951,252 @@ operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); }") @@ -73339,7 +75909,7 @@ Index: gcc/config/rs6000/rs6000.md ;; Next come the multi-word integer load and store and the load and store ;; multiple insns. -@@ -8565,8 +10154,8 @@ +@@ -8565,8 +10205,8 @@ ;; Use of fprs is disparaged slightly otherwise reload prefers to reload ;; a gpr into a fpr instead of reloading an invalid 'Y' address (define_insn "*movdi_internal32" @@ -73350,7 +75920,7 @@ Index: gcc/config/rs6000/rs6000.md "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" -@@ -8577,15 +10166,34 @@ +@@ -8577,15 +10217,34 @@ stfd%U0%X0 %1,%0 lfd%U1%X1 %0,%1 fmr %0,%1 @@ -73389,7 +75959,7 @@ Index: gcc/config/rs6000/rs6000.md [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 1))] " -@@ -8607,14 +10215,15 @@ +@@ -8607,14 +10266,15 @@ [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "") (match_operand:DIFD 1 "input_operand" ""))] "reload_completed && !TARGET_POWERPC64 @@ -73410,7 +75980,7 @@ Index: gcc/config/rs6000/rs6000.md && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" "@ -@@ -8631,33 +10240,52 @@ +@@ -8631,33 +10291,52 @@ mt%0 %1 nop mftgpr %0,%1 @@ -73489,7 +76059,7 @@ Index: gcc/config/rs6000/rs6000.md ;; immediate value valid for a single instruction hiding in a const_double (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") -@@ -8719,14 +10347,16 @@ +@@ -8719,14 +10398,16 @@ FAIL; }") @@ -73512,7 +76082,7 @@ Index: gcc/config/rs6000/rs6000.md "* { switch (which_alternative) -@@ -8756,27 +10386,32 @@ +@@ -8756,27 +10437,32 @@ (const_string "always") (const_string "conditional")))]) @@ -73558,7 +76128,7 @@ Index: gcc/config/rs6000/rs6000.md if (GET_CODE (operands[1]) == CONST_DOUBLE) { operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); -@@ -8792,10 +10427,12 @@ +@@ -8792,10 +10478,12 @@ }") (define_split @@ -73575,7 +76145,7 @@ Index: gcc/config/rs6000/rs6000.md [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) -@@ -9651,7 +11288,7 @@ +@@ -9651,7 +11339,7 @@ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGD) (clobber (reg:SI LR_REGNO))] @@ -73584,7 +76154,7 @@ Index: gcc/config/rs6000/rs6000.md { if (TARGET_CMODEL != CMODEL_SMALL) return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;" -@@ -9723,7 +11360,7 @@ +@@ -9723,7 +11411,7 @@ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) @@ -73593,7 +76163,7 @@ Index: gcc/config/rs6000/rs6000.md " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -@@ -9746,7 +11383,8 @@ +@@ -9746,7 +11434,8 @@ (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") @@ -73603,7 +76173,7 @@ Index: gcc/config/rs6000/rs6000.md UNSPEC_TLSGD)))] "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" "addi %0,%1,%2@got@tlsgd@l" -@@ -9759,7 +11397,8 @@ +@@ -9759,7 +11448,8 @@ (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGD) (clobber (reg:SI LR_REGNO))] @@ -73613,7 +76183,7 @@ Index: gcc/config/rs6000/rs6000.md "bl %z1(%3@tlsgd)\;nop" [(set_attr "type" "branch") (set_attr "length" "8")]) -@@ -9791,7 +11430,7 @@ +@@ -9791,7 +11481,7 @@ (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")] UNSPEC_TLSLD) (clobber (reg:SI LR_REGNO))] @@ -73622,7 +76192,7 @@ Index: gcc/config/rs6000/rs6000.md { if (TARGET_CMODEL != CMODEL_SMALL) return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;" -@@ -9858,7 +11497,7 @@ +@@ -9858,7 +11548,7 @@ (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 2) @@ -73631,7 +76201,7 @@ Index: gcc/config/rs6000/rs6000.md " { operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -@@ -9881,7 +11520,9 @@ +@@ -9881,7 +11571,9 @@ (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") @@ -73642,7 +76212,7 @@ Index: gcc/config/rs6000/rs6000.md "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" "addi %0,%1,%&@got@tlsld@l" [(set_attr "length" "4")]) -@@ -9892,7 +11533,8 @@ +@@ -9892,7 +11584,8 @@ (match_operand 2 "" "g"))) (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD) (clobber (reg:SI LR_REGNO))] @@ -73652,7 +76222,7 @@ Index: gcc/config/rs6000/rs6000.md "bl %z1(%&@tlsld)\;nop" [(set_attr "type" "branch") (set_attr "length" "8")]) -@@ -9953,7 +11595,7 @@ +@@ -9953,7 +11646,7 @@ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) @@ -73661,7 +76231,7 @@ Index: gcc/config/rs6000/rs6000.md " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -@@ -9976,7 +11618,8 @@ +@@ -9976,7 +11669,8 @@ (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") @@ -73671,7 +76241,7 @@ Index: gcc/config/rs6000/rs6000.md UNSPEC_TLSGOTDTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)" -@@ -10022,7 +11665,7 @@ +@@ -10022,7 +11716,7 @@ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) @@ -73680,7 +76250,7 @@ Index: gcc/config/rs6000/rs6000.md " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); -@@ -10045,7 +11688,8 @@ +@@ -10045,7 +11739,8 @@ (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") @@ -73690,7 +76260,7 @@ Index: gcc/config/rs6000/rs6000.md UNSPEC_TLSGOTTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)" -@@ -10261,7 +11905,7 @@ +@@ -10261,7 +11956,7 @@ [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unspec:SI [(const_int 0)] UNSPEC_TOC)) (use (reg:SI 2))])] @@ -73699,7 +76269,7 @@ Index: gcc/config/rs6000/rs6000.md "* { char buf[30]; -@@ -10276,7 +11920,7 @@ +@@ -10276,7 +11971,7 @@ [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (unspec:DI [(const_int 0)] UNSPEC_TOC)) (use (reg:DI 2))])] @@ -73708,7 +76278,7 @@ Index: gcc/config/rs6000/rs6000.md "* { char buf[30]; -@@ -10306,7 +11950,7 @@ +@@ -10306,7 +12001,7 @@ [(parallel [(set (reg:SI LR_REGNO) (match_operand:SI 0 "immediate_operand" "s")) (use (unspec [(match_dup 0)] UNSPEC_TOC))])] @@ -73717,7 +76287,7 @@ Index: gcc/config/rs6000/rs6000.md && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" "") -@@ -10314,7 +11958,7 @@ +@@ -10314,7 +12009,7 @@ [(set (reg:SI LR_REGNO) (match_operand:SI 0 "immediate_operand" "s")) (use (unspec [(match_dup 0)] UNSPEC_TOC))] @@ -73726,7 +76296,7 @@ Index: gcc/config/rs6000/rs6000.md && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" "bcl 20,31,%0\\n%0:" [(set_attr "type" "branch") -@@ -10324,7 +11968,7 @@ +@@ -10324,7 +12019,7 @@ [(set (reg:SI LR_REGNO) (match_operand:SI 0 "immediate_operand" "s")) (use (unspec [(match_dup 0)] UNSPEC_TOC))] @@ -73735,7 +76305,7 @@ Index: gcc/config/rs6000/rs6000.md && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" "* { -@@ -10344,7 +11988,7 @@ +@@ -10344,7 +12039,7 @@ (label_ref (match_operand 1 "" ""))] UNSPEC_TOCPTR)) (match_dup 1)])] @@ -73744,7 +76314,7 @@ Index: gcc/config/rs6000/rs6000.md "") (define_insn "load_toc_v4_PIC_1b_normal" -@@ -10353,7 +11997,7 @@ +@@ -10353,7 +12048,7 @@ (label_ref (match_operand 1 "" ""))] UNSPEC_TOCPTR)) (match_dup 1)] @@ -73753,7 +76323,7 @@ Index: gcc/config/rs6000/rs6000.md "bcl 20,31,$+8\;.long %0-$" [(set_attr "type" "branch") (set_attr "length" "8")]) -@@ -10364,7 +12008,7 @@ +@@ -10364,7 +12059,7 @@ (label_ref (match_operand 1 "" ""))] UNSPEC_TOCPTR)) (match_dup 1)] @@ -73762,7 +76332,7 @@ Index: gcc/config/rs6000/rs6000.md "* { char name[32]; -@@ -10382,7 +12026,7 @@ +@@ -10382,7 +12077,7 @@ (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") (minus:SI (match_operand:SI 2 "immediate_operand" "s") (match_operand:SI 3 "immediate_operand" "s")))))] @@ -73771,7 +76341,7 @@ Index: gcc/config/rs6000/rs6000.md "lwz %0,%2-%3(%1)" [(set_attr "type" "load")]) -@@ -10392,7 +12036,7 @@ +@@ -10392,7 +12087,7 @@ (high:SI (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") (match_operand:SI 3 "symbol_ref_operand" "s")))))] @@ -73780,7 +76350,7 @@ Index: gcc/config/rs6000/rs6000.md "addis %0,%1,%2-%3@ha") (define_insn "load_toc_v4_PIC_3c" -@@ -10400,7 +12044,7 @@ +@@ -10400,7 +12095,7 @@ (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") (match_operand:SI 3 "symbol_ref_operand" "s"))))] @@ -73789,7 +76359,7 @@ Index: gcc/config/rs6000/rs6000.md "addi %0,%1,%2-%3@l") ;; If the TOC is shared over a translation unit, as happens with all -@@ -10542,8 +12186,13 @@ +@@ -10542,8 +12237,13 @@ operands[0] = XEXP (operands[0], 0); @@ -73804,7 +76374,7 @@ Index: gcc/config/rs6000/rs6000.md || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) { if (INTVAL (operands[2]) & CALL_LONG) -@@ -10556,12 +12205,6 @@ +@@ -10556,12 +12256,6 @@ operands[0] = force_reg (Pmode, operands[0]); break; @@ -73817,7 +76387,7 @@ Index: gcc/config/rs6000/rs6000.md default: gcc_unreachable (); } -@@ -10587,8 +12230,13 @@ +@@ -10587,8 +12281,13 @@ operands[1] = XEXP (operands[1], 0); @@ -73832,7 +76402,7 @@ Index: gcc/config/rs6000/rs6000.md || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) { if (INTVAL (operands[3]) & CALL_LONG) -@@ -10601,12 +12249,6 @@ +@@ -10601,12 +12300,6 @@ operands[1] = force_reg (Pmode, operands[1]); break; @@ -73845,7 +76415,7 @@ Index: gcc/config/rs6000/rs6000.md default: gcc_unreachable (); } -@@ -10698,136 +12340,7 @@ +@@ -10698,136 +12391,7 @@ [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -73982,7 +76552,7 @@ Index: gcc/config/rs6000/rs6000.md ;; A function pointer under System V is just a normal pointer ;; operands[0] is the function pointer ;; operands[1] is the stack size to clean up -@@ -11009,6 +12522,104 @@ +@@ -11009,6 +12573,104 @@ [(set_attr "type" "branch,branch") (set_attr "length" "4,8")]) @@ -74087,7 +76657,7 @@ Index: gcc/config/rs6000/rs6000.md ;; Call subroutine returning any type. (define_expand "untyped_call" [(parallel [(call (match_operand 0 "" "") -@@ -11056,8 +12667,41 @@ +@@ -11056,8 +12718,41 @@ gcc_assert (GET_CODE (operands[1]) == CONST_INT); operands[0] = XEXP (operands[0], 0); @@ -74129,7 +76699,7 @@ Index: gcc/config/rs6000/rs6000.md ;; this and similar patterns must be marked as using LR, otherwise ;; dataflow will try to delete the store into it. This is true ;; even when the actual reg to jump to is in CTR, when LR was -@@ -11123,7 +12767,6 @@ +@@ -11123,7 +12818,6 @@ [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -74137,7 +76707,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "*sibcall_value_local64" [(set (match_operand 0 "" "") (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) -@@ -11145,35 +12788,6 @@ +@@ -11145,35 +12839,6 @@ [(set_attr "type" "branch") (set_attr "length" "4,8")]) @@ -74173,7 +76743,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "*sibcall_nonlocal_sysv<mode>" [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c")) (match_operand 1 "" "")) -@@ -11204,27 +12818,6 @@ +@@ -11204,27 +12869,6 @@ [(set_attr "type" "branch") (set_attr "length" "4,8,4,8")]) @@ -74201,7 +76771,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "*sibcall_value_nonlocal_sysv<mode>" [(set (match_operand 0 "" "") (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c")) -@@ -11256,6 +12849,31 @@ +@@ -11256,6 +12900,31 @@ [(set_attr "type" "branch") (set_attr "length" "4,8,4,8")]) @@ -74233,7 +76803,7 @@ Index: gcc/config/rs6000/rs6000.md (define_expand "sibcall_epilogue" [(use (const_int 0))] "" -@@ -11294,7 +12912,14 @@ +@@ -11294,7 +12963,14 @@ operands[1] = gen_rtx_REG (Pmode, 0); return "st<wd>%U0%X0 %1,%0"; } @@ -74249,7 +76819,7 @@ Index: gcc/config/rs6000/rs6000.md (set_attr "length" "4")]) (define_insn "probe_stack_range<P:mode>" -@@ -11589,23 +13214,6 @@ +@@ -11589,23 +13265,6 @@ [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) @@ -74273,7 +76843,7 @@ Index: gcc/config/rs6000/rs6000.md ;; Only need to compare second words if first words equal (define_insn "*cmptf_internal1" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") -@@ -13501,6 +15109,14 @@ +@@ -13501,6 +15160,14 @@ "mfcr %0" [(set_attr "type" "mfcr")]) @@ -74288,7 +76858,7 @@ Index: gcc/config/rs6000/rs6000.md (define_insn "*stmw" [(match_parallel 0 "stmw_operation" [(set (match_operand:SI 1 "memory_operand" "=m") -@@ -13885,7 +15501,7 @@ +@@ -13885,7 +15552,7 @@ (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))] "TARGET_POPCNTD" "bpermd %0,%1,%2" @@ -74297,7 +76867,7 @@ Index: gcc/config/rs6000/rs6000.md ;; Builtin fma support. Handle -@@ -13900,6 +15516,20 @@ +@@ -13900,6 +15567,20 @@ "" "") @@ -74318,7 +76888,7 @@ Index: gcc/config/rs6000/rs6000.md ; Altivec only has fma and nfms. (define_expand "fms<mode>4" [(set (match_operand:FMA_F 0 "register_operand" "") -@@ -13910,6 +15540,20 @@ +@@ -13910,6 +15591,20 @@ "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") @@ -74339,7 +76909,7 @@ Index: gcc/config/rs6000/rs6000.md ;; If signed zeros are ignored, -(a * b - c) = -a * b + c. (define_expand "fnma<mode>4" [(set (match_operand:FMA_F 0 "register_operand" "") -@@ -13943,6 +15587,21 @@ +@@ -13943,6 +15638,21 @@ "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" "") @@ -74361,7 +76931,7 @@ Index: gcc/config/rs6000/rs6000.md ; Not an official optab name, but used from builtins. (define_expand "nfms<mode>4" [(set (match_operand:FMA_F 0 "register_operand" "") -@@ -13954,6 +15613,23 @@ +@@ -13954,6 +15664,23 @@ "" "") @@ -74385,7 +76955,7 @@ Index: gcc/config/rs6000/rs6000.md (define_expand "rs6000_get_timebase" [(use (match_operand:DI 0 "gpc_reg_operand" ""))] "" -@@ -14020,7 +15696,44 @@ +@@ -14020,7 +15747,229 @@ }) @@ -74426,11 +76996,196 @@ Index: gcc/config/rs6000/rs6000.md +}) + + ++;; Miscellaneous ISA 2.06 (power7) instructions ++(define_insn "addg6s" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "r") ++ (match_operand:SI 2 "register_operand" "r")] ++ UNSPEC_ADDG6S))] ++ "TARGET_POPCNTD" ++ "addg6s %0,%1,%2" ++ [(set_attr "type" "integer") ++ (set_attr "length" "4")]) ++ ++(define_insn "cdtbcd" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "r")] ++ UNSPEC_CDTBCD))] ++ "TARGET_POPCNTD" ++ "cdtbcd %0,%1" ++ [(set_attr "type" "integer") ++ (set_attr "length" "4")]) ++ ++(define_insn "cbcdtd" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(match_operand:SI 1 "register_operand" "r")] ++ UNSPEC_CBCDTD))] ++ "TARGET_POPCNTD" ++ "cbcdtd %0,%1" ++ [(set_attr "type" "integer") ++ (set_attr "length" "4")]) ++ ++(define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE ++ UNSPEC_DIVEO ++ UNSPEC_DIVEU ++ UNSPEC_DIVEUO]) ++ ++(define_int_attr div_extend [(UNSPEC_DIVE "e") ++ (UNSPEC_DIVEO "eo") ++ (UNSPEC_DIVEU "eu") ++ (UNSPEC_DIVEUO "euo")]) ++ ++(define_insn "div<div_extend>_<mode>" ++ [(set (match_operand:GPR 0 "register_operand" "=r") ++ (unspec:GPR [(match_operand:GPR 1 "register_operand" "r") ++ (match_operand:GPR 2 "register_operand" "r")] ++ UNSPEC_DIV_EXTEND))] ++ "TARGET_POPCNTD" ++ "div<wd><div_extend> %0,%1,%2" ++ [(set_attr "type" "<idiv_ldiv>")]) ++ ++ ++;; Pack/unpack 128-bit floating point types that take 2 scalar registers ++ ++; Type of the 64-bit part when packing/unpacking 128-bit floating point types ++(define_mode_attr FP128_64 [(TF "DF") (TD "DI")]) ++ ++(define_expand "unpack<mode>" ++ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "") ++ (unspec:<FP128_64> ++ [(match_operand:FMOVE128 1 "register_operand" "") ++ (match_operand:QI 2 "const_0_to_1_operand" "")] ++ UNSPEC_UNPACK_128BIT))] ++ "" ++ "") ++ ++;; The Advance Toolchain 7.0-3 added private builtins: __builtin_longdouble_dw0 ++;; and __builtin_longdouble_dw1 to optimize glibc. Add support for these ++;; builtins here. ++ ++(define_expand "unpacktf_0" ++ [(set (match_operand:DF 0 "nonimmediate_operand" "") ++ (unspec:DF [(match_operand:TF 1 "register_operand" "") ++ (const_int 0)] ++ UNSPEC_UNPACK_128BIT))] ++ "" ++ "") ++ ++(define_expand "unpacktf_1" ++ [(set (match_operand:DF 0 "nonimmediate_operand" "") ++ (unspec:DF [(match_operand:TF 1 "register_operand" "") ++ (const_int 1)] ++ UNSPEC_UNPACK_128BIT))] ++ "" ++ "") ++ ++(define_insn_and_split "unpack<mode>_dm" ++ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m") ++ (unspec:<FP128_64> ++ [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r") ++ (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")] ++ UNSPEC_UNPACK_128BIT))] ++ "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" ++ "#" ++ "&& reload_completed" ++ [(set (match_dup 0) (match_dup 3))] ++{ ++ unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]); ++ ++ if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno) ++ { ++ emit_note (NOTE_INSN_DELETED); ++ DONE; ++ } ++ ++ operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno); ++} ++ [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "unpack<mode>_nodm" ++ [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m") ++ (unspec:<FP128_64> ++ [(match_operand:FMOVE128 1 "register_operand" "d,d") ++ (match_operand:QI 2 "const_0_to_1_operand" "i,i")] ++ UNSPEC_UNPACK_128BIT))] ++ "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE" ++ "#" ++ "&& reload_completed" ++ [(set (match_dup 0) (match_dup 3))] ++{ ++ unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]); ++ ++ if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno) ++ { ++ emit_note (NOTE_INSN_DELETED); ++ DONE; ++ } ++ ++ operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno); ++} ++ [(set_attr "type" "fp,fpstore") ++ (set_attr "length" "4")]) ++ ++(define_insn_and_split "pack<mode>" ++ [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d") ++ (unspec:FMOVE128 ++ [(match_operand:<FP128_64> 1 "register_operand" "0,d") ++ (match_operand:<FP128_64> 2 "register_operand" "d,d")] ++ UNSPEC_PACK_128BIT))] ++ "" ++ "@ ++ fmr %L0,%2 ++ #" ++ "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])" ++ [(set (match_dup 3) (match_dup 1)) ++ (set (match_dup 4) (match_dup 2))] ++{ ++ unsigned dest_hi = REGNO (operands[0]); ++ unsigned dest_lo = dest_hi + 1; ++ ++ gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo)); ++ gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo)); ++ ++ operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi); ++ operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo); ++} ++ [(set_attr "type" "fp,fp") ++ (set_attr "length" "4,8")]) ++ ++(define_insn "unpackv1ti" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa") ++ (match_operand:QI 2 "const_0_to_1_operand" "O,i")] ++ UNSPEC_UNPACK_128BIT))] ++ "TARGET_VSX" ++{ ++ if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0) ++ return ASM_COMMENT_START " xxpermdi to same register"; ++ ++ operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3); ++ return "xxpermdi %x0,%x1,%x1,%3"; ++} ++ [(set_attr "type" "vecperm") ++ (set_attr "length" "4")]) ++ ++(define_insn "packv1ti" ++ [(set (match_operand:V1TI 0 "register_operand" "=wa") ++ (unspec:V1TI ++ [(match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")] ++ UNSPEC_PACK_128BIT))] ++ "TARGET_VSX" ++ "xxpermdi %x0,%x1,%x2,0" ++ [(set_attr "type" "vecperm") ++ (set_attr "length" "4")]) ++ ++ + (include "sync.md") (include "vector.md") (include "vsx.md") -@@ -14028,3 +15741,5 @@ +@@ -14028,3 +15977,5 @@ (include "spe.md") (include "dfp.md") (include "paired.md") @@ -76490,6 +79245,23 @@ Index: gcc/regcprop.c /* Special-case plain move instructions, since we may well be able to do the move from a different register class. */ if (set && REG_P (SET_SRC (set))) +Index: gcc/tree-ssa-operands.c +=================================================================== +--- a/src/gcc/tree-ssa-operands.c (.../tags/gcc_4_8_2_release) ++++ b/src/gcc/tree-ssa-operands.c (.../branches/gcc-4_8-branch) +@@ -626,10 +626,8 @@ + call-clobbered. */ + if (!(call_flags & ECF_NOVOPS)) + { +- /* A 'pure' or a 'const' function never call-clobbers anything. +- A 'noreturn' function might, but since we don't return anyway +- there is no point in recording that. */ +- if (!(call_flags & (ECF_PURE | ECF_CONST | ECF_NORETURN))) ++ /* A 'pure' or a 'const' function never call-clobbers anything. */ ++ if (!(call_flags & (ECF_PURE | ECF_CONST))) + add_virtual_operand (stmt, opf_def); + else if (!(call_flags & ECF_CONST)) + add_virtual_operand (stmt, opf_use); Index: libgo/configure =================================================================== --- a/src/libgo/configure (.../tags/gcc_4_8_2_release) @@ -78343,22 +81115,42 @@ Index: libgfortran/configure #include "confdefs.h" #if HAVE_DLFCN_H +Index: libgfortran/intrinsics/system_clock.c +=================================================================== +--- a/src/libgfortran/intrinsics/system_clock.c (.../tags/gcc_4_8_2_release) ++++ b/src/libgfortran/intrinsics/system_clock.c (.../branches/gcc-4_8-branch) +@@ -32,7 +32,8 @@ + /* POSIX states that CLOCK_REALTIME must be present if clock_gettime + is available, others are optional. */ + #if defined(HAVE_CLOCK_GETTIME) || defined(HAVE_CLOCK_GETTIME_LIBRT) +-#ifdef CLOCK_MONOTONIC ++#if defined(CLOCK_MONOTONIC) && defined(_POSIX_MONOTONIC_CLOCK) \ ++ && _POSIX_MONOTONIC_CLOCK >= 0 + #define GF_CLOCK_MONOTONIC CLOCK_MONOTONIC + #else + #define GF_CLOCK_MONOTONIC CLOCK_REALTIME Index: libgfortran/ChangeLog =================================================================== --- a/src/libgfortran/ChangeLog (.../tags/gcc_4_8_2_release) +++ b/src/libgfortran/ChangeLog (.../branches/gcc-4_8-branch) -@@ -1,3 +1,69 @@ +@@ -1,3 +1,75 @@ ++2014-05-03 Janne Blomqvist <jb@gcc.gnu.org> ++ ++ Backport from 4.9 ++ PR libfortran/56919 ++ * intrinsics/system_clock.c (GF_CLOCK_MONOTONIC): Check ++ _POSIX_MONOTONIC_CLOCK as well. ++ +2014-04-12 Jerry DeLisle <jvdelisle@gcc.gnu> + + Backport from mainline + PR libfortran/60810 -+ io/unit.c (is_trim_ok): If internal unit is array, do not trim. ++ * io/unit.c (is_trim_ok): If internal unit is array, do not trim. + +2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2013-11-15 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> -+ + * configure: Regenerate. + +2014-03-15 Dominique d'Humieres <dominiq@lps.ens.fr> |