1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
|
/*
* Copyright 1992, Linus Torvalds.
*
* Note: inlines with more than a single statement should be marked
* __always_inline to avoid problems with older gcc's inlining heuristics.
*/
#include "kvm_bitops.h"
#include "kvm_impl.h"
#define ADDR BITOP_ADDR(addr)
/*
* set_bit - Atomically set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* This function is atomic and may not be reordered. See __set_bit()
* if you do not require the atomic guarantees.
*
* Note: there are no guarantees that this function will not be reordered
* on non x86 architectures, so if you are writing portable code,
* make sure not to rely on its reordering guarantees.
*
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
inline void
set_bit(unsigned int nr, volatile unsigned long *addr)
{
if (IS_IMMEDIATE(nr)) {
__asm__ volatile("lock orb %1,%0"
: CONST_MASK_ADDR(nr, addr)
: "iq" ((uint8_t)CONST_MASK(nr))
: "memory");
} else {
__asm__ volatile("lock bts %1,%0"
: BITOP_ADDR(addr) : "Ir" (nr) : "memory");
}
}
/*
* __set_bit - Set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* Unlike set_bit(), this function is non-atomic and may be reordered.
* If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds.
*/
inline void
__set_bit(int nr, volatile unsigned long *addr)
{
__asm__ volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory");
}
/*
* clear_bit - Clears a bit in memory
* @nr: Bit to clear
* @addr: Address to start counting from
*
* clear_bit() is atomic and may not be reordered. However, it does
* not contain a memory barrier, so if it is used for locking purposes,
* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
* in order to ensure changes are visible on other processors.
*/
inline void
clear_bit(int nr, volatile unsigned long *addr)
{
if (IS_IMMEDIATE(nr)) {
__asm__ volatile("lock andb %1,%0"
: CONST_MASK_ADDR(nr, addr)
: "iq" ((uint8_t)~CONST_MASK(nr)));
} else {
__asm__ volatile("lock btr %1,%0"
: BITOP_ADDR(addr)
: "Ir" (nr));
}
}
inline void
__clear_bit(int nr, volatile unsigned long *addr)
{
__asm__ volatile("btr %1,%0" : ADDR : "Ir" (nr));
}
/*
* test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
inline int
test_and_set_bit(int nr, volatile unsigned long *addr)
{
int oldbit;
__asm__ volatile("lock bts %2,%1\n\t"
"sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
return (oldbit);
}
/*
* __test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
inline int
__test_and_set_bit(int nr, volatile unsigned long *addr)
{
int oldbit;
__asm__("bts %2,%1\n\t"
"sbb %0,%0"
: "=r" (oldbit), ADDR
: "Ir" (nr));
return (oldbit);
}
/*
* test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to clear
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
inline int
test_and_clear_bit(int nr, volatile unsigned long *addr)
{
int oldbit;
__asm__ volatile("lock btr %2,%1\n\t"
"sbb %0,%0"
: "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
return (oldbit);
}
/*
* __test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to clear
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
inline int
__test_and_clear_bit(int nr, volatile unsigned long *addr)
{
int oldbit;
__asm__ volatile("btr %2,%1\n\t"
"sbb %0,%0"
: "=r" (oldbit), ADDR
: "Ir" (nr));
return (oldbit);
}
inline int
constant_test_bit(unsigned int nr, const volatile unsigned long *addr)
{
return (((1UL << (nr % 64)) &
(((unsigned long *)addr)[nr / 64])) != 0);
}
inline int
variable_test_bit(int nr, volatile const unsigned long *addr)
{
int oldbit;
__asm__ volatile("bt %2,%1\n\t"
"sbb %0,%0"
: "=r" (oldbit)
: "m" (*(unsigned long *)addr), "Ir" (nr));
return (oldbit);
}
/*
* __ffs - find first set bit in word
* @word: The word to search
*
* Undefined if no bit exists, so code should check against 0 first.
*/
inline unsigned long
__ffs(unsigned long word)
{
__asm__("bsf %1,%0"
: "=r" (word)
: "rm" (word));
return (word);
}
/*
* ffz - find first zero bit in word
* @word: The word to search
*
* Undefined if no zero exists, so code should check against ~0UL first.
*/
inline unsigned long
ffz(unsigned long word)
{
__asm__("bsf %1,%0"
: "=r" (word)
: "r" (~word));
return (word);
}
/*
* __fls: find last set bit in word
* @word: The word to search
*
* Undefined if no set bit exists, so code should check against 0 first.
*/
inline unsigned long
__fls(unsigned long word)
{
__asm__("bsr %1,%0"
: "=r" (word)
: "rm" (word));
return (word);
}
|
