6450048 Fix fire hardware revision checking

6451125 Cleanup of old px and px_pci driver aliases

3 files changed, 35 insertions, 61 deletions

diff --git a/usr/src/uts/sparc/os/driver_aliases b/usr/src/uts/sparc/os/driver_aliases
index 70c71a19d8..79127666b7 100644
--- a/usr/src/uts/sparc/os/driver_aliases
+++ b/usr/src/uts/sparc/os/driver_aliases
@@ -143,15 +143,8 @@ sgen "scsa,08.bfcp"
 sgen "scsa,08.bvhci"
 ibd "ib.ipib"
 px "SUNW,sun4v-pci"
-px "pci108e,80f0"
 px "pciex108e,80f0"
 px "pciex108e,80f8"
-px_pci "pci1033,124"
-px_pci "pci1033,125"
-px_pci "pci8086,340"
-px_pci "pci8086,341"
-px_pci "pci10b5,8532"
-px_pci "pci10b5,8516"
 px_pci "pciexclass,060400"
 pxb_bcm "pciex1166,103"
 vnex "SUNW,sun4v-virtual-devices"
diff --git a/usr/src/uts/sun4u/io/px/px_lib4u.c b/usr/src/uts/sun4u/io/px/px_lib4u.c
index 732bc7ca60..c8fe7cfc51 100644
--- a/usr/src/uts/sun4u/io/px/px_lib4u.c
+++ b/usr/src/uts/sun4u/io/px/px_lib4u.c
@@ -64,7 +64,7 @@ uint64_t px_paddr_mask;
 static int px_goto_l23ready(px_t *px_p);
 static int px_goto_l0(px_t *px_p);
 static int px_pre_pwron_check(px_t *px_p);
-static uint32_t px_identity_chip(px_t *px_p);
+static uint32_t px_identity_init(px_t *px_p);
 static boolean_t px_cpr_callb(void *arg, int code);
 static uint_t px_cb_intr(caddr_t arg);
 
@@ -157,38 +157,26 @@ px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl)
 	px_t		*px_p = DIP_TO_STATE(dip);
 	caddr_t		xbc_csr_base, csr_base;
 	px_dvma_range_prop_t	px_dvma_range;
-	uint32_t	chip_id;
+	px_chip_type_t	chip_type = px_identity_init(px_p);
 	pxu_t		*pxu_p;
 
-	DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip);
+	DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p", dip);
 
-	if ((chip_id = px_identity_chip(px_p)) == PX_CHIP_UNIDENTIFIED)
-		return (DDI_FAILURE);
-
-	switch (chip_id) {
-	case FIRE_VER_10:
-		cmn_err(CE_WARN, "FIRE Hardware Version 1.0 is not supported");
-		return (DDI_FAILURE);
-	case FIRE_VER_20:
-		DBG(DBG_ATTACH, dip, "FIRE Hardware Version 2.0\n");
-		px_paddr_mask = MMU_FIRE_PADDR_MASK;
-		break;
-	case OBERON_VER_10:
-		DBG(DBG_ATTACH, dip, "Oberon Hardware Version 1.0\n");
-		px_paddr_mask = MMU_OBERON_PADDR_MASK;
-		break;
-	default:
-		cmn_err(CE_WARN, "%s%d: PX Hardware Version Unknown\n",
-		    ddi_driver_name(dip), ddi_get_instance(dip));
+	if (chip_type == PX_CHIP_UNIDENTIFIED) {
+		cmn_err(CE_WARN, "%s%d: Unrecognized Hardware Version\n",
+		    NAMEINST(dip));
 		return (DDI_FAILURE);
 	}
 
+	px_paddr_mask = (chip_type == PX_CHIP_FIRE) ? MMU_FIRE_PADDR_MASK :
+	    MMU_OBERON_PADDR_MASK;
+
 	/*
 	 * Allocate platform specific structure and link it to
 	 * the px state structure.
 	 */
 	pxu_p = kmem_zalloc(sizeof (pxu_t), KM_SLEEP);
-	pxu_p->chip_id = chip_id;
+	pxu_p->chip_type = chip_type;
 	pxu_p->portid  = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
 	    "portid", -1);
 
@@ -1982,7 +1970,7 @@ l0_done:
  * the identity defaults to PX_CHIP_UNIDENTIFIED.
  */
 static uint32_t
-px_identity_chip(px_t *px_p)
+px_identity_init(px_t *px_p)
 {
 	dev_info_t	*dip = px_p->px_dip;
 	char		*name = ddi_binding_name(dip);
@@ -1992,22 +1980,22 @@ px_identity_chip(px_t *px_p)
 	    "module-revision#", 0);
 
 	/* Check for Fire driver binding name */
-	if ((strcmp(name, "pci108e,80f0") == 0) ||
-	    (strcmp(name, "pciex108e,80f0") == 0)) {
-		DBG(DBG_ATTACH, dip, "px_identity_chip: %s%d: "
-		    "name %s module-revision %d\n", ddi_driver_name(dip),
-		    ddi_get_instance(dip), name, revision);
+	if (strcmp(name, "pciex108e,80f0") == 0) {
+		DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: "
+		    "(FIRE), module-revision %d\n", NAMEINST(dip),
+		    revision);
 
-		return (PX_CHIP_ID(PX_CHIP_FIRE, revision, 0x00));
+		return ((revision >= FIRE_MOD_REV_20) ?
+		    PX_CHIP_FIRE : PX_CHIP_UNIDENTIFIED);
 	}
 
 	/* Check for Oberon driver binding name */
 	if (strcmp(name, "pciex108e,80f8") == 0) {
-		DBG(DBG_ATTACH, dip, "px_identity_chip: %s%d: "
-		    "name %s module-revision %d\n", ddi_driver_name(dip),
-		    ddi_get_instance(dip), name, revision);
+		DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: "
+		    "(OBERON), module-revision %d\n", NAMEINST(dip),
+		    revision);
 
-		return (PX_CHIP_ID(PX_CHIP_OBERON, revision, 0x00));
+		return (PX_CHIP_OBERON);
 	}
 
 	DBG(DBG_ATTACH, dip, "%s%d: Unknown PCI Express Host bridge %s %x\n",
diff --git a/usr/src/uts/sun4u/io/px/px_lib4u.h b/usr/src/uts/sun4u/io/px/px_lib4u.h
index e8333f7e01..cb4567302d 100644
--- a/usr/src/uts/sun4u/io/px/px_lib4u.h
+++ b/usr/src/uts/sun4u/io/px/px_lib4u.h
@@ -71,6 +71,15 @@ typedef struct px_cb_list {
 	struct px_cb_list	*next;
 } px_cb_list_t;
 
+/* IO chip type */
+typedef enum {
+	PX_CHIP_UNIDENTIFIED = 0,
+	PX_CHIP_FIRE = 1,
+	PX_CHIP_OBERON = 2
+} px_chip_type_t;
+
+#define	PX_CHIP_TYPE(pxu_p)	((pxu_p)->chip_type)
+
 typedef struct px_cb {
 	px_cb_list_t	*pxl;		/* linked list px */
 	kmutex_t	cb_mutex;	/* lock for CB */
@@ -81,7 +90,7 @@ typedef struct px_cb {
 } px_cb_t;
 
 typedef struct pxu {
-	uint32_t	chip_id;
+	px_chip_type_t	chip_type;
 	uint8_t		portid;
 	uint16_t	tsb_cookie;
 	uint32_t	tsb_size;
@@ -262,30 +271,14 @@ typedef	struct eq_rec {
 #define	PX_BDF_TO_CFGADDR(bdf, offset) (((bdf) << PX_PA_BDF_SHIFT) + (offset))
 
 /*
- * The sequence of the chip_type appearance is significant.
- * There are code depending on it: PX_CHIP_TYPE(pxu_p) < PX_CHIP_FIRE.
- */
-typedef enum {
-	PX_CHIP_UNIDENTIFIED = 0,
-	PX_CHIP_FIRE = 1,
-	PX_CHIP_OBERON = 2
-} px_chip_id_t;
-
-/*
- * [msb]                                [lsb]
- * 0x00 <chip_type> <version#> <module-revision#>
+ * Fire hardware specific version definitions.
+ * All Fire versions > 2.0 will be numerically greater than FIRE_MOD_REV_20
  */
-#define	PX_CHIP_ID(t, v, m)	(((t) << 16) | ((v) << 8) | (m))
-#define	PX_CHIP_TYPE(pxu_p)	(((pxu_p)->chip_id) >> 16)
-#define	PX_CHIP_REV(pxu_p)	 (((pxu_p)->chip_id) & 0xFF)
-#define	PX_CHIP_VER(pxu_p)	 ((((pxu_p)->chip_id) >> 8) & 0xFF)
+#define	FIRE_MOD_REV_20	0x03
 
 /*
- * Fire hardware specific version definitions.
+ * Oberon specific definitions.
  */
-#define	FIRE_VER_10	PX_CHIP_ID(PX_CHIP_FIRE, 0x01, 0x00)
-#define	FIRE_VER_20	PX_CHIP_ID(PX_CHIP_FIRE, 0x03, 0x00)
-#define	OBERON_VER_10	PX_CHIP_ID(PX_CHIP_OBERON, 0x00, 0x00)
 #define	OBERON_RANGE_PROP_MASK	0x7fff
 
 /*