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-rw-r--r--usr/src/pkgdefs/Makefile1
-rw-r--r--usr/src/pkgdefs/SUNWmyri10ge/Makefile39
-rw-r--r--usr/src/pkgdefs/SUNWmyri10ge/pkginfo.tmpl45
-rw-r--r--usr/src/pkgdefs/SUNWmyri10ge/postinstall.tmpl30
-rw-r--r--usr/src/pkgdefs/SUNWmyri10ge/preremove.tmpl28
-rw-r--r--usr/src/pkgdefs/SUNWmyri10ge/prototype_com47
-rw-r--r--usr/src/pkgdefs/SUNWmyri10ge/prototype_i38646
-rw-r--r--usr/src/pkgdefs/SUNWmyri10ge/prototype_sparc46
-rw-r--r--usr/src/pkgdefs/common_files/i.minorperm_i3864
-rw-r--r--usr/src/pkgdefs/common_files/i.minorperm_sparc4
-rw-r--r--usr/src/tools/opensolaris/license-list1
-rw-r--r--usr/src/uts/common/Makefile.files6
-rw-r--r--usr/src/uts/common/Makefile.rules7
-rw-r--r--usr/src/uts/common/io/myri10ge/THIRDPARTYLICENSE4
-rw-r--r--usr/src/uts/common/io/myri10ge/THIRDPARTYLICENSE.descrip1
-rw-r--r--usr/src/uts/common/io/myri10ge/drv/myri10ge.c6093
-rw-r--r--usr/src/uts/common/io/myri10ge/drv/myri10ge_lro.c366
-rw-r--r--usr/src/uts/common/io/myri10ge/drv/myri10ge_var.h533
-rw-r--r--usr/src/uts/common/io/myri10ge/drv/myri10ge_version.h45
-rw-r--r--usr/src/uts/common/io/myri10ge/firmware/mcp_gen_header.h121
-rw-r--r--usr/src/uts/common/io/myri10ge/firmware/myri10ge_mcp.h520
-rw-r--r--usr/src/uts/common/io/myri10ge/firmware/rss_eth_z8e.h9403
-rw-r--r--usr/src/uts/common/io/myri10ge/firmware/rss_ethp_z8e.h9488
-rw-r--r--usr/src/uts/intel/Makefile.intel.shared1
-rw-r--r--usr/src/uts/intel/myri10ge/Makefile94
-rw-r--r--usr/src/uts/intel/os/minor_perm2
-rw-r--r--usr/src/uts/sparc/Makefile.sparc.shared1
-rw-r--r--usr/src/uts/sparc/myri10ge/Makefile94
-rw-r--r--usr/src/uts/sparc/os/minor_perm2
29 files changed, 27072 insertions, 0 deletions
diff --git a/usr/src/pkgdefs/Makefile b/usr/src/pkgdefs/Makefile
index 60c1015608..667a13fc50 100644
--- a/usr/src/pkgdefs/Makefile
+++ b/usr/src/pkgdefs/Makefile
@@ -347,6 +347,7 @@ COMMON_SUBDIRS= \
SUNWmptsas \
SUNWmrsas \
SUNWmxfe \
+ SUNWmyri10ge \
SUNWncar \
SUNWncau \
SUNWndmpr \
diff --git a/usr/src/pkgdefs/SUNWmyri10ge/Makefile b/usr/src/pkgdefs/SUNWmyri10ge/Makefile
new file mode 100644
index 0000000000..928e8820e0
--- /dev/null
+++ b/usr/src/pkgdefs/SUNWmyri10ge/Makefile
@@ -0,0 +1,39 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+include ../Makefile.com
+
+TMPLFILES += postinstall preremove
+DATAFILES += depend
+LICENSEFILES += ../../uts/common/io/myri10ge/THIRDPARTYLICENSE
+
+.KEEP_STATE:
+
+all: $(FILES)
+install: all pkg
+
+include ../Makefile.targ
+include ../Makefile.prtarg
diff --git a/usr/src/pkgdefs/SUNWmyri10ge/pkginfo.tmpl b/usr/src/pkgdefs/SUNWmyri10ge/pkginfo.tmpl
new file mode 100644
index 0000000000..62a305d64c
--- /dev/null
+++ b/usr/src/pkgdefs/SUNWmyri10ge/pkginfo.tmpl
@@ -0,0 +1,45 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+PKG=SUNWmyri10ge
+NAME=Myricom 10Gb NIC Driver
+ARCH="ISA"
+VERSION="ONVERS,REV=0.0.0"
+SUNW_PRODNAME="SunOS"
+SUNW_PRODVERS="RELEASE/VERSION"
+SUNW_PKGVERS="1.0"
+SUNW_PKGTYPE="root"
+MAXINST="1000"
+CATEGORY=system
+VENDOR="Sun Microsystems, Inc."
+DESC="Myricom 10 Gigabit Ethernet Adapter Driver"
+CLASSES="none preserve"
+HOTLINE="Please contact your local service provider"
+EMAIL=""
+BASEDIR=/
+SUNW_PKG_ALLZONES="true"
+SUNW_PKG_HOLLOW="true"
+SUNW_PKG_THISZONE="false"
diff --git a/usr/src/pkgdefs/SUNWmyri10ge/postinstall.tmpl b/usr/src/pkgdefs/SUNWmyri10ge/postinstall.tmpl
new file mode 100644
index 0000000000..6f540666ad
--- /dev/null
+++ b/usr/src/pkgdefs/SUNWmyri10ge/postinstall.tmpl
@@ -0,0 +1,30 @@
+#!/sbin/sh
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+# Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+include drv_utils
+
+pkg_drvadd -i \
+ '"pci14c1,8" "pciex14c1,8" "pci14c1,9" "pciex14c1,9"' \
+ -m '* 0666 root sys' myri10ge || exit 1
diff --git a/usr/src/pkgdefs/SUNWmyri10ge/preremove.tmpl b/usr/src/pkgdefs/SUNWmyri10ge/preremove.tmpl
new file mode 100644
index 0000000000..d4d2fd45bb
--- /dev/null
+++ b/usr/src/pkgdefs/SUNWmyri10ge/preremove.tmpl
@@ -0,0 +1,28 @@
+#!/sbin/sh
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+# Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+include drv_utils
+
+pkg_drvrem myri10ge || exit 1
diff --git a/usr/src/pkgdefs/SUNWmyri10ge/prototype_com b/usr/src/pkgdefs/SUNWmyri10ge/prototype_com
new file mode 100644
index 0000000000..1d9f37c965
--- /dev/null
+++ b/usr/src/pkgdefs/SUNWmyri10ge/prototype_com
@@ -0,0 +1,47 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+#
+# This required package information file contains a list of package contents.
+# The 'pkgmk' command uses this file to identify the contents of a package
+# and their location on the development machine when building the package.
+# Can be created via a text editor or through use of the 'pkgproto' command.
+
+#!search <pathname pathname ...> # where to find pkg objects
+#!include <filename> # include another 'prototype' file
+#!default <mode> <owner> <group> # default used if not specified on entry
+#!<param>=<value> # puts parameter in pkg environment
+#
+#
+i pkginfo
+i copyright
+i depend
+i postinstall
+i preremove
+
+# Myricom 10Gb NIC driver
+d none kernel 0755 root sys
+d none kernel/drv 0755 root sys
diff --git a/usr/src/pkgdefs/SUNWmyri10ge/prototype_i386 b/usr/src/pkgdefs/SUNWmyri10ge/prototype_i386
new file mode 100644
index 0000000000..045760d22a
--- /dev/null
+++ b/usr/src/pkgdefs/SUNWmyri10ge/prototype_i386
@@ -0,0 +1,46 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+#
+# This required package information file contains a list of package contents.
+# The 'pkgmk' command uses this file to identify the contents of a package
+# and their location on the development machine when building the package.
+# Can be created via a text editor or through use of the 'pkgproto' command.
+
+#!search <pathname pathname ...> # where to find pkg objects
+#!include <filename> # include another 'prototype' file
+#!default <mode> <owner> <group> # default used if not specified on entry
+#!<param>=<value> # puts parameter in pkg environment
+
+#
+# Include ISA independent files (prototype_com)
+#
+!include prototype_com
+
+# Myricom 10Gb NIC driver
+f none kernel/drv/myri10ge 0755 root sys
+d none kernel/drv/amd64 0755 root sys
+f none kernel/drv/amd64/myri10ge 0755 root sys
diff --git a/usr/src/pkgdefs/SUNWmyri10ge/prototype_sparc b/usr/src/pkgdefs/SUNWmyri10ge/prototype_sparc
new file mode 100644
index 0000000000..e822120386
--- /dev/null
+++ b/usr/src/pkgdefs/SUNWmyri10ge/prototype_sparc
@@ -0,0 +1,46 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+
+#
+# Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+#
+# This required package information file contains a list of package contents.
+# The 'pkgmk' command uses this file to identify the contents of a package
+# and their location on the development machine when building the package.
+# Can be created via a text editor or through use of the 'pkgproto' command.
+
+#!search <pathname pathname ...> # where to find pkg objects
+#!include <filename> # include another 'prototype' file
+#!default <mode> <owner> <group> # default used if not specified on entry
+#!<param>=<value> # puts parameter in pkg environment
+
+#
+# Include ISA independent files (prototype_com)
+#
+!include prototype_com
+#
+
+# Myricom 10Gb NIC driver
+d none kernel/drv/sparcv9 0755 root sys
+f none kernel/drv/sparcv9/myri10ge 0755 root sys
diff --git a/usr/src/pkgdefs/common_files/i.minorperm_i386 b/usr/src/pkgdefs/common_files/i.minorperm_i386
index da51a3f109..9572480f9a 100644
--- a/usr/src/pkgdefs/common_files/i.minorperm_i386
+++ b/usr/src/pkgdefs/common_files/i.minorperm_i386
@@ -103,6 +103,7 @@ systrace:systrace 0600 root sys 0644 root sys /dev/dtrace/provider/systrace
clone:bge 0600 root sys 0666 root sys /dev/bge
clone:igb 0600 root sys 0666 root sys /dev/igb
clone:ixgbe 0600 root sys 0666 root sys /dev/ixgbe
+clone:myri10ge 0600 root sys 0666 root sys /dev/myri10ge
clone:rge 0600 root sys 0666 root sys /dev/rge
clone:xge 0600 root sys 0666 root sys /dev/xge
clone:nge 0600 root sys 0666 root sys /dev/nge
@@ -134,6 +135,7 @@ clone:mxfe 0600 root sys 0666 root sys /dev/mxfe
bge:* 0600 root sys 0666 root sys /dev/bge*
igb:* 0600 root sys 0666 root sys /dev/igb*
ixgbe:* 0600 root sys 0666 root sys /dev/ixgbe*
+myri10ge:* 0600 root sys 0666 root sys /dev/myri10ge*
rge:* 0600 root sys 0666 root sys /dev/rge*
xge:* 0600 root sys 0666 root sys /dev/xge*
nge:* 0600 root sys 0666 root sys /dev/nge*
@@ -293,6 +295,7 @@ cpuid:self
clone:bge
clone:igb
clone:ixgbe
+clone:myri10ge
clone:rge
clone:xge
clone:nge
@@ -325,6 +328,7 @@ clone:mxfe
bge:*
igb:*
ixgbe:*
+myri10ge:*
rge:*
xge:*
nge:*
diff --git a/usr/src/pkgdefs/common_files/i.minorperm_sparc b/usr/src/pkgdefs/common_files/i.minorperm_sparc
index 3a8ad588f8..b8480f9070 100644
--- a/usr/src/pkgdefs/common_files/i.minorperm_sparc
+++ b/usr/src/pkgdefs/common_files/i.minorperm_sparc
@@ -95,6 +95,7 @@ clone:qfe 0600 root sys 0666 root sys /dev/qfe
clone:bge 0600 root sys 0666 root sys /dev/bge
clone:igb 0600 root sys 0666 root sys /dev/igb
clone:ixgbe 0600 root sys 0666 root sys /dev/ixgbe
+clone:myri10ge 0600 root sys 0666 root sys /dev/myri10ge
clone:rge 0600 root sys 0666 root sys /dev/rge
clone:xge 0600 root sys 0666 root sys /dev/xge
clone:nge 0600 root sys 0666 root sys /dev/nge
@@ -110,6 +111,7 @@ clone:rtls 0600 root sys 0666 root sys /dev/rtls
bge:* 0600 root sys 0666 root sys /dev/bge*
igb:* 0600 root sys 0666 root sys /dev/igb*
ixgbe:* 0600 root sys 0666 root sys /dev/ixgbe*
+myri10ge:* 0600 root sys 0666 root sys /dev/myri10ge*
rge:* 0600 root sys 0666 root sys /dev/rge*
xge:* 0600 root sys 0666 root sys /dev/xge*
nge:* 0600 root sys 0666 root sys /dev/nge*
@@ -280,6 +282,7 @@ bscv:*
clone:bge
clone:igb
clone:ixgbe
+clone:myri10ge
clone:rge
clone:xge
clone:nge
@@ -295,6 +298,7 @@ clone:rtls
bge:*
igb:*
ixgbe:*
+myri10ge:*
rge:*
xge:*
nge:*
diff --git a/usr/src/tools/opensolaris/license-list b/usr/src/tools/opensolaris/license-list
index 57eee74470..ecfa5c3cd6 100644
--- a/usr/src/tools/opensolaris/license-list
+++ b/usr/src/tools/opensolaris/license-list
@@ -158,6 +158,7 @@ usr/src/uts/common/io/mega_sas/THIRDPARTYLICENSE
usr/src/uts/common/io/mr_sas/THIRDPARTYLICENSE
usr/src/uts/common/io/mxfe/THIRDPARTYLICENSE
usr/src/uts/common/io/ntxn/THIRDPARTYLICENSE
+usr/src/uts/common/io/myri10ge/THIRDPARTYLICENSE
usr/src/uts/common/io/pcan/THIRDPARTYLICENSE
usr/src/uts/common/io/pcwl/THIRDPARTYLICENSE
usr/src/uts/common/io/ppp/THIRDPARTYLICENSE
diff --git a/usr/src/uts/common/Makefile.files b/usr/src/uts/common/Makefile.files
index d06ac373ba..0076d096ee 100644
--- a/usr/src/uts/common/Makefile.files
+++ b/usr/src/uts/common/Makefile.files
@@ -1914,6 +1914,12 @@ ISCSI_INITIATOR_OBJS = chap.o iscsi_io.o iscsi_thread.o \
#
NTXN_OBJS = unm_nic_init.o unm_gem.o unm_nic_hw.o unm_ndd.o \
unm_nic_main.o unm_nic_isr.o unm_nic_ctx.o niu.o
+
+#
+# Myricom 10Gb NIC driver module
+#
+MYRI10GE_OBJS = myri10ge.o myri10ge_lro.o
+
# nulldriver module
#
NULLDRIVER_OBJS = nulldriver.o
diff --git a/usr/src/uts/common/Makefile.rules b/usr/src/uts/common/Makefile.rules
index 0049e42f49..874e1eebb2 100644
--- a/usr/src/uts/common/Makefile.rules
+++ b/usr/src/uts/common/Makefile.rules
@@ -1203,6 +1203,10 @@ $(OBJS_DIR)/%.o: $(UTSBASE)/common/io/ntxn/%.c
$(COMPILE.c) -o $@ $<
$(CTFCONVERT_O)
+$(OBJS_DIR)/%.o: $(UTSBASE)/common/io/myri10ge/drv/%.c
+ $(COMPILE.c) -o $@ $<
+ $(CTFCONVERT_O)
+
$(OBJS_DIR)/%.o: $(UTSBASE)/common/ipp/%.c
$(COMPILE.c) -o $@ $<
$(CTFCONVERT_O)
@@ -2287,6 +2291,9 @@ $(LINTS_DIR)/%.ln: $(UTSBASE)/common/io/ixgbe/%.c
$(LINTS_DIR)/%.ln: $(UTSBASE)/common/io/ntxn/%.c
@($(LHEAD) $(LINT.c) $< $(LTAIL))
+$(LINTS_DIR)/%.ln: $(UTSBASE)/common/io/myri10ge/drv/%.c
+ @($(LHEAD) $(LINT.c) $< $(LTAIL))
+
$(LINTS_DIR)/%.ln: $(UTSBASE)/common/ipp/%.c
@($(LHEAD) $(LINT.c) $< $(LTAIL))
diff --git a/usr/src/uts/common/io/myri10ge/THIRDPARTYLICENSE b/usr/src/uts/common/io/myri10ge/THIRDPARTYLICENSE
new file mode 100644
index 0000000000..c6f6575713
--- /dev/null
+++ b/usr/src/uts/common/io/myri10ge/THIRDPARTYLICENSE
@@ -0,0 +1,4 @@
+/*
+ * Copyright 2007-2009 Myricom, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
diff --git a/usr/src/uts/common/io/myri10ge/THIRDPARTYLICENSE.descrip b/usr/src/uts/common/io/myri10ge/THIRDPARTYLICENSE.descrip
new file mode 100644
index 0000000000..bc4b03ee85
--- /dev/null
+++ b/usr/src/uts/common/io/myri10ge/THIRDPARTYLICENSE.descrip
@@ -0,0 +1 @@
+myri10ge - 10Gb NIC driver for Myricom's Ethernet cards
diff --git a/usr/src/uts/common/io/myri10ge/drv/myri10ge.c b/usr/src/uts/common/io/myri10ge/drv/myri10ge.c
new file mode 100644
index 0000000000..1d3cc845d8
--- /dev/null
+++ b/usr/src/uts/common/io/myri10ge/drv/myri10ge.c
@@ -0,0 +1,6093 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007-2009 Myricom, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef lint
+static const char __idstring[] =
+ "@(#)$Id: myri10ge.c,v 1.186 2009-06-29 13:47:22 gallatin Exp $";
+#endif
+
+#define MXGEFW_NDIS
+#include "myri10ge_var.h"
+#include "rss_eth_z8e.h"
+#include "rss_ethp_z8e.h"
+#include "mcp_gen_header.h"
+
+#define MYRI10GE_MAX_ETHER_MTU 9014
+
+#define MYRI10GE_ETH_STOPPED 0
+#define MYRI10GE_ETH_STOPPING 1
+#define MYRI10GE_ETH_STARTING 2
+#define MYRI10GE_ETH_RUNNING 3
+#define MYRI10GE_ETH_OPEN_FAILED 4
+#define MYRI10GE_ETH_SUSPENDED_RUNNING 5
+
+static int myri10ge_small_bytes = 510;
+static int myri10ge_intr_coal_delay = 125;
+static int myri10ge_flow_control = 1;
+#if #cpu(i386) || defined __i386 || defined i386 || \
+ defined __i386__ || #cpu(x86_64) || defined __x86_64__
+static int myri10ge_nvidia_ecrc_enable = 1;
+#endif
+static int myri10ge_mtu_override = 0;
+static int myri10ge_tx_copylen = 512;
+static int myri10ge_deassert_wait = 1;
+static int myri10ge_verbose = 0;
+static int myri10ge_watchdog_reset = 0;
+static int myri10ge_use_msix = 1;
+static int myri10ge_max_slices = -1;
+static int myri10ge_use_msi = 1;
+int myri10ge_force_firmware = 0;
+static boolean_t myri10ge_use_lso = B_TRUE;
+static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
+static int myri10ge_tx_hash = 1;
+static int myri10ge_lro = 1;
+static int myri10ge_lro_cnt = 8;
+int myri10ge_lro_max_aggr = 2;
+static int myri10ge_lso_copy = 0;
+static mblk_t *myri10ge_send_wrapper(void *arg, mblk_t *mp);
+int myri10ge_tx_handles_initial = 128;
+
+static kmutex_t myri10ge_param_lock;
+static void* myri10ge_db_lastfree;
+
+static int myri10ge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
+static int myri10ge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
+static int myri10ge_quiesce(dev_info_t *dip);
+
+DDI_DEFINE_STREAM_OPS(myri10ge_ops, nulldev, nulldev, myri10ge_attach,
+ myri10ge_detach, nodev, NULL, D_MP, NULL, myri10ge_quiesce);
+
+
+static struct modldrv modldrv = {
+ &mod_driverops,
+ "Myricom 10G driver (10GbE)",
+ &myri10ge_ops,
+};
+
+
+static struct modlinkage modlinkage = {
+ MODREV_1,
+ {&modldrv, NULL},
+};
+
+unsigned char myri10ge_broadcastaddr[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+
+static ddi_dma_attr_t myri10ge_misc_dma_attr = {
+ DMA_ATTR_V0, /* version number. */
+ (uint64_t)0, /* low address */
+ (uint64_t)0xffffffffffffffffULL, /* high address */
+ (uint64_t)0x7ffffff, /* address counter max */
+ (uint64_t)4096, /* alignment */
+ (uint_t)0x7f, /* burstsizes for 32b and 64b xfers */
+ (uint32_t)0x1, /* minimum transfer size */
+ (uint64_t)0x7fffffff, /* maximum transfer size */
+ (uint64_t)0x7fffffff, /* maximum segment size */
+ 1, /* scatter/gather list length */
+ 1, /* granularity */
+ 0 /* attribute flags */
+};
+
+/*
+ * The Myri10GE NIC has the following constraints on receive buffers:
+ * 1) Buffers which cross a 4KB boundary must be aligned to 4KB
+ * 2) Buffers which are not aligned to 4KB must not cross a 4KB boundary
+ */
+
+static ddi_dma_attr_t myri10ge_rx_jumbo_dma_attr = {
+ DMA_ATTR_V0, /* version number. */
+ (uint64_t)0, /* low address */
+ (uint64_t)0xffffffffffffffffULL, /* high address */
+ (uint64_t)0x7ffffff, /* address counter max */
+ (uint64_t)4096, /* alignment */
+ (uint_t)0x7f, /* burstsizes for 32b and 64b xfers */
+ (uint32_t)0x1, /* minimum transfer size */
+ (uint64_t)0x7fffffff, /* maximum transfer size */
+ UINT64_MAX, /* maximum segment size */
+ 1, /* scatter/gather list length */
+ 1, /* granularity */
+ 0 /* attribute flags */
+};
+
+static ddi_dma_attr_t myri10ge_rx_std_dma_attr = {
+ DMA_ATTR_V0, /* version number. */
+ (uint64_t)0, /* low address */
+ (uint64_t)0xffffffffffffffffULL, /* high address */
+ (uint64_t)0x7ffffff, /* address counter max */
+#if defined sparc64 || defined __sparcv9
+ (uint64_t)4096, /* alignment */
+#else
+ (uint64_t)0x80, /* alignment */
+#endif
+ (uint_t)0x7f, /* burstsizes for 32b and 64b xfers */
+ (uint32_t)0x1, /* minimum transfer size */
+ (uint64_t)0x7fffffff, /* maximum transfer size */
+#if defined sparc64 || defined __sparcv9
+ UINT64_MAX, /* maximum segment size */
+#else
+ (uint64_t)0xfff, /* maximum segment size */
+#endif
+ 1, /* scatter/gather list length */
+ 1, /* granularity */
+ 0 /* attribute flags */
+};
+
+static ddi_dma_attr_t myri10ge_tx_dma_attr = {
+ DMA_ATTR_V0, /* version number. */
+ (uint64_t)0, /* low address */
+ (uint64_t)0xffffffffffffffffULL, /* high address */
+ (uint64_t)0x7ffffff, /* address counter max */
+ (uint64_t)1, /* alignment */
+ (uint_t)0x7f, /* burstsizes for 32b and 64b xfers */
+ (uint32_t)0x1, /* minimum transfer size */
+ (uint64_t)0x7fffffff, /* maximum transfer size */
+ UINT64_MAX, /* maximum segment size */
+ INT32_MAX, /* scatter/gather list length */
+ 1, /* granularity */
+ 0 /* attribute flags */
+};
+
+#if defined sparc64 || defined __sparcv9
+#define WC 0
+#else
+#define WC 1
+#endif
+
+struct ddi_device_acc_attr myri10ge_dev_access_attr = {
+ DDI_DEVICE_ATTR_V0, /* version */
+ DDI_NEVERSWAP_ACC, /* endian flash */
+#if WC
+ DDI_MERGING_OK_ACC /* data order */
+#else
+ DDI_STRICTORDER_ACC
+#endif
+};
+
+static void myri10ge_watchdog(void *arg);
+
+#ifdef MYRICOM_PRIV
+int myri10ge_mtu = MYRI10GE_MAX_ETHER_MTU + MXGEFW_PAD + VLAN_TAGSZ;
+#else
+int myri10ge_mtu = ETHERMAX + MXGEFW_PAD + VLAN_TAGSZ;
+#endif
+int myri10ge_bigbufs_initial = 1024;
+int myri10ge_bigbufs_max = 4096;
+
+
+caddr_t
+myri10ge_dma_alloc(dev_info_t *dip, size_t len,
+ ddi_dma_attr_t *attr, ddi_device_acc_attr_t *accattr,
+ uint_t alloc_flags, int bind_flags, struct myri10ge_dma_stuff *dma,
+ int warn, int (*wait)(caddr_t))
+{
+ caddr_t kaddr;
+ size_t real_length;
+ ddi_dma_cookie_t cookie;
+ uint_t count;
+ int err;
+
+ err = ddi_dma_alloc_handle(dip, attr, wait,
+ NULL, &dma->handle);
+ if (err != DDI_SUCCESS) {
+ if (warn)
+ cmn_err(CE_WARN,
+ "myri10ge: ddi_dma_alloc_handle failed\n");
+ goto abort_with_nothing;
+ }
+
+ err = ddi_dma_mem_alloc(dma->handle, len, accattr, alloc_flags,
+ wait, NULL, &kaddr, &real_length,
+ &dma->acc_handle);
+ if (err != DDI_SUCCESS) {
+ if (warn)
+ cmn_err(CE_WARN,
+ "myri10ge: ddi_dma_mem_alloc failed\n");
+ goto abort_with_handle;
+ }
+
+ err = ddi_dma_addr_bind_handle(dma->handle, NULL, kaddr, len,
+ bind_flags, wait, NULL, &cookie, &count);
+
+ if (err != DDI_SUCCESS) {
+ if (warn)
+ cmn_err(CE_WARN,
+ "myri10ge: ddi_dma_addr_bind_handle failed\n");
+ goto abort_with_mem;
+ }
+
+ if (count != 1) {
+ if (warn)
+ cmn_err(CE_WARN,
+ "myri10ge: got too many dma segments ");
+ goto abort_with_bind;
+ }
+ dma->low = htonl(MYRI10GE_LOWPART_TO_U32(cookie.dmac_laddress));
+ dma->high = htonl(MYRI10GE_HIGHPART_TO_U32(cookie.dmac_laddress));
+ return (kaddr);
+
+abort_with_bind:
+ (void) ddi_dma_unbind_handle(dma->handle);
+
+abort_with_mem:
+ ddi_dma_mem_free(&dma->acc_handle);
+
+abort_with_handle:
+ ddi_dma_free_handle(&dma->handle);
+abort_with_nothing:
+ if (warn) {
+ cmn_err(CE_WARN, "myri10ge: myri10ge_dma_alloc failed.\n ");
+ cmn_err(CE_WARN, "args: dip=%p len=0x%lx ddi_dma_attr=%p\n",
+ (void*) dip, len, (void*) attr);
+ cmn_err(CE_WARN,
+ "args: ddi_device_acc_attr=%p alloc_flags=0x%x\n",
+ (void*) accattr, alloc_flags);
+ cmn_err(CE_WARN, "args: bind_flags=0x%x dmastuff=%p",
+ bind_flags, (void*) dma);
+ }
+ return (NULL);
+
+}
+
+void
+myri10ge_dma_free(struct myri10ge_dma_stuff *dma)
+{
+ (void) ddi_dma_unbind_handle(dma->handle);
+ ddi_dma_mem_free(&dma->acc_handle);
+ ddi_dma_free_handle(&dma->handle);
+}
+
+static inline void
+myri10ge_pio_copy32(void *to, uint32_t *from32, size_t size)
+{
+ register volatile uint32_t *to32;
+ size_t i;
+
+ to32 = (volatile uint32_t *) to;
+ for (i = (size / 4); i; i--) {
+ *to32 = *from32;
+ to32++;
+ from32++;
+ }
+}
+
+#if defined(_LP64)
+static inline void
+myri10ge_pio_copy64(void *to, uint64_t *from64, size_t size)
+{
+ register volatile uint64_t *to64;
+ size_t i;
+
+ to64 = (volatile uint64_t *) to;
+ for (i = (size / 8); i; i--) {
+ *to64 = *from64;
+ to64++;
+ from64++;
+ }
+}
+#endif
+
+/*
+ * This routine copies memory from the host to the NIC.
+ * The "size" argument must always be a multiple of
+ * the size of long (4 or 8 bytes), and to/from must also
+ * be naturally aligned.
+ */
+static inline void
+myri10ge_pio_copy(void *to, void *from, size_t size)
+{
+#if !defined(_LP64)
+ ASSERT((size % 4) == 0);
+ myri10ge_pio_copy32(to, (uint32_t *)from, size);
+#else
+ ASSERT((size % 8) == 0);
+ myri10ge_pio_copy64(to, (uint64_t *)from, size);
+#endif
+}
+
+
+/*
+ * Due to various bugs in Solaris (especially bug 6186772 where the
+ * TCP/UDP checksum is calculated incorrectly on mblk chains with more
+ * than two elements), and the design bug where hardware checksums are
+ * ignored on mblk chains with more than 2 elements, we need to
+ * allocate private pool of physically contiguous receive buffers.
+ */
+
+static void
+myri10ge_jpool_init(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_jpool_stuff *jpool = &ss->jpool;
+
+ bzero(jpool, sizeof (*jpool));
+ mutex_init(&jpool->mtx, NULL, MUTEX_DRIVER,
+ ss->mgp->icookie);
+ jpool->head = NULL;
+}
+
+static void
+myri10ge_jpool_fini(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_jpool_stuff *jpool = &ss->jpool;
+
+ if (jpool->head != NULL) {
+ cmn_err(CE_WARN,
+ "%s: BUG! myri10ge_jpool_fini called on non-empty pool\n",
+ ss->mgp->name);
+ }
+ mutex_destroy(&jpool->mtx);
+}
+
+
+/*
+ * copy an array of mcp_kreq_ether_recv_t's to the mcp. Copy
+ * at most 32 bytes at a time, so as to avoid involving the software
+ * pio handler in the nic. We re-write the first segment's low
+ * DMA address to mark it valid only after we write the entire chunk
+ * in a burst
+ */
+static inline void
+myri10ge_submit_8rx(mcp_kreq_ether_recv_t *dst, mcp_kreq_ether_recv_t *src)
+{
+ src->addr_low |= BE_32(1);
+ myri10ge_pio_copy(dst, src, 4 * sizeof (*src));
+ mb();
+ myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof (*src));
+ mb();
+ src->addr_low &= ~(BE_32(1));
+ dst->addr_low = src->addr_low;
+ mb();
+}
+
+static void
+myri10ge_pull_jpool(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_jpool_stuff *jpool = &ss->jpool;
+ struct myri10ge_jpool_entry *jtail, *j, *jfree;
+ volatile uintptr_t *putp;
+ uintptr_t put;
+ int i;
+
+ /* find tail */
+ jtail = NULL;
+ if (jpool->head != NULL) {
+ j = jpool->head;
+ while (j->next != NULL)
+ j = j->next;
+ jtail = j;
+ }
+
+ /*
+ * iterate over all per-CPU caches, and add contents into
+ * jpool
+ */
+ for (i = 0; i < MYRI10GE_MAX_CPUS; i++) {
+ /* take per-CPU free list */
+ putp = (void *)&jpool->cpu[i & MYRI10GE_MAX_CPU_MASK].head;
+ if (*putp == NULL)
+ continue;
+ put = atomic_swap_ulong(putp, 0);
+ jfree = (struct myri10ge_jpool_entry *)put;
+
+ /* append to pool */
+ if (jtail == NULL) {
+ jpool->head = jfree;
+ } else {
+ jtail->next = jfree;
+ }
+ j = jfree;
+ while (j->next != NULL)
+ j = j->next;
+ jtail = j;
+ }
+}
+
+/*
+ * Transfers buffers from the free pool to the nic
+ * Must be called holding the jpool mutex.
+ */
+
+static inline void
+myri10ge_restock_jumbos(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_jpool_stuff *jpool = &ss->jpool;
+ struct myri10ge_jpool_entry *j;
+ myri10ge_rx_ring_t *rx;
+ int i, idx, limit;
+
+ rx = &ss->rx_big;
+ limit = ss->j_rx_cnt + (rx->mask + 1);
+
+ for (i = rx->cnt; i != limit; i++) {
+ idx = i & (rx->mask);
+ j = jpool->head;
+ if (j == NULL) {
+ myri10ge_pull_jpool(ss);
+ j = jpool->head;
+ if (j == NULL) {
+ break;
+ }
+ }
+ jpool->head = j->next;
+ rx->info[idx].j = j;
+ rx->shadow[idx].addr_low = j->dma.low;
+ rx->shadow[idx].addr_high = j->dma.high;
+ /* copy 4 descriptors (32-bytes) to the mcp at a time */
+ if ((idx & 7) == 7) {
+ myri10ge_submit_8rx(&rx->lanai[idx - 7],
+ &rx->shadow[idx - 7]);
+ }
+ }
+ rx->cnt = i;
+}
+
+/*
+ * Transfer buffers from the nic to the free pool.
+ * Should be called holding the jpool mutex
+ */
+
+static inline void
+myri10ge_unstock_jumbos(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_jpool_stuff *jpool = &ss->jpool;
+ struct myri10ge_jpool_entry *j;
+ myri10ge_rx_ring_t *rx;
+ int i;
+
+ mutex_enter(&jpool->mtx);
+ rx = &ss->rx_big;
+
+ for (i = 0; i < rx->mask + 1; i++) {
+ j = rx->info[i].j;
+ rx->info[i].j = NULL;
+ if (j == NULL)
+ continue;
+ j->next = jpool->head;
+ jpool->head = j;
+ }
+ mutex_exit(&jpool->mtx);
+
+}
+
+
+/*
+ * Free routine which is called when the mblk allocated via
+ * esballoc() is freed. Here we return the jumbo buffer
+ * to the free pool, and possibly pass some jumbo buffers
+ * to the nic
+ */
+
+static void
+myri10ge_jfree_rtn(void *arg)
+{
+ struct myri10ge_jpool_entry *j = (struct myri10ge_jpool_entry *)arg;
+ struct myri10ge_jpool_stuff *jpool;
+ volatile uintptr_t *putp;
+ uintptr_t old, new;
+
+ jpool = &j->ss->jpool;
+
+ /* prepend buffer locklessly to per-CPU freelist */
+ putp = (void *)&jpool->cpu[CPU->cpu_seqid & MYRI10GE_MAX_CPU_MASK].head;
+ new = (uintptr_t)j;
+ do {
+ old = *putp;
+ j->next = (void *)old;
+ } while (atomic_cas_ulong(putp, old, new) != old);
+}
+
+static void
+myri10ge_remove_jbuf(struct myri10ge_jpool_entry *j)
+{
+ (void) ddi_dma_unbind_handle(j->dma_handle);
+ ddi_dma_mem_free(&j->acc_handle);
+ ddi_dma_free_handle(&j->dma_handle);
+ kmem_free(j, sizeof (*j));
+}
+
+
+/*
+ * Allocates one physically contiguous descriptor
+ * and add it to the jumbo buffer pool.
+ */
+
+static int
+myri10ge_add_jbuf(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_jpool_entry *j;
+ struct myri10ge_jpool_stuff *jpool = &ss->jpool;
+ ddi_dma_attr_t *rx_dma_attr;
+ size_t real_length;
+ ddi_dma_cookie_t cookie;
+ uint_t count;
+ int err;
+
+ if (myri10ge_mtu < 2048)
+ rx_dma_attr = &myri10ge_rx_std_dma_attr;
+ else
+ rx_dma_attr = &myri10ge_rx_jumbo_dma_attr;
+
+again:
+ j = (struct myri10ge_jpool_entry *)
+ kmem_alloc(sizeof (*j), KM_SLEEP);
+ err = ddi_dma_alloc_handle(ss->mgp->dip, rx_dma_attr,
+ DDI_DMA_DONTWAIT, NULL, &j->dma_handle);
+ if (err != DDI_SUCCESS)
+ goto abort_with_j;
+
+ err = ddi_dma_mem_alloc(j->dma_handle, myri10ge_mtu,
+ &myri10ge_dev_access_attr, DDI_DMA_STREAMING, DDI_DMA_DONTWAIT,
+ NULL, &j->buf, &real_length, &j->acc_handle);
+ if (err != DDI_SUCCESS)
+ goto abort_with_handle;
+
+ err = ddi_dma_addr_bind_handle(j->dma_handle, NULL, j->buf,
+ real_length, DDI_DMA_READ|DDI_DMA_STREAMING, DDI_DMA_DONTWAIT,
+ NULL, &cookie, &count);
+ if (err != DDI_SUCCESS)
+ goto abort_with_mem;
+
+ /*
+ * Make certain std MTU buffers do not cross a 4KB boundary:
+ *
+ * Setting dma_attr_align=4096 will do this, but the system
+ * will only allocate 1 RX buffer per 4KB page, rather than 2.
+ * Setting dma_attr_granular=4096 *seems* to work around this,
+ * but I'm paranoid about future systems no longer honoring
+ * this, so fall back to the safe, but memory wasting way if a
+ * buffer crosses a 4KB boundary.
+ */
+
+ if (rx_dma_attr == &myri10ge_rx_std_dma_attr &&
+ rx_dma_attr->dma_attr_align != 4096) {
+ uint32_t start, end;
+
+ start = MYRI10GE_LOWPART_TO_U32(cookie.dmac_laddress);
+ end = start + myri10ge_mtu;
+ if (((end >> 12) != (start >> 12)) && (start & 4095U)) {
+ printf("std buffer crossed a 4KB boundary!\n");
+ myri10ge_remove_jbuf(j);
+ rx_dma_attr->dma_attr_align = 4096;
+ rx_dma_attr->dma_attr_seg = UINT64_MAX;
+ goto again;
+ }
+ }
+
+ j->dma.low =
+ htonl(MYRI10GE_LOWPART_TO_U32(cookie.dmac_laddress));
+ j->dma.high =
+ htonl(MYRI10GE_HIGHPART_TO_U32(cookie.dmac_laddress));
+ j->ss = ss;
+
+
+ j->free_func.free_func = myri10ge_jfree_rtn;
+ j->free_func.free_arg = (char *)j;
+ mutex_enter(&jpool->mtx);
+ j->next = jpool->head;
+ jpool->head = j;
+ jpool->num_alloc++;
+ mutex_exit(&jpool->mtx);
+ return (0);
+
+abort_with_mem:
+ ddi_dma_mem_free(&j->acc_handle);
+
+abort_with_handle:
+ ddi_dma_free_handle(&j->dma_handle);
+
+abort_with_j:
+ kmem_free(j, sizeof (*j));
+
+ /*
+ * If an allocation failed, perhaps it failed because it could
+ * not satisfy granularity requirement. Disable that, and
+ * try agin.
+ */
+ if (rx_dma_attr == &myri10ge_rx_std_dma_attr &&
+ rx_dma_attr->dma_attr_align != 4096) {
+ cmn_err(CE_NOTE,
+ "!alloc failed, reverting to gran=1\n");
+ rx_dma_attr->dma_attr_align = 4096;
+ rx_dma_attr->dma_attr_seg = UINT64_MAX;
+ goto again;
+ }
+ return (err);
+}
+
+static int
+myri10ge_jfree_cnt(struct myri10ge_jpool_stuff *jpool)
+{
+ int i;
+ struct myri10ge_jpool_entry *j;
+
+ mutex_enter(&jpool->mtx);
+ j = jpool->head;
+ i = 0;
+ while (j != NULL) {
+ i++;
+ j = j->next;
+ }
+ mutex_exit(&jpool->mtx);
+ return (i);
+}
+
+static int
+myri10ge_add_jbufs(struct myri10ge_slice_state *ss, int num, int total)
+{
+ struct myri10ge_jpool_stuff *jpool = &ss->jpool;
+ int allocated = 0;
+ int err;
+ int needed;
+
+ /*
+ * if total is set, user wants "num" jbufs in the pool,
+ * otherwise the user wants to "num" additional jbufs
+ * added to the pool
+ */
+ if (total && jpool->num_alloc) {
+ allocated = myri10ge_jfree_cnt(jpool);
+ needed = num - allocated;
+ } else {
+ needed = num;
+ }
+
+ while (needed > 0) {
+ needed--;
+ err = myri10ge_add_jbuf(ss);
+ if (err == 0) {
+ allocated++;
+ }
+ }
+ return (allocated);
+}
+
+static void
+myri10ge_remove_jbufs(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_jpool_stuff *jpool = &ss->jpool;
+ struct myri10ge_jpool_entry *j;
+
+ mutex_enter(&jpool->mtx);
+ myri10ge_pull_jpool(ss);
+ while (jpool->head != NULL) {
+ jpool->num_alloc--;
+ j = jpool->head;
+ jpool->head = j->next;
+ myri10ge_remove_jbuf(j);
+ }
+ mutex_exit(&jpool->mtx);
+}
+
+static void
+myri10ge_carve_up_jbufs_into_small_ring(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_jpool_stuff *jpool = &ss->jpool;
+ struct myri10ge_jpool_entry *j = NULL;
+ caddr_t ptr;
+ uint32_t dma_low, dma_high;
+ int idx, len;
+ unsigned int alloc_size;
+
+ dma_low = dma_high = len = 0;
+ alloc_size = myri10ge_small_bytes + MXGEFW_PAD;
+ ptr = NULL;
+ for (idx = 0; idx < ss->rx_small.mask + 1; idx++) {
+ /* Allocate a jumbo frame and carve it into small frames */
+ if (len < alloc_size) {
+ mutex_enter(&jpool->mtx);
+ /* remove jumbo from freelist */
+ j = jpool->head;
+ jpool->head = j->next;
+ /* place it onto small list */
+ j->next = ss->small_jpool;
+ ss->small_jpool = j;
+ mutex_exit(&jpool->mtx);
+ len = myri10ge_mtu;
+ dma_low = ntohl(j->dma.low);
+ dma_high = ntohl(j->dma.high);
+ ptr = j->buf;
+ }
+ ss->rx_small.info[idx].ptr = ptr;
+ ss->rx_small.shadow[idx].addr_low = htonl(dma_low);
+ ss->rx_small.shadow[idx].addr_high = htonl(dma_high);
+ len -= alloc_size;
+ ptr += alloc_size;
+ dma_low += alloc_size;
+ }
+}
+
+/*
+ * Return the jumbo bufs we carved up for small to the jumbo pool
+ */
+
+static void
+myri10ge_release_small_jbufs(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_jpool_stuff *jpool = &ss->jpool;
+ struct myri10ge_jpool_entry *j = NULL;
+
+ mutex_enter(&jpool->mtx);
+ while (ss->small_jpool != NULL) {
+ j = ss->small_jpool;
+ ss->small_jpool = j->next;
+ j->next = jpool->head;
+ jpool->head = j;
+ }
+ mutex_exit(&jpool->mtx);
+ ss->jbufs_for_smalls = 0;
+}
+
+static int
+myri10ge_add_tx_handle(struct myri10ge_slice_state *ss)
+{
+ myri10ge_tx_ring_t *tx = &ss->tx;
+ struct myri10ge_priv *mgp = ss->mgp;
+ struct myri10ge_tx_dma_handle *handle;
+ int err;
+
+ handle = kmem_zalloc(sizeof (*handle), KM_SLEEP);
+ err = ddi_dma_alloc_handle(mgp->dip,
+ &myri10ge_tx_dma_attr,
+ DDI_DMA_SLEEP, NULL,
+ &handle->h);
+ if (err) {
+ static int limit = 0;
+ if (limit == 0)
+ cmn_err(CE_WARN, "%s: Falled to alloc tx dma handle\n",
+ mgp->name);
+ limit++;
+ kmem_free(handle, sizeof (*handle));
+ return (err);
+ }
+ mutex_enter(&tx->handle_lock);
+ MYRI10GE_SLICE_STAT_INC(tx_handles_alloced);
+ handle->next = tx->free_tx_handles;
+ tx->free_tx_handles = handle;
+ mutex_exit(&tx->handle_lock);
+ return (DDI_SUCCESS);
+}
+
+static void
+myri10ge_remove_tx_handles(struct myri10ge_slice_state *ss)
+{
+ myri10ge_tx_ring_t *tx = &ss->tx;
+ struct myri10ge_tx_dma_handle *handle;
+ mutex_enter(&tx->handle_lock);
+
+ handle = tx->free_tx_handles;
+ while (handle != NULL) {
+ tx->free_tx_handles = handle->next;
+ ddi_dma_free_handle(&handle->h);
+ kmem_free(handle, sizeof (*handle));
+ handle = tx->free_tx_handles;
+ MYRI10GE_SLICE_STAT_DEC(tx_handles_alloced);
+ }
+ mutex_exit(&tx->handle_lock);
+ if (MYRI10GE_SLICE_STAT(tx_handles_alloced) != 0) {
+ cmn_err(CE_WARN, "%s: %d tx dma handles allocated at close\n",
+ ss->mgp->name,
+ (int)MYRI10GE_SLICE_STAT(tx_handles_alloced));
+ }
+}
+
+static void
+myri10ge_free_tx_handles(myri10ge_tx_ring_t *tx,
+ struct myri10ge_tx_dma_handle_head *list)
+{
+ mutex_enter(&tx->handle_lock);
+ list->tail->next = tx->free_tx_handles;
+ tx->free_tx_handles = list->head;
+ mutex_exit(&tx->handle_lock);
+}
+
+static void
+myri10ge_free_tx_handle_slist(myri10ge_tx_ring_t *tx,
+ struct myri10ge_tx_dma_handle *handle)
+{
+ struct myri10ge_tx_dma_handle_head list;
+
+ if (handle == NULL)
+ return;
+ list.head = handle;
+ list.tail = handle;
+ while (handle != NULL) {
+ list.tail = handle;
+ handle = handle->next;
+ }
+ myri10ge_free_tx_handles(tx, &list);
+}
+
+static int
+myri10ge_alloc_tx_handles(struct myri10ge_slice_state *ss, int count,
+ struct myri10ge_tx_dma_handle **ret)
+{
+ myri10ge_tx_ring_t *tx = &ss->tx;
+ struct myri10ge_tx_dma_handle *handle;
+ int err, i;
+
+ mutex_enter(&tx->handle_lock);
+ for (i = 0; i < count; i++) {
+ handle = tx->free_tx_handles;
+ while (handle == NULL) {
+ mutex_exit(&tx->handle_lock);
+ err = myri10ge_add_tx_handle(ss);
+ if (err != DDI_SUCCESS) {
+ goto abort_with_handles;
+ }
+ mutex_enter(&tx->handle_lock);
+ handle = tx->free_tx_handles;
+ }
+ tx->free_tx_handles = handle->next;
+ handle->next = *ret;
+ *ret = handle;
+ }
+ mutex_exit(&tx->handle_lock);
+ return (DDI_SUCCESS);
+
+abort_with_handles:
+ myri10ge_free_tx_handle_slist(tx, *ret);
+ return (err);
+}
+
+
+/*
+ * Frees DMA resources associated with the send ring
+ */
+static void
+myri10ge_unprepare_tx_ring(struct myri10ge_slice_state *ss)
+{
+ myri10ge_tx_ring_t *tx;
+ struct myri10ge_tx_dma_handle_head handles;
+ size_t bytes;
+ int idx;
+
+ tx = &ss->tx;
+ handles.head = NULL;
+ handles.tail = NULL;
+ for (idx = 0; idx < ss->tx.mask + 1; idx++) {
+ if (tx->info[idx].m) {
+ (void) ddi_dma_unbind_handle(tx->info[idx].handle->h);
+ handles.head = tx->info[idx].handle;
+ if (handles.tail == NULL)
+ handles.tail = tx->info[idx].handle;
+ freeb(tx->info[idx].m);
+ tx->info[idx].m = 0;
+ tx->info[idx].handle = 0;
+ }
+ tx->cp[idx].va = NULL;
+ myri10ge_dma_free(&tx->cp[idx].dma);
+ }
+ bytes = sizeof (*tx->cp) * (tx->mask + 1);
+ kmem_free(tx->cp, bytes);
+ tx->cp = NULL;
+ if (handles.head != NULL)
+ myri10ge_free_tx_handles(tx, &handles);
+ myri10ge_remove_tx_handles(ss);
+}
+
+/*
+ * Allocates DMA handles associated with the send ring
+ */
+static inline int
+myri10ge_prepare_tx_ring(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_tx_dma_handle *handles;
+ int h;
+ size_t bytes;
+
+ bytes = sizeof (*ss->tx.cp) * (ss->tx.mask + 1);
+ ss->tx.cp = kmem_zalloc(bytes, KM_SLEEP);
+ if (ss->tx.cp == NULL) {
+ cmn_err(CE_WARN,
+ "%s: Failed to allocate tx copyblock storage\n",
+ ss->mgp->name);
+ return (DDI_FAILURE);
+ }
+
+
+ /* allocate the TX copyblocks */
+ for (h = 0; h < ss->tx.mask + 1; h++) {
+ ss->tx.cp[h].va = myri10ge_dma_alloc(ss->mgp->dip,
+ 4096, &myri10ge_rx_jumbo_dma_attr,
+ &myri10ge_dev_access_attr, DDI_DMA_STREAMING,
+ DDI_DMA_WRITE|DDI_DMA_STREAMING, &ss->tx.cp[h].dma, 1,
+ DDI_DMA_DONTWAIT);
+ if (ss->tx.cp[h].va == NULL) {
+ cmn_err(CE_WARN, "%s: Failed to allocate tx "
+ "copyblock %d\n", ss->mgp->name, h);
+ goto abort_with_copyblocks;
+ }
+ }
+ /* pre-allocate transmit handles */
+ handles = NULL;
+ (void) myri10ge_alloc_tx_handles(ss, myri10ge_tx_handles_initial,
+ &handles);
+ if (handles != NULL)
+ myri10ge_free_tx_handle_slist(&ss->tx, handles);
+
+ return (DDI_SUCCESS);
+
+abort_with_copyblocks:
+ while (h > 0) {
+ h--;
+ myri10ge_dma_free(&ss->tx.cp[h].dma);
+ }
+
+ bytes = sizeof (*ss->tx.cp) * (ss->tx.mask + 1);
+ kmem_free(ss->tx.cp, bytes);
+ ss->tx.cp = NULL;
+ return (DDI_FAILURE);
+}
+
+/*
+ * The eeprom strings on the lanaiX have the format
+ * SN=x\0
+ * MAC=x:x:x:x:x:x\0
+ * PT:ddd mmm xx xx:xx:xx xx\0
+ * PV:ddd mmm xx xx:xx:xx xx\0
+ */
+static int
+myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
+{
+#define MYRI10GE_NEXT_STRING(p) while (ptr < limit && *ptr++)
+#define myri10ge_digit(c) (((c) >= '0' && (c) <= '9') ? ((c) - '0') : \
+ (((c) >= 'A' && (c) <= 'F') ? (10 + (c) - 'A') : \
+ (((c) >= 'a' && (c) <= 'f') ? (10 + (c) - 'a') : -1)))
+
+ char *ptr, *limit;
+ int i, hv, lv;
+
+ ptr = mgp->eeprom_strings;
+ limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
+
+ while (*ptr != '\0' && ptr < limit) {
+ if (memcmp(ptr, "MAC=", 4) == 0) {
+ ptr += 4;
+ if (myri10ge_verbose)
+ printf("%s: mac address = %s\n", mgp->name,
+ ptr);
+ mgp->mac_addr_string = ptr;
+ for (i = 0; i < 6; i++) {
+ if ((ptr + 2) > limit)
+ goto abort;
+
+ if (*(ptr+1) == ':') {
+ hv = 0;
+ lv = myri10ge_digit(*ptr); ptr++;
+ } else {
+ hv = myri10ge_digit(*ptr); ptr++;
+ lv = myri10ge_digit(*ptr); ptr++;
+ }
+ mgp->mac_addr[i] = (hv << 4) | lv;
+ ptr++;
+ }
+ }
+ if (memcmp((const void *)ptr, "SN=", 3) == 0) {
+ ptr += 3;
+ mgp->sn_str = (char *)ptr;
+ }
+ if (memcmp((const void *)ptr, "PC=", 3) == 0) {
+ ptr += 3;
+ mgp->pc_str = (char *)ptr;
+ }
+ MYRI10GE_NEXT_STRING(ptr);
+ }
+
+ return (0);
+
+abort:
+ cmn_err(CE_WARN, "%s: failed to parse eeprom_strings", mgp->name);
+ return (ENXIO);
+}
+
+
+/*
+ * Determine the register set containing the PCI resource we
+ * want to map: the memory-mappable part of the interface. We do
+ * this by scanning the DDI "reg" property of the interface,
+ * which is an array of mx_ddi_reg_set structures.
+ */
+static int
+myri10ge_reg_set(dev_info_t *dip, int *reg_set, int *span,
+ unsigned long *busno, unsigned long *devno,
+ unsigned long *funcno)
+{
+
+#define REGISTER_NUMBER(ip) (ip[0] >> 0 & 0xff)
+#define FUNCTION_NUMBER(ip) (ip[0] >> 8 & 0x07)
+#define DEVICE_NUMBER(ip) (ip[0] >> 11 & 0x1f)
+#define BUS_NUMBER(ip) (ip[0] >> 16 & 0xff)
+#define ADDRESS_SPACE(ip) (ip[0] >> 24 & 0x03)
+#define PCI_ADDR_HIGH(ip) (ip[1])
+#define PCI_ADDR_LOW(ip) (ip[2])
+#define PCI_SPAN_HIGH(ip) (ip[3])
+#define PCI_SPAN_LOW(ip) (ip[4])
+
+#define MX_DDI_REG_SET_32_BIT_MEMORY_SPACE 2
+#define MX_DDI_REG_SET_64_BIT_MEMORY_SPACE 3
+
+ int *data, i, *rs;
+ uint32_t nelementsp;
+
+#ifdef MYRI10GE_REGSET_VERBOSE
+ char *address_space_name[] = { "Configuration Space",
+ "I/O Space",
+ "32-bit Memory Space",
+ "64-bit Memory Space"
+ };
+#endif
+
+ if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
+ "reg", &data, &nelementsp) != DDI_SUCCESS) {
+ printf("Could not determine register set.\n");
+ return (ENXIO);
+ }
+
+#ifdef MYRI10GE_REGSET_VERBOSE
+ printf("There are %d register sets.\n", nelementsp / 5);
+#endif
+ if (!nelementsp) {
+ printf("Didn't find any \"reg\" properties.\n");
+ ddi_prop_free(data);
+ return (ENODEV);
+ }
+
+ /* Scan for the register number. */
+ rs = &data[0];
+ *busno = BUS_NUMBER(rs);
+ *devno = DEVICE_NUMBER(rs);
+ *funcno = FUNCTION_NUMBER(rs);
+
+#ifdef MYRI10GE_REGSET_VERBOSE
+ printf("*** Scanning for register number.\n");
+#endif
+ for (i = 0; i < nelementsp / 5; i++) {
+ rs = &data[5 * i];
+#ifdef MYRI10GE_REGSET_VERBOSE
+ printf("Examining register set %d:\n", i);
+ printf(" Register number = %d.\n", REGISTER_NUMBER(rs));
+ printf(" Function number = %d.\n", FUNCTION_NUMBER(rs));
+ printf(" Device number = %d.\n", DEVICE_NUMBER(rs));
+ printf(" Bus number = %d.\n", BUS_NUMBER(rs));
+ printf(" Address space = %d (%s ).\n", ADDRESS_SPACE(rs),
+ address_space_name[ADDRESS_SPACE(rs)]);
+ printf(" pci address 0x%08x %08x\n", PCI_ADDR_HIGH(rs),
+ PCI_ADDR_LOW(rs));
+ printf(" pci span 0x%08x %08x\n", PCI_SPAN_HIGH(rs),
+ PCI_SPAN_LOW(rs));
+#endif
+ /* We are looking for a memory property. */
+
+ if (ADDRESS_SPACE(rs) == MX_DDI_REG_SET_64_BIT_MEMORY_SPACE ||
+ ADDRESS_SPACE(rs) == MX_DDI_REG_SET_32_BIT_MEMORY_SPACE) {
+ *reg_set = i;
+
+#ifdef MYRI10GE_REGSET_VERBOSE
+ printf("%s uses register set %d.\n",
+ address_space_name[ADDRESS_SPACE(rs)], *reg_set);
+#endif
+
+ *span = (PCI_SPAN_LOW(rs));
+#ifdef MYRI10GE_REGSET_VERBOSE
+ printf("Board span is 0x%x\n", *span);
+#endif
+ break;
+ }
+ }
+
+ ddi_prop_free(data);
+
+ /* If no match, fail. */
+ if (i >= nelementsp / 5) {
+ return (EIO);
+ }
+
+ return (0);
+}
+
+
+static int
+myri10ge_load_firmware_from_zlib(struct myri10ge_priv *mgp, uint32_t *limit)
+{
+ void *inflate_buffer;
+ int rv, status;
+ size_t sram_size = mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE;
+ size_t destlen;
+ mcp_gen_header_t *hdr;
+ unsigned hdr_offset, i;
+
+
+ *limit = 0; /* -Wuninitialized */
+ status = 0;
+
+ inflate_buffer = kmem_zalloc(sram_size, KM_NOSLEEP);
+ if (!inflate_buffer) {
+ cmn_err(CE_WARN,
+ "%s: Could not allocate buffer to inflate mcp\n",
+ mgp->name);
+ return (ENOMEM);
+ }
+
+ destlen = sram_size;
+ rv = z_uncompress(inflate_buffer, &destlen, mgp->eth_z8e,
+ mgp->eth_z8e_length);
+
+ if (rv != Z_OK) {
+ cmn_err(CE_WARN, "%s: Could not inflate mcp: %s\n",
+ mgp->name, z_strerror(rv));
+ status = ENXIO;
+ goto abort;
+ }
+
+ *limit = (uint32_t)destlen;
+
+ hdr_offset = htonl(*(uint32_t *)(void *)((char *)inflate_buffer +
+ MCP_HEADER_PTR_OFFSET));
+ hdr = (void *)((char *)inflate_buffer + hdr_offset);
+ if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
+ cmn_err(CE_WARN, "%s: Bad firmware type: 0x%x\n", mgp->name,
+ ntohl(hdr->mcp_type));
+ status = EIO;
+ goto abort;
+ }
+
+ /* save firmware version for kstat */
+ (void) strncpy(mgp->fw_version, hdr->version, sizeof (mgp->fw_version));
+ if (myri10ge_verbose)
+ printf("%s: firmware id: %s\n", mgp->name, hdr->version);
+
+ /* Copy the inflated firmware to NIC SRAM. */
+ for (i = 0; i < *limit; i += 256) {
+ myri10ge_pio_copy((char *)mgp->sram + MYRI10GE_FW_OFFSET + i,
+ (char *)inflate_buffer + i,
+ min(256U, (unsigned)(*limit - i)));
+ mb();
+ (void) *(int *)(void *)mgp->sram;
+ mb();
+ }
+
+abort:
+ kmem_free(inflate_buffer, sram_size);
+
+ return (status);
+
+}
+
+
+int
+myri10ge_send_cmd(struct myri10ge_priv *mgp, uint32_t cmd,
+ myri10ge_cmd_t *data)
+{
+ mcp_cmd_t *buf;
+ char buf_bytes[sizeof (*buf) + 8];
+ volatile mcp_cmd_response_t *response = mgp->cmd;
+ volatile char *cmd_addr =
+ (volatile char *)mgp->sram + MXGEFW_ETH_CMD;
+ int sleep_total = 0;
+
+ /* ensure buf is aligned to 8 bytes */
+ buf = (mcp_cmd_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
+
+ buf->data0 = htonl(data->data0);
+ buf->data1 = htonl(data->data1);
+ buf->data2 = htonl(data->data2);
+ buf->cmd = htonl(cmd);
+ buf->response_addr.low = mgp->cmd_dma.low;
+ buf->response_addr.high = mgp->cmd_dma.high;
+ mutex_enter(&mgp->cmd_lock);
+ response->result = 0xffffffff;
+ mb();
+
+ myri10ge_pio_copy((void *)cmd_addr, buf, sizeof (*buf));
+
+ /* wait up to 20ms */
+ for (sleep_total = 0; sleep_total < 20; sleep_total++) {
+ mb();
+ if (response->result != 0xffffffff) {
+ if (response->result == 0) {
+ data->data0 = ntohl(response->data);
+ mutex_exit(&mgp->cmd_lock);
+ return (0);
+ } else if (ntohl(response->result)
+ == MXGEFW_CMD_UNKNOWN) {
+ mutex_exit(&mgp->cmd_lock);
+ return (ENOSYS);
+ } else if (ntohl(response->result)
+ == MXGEFW_CMD_ERROR_UNALIGNED) {
+ mutex_exit(&mgp->cmd_lock);
+ return (E2BIG);
+ } else {
+ cmn_err(CE_WARN,
+ "%s: command %d failed, result = %d\n",
+ mgp->name, cmd, ntohl(response->result));
+ mutex_exit(&mgp->cmd_lock);
+ return (ENXIO);
+ }
+ }
+ drv_usecwait(1000);
+ }
+ mutex_exit(&mgp->cmd_lock);
+ cmn_err(CE_WARN, "%s: command %d timed out, result = %d\n",
+ mgp->name, cmd, ntohl(response->result));
+ return (EAGAIN);
+}
+
+/*
+ * Enable or disable periodic RDMAs from the host to make certain
+ * chipsets resend dropped PCIe messages
+ */
+
+static void
+myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
+{
+ char buf_bytes[72];
+ volatile uint32_t *confirm;
+ volatile char *submit;
+ uint32_t *buf;
+ int i;
+
+ buf = (uint32_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
+
+ /* clear confirmation addr */
+ confirm = (volatile uint32_t *)mgp->cmd;
+ *confirm = 0;
+ mb();
+
+ /*
+ * send an rdma command to the PCIe engine, and wait for the
+ * response in the confirmation address. The firmware should
+ * write a -1 there to indicate it is alive and well
+ */
+
+ buf[0] = mgp->cmd_dma.high; /* confirm addr MSW */
+ buf[1] = mgp->cmd_dma.low; /* confirm addr LSW */
+ buf[2] = htonl(0xffffffff); /* confirm data */
+ buf[3] = htonl(mgp->cmd_dma.high); /* dummy addr MSW */
+ buf[4] = htonl(mgp->cmd_dma.low); /* dummy addr LSW */
+ buf[5] = htonl(enable); /* enable? */
+
+
+ submit = (volatile char *)(mgp->sram + MXGEFW_BOOT_DUMMY_RDMA);
+
+ myri10ge_pio_copy((char *)submit, buf, 64);
+ mb();
+ drv_usecwait(1000);
+ mb();
+ i = 0;
+ while (*confirm != 0xffffffff && i < 20) {
+ drv_usecwait(1000);
+ i++;
+ }
+ if (*confirm != 0xffffffff) {
+ cmn_err(CE_WARN, "%s: dummy rdma %s failed (%p = 0x%x)",
+ mgp->name,
+ (enable ? "enable" : "disable"), (void*) confirm, *confirm);
+ }
+}
+
+static int
+myri10ge_load_firmware(struct myri10ge_priv *mgp)
+{
+ myri10ge_cmd_t cmd;
+ volatile uint32_t *confirm;
+ volatile char *submit;
+ char buf_bytes[72];
+ uint32_t *buf, size;
+ int status, i;
+
+ buf = (uint32_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
+
+ status = myri10ge_load_firmware_from_zlib(mgp, &size);
+ if (status) {
+ cmn_err(CE_WARN, "%s: firmware loading failed\n", mgp->name);
+ return (status);
+ }
+
+ /* clear confirmation addr */
+ confirm = (volatile uint32_t *)mgp->cmd;
+ *confirm = 0;
+ mb();
+
+ /*
+ * send a reload command to the bootstrap MCP, and wait for the
+ * response in the confirmation address. The firmware should
+ * write a -1 there to indicate it is alive and well
+ */
+
+ buf[0] = mgp->cmd_dma.high; /* confirm addr MSW */
+ buf[1] = mgp->cmd_dma.low; /* confirm addr LSW */
+ buf[2] = htonl(0xffffffff); /* confirm data */
+
+ /*
+ * FIX: All newest firmware should un-protect the bottom of
+ * the sram before handoff. However, the very first interfaces
+ * do not. Therefore the handoff copy must skip the first 8 bytes
+ */
+ buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
+ buf[4] = htonl(size - 8); /* length of code */
+ buf[5] = htonl(8); /* where to copy to */
+ buf[6] = htonl(0); /* where to jump to */
+
+ submit = (volatile char *)(mgp->sram + MXGEFW_BOOT_HANDOFF);
+
+ myri10ge_pio_copy((char *)submit, buf, 64);
+ mb();
+ drv_usecwait(1000);
+ mb();
+ i = 0;
+ while (*confirm != 0xffffffff && i < 1000) {
+ drv_usecwait(1000);
+ i++;
+ }
+ if (*confirm != 0xffffffff) {
+ cmn_err(CE_WARN, "%s: handoff failed (%p = 0x%x)",
+ mgp->name, (void *) confirm, *confirm);
+
+ return (ENXIO);
+ }
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed MXGEFW_CMD_GET_RX_RING_SIZE\n",
+ mgp->name);
+ return (ENXIO);
+ }
+
+ mgp->max_intr_slots = 2 * (cmd.data0 / sizeof (mcp_dma_addr_t));
+ myri10ge_dummy_rdma(mgp, 1);
+ return (0);
+}
+
+static int
+myri10ge_m_unicst(void *arg, const uint8_t *addr)
+{
+ struct myri10ge_priv *mgp = arg;
+ myri10ge_cmd_t cmd;
+ int status;
+
+ cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
+ | (addr[2] << 8) | addr[3]);
+
+ cmd.data1 = ((addr[4] << 8) | (addr[5]));
+
+ status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd);
+ if (status == 0 && (addr != mgp->mac_addr))
+ (void) memcpy(mgp->mac_addr, addr, sizeof (mgp->mac_addr));
+
+ return (status);
+}
+
+static int
+myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
+{
+ myri10ge_cmd_t cmd;
+ int status;
+
+ if (pause)
+ status = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_FLOW_CONTROL,
+ &cmd);
+ else
+ status = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_FLOW_CONTROL,
+ &cmd);
+
+ if (status) {
+ cmn_err(CE_WARN, "%s: Failed to set flow control mode\n",
+ mgp->name);
+ return (ENXIO);
+ }
+ mgp->pause = pause;
+ return (0);
+}
+
+static void
+myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc)
+{
+ myri10ge_cmd_t cmd;
+ int status;
+
+ if (promisc)
+ status = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_PROMISC, &cmd);
+ else
+ status = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_PROMISC, &cmd);
+
+ if (status) {
+ cmn_err(CE_WARN, "%s: Failed to set promisc mode\n",
+ mgp->name);
+ }
+}
+
+static int
+myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
+{
+ myri10ge_cmd_t cmd;
+ int status;
+ uint32_t len;
+ void *dmabench;
+ struct myri10ge_dma_stuff dmabench_dma;
+ char *test = " ";
+
+ /*
+ * Run a small DMA test.
+ * The magic multipliers to the length tell the firmware
+ * tp do DMA read, write, or read+write tests. The
+ * results are returned in cmd.data0. The upper 16
+ * bits or the return is the number of transfers completed.
+ * The lower 16 bits is the time in 0.5us ticks that the
+ * transfers took to complete
+ */
+
+ len = mgp->tx_boundary;
+
+ dmabench = myri10ge_dma_alloc(mgp->dip, len,
+ &myri10ge_rx_jumbo_dma_attr, &myri10ge_dev_access_attr,
+ DDI_DMA_STREAMING, DDI_DMA_RDWR|DDI_DMA_STREAMING,
+ &dmabench_dma, 1, DDI_DMA_DONTWAIT);
+ mgp->read_dma = mgp->write_dma = mgp->read_write_dma = 0;
+ if (dmabench == NULL) {
+ cmn_err(CE_WARN, "%s dma benchmark aborted\n", mgp->name);
+ return (ENOMEM);
+ }
+
+ cmd.data0 = ntohl(dmabench_dma.low);
+ cmd.data1 = ntohl(dmabench_dma.high);
+ cmd.data2 = len * 0x10000;
+ status = myri10ge_send_cmd(mgp, test_type, &cmd);
+ if (status != 0) {
+ test = "read";
+ goto abort;
+ }
+ mgp->read_dma = ((cmd.data0>>16) * len * 2) / (cmd.data0 & 0xffff);
+
+ cmd.data0 = ntohl(dmabench_dma.low);
+ cmd.data1 = ntohl(dmabench_dma.high);
+ cmd.data2 = len * 0x1;
+ status = myri10ge_send_cmd(mgp, test_type, &cmd);
+ if (status != 0) {
+ test = "write";
+ goto abort;
+ }
+ mgp->write_dma = ((cmd.data0>>16) * len * 2) / (cmd.data0 & 0xffff);
+
+ cmd.data0 = ntohl(dmabench_dma.low);
+ cmd.data1 = ntohl(dmabench_dma.high);
+ cmd.data2 = len * 0x10001;
+ status = myri10ge_send_cmd(mgp, test_type, &cmd);
+ if (status != 0) {
+ test = "read/write";
+ goto abort;
+ }
+ mgp->read_write_dma = ((cmd.data0>>16) * len * 2 * 2) /
+ (cmd.data0 & 0xffff);
+
+
+abort:
+ myri10ge_dma_free(&dmabench_dma);
+ if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
+ cmn_err(CE_WARN, "%s %s dma benchmark failed\n", mgp->name,
+ test);
+ return (status);
+}
+
+static int
+myri10ge_reset(struct myri10ge_priv *mgp)
+{
+ myri10ge_cmd_t cmd;
+ struct myri10ge_nic_stat *ethstat;
+ struct myri10ge_slice_state *ss;
+ int i, status;
+ size_t bytes;
+
+ /* send a reset command to the card to see if it is alive */
+ (void) memset(&cmd, 0, sizeof (cmd));
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed reset\n", mgp->name);
+ return (ENXIO);
+ }
+
+ /* Now exchange information about interrupts */
+
+ bytes = mgp->max_intr_slots * sizeof (*mgp->ss[0].rx_done.entry);
+ cmd.data0 = (uint32_t)bytes;
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd);
+
+ /*
+ * Even though we already know how many slices are supported
+ * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
+ * has magic side effects, and must be called after a reset.
+ * It must be called prior to calling any RSS related cmds,
+ * including assigning an interrupt queue for anything but
+ * slice 0. It must also be called *after*
+ * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
+ * the firmware to compute offsets.
+ */
+
+ if (mgp->num_slices > 1) {
+
+ /* ask the maximum number of slices it supports */
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
+ &cmd);
+ if (status != 0) {
+ cmn_err(CE_WARN,
+ "%s: failed to get number of slices\n",
+ mgp->name);
+ return (status);
+ }
+
+ /*
+ * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
+ * to setting up the interrupt queue DMA
+ */
+
+ cmd.data0 = mgp->num_slices;
+ cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE |
+ MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
+ &cmd);
+ if (status != 0) {
+ cmn_err(CE_WARN,
+ "%s: failed to set number of slices\n",
+ mgp->name);
+ return (status);
+ }
+ }
+ for (i = 0; i < mgp->num_slices; i++) {
+ ss = &mgp->ss[i];
+ cmd.data0 = ntohl(ss->rx_done.dma.low);
+ cmd.data1 = ntohl(ss->rx_done.dma.high);
+ cmd.data2 = i;
+ status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
+ &cmd);
+ };
+
+ status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd);
+ for (i = 0; i < mgp->num_slices; i++) {
+ ss = &mgp->ss[i];
+ ss->irq_claim = (volatile unsigned int *)
+ (void *)(mgp->sram + cmd.data0 + 8 * i);
+ }
+
+ if (mgp->ddi_intr_type == DDI_INTR_TYPE_FIXED) {
+ status |= myri10ge_send_cmd(mgp,
+ MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, &cmd);
+ mgp->irq_deassert = (uint32_t *)(void *)(mgp->sram + cmd.data0);
+ }
+
+ status |= myri10ge_send_cmd(mgp,
+ MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd);
+ mgp->intr_coal_delay_ptr = (uint32_t *)(void *)(mgp->sram + cmd.data0);
+
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed set interrupt parameters\n",
+ mgp->name);
+ return (status);
+ }
+
+ *mgp->intr_coal_delay_ptr = htonl(mgp->intr_coal_delay);
+ (void) myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
+
+ /* reset mcp/driver shared state back to 0 */
+
+ for (i = 0; i < mgp->num_slices; i++) {
+ ss = &mgp->ss[i];
+ bytes = mgp->max_intr_slots *
+ sizeof (*mgp->ss[0].rx_done.entry);
+ (void) memset(ss->rx_done.entry, 0, bytes);
+ ss->tx.req = 0;
+ ss->tx.done = 0;
+ ss->tx.pkt_done = 0;
+ ss->rx_big.cnt = 0;
+ ss->rx_small.cnt = 0;
+ ss->rx_done.idx = 0;
+ ss->rx_done.cnt = 0;
+ ss->rx_token = 0;
+ ss->tx.watchdog_done = 0;
+ ss->tx.watchdog_req = 0;
+ ss->tx.active = 0;
+ ss->tx.activate = 0;
+ }
+ mgp->watchdog_rx_pause = 0;
+ if (mgp->ksp_stat != NULL) {
+ ethstat = (struct myri10ge_nic_stat *)mgp->ksp_stat->ks_data;
+ ethstat->link_changes.value.ul = 0;
+ }
+ status = myri10ge_m_unicst(mgp, mgp->mac_addr);
+ myri10ge_change_promisc(mgp, 0);
+ (void) myri10ge_change_pause(mgp, mgp->pause);
+ return (status);
+}
+
+static int
+myri10ge_init_toeplitz(struct myri10ge_priv *mgp)
+{
+ myri10ge_cmd_t cmd;
+ int i, b, s, t, j;
+ int status;
+ uint32_t k[8];
+ uint32_t tmp;
+ uint8_t *key;
+
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RSS_KEY_OFFSET,
+ &cmd);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed to get rss key\n",
+ mgp->name);
+ return (EIO);
+ }
+ myri10ge_pio_copy32(mgp->rss_key,
+ (uint32_t *)(void*)((char *)mgp->sram + cmd.data0),
+ sizeof (mgp->rss_key));
+
+ mgp->toeplitz_hash_table = kmem_alloc(sizeof (uint32_t) * 12 * 256,
+ KM_SLEEP);
+ key = (uint8_t *)mgp->rss_key;
+ t = 0;
+ for (b = 0; b < 12; b++) {
+ for (s = 0; s < 8; s++) {
+ /* Bits: b*8+s, ..., b*8+s+31 */
+ k[s] = 0;
+ for (j = 0; j < 32; j++) {
+ int bit = b*8+s+j;
+ bit = 0x1 & (key[bit / 8] >> (7 -(bit & 0x7)));
+ k[s] |= bit << (31 - j);
+ }
+ }
+
+ for (i = 0; i <= 0xff; i++) {
+ tmp = 0;
+ if (i & (1 << 7)) { tmp ^= k[0]; }
+ if (i & (1 << 6)) { tmp ^= k[1]; }
+ if (i & (1 << 5)) { tmp ^= k[2]; }
+ if (i & (1 << 4)) { tmp ^= k[3]; }
+ if (i & (1 << 3)) { tmp ^= k[4]; }
+ if (i & (1 << 2)) { tmp ^= k[5]; }
+ if (i & (1 << 1)) { tmp ^= k[6]; }
+ if (i & (1 << 0)) { tmp ^= k[7]; }
+ mgp->toeplitz_hash_table[t++] = tmp;
+ }
+ }
+ return (0);
+}
+
+static inline struct myri10ge_slice_state *
+myri10ge_toeplitz_send_hash(struct myri10ge_priv *mgp, struct ip *ip)
+{
+ struct tcphdr *hdr;
+ uint32_t saddr, daddr;
+ uint32_t hash, slice;
+ uint32_t *table = mgp->toeplitz_hash_table;
+ uint16_t src, dst;
+
+ /*
+ * Note hashing order is reversed from how it is done
+ * in the NIC, so as to generate the same hash value
+ * for the connection to try to keep connections CPU local
+ */
+
+ /* hash on IPv4 src/dst address */
+ saddr = ntohl(ip->ip_src.s_addr);
+ daddr = ntohl(ip->ip_dst.s_addr);
+ hash = table[(256 * 0) + ((daddr >> 24) & 0xff)];
+ hash ^= table[(256 * 1) + ((daddr >> 16) & 0xff)];
+ hash ^= table[(256 * 2) + ((daddr >> 8) & 0xff)];
+ hash ^= table[(256 * 3) + ((daddr) & 0xff)];
+ hash ^= table[(256 * 4) + ((saddr >> 24) & 0xff)];
+ hash ^= table[(256 * 5) + ((saddr >> 16) & 0xff)];
+ hash ^= table[(256 * 6) + ((saddr >> 8) & 0xff)];
+ hash ^= table[(256 * 7) + ((saddr) & 0xff)];
+ /* hash on TCP port, if required */
+ if ((myri10ge_rss_hash & MXGEFW_RSS_HASH_TYPE_TCP_IPV4) &&
+ ip->ip_p == IPPROTO_TCP) {
+ hdr = (struct tcphdr *)(void *)
+ (((uint8_t *)ip) + (ip->ip_hl << 2));
+ src = ntohs(hdr->th_sport);
+ dst = ntohs(hdr->th_dport);
+
+ hash ^= table[(256 * 8) + ((dst >> 8) & 0xff)];
+ hash ^= table[(256 * 9) + ((dst) & 0xff)];
+ hash ^= table[(256 * 10) + ((src >> 8) & 0xff)];
+ hash ^= table[(256 * 11) + ((src) & 0xff)];
+ }
+ slice = (mgp->num_slices - 1) & hash;
+ return (&mgp->ss[slice]);
+
+}
+
+static inline struct myri10ge_slice_state *
+myri10ge_simple_send_hash(struct myri10ge_priv *mgp, struct ip *ip)
+{
+ struct tcphdr *hdr;
+ uint32_t slice, hash_val;
+
+
+ if (ip->ip_p != IPPROTO_TCP && ip->ip_p != IPPROTO_UDP) {
+ return (&mgp->ss[0]);
+ }
+ hdr = (struct tcphdr *)(void *)(((uint8_t *)ip) + (ip->ip_hl << 2));
+
+ /*
+ * Use the second byte of the *destination* address for
+ * MXGEFW_RSS_HASH_TYPE_SRC_PORT, so as to match NIC's hashing
+ */
+ hash_val = ntohs(hdr->th_dport) & 0xff;
+ if (myri10ge_rss_hash == MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT)
+ hash_val += ntohs(hdr->th_sport) & 0xff;
+
+ slice = (mgp->num_slices - 1) & hash_val;
+ return (&mgp->ss[slice]);
+}
+
+static inline struct myri10ge_slice_state *
+myri10ge_send_hash(struct myri10ge_priv *mgp, mblk_t *mp)
+{
+ unsigned int slice = 0;
+ struct ether_header *eh;
+ struct ether_vlan_header *vh;
+ struct ip *ip;
+ int ehl, ihl;
+
+ if (mgp->num_slices == 1)
+ return (&mgp->ss[0]);
+
+ if (myri10ge_tx_hash == 0) {
+ slice = CPU->cpu_id & (mgp->num_slices - 1);
+ return (&mgp->ss[slice]);
+ }
+
+ /*
+ * ensure it is a TCP or UDP over IPv4 packet, and that the
+ * headers are in the 1st mblk. Otherwise, punt
+ */
+ ehl = sizeof (*eh);
+ ihl = sizeof (*ip);
+ if ((MBLKL(mp)) < (ehl + ihl + 8))
+ return (&mgp->ss[0]);
+ eh = (struct ether_header *)(void *)mp->b_rptr;
+ ip = (struct ip *)(void *)(eh + 1);
+ if (eh->ether_type != BE_16(ETHERTYPE_IP)) {
+ if (eh->ether_type != BE_16(ETHERTYPE_VLAN))
+ return (&mgp->ss[0]);
+ vh = (struct ether_vlan_header *)(void *)mp->b_rptr;
+ if (vh->ether_type != BE_16(ETHERTYPE_IP))
+ return (&mgp->ss[0]);
+ ehl += 4;
+ ip = (struct ip *)(void *)(vh + 1);
+ }
+ ihl = ip->ip_hl << 2;
+ if (MBLKL(mp) < (ehl + ihl + 8))
+ return (&mgp->ss[0]);
+ switch (myri10ge_rss_hash) {
+ case MXGEFW_RSS_HASH_TYPE_IPV4:
+ /* fallthru */
+ case MXGEFW_RSS_HASH_TYPE_TCP_IPV4:
+ /* fallthru */
+ case (MXGEFW_RSS_HASH_TYPE_IPV4|MXGEFW_RSS_HASH_TYPE_TCP_IPV4):
+ return (myri10ge_toeplitz_send_hash(mgp, ip));
+ case MXGEFW_RSS_HASH_TYPE_SRC_PORT:
+ /* fallthru */
+ case MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT:
+ return (myri10ge_simple_send_hash(mgp, ip));
+ default:
+ break;
+ }
+ return (&mgp->ss[0]);
+}
+
+static int
+myri10ge_setup_slice(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_priv *mgp = ss->mgp;
+ myri10ge_cmd_t cmd;
+ int tx_ring_size, rx_ring_size;
+ int tx_ring_entries, rx_ring_entries;
+ int slice, status;
+ int allocated, idx;
+ size_t bytes;
+
+ slice = ss - mgp->ss;
+ cmd.data0 = slice;
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd);
+ tx_ring_size = cmd.data0;
+ cmd.data0 = slice;
+ status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd);
+ if (status != 0)
+ return (status);
+ rx_ring_size = cmd.data0;
+
+ tx_ring_entries = tx_ring_size / sizeof (struct mcp_kreq_ether_send);
+ rx_ring_entries = rx_ring_size / sizeof (struct mcp_dma_addr);
+ ss->tx.mask = tx_ring_entries - 1;
+ ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
+
+ /* get the lanai pointers to the send and receive rings */
+
+ cmd.data0 = slice;
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd);
+ ss->tx.lanai = (mcp_kreq_ether_send_t *)(void *)(mgp->sram + cmd.data0);
+ if (mgp->num_slices > 1) {
+ ss->tx.go = (char *)mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice;
+ ss->tx.stop = (char *)mgp->sram + MXGEFW_ETH_SEND_STOP +
+ 64 * slice;
+ } else {
+ ss->tx.go = NULL;
+ ss->tx.stop = NULL;
+ }
+
+ cmd.data0 = slice;
+ status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd);
+ ss->rx_small.lanai = (mcp_kreq_ether_recv_t *)
+ (void *)(mgp->sram + cmd.data0);
+
+ cmd.data0 = slice;
+ status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd);
+ ss->rx_big.lanai = (mcp_kreq_ether_recv_t *)(void *)
+ (mgp->sram + cmd.data0);
+
+ if (status != 0) {
+ cmn_err(CE_WARN,
+ "%s: failed to get ring sizes or locations\n", mgp->name);
+ return (status);
+ }
+
+ status = ENOMEM;
+ bytes = rx_ring_entries * sizeof (*ss->rx_small.shadow);
+ ss->rx_small.shadow = kmem_zalloc(bytes, KM_SLEEP);
+ if (ss->rx_small.shadow == NULL)
+ goto abort;
+ (void) memset(ss->rx_small.shadow, 0, bytes);
+
+ bytes = rx_ring_entries * sizeof (*ss->rx_big.shadow);
+ ss->rx_big.shadow = kmem_zalloc(bytes, KM_SLEEP);
+ if (ss->rx_big.shadow == NULL)
+ goto abort_with_rx_small_shadow;
+ (void) memset(ss->rx_big.shadow, 0, bytes);
+
+ /* allocate the host info rings */
+
+ bytes = tx_ring_entries * sizeof (*ss->tx.info);
+ ss->tx.info = kmem_zalloc(bytes, KM_SLEEP);
+ if (ss->tx.info == NULL)
+ goto abort_with_rx_big_shadow;
+ (void) memset(ss->tx.info, 0, bytes);
+
+ bytes = rx_ring_entries * sizeof (*ss->rx_small.info);
+ ss->rx_small.info = kmem_zalloc(bytes, KM_SLEEP);
+ if (ss->rx_small.info == NULL)
+ goto abort_with_tx_info;
+ (void) memset(ss->rx_small.info, 0, bytes);
+
+ bytes = rx_ring_entries * sizeof (*ss->rx_big.info);
+ ss->rx_big.info = kmem_zalloc(bytes, KM_SLEEP);
+ if (ss->rx_big.info == NULL)
+ goto abort_with_rx_small_info;
+ (void) memset(ss->rx_big.info, 0, bytes);
+
+ ss->tx.stall = ss->tx.sched = 0;
+ ss->tx.stall_early = ss->tx.stall_late = 0;
+
+ ss->jbufs_for_smalls = 1 + (1 + ss->rx_small.mask) /
+ (myri10ge_mtu / (myri10ge_small_bytes + MXGEFW_PAD));
+
+ allocated = myri10ge_add_jbufs(ss,
+ myri10ge_bigbufs_initial + ss->jbufs_for_smalls, 1);
+ if (allocated < ss->jbufs_for_smalls + myri10ge_bigbufs_initial) {
+ cmn_err(CE_WARN,
+ "%s: Could not allocate enough receive buffers (%d/%d)\n",
+ mgp->name, allocated,
+ myri10ge_bigbufs_initial + ss->jbufs_for_smalls);
+ goto abort_with_jumbos;
+ }
+
+ myri10ge_carve_up_jbufs_into_small_ring(ss);
+ ss->j_rx_cnt = 0;
+
+ mutex_enter(&ss->jpool.mtx);
+ if (allocated < rx_ring_entries)
+ ss->jpool.low_water = allocated / 4;
+ else
+ ss->jpool.low_water = rx_ring_entries / 2;
+
+ /*
+ * invalidate the big receive ring in case we do not
+ * allocate sufficient jumbos to fill it
+ */
+ (void) memset(ss->rx_big.shadow, 1,
+ (ss->rx_big.mask + 1) * sizeof (ss->rx_big.shadow[0]));
+ for (idx = 7; idx <= ss->rx_big.mask; idx += 8) {
+ myri10ge_submit_8rx(&ss->rx_big.lanai[idx - 7],
+ &ss->rx_big.shadow[idx - 7]);
+ mb();
+ }
+
+
+ myri10ge_restock_jumbos(ss);
+
+ for (idx = 7; idx <= ss->rx_small.mask; idx += 8) {
+ myri10ge_submit_8rx(&ss->rx_small.lanai[idx - 7],
+ &ss->rx_small.shadow[idx - 7]);
+ mb();
+ }
+ ss->rx_small.cnt = ss->rx_small.mask + 1;
+
+ mutex_exit(&ss->jpool.mtx);
+
+ status = myri10ge_prepare_tx_ring(ss);
+
+ if (status != 0)
+ goto abort_with_small_jbufs;
+
+ cmd.data0 = ntohl(ss->fw_stats_dma.low);
+ cmd.data1 = ntohl(ss->fw_stats_dma.high);
+ cmd.data2 = sizeof (mcp_irq_data_t);
+ cmd.data2 |= (slice << 16);
+ bzero(ss->fw_stats, sizeof (*ss->fw_stats));
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd);
+ if (status == ENOSYS) {
+ cmd.data0 = ntohl(ss->fw_stats_dma.low) +
+ offsetof(mcp_irq_data_t, send_done_count);
+ cmd.data1 = ntohl(ss->fw_stats_dma.high);
+ status = myri10ge_send_cmd(mgp,
+ MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, &cmd);
+ }
+ if (status) {
+ cmn_err(CE_WARN, "%s: Couldn't set stats DMA\n", mgp->name);
+ goto abort_with_tx;
+ }
+
+ return (0);
+
+abort_with_tx:
+ myri10ge_unprepare_tx_ring(ss);
+
+abort_with_small_jbufs:
+ myri10ge_release_small_jbufs(ss);
+
+abort_with_jumbos:
+ if (allocated != 0) {
+ mutex_enter(&ss->jpool.mtx);
+ ss->jpool.low_water = 0;
+ mutex_exit(&ss->jpool.mtx);
+ myri10ge_unstock_jumbos(ss);
+ myri10ge_remove_jbufs(ss);
+ }
+
+ bytes = rx_ring_entries * sizeof (*ss->rx_big.info);
+ kmem_free(ss->rx_big.info, bytes);
+
+abort_with_rx_small_info:
+ bytes = rx_ring_entries * sizeof (*ss->rx_small.info);
+ kmem_free(ss->rx_small.info, bytes);
+
+abort_with_tx_info:
+ bytes = tx_ring_entries * sizeof (*ss->tx.info);
+ kmem_free(ss->tx.info, bytes);
+
+abort_with_rx_big_shadow:
+ bytes = rx_ring_entries * sizeof (*ss->rx_big.shadow);
+ kmem_free(ss->rx_big.shadow, bytes);
+
+abort_with_rx_small_shadow:
+ bytes = rx_ring_entries * sizeof (*ss->rx_small.shadow);
+ kmem_free(ss->rx_small.shadow, bytes);
+abort:
+ return (status);
+
+}
+
+static void
+myri10ge_teardown_slice(struct myri10ge_slice_state *ss)
+{
+ int tx_ring_entries, rx_ring_entries;
+ size_t bytes;
+
+ /* ignore slices that have not been fully setup */
+ if (ss->tx.cp == NULL)
+ return;
+ /* Free the TX copy buffers */
+ myri10ge_unprepare_tx_ring(ss);
+
+ /* stop passing returned buffers to firmware */
+
+ mutex_enter(&ss->jpool.mtx);
+ ss->jpool.low_water = 0;
+ mutex_exit(&ss->jpool.mtx);
+ myri10ge_release_small_jbufs(ss);
+
+ /* Release the free jumbo frame pool */
+ myri10ge_unstock_jumbos(ss);
+ myri10ge_remove_jbufs(ss);
+
+ rx_ring_entries = ss->rx_big.mask + 1;
+ tx_ring_entries = ss->tx.mask + 1;
+
+ bytes = rx_ring_entries * sizeof (*ss->rx_big.info);
+ kmem_free(ss->rx_big.info, bytes);
+
+ bytes = rx_ring_entries * sizeof (*ss->rx_small.info);
+ kmem_free(ss->rx_small.info, bytes);
+
+ bytes = tx_ring_entries * sizeof (*ss->tx.info);
+ kmem_free(ss->tx.info, bytes);
+
+ bytes = rx_ring_entries * sizeof (*ss->rx_big.shadow);
+ kmem_free(ss->rx_big.shadow, bytes);
+
+ bytes = rx_ring_entries * sizeof (*ss->rx_small.shadow);
+ kmem_free(ss->rx_small.shadow, bytes);
+
+}
+static int
+myri10ge_start_locked(struct myri10ge_priv *mgp)
+{
+ myri10ge_cmd_t cmd;
+ int status, big_pow2, i;
+ volatile uint8_t *itable;
+
+ status = DDI_SUCCESS;
+ /* Allocate DMA resources and receive buffers */
+
+ status = myri10ge_reset(mgp);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed reset\n", mgp->name);
+ return (DDI_FAILURE);
+ }
+
+ if (mgp->num_slices > 1) {
+ cmd.data0 = mgp->num_slices;
+ cmd.data1 = 1; /* use MSI-X */
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
+ &cmd);
+ if (status != 0) {
+ cmn_err(CE_WARN,
+ "%s: failed to set number of slices\n",
+ mgp->name);
+ goto abort_with_nothing;
+ }
+ /* setup the indirection table */
+ cmd.data0 = mgp->num_slices;
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
+ &cmd);
+
+ status |= myri10ge_send_cmd(mgp,
+ MXGEFW_CMD_GET_RSS_TABLE_OFFSET, &cmd);
+ if (status != 0) {
+ cmn_err(CE_WARN,
+ "%s: failed to setup rss tables\n", mgp->name);
+ }
+
+ /* just enable an identity mapping */
+ itable = mgp->sram + cmd.data0;
+ for (i = 0; i < mgp->num_slices; i++)
+ itable[i] = (uint8_t)i;
+
+ if (myri10ge_rss_hash & MYRI10GE_TOEPLITZ_HASH) {
+ status = myri10ge_init_toeplitz(mgp);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed to setup "
+ "toeplitz tx hash table", mgp->name);
+ goto abort_with_nothing;
+ }
+ }
+ cmd.data0 = 1;
+ cmd.data1 = myri10ge_rss_hash;
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
+ &cmd);
+ if (status != 0) {
+ cmn_err(CE_WARN,
+ "%s: failed to enable slices\n", mgp->name);
+ goto abort_with_toeplitz;
+ }
+ }
+
+ for (i = 0; i < mgp->num_slices; i++) {
+ status = myri10ge_setup_slice(&mgp->ss[i]);
+ if (status != 0)
+ goto abort_with_slices;
+ }
+
+ /*
+ * Tell the MCP how many buffers he has, and to
+ * bring the ethernet interface up
+ *
+ * Firmware needs the big buff size as a power of 2. Lie and
+ * tell him the buffer is larger, because we only use 1
+ * buffer/pkt, and the mtu will prevent overruns
+ */
+ big_pow2 = myri10ge_mtu + MXGEFW_PAD;
+ while ((big_pow2 & (big_pow2 - 1)) != 0)
+ big_pow2++;
+
+ /* now give firmware buffers sizes, and MTU */
+ cmd.data0 = myri10ge_mtu;
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd);
+ cmd.data0 = myri10ge_small_bytes;
+ status |=
+ myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd);
+ cmd.data0 = big_pow2;
+ status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd);
+ if (status) {
+ cmn_err(CE_WARN, "%s: Couldn't set buffer sizes\n", mgp->name);
+ goto abort_with_slices;
+ }
+
+
+ cmd.data0 = 1;
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd);
+ if (status) {
+ cmn_err(CE_WARN, "%s: unable to setup TSO (%d)\n",
+ mgp->name, status);
+ } else {
+ mgp->features |= MYRI10GE_TSO;
+ }
+
+ mgp->link_state = -1;
+ mgp->rdma_tags_available = 15;
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd);
+ if (status) {
+ cmn_err(CE_WARN, "%s: unable to start ethernet\n", mgp->name);
+ goto abort_with_slices;
+ }
+ mgp->running = MYRI10GE_ETH_RUNNING;
+ return (DDI_SUCCESS);
+
+abort_with_slices:
+ for (i = 0; i < mgp->num_slices; i++)
+ myri10ge_teardown_slice(&mgp->ss[i]);
+
+ mgp->running = MYRI10GE_ETH_STOPPED;
+
+abort_with_toeplitz:
+ if (mgp->toeplitz_hash_table != NULL) {
+ kmem_free(mgp->toeplitz_hash_table,
+ sizeof (uint32_t) * 12 * 256);
+ mgp->toeplitz_hash_table = NULL;
+ }
+
+abort_with_nothing:
+ return (DDI_FAILURE);
+}
+
+static void
+myri10ge_stop_locked(struct myri10ge_priv *mgp)
+{
+ int status, old_down_cnt;
+ myri10ge_cmd_t cmd;
+ int wait_time = 10;
+ int i, polling;
+
+ old_down_cnt = mgp->down_cnt;
+ mb();
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd);
+ if (status) {
+ cmn_err(CE_WARN, "%s: Couldn't bring down link\n", mgp->name);
+ }
+
+ while (old_down_cnt == *((volatile int *)&mgp->down_cnt)) {
+ delay(1 * drv_usectohz(1000000));
+ wait_time--;
+ if (wait_time == 0)
+ break;
+ }
+again:
+ if (old_down_cnt == *((volatile int *)&mgp->down_cnt)) {
+ cmn_err(CE_WARN, "%s: didn't get down irq\n", mgp->name);
+ for (i = 0; i < mgp->num_slices; i++) {
+ /*
+ * take and release the rx lock to ensure
+ * that no interrupt thread is blocked
+ * elsewhere in the stack, preventing
+ * completion
+ */
+
+ mutex_enter(&mgp->ss[i].rx_lock);
+ printf("%s: slice %d rx irq idle\n",
+ mgp->name, i);
+ mutex_exit(&mgp->ss[i].rx_lock);
+
+ /* verify that the poll handler is inactive */
+ mutex_enter(&mgp->ss->poll_lock);
+ polling = mgp->ss->rx_polling;
+ mutex_exit(&mgp->ss->poll_lock);
+ if (polling) {
+ printf("%s: slice %d is polling\n",
+ mgp->name, i);
+ delay(1 * drv_usectohz(1000000));
+ goto again;
+ }
+ }
+ delay(1 * drv_usectohz(1000000));
+ if (old_down_cnt == *((volatile int *)&mgp->down_cnt)) {
+ cmn_err(CE_WARN, "%s: Never got down irq\n", mgp->name);
+ }
+ }
+
+ for (i = 0; i < mgp->num_slices; i++)
+ myri10ge_teardown_slice(&mgp->ss[i]);
+
+ if (mgp->toeplitz_hash_table != NULL) {
+ kmem_free(mgp->toeplitz_hash_table,
+ sizeof (uint32_t) * 12 * 256);
+ mgp->toeplitz_hash_table = NULL;
+ }
+ mgp->running = MYRI10GE_ETH_STOPPED;
+}
+
+static int
+myri10ge_m_start(void *arg)
+{
+ struct myri10ge_priv *mgp = arg;
+ int status;
+
+ mutex_enter(&mgp->intrlock);
+
+ if (mgp->running != MYRI10GE_ETH_STOPPED) {
+ mutex_exit(&mgp->intrlock);
+ return (DDI_FAILURE);
+ }
+ status = myri10ge_start_locked(mgp);
+ mutex_exit(&mgp->intrlock);
+
+ if (status != DDI_SUCCESS)
+ return (status);
+
+ /* start the watchdog timer */
+ mgp->timer_id = timeout(myri10ge_watchdog, mgp,
+ mgp->timer_ticks);
+ return (DDI_SUCCESS);
+
+}
+
+static void
+myri10ge_m_stop(void *arg)
+{
+ struct myri10ge_priv *mgp = arg;
+
+ mutex_enter(&mgp->intrlock);
+ /* if the device not running give up */
+ if (mgp->running != MYRI10GE_ETH_RUNNING) {
+ mutex_exit(&mgp->intrlock);
+ return;
+ }
+
+ mgp->running = MYRI10GE_ETH_STOPPING;
+ mutex_exit(&mgp->intrlock);
+ (void) untimeout(mgp->timer_id);
+ mutex_enter(&mgp->intrlock);
+ myri10ge_stop_locked(mgp);
+ mutex_exit(&mgp->intrlock);
+
+}
+
+static inline void
+myri10ge_rx_csum(mblk_t *mp, struct myri10ge_rx_ring_stats *s, uint32_t csum)
+{
+ struct ether_header *eh;
+ struct ip *ip;
+ struct ip6_hdr *ip6;
+ uint32_t start, stuff, end, partial, hdrlen;
+
+
+ csum = ntohs((uint16_t)csum);
+ eh = (struct ether_header *)(void *)mp->b_rptr;
+ hdrlen = sizeof (*eh);
+ if (eh->ether_dhost.ether_addr_octet[0] & 1) {
+ if (0 == (bcmp(eh->ether_dhost.ether_addr_octet,
+ myri10ge_broadcastaddr, sizeof (eh->ether_dhost))))
+ s->brdcstrcv++;
+ else
+ s->multircv++;
+ }
+
+ if (eh->ether_type == BE_16(ETHERTYPE_VLAN)) {
+ /*
+ * fix checksum by subtracting 4 bytes after what the
+ * firmware thought was the end of the ether hdr
+ */
+ partial = *(uint32_t *)
+ (void *)(mp->b_rptr + ETHERNET_HEADER_SIZE);
+ csum += ~partial;
+ csum += (csum < ~partial);
+ csum = (csum >> 16) + (csum & 0xFFFF);
+ csum = (csum >> 16) + (csum & 0xFFFF);
+ hdrlen += VLAN_TAGSZ;
+ }
+
+ if (eh->ether_type == BE_16(ETHERTYPE_IP)) {
+ ip = (struct ip *)(void *)(mp->b_rptr + hdrlen);
+ start = ip->ip_hl << 2;
+
+ if (ip->ip_p == IPPROTO_TCP)
+ stuff = start + offsetof(struct tcphdr, th_sum);
+ else if (ip->ip_p == IPPROTO_UDP)
+ stuff = start + offsetof(struct udphdr, uh_sum);
+ else
+ return;
+ end = ntohs(ip->ip_len);
+ } else if (eh->ether_type == BE_16(ETHERTYPE_IPV6)) {
+ ip6 = (struct ip6_hdr *)(void *)(mp->b_rptr + hdrlen);
+ start = sizeof (*ip6);
+ if (ip6->ip6_nxt == IPPROTO_TCP) {
+ stuff = start + offsetof(struct tcphdr, th_sum);
+ } else if (ip6->ip6_nxt == IPPROTO_UDP)
+ stuff = start + offsetof(struct udphdr, uh_sum);
+ else
+ return;
+ end = start + ntohs(ip6->ip6_plen);
+ /*
+ * IPv6 headers do not contain a checksum, and hence
+ * do not checksum to zero, so they don't "fall out"
+ * of the partial checksum calculation like IPv4
+ * headers do. We need to fix the partial checksum by
+ * subtracting the checksum of the IPv6 header.
+ */
+
+ partial = myri10ge_csum_generic((uint16_t *)ip6, sizeof (*ip6));
+ csum += ~partial;
+ csum += (csum < ~partial);
+ csum = (csum >> 16) + (csum & 0xFFFF);
+ csum = (csum >> 16) + (csum & 0xFFFF);
+ } else {
+ return;
+ }
+
+ if (MBLKL(mp) > hdrlen + end) {
+ /* padded frame, so hw csum may be invalid */
+ return;
+ }
+
+ (void) hcksum_assoc(mp, NULL, NULL, start, stuff, end,
+ csum, HCK_PARTIALCKSUM, 0);
+}
+
+static mblk_t *
+myri10ge_rx_done_small(struct myri10ge_slice_state *ss, uint32_t len,
+ uint32_t csum)
+{
+ mblk_t *mp;
+ myri10ge_rx_ring_t *rx;
+ int idx;
+
+ rx = &ss->rx_small;
+ idx = rx->cnt & rx->mask;
+ ss->rx_small.cnt++;
+
+ /* allocate a new buffer to pass up the stack */
+ mp = allocb(len + MXGEFW_PAD, 0);
+ if (mp == NULL) {
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(rx_small_nobuf);
+ goto abort;
+ }
+ bcopy(ss->rx_small.info[idx].ptr,
+ (caddr_t)mp->b_wptr, len + MXGEFW_PAD);
+ mp->b_wptr += len + MXGEFW_PAD;
+ mp->b_rptr += MXGEFW_PAD;
+
+ ss->rx_stats.ibytes += len;
+ ss->rx_stats.ipackets += 1;
+ myri10ge_rx_csum(mp, &ss->rx_stats, csum);
+
+abort:
+ if ((idx & 7) == 7) {
+ myri10ge_submit_8rx(&rx->lanai[idx - 7],
+ &rx->shadow[idx - 7]);
+ }
+
+ return (mp);
+}
+
+
+static mblk_t *
+myri10ge_rx_done_big(struct myri10ge_slice_state *ss, uint32_t len,
+ uint32_t csum)
+{
+ struct myri10ge_jpool_stuff *jpool;
+ struct myri10ge_jpool_entry *j;
+ mblk_t *mp;
+ int idx, num_owned_by_mcp;
+
+ jpool = &ss->jpool;
+ idx = ss->j_rx_cnt & ss->rx_big.mask;
+ j = ss->rx_big.info[idx].j;
+
+ if (j == NULL) {
+ printf("%s: null j at idx=%d, rx_big.cnt = %d, j_rx_cnt=%d\n",
+ ss->mgp->name, idx, ss->rx_big.cnt, ss->j_rx_cnt);
+ return (NULL);
+ }
+
+
+ ss->rx_big.info[idx].j = NULL;
+ ss->j_rx_cnt++;
+
+
+ /*
+ * Check to see if we are low on rx buffers.
+ * Note that we must leave at least 8 free so there are
+ * enough to free in a single 64-byte write.
+ */
+ num_owned_by_mcp = ss->rx_big.cnt - ss->j_rx_cnt;
+ if (num_owned_by_mcp < jpool->low_water) {
+ mutex_enter(&jpool->mtx);
+ myri10ge_restock_jumbos(ss);
+ mutex_exit(&jpool->mtx);
+ num_owned_by_mcp = ss->rx_big.cnt - ss->j_rx_cnt;
+ /* if we are still low, then we have to copy */
+ if (num_owned_by_mcp < 16) {
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(rx_copy);
+ /* allocate a new buffer to pass up the stack */
+ mp = allocb(len + MXGEFW_PAD, 0);
+ if (mp == NULL) {
+ goto abort;
+ }
+ bcopy(j->buf,
+ (caddr_t)mp->b_wptr, len + MXGEFW_PAD);
+ myri10ge_jfree_rtn(j);
+ /* push buffer back to NIC */
+ mutex_enter(&jpool->mtx);
+ myri10ge_restock_jumbos(ss);
+ mutex_exit(&jpool->mtx);
+ goto set_len;
+ }
+ }
+
+ /* loan our buffer to the stack */
+ mp = desballoc((unsigned char *)j->buf, myri10ge_mtu, 0, &j->free_func);
+ if (mp == NULL) {
+ goto abort;
+ }
+
+set_len:
+ mp->b_rptr += MXGEFW_PAD;
+ mp->b_wptr = ((unsigned char *) mp->b_rptr + len);
+
+ ss->rx_stats.ibytes += len;
+ ss->rx_stats.ipackets += 1;
+ myri10ge_rx_csum(mp, &ss->rx_stats, csum);
+
+ return (mp);
+
+abort:
+ myri10ge_jfree_rtn(j);
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(rx_big_nobuf);
+ return (NULL);
+}
+
+/*
+ * Free all transmit buffers up until the specified index
+ */
+static inline void
+myri10ge_tx_done(struct myri10ge_slice_state *ss, uint32_t mcp_index)
+{
+ myri10ge_tx_ring_t *tx;
+ struct myri10ge_tx_dma_handle_head handles;
+ int idx;
+ int limit = 0;
+
+ tx = &ss->tx;
+ handles.head = NULL;
+ handles.tail = NULL;
+ while (tx->pkt_done != (int)mcp_index) {
+ idx = tx->done & tx->mask;
+
+ /*
+ * mblk & DMA handle attached only to first slot
+ * per buffer in the packet
+ */
+
+ if (tx->info[idx].m) {
+ (void) ddi_dma_unbind_handle(tx->info[idx].handle->h);
+ tx->info[idx].handle->next = handles.head;
+ handles.head = tx->info[idx].handle;
+ if (handles.tail == NULL)
+ handles.tail = tx->info[idx].handle;
+ freeb(tx->info[idx].m);
+ tx->info[idx].m = 0;
+ tx->info[idx].handle = 0;
+ }
+ if (tx->info[idx].ostat.opackets != 0) {
+ tx->stats.multixmt += tx->info[idx].ostat.multixmt;
+ tx->stats.brdcstxmt += tx->info[idx].ostat.brdcstxmt;
+ tx->stats.obytes += tx->info[idx].ostat.obytes;
+ tx->stats.opackets += tx->info[idx].ostat.opackets;
+ tx->info[idx].stat.un.all = 0;
+ tx->pkt_done++;
+ }
+
+ tx->done++;
+ /*
+ * if we stalled the queue, wake it. But Wait until
+ * we have at least 1/2 our slots free.
+ */
+ if ((tx->req - tx->done) < (tx->mask >> 1) &&
+ tx->stall != tx->sched) {
+ mutex_enter(&ss->tx.lock);
+ tx->sched = tx->stall;
+ mutex_exit(&ss->tx.lock);
+ mac_tx_ring_update(ss->mgp->mh, tx->rh);
+ }
+
+ /* limit potential for livelock */
+ if (unlikely(++limit > 2 * tx->mask))
+ break;
+ }
+ if (tx->req == tx->done && tx->stop != NULL) {
+ /*
+ * Nic has sent all pending requests, allow him
+ * to stop polling this queue
+ */
+ mutex_enter(&tx->lock);
+ if (tx->req == tx->done && tx->active) {
+ *(int *)(void *)tx->stop = 1;
+ tx->active = 0;
+ mb();
+ }
+ mutex_exit(&tx->lock);
+ }
+ if (handles.head != NULL)
+ myri10ge_free_tx_handles(tx, &handles);
+}
+
+static void
+myri10ge_mbl_init(struct myri10ge_mblk_list *mbl)
+{
+ mbl->head = NULL;
+ mbl->tail = &mbl->head;
+ mbl->cnt = 0;
+}
+
+/*ARGSUSED*/
+void
+myri10ge_mbl_append(struct myri10ge_slice_state *ss,
+ struct myri10ge_mblk_list *mbl, mblk_t *mp)
+{
+ *(mbl->tail) = mp;
+ mbl->tail = &mp->b_next;
+ mp->b_next = NULL;
+ mbl->cnt++;
+}
+
+
+static inline void
+myri10ge_clean_rx_done(struct myri10ge_slice_state *ss,
+ struct myri10ge_mblk_list *mbl, int limit, boolean_t *stop)
+{
+ myri10ge_rx_done_t *rx_done = &ss->rx_done;
+ struct myri10ge_priv *mgp = ss->mgp;
+ mblk_t *mp;
+ struct lro_entry *lro;
+ uint16_t length;
+ uint16_t checksum;
+
+
+ while (rx_done->entry[rx_done->idx].length != 0) {
+ if (unlikely (*stop)) {
+ break;
+ }
+ length = ntohs(rx_done->entry[rx_done->idx].length);
+ length &= (~MXGEFW_RSS_HASH_MASK);
+
+ /* limit potential for livelock */
+ limit -= length;
+ if (unlikely(limit < 0))
+ break;
+
+ rx_done->entry[rx_done->idx].length = 0;
+ checksum = ntohs(rx_done->entry[rx_done->idx].checksum);
+ if (length <= myri10ge_small_bytes)
+ mp = myri10ge_rx_done_small(ss, length, checksum);
+ else
+ mp = myri10ge_rx_done_big(ss, length, checksum);
+ if (mp != NULL) {
+ if (!myri10ge_lro ||
+ 0 != myri10ge_lro_rx(ss, mp, checksum, mbl))
+ myri10ge_mbl_append(ss, mbl, mp);
+ }
+ rx_done->cnt++;
+ rx_done->idx = rx_done->cnt & (mgp->max_intr_slots - 1);
+ }
+ while (ss->lro_active != NULL) {
+ lro = ss->lro_active;
+ ss->lro_active = lro->next;
+ myri10ge_lro_flush(ss, lro, mbl);
+ }
+}
+
+static void
+myri10ge_intr_rx(struct myri10ge_slice_state *ss)
+{
+ uint64_t gen;
+ struct myri10ge_mblk_list mbl;
+
+ myri10ge_mbl_init(&mbl);
+ if (mutex_tryenter(&ss->rx_lock) == 0)
+ return;
+ gen = ss->rx_gen_num;
+ myri10ge_clean_rx_done(ss, &mbl, MYRI10GE_POLL_NULL,
+ &ss->rx_polling);
+ if (mbl.head != NULL)
+ mac_rx_ring(ss->mgp->mh, ss->rx_rh, mbl.head, gen);
+ mutex_exit(&ss->rx_lock);
+
+}
+
+static mblk_t *
+myri10ge_poll_rx(void *arg, int bytes)
+{
+ struct myri10ge_slice_state *ss = arg;
+ struct myri10ge_mblk_list mbl;
+ boolean_t dummy = B_FALSE;
+
+ if (bytes == 0)
+ return (NULL);
+
+ myri10ge_mbl_init(&mbl);
+ mutex_enter(&ss->rx_lock);
+ if (ss->rx_polling)
+ myri10ge_clean_rx_done(ss, &mbl, bytes, &dummy);
+ else
+ printf("%d: poll_rx: token=%d, polling=%d\n", (int)(ss -
+ ss->mgp->ss), ss->rx_token, ss->rx_polling);
+ mutex_exit(&ss->rx_lock);
+ return (mbl.head);
+}
+
+/*ARGSUSED*/
+static uint_t
+myri10ge_intr(caddr_t arg0, caddr_t arg1)
+{
+ struct myri10ge_slice_state *ss =
+ (struct myri10ge_slice_state *)(void *)arg0;
+ struct myri10ge_priv *mgp = ss->mgp;
+ mcp_irq_data_t *stats = ss->fw_stats;
+ myri10ge_tx_ring_t *tx = &ss->tx;
+ uint32_t send_done_count;
+ uint8_t valid;
+
+
+ /* make sure the DMA has finished */
+ if (!stats->valid) {
+ return (DDI_INTR_UNCLAIMED);
+ }
+ valid = stats->valid;
+
+ /* low bit indicates receives are present */
+ if (valid & 1)
+ myri10ge_intr_rx(ss);
+
+ if (mgp->ddi_intr_type == DDI_INTR_TYPE_FIXED) {
+ /* lower legacy IRQ */
+ *mgp->irq_deassert = 0;
+ if (!myri10ge_deassert_wait)
+ /* don't wait for conf. that irq is low */
+ stats->valid = 0;
+ mb();
+ } else {
+ /* no need to wait for conf. that irq is low */
+ stats->valid = 0;
+ }
+
+ do {
+ /* check for transmit completes and receives */
+ send_done_count = ntohl(stats->send_done_count);
+ if (send_done_count != tx->pkt_done)
+ myri10ge_tx_done(ss, (int)send_done_count);
+ } while (*((volatile uint8_t *) &stats->valid));
+
+ if (stats->stats_updated) {
+ if (mgp->link_state != stats->link_up || stats->link_down) {
+ mgp->link_state = stats->link_up;
+ if (stats->link_down) {
+ mgp->down_cnt += stats->link_down;
+ mgp->link_state = 0;
+ }
+ if (mgp->link_state) {
+ if (myri10ge_verbose)
+ printf("%s: link up\n", mgp->name);
+ mac_link_update(mgp->mh, LINK_STATE_UP);
+ } else {
+ if (myri10ge_verbose)
+ printf("%s: link down\n", mgp->name);
+ mac_link_update(mgp->mh, LINK_STATE_DOWN);
+ }
+ MYRI10GE_NIC_STAT_INC(link_changes);
+ }
+ if (mgp->rdma_tags_available !=
+ ntohl(ss->fw_stats->rdma_tags_available)) {
+ mgp->rdma_tags_available =
+ ntohl(ss->fw_stats->rdma_tags_available);
+ cmn_err(CE_NOTE, "%s: RDMA timed out! "
+ "%d tags left\n", mgp->name,
+ mgp->rdma_tags_available);
+ }
+ }
+
+ mb();
+ /* check to see if we have rx token to pass back */
+ if (valid & 0x1) {
+ mutex_enter(&ss->poll_lock);
+ if (ss->rx_polling) {
+ ss->rx_token = 1;
+ } else {
+ *ss->irq_claim = BE_32(3);
+ ss->rx_token = 0;
+ }
+ mutex_exit(&ss->poll_lock);
+ }
+ *(ss->irq_claim + 1) = BE_32(3);
+ return (DDI_INTR_CLAIMED);
+}
+
+/*
+ * Add or remove a multicast address. This is called with our
+ * macinfo's lock held by GLD, so we do not need to worry about
+ * our own locking here.
+ */
+static int
+myri10ge_m_multicst(void *arg, boolean_t add, const uint8_t *multicastaddr)
+{
+ myri10ge_cmd_t cmd;
+ struct myri10ge_priv *mgp = arg;
+ int status, join_leave;
+
+ if (add)
+ join_leave = MXGEFW_JOIN_MULTICAST_GROUP;
+ else
+ join_leave = MXGEFW_LEAVE_MULTICAST_GROUP;
+ (void) memcpy(&cmd.data0, multicastaddr, 4);
+ (void) memcpy(&cmd.data1, multicastaddr + 4, 2);
+ cmd.data0 = htonl(cmd.data0);
+ cmd.data1 = htonl(cmd.data1);
+ status = myri10ge_send_cmd(mgp, join_leave, &cmd);
+ if (status == 0)
+ return (0);
+
+ cmn_err(CE_WARN, "%s: failed to set multicast address\n",
+ mgp->name);
+ return (status);
+}
+
+
+static int
+myri10ge_m_promisc(void *arg, boolean_t on)
+{
+ struct myri10ge_priv *mgp = arg;
+
+ myri10ge_change_promisc(mgp, on);
+ return (0);
+}
+
+/*
+ * copy an array of mcp_kreq_ether_send_t's to the mcp. Copy
+ * backwards one at a time and handle ring wraps
+ */
+
+static inline void
+myri10ge_submit_req_backwards(myri10ge_tx_ring_t *tx,
+ mcp_kreq_ether_send_t *src, int cnt)
+{
+ int idx, starting_slot;
+ starting_slot = tx->req;
+ while (cnt > 1) {
+ cnt--;
+ idx = (starting_slot + cnt) & tx->mask;
+ myri10ge_pio_copy(&tx->lanai[idx],
+ &src[cnt], sizeof (*src));
+ mb();
+ }
+}
+
+/*
+ * copy an array of mcp_kreq_ether_send_t's to the mcp. Copy
+ * at most 32 bytes at a time, so as to avoid involving the software
+ * pio handler in the nic. We re-write the first segment's flags
+ * to mark them valid only after writing the entire chain
+ */
+
+static inline void
+myri10ge_submit_req(myri10ge_tx_ring_t *tx, mcp_kreq_ether_send_t *src,
+ int cnt)
+{
+ int idx, i;
+ uint32_t *src_ints, *dst_ints;
+ mcp_kreq_ether_send_t *srcp, *dstp, *dst;
+ uint8_t last_flags;
+
+ idx = tx->req & tx->mask;
+
+ last_flags = src->flags;
+ src->flags = 0;
+ mb();
+ dst = dstp = &tx->lanai[idx];
+ srcp = src;
+
+ if ((idx + cnt) < tx->mask) {
+ for (i = 0; i < (cnt - 1); i += 2) {
+ myri10ge_pio_copy(dstp, srcp, 2 * sizeof (*src));
+ mb(); /* force write every 32 bytes */
+ srcp += 2;
+ dstp += 2;
+ }
+ } else {
+ /*
+ * submit all but the first request, and ensure
+ * that it is submitted below
+ */
+ myri10ge_submit_req_backwards(tx, src, cnt);
+ i = 0;
+ }
+ if (i < cnt) {
+ /* submit the first request */
+ myri10ge_pio_copy(dstp, srcp, sizeof (*src));
+ mb(); /* barrier before setting valid flag */
+ }
+
+ /* re-write the last 32-bits with the valid flags */
+ src->flags |= last_flags;
+ src_ints = (uint32_t *)src;
+ src_ints += 3;
+ dst_ints = (uint32_t *)dst;
+ dst_ints += 3;
+ *dst_ints = *src_ints;
+ tx->req += cnt;
+ mb();
+ /* notify NIC to poll this tx ring */
+ if (!tx->active && tx->go != NULL) {
+ *(int *)(void *)tx->go = 1;
+ tx->active = 1;
+ tx->activate++;
+ mb();
+ }
+}
+
+/* ARGSUSED */
+static inline void
+myri10ge_lso_info_get(mblk_t *mp, uint32_t *mss, uint32_t *flags)
+{
+ uint32_t lso_flag;
+ lso_info_get(mp, mss, &lso_flag);
+ (*flags) |= lso_flag;
+}
+
+
+/* like pullupmsg, except preserve hcksum/LSO attributes */
+static int
+myri10ge_pullup(struct myri10ge_slice_state *ss, mblk_t *mp)
+{
+ uint32_t start, stuff, tx_offload_flags, mss;
+ int ok;
+
+ mss = 0;
+ hcksum_retrieve(mp, NULL, NULL, &start, &stuff, NULL, NULL,
+ &tx_offload_flags);
+ myri10ge_lso_info_get(mp, &mss, &tx_offload_flags);
+
+ ok = pullupmsg(mp, -1);
+ if (!ok) {
+ printf("pullupmsg failed");
+ return (DDI_FAILURE);
+ }
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(xmit_pullup);
+ (void) hcksum_assoc(mp, NULL, NULL, start, stuff, NULL,
+ NULL, tx_offload_flags, 0);
+ if (tx_offload_flags & HW_LSO)
+ DB_LSOMSS(mp) = (uint16_t)mss;
+ lso_info_set(mp, mss, tx_offload_flags);
+ return (DDI_SUCCESS);
+}
+
+static inline void
+myri10ge_tx_stat(struct myri10ge_tx_pkt_stats *s, struct ether_header *eh,
+ int opackets, int obytes)
+{
+ s->un.all = 0;
+ if (eh->ether_dhost.ether_addr_octet[0] & 1) {
+ if (0 == (bcmp(eh->ether_dhost.ether_addr_octet,
+ myri10ge_broadcastaddr, sizeof (eh->ether_dhost))))
+ s->un.s.brdcstxmt = 1;
+ else
+ s->un.s.multixmt = 1;
+ }
+ s->un.s.opackets = (uint16_t)opackets;
+ s->un.s.obytes = obytes;
+}
+
+static int
+myri10ge_tx_copy(struct myri10ge_slice_state *ss, mblk_t *mp,
+ mcp_kreq_ether_send_t *req)
+{
+ myri10ge_tx_ring_t *tx = &ss->tx;
+ caddr_t ptr;
+ struct myri10ge_tx_copybuf *cp;
+ mblk_t *bp;
+ int idx, mblen, avail;
+ uint16_t len;
+
+ mutex_enter(&tx->lock);
+ avail = tx->mask - (tx->req - tx->done);
+ if (avail <= 1) {
+ mutex_exit(&tx->lock);
+ return (EBUSY);
+ }
+ idx = tx->req & tx->mask;
+ cp = &tx->cp[idx];
+ ptr = cp->va;
+ for (len = 0, bp = mp; bp != NULL; bp = bp->b_cont) {
+ mblen = MBLKL(bp);
+ bcopy(bp->b_rptr, ptr, mblen);
+ ptr += mblen;
+ len += mblen;
+ }
+ /* ensure runts are padded to 60 bytes */
+ if (len < 60) {
+ bzero(ptr, 64 - len);
+ len = 60;
+ }
+ req->addr_low = cp->dma.low;
+ req->addr_high = cp->dma.high;
+ req->length = htons(len);
+ req->pad = 0;
+ req->rdma_count = 1;
+ myri10ge_tx_stat(&tx->info[idx].stat,
+ (struct ether_header *)(void *)cp->va, 1, len);
+ (void) ddi_dma_sync(cp->dma.handle, 0, len, DDI_DMA_SYNC_FORDEV);
+ myri10ge_submit_req(&ss->tx, req, 1);
+ mutex_exit(&tx->lock);
+ freemsg(mp);
+ return (DDI_SUCCESS);
+}
+
+
+static void
+myri10ge_send_locked(myri10ge_tx_ring_t *tx, mcp_kreq_ether_send_t *req_list,
+ struct myri10ge_tx_buffer_state *tx_info,
+ int count)
+{
+ int i, idx;
+
+ idx = 0; /* gcc -Wuninitialized */
+ /* store unmapping and bp info for tx irq handler */
+ for (i = 0; i < count; i++) {
+ idx = (tx->req + i) & tx->mask;
+ tx->info[idx].m = tx_info[i].m;
+ tx->info[idx].handle = tx_info[i].handle;
+ }
+ tx->info[idx].stat.un.all = tx_info[0].stat.un.all;
+
+ /* submit the frame to the nic */
+ myri10ge_submit_req(tx, req_list, count);
+
+
+}
+
+
+
+static void
+myri10ge_copydata(mblk_t *mp, int off, int len, caddr_t buf)
+{
+ mblk_t *bp;
+ int seglen;
+ uint_t count;
+
+ bp = mp;
+
+ while (off > 0) {
+ seglen = MBLKL(bp);
+ if (off < seglen)
+ break;
+ off -= seglen;
+ bp = bp->b_cont;
+ }
+ while (len > 0) {
+ seglen = MBLKL(bp);
+ count = min(seglen - off, len);
+ bcopy(bp->b_rptr + off, buf, count);
+ len -= count;
+ buf += count;
+ off = 0;
+ bp = bp->b_cont;
+ }
+}
+
+static int
+myri10ge_ether_parse_header(mblk_t *mp)
+{
+ struct ether_header eh_copy;
+ struct ether_header *eh;
+ int eth_hdr_len, seglen;
+
+ seglen = MBLKL(mp);
+ eth_hdr_len = sizeof (*eh);
+ if (seglen < eth_hdr_len) {
+ myri10ge_copydata(mp, 0, eth_hdr_len, (caddr_t)&eh_copy);
+ eh = &eh_copy;
+ } else {
+ eh = (struct ether_header *)(void *)mp->b_rptr;
+ }
+ if (eh->ether_type == BE_16(ETHERTYPE_VLAN)) {
+ eth_hdr_len += 4;
+ }
+
+ return (eth_hdr_len);
+}
+
+static int
+myri10ge_lso_parse_header(mblk_t *mp, int off)
+{
+ char buf[128];
+ int seglen;
+ struct ip *ip;
+ struct tcphdr *tcp;
+
+ seglen = MBLKL(mp);
+ if (seglen < off + sizeof (*ip)) {
+ myri10ge_copydata(mp, off, sizeof (*ip), buf);
+ ip = (struct ip *)(void *)buf;
+ } else {
+ ip = (struct ip *)(void *)(mp->b_rptr + off);
+ }
+ if (seglen < off + (ip->ip_hl << 2) + sizeof (*tcp)) {
+ myri10ge_copydata(mp, off,
+ (ip->ip_hl << 2) + sizeof (*tcp), buf);
+ ip = (struct ip *)(void *)buf;
+ }
+ tcp = (struct tcphdr *)(void *)((char *)ip + (ip->ip_hl << 2));
+ return (off + ((ip->ip_hl + tcp->th_off) << 2));
+}
+
+static int
+myri10ge_tx_tso_copy(struct myri10ge_slice_state *ss, mblk_t *mp,
+ mcp_kreq_ether_send_t *req_list, int hdr_size, int pkt_size,
+ uint16_t mss, uint8_t cksum_offset)
+{
+ myri10ge_tx_ring_t *tx = &ss->tx;
+ struct myri10ge_priv *mgp = ss->mgp;
+ mblk_t *bp;
+ mcp_kreq_ether_send_t *req;
+ struct myri10ge_tx_copybuf *cp;
+ caddr_t rptr, ptr;
+ int mblen, count, cum_len, mss_resid, tx_req, pkt_size_tmp;
+ int resid, avail, idx, hdr_size_tmp, tx_boundary;
+ int rdma_count;
+ uint32_t seglen, len, boundary, low, high_swapped;
+ uint16_t pseudo_hdr_offset = htons(mss);
+ uint8_t flags;
+
+ tx_boundary = mgp->tx_boundary;
+ hdr_size_tmp = hdr_size;
+ resid = tx_boundary;
+ count = 1;
+ mutex_enter(&tx->lock);
+
+ /* check to see if the slots are really there */
+ avail = tx->mask - (tx->req - tx->done);
+ if (unlikely(avail <= MYRI10GE_MAX_SEND_DESC_TSO)) {
+ atomic_add_32(&tx->stall, 1);
+ mutex_exit(&tx->lock);
+ return (EBUSY);
+ }
+
+ /* copy */
+ cum_len = -hdr_size;
+ count = 0;
+ req = req_list;
+ idx = tx->mask & tx->req;
+ cp = &tx->cp[idx];
+ low = ntohl(cp->dma.low);
+ ptr = cp->va;
+ cp->len = 0;
+ if (mss) {
+ int payload = pkt_size - hdr_size;
+ uint16_t opackets = (payload / mss) + ((payload % mss) != 0);
+ tx->info[idx].ostat.opackets = opackets;
+ tx->info[idx].ostat.obytes = (opackets - 1) * hdr_size
+ + pkt_size;
+ }
+ hdr_size_tmp = hdr_size;
+ mss_resid = mss;
+ flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
+ tx_req = tx->req;
+ for (bp = mp; bp != NULL; bp = bp->b_cont) {
+ mblen = MBLKL(bp);
+ rptr = (caddr_t)bp->b_rptr;
+ len = min(hdr_size_tmp, mblen);
+ if (len) {
+ bcopy(rptr, ptr, len);
+ rptr += len;
+ ptr += len;
+ resid -= len;
+ mblen -= len;
+ hdr_size_tmp -= len;
+ cp->len += len;
+ if (hdr_size_tmp)
+ continue;
+ if (resid < mss) {
+ tx_req++;
+ idx = tx->mask & tx_req;
+ cp = &tx->cp[idx];
+ low = ntohl(cp->dma.low);
+ ptr = cp->va;
+ resid = tx_boundary;
+ }
+ }
+ while (mblen) {
+ len = min(mss_resid, mblen);
+ bcopy(rptr, ptr, len);
+ mss_resid -= len;
+ resid -= len;
+ mblen -= len;
+ rptr += len;
+ ptr += len;
+ cp->len += len;
+ if (mss_resid == 0) {
+ mss_resid = mss;
+ if (resid < mss) {
+ tx_req++;
+ idx = tx->mask & tx_req;
+ cp = &tx->cp[idx];
+ cp->len = 0;
+ low = ntohl(cp->dma.low);
+ ptr = cp->va;
+ resid = tx_boundary;
+ }
+ }
+ }
+ }
+
+ req = req_list;
+ pkt_size_tmp = pkt_size;
+ count = 0;
+ rdma_count = 0;
+ tx_req = tx->req;
+ while (pkt_size_tmp) {
+ idx = tx->mask & tx_req;
+ cp = &tx->cp[idx];
+ high_swapped = cp->dma.high;
+ low = ntohl(cp->dma.low);
+ len = cp->len;
+ if (len == 0) {
+ printf("len=0! pkt_size_tmp=%d, pkt_size=%d\n",
+ pkt_size_tmp, pkt_size);
+ for (bp = mp; bp != NULL; bp = bp->b_cont) {
+ mblen = MBLKL(bp);
+ printf("mblen:%d\n", mblen);
+ }
+ pkt_size_tmp = pkt_size;
+ tx_req = tx->req;
+ while (pkt_size_tmp > 0) {
+ idx = tx->mask & tx_req;
+ cp = &tx->cp[idx];
+ printf("cp->len = %d\n", cp->len);
+ pkt_size_tmp -= cp->len;
+ tx_req++;
+ }
+ printf("dropped\n");
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(xmit_err);
+ goto done;
+ }
+ pkt_size_tmp -= len;
+ while (len) {
+ while (len) {
+ uint8_t flags_next;
+ int cum_len_next;
+
+ boundary = (low + mgp->tx_boundary) &
+ ~(mgp->tx_boundary - 1);
+ seglen = boundary - low;
+ if (seglen > len)
+ seglen = len;
+
+ flags_next = flags & ~MXGEFW_FLAGS_FIRST;
+ cum_len_next = cum_len + seglen;
+ (req-rdma_count)->rdma_count = rdma_count + 1;
+ if (likely(cum_len >= 0)) {
+ /* payload */
+ int next_is_first, chop;
+
+ chop = (cum_len_next > mss);
+ cum_len_next = cum_len_next % mss;
+ next_is_first = (cum_len_next == 0);
+ flags |= chop *
+ MXGEFW_FLAGS_TSO_CHOP;
+ flags_next |= next_is_first *
+ MXGEFW_FLAGS_FIRST;
+ rdma_count |= -(chop | next_is_first);
+ rdma_count += chop & !next_is_first;
+ } else if (likely(cum_len_next >= 0)) {
+ /* header ends */
+ int small;
+
+ rdma_count = -1;
+ cum_len_next = 0;
+ seglen = -cum_len;
+ small = (mss <= MXGEFW_SEND_SMALL_SIZE);
+ flags_next = MXGEFW_FLAGS_TSO_PLD |
+ MXGEFW_FLAGS_FIRST |
+ (small * MXGEFW_FLAGS_SMALL);
+ }
+ req->addr_high = high_swapped;
+ req->addr_low = htonl(low);
+ req->pseudo_hdr_offset = pseudo_hdr_offset;
+ req->pad = 0; /* complete solid 16-byte block */
+ req->rdma_count = 1;
+ req->cksum_offset = cksum_offset;
+ req->length = htons(seglen);
+ req->flags = flags | ((cum_len & 1) *
+ MXGEFW_FLAGS_ALIGN_ODD);
+ if (cksum_offset > seglen)
+ cksum_offset -= seglen;
+ else
+ cksum_offset = 0;
+ low += seglen;
+ len -= seglen;
+ cum_len = cum_len_next;
+ req++;
+ req->flags = 0;
+ flags = flags_next;
+ count++;
+ rdma_count++;
+ }
+ }
+ tx_req++;
+ }
+ (req-rdma_count)->rdma_count = (uint8_t)rdma_count;
+ do {
+ req--;
+ req->flags |= MXGEFW_FLAGS_TSO_LAST;
+ } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
+ MXGEFW_FLAGS_FIRST)));
+
+ myri10ge_submit_req(tx, req_list, count);
+done:
+ mutex_exit(&tx->lock);
+ freemsg(mp);
+ return (DDI_SUCCESS);
+}
+
+/*
+ * Try to send the chain of buffers described by the mp. We must not
+ * encapsulate more than eth->tx.req - eth->tx.done, or
+ * MXGEFW_MAX_SEND_DESC, whichever is more.
+ */
+
+static int
+myri10ge_send(struct myri10ge_slice_state *ss, mblk_t *mp,
+ mcp_kreq_ether_send_t *req_list, struct myri10ge_tx_buffer_state *tx_info)
+{
+ struct myri10ge_priv *mgp = ss->mgp;
+ myri10ge_tx_ring_t *tx = &ss->tx;
+ mcp_kreq_ether_send_t *req;
+ struct myri10ge_tx_dma_handle *handles, *dma_handle = NULL;
+ mblk_t *bp;
+ ddi_dma_cookie_t cookie;
+ int err, rv, count, avail, mblen, try_pullup, i, max_segs, maclen,
+ rdma_count, cum_len, lso_hdr_size;
+ uint32_t start, stuff, tx_offload_flags;
+ uint32_t seglen, len, mss, boundary, low, high_swapped;
+ uint_t ncookies;
+ uint16_t pseudo_hdr_offset;
+ uint8_t flags, cksum_offset, odd_flag;
+ int pkt_size;
+ int lso_copy = myri10ge_lso_copy;
+ try_pullup = 1;
+
+again:
+ /* Setup checksum offloading, if needed */
+ hcksum_retrieve(mp, NULL, NULL, &start, &stuff, NULL, NULL,
+ &tx_offload_flags);
+ myri10ge_lso_info_get(mp, &mss, &tx_offload_flags);
+ if (tx_offload_flags & HW_LSO) {
+ max_segs = MYRI10GE_MAX_SEND_DESC_TSO;
+ if ((tx_offload_flags & HCK_PARTIALCKSUM) == 0) {
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(xmit_lsobadflags);
+ freemsg(mp);
+ return (DDI_SUCCESS);
+ }
+ } else {
+ max_segs = MXGEFW_MAX_SEND_DESC;
+ mss = 0;
+ }
+ req = req_list;
+ cksum_offset = 0;
+ pseudo_hdr_offset = 0;
+
+ /* leave an extra slot keep the ring from wrapping */
+ avail = tx->mask - (tx->req - tx->done);
+
+ /*
+ * If we have > MXGEFW_MAX_SEND_DESC, then any over-length
+ * message will need to be pulled up in order to fit.
+ * Otherwise, we are low on transmit descriptors, it is
+ * probably better to stall and try again rather than pullup a
+ * message to fit.
+ */
+
+ if (avail < max_segs) {
+ err = EBUSY;
+ atomic_add_32(&tx->stall_early, 1);
+ goto stall;
+ }
+
+ /* find out how long the frame is and how many segments it is */
+ count = 0;
+ odd_flag = 0;
+ pkt_size = 0;
+ flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
+ for (bp = mp; bp != NULL; bp = bp->b_cont) {
+ dblk_t *dbp;
+ mblen = MBLKL(bp);
+ if (mblen == 0) {
+ /*
+ * we can't simply skip over 0-length mblks
+ * because the hardware can't deal with them,
+ * and we could leak them.
+ */
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(xmit_zero_len);
+ err = EIO;
+ goto pullup;
+ }
+ /*
+ * There's no advantage to copying most gesballoc
+ * attached blocks, so disable lso copy in that case
+ */
+ if (mss && lso_copy == 1 && ((dbp = bp->b_datap) != NULL)) {
+ if ((void *)dbp->db_lastfree != myri10ge_db_lastfree) {
+ lso_copy = 0;
+ }
+ }
+ pkt_size += mblen;
+ count++;
+ }
+
+ /* Try to pull up excessivly long chains */
+ if (count >= max_segs) {
+ err = myri10ge_pullup(ss, mp);
+ if (likely(err == DDI_SUCCESS)) {
+ count = 1;
+ } else {
+ if (count < MYRI10GE_MAX_SEND_DESC_TSO) {
+ /*
+ * just let the h/w send it, it will be
+ * inefficient, but us better than dropping
+ */
+ max_segs = MYRI10GE_MAX_SEND_DESC_TSO;
+ } else {
+ /* drop it */
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(xmit_err);
+ freemsg(mp);
+ return (0);
+ }
+ }
+ }
+
+ cum_len = 0;
+ maclen = myri10ge_ether_parse_header(mp);
+
+ if (tx_offload_flags & HCK_PARTIALCKSUM) {
+
+ cksum_offset = start + maclen;
+ pseudo_hdr_offset = htons(stuff + maclen);
+ odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
+ flags |= MXGEFW_FLAGS_CKSUM;
+ }
+
+ lso_hdr_size = 0; /* -Wunitinialized */
+ if (mss) { /* LSO */
+ /* this removes any CKSUM flag from before */
+ flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
+ /*
+ * parse the headers and set cum_len to a negative
+ * value to reflect the offset of the TCP payload
+ */
+ lso_hdr_size = myri10ge_lso_parse_header(mp, maclen);
+ cum_len = -lso_hdr_size;
+ if ((mss < mgp->tx_boundary) && lso_copy) {
+ err = myri10ge_tx_tso_copy(ss, mp, req_list,
+ lso_hdr_size, pkt_size, mss, cksum_offset);
+ return (err);
+ }
+
+ /*
+ * for TSO, pseudo_hdr_offset holds mss. The firmware
+ * figures out where to put the checksum by parsing
+ * the header.
+ */
+
+ pseudo_hdr_offset = htons(mss);
+ } else if (pkt_size <= MXGEFW_SEND_SMALL_SIZE) {
+ flags |= MXGEFW_FLAGS_SMALL;
+ if (pkt_size < myri10ge_tx_copylen) {
+ req->cksum_offset = cksum_offset;
+ req->pseudo_hdr_offset = pseudo_hdr_offset;
+ req->flags = flags;
+ err = myri10ge_tx_copy(ss, mp, req);
+ return (err);
+ }
+ cum_len = 0;
+ }
+
+ /* pull one DMA handle for each bp from our freelist */
+ handles = NULL;
+ err = myri10ge_alloc_tx_handles(ss, count, &handles);
+ if (err != DDI_SUCCESS) {
+ err = DDI_FAILURE;
+ goto stall;
+ }
+ count = 0;
+ rdma_count = 0;
+ for (bp = mp; bp != NULL; bp = bp->b_cont) {
+ mblen = MBLKL(bp);
+ dma_handle = handles;
+ handles = handles->next;
+
+ rv = ddi_dma_addr_bind_handle(dma_handle->h, NULL,
+ (caddr_t)bp->b_rptr, mblen,
+ DDI_DMA_WRITE | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL,
+ &cookie, &ncookies);
+ if (unlikely(rv != DDI_DMA_MAPPED)) {
+ err = EIO;
+ try_pullup = 0;
+ dma_handle->next = handles;
+ handles = dma_handle;
+ goto abort_with_handles;
+ }
+
+ /* reserve the slot */
+ tx_info[count].m = bp;
+ tx_info[count].handle = dma_handle;
+
+ for (; ; ) {
+ low = MYRI10GE_LOWPART_TO_U32(cookie.dmac_laddress);
+ high_swapped =
+ htonl(MYRI10GE_HIGHPART_TO_U32(
+ cookie.dmac_laddress));
+ len = (uint32_t)cookie.dmac_size;
+ while (len) {
+ uint8_t flags_next;
+ int cum_len_next;
+
+ boundary = (low + mgp->tx_boundary) &
+ ~(mgp->tx_boundary - 1);
+ seglen = boundary - low;
+ if (seglen > len)
+ seglen = len;
+
+ flags_next = flags & ~MXGEFW_FLAGS_FIRST;
+ cum_len_next = cum_len + seglen;
+ if (mss) {
+ (req-rdma_count)->rdma_count =
+ rdma_count + 1;
+ if (likely(cum_len >= 0)) {
+ /* payload */
+ int next_is_first, chop;
+
+ chop = (cum_len_next > mss);
+ cum_len_next =
+ cum_len_next % mss;
+ next_is_first =
+ (cum_len_next == 0);
+ flags |= chop *
+ MXGEFW_FLAGS_TSO_CHOP;
+ flags_next |= next_is_first *
+ MXGEFW_FLAGS_FIRST;
+ rdma_count |=
+ -(chop | next_is_first);
+ rdma_count +=
+ chop & !next_is_first;
+ } else if (likely(cum_len_next >= 0)) {
+ /* header ends */
+ int small;
+
+ rdma_count = -1;
+ cum_len_next = 0;
+ seglen = -cum_len;
+ small = (mss <=
+ MXGEFW_SEND_SMALL_SIZE);
+ flags_next =
+ MXGEFW_FLAGS_TSO_PLD
+ | MXGEFW_FLAGS_FIRST
+ | (small *
+ MXGEFW_FLAGS_SMALL);
+ }
+ }
+ req->addr_high = high_swapped;
+ req->addr_low = htonl(low);
+ req->pseudo_hdr_offset = pseudo_hdr_offset;
+ req->pad = 0; /* complete solid 16-byte block */
+ req->rdma_count = 1;
+ req->cksum_offset = cksum_offset;
+ req->length = htons(seglen);
+ req->flags = flags | ((cum_len & 1) * odd_flag);
+ if (cksum_offset > seglen)
+ cksum_offset -= seglen;
+ else
+ cksum_offset = 0;
+ low += seglen;
+ len -= seglen;
+ cum_len = cum_len_next;
+ count++;
+ rdma_count++;
+ /* make sure all the segments will fit */
+ if (unlikely(count >= max_segs)) {
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(
+ xmit_lowbuf);
+ /* may try a pullup */
+ err = EBUSY;
+ if (try_pullup)
+ try_pullup = 2;
+ goto abort_with_handles;
+ }
+ req++;
+ req->flags = 0;
+ flags = flags_next;
+ tx_info[count].m = 0;
+ }
+ ncookies--;
+ if (ncookies == 0)
+ break;
+ ddi_dma_nextcookie(dma_handle->h, &cookie);
+ }
+ }
+ (req-rdma_count)->rdma_count = (uint8_t)rdma_count;
+
+ if (mss) {
+ do {
+ req--;
+ req->flags |= MXGEFW_FLAGS_TSO_LAST;
+ } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
+ MXGEFW_FLAGS_FIRST)));
+ }
+
+ /* calculate tx stats */
+ if (mss) {
+ uint16_t opackets;
+ int payload;
+
+ payload = pkt_size - lso_hdr_size;
+ opackets = (payload / mss) + ((payload % mss) != 0);
+ tx_info[0].stat.un.all = 0;
+ tx_info[0].ostat.opackets = opackets;
+ tx_info[0].ostat.obytes = (opackets - 1) * lso_hdr_size
+ + pkt_size;
+ } else {
+ myri10ge_tx_stat(&tx_info[0].stat,
+ (struct ether_header *)(void *)mp->b_rptr, 1, pkt_size);
+ }
+ mutex_enter(&tx->lock);
+
+ /* check to see if the slots are really there */
+ avail = tx->mask - (tx->req - tx->done);
+ if (unlikely(avail <= count)) {
+ mutex_exit(&tx->lock);
+ err = 0;
+ goto late_stall;
+ }
+
+ myri10ge_send_locked(tx, req_list, tx_info, count);
+ mutex_exit(&tx->lock);
+ return (DDI_SUCCESS);
+
+late_stall:
+ try_pullup = 0;
+ atomic_add_32(&tx->stall_late, 1);
+
+abort_with_handles:
+ /* unbind and free handles from previous mblks */
+ for (i = 0; i < count; i++) {
+ bp = tx_info[i].m;
+ tx_info[i].m = 0;
+ if (bp) {
+ dma_handle = tx_info[i].handle;
+ (void) ddi_dma_unbind_handle(dma_handle->h);
+ dma_handle->next = handles;
+ handles = dma_handle;
+ tx_info[i].handle = NULL;
+ tx_info[i].m = NULL;
+ }
+ }
+ myri10ge_free_tx_handle_slist(tx, handles);
+pullup:
+ if (try_pullup) {
+ err = myri10ge_pullup(ss, mp);
+ if (err != DDI_SUCCESS && try_pullup == 2) {
+ /* drop */
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(xmit_err);
+ freemsg(mp);
+ return (0);
+ }
+ try_pullup = 0;
+ goto again;
+ }
+
+stall:
+ if (err != 0) {
+ if (err == EBUSY) {
+ atomic_add_32(&tx->stall, 1);
+ } else {
+ MYRI10GE_ATOMIC_SLICE_STAT_INC(xmit_err);
+ }
+ }
+ return (err);
+}
+
+static mblk_t *
+myri10ge_send_wrapper(void *arg, mblk_t *mp)
+{
+ struct myri10ge_slice_state *ss = arg;
+ int err = 0;
+ mcp_kreq_ether_send_t *req_list;
+#if defined(__i386)
+ /*
+ * We need about 2.5KB of scratch space to handle transmits.
+ * i86pc has only 8KB of kernel stack space, so we malloc the
+ * scratch space there rather than keeping it on the stack.
+ */
+ size_t req_size, tx_info_size;
+ struct myri10ge_tx_buffer_state *tx_info;
+ caddr_t req_bytes;
+
+ req_size = sizeof (*req_list) * (MYRI10GE_MAX_SEND_DESC_TSO + 4)
+ + 8;
+ req_bytes = kmem_alloc(req_size, KM_SLEEP);
+ tx_info_size = sizeof (*tx_info) * (MYRI10GE_MAX_SEND_DESC_TSO + 1);
+ tx_info = kmem_alloc(tx_info_size, KM_SLEEP);
+#else
+ char req_bytes[sizeof (*req_list) * (MYRI10GE_MAX_SEND_DESC_TSO + 4)
+ + 8];
+ struct myri10ge_tx_buffer_state tx_info[MYRI10GE_MAX_SEND_DESC_TSO + 1];
+#endif
+
+ /* ensure req_list entries are aligned to 8 bytes */
+ req_list = (struct mcp_kreq_ether_send *)
+ (((unsigned long)req_bytes + 7UL) & ~7UL);
+
+ err = myri10ge_send(ss, mp, req_list, tx_info);
+
+#if defined(__i386)
+ kmem_free(tx_info, tx_info_size);
+ kmem_free(req_bytes, req_size);
+#endif
+ if (err)
+ return (mp);
+ else
+ return (NULL);
+}
+
+static int
+myri10ge_addmac(void *arg, const uint8_t *mac_addr)
+{
+ struct myri10ge_priv *mgp = arg;
+ int err;
+
+ if (mac_addr == NULL)
+ return (EINVAL);
+
+ mutex_enter(&mgp->intrlock);
+ if (mgp->macaddr_cnt) {
+ mutex_exit(&mgp->intrlock);
+ return (ENOSPC);
+ }
+ err = myri10ge_m_unicst(mgp, mac_addr);
+ if (!err)
+ mgp->macaddr_cnt++;
+
+ mutex_exit(&mgp->intrlock);
+ if (err)
+ return (err);
+
+ bcopy(mac_addr, mgp->mac_addr, sizeof (mgp->mac_addr));
+ return (0);
+}
+
+/*ARGSUSED*/
+static int
+myri10ge_remmac(void *arg, const uint8_t *mac_addr)
+{
+ struct myri10ge_priv *mgp = arg;
+
+ mutex_enter(&mgp->intrlock);
+ mgp->macaddr_cnt--;
+ mutex_exit(&mgp->intrlock);
+
+ return (0);
+}
+
+/*ARGSUSED*/
+static void
+myri10ge_fill_group(void *arg, mac_ring_type_t rtype, const int index,
+ mac_group_info_t *infop, mac_group_handle_t gh)
+{
+ struct myri10ge_priv *mgp = arg;
+
+ if (rtype != MAC_RING_TYPE_RX)
+ return;
+
+ infop->mgi_driver = (mac_group_driver_t)mgp;
+ infop->mgi_start = NULL;
+ infop->mgi_stop = NULL;
+ infop->mgi_addmac = myri10ge_addmac;
+ infop->mgi_remmac = myri10ge_remmac;
+ infop->mgi_count = mgp->num_slices;
+}
+
+static int
+myri10ge_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num)
+{
+ struct myri10ge_slice_state *ss;
+
+ ss = (struct myri10ge_slice_state *)rh;
+ mutex_enter(&ss->rx_lock);
+ ss->rx_gen_num = mr_gen_num;
+ mutex_exit(&ss->rx_lock);
+ return (0);
+}
+
+static int
+myri10ge_rx_ring_intr_disable(mac_intr_handle_t intrh)
+{
+ struct myri10ge_slice_state *ss;
+
+ ss = (struct myri10ge_slice_state *)intrh;
+ mutex_enter(&ss->poll_lock);
+ ss->rx_polling = B_TRUE;
+ mutex_exit(&ss->poll_lock);
+ return (0);
+}
+
+static int
+myri10ge_rx_ring_intr_enable(mac_intr_handle_t intrh)
+{
+ struct myri10ge_slice_state *ss;
+
+ ss = (struct myri10ge_slice_state *)intrh;
+ mutex_enter(&ss->poll_lock);
+ ss->rx_polling = B_FALSE;
+ if (ss->rx_token) {
+ *ss->irq_claim = BE_32(3);
+ ss->rx_token = 0;
+ }
+ mutex_exit(&ss->poll_lock);
+ return (0);
+}
+
+/*ARGSUSED*/
+static void
+myri10ge_fill_ring(void *arg, mac_ring_type_t rtype, const int rg_index,
+ const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh)
+{
+ struct myri10ge_priv *mgp = arg;
+ struct myri10ge_slice_state *ss;
+ mac_intr_t *mintr = &infop->mri_intr;
+
+ ASSERT((unsigned int)ring_index < mgp->num_slices);
+
+ ss = &mgp->ss[ring_index];
+ switch (rtype) {
+ case MAC_RING_TYPE_RX:
+ ss->rx_rh = rh;
+ infop->mri_driver = (mac_ring_driver_t)ss;
+ infop->mri_start = myri10ge_ring_start;
+ infop->mri_stop = NULL;
+ infop->mri_poll = myri10ge_poll_rx;
+ mintr->mi_handle = (mac_intr_handle_t)ss;
+ mintr->mi_enable = myri10ge_rx_ring_intr_enable;
+ mintr->mi_disable = myri10ge_rx_ring_intr_disable;
+ break;
+ case MAC_RING_TYPE_TX:
+ ss->tx.rh = rh;
+ infop->mri_driver = (mac_ring_driver_t)ss;
+ infop->mri_start = NULL;
+ infop->mri_stop = NULL;
+ infop->mri_tx = myri10ge_send_wrapper;
+ break;
+ default:
+ break;
+ }
+}
+
+static void
+myri10ge_nic_stat_destroy(struct myri10ge_priv *mgp)
+{
+ if (mgp->ksp_stat == NULL)
+ return;
+
+ kstat_delete(mgp->ksp_stat);
+ mgp->ksp_stat = NULL;
+}
+
+static void
+myri10ge_slice_stat_destroy(struct myri10ge_slice_state *ss)
+{
+ if (ss->ksp_stat == NULL)
+ return;
+
+ kstat_delete(ss->ksp_stat);
+ ss->ksp_stat = NULL;
+}
+
+static void
+myri10ge_info_destroy(struct myri10ge_priv *mgp)
+{
+ if (mgp->ksp_info == NULL)
+ return;
+
+ kstat_delete(mgp->ksp_info);
+ mgp->ksp_info = NULL;
+}
+
+static int
+myri10ge_nic_stat_kstat_update(kstat_t *ksp, int rw)
+{
+ struct myri10ge_nic_stat *ethstat;
+ struct myri10ge_priv *mgp;
+ mcp_irq_data_t *fw_stats;
+
+
+ if (rw == KSTAT_WRITE)
+ return (EACCES);
+
+ ethstat = (struct myri10ge_nic_stat *)ksp->ks_data;
+ mgp = (struct myri10ge_priv *)ksp->ks_private;
+ fw_stats = mgp->ss[0].fw_stats;
+
+ ethstat->dma_read_bw_MBs.value.ul = mgp->read_dma;
+ ethstat->dma_write_bw_MBs.value.ul = mgp->write_dma;
+ ethstat->dma_read_write_bw_MBs.value.ul = mgp->read_write_dma;
+ if (myri10ge_tx_dma_attr.dma_attr_flags & DDI_DMA_FORCE_PHYSICAL)
+ ethstat->dma_force_physical.value.ul = 1;
+ else
+ ethstat->dma_force_physical.value.ul = 0;
+ ethstat->lanes.value.ul = mgp->pcie_link_width;
+ ethstat->dropped_bad_crc32.value.ul =
+ ntohl(fw_stats->dropped_bad_crc32);
+ ethstat->dropped_bad_phy.value.ul =
+ ntohl(fw_stats->dropped_bad_phy);
+ ethstat->dropped_link_error_or_filtered.value.ul =
+ ntohl(fw_stats->dropped_link_error_or_filtered);
+ ethstat->dropped_link_overflow.value.ul =
+ ntohl(fw_stats->dropped_link_overflow);
+ ethstat->dropped_multicast_filtered.value.ul =
+ ntohl(fw_stats->dropped_multicast_filtered);
+ ethstat->dropped_no_big_buffer.value.ul =
+ ntohl(fw_stats->dropped_no_big_buffer);
+ ethstat->dropped_no_small_buffer.value.ul =
+ ntohl(fw_stats->dropped_no_small_buffer);
+ ethstat->dropped_overrun.value.ul =
+ ntohl(fw_stats->dropped_overrun);
+ ethstat->dropped_pause.value.ul =
+ ntohl(fw_stats->dropped_pause);
+ ethstat->dropped_runt.value.ul =
+ ntohl(fw_stats->dropped_runt);
+ ethstat->link_up.value.ul =
+ ntohl(fw_stats->link_up);
+ ethstat->dropped_unicast_filtered.value.ul =
+ ntohl(fw_stats->dropped_unicast_filtered);
+ return (0);
+}
+
+static int
+myri10ge_slice_stat_kstat_update(kstat_t *ksp, int rw)
+{
+ struct myri10ge_slice_stat *ethstat;
+ struct myri10ge_slice_state *ss;
+
+ if (rw == KSTAT_WRITE)
+ return (EACCES);
+
+ ethstat = (struct myri10ge_slice_stat *)ksp->ks_data;
+ ss = (struct myri10ge_slice_state *)ksp->ks_private;
+
+ ethstat->rx_big.value.ul = ss->j_rx_cnt;
+ ethstat->rx_bigbuf_firmware.value.ul = ss->rx_big.cnt - ss->j_rx_cnt;
+ ethstat->rx_bigbuf_pool.value.ul =
+ ss->jpool.num_alloc - ss->jbufs_for_smalls;
+ ethstat->rx_bigbuf_smalls.value.ul = ss->jbufs_for_smalls;
+ ethstat->rx_small.value.ul = ss->rx_small.cnt -
+ (ss->rx_small.mask + 1);
+ ethstat->tx_done.value.ul = ss->tx.done;
+ ethstat->tx_req.value.ul = ss->tx.req;
+ ethstat->tx_activate.value.ul = ss->tx.activate;
+ ethstat->xmit_sched.value.ul = ss->tx.sched;
+ ethstat->xmit_stall.value.ul = ss->tx.stall;
+ ethstat->xmit_stall_early.value.ul = ss->tx.stall_early;
+ ethstat->xmit_stall_late.value.ul = ss->tx.stall_late;
+ ethstat->xmit_err.value.ul = MYRI10GE_SLICE_STAT(xmit_err);
+ return (0);
+}
+
+static int
+myri10ge_info_kstat_update(kstat_t *ksp, int rw)
+{
+ struct myri10ge_info *info;
+ struct myri10ge_priv *mgp;
+
+
+ if (rw == KSTAT_WRITE)
+ return (EACCES);
+
+ info = (struct myri10ge_info *)ksp->ks_data;
+ mgp = (struct myri10ge_priv *)ksp->ks_private;
+ kstat_named_setstr(&info->driver_version, MYRI10GE_VERSION_STR);
+ kstat_named_setstr(&info->firmware_version, mgp->fw_version);
+ kstat_named_setstr(&info->firmware_name, mgp->fw_name);
+ kstat_named_setstr(&info->interrupt_type, mgp->intr_type);
+ kstat_named_setstr(&info->product_code, mgp->pc_str);
+ kstat_named_setstr(&info->serial_number, mgp->sn_str);
+ return (0);
+}
+
+static struct myri10ge_info myri10ge_info_template = {
+ { "driver_version", KSTAT_DATA_STRING },
+ { "firmware_version", KSTAT_DATA_STRING },
+ { "firmware_name", KSTAT_DATA_STRING },
+ { "interrupt_type", KSTAT_DATA_STRING },
+ { "product_code", KSTAT_DATA_STRING },
+ { "serial_number", KSTAT_DATA_STRING },
+};
+static kmutex_t myri10ge_info_template_lock;
+
+
+static int
+myri10ge_info_init(struct myri10ge_priv *mgp)
+{
+ struct kstat *ksp;
+
+ ksp = kstat_create("myri10ge", ddi_get_instance(mgp->dip),
+ "myri10ge_info", "net", KSTAT_TYPE_NAMED,
+ sizeof (myri10ge_info_template) /
+ sizeof (kstat_named_t), KSTAT_FLAG_VIRTUAL);
+ if (ksp == NULL) {
+ cmn_err(CE_WARN,
+ "%s: myri10ge_info_init: kstat_create failed", mgp->name);
+ return (DDI_FAILURE);
+ }
+ mgp->ksp_info = ksp;
+ ksp->ks_update = myri10ge_info_kstat_update;
+ ksp->ks_private = (void *) mgp;
+ ksp->ks_data = &myri10ge_info_template;
+ ksp->ks_lock = &myri10ge_info_template_lock;
+ if (MYRI10GE_VERSION_STR != NULL)
+ ksp->ks_data_size += strlen(MYRI10GE_VERSION_STR) + 1;
+ if (mgp->fw_version != NULL)
+ ksp->ks_data_size += strlen(mgp->fw_version) + 1;
+ ksp->ks_data_size += strlen(mgp->fw_name) + 1;
+ ksp->ks_data_size += strlen(mgp->intr_type) + 1;
+ if (mgp->pc_str != NULL)
+ ksp->ks_data_size += strlen(mgp->pc_str) + 1;
+ if (mgp->sn_str != NULL)
+ ksp->ks_data_size += strlen(mgp->sn_str) + 1;
+
+ kstat_install(ksp);
+ return (DDI_SUCCESS);
+}
+
+
+static int
+myri10ge_nic_stat_init(struct myri10ge_priv *mgp)
+{
+ struct kstat *ksp;
+ struct myri10ge_nic_stat *ethstat;
+
+ ksp = kstat_create("myri10ge", ddi_get_instance(mgp->dip),
+ "myri10ge_nic_stats", "net", KSTAT_TYPE_NAMED,
+ sizeof (*ethstat) / sizeof (kstat_named_t), 0);
+ if (ksp == NULL) {
+ cmn_err(CE_WARN,
+ "%s: myri10ge_stat_init: kstat_create failed", mgp->name);
+ return (DDI_FAILURE);
+ }
+ mgp->ksp_stat = ksp;
+ ethstat = (struct myri10ge_nic_stat *)(ksp->ks_data);
+
+ kstat_named_init(&ethstat->dma_read_bw_MBs,
+ "dma_read_bw_MBs", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dma_write_bw_MBs,
+ "dma_write_bw_MBs", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dma_read_write_bw_MBs,
+ "dma_read_write_bw_MBs", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dma_force_physical,
+ "dma_force_physical", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->lanes,
+ "lanes", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_bad_crc32,
+ "dropped_bad_crc32", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_bad_phy,
+ "dropped_bad_phy", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_link_error_or_filtered,
+ "dropped_link_error_or_filtered", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_link_overflow,
+ "dropped_link_overflow", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_multicast_filtered,
+ "dropped_multicast_filtered", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_no_big_buffer,
+ "dropped_no_big_buffer", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_no_small_buffer,
+ "dropped_no_small_buffer", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_overrun,
+ "dropped_overrun", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_pause,
+ "dropped_pause", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_runt,
+ "dropped_runt", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_unicast_filtered,
+ "dropped_unicast_filtered", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->dropped_runt, "dropped_runt",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->link_up, "link_up", KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->link_changes, "link_changes",
+ KSTAT_DATA_ULONG);
+ ksp->ks_update = myri10ge_nic_stat_kstat_update;
+ ksp->ks_private = (void *) mgp;
+ kstat_install(ksp);
+ return (DDI_SUCCESS);
+}
+
+static int
+myri10ge_slice_stat_init(struct myri10ge_slice_state *ss)
+{
+ struct myri10ge_priv *mgp = ss->mgp;
+ struct kstat *ksp;
+ struct myri10ge_slice_stat *ethstat;
+ int instance;
+
+ /*
+ * fake an instance so that the same slice numbers from
+ * different instances do not collide
+ */
+ instance = (ddi_get_instance(mgp->dip) * 1000) + (int)(ss - mgp->ss);
+ ksp = kstat_create("myri10ge", instance,
+ "myri10ge_slice_stats", "net", KSTAT_TYPE_NAMED,
+ sizeof (*ethstat) / sizeof (kstat_named_t), 0);
+ if (ksp == NULL) {
+ cmn_err(CE_WARN,
+ "%s: myri10ge_stat_init: kstat_create failed", mgp->name);
+ return (DDI_FAILURE);
+ }
+ ss->ksp_stat = ksp;
+ ethstat = (struct myri10ge_slice_stat *)(ksp->ks_data);
+ kstat_named_init(&ethstat->lro_bad_csum, "lro_bad_csum",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->lro_flushed, "lro_flushed",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->lro_queued, "lro_queued",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->rx_bigbuf_firmware, "rx_bigbuf_firmware",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->rx_bigbuf_pool, "rx_bigbuf_pool",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->rx_bigbuf_smalls, "rx_bigbuf_smalls",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->rx_copy, "rx_copy",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->rx_big_nobuf, "rx_big_nobuf",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->rx_small_nobuf, "rx_small_nobuf",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->xmit_zero_len, "xmit_zero_len",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->xmit_pullup, "xmit_pullup",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->xmit_pullup_first, "xmit_pullup_first",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->xmit_lowbuf, "xmit_lowbuf",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->xmit_lsobadflags, "xmit_lsobadflags",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->xmit_sched, "xmit_sched",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->xmit_stall, "xmit_stall",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->xmit_stall_early, "xmit_stall_early",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->xmit_stall_late, "xmit_stall_late",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->xmit_err, "xmit_err",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->tx_req, "tx_req",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->tx_activate, "tx_activate",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->tx_done, "tx_done",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->tx_handles_alloced, "tx_handles_alloced",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->rx_big, "rx_big",
+ KSTAT_DATA_ULONG);
+ kstat_named_init(&ethstat->rx_small, "rx_small",
+ KSTAT_DATA_ULONG);
+ ksp->ks_update = myri10ge_slice_stat_kstat_update;
+ ksp->ks_private = (void *) ss;
+ kstat_install(ksp);
+ return (DDI_SUCCESS);
+}
+
+
+
+#if #cpu(i386) || defined __i386 || defined i386 || \
+ defined __i386__ || #cpu(x86_64) || defined __x86_64__
+
+#include <vm/hat.h>
+void *device_arena_alloc(size_t size, int vm_flag);
+void device_arena_free(void *vaddr, size_t size);
+
+static void
+myri10ge_enable_nvidia_ecrc(struct myri10ge_priv *mgp)
+{
+ dev_info_t *parent_dip;
+ ddi_acc_handle_t handle;
+ unsigned long bus_number, dev_number, func_number;
+ unsigned long cfg_pa, paddr, base, pgoffset;
+ char *cvaddr, *ptr;
+ uint32_t *ptr32;
+ int retval = DDI_FAILURE;
+ int dontcare;
+ uint16_t read_vid, read_did, vendor_id, device_id;
+
+ if (!myri10ge_nvidia_ecrc_enable)
+ return;
+
+ parent_dip = ddi_get_parent(mgp->dip);
+ if (parent_dip == NULL) {
+ cmn_err(CE_WARN, "%s: I'm an orphan?", mgp->name);
+ return;
+ }
+
+ if (pci_config_setup(parent_dip, &handle) != DDI_SUCCESS) {
+ cmn_err(CE_WARN,
+ "%s: Could not access my parent's registers", mgp->name);
+ return;
+ }
+
+ vendor_id = pci_config_get16(handle, PCI_CONF_VENID);
+ device_id = pci_config_get16(handle, PCI_CONF_DEVID);
+ pci_config_teardown(&handle);
+
+ if (myri10ge_verbose) {
+ unsigned long bus_number, dev_number, func_number;
+ int reg_set, span;
+ (void) myri10ge_reg_set(parent_dip, &reg_set, &span,
+ &bus_number, &dev_number, &func_number);
+ if (myri10ge_verbose)
+ printf("%s: parent at %ld:%ld:%ld\n", mgp->name,
+ bus_number, dev_number, func_number);
+ }
+
+ if (vendor_id != 0x10de)
+ return;
+
+ if (device_id != 0x005d /* CK804 */ &&
+ (device_id < 0x374 || device_id > 0x378) /* MCP55 */) {
+ return;
+ }
+ (void) myri10ge_reg_set(parent_dip, &dontcare, &dontcare,
+ &bus_number, &dev_number, &func_number);
+
+ for (cfg_pa = 0xf0000000UL;
+ retval != DDI_SUCCESS && cfg_pa >= 0xe0000000UL;
+ cfg_pa -= 0x10000000UL) {
+ /* find the config space address for the nvidia bridge */
+ paddr = (cfg_pa + bus_number * 0x00100000UL +
+ (dev_number * 8 + func_number) * 0x00001000UL);
+
+ base = paddr & (~MMU_PAGEOFFSET);
+ pgoffset = paddr & MMU_PAGEOFFSET;
+
+ /* map it into the kernel */
+ cvaddr = device_arena_alloc(ptob(1), VM_NOSLEEP);
+ if (cvaddr == NULL)
+ cmn_err(CE_WARN, "%s: failed to map nf4: cvaddr\n",
+ mgp->name);
+
+ hat_devload(kas.a_hat, cvaddr, mmu_ptob(1), mmu_btop(base),
+ PROT_WRITE|HAT_STRICTORDER, HAT_LOAD_LOCK);
+
+ ptr = cvaddr + pgoffset;
+ read_vid = *(uint16_t *)(void *)(ptr + PCI_CONF_VENID);
+ read_did = *(uint16_t *)(void *)(ptr + PCI_CONF_DEVID);
+ if (vendor_id == read_did || device_id == read_did) {
+ ptr32 = (uint32_t *)(void *)(ptr + 0x178);
+ if (myri10ge_verbose)
+ printf("%s: Enabling ECRC on upstream "
+ "Nvidia bridge (0x%x:0x%x) "
+ "at %ld:%ld:%ld\n", mgp->name,
+ read_vid, read_did, bus_number,
+ dev_number, func_number);
+ *ptr32 |= 0x40;
+ retval = DDI_SUCCESS;
+ }
+ hat_unload(kas.a_hat, cvaddr, ptob(1), HAT_UNLOAD_UNLOCK);
+ device_arena_free(cvaddr, ptob(1));
+ }
+}
+
+#else
+/*ARGSUSED*/
+static void
+myri10ge_enable_nvidia_ecrc(struct myri10ge_priv *mgp)
+{
+}
+#endif /* i386 */
+
+
+/*
+ * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
+ * when the PCI-E Completion packets are aligned on an 8-byte
+ * boundary. Some PCI-E chip sets always align Completion packets; on
+ * the ones that do not, the alignment can be enforced by enabling
+ * ECRC generation (if supported).
+ *
+ * When PCI-E Completion packets are not aligned, it is actually more
+ * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
+ *
+ * If the driver can neither enable ECRC nor verify that it has
+ * already been enabled, then it must use a firmware image which works
+ * around unaligned completion packets (ethp_z8e.dat), and it should
+ * also ensure that it never gives the device a Read-DMA which is
+ * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
+ * enabled, then the driver should use the aligned (eth_z8e.dat)
+ * firmware image, and set tx.boundary to 4KB.
+ */
+
+
+static int
+myri10ge_firmware_probe(struct myri10ge_priv *mgp)
+{
+ int status;
+
+ mgp->tx_boundary = 4096;
+ /*
+ * Verify the max read request size was set to 4KB
+ * before trying the test with 4KB.
+ */
+ if (mgp->max_read_request_4k == 0)
+ mgp->tx_boundary = 2048;
+ /*
+ * load the optimized firmware which assumes aligned PCIe
+ * completions in order to see if it works on this host.
+ */
+
+ mgp->fw_name = "rss_eth_z8e";
+ mgp->eth_z8e = (unsigned char *)rss_eth_z8e;
+ mgp->eth_z8e_length = rss_eth_z8e_length;
+
+ status = myri10ge_load_firmware(mgp);
+ if (status != 0) {
+ return (status);
+ }
+ /*
+ * Enable ECRC if possible
+ */
+ myri10ge_enable_nvidia_ecrc(mgp);
+
+ /*
+ * Run a DMA test which watches for unaligned completions and
+ * aborts on the first one seen.
+ */
+ status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
+ if (status == 0)
+ return (0); /* keep the aligned firmware */
+
+ if (status != E2BIG)
+ cmn_err(CE_WARN, "%s: DMA test failed: %d\n",
+ mgp->name, status);
+ if (status == ENOSYS)
+ cmn_err(CE_WARN, "%s: Falling back to ethp! "
+ "Please install up to date fw\n", mgp->name);
+ return (status);
+}
+
+static int
+myri10ge_select_firmware(struct myri10ge_priv *mgp)
+{
+ int aligned;
+
+ aligned = 0;
+
+ if (myri10ge_force_firmware == 1) {
+ if (myri10ge_verbose)
+ printf("%s: Assuming aligned completions (forced)\n",
+ mgp->name);
+ aligned = 1;
+ goto done;
+ }
+
+ if (myri10ge_force_firmware == 2) {
+ if (myri10ge_verbose)
+ printf("%s: Assuming unaligned completions (forced)\n",
+ mgp->name);
+ aligned = 0;
+ goto done;
+ }
+
+ /* If the width is less than 8, we may used the aligned firmware */
+ if (mgp->pcie_link_width != 0 && mgp->pcie_link_width < 8) {
+ cmn_err(CE_WARN, "!%s: PCIe link running at x%d\n",
+ mgp->name, mgp->pcie_link_width);
+ aligned = 1;
+ goto done;
+ }
+
+ if (0 == myri10ge_firmware_probe(mgp))
+ return (0); /* keep optimized firmware */
+
+done:
+ if (aligned) {
+ mgp->fw_name = "rss_eth_z8e";
+ mgp->eth_z8e = (unsigned char *)rss_eth_z8e;
+ mgp->eth_z8e_length = rss_eth_z8e_length;
+ mgp->tx_boundary = 4096;
+ } else {
+ mgp->fw_name = "rss_ethp_z8e";
+ mgp->eth_z8e = (unsigned char *)rss_ethp_z8e;
+ mgp->eth_z8e_length = rss_ethp_z8e_length;
+ mgp->tx_boundary = 2048;
+ }
+
+ return (myri10ge_load_firmware(mgp));
+}
+
+static int
+myri10ge_add_intrs(struct myri10ge_priv *mgp, int add_handler)
+{
+ dev_info_t *devinfo = mgp->dip;
+ int count, avail, actual, intr_types;
+ int x, y, rc, inum = 0;
+
+
+ rc = ddi_intr_get_supported_types(devinfo, &intr_types);
+ if (rc != DDI_SUCCESS) {
+ cmn_err(CE_WARN,
+ "!%s: ddi_intr_get_nintrs() failure, rc = %d\n", mgp->name,
+ rc);
+ return (DDI_FAILURE);
+ }
+
+ if (!myri10ge_use_msi)
+ intr_types &= ~DDI_INTR_TYPE_MSI;
+ if (!myri10ge_use_msix)
+ intr_types &= ~DDI_INTR_TYPE_MSIX;
+
+ if (intr_types & DDI_INTR_TYPE_MSIX) {
+ mgp->ddi_intr_type = DDI_INTR_TYPE_MSIX;
+ mgp->intr_type = "MSI-X";
+ } else if (intr_types & DDI_INTR_TYPE_MSI) {
+ mgp->ddi_intr_type = DDI_INTR_TYPE_MSI;
+ mgp->intr_type = "MSI";
+ } else {
+ mgp->ddi_intr_type = DDI_INTR_TYPE_FIXED;
+ mgp->intr_type = "Legacy";
+ }
+ /* Get number of interrupts */
+ rc = ddi_intr_get_nintrs(devinfo, mgp->ddi_intr_type, &count);
+ if ((rc != DDI_SUCCESS) || (count == 0)) {
+ cmn_err(CE_WARN, "%s: ddi_intr_get_nintrs() failure, rc: %d, "
+ "count: %d", mgp->name, rc, count);
+
+ return (DDI_FAILURE);
+ }
+
+ /* Get number of available interrupts */
+ rc = ddi_intr_get_navail(devinfo, mgp->ddi_intr_type, &avail);
+ if ((rc != DDI_SUCCESS) || (avail == 0)) {
+ cmn_err(CE_WARN, "%s: ddi_intr_get_navail() failure, "
+ "rc: %d, avail: %d\n", mgp->name, rc, avail);
+ return (DDI_FAILURE);
+ }
+ if (avail < count) {
+ cmn_err(CE_NOTE,
+ "!%s: nintrs() returned %d, navail returned %d",
+ mgp->name, count, avail);
+ count = avail;
+ }
+
+ if (count < mgp->num_slices)
+ return (DDI_FAILURE);
+
+ if (count > mgp->num_slices)
+ count = mgp->num_slices;
+
+ /* Allocate memory for MSI interrupts */
+ mgp->intr_size = count * sizeof (ddi_intr_handle_t);
+ mgp->htable = kmem_alloc(mgp->intr_size, KM_SLEEP);
+
+ rc = ddi_intr_alloc(devinfo, mgp->htable, mgp->ddi_intr_type, inum,
+ count, &actual, DDI_INTR_ALLOC_NORMAL);
+
+ if ((rc != DDI_SUCCESS) || (actual == 0)) {
+ cmn_err(CE_WARN, "%s: ddi_intr_alloc() failed: %d",
+ mgp->name, rc);
+
+ kmem_free(mgp->htable, mgp->intr_size);
+ mgp->htable = NULL;
+ return (DDI_FAILURE);
+ }
+
+ if ((actual < count) && myri10ge_verbose) {
+ cmn_err(CE_NOTE, "%s: got %d/%d slices",
+ mgp->name, actual, count);
+ }
+
+ mgp->intr_cnt = actual;
+
+ /*
+ * Get priority for first irq, assume remaining are all the same
+ */
+ if (ddi_intr_get_pri(mgp->htable[0], &mgp->intr_pri)
+ != DDI_SUCCESS) {
+ cmn_err(CE_WARN, "%s: ddi_intr_get_pri() failed", mgp->name);
+
+ /* Free already allocated intr */
+ for (y = 0; y < actual; y++) {
+ (void) ddi_intr_free(mgp->htable[y]);
+ }
+
+ kmem_free(mgp->htable, mgp->intr_size);
+ mgp->htable = NULL;
+ return (DDI_FAILURE);
+ }
+
+ mgp->icookie = (void *)(uintptr_t)mgp->intr_pri;
+
+ if (!add_handler)
+ return (DDI_SUCCESS);
+
+ /* Call ddi_intr_add_handler() */
+ for (x = 0; x < actual; x++) {
+ if (ddi_intr_add_handler(mgp->htable[x], myri10ge_intr,
+ (caddr_t)&mgp->ss[x], NULL) != DDI_SUCCESS) {
+ cmn_err(CE_WARN, "%s: ddi_intr_add_handler() failed",
+ mgp->name);
+
+ /* Free already allocated intr */
+ for (y = 0; y < actual; y++) {
+ (void) ddi_intr_free(mgp->htable[y]);
+ }
+
+ kmem_free(mgp->htable, mgp->intr_size);
+ mgp->htable = NULL;
+ return (DDI_FAILURE);
+ }
+ }
+
+ (void) ddi_intr_get_cap(mgp->htable[0], &mgp->intr_cap);
+ if (mgp->intr_cap & DDI_INTR_FLAG_BLOCK) {
+ /* Call ddi_intr_block_enable() for MSI */
+ (void) ddi_intr_block_enable(mgp->htable, mgp->intr_cnt);
+ } else {
+ /* Call ddi_intr_enable() for MSI non block enable */
+ for (x = 0; x < mgp->intr_cnt; x++) {
+ (void) ddi_intr_enable(mgp->htable[x]);
+ }
+ }
+
+ return (DDI_SUCCESS);
+}
+
+static void
+myri10ge_rem_intrs(struct myri10ge_priv *mgp, int handler_installed)
+{
+ int x, err;
+
+ /* Disable all interrupts */
+ if (handler_installed) {
+ if (mgp->intr_cap & DDI_INTR_FLAG_BLOCK) {
+ /* Call ddi_intr_block_disable() */
+ (void) ddi_intr_block_disable(mgp->htable,
+ mgp->intr_cnt);
+ } else {
+ for (x = 0; x < mgp->intr_cnt; x++) {
+ (void) ddi_intr_disable(mgp->htable[x]);
+ }
+ }
+ }
+
+ for (x = 0; x < mgp->intr_cnt; x++) {
+ if (handler_installed) {
+ /* Call ddi_intr_remove_handler() */
+ err = ddi_intr_remove_handler(mgp->htable[x]);
+ if (err != DDI_SUCCESS) {
+ cmn_err(CE_WARN,
+ "%s: ddi_intr_remove_handler for"
+ "vec %d returned %d\n", mgp->name,
+ x, err);
+ }
+ }
+ err = ddi_intr_free(mgp->htable[x]);
+ if (err != DDI_SUCCESS) {
+ cmn_err(CE_WARN,
+ "%s: ddi_intr_free for vec %d returned %d\n",
+ mgp->name, x, err);
+ }
+ }
+ kmem_free(mgp->htable, mgp->intr_size);
+ mgp->htable = NULL;
+}
+
+static void
+myri10ge_test_physical(dev_info_t *dip)
+{
+ ddi_dma_handle_t handle;
+ struct myri10ge_dma_stuff dma;
+ void *addr;
+ int err;
+
+ /* test #1, sufficient for older sparc systems */
+ myri10ge_tx_dma_attr.dma_attr_flags = DDI_DMA_FORCE_PHYSICAL;
+ err = ddi_dma_alloc_handle(dip, &myri10ge_tx_dma_attr,
+ DDI_DMA_DONTWAIT, NULL, &handle);
+ if (err == DDI_DMA_BADATTR)
+ goto fail;
+ ddi_dma_free_handle(&handle);
+
+ /* test #2, required on Olympis where the bind is what fails */
+ addr = myri10ge_dma_alloc(dip, 128, &myri10ge_tx_dma_attr,
+ &myri10ge_dev_access_attr, DDI_DMA_STREAMING,
+ DDI_DMA_WRITE|DDI_DMA_STREAMING, &dma, 0, DDI_DMA_DONTWAIT);
+ if (addr == NULL)
+ goto fail;
+ myri10ge_dma_free(&dma);
+ return;
+
+fail:
+ if (myri10ge_verbose)
+ printf("myri10ge%d: DDI_DMA_FORCE_PHYSICAL failed, "
+ "using IOMMU\n", ddi_get_instance(dip));
+
+ myri10ge_tx_dma_attr.dma_attr_flags &= ~DDI_DMA_FORCE_PHYSICAL;
+}
+
+static void
+myri10ge_get_props(dev_info_t *dip)
+{
+
+ myri10ge_flow_control = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_flow_control", myri10ge_flow_control);
+
+ myri10ge_intr_coal_delay = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_intr_coal_delay", myri10ge_intr_coal_delay);
+
+#if #cpu(i386) || defined __i386 || defined i386 || \
+ defined __i386__ || #cpu(x86_64) || defined __x86_64__
+ myri10ge_nvidia_ecrc_enable = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_nvidia_ecrc_enable", 1);
+#endif
+
+
+ myri10ge_use_msi = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_use_msi", myri10ge_use_msi);
+
+ myri10ge_deassert_wait = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_deassert_wait", myri10ge_deassert_wait);
+
+ myri10ge_verbose = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_verbose", myri10ge_verbose);
+
+ myri10ge_tx_copylen = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_tx_copylen", myri10ge_tx_copylen);
+
+ if (myri10ge_tx_copylen < 60) {
+ cmn_err(CE_WARN,
+ "myri10ge_tx_copylen must be >= 60 bytes\n");
+ myri10ge_tx_copylen = 60;
+ }
+
+ myri10ge_mtu_override = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_mtu_override", myri10ge_mtu_override);
+
+ if (myri10ge_mtu_override >= 1500 && myri10ge_mtu_override <= 9000)
+ myri10ge_mtu = myri10ge_mtu_override +
+ sizeof (struct ether_header) + MXGEFW_PAD + VLAN_TAGSZ;
+ else if (myri10ge_mtu_override != 0) {
+ cmn_err(CE_WARN,
+ "myri10ge_mtu_override must be between 1500 and "
+ "9000 bytes\n");
+ }
+
+ myri10ge_bigbufs_initial = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_bigbufs_initial", myri10ge_bigbufs_initial);
+ myri10ge_bigbufs_max = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_bigbufs_max", myri10ge_bigbufs_max);
+
+ myri10ge_watchdog_reset = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_watchdog_reset", myri10ge_watchdog_reset);
+
+ if (myri10ge_bigbufs_initial < 128) {
+ cmn_err(CE_WARN,
+ "myri10ge_bigbufs_initial be at least 128\n");
+ myri10ge_bigbufs_initial = 128;
+ }
+ if (myri10ge_bigbufs_max < 128) {
+ cmn_err(CE_WARN,
+ "myri10ge_bigbufs_max be at least 128\n");
+ myri10ge_bigbufs_max = 128;
+ }
+
+ if (myri10ge_bigbufs_max < myri10ge_bigbufs_initial) {
+ cmn_err(CE_WARN,
+ "myri10ge_bigbufs_max must be >= "
+ "myri10ge_bigbufs_initial\n");
+ myri10ge_bigbufs_max = myri10ge_bigbufs_initial;
+ }
+
+ myri10ge_force_firmware = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_force_firmware", myri10ge_force_firmware);
+
+ myri10ge_max_slices = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_max_slices", myri10ge_max_slices);
+
+ myri10ge_use_msix = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_use_msix", myri10ge_use_msix);
+
+ myri10ge_rss_hash = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_rss_hash", myri10ge_rss_hash);
+
+ if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX ||
+ myri10ge_rss_hash < MXGEFW_RSS_HASH_TYPE_IPV4) {
+ cmn_err(CE_WARN, "myri10ge: Illegal rssh hash type %d\n",
+ myri10ge_rss_hash);
+ myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
+ }
+ myri10ge_lro = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_lro", myri10ge_lro);
+ myri10ge_lro_cnt = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_lro_cnt", myri10ge_lro_cnt);
+ myri10ge_lro_max_aggr = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_lro_max_aggr", myri10ge_lro_max_aggr);
+ myri10ge_tx_hash = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_tx_hash", myri10ge_tx_hash);
+ myri10ge_use_lso = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_use_lso", myri10ge_use_lso);
+ myri10ge_lso_copy = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_lso_copy", myri10ge_lso_copy);
+ myri10ge_tx_handles_initial = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_tx_handles_initial", myri10ge_tx_handles_initial);
+ myri10ge_small_bytes = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
+ "myri10ge_small_bytes", myri10ge_small_bytes);
+ if ((myri10ge_small_bytes + MXGEFW_PAD) & (128 -1)) {
+ cmn_err(CE_WARN, "myri10ge: myri10ge_small_bytes (%d)\n",
+ myri10ge_small_bytes);
+ cmn_err(CE_WARN, "must be aligned on 128b bndry -2\n");
+ myri10ge_small_bytes += 128;
+ myri10ge_small_bytes &= ~(128 -1);
+ myri10ge_small_bytes -= MXGEFW_PAD;
+ cmn_err(CE_WARN, "rounded up to %d\n",
+ myri10ge_small_bytes);
+
+ myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
+ }
+}
+
+#ifndef PCI_EXP_LNKSTA
+#define PCI_EXP_LNKSTA 18
+#endif
+
+static int
+myri10ge_find_cap(ddi_acc_handle_t handle, uint8_t *capptr, uint8_t capid)
+{
+ uint16_t status;
+ uint8_t ptr;
+
+ /* check to see if we have capabilities */
+ status = pci_config_get16(handle, PCI_CONF_STAT);
+ if (!(status & PCI_STAT_CAP)) {
+ cmn_err(CE_WARN, "PCI_STAT_CAP not found\n");
+ return (ENXIO);
+ }
+
+ ptr = pci_config_get8(handle, PCI_CONF_CAP_PTR);
+
+ /* Walk the capabilities list, looking for a PCI Express cap */
+ while (ptr != PCI_CAP_NEXT_PTR_NULL) {
+ if (pci_config_get8(handle, ptr + PCI_CAP_ID) == capid)
+ break;
+ ptr = pci_config_get8(handle, ptr + PCI_CAP_NEXT_PTR);
+ }
+ if (ptr < 64) {
+ cmn_err(CE_WARN, "Bad capability offset %d\n", ptr);
+ return (ENXIO);
+ }
+ *capptr = ptr;
+ return (0);
+}
+
+static int
+myri10ge_set_max_readreq(ddi_acc_handle_t handle)
+{
+ int err;
+ uint16_t val;
+ uint8_t ptr;
+
+ err = myri10ge_find_cap(handle, &ptr, PCI_CAP_ID_PCI_E);
+ if (err != 0) {
+ cmn_err(CE_WARN, "could not find PCIe cap\n");
+ return (ENXIO);
+ }
+
+ /* set max read req to 4096 */
+ val = pci_config_get16(handle, ptr + PCIE_DEVCTL);
+ val = (val & ~PCIE_DEVCTL_MAX_READ_REQ_MASK) |
+ PCIE_DEVCTL_MAX_READ_REQ_4096;
+ pci_config_put16(handle, ptr + PCIE_DEVCTL, val);
+ val = pci_config_get16(handle, ptr + PCIE_DEVCTL);
+ if ((val & (PCIE_DEVCTL_MAX_READ_REQ_4096)) !=
+ PCIE_DEVCTL_MAX_READ_REQ_4096) {
+ cmn_err(CE_WARN, "could not set max read req (%x)\n", val);
+ return (EINVAL);
+ }
+ return (0);
+}
+
+static int
+myri10ge_read_pcie_link_width(ddi_acc_handle_t handle, int *link)
+{
+ int err;
+ uint16_t val;
+ uint8_t ptr;
+
+ err = myri10ge_find_cap(handle, &ptr, PCI_CAP_ID_PCI_E);
+ if (err != 0) {
+ cmn_err(CE_WARN, "could not set max read req\n");
+ return (ENXIO);
+ }
+
+ /* read link width */
+ val = pci_config_get16(handle, ptr + PCIE_LINKSTS);
+ val &= PCIE_LINKSTS_NEG_WIDTH_MASK;
+ *link = (val >> 4);
+ return (0);
+}
+
+static int
+myri10ge_reset_nic(struct myri10ge_priv *mgp)
+{
+ ddi_acc_handle_t handle = mgp->cfg_hdl;
+ uint32_t reboot;
+ uint16_t cmd;
+ int err;
+
+ cmd = pci_config_get16(handle, PCI_CONF_COMM);
+ if ((cmd & PCI_COMM_ME) == 0) {
+ /*
+ * Bus master DMA disabled? Check to see if the card
+ * rebooted due to a parity error For now, just report
+ * it
+ */
+
+ /* enter read32 mode */
+ pci_config_put8(handle, mgp->vso + 0x10, 0x3);
+ /* read REBOOT_STATUS (0xfffffff0) */
+ pci_config_put32(handle, mgp->vso + 0x18, 0xfffffff0);
+ reboot = pci_config_get16(handle, mgp->vso + 0x14);
+ cmn_err(CE_WARN, "%s NIC rebooted 0x%x\n", mgp->name, reboot);
+ return (0);
+ }
+ if (!myri10ge_watchdog_reset) {
+ cmn_err(CE_WARN, "%s: not resetting\n", mgp->name);
+ return (1);
+ }
+
+ myri10ge_stop_locked(mgp);
+ err = myri10ge_start_locked(mgp);
+ if (err == DDI_FAILURE) {
+ return (0);
+ }
+ mac_tx_update(mgp->mh);
+ return (1);
+}
+
+static inline int
+myri10ge_ring_stalled(myri10ge_tx_ring_t *tx)
+{
+ if (tx->sched != tx->stall &&
+ tx->done == tx->watchdog_done &&
+ tx->watchdog_req != tx->watchdog_done)
+ return (1);
+ return (0);
+}
+
+static void
+myri10ge_watchdog(void *arg)
+{
+ struct myri10ge_priv *mgp;
+ struct myri10ge_slice_state *ss;
+ myri10ge_tx_ring_t *tx;
+ int nic_ok = 1;
+ int slices_stalled, rx_pause, i;
+ int add_rx;
+
+ mgp = arg;
+ mutex_enter(&mgp->intrlock);
+ if (mgp->running != MYRI10GE_ETH_RUNNING) {
+ cmn_err(CE_WARN,
+ "%s not running, not rearming watchdog (%d)\n",
+ mgp->name, mgp->running);
+ mutex_exit(&mgp->intrlock);
+ return;
+ }
+
+ rx_pause = ntohl(mgp->ss[0].fw_stats->dropped_pause);
+
+ /*
+ * make sure nic is stalled before we reset the nic, so as to
+ * ensure we don't rip the transmit data structures out from
+ * under a pending transmit
+ */
+
+ for (slices_stalled = 0, i = 0; i < mgp->num_slices; i++) {
+ tx = &mgp->ss[i].tx;
+ slices_stalled = myri10ge_ring_stalled(tx);
+ if (slices_stalled)
+ break;
+ }
+
+ if (slices_stalled) {
+ if (mgp->watchdog_rx_pause == rx_pause) {
+ cmn_err(CE_WARN,
+ "%s slice %d stalled:(%d, %d, %d, %d, %d %d %d\n)",
+ mgp->name, i, tx->sched, tx->stall,
+ tx->done, tx->watchdog_done, tx->req, tx->pkt_done,
+ (int)ntohl(mgp->ss[i].fw_stats->send_done_count));
+ nic_ok = myri10ge_reset_nic(mgp);
+ } else {
+ cmn_err(CE_WARN,
+ "%s Flow controlled, check link partner\n",
+ mgp->name);
+ }
+ }
+
+ if (!nic_ok) {
+ cmn_err(CE_WARN,
+ "%s Nic dead, not rearming watchdog\n", mgp->name);
+ mutex_exit(&mgp->intrlock);
+ return;
+ }
+ for (i = 0; i < mgp->num_slices; i++) {
+ ss = &mgp->ss[i];
+ tx = &ss->tx;
+ tx->watchdog_done = tx->done;
+ tx->watchdog_req = tx->req;
+ if (ss->watchdog_rx_copy != MYRI10GE_SLICE_STAT(rx_copy)) {
+ ss->watchdog_rx_copy = MYRI10GE_SLICE_STAT(rx_copy);
+ add_rx =
+ min(ss->jpool.num_alloc,
+ myri10ge_bigbufs_max -
+ (ss->jpool.num_alloc -
+ ss->jbufs_for_smalls));
+ if (add_rx != 0) {
+ (void) myri10ge_add_jbufs(ss, add_rx, 0);
+ /* now feed them to the firmware */
+ mutex_enter(&ss->jpool.mtx);
+ myri10ge_restock_jumbos(ss);
+ mutex_exit(&ss->jpool.mtx);
+ }
+ }
+ }
+ mgp->watchdog_rx_pause = rx_pause;
+
+ mgp->timer_id = timeout(myri10ge_watchdog, mgp,
+ mgp->timer_ticks);
+ mutex_exit(&mgp->intrlock);
+}
+
+/*ARGSUSED*/
+static int
+myri10ge_get_coalesce(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
+
+{
+ struct myri10ge_priv *mgp = (struct myri10ge_priv *)(void *)cp;
+ (void) mi_mpprintf(mp, "%d", mgp->intr_coal_delay);
+ return (0);
+}
+
+/*ARGSUSED*/
+static int
+myri10ge_set_coalesce(queue_t *q, mblk_t *mp, char *value,
+ caddr_t cp, cred_t *credp)
+
+{
+ struct myri10ge_priv *mgp = (struct myri10ge_priv *)(void *)cp;
+ char *end;
+ size_t new_value;
+
+ new_value = mi_strtol(value, &end, 10);
+ if (end == value)
+ return (EINVAL);
+
+ mutex_enter(&myri10ge_param_lock);
+ mgp->intr_coal_delay = (int)new_value;
+ *mgp->intr_coal_delay_ptr = htonl(mgp->intr_coal_delay);
+ mutex_exit(&myri10ge_param_lock);
+ return (0);
+}
+
+/*ARGSUSED*/
+static int
+myri10ge_get_pauseparam(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
+
+{
+ struct myri10ge_priv *mgp = (struct myri10ge_priv *)(void *)cp;
+ (void) mi_mpprintf(mp, "%d", mgp->pause);
+ return (0);
+}
+
+/*ARGSUSED*/
+static int
+myri10ge_set_pauseparam(queue_t *q, mblk_t *mp, char *value,
+ caddr_t cp, cred_t *credp)
+
+{
+ struct myri10ge_priv *mgp = (struct myri10ge_priv *)(void *)cp;
+ char *end;
+ size_t new_value;
+ int err = 0;
+
+ new_value = mi_strtol(value, &end, 10);
+ if (end == value)
+ return (EINVAL);
+ if (new_value != 0)
+ new_value = 1;
+
+ mutex_enter(&myri10ge_param_lock);
+ if (new_value != mgp->pause)
+ err = myri10ge_change_pause(mgp, new_value);
+ mutex_exit(&myri10ge_param_lock);
+ return (err);
+}
+
+/*ARGSUSED*/
+static int
+myri10ge_get_int(queue_t *q, mblk_t *mp, caddr_t cp, cred_t *credp)
+
+{
+ (void) mi_mpprintf(mp, "%d", *(int *)(void *)cp);
+ return (0);
+}
+
+/*ARGSUSED*/
+static int
+myri10ge_set_int(queue_t *q, mblk_t *mp, char *value,
+ caddr_t cp, cred_t *credp)
+
+{
+ char *end;
+ size_t new_value;
+
+ new_value = mi_strtol(value, &end, 10);
+ if (end == value)
+ return (EINVAL);
+ *(int *)(void *)cp = new_value;
+
+ return (0);
+}
+
+static void
+myri10ge_ndd_init(struct myri10ge_priv *mgp)
+{
+ mgp->nd_head = NULL;
+
+ (void) nd_load(&mgp->nd_head, "myri10ge_intr_coal_delay",
+ myri10ge_get_coalesce, myri10ge_set_coalesce, (caddr_t)mgp);
+ (void) nd_load(&mgp->nd_head, "myri10ge_flow_control",
+ myri10ge_get_pauseparam, myri10ge_set_pauseparam, (caddr_t)mgp);
+ (void) nd_load(&mgp->nd_head, "myri10ge_verbose",
+ myri10ge_get_int, myri10ge_set_int, (caddr_t)&myri10ge_verbose);
+ (void) nd_load(&mgp->nd_head, "myri10ge_deassert_wait",
+ myri10ge_get_int, myri10ge_set_int,
+ (caddr_t)&myri10ge_deassert_wait);
+ (void) nd_load(&mgp->nd_head, "myri10ge_bigbufs_max",
+ myri10ge_get_int, myri10ge_set_int,
+ (caddr_t)&myri10ge_bigbufs_max);
+ (void) nd_load(&mgp->nd_head, "myri10ge_lro",
+ myri10ge_get_int, myri10ge_set_int,
+ (caddr_t)&myri10ge_lro);
+ (void) nd_load(&mgp->nd_head, "myri10ge_lro_max_aggr",
+ myri10ge_get_int, myri10ge_set_int,
+ (caddr_t)&myri10ge_lro_max_aggr);
+ (void) nd_load(&mgp->nd_head, "myri10ge_tx_hash",
+ myri10ge_get_int, myri10ge_set_int,
+ (caddr_t)&myri10ge_tx_hash);
+ (void) nd_load(&mgp->nd_head, "myri10ge_lso_copy",
+ myri10ge_get_int, myri10ge_set_int,
+ (caddr_t)&myri10ge_lso_copy);
+}
+
+static void
+myri10ge_ndd_fini(struct myri10ge_priv *mgp)
+{
+ nd_free(&mgp->nd_head);
+}
+
+static void
+myri10ge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp)
+{
+ struct iocblk *iocp;
+ struct myri10ge_priv *mgp = arg;
+ int cmd, ok, err;
+
+ iocp = (struct iocblk *)(void *)mp->b_rptr;
+ cmd = iocp->ioc_cmd;
+
+ ok = 0;
+ err = 0;
+
+ switch (cmd) {
+ case ND_GET:
+ case ND_SET:
+ ok = nd_getset(wq, mgp->nd_head, mp);
+ break;
+ default:
+ break;
+ }
+ if (!ok)
+ err = EINVAL;
+ else
+ err = iocp->ioc_error;
+
+ if (!err)
+ miocack(wq, mp, iocp->ioc_count, err);
+ else
+ miocnak(wq, mp, 0, err);
+}
+
+static struct myri10ge_priv *mgp_list;
+
+struct myri10ge_priv *
+myri10ge_get_instance(uint_t unit)
+{
+ struct myri10ge_priv *mgp;
+
+ mutex_enter(&myri10ge_param_lock);
+ for (mgp = mgp_list; mgp != NULL; mgp = mgp->next) {
+ if (unit == ddi_get_instance(mgp->dip)) {
+ mgp->refcnt++;
+ break;
+ }
+ }
+ mutex_exit(&myri10ge_param_lock);
+ return (mgp);
+}
+
+void
+myri10ge_put_instance(struct myri10ge_priv *mgp)
+{
+ mutex_enter(&myri10ge_param_lock);
+ mgp->refcnt--;
+ mutex_exit(&myri10ge_param_lock);
+}
+
+static boolean_t
+myri10ge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data)
+{
+ struct myri10ge_priv *mgp = arg;
+ uint32_t *cap_hcksum;
+ mac_capab_lso_t *cap_lso;
+ mac_capab_rings_t *cap_rings;
+
+ switch (cap) {
+ case MAC_CAPAB_HCKSUM:
+ cap_hcksum = cap_data;
+ *cap_hcksum = HCKSUM_INET_PARTIAL;
+ break;
+ case MAC_CAPAB_RINGS:
+ cap_rings = cap_data;
+ switch (cap_rings->mr_type) {
+ case MAC_RING_TYPE_RX:
+ cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
+ cap_rings->mr_rnum = mgp->num_slices;
+ cap_rings->mr_gnum = 1;
+ cap_rings->mr_rget = myri10ge_fill_ring;
+ cap_rings->mr_gget = myri10ge_fill_group;
+ break;
+ case MAC_RING_TYPE_TX:
+ cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC;
+ cap_rings->mr_rnum = mgp->num_slices;
+ cap_rings->mr_gnum = 0;
+ cap_rings->mr_rget = myri10ge_fill_ring;
+ cap_rings->mr_gget = NULL;
+ break;
+ default:
+ return (B_FALSE);
+ }
+ break;
+ case MAC_CAPAB_LSO:
+ cap_lso = cap_data;
+ if (!myri10ge_use_lso)
+ return (B_FALSE);
+ if (!(mgp->features & MYRI10GE_TSO))
+ return (B_FALSE);
+ cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4;
+ cap_lso->lso_basic_tcp_ipv4.lso_max = (uint16_t)-1;
+ break;
+
+ default:
+ return (B_FALSE);
+ }
+ return (B_TRUE);
+}
+
+
+static int
+myri10ge_m_stat(void *arg, uint_t stat, uint64_t *val)
+{
+ struct myri10ge_priv *mgp = arg;
+ struct myri10ge_rx_ring_stats *rstat;
+ struct myri10ge_tx_ring_stats *tstat;
+ mcp_irq_data_t *fw_stats = mgp->ss[0].fw_stats;
+ struct myri10ge_slice_state *ss;
+ uint64_t tmp = 0;
+ int i;
+
+ switch (stat) {
+ case MAC_STAT_IFSPEED:
+ *val = 10ull * 1000ull * 1000000ull;
+ break;
+
+ case MAC_STAT_MULTIRCV:
+ for (i = 0; i < mgp->num_slices; i++) {
+ rstat = &mgp->ss[i].rx_stats;
+ tmp += rstat->multircv;
+ }
+ *val = tmp;
+ break;
+
+ case MAC_STAT_BRDCSTRCV:
+ for (i = 0; i < mgp->num_slices; i++) {
+ rstat = &mgp->ss[i].rx_stats;
+ tmp += rstat->brdcstrcv;
+ }
+ *val = tmp;
+ break;
+
+ case MAC_STAT_MULTIXMT:
+ for (i = 0; i < mgp->num_slices; i++) {
+ tstat = &mgp->ss[i].tx.stats;
+ tmp += tstat->multixmt;
+ }
+ *val = tmp;
+ break;
+
+ case MAC_STAT_BRDCSTXMT:
+ for (i = 0; i < mgp->num_slices; i++) {
+ tstat = &mgp->ss[i].tx.stats;
+ tmp += tstat->brdcstxmt;
+ }
+ *val = tmp;
+ break;
+
+ case MAC_STAT_NORCVBUF:
+ tmp = ntohl(fw_stats->dropped_no_big_buffer);
+ tmp += ntohl(fw_stats->dropped_no_small_buffer);
+ tmp += ntohl(fw_stats->dropped_link_overflow);
+ for (i = 0; i < mgp->num_slices; i++) {
+ ss = &mgp->ss[i];
+ tmp += MYRI10GE_SLICE_STAT(rx_big_nobuf);
+ tmp += MYRI10GE_SLICE_STAT(rx_small_nobuf);
+ }
+ *val = tmp;
+ break;
+
+ case MAC_STAT_IERRORS:
+ tmp += ntohl(fw_stats->dropped_bad_crc32);
+ tmp += ntohl(fw_stats->dropped_bad_phy);
+ tmp += ntohl(fw_stats->dropped_runt);
+ tmp += ntohl(fw_stats->dropped_overrun);
+ *val = tmp;
+ break;
+
+ case MAC_STAT_OERRORS:
+ for (i = 0; i < mgp->num_slices; i++) {
+ ss = &mgp->ss[i];
+ tmp += MYRI10GE_SLICE_STAT(xmit_lsobadflags);
+ tmp += MYRI10GE_SLICE_STAT(xmit_err);
+ }
+ *val = tmp;
+ break;
+
+ case MAC_STAT_RBYTES:
+ for (i = 0; i < mgp->num_slices; i++) {
+ rstat = &mgp->ss[i].rx_stats;
+ tmp += rstat->ibytes;
+ }
+ *val = tmp;
+ break;
+
+ case MAC_STAT_IPACKETS:
+ for (i = 0; i < mgp->num_slices; i++) {
+ rstat = &mgp->ss[i].rx_stats;
+ tmp += rstat->ipackets;
+ }
+ *val = tmp;
+ break;
+
+ case MAC_STAT_OBYTES:
+ for (i = 0; i < mgp->num_slices; i++) {
+ tstat = &mgp->ss[i].tx.stats;
+ tmp += tstat->obytes;
+ }
+ *val = tmp;
+ break;
+
+ case MAC_STAT_OPACKETS:
+ for (i = 0; i < mgp->num_slices; i++) {
+ tstat = &mgp->ss[i].tx.stats;
+ tmp += tstat->opackets;
+ }
+ *val = tmp;
+ break;
+
+ case ETHER_STAT_TOOLONG_ERRORS:
+ *val = ntohl(fw_stats->dropped_overrun);
+ break;
+
+#ifdef SOLARIS_S11
+ case ETHER_STAT_TOOSHORT_ERRORS:
+ *val = ntohl(fw_stats->dropped_runt);
+ break;
+#endif
+
+ case ETHER_STAT_LINK_PAUSE:
+ *val = mgp->pause;
+ break;
+
+ case ETHER_STAT_LINK_AUTONEG:
+ *val = 1;
+ break;
+
+ case ETHER_STAT_LINK_DUPLEX:
+ *val = LINK_DUPLEX_FULL;
+ break;
+
+ default:
+ return (ENOTSUP);
+ }
+
+ return (0);
+}
+
+static mac_callbacks_t myri10ge_m_callbacks = {
+ (MC_IOCTL | MC_GETCAPAB),
+ myri10ge_m_stat,
+ myri10ge_m_start,
+ myri10ge_m_stop,
+ myri10ge_m_promisc,
+ myri10ge_m_multicst,
+ NULL,
+ NULL,
+ myri10ge_m_ioctl,
+ myri10ge_m_getcapab
+};
+
+
+static int
+myri10ge_probe_slices(struct myri10ge_priv *mgp)
+{
+ myri10ge_cmd_t cmd;
+ int status;
+
+ mgp->num_slices = 1;
+
+ /* hit the board with a reset to ensure it is alive */
+ (void) memset(&cmd, 0, sizeof (cmd));
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed reset\n", mgp->name);
+ return (ENXIO);
+ }
+
+ if (myri10ge_use_msix == 0)
+ return (0);
+
+ /* tell it the size of the interrupt queues */
+ cmd.data0 = mgp->max_intr_slots * sizeof (struct mcp_slot);
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed MXGEFW_CMD_SET_INTRQ_SIZE\n",
+ mgp->name);
+ return (ENXIO);
+ }
+
+ /* ask the maximum number of slices it supports */
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
+ &cmd);
+ if (status != 0)
+ return (0);
+
+ mgp->num_slices = cmd.data0;
+
+ /*
+ * if the admin did not specify a limit to how many
+ * slices we should use, cap it automatically to the
+ * number of CPUs currently online
+ */
+ if (myri10ge_max_slices == -1)
+ myri10ge_max_slices = ncpus;
+
+ if (mgp->num_slices > myri10ge_max_slices)
+ mgp->num_slices = myri10ge_max_slices;
+
+
+ /*
+ * Now try to allocate as many MSI-X vectors as we have
+ * slices. We give up on MSI-X if we can only get a single
+ * vector.
+ */
+ while (mgp->num_slices > 1) {
+ /* make sure it is a power of two */
+ while (mgp->num_slices & (mgp->num_slices - 1))
+ mgp->num_slices--;
+ if (mgp->num_slices == 1)
+ return (0);
+
+ status = myri10ge_add_intrs(mgp, 0);
+ if (status == 0) {
+ myri10ge_rem_intrs(mgp, 0);
+ if (mgp->intr_cnt == mgp->num_slices) {
+ if (myri10ge_verbose)
+ printf("Got %d slices!\n",
+ mgp->num_slices);
+ return (0);
+ }
+ mgp->num_slices = mgp->intr_cnt;
+ } else {
+ mgp->num_slices = mgp->num_slices / 2;
+ }
+ }
+
+ if (myri10ge_verbose)
+ printf("Got %d slices\n", mgp->num_slices);
+ return (0);
+}
+
+static void
+myri10ge_lro_free(struct myri10ge_slice_state *ss)
+{
+ struct lro_entry *lro;
+
+ while (ss->lro_free != NULL) {
+ lro = ss->lro_free;
+ ss->lro_free = lro->next;
+ kmem_free(lro, sizeof (*lro));
+ }
+}
+
+static void
+myri10ge_lro_alloc(struct myri10ge_slice_state *ss)
+{
+ struct lro_entry *lro;
+ int idx;
+
+ ss->lro_free = NULL;
+ ss->lro_active = NULL;
+
+ for (idx = 0; idx < myri10ge_lro_cnt; idx++) {
+ lro = kmem_zalloc(sizeof (*lro), KM_SLEEP);
+ if (lro == NULL)
+ continue;
+ lro->next = ss->lro_free;
+ ss->lro_free = lro;
+ }
+}
+
+static void
+myri10ge_free_slices(struct myri10ge_priv *mgp)
+{
+ struct myri10ge_slice_state *ss;
+ size_t bytes;
+ int i;
+
+ if (mgp->ss == NULL)
+ return;
+
+ for (i = 0; i < mgp->num_slices; i++) {
+ ss = &mgp->ss[i];
+ if (ss->rx_done.entry == NULL)
+ continue;
+ myri10ge_dma_free(&ss->rx_done.dma);
+ ss->rx_done.entry = NULL;
+ if (ss->fw_stats == NULL)
+ continue;
+ myri10ge_dma_free(&ss->fw_stats_dma);
+ ss->fw_stats = NULL;
+ mutex_destroy(&ss->rx_lock);
+ mutex_destroy(&ss->tx.lock);
+ mutex_destroy(&ss->tx.handle_lock);
+ mutex_destroy(&ss->poll_lock);
+ myri10ge_jpool_fini(ss);
+ myri10ge_slice_stat_destroy(ss);
+ myri10ge_lro_free(ss);
+ }
+ bytes = sizeof (*mgp->ss) * mgp->num_slices;
+ kmem_free(mgp->ss, bytes);
+ mgp->ss = NULL;
+}
+
+
+static int
+myri10ge_alloc_slices(struct myri10ge_priv *mgp)
+{
+ struct myri10ge_slice_state *ss;
+ size_t bytes;
+ int i;
+
+ bytes = sizeof (*mgp->ss) * mgp->num_slices;
+ mgp->ss = kmem_zalloc(bytes, KM_SLEEP);
+ if (mgp->ss == NULL)
+ return (ENOMEM);
+ for (i = 0; i < mgp->num_slices; i++) {
+ ss = &mgp->ss[i];
+
+ ss->mgp = mgp;
+
+ /* allocate the per-slice firmware stats */
+ bytes = sizeof (*ss->fw_stats);
+ ss->fw_stats = (mcp_irq_data_t *)(void *)
+ myri10ge_dma_alloc(mgp->dip, bytes,
+ &myri10ge_misc_dma_attr, &myri10ge_dev_access_attr,
+ DDI_DMA_CONSISTENT, DDI_DMA_READ|DDI_DMA_CONSISTENT,
+ &ss->fw_stats_dma, 1, DDI_DMA_DONTWAIT);
+ if (ss->fw_stats == NULL)
+ goto abort;
+ (void) memset(ss->fw_stats, 0, bytes);
+
+ /* allocate rx done ring */
+ bytes = mgp->max_intr_slots *
+ sizeof (*ss->rx_done.entry);
+ ss->rx_done.entry = (mcp_slot_t *)(void *)
+ myri10ge_dma_alloc(mgp->dip, bytes,
+ &myri10ge_misc_dma_attr, &myri10ge_dev_access_attr,
+ DDI_DMA_CONSISTENT, DDI_DMA_READ|DDI_DMA_CONSISTENT,
+ &ss->rx_done.dma, 1, DDI_DMA_DONTWAIT);
+ if (ss->rx_done.entry == NULL) {
+ goto abort;
+ }
+ (void) memset(ss->rx_done.entry, 0, bytes);
+ mutex_init(&ss->rx_lock, NULL, MUTEX_DEFAULT, mgp->icookie);
+ mutex_init(&ss->tx.lock, NULL, MUTEX_DEFAULT, NULL);
+ mutex_init(&ss->tx.handle_lock, NULL, MUTEX_DEFAULT, NULL);
+ mutex_init(&ss->poll_lock, NULL, MUTEX_DEFAULT, NULL);
+ myri10ge_jpool_init(ss);
+ (void) myri10ge_slice_stat_init(ss);
+ myri10ge_lro_alloc(ss);
+ }
+
+ return (0);
+
+abort:
+ myri10ge_free_slices(mgp);
+ return (ENOMEM);
+}
+
+static int
+myri10ge_save_msi_state(struct myri10ge_priv *mgp,
+ ddi_acc_handle_t handle)
+{
+ uint8_t ptr;
+ int err;
+
+ err = myri10ge_find_cap(handle, &ptr, PCI_CAP_ID_MSI);
+ if (err != 0) {
+ cmn_err(CE_WARN, "%s: could not find MSI cap\n",
+ mgp->name);
+ return (DDI_FAILURE);
+ }
+ mgp->pci_saved_state.msi_ctrl =
+ pci_config_get16(handle, ptr + PCI_MSI_CTRL);
+ mgp->pci_saved_state.msi_addr_low =
+ pci_config_get32(handle, ptr + PCI_MSI_ADDR_OFFSET);
+ mgp->pci_saved_state.msi_addr_high =
+ pci_config_get32(handle, ptr + PCI_MSI_ADDR_OFFSET + 4);
+ mgp->pci_saved_state.msi_data_32 =
+ pci_config_get16(handle, ptr + PCI_MSI_32BIT_DATA);
+ mgp->pci_saved_state.msi_data_64 =
+ pci_config_get16(handle, ptr + PCI_MSI_64BIT_DATA);
+ return (DDI_SUCCESS);
+}
+
+static int
+myri10ge_restore_msi_state(struct myri10ge_priv *mgp,
+ ddi_acc_handle_t handle)
+{
+ uint8_t ptr;
+ int err;
+
+ err = myri10ge_find_cap(handle, &ptr, PCI_CAP_ID_MSI);
+ if (err != 0) {
+ cmn_err(CE_WARN, "%s: could not find MSI cap\n",
+ mgp->name);
+ return (DDI_FAILURE);
+ }
+
+ pci_config_put16(handle, ptr + PCI_MSI_CTRL,
+ mgp->pci_saved_state.msi_ctrl);
+ pci_config_put32(handle, ptr + PCI_MSI_ADDR_OFFSET,
+ mgp->pci_saved_state.msi_addr_low);
+ pci_config_put32(handle, ptr + PCI_MSI_ADDR_OFFSET + 4,
+ mgp->pci_saved_state.msi_addr_high);
+ pci_config_put16(handle, ptr + PCI_MSI_32BIT_DATA,
+ mgp->pci_saved_state.msi_data_32);
+ pci_config_put16(handle, ptr + PCI_MSI_64BIT_DATA,
+ mgp->pci_saved_state.msi_data_64);
+
+ return (DDI_SUCCESS);
+}
+
+static int
+myri10ge_save_pci_state(struct myri10ge_priv *mgp)
+{
+ ddi_acc_handle_t handle = mgp->cfg_hdl;
+ int i;
+ int err = DDI_SUCCESS;
+
+
+ /* Save the non-extended PCI config space 32-bits at a time */
+ for (i = 0; i < 16; i++)
+ mgp->pci_saved_state.base[i] =
+ pci_config_get32(handle, i*4);
+
+ /* now save MSI interrupt state *, if needed */
+ if (mgp->ddi_intr_type == DDI_INTR_TYPE_MSI)
+ err = myri10ge_save_msi_state(mgp, handle);
+
+ return (err);
+}
+
+static int
+myri10ge_restore_pci_state(struct myri10ge_priv *mgp)
+{
+ ddi_acc_handle_t handle = mgp->cfg_hdl;
+ int i;
+ int err = DDI_SUCCESS;
+
+
+ /* Restore the non-extended PCI config space 32-bits at a time */
+ for (i = 15; i >= 0; i--)
+ pci_config_put32(handle, i*4, mgp->pci_saved_state.base[i]);
+
+ /* now restore MSI interrupt state *, if needed */
+ if (mgp->ddi_intr_type == DDI_INTR_TYPE_MSI)
+ err = myri10ge_restore_msi_state(mgp, handle);
+
+ if (mgp->max_read_request_4k)
+ (void) myri10ge_set_max_readreq(handle);
+ return (err);
+}
+
+
+static int
+myri10ge_suspend(dev_info_t *dip)
+{
+ struct myri10ge_priv *mgp = ddi_get_driver_private(dip);
+ int status;
+
+ if (mgp == NULL) {
+ cmn_err(CE_WARN, "null dip in myri10ge_suspend\n");
+ return (DDI_FAILURE);
+ }
+ if (mgp->dip != dip) {
+ cmn_err(CE_WARN, "bad dip in myri10ge_suspend\n");
+ return (DDI_FAILURE);
+ }
+ mutex_enter(&mgp->intrlock);
+ if (mgp->running == MYRI10GE_ETH_RUNNING) {
+ mgp->running = MYRI10GE_ETH_STOPPING;
+ mutex_exit(&mgp->intrlock);
+ (void) untimeout(mgp->timer_id);
+ mutex_enter(&mgp->intrlock);
+ myri10ge_stop_locked(mgp);
+ mgp->running = MYRI10GE_ETH_SUSPENDED_RUNNING;
+ }
+ status = myri10ge_save_pci_state(mgp);
+ mutex_exit(&mgp->intrlock);
+ return (status);
+}
+
+static int
+myri10ge_resume(dev_info_t *dip)
+{
+ struct myri10ge_priv *mgp = ddi_get_driver_private(dip);
+ int status = DDI_SUCCESS;
+
+ if (mgp == NULL) {
+ cmn_err(CE_WARN, "null dip in myri10ge_resume\n");
+ return (DDI_FAILURE);
+ }
+ if (mgp->dip != dip) {
+ cmn_err(CE_WARN, "bad dip in myri10ge_resume\n");
+ return (DDI_FAILURE);
+ }
+
+ mutex_enter(&mgp->intrlock);
+ status = myri10ge_restore_pci_state(mgp);
+ if (status == DDI_SUCCESS &&
+ mgp->running == MYRI10GE_ETH_SUSPENDED_RUNNING) {
+ status = myri10ge_start_locked(mgp);
+ }
+ mutex_exit(&mgp->intrlock);
+ if (status != DDI_SUCCESS)
+ return (status);
+
+ /* start the watchdog timer */
+ mgp->timer_id = timeout(myri10ge_watchdog, mgp,
+ mgp->timer_ticks);
+ return (DDI_SUCCESS);
+}
+
+static int
+myri10ge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
+{
+
+ struct myri10ge_priv *mgp;
+ mac_register_t *macp, *omacp;
+ ddi_acc_handle_t handle;
+ uint32_t csr, hdr_offset;
+ int status, span, link_width, max_read_request_4k;
+ unsigned long bus_number, dev_number, func_number;
+ size_t bytes;
+ offset_t ss_offset;
+ uint8_t vso;
+
+ if (cmd == DDI_RESUME) {
+ return (myri10ge_resume(dip));
+ }
+
+ if (cmd != DDI_ATTACH)
+ return (DDI_FAILURE);
+ if (pci_config_setup(dip, &handle) != DDI_SUCCESS)
+ return (DDI_FAILURE);
+
+ /* enable busmater and io space access */
+ csr = pci_config_get32(handle, PCI_CONF_COMM);
+ pci_config_put32(handle, PCI_CONF_COMM,
+ (csr |PCI_COMM_ME|PCI_COMM_MAE));
+ status = myri10ge_read_pcie_link_width(handle, &link_width);
+ if (status != 0) {
+ cmn_err(CE_WARN, "could not read link width!\n");
+ link_width = 0;
+ }
+ max_read_request_4k = !myri10ge_set_max_readreq(handle);
+ status = myri10ge_find_cap(handle, &vso, PCI_CAP_ID_VS);
+ if (status != 0)
+ goto abort_with_cfg_hdl;
+ if ((omacp = mac_alloc(MAC_VERSION)) == NULL)
+ goto abort_with_cfg_hdl;
+ /*
+ * XXXX Hack: mac_register_t grows in newer kernels. To be
+ * able to write newer fields, such as m_margin, without
+ * writing outside allocated memory, we allocate our own macp
+ * and pass that to mac_register()
+ */
+ macp = kmem_zalloc(sizeof (*macp) * 8, KM_SLEEP);
+ macp->m_version = omacp->m_version;
+
+ if ((mgp = (struct myri10ge_priv *)
+ kmem_zalloc(sizeof (*mgp), KM_SLEEP)) == NULL) {
+ goto abort_with_macinfo;
+ }
+ ddi_set_driver_private(dip, mgp);
+
+ /* setup device name for log messages */
+ (void) sprintf(mgp->name, "myri10ge%d", ddi_get_instance(dip));
+
+ mutex_enter(&myri10ge_param_lock);
+ myri10ge_get_props(dip);
+ mgp->intr_coal_delay = myri10ge_intr_coal_delay;
+ mgp->pause = myri10ge_flow_control;
+ mutex_exit(&myri10ge_param_lock);
+
+ mgp->max_read_request_4k = max_read_request_4k;
+ mgp->pcie_link_width = link_width;
+ mgp->running = MYRI10GE_ETH_STOPPED;
+ mgp->vso = vso;
+ mgp->dip = dip;
+ mgp->cfg_hdl = handle;
+
+ mgp->timer_ticks = 5 * drv_usectohz(1000000); /* 5 seconds */
+ myri10ge_test_physical(dip);
+
+ /* allocate command page */
+ bytes = sizeof (*mgp->cmd);
+ mgp->cmd = (mcp_cmd_response_t *)
+ (void *)myri10ge_dma_alloc(dip, bytes,
+ &myri10ge_misc_dma_attr, &myri10ge_dev_access_attr,
+ DDI_DMA_CONSISTENT, DDI_DMA_RDWR|DDI_DMA_CONSISTENT,
+ &mgp->cmd_dma, 1, DDI_DMA_DONTWAIT);
+ if (mgp->cmd == NULL)
+ goto abort_with_mgp;
+
+ (void) myri10ge_reg_set(dip, &mgp->reg_set, &span, &bus_number,
+ &dev_number, &func_number);
+ if (myri10ge_verbose)
+ printf("%s at %ld:%ld:%ld attaching\n", mgp->name,
+ bus_number, dev_number, func_number);
+ status = ddi_regs_map_setup(dip, mgp->reg_set, (caddr_t *)&mgp->sram,
+ (offset_t)0, (offset_t)span, &myri10ge_dev_access_attr,
+ &mgp->io_handle);
+ if (status != DDI_SUCCESS) {
+ cmn_err(CE_WARN, "%s: couldn't map memory space", mgp->name);
+ printf("%s: reg_set = %d, span = %d, status = %d",
+ mgp->name, mgp->reg_set, span, status);
+ goto abort_with_mgp;
+ }
+
+ hdr_offset = *(uint32_t *)(void*)(mgp->sram + MCP_HEADER_PTR_OFFSET);
+ hdr_offset = ntohl(hdr_offset) & 0xffffc;
+ ss_offset = hdr_offset +
+ offsetof(struct mcp_gen_header, string_specs);
+ mgp->sram_size = ntohl(*(uint32_t *)(void*)(mgp->sram + ss_offset));
+ myri10ge_pio_copy32(mgp->eeprom_strings,
+ (uint32_t *)(void*)((char *)mgp->sram + mgp->sram_size),
+ MYRI10GE_EEPROM_STRINGS_SIZE);
+ (void) memset(mgp->eeprom_strings +
+ MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
+
+ status = myri10ge_read_mac_addr(mgp);
+ if (status) {
+ goto abort_with_mapped;
+ }
+
+ status = myri10ge_select_firmware(mgp);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed to load firmware\n", mgp->name);
+ goto abort_with_mapped;
+ }
+
+ status = myri10ge_probe_slices(mgp);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed to probe slices\n", mgp->name);
+ goto abort_with_dummy_rdma;
+ }
+
+ status = myri10ge_alloc_slices(mgp);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: failed to alloc slices\n", mgp->name);
+ goto abort_with_dummy_rdma;
+ }
+
+ /* add the interrupt handler */
+ status = myri10ge_add_intrs(mgp, 1);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: Failed to add interrupt\n",
+ mgp->name);
+ goto abort_with_slices;
+ }
+
+ /* now that we have an iblock_cookie, init the mutexes */
+ mutex_init(&mgp->cmd_lock, NULL, MUTEX_DRIVER, mgp->icookie);
+ mutex_init(&mgp->intrlock, NULL, MUTEX_DRIVER, mgp->icookie);
+
+
+ status = myri10ge_nic_stat_init(mgp);
+ if (status != DDI_SUCCESS)
+ goto abort_with_interrupts;
+ status = myri10ge_info_init(mgp);
+ if (status != DDI_SUCCESS)
+ goto abort_with_stats;
+
+ /*
+ * Initialize GLD state
+ */
+
+ macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
+ macp->m_driver = mgp;
+ macp->m_dip = dip;
+ macp->m_src_addr = mgp->mac_addr;
+ macp->m_callbacks = &myri10ge_m_callbacks;
+ macp->m_min_sdu = 0;
+ macp->m_max_sdu = myri10ge_mtu -
+ (sizeof (struct ether_header) + MXGEFW_PAD + VLAN_TAGSZ);
+#ifdef SOLARIS_S11
+ macp->m_margin = VLAN_TAGSZ;
+#endif
+ macp->m_v12n = MAC_VIRT_LEVEL1;
+ status = mac_register(macp, &mgp->mh);
+ if (status != 0) {
+ cmn_err(CE_WARN, "%s: mac_register failed with %d\n",
+ mgp->name, status);
+ goto abort_with_info;
+ }
+ myri10ge_ndd_init(mgp);
+ if (myri10ge_verbose)
+ printf("%s: %s, tx bndry %d, fw %s\n", mgp->name,
+ mgp->intr_type, mgp->tx_boundary, mgp->fw_name);
+ mutex_enter(&myri10ge_param_lock);
+ mgp->next = mgp_list;
+ mgp_list = mgp;
+ mutex_exit(&myri10ge_param_lock);
+ kmem_free(macp, sizeof (*macp) * 8);
+ mac_free(omacp);
+ return (DDI_SUCCESS);
+
+abort_with_info:
+ myri10ge_info_destroy(mgp);
+
+abort_with_stats:
+ myri10ge_nic_stat_destroy(mgp);
+
+abort_with_interrupts:
+ mutex_destroy(&mgp->cmd_lock);
+ mutex_destroy(&mgp->intrlock);
+ myri10ge_rem_intrs(mgp, 1);
+
+abort_with_slices:
+ myri10ge_free_slices(mgp);
+
+abort_with_dummy_rdma:
+ myri10ge_dummy_rdma(mgp, 0);
+
+abort_with_mapped:
+ ddi_regs_map_free(&mgp->io_handle);
+
+ myri10ge_dma_free(&mgp->cmd_dma);
+
+abort_with_mgp:
+ kmem_free(mgp, sizeof (*mgp));
+
+abort_with_macinfo:
+ kmem_free(macp, sizeof (*macp) * 8);
+ mac_free(omacp);
+
+abort_with_cfg_hdl:
+ pci_config_teardown(&handle);
+ return (DDI_FAILURE);
+
+}
+
+
+static int
+myri10ge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
+{
+ struct myri10ge_priv *mgp, *tmp;
+ int status, i, jbufs_alloced;
+
+ if (cmd == DDI_SUSPEND) {
+ status = myri10ge_suspend(dip);
+ return (status);
+ }
+
+ if (cmd != DDI_DETACH) {
+ return (DDI_FAILURE);
+ }
+ /* Get the driver private (gld_mac_info_t) structure */
+ mgp = ddi_get_driver_private(dip);
+
+ mutex_enter(&mgp->intrlock);
+ jbufs_alloced = 0;
+ for (i = 0; i < mgp->num_slices; i++) {
+ myri10ge_remove_jbufs(&mgp->ss[i]);
+ jbufs_alloced += mgp->ss[i].jpool.num_alloc;
+ }
+ mutex_exit(&mgp->intrlock);
+ if (jbufs_alloced != 0) {
+ cmn_err(CE_NOTE, "%s: %d loaned rx buffers remain\n",
+ mgp->name, jbufs_alloced);
+ return (DDI_FAILURE);
+ }
+
+ mutex_enter(&myri10ge_param_lock);
+ if (mgp->refcnt != 0) {
+ mutex_exit(&myri10ge_param_lock);
+ cmn_err(CE_NOTE, "%s: %d external refs remain\n",
+ mgp->name, mgp->refcnt);
+ return (DDI_FAILURE);
+ }
+ mutex_exit(&myri10ge_param_lock);
+
+ status = mac_unregister(mgp->mh);
+ if (status != DDI_SUCCESS)
+ return (status);
+
+ myri10ge_ndd_fini(mgp);
+ myri10ge_dummy_rdma(mgp, 0);
+ myri10ge_nic_stat_destroy(mgp);
+ myri10ge_info_destroy(mgp);
+
+ mutex_destroy(&mgp->cmd_lock);
+ mutex_destroy(&mgp->intrlock);
+
+ myri10ge_rem_intrs(mgp, 1);
+
+ myri10ge_free_slices(mgp);
+ ddi_regs_map_free(&mgp->io_handle);
+ myri10ge_dma_free(&mgp->cmd_dma);
+ pci_config_teardown(&mgp->cfg_hdl);
+
+ mutex_enter(&myri10ge_param_lock);
+ if (mgp_list == mgp) {
+ mgp_list = mgp->next;
+ } else {
+ tmp = mgp_list;
+ while (tmp->next != mgp && tmp->next != NULL)
+ tmp = tmp->next;
+ if (tmp->next != NULL)
+ tmp->next = tmp->next->next;
+ }
+ kmem_free(mgp, sizeof (*mgp));
+ mutex_exit(&myri10ge_param_lock);
+ return (DDI_SUCCESS);
+}
+
+/*
+ * Helper for quiesce entry point: Interrupt threads are not being
+ * scheduled, so we must poll for the confirmation DMA to arrive in
+ * the firmware stats block for slice 0. We're essentially running
+ * the guts of the interrupt handler, and just cherry picking the
+ * confirmation that the NIC is queuesced (stats->link_down)
+ */
+
+static int
+myri10ge_poll_down(struct myri10ge_priv *mgp)
+{
+ struct myri10ge_slice_state *ss = mgp->ss;
+ mcp_irq_data_t *stats = ss->fw_stats;
+ int valid;
+ int found_down = 0;
+
+
+ /* check for a pending IRQ */
+
+ if (! *((volatile uint8_t *)& stats->valid))
+ return (0);
+ valid = stats->valid;
+
+ /*
+ * Make sure to tell the NIC to lower a legacy IRQ, else
+ * it may have corrupt state after restarting
+ */
+
+ if (mgp->ddi_intr_type == DDI_INTR_TYPE_FIXED) {
+ /* lower legacy IRQ */
+ *mgp->irq_deassert = 0;
+ mb();
+ /* wait for irq conf DMA */
+ while (*((volatile uint8_t *)& stats->valid))
+ ;
+ }
+ if (stats->stats_updated && stats->link_down)
+ found_down = 1;
+
+ if (valid & 0x1)
+ *ss->irq_claim = BE_32(3);
+ *(ss->irq_claim + 1) = BE_32(3);
+
+ return (found_down);
+}
+
+static int
+myri10ge_quiesce(dev_info_t *dip)
+{
+ struct myri10ge_priv *mgp;
+ myri10ge_cmd_t cmd;
+ int status, down, i;
+
+ mgp = ddi_get_driver_private(dip);
+ if (mgp == NULL)
+ return (DDI_FAILURE);
+
+ /* if devices was unplumbed, it is guaranteed to be quiescent */
+ if (mgp->running == MYRI10GE_ETH_STOPPED)
+ return (DDI_SUCCESS);
+
+ /* send a down CMD to queuesce NIC */
+ status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd);
+ if (status) {
+ cmn_err(CE_WARN, "%s: Couldn't bring down link\n", mgp->name);
+ return (DDI_FAILURE);
+ }
+
+ for (i = 0; i < 20; i++) {
+ down = myri10ge_poll_down(mgp);
+ if (down)
+ break;
+ delay(drv_usectohz(100000));
+ mb();
+ }
+ if (down)
+ return (DDI_SUCCESS);
+ return (DDI_FAILURE);
+}
+
+/*
+ * Distinguish between allocb'ed blocks, and gesballoc'ed attached
+ * storage.
+ */
+static void
+myri10ge_find_lastfree(void)
+{
+ mblk_t *mp = allocb(1024, 0);
+ dblk_t *dbp;
+
+ if (mp == NULL) {
+ cmn_err(CE_WARN, "myri10ge_find_lastfree failed\n");
+ return;
+ }
+ dbp = mp->b_datap;
+ myri10ge_db_lastfree = (void *)dbp->db_lastfree;
+}
+
+int
+_init(void)
+{
+ int i;
+
+ if (myri10ge_verbose)
+ cmn_err(CE_NOTE,
+ "Myricom 10G driver (10GbE) version %s loading\n",
+ MYRI10GE_VERSION_STR);
+ myri10ge_find_lastfree();
+ mac_init_ops(&myri10ge_ops, "myri10ge");
+ mutex_init(&myri10ge_param_lock, NULL, MUTEX_DEFAULT, NULL);
+ if ((i = mod_install(&modlinkage)) != 0) {
+ cmn_err(CE_WARN, "mod_install returned %d\n", i);
+ mac_fini_ops(&myri10ge_ops);
+ mutex_destroy(&myri10ge_param_lock);
+ }
+ return (i);
+}
+
+int
+_fini(void)
+{
+ int i;
+ i = mod_remove(&modlinkage);
+ if (i != 0) {
+ return (i);
+ }
+ mac_fini_ops(&myri10ge_ops);
+ mutex_destroy(&myri10ge_param_lock);
+ return (0);
+}
+
+int
+_info(struct modinfo *modinfop)
+{
+ return (mod_info(&modlinkage, modinfop));
+}
+
+
+/*
+ * This file uses MyriGE driver indentation.
+ *
+ * Local Variables:
+ * c-file-style:"sun"
+ * tab-width:8
+ * End:
+ */
diff --git a/usr/src/uts/common/io/myri10ge/drv/myri10ge_lro.c b/usr/src/uts/common/io/myri10ge/drv/myri10ge_lro.c
new file mode 100644
index 0000000000..2d03fceac6
--- /dev/null
+++ b/usr/src/uts/common/io/myri10ge/drv/myri10ge_lro.c
@@ -0,0 +1,366 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007-2009 Myricom, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef lint
+static const char __idstring[] =
+ "@(#)$Id: myri10ge_lro.c,v 1.7 2009-06-29 13:47:22 gallatin Exp $";
+#endif
+
+#include "myri10ge_var.h"
+
+#define IP_OFFMASK 0x1fff
+#define TCPOPT_TIMESTAMP 8
+#define TCPOLEN_TIMESTAMP 10
+#define TCPOLEN_TSTAMP_APPA 12
+
+
+/*
+ * Assume len is a multiple of 4. Note that "raw" must be
+ * suitably aligned. In practice, it will always enter algned on
+ * at least a 4 bytes bounday, due to the alignment of our rx buffers.
+ */
+uint16_t
+myri10ge_csum_generic(uint16_t *raw, int len)
+{
+ uint32_t csum;
+ csum = 0;
+ while (len > 0) {
+ csum += *raw;
+ raw++;
+ csum += *raw;
+ raw++;
+ len -= 4;
+ }
+ csum = (csum >> 16) + (csum & 0xffff);
+ csum = (csum >> 16) + (csum & 0xffff);
+ return ((uint16_t)csum);
+}
+
+static uint16_t
+myri10ge_in_pseudo(unsigned int a, unsigned int b,
+ unsigned int c)
+{
+ uint64_t csum;
+
+ csum = (uint64_t)a + b + c;
+ csum = (csum >> 16) + (csum & 0xffff);
+ csum = (csum >> 16) + (csum & 0xffff);
+ return ((uint16_t)csum);
+}
+
+void
+myri10ge_lro_flush(struct myri10ge_slice_state *ss, struct lro_entry *lro,
+ struct myri10ge_mblk_list *mbl)
+{
+ struct ip *ip;
+ struct tcphdr *tcp;
+ uint32_t *ts_ptr;
+ uint32_t tcplen, tcp_csum;
+
+ if (lro->append_cnt) {
+ /*
+ * incorporate the new len into the ip header and
+ * re-calculate the checksum
+ */
+ ip = lro->ip;
+ ip->ip_len = htons(lro->len - ETHERNET_HEADER_SIZE);
+ ip->ip_sum = 0;
+ ip->ip_sum = 0xffff ^
+ myri10ge_csum_generic((uint16_t *)ip, sizeof (*ip));
+ /* incorporate the latest ack into the tcp header */
+ tcp = (struct tcphdr *)(ip + 1);
+ tcp->th_ack = lro->ack_seq;
+ tcp->th_win = lro->window;
+ tcp->th_flags = lro->flags;
+ /* incorporate latest timestamp into the tcp header */
+ if (lro->timestamp) {
+ ts_ptr = (uint32_t *)(tcp + 1);
+ ts_ptr[1] = htonl(lro->tsval);
+ ts_ptr[2] = lro->tsecr;
+ }
+ /*
+ * update checksum in tcp header by re-calculating the
+ * tcp pseudoheader checksum, and adding it to the checksum
+ * of the tcp payload data
+ */
+ tcp->th_sum = 0;
+ tcplen = lro->len - sizeof (*ip) - ETHERNET_HEADER_SIZE;
+ tcp_csum = lro->data_csum;
+ tcp_csum += myri10ge_in_pseudo(ip->ip_src.s_addr,
+ ip->ip_dst.s_addr, htons(tcplen + IPPROTO_TCP));
+ tcp_csum += myri10ge_csum_generic((uint16_t *)tcp,
+ tcp->th_off << 2);
+ tcp_csum = (tcp_csum & 0xffff) + (tcp_csum >> 16);
+ tcp_csum = (tcp_csum & 0xffff) + (tcp_csum >> 16);
+ tcp->th_sum = 0xffff ^ tcp_csum;
+ }
+
+ (void) hcksum_assoc(lro->m_head, NULL, NULL, 0, 0, 0,
+ 0, HCK_IPV4_HDRCKSUM | HCK_FULLCKSUM | HCK_FULLCKSUM_OK, 0);
+
+ mbl->cnt += lro->append_cnt;
+ myri10ge_mbl_append(ss, mbl, lro->m_head);
+ MYRI10GE_SLICE_STAT_INC(lro_flushed);
+ MYRI10GE_SLICE_STAT_ADD(lro_queued, lro->append_cnt + 1);
+ lro->m_head = NULL;
+ lro->timestamp = 0;
+ lro->append_cnt = 0;
+ lro->next = ss->lro_free;
+ ss->lro_free = lro;
+}
+
+int
+myri10ge_lro_rx(struct myri10ge_slice_state *ss, mblk_t *m_head,
+ uint32_t csum, struct myri10ge_mblk_list *mbl)
+{
+ struct ether_header *eh;
+ struct ip *ip;
+ struct tcphdr *tcp;
+ uint32_t *ts_ptr;
+ struct lro_entry *lro, *curr;
+ int hlen, ip_len, tcp_hdr_len, tcp_data_len;
+ int opt_bytes, trim;
+ int tot_len = MBLKL(m_head);
+ uint32_t seq, tmp_csum;
+
+ eh = (struct ether_header *)(void *)m_head->b_rptr;
+ if (eh->ether_type != htons(ETHERTYPE_IP))
+ return (EINVAL);
+ ip = (struct ip *)(void *)(eh + 1);
+ if (ip->ip_p != IPPROTO_TCP)
+ return (EINVAL);
+
+ /* ensure there are no options */
+ if ((ip->ip_hl << 2) != sizeof (*ip))
+ return (EINVAL);
+
+ /* .. and the packet is not fragmented */
+ if (ip->ip_off & htons(IP_MF|IP_OFFMASK))
+ return (EINVAL);
+
+ /* verify that the IP header checksum is correct */
+ tmp_csum = myri10ge_csum_generic((uint16_t *)ip, sizeof (*ip));
+ if (unlikely((tmp_csum ^ 0xffff) != 0)) {
+ MYRI10GE_SLICE_STAT_INC(lro_bad_csum);
+ return (EINVAL);
+ }
+
+ /* find the TCP header */
+ tcp = (struct tcphdr *)(ip + 1);
+
+ /* ensure no bits set besides ack or psh */
+ if ((tcp->th_flags & ~(TH_ACK | TH_PUSH)) != 0)
+ return (EINVAL);
+
+ /*
+ * check for timestamps. Since the only option we handle are
+ * timestamps, we only have to handle the simple case of
+ * aligned timestamps
+ */
+
+ opt_bytes = (tcp->th_off << 2) - sizeof (*tcp);
+ tcp_hdr_len = sizeof (*tcp) + opt_bytes;
+ ts_ptr = (uint32_t *)(tcp + 1);
+ if (opt_bytes != 0) {
+ if (unlikely(opt_bytes != TCPOLEN_TSTAMP_APPA) ||
+ (*ts_ptr != ntohl(TCPOPT_NOP<<24|TCPOPT_NOP<<16|
+ TCPOPT_TIMESTAMP<<8|TCPOLEN_TIMESTAMP)))
+ return (EINVAL);
+ }
+
+ ip_len = ntohs(ip->ip_len);
+ tcp_data_len = ip_len - (tcp->th_off << 2) - sizeof (*ip);
+
+ /*
+ * If frame is padded beyond the end of the IP packet,
+ * then we must trim the extra bytes off the end.
+ */
+ trim = tot_len - (ip_len + ETHERNET_HEADER_SIZE);
+ if (trim != 0) {
+ if (trim < 0) {
+ /* truncated packet */
+ return (EINVAL);
+ }
+ m_head->b_wptr -= trim;
+ tot_len -= trim;
+ }
+
+ /* Verify TCP checksum */
+ csum = ntohs((uint16_t)csum);
+ tmp_csum = csum + myri10ge_in_pseudo(ip->ip_src.s_addr,
+ ip->ip_dst.s_addr, htons(tcp_hdr_len + tcp_data_len + IPPROTO_TCP));
+ tmp_csum = (tmp_csum & 0xffff) + (tmp_csum >> 16);
+ tmp_csum = (tmp_csum & 0xffff) + (tmp_csum >> 16);
+ if (tmp_csum != 0xffff) {
+ MYRI10GE_SLICE_STAT_INC(lro_bad_csum);
+ return (EINVAL);
+ }
+
+ hlen = ip_len + ETHERNET_HEADER_SIZE - tcp_data_len;
+ seq = ntohl(tcp->th_seq);
+
+ for (lro = ss->lro_active; lro != NULL; lro = lro->next) {
+ if (lro->source_port == tcp->th_sport &&
+ lro->dest_port == tcp->th_dport &&
+ lro->source_ip == ip->ip_src.s_addr &&
+ lro->dest_ip == ip->ip_dst.s_addr) {
+ /* Try to append it */
+
+ if (unlikely(seq != lro->next_seq)) {
+ /* out of order packet */
+ if (ss->lro_active == lro) {
+ ss->lro_active = lro->next;
+ } else {
+ curr = ss->lro_active;
+ while (curr->next != lro)
+ curr = curr->next;
+ curr->next = lro->next;
+ }
+ myri10ge_lro_flush(ss, lro, mbl);
+ return (EINVAL);
+ }
+
+ if (opt_bytes) {
+ uint32_t tsval = ntohl(*(ts_ptr + 1));
+ /* make sure timestamp values are increasing */
+ if (unlikely(lro->tsval > tsval ||
+ *(ts_ptr + 2) == 0)) {
+ return (-8);
+ }
+ lro->tsval = tsval;
+ lro->tsecr = *(ts_ptr + 2);
+ }
+
+ lro->next_seq += tcp_data_len;
+ lro->ack_seq = tcp->th_ack;
+ lro->window = tcp->th_win;
+ lro->flags |= tcp->th_flags;
+ lro->append_cnt++;
+ if (tcp_data_len == 0) {
+ freeb(m_head);
+ return (0);
+ }
+ /*
+ * subtract off the checksum of the tcp header
+ * from the hardware checksum, and add it to
+ * the stored tcp data checksum. Byteswap
+ * the checksum if the total length so far is
+ * odd
+ */
+ tmp_csum = myri10ge_csum_generic((uint16_t *)tcp,
+ tcp_hdr_len);
+ csum = csum + (tmp_csum ^ 0xffff);
+ csum = (csum & 0xffff) + (csum >> 16);
+ csum = (csum & 0xffff) + (csum >> 16);
+ if (lro->len & 0x1) {
+ /* Odd number of bytes so far, flip bytes */
+ csum = ((csum << 8) | (csum >> 8)) & 0xffff;
+ }
+ csum = csum + lro->data_csum;
+ csum = (csum & 0xffff) + (csum >> 16);
+ csum = (csum & 0xffff) + (csum >> 16);
+ lro->data_csum = csum;
+
+ lro->len += tcp_data_len;
+
+ /*
+ * adjust mblk so that rptr points to
+ * the first byte of the payload
+ */
+ m_head->b_rptr += hlen;
+ /* append mbuf chain */
+ lro->m_tail->b_cont = m_head;
+ /* advance the last pointer */
+ lro->m_tail = m_head;
+ /* flush packet if required */
+ if (lro->len > (65535 - myri10ge_mtu) ||
+ (lro->append_cnt + 1) == myri10ge_lro_max_aggr) {
+ if (ss->lro_active == lro) {
+ ss->lro_active = lro->next;
+ } else {
+ curr = ss->lro_active;
+ while (curr->next != lro)
+ curr = curr->next;
+ curr->next = lro->next;
+ }
+ myri10ge_lro_flush(ss, lro, mbl);
+ }
+ return (0);
+ }
+ }
+
+ if (ss->lro_free == NULL)
+ return (ENOMEM);
+
+ /* start a new chain */
+ lro = ss->lro_free;
+ ss->lro_free = lro->next;
+ lro->next = ss->lro_active;
+ ss->lro_active = lro;
+ lro->source_port = tcp->th_sport;
+ lro->dest_port = tcp->th_dport;
+ lro->source_ip = ip->ip_src.s_addr;
+ lro->dest_ip = ip->ip_dst.s_addr;
+ lro->next_seq = seq + tcp_data_len;
+ lro->mss = (uint16_t)tcp_data_len;
+ lro->ack_seq = tcp->th_ack;
+ lro->window = tcp->th_win;
+ lro->flags = tcp->th_flags;
+
+ /*
+ * save the checksum of just the TCP payload by
+ * subtracting off the checksum of the TCP header from
+ * the entire hardware checksum
+ * Since IP header checksum is correct, checksum over
+ * the IP header is -0. Substracting -0 is unnecessary.
+ */
+ tmp_csum = myri10ge_csum_generic((uint16_t *)tcp, tcp_hdr_len);
+ csum = csum + (tmp_csum ^ 0xffff);
+ csum = (csum & 0xffff) + (csum >> 16);
+ csum = (csum & 0xffff) + (csum >> 16);
+ lro->data_csum = csum;
+ lro->ip = ip;
+
+ /* record timestamp if it is present */
+ if (opt_bytes) {
+ lro->timestamp = 1;
+ lro->tsval = ntohl(*(ts_ptr + 1));
+ lro->tsecr = *(ts_ptr + 2);
+ }
+ lro->len = tot_len;
+ lro->m_head = m_head;
+ lro->m_tail = m_head;
+ return (0);
+}
+
+/*
+ * This file uses MyriGE driver indentation.
+ *
+ * Local Variables:
+ * c-file-style:"sun"
+ * tab-width:8
+ * End:
+ */
diff --git a/usr/src/uts/common/io/myri10ge/drv/myri10ge_var.h b/usr/src/uts/common/io/myri10ge/drv/myri10ge_var.h
new file mode 100644
index 0000000000..6840795e94
--- /dev/null
+++ b/usr/src/uts/common/io/myri10ge/drv/myri10ge_var.h
@@ -0,0 +1,533 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007-2009 Myricom, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef MYRI10GE_VAR_H
+#define MYRI10GE_VAR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/types.h>
+#include <sys/errno.h>
+#include <sys/param.h>
+#include <sys/atomic.h>
+#include <sys/stropts.h>
+#include <sys/stream.h>
+#include <sys/kmem.h>
+#include <sys/ksynch.h>
+#include <sys/stat.h>
+#include <sys/modctl.h>
+#include <sys/debug.h>
+#include <sys/dlpi.h>
+#include <sys/ethernet.h>
+#include <sys/mac_provider.h>
+#define MAC_CAPAB_POLL 0
+#define MC_RESOURCES 0
+#include <sys/mac_ether.h>
+#ifndef MYRICOM_PRIV
+#include <sys/vlan.h>
+#endif
+#include <sys/pci.h>
+#include <sys/pcie.h>
+#include <sys/ddi.h>
+#include <sys/sunddi.h>
+#include <sys/strsubr.h> /* for hw cksum stuff */
+#include <sys/pattr.h> /* for hw cksum stuff */
+#ifdef MYRICOM_PRIV
+#include <netinet/in.h> /* for hw cksum stuff */
+#endif
+#include <netinet/ip.h> /* for hw cksum stuff */
+#include <netinet/ip6.h> /* for hw cksum stuff */
+#include <netinet/tcp.h> /* for hw cksum stuff */
+#include <netinet/udp.h> /* for hw cksum stuff */
+#include <sys/strsun.h>
+#include <inet/common.h>
+#include <inet/mi.h>
+#include <inet/nd.h>
+#include <sys/zmod.h>
+#include <sys/cpuvar.h>
+#include <sys/proc.h>
+#include <sys/callb.h>
+
+#include "myri10ge_mcp.h"
+#include "myri10ge_version.h"
+
+#define MYRI10GE_FW_OFFSET 1024*1024
+#define MYRI10GE_EEPROM_STRINGS_SIZE 256
+#define MYRI10GE_HIGHPART_TO_U32(X) \
+(sizeof (X) == 8) ? ((uint32_t)((uint64_t)(X) >> 32)) : (0)
+#define MYRI10GE_LOWPART_TO_U32(X) ((uint32_t)(X))
+
+#define MYRI10GE_DDI_REG_SET_32_BIT_MEMORY_SPACE 2
+#define MYRI10GE_DDI_REG_SET_64_BIT_MEMORY_SPACE 3
+
+/*
+ * Max descriptors a TSO send can use; worst case is every descriptor
+ * crosses a 2KB boundary, as do the headers
+ */
+
+#define MYRI10GE_MAX_SEND_DESC_TSO (2 + (65536 / 2048) * 2)
+
+#ifdef MYRICOM_PRIV
+#define VLAN_TAGSZ 4
+#endif
+
+#if defined DDI_INTR_IS_MSI_OR_MSIX
+#define MYRI10GE_USE_MSI 1
+#else
+#define MYRI10GE_USE_MSI 0
+#endif
+
+
+struct myri10ge_dma_stuff {
+ ddi_dma_handle_t handle;
+ ddi_acc_handle_t acc_handle;
+ uint32_t low;
+ uint32_t high;
+};
+
+typedef struct myri10ge_mblkq {
+ struct myri10ge_priv *mgp;
+ kmutex_t lock;
+ mblk_t *head;
+ mblk_t *tail;
+ unsigned long cnt;
+} myri10ge_mblkq_t;
+
+typedef struct {
+ mcp_slot_t *entry;
+ struct myri10ge_dma_stuff dma;
+ int cnt;
+ int idx;
+} myri10ge_rx_done_t;
+
+
+typedef struct
+{
+ uint32_t data0;
+ uint32_t data1;
+ uint32_t data2;
+} myri10ge_cmd_t;
+
+struct myri10ge_pci_saved_state {
+ uint32_t base[16];
+ uint32_t msi_addr_low;
+ uint32_t msi_addr_high;
+ uint16_t msi_data_32;
+ uint16_t msi_data_64;
+ uint16_t msi_ctrl;
+};
+
+struct myri10ge_jpool_entry;
+
+struct myri10ge_jpool_entry {
+ struct myri10ge_jpool_entry *next;
+ ddi_dma_handle_t dma_handle;
+ ddi_acc_handle_t acc_handle;
+ caddr_t buf;
+ struct myri10ge_slice_state *ss;
+ mcp_dma_addr_t dma; /* Kept in network byte order */
+ frtn_t free_func;
+};
+
+#define MYRI10GE_CPU_CACHE_SZ 64
+struct myri10ge_per_cpu_jpool {
+ struct myri10ge_jpool_entry *head;
+ uint8_t _pad[MYRI10GE_CPU_CACHE_SZ - sizeof (void *)];
+};
+
+#define MYRI10GE_MAX_CPUS 64
+#define MYRI10GE_MAX_CPU_MASK (64 - 1)
+
+struct myri10ge_jpool_stuff {
+ struct myri10ge_jpool_entry *head;
+ struct myri10ge_per_cpu_jpool cpu[MYRI10GE_MAX_CPUS];
+ kmutex_t mtx;
+ int num_alloc;
+ int low_water;
+};
+
+struct myri10ge_tx_ring_stats
+{
+ uint64_t multixmt;
+ uint64_t brdcstxmt;
+ uint64_t opackets;
+ uint64_t obytes;
+};
+
+struct myri10ge_rx_ring_stats
+{
+ uint64_t multircv;
+ uint64_t brdcstrcv;
+ uint64_t ipackets;
+ uint64_t ibytes;
+};
+
+struct myri10ge_tx_ring_entry_stats
+{
+ uint32_t obytes;
+ uint16_t opackets;
+ uint8_t brdcstxmt;
+ uint8_t multixmt;
+};
+
+struct myri10ge_tx_pkt_stats {
+ union {
+ uint64_t all;
+ struct myri10ge_tx_ring_entry_stats s;
+ } un;
+};
+
+#define ostat stat.un.s
+
+struct myri10ge_tx_dma_handle {
+ struct myri10ge_tx_dma_handle *next;
+ ddi_dma_handle_t h;
+};
+
+struct myri10ge_tx_dma_handle_head {
+ struct myri10ge_tx_dma_handle *head;
+ struct myri10ge_tx_dma_handle *tail;
+};
+
+struct myri10ge_rx_buffer_state {
+ caddr_t ptr;
+ struct myri10ge_jpool_entry *j;
+};
+
+struct myri10ge_tx_buffer_state {
+ mblk_t *m;
+ struct myri10ge_tx_dma_handle *handle;
+ struct myri10ge_tx_pkt_stats stat;
+};
+
+struct myri10ge_nic_stat {
+ struct kstat_named dma_force_physical;
+ struct kstat_named dma_read_bw_MBs;
+ struct kstat_named dma_write_bw_MBs;
+ struct kstat_named dma_read_write_bw_MBs;
+ struct kstat_named lanes;
+ struct kstat_named dropped_bad_crc32;
+ struct kstat_named dropped_bad_phy;
+ struct kstat_named dropped_link_error_or_filtered;
+ struct kstat_named dropped_link_overflow;
+ struct kstat_named dropped_multicast_filtered;
+ struct kstat_named dropped_no_big_buffer;
+ struct kstat_named dropped_no_small_buffer;
+ struct kstat_named dropped_overrun;
+ struct kstat_named dropped_pause;
+ struct kstat_named dropped_runt;
+ struct kstat_named dropped_unicast_filtered;
+ struct kstat_named link_changes;
+ struct kstat_named link_up;
+};
+
+struct myri10ge_slice_stat {
+ struct kstat_named lro_bad_csum;
+ struct kstat_named lro_flushed;
+ struct kstat_named lro_queued;
+ struct kstat_named rx_big;
+ struct kstat_named rx_bigbuf_firmware;
+ struct kstat_named rx_bigbuf_pool;
+ struct kstat_named rx_bigbuf_smalls;
+ struct kstat_named rx_copy;
+ struct kstat_named rx_small;
+ struct kstat_named rx_big_nobuf;
+ struct kstat_named rx_small_nobuf;
+ struct kstat_named tx_activate;
+ struct kstat_named tx_done;
+ struct kstat_named tx_handles_alloced;
+ struct kstat_named tx_req;
+ struct kstat_named xmit_err;
+ struct kstat_named xmit_lowbuf;
+ struct kstat_named xmit_lsobadflags;
+ struct kstat_named xmit_pullup;
+ struct kstat_named xmit_pullup_first;
+ struct kstat_named xmit_sched;
+ struct kstat_named xmit_stall;
+ struct kstat_named xmit_stall_early;
+ struct kstat_named xmit_stall_late;
+ struct kstat_named xmit_zero_len;
+};
+
+struct myri10ge_info {
+ struct kstat_named driver_version;
+ struct kstat_named firmware_version;
+ struct kstat_named firmware_name;
+ struct kstat_named interrupt_type;
+ struct kstat_named product_code;
+ struct kstat_named serial_number;
+};
+
+
+#define MYRI10GE_NIC_STAT_INC(field) \
+(((struct myri10ge_nic_stat *)mgp->ksp_stat->ks_data)->field.value.ul)++
+#define MYRI10GE_SLICE_STAT_INC(field) \
+(((struct myri10ge_slice_stat *)ss->ksp_stat->ks_data)->field.value.ul)++
+#define MYRI10GE_SLICE_STAT_ADD(field, val) \
+(((struct myri10ge_slice_stat *)ss->ksp_stat->ks_data)->field.value.ul) += val
+#define MYRI10GE_SLICE_STAT_DEC(field) \
+(((struct myri10ge_slice_stat *)ss->ksp_stat->ks_data)->field.value.ul)--
+#define MYRI10GE_ATOMIC_SLICE_STAT_INC(field) \
+atomic_add_long(&(((struct myri10ge_slice_stat *) \
+ ss->ksp_stat->ks_data)->field.value.ul), 1)
+#define MYRI10GE_ATOMIC_SLICE_STAT_DEC(field) \
+atomic_add_long(&(((struct myri10ge_slice_stat *) \
+ ss->ksp_stat->ks_data)->field.value.ul), -1)
+#define MYRI10GE_SLICE_STAT(field) \
+(((struct myri10ge_slice_stat *)ss->ksp_stat->ks_data)->field.value.ul)
+
+
+struct myri10ge_tx_copybuf
+{
+ caddr_t va;
+ int len;
+ struct myri10ge_dma_stuff dma;
+};
+
+typedef struct
+{
+ mcp_kreq_ether_recv_t *lanai; /* lanai ptr for recv ring */
+ mcp_kreq_ether_recv_t *shadow; /* host shadow of recv ring */
+ struct myri10ge_rx_buffer_state *info;
+ int cnt;
+ int alloc_fail;
+ int mask; /* number of rx slots -1 */
+ boolean_t polling;
+} myri10ge_rx_ring_t;
+
+typedef struct
+{
+ mcp_kreq_ether_send_t *lanai; /* lanai ptr for sendq */
+ char *go; /* doorbell to poll sendq */
+ char *stop; /* doorbell to !poll sendq */
+ struct myri10ge_tx_buffer_state *info;
+ struct myri10ge_tx_copybuf *cp;
+ int req; /* transmits submitted */
+ int mask; /* number of transmit slots -1 */
+ int done; /* transmits completed */
+ int pkt_done; /* packets completed */
+ int active;
+ uint32_t stall;
+ uint32_t stall_early;
+ uint32_t stall_late;
+ int sched;
+ kmutex_t lock;
+ struct myri10ge_tx_ring_stats stats;
+ int watchdog_req;
+ int watchdog_done;
+ unsigned long activate;
+ kmutex_t handle_lock;
+ struct myri10ge_tx_dma_handle *free_tx_handles;
+ mac_ring_handle_t rh;
+} myri10ge_tx_ring_t;
+
+struct lro_entry;
+
+struct lro_entry
+{
+ struct lro_entry *next;
+ mblk_t *m_head;
+ mblk_t *m_tail;
+ int timestamp;
+ struct ip *ip;
+ uint32_t tsval;
+ uint32_t tsecr;
+ uint32_t source_ip;
+ uint32_t dest_ip;
+ uint32_t next_seq;
+ uint32_t ack_seq;
+ uint32_t len;
+ uint32_t data_csum;
+ uint16_t window;
+ uint16_t source_port;
+ uint16_t dest_port;
+ uint16_t append_cnt;
+ uint16_t mss;
+ uint8_t flags;
+};
+
+struct myri10ge_mblk_list
+{
+ mblk_t *head;
+ mblk_t **tail;
+ int cnt;
+};
+
+struct myri10ge_priv;
+
+struct myri10ge_slice_state {
+ struct myri10ge_priv *mgp;
+ myri10ge_tx_ring_t tx; /* transmit ring */
+ myri10ge_rx_ring_t rx_small;
+ myri10ge_rx_ring_t rx_big;
+ myri10ge_rx_done_t rx_done;
+ struct myri10ge_jpool_stuff jpool;
+ struct myri10ge_rx_ring_stats rx_stats;
+ volatile uint32_t *irq_claim;
+ mcp_irq_data_t *fw_stats;
+ struct lro_entry *lro_active;
+ struct lro_entry *lro_free;
+ struct myri10ge_dma_stuff fw_stats_dma;
+ int jbufs_for_smalls;
+ struct myri10ge_jpool_entry *small_jpool;
+ int j_rx_cnt;
+ mac_resource_handle_t mrh;
+ kstat_t *ksp_stat;
+ mac_ring_handle_t rx_rh;
+ kmutex_t rx_lock;
+ kmutex_t poll_lock;
+ uint64_t rx_gen_num;
+ boolean_t rx_polling;
+ int rx_token;
+ int watchdog_rx_copy;
+};
+
+struct myri10ge_priv {
+ struct myri10ge_slice_state *ss;
+ int max_intr_slots;
+ int num_slices;
+ dev_info_t *dip;
+ mac_handle_t mh;
+ ddi_acc_handle_t io_handle;
+ int tx_boundary;
+ int watchdog_rx_pause;
+ kstat_t *ksp_stat;
+ kstat_t *ksp_info;
+ int running; /* running? */
+ int csum_flag; /* rx_csums? */
+ uint8_t mac_addr[6]; /* eeprom mac address */
+ volatile uint8_t *sram;
+ int sram_size;
+ unsigned long board_span;
+ unsigned long iomem_base;
+ volatile uint32_t *irq_deassert;
+ char *mac_addr_string;
+ mcp_cmd_response_t *cmd;
+ struct myri10ge_dma_stuff cmd_dma;
+ int msi_enabled;
+ int link_state;
+ int rdma_tags_available;
+ int intr_coal_delay;
+ volatile uint32_t *intr_coal_delay_ptr;
+ kmutex_t cmd_lock;
+ kmutex_t intrlock;
+ int down_cnt;
+ int watchdog_resets;
+ unsigned char *eth_z8e;
+ unsigned int eth_z8e_length;
+ ddi_iblock_cookie_t icookie;
+ ddi_intr_handle_t *htable;
+ int intr_size;
+ int intr_cnt;
+ int intr_cap;
+ unsigned int intr_pri;
+ int ddi_intr_type;
+ int pause;
+ timeout_id_t timer_id;
+ clock_t timer_ticks;
+ int vso;
+ uint32_t mcp_index;
+ char fw_version[128];
+ char name[32];
+ char *fw_name;
+ char *intr_type;
+ char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
+ char *sn_str;
+ char *pc_str;
+ uint32_t read_dma;
+ uint32_t write_dma;
+ uint32_t read_write_dma;
+ uint32_t pcie_link_width;
+ int max_read_request_4k;
+ caddr_t nd_head;
+ struct myri10ge_priv *next;
+ uint_t refcnt;
+ int reg_set;
+ int features;
+ struct myri10ge_pci_saved_state pci_saved_state;
+ uint32_t *toeplitz_hash_table;
+ uint32_t rss_key[8];
+ ddi_acc_handle_t cfg_hdl;
+ int macaddr_cnt;
+};
+
+/* features bitmask */
+#define MYRI10GE_TSO 1
+
+#if defined(__GNUC__)
+#define likely(x) __builtin_expect((x), 1)
+#define unlikely(x) __builtin_expect((x), 0)
+#else
+#define likely(x) (x)
+#define unlikely(x) (x)
+#endif /* defined(__GNUC__) */
+
+#define mb membar_producer
+
+struct myri10ge_priv *myri10ge_get_instance(uint_t unit);
+void myri10ge_put_instance(struct myri10ge_priv *);
+int myri10ge_send_cmd(struct myri10ge_priv *mgp, uint32_t cmd,
+ myri10ge_cmd_t *data);
+caddr_t myri10ge_dma_alloc(dev_info_t *dip, size_t len,
+ ddi_dma_attr_t *attr, ddi_device_acc_attr_t *accattr,
+ uint_t alloc_flags, int bind_flags, struct myri10ge_dma_stuff *dma,
+ int warn, int (*waitfp)(caddr_t));
+void myri10ge_dma_free(struct myri10ge_dma_stuff *dma);
+
+void myri10ge_lro_flush(struct myri10ge_slice_state *ss,
+ struct lro_entry *lro, struct myri10ge_mblk_list *mbl);
+int myri10ge_lro_rx(struct myri10ge_slice_state *ss, mblk_t *m_head,
+ uint32_t csum, struct myri10ge_mblk_list *mbl);
+void myri10ge_mbl_append(struct myri10ge_slice_state *ss,
+ struct myri10ge_mblk_list *mbl, mblk_t *mp);
+uint16_t myri10ge_csum_generic(uint16_t *raw, int len);
+extern int myri10ge_lro_max_aggr;
+extern int myri10ge_mtu;
+
+#ifndef ETHERNET_HEADER_SIZE
+#define ETHERNET_HEADER_SIZE 14
+#endif
+
+#define MYRI10GE_TOEPLITZ_HASH (MXGEFW_RSS_HASH_TYPE_TCP_IPV4|\
+ MXGEFW_RSS_HASH_TYPE_IPV4)
+#define MYRI10GE_POLL_NULL INT_MAX
+
+/*
+ * This file uses MyriGE driver indentation.
+ *
+ * Local Variables:
+ * c-file-style:"sun"
+ * tab-width:8
+ * End:
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MYRI10GE_VAR_H */
diff --git a/usr/src/uts/common/io/myri10ge/drv/myri10ge_version.h b/usr/src/uts/common/io/myri10ge/drv/myri10ge_version.h
new file mode 100644
index 0000000000..daefcb37c2
--- /dev/null
+++ b/usr/src/uts/common/io/myri10ge/drv/myri10ge_version.h
@@ -0,0 +1,45 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007-2009 Myricom, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef MYRI10GE_VERSION_H
+#define MYRI10GE_VERSION_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MYRI10GE_MAJOR_VERSION 1
+#define MYRI10GE_MINOR_VERSION 4
+#define MYRI10GE_TEENY_VERSION 5
+#define MYRI10GE_VERSION_SUFFIX "gldv3"
+#define MYRI10GE_VERSION_STR "1.4.5gldv3"
+#define MYRI10GE_SHORT_VERSION_STR "1.4.5"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MYRI10GE_VERSION_H */
diff --git a/usr/src/uts/common/io/myri10ge/firmware/mcp_gen_header.h b/usr/src/uts/common/io/myri10ge/firmware/mcp_gen_header.h
new file mode 100644
index 0000000000..7ced84ec04
--- /dev/null
+++ b/usr/src/uts/common/io/myri10ge/firmware/mcp_gen_header.h
@@ -0,0 +1,121 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007-2009 Myricom, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _mcp_gen_header_h
+#define _mcp_gen_header_h
+
+/**
+ @file
+ This file define a standard header used as a first entry point to
+ exchange information between firmware/driver and driver.
+
+ The header structure can be anywhere in the mcp. It will usually be in
+ the .data section, because some fields needs to be initialized at
+ compile time.
+
+ The 32bit word at offset MX_HEADER_PTR_OFFSET in the mcp must
+ contains the location of the header.
+
+ Typically a MCP will start with the following:
+ @code
+ .text
+ .space 52 ! to help catch MEMORY_INT errors
+ bt start ! jump to real code
+ nop
+ .long _gen_mcp_header
+ @endcode
+
+ The source will have a definition like:
+ @code
+ mcp_gen_header_t gen_mcp_header = {
+ .header_length = sizeof(mcp_gen_header_t),
+ .mcp_type = MCP_TYPE_XXX,
+ .version = "something $Id: mcp_gen_header.h,v 1.9 2009-02-27 16:29:36 loic Exp $",
+ .mcp_globals = (unsigned)&Globals
+ };
+ @endcode
+ In most case using the convenience MCP_GEN_HEADER_DECL() macro is simpler than
+ doing a full manual declaration.
+
+*/
+
+
+#define MCP_HEADER_PTR_OFFSET 0x3c
+
+#define MCP_TYPE_MX 0x4d582020 /* "MX " */
+#define MCP_TYPE_PCIE 0x70636965 /* "PCIE" pcie-only MCP */
+#define MCP_TYPE_ETH 0x45544820 /* "ETH " */
+#define MCP_TYPE_MCP0 0x4d435030 /* "MCP0" */
+#define MCP_TYPE_DFLT 0x20202020 /* " " */
+#define MCP_TYPE_ETHZ 0x4554485a /* "ETHZ" */
+
+struct mcp_gen_header {
+ /* the first 4 fields are filled at compile time */
+ unsigned header_length;
+ unsigned mcp_type;
+ char version[128];
+ unsigned mcp_private; /* pointer to mcp-type specific structure */
+
+ /* filled by the MCP at run-time */
+ unsigned sram_size;
+ unsigned string_specs; /* either the original STRING_SPECS or a superset */
+ unsigned string_specs_len;
+
+ /* Fields above this comment are guaranteed to be present.
+
+ Fields below this comment are extensions added in later versions
+ of this struct, drivers should compare the header_length against
+ offsetof(field) to check wether a given MCP implements them.
+
+ Never remove any field. Keep everything naturally align.
+ */
+
+ /* Specifies if the running mcp is mcp0, 1, or 2. */
+ unsigned char mcp_index;
+ unsigned char disable_rabbit;
+ unsigned char unaligned_tlp;
+ unsigned char pcie_link_algo;
+ unsigned counters_addr;
+ unsigned copy_block_info; /* for small mcps loaded with "lload -d" */
+ unsigned short handoff_id_major; /* must be equal */
+ unsigned short handoff_id_caps; /* bitfield: new mcp must have superset */
+ unsigned msix_table_addr; /* start address of msix table in firmware */
+ unsigned bss_addr; /* start of bss */
+ unsigned features;
+ unsigned ee_hdr_addr;
+ /* 8 */
+};
+typedef struct mcp_gen_header mcp_gen_header_t;
+
+struct zmcp_info {
+ unsigned info_len;
+ unsigned zmcp_addr;
+ unsigned zmcp_len;
+ unsigned mcp_edata;
+};
+
+
+#endif /* _mcp_gen_header_h */
diff --git a/usr/src/uts/common/io/myri10ge/firmware/myri10ge_mcp.h b/usr/src/uts/common/io/myri10ge/firmware/myri10ge_mcp.h
new file mode 100644
index 0000000000..2d0cd6b4b0
--- /dev/null
+++ b/usr/src/uts/common/io/myri10ge/firmware/myri10ge_mcp.h
@@ -0,0 +1,520 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007-2009 Myricom, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _myri10ge_mcp_h
+#define _myri10ge_mcp_h
+
+#define MXGEFW_VERSION_MAJOR 1
+#define MXGEFW_VERSION_MINOR 4
+
+#ifdef MXGEFW
+#ifndef _stdint_h_
+typedef signed char int8_t;
+typedef signed short int16_t;
+typedef signed int int32_t;
+typedef signed long long int64_t;
+typedef unsigned char uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int uint32_t;
+typedef unsigned long long uint64_t;
+#endif
+#endif
+
+/* 8 Bytes */
+struct mcp_dma_addr {
+ uint32_t high;
+ uint32_t low;
+};
+typedef struct mcp_dma_addr mcp_dma_addr_t;
+
+/* 4 Bytes */
+struct mcp_slot {
+ uint16_t checksum;
+ uint16_t length;
+};
+typedef struct mcp_slot mcp_slot_t;
+
+#ifdef MXGEFW_NDIS
+/* 8-byte descriptor, exclusively used by NDIS drivers. */
+struct mcp_slot_8 {
+ /* Place hash value at the top so it gets written before length.
+ * The driver polls length.
+ */
+ uint32_t hash;
+ uint16_t checksum;
+ uint16_t length;
+};
+typedef struct mcp_slot_8 mcp_slot_8_t;
+
+/* Two bits of length in mcp_slot are used to indicate hash type. */
+#define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */
+#define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */
+#define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */
+#define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */
+#endif
+
+/* 64 Bytes */
+struct mcp_cmd {
+ uint32_t cmd;
+ uint32_t data0; /* will be low portion if data > 32 bits */
+ /* 8 */
+ uint32_t data1; /* will be high portion if data > 32 bits */
+ uint32_t data2; /* currently unused.. */
+ /* 16 */
+ struct mcp_dma_addr response_addr;
+ /* 24 */
+ uint8_t pad[40];
+};
+typedef struct mcp_cmd mcp_cmd_t;
+
+/* 8 Bytes */
+struct mcp_cmd_response {
+ uint32_t data;
+ uint32_t result;
+};
+typedef struct mcp_cmd_response mcp_cmd_response_t;
+
+
+
+/*
+ flags used in mcp_kreq_ether_send_t:
+
+ The SMALL flag is only needed in the first segment. It is raised
+ for packets that are total less or equal 512 bytes.
+
+ The CKSUM flag must be set in all segments.
+
+ The PADDED flags is set if the packet needs to be padded, and it
+ must be set for all segments.
+
+ The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
+ length of all previous segments was odd.
+*/
+
+
+#define MXGEFW_FLAGS_SMALL 0x1
+#define MXGEFW_FLAGS_TSO_HDR 0x1
+#define MXGEFW_FLAGS_FIRST 0x2
+#define MXGEFW_FLAGS_ALIGN_ODD 0x4
+#define MXGEFW_FLAGS_CKSUM 0x8
+#define MXGEFW_FLAGS_TSO_LAST 0x8
+#define MXGEFW_FLAGS_NO_TSO 0x10
+#define MXGEFW_FLAGS_TSO_CHOP 0x10
+#define MXGEFW_FLAGS_TSO_PLD 0x20
+
+#define MXGEFW_SEND_SMALL_SIZE 1520
+#define MXGEFW_MAX_MTU 9400
+
+union mcp_pso_or_cumlen {
+ uint16_t pseudo_hdr_offset;
+ uint16_t cum_len;
+};
+typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t;
+
+#define MXGEFW_MAX_SEND_DESC 12
+#define MXGEFW_PAD 2
+
+/* 16 Bytes */
+struct mcp_kreq_ether_send {
+ uint32_t addr_high;
+ uint32_t addr_low;
+ uint16_t pseudo_hdr_offset;
+ uint16_t length;
+ uint8_t pad;
+ uint8_t rdma_count;
+ uint8_t cksum_offset; /* where to start computing cksum */
+ uint8_t flags; /* as defined above */
+};
+typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t;
+
+/* 8 Bytes */
+struct mcp_kreq_ether_recv {
+ uint32_t addr_high;
+ uint32_t addr_low;
+};
+typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t;
+
+
+/* Commands */
+
+#define MXGEFW_BOOT_HANDOFF 0xfc0000
+#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0
+
+#define MXGEFW_ETH_CMD 0xf80000
+#define MXGEFW_ETH_SEND_4 0x200000
+#define MXGEFW_ETH_SEND_1 0x240000
+#define MXGEFW_ETH_SEND_2 0x280000
+#define MXGEFW_ETH_SEND_3 0x2c0000
+#define MXGEFW_ETH_RECV_SMALL 0x300000
+#define MXGEFW_ETH_RECV_BIG 0x340000
+#define MXGEFW_ETH_SEND_GO 0x380000
+#define MXGEFW_ETH_SEND_STOP 0x3C0000
+
+#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000))
+#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
+
+enum myri10ge_mcp_cmd_type {
+ MXGEFW_CMD_NONE = 0,
+ /* Reset the mcp, it is left in a safe state, waiting
+ for the driver to set all its parameters */
+ MXGEFW_CMD_RESET = 1,
+
+ /* get the version number of the current firmware..
+ (may be available in the eeprom strings..? */
+ MXGEFW_GET_MCP_VERSION = 2,
+
+
+ /* Parameters which must be set by the driver before it can
+ issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
+ MXGEFW_CMD_RESET is issued */
+
+ MXGEFW_CMD_SET_INTRQ_DMA = 3,
+ /* data0 = LSW of the host address
+ * data1 = MSW of the host address
+ * data2 = slice number if multiple slices are used
+ */
+
+ MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */
+ MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */
+
+
+ /* Parameters which refer to lanai SRAM addresses where the
+ driver must issue PIO writes for various things */
+
+ MXGEFW_CMD_GET_SEND_OFFSET = 6,
+ MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7,
+ MXGEFW_CMD_GET_BIG_RX_OFFSET = 8,
+ /* data0 = slice number if multiple slices are used */
+
+ MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9,
+ MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10,
+
+ /* Parameters which refer to rings stored on the MCP,
+ and whose size is controlled by the mcp */
+
+ MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */
+ MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */
+
+ /* Parameters which refer to rings stored in the host,
+ and whose size is controlled by the host. Note that
+ all must be physically contiguous and must contain
+ a power of 2 number of entries. */
+
+ MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */
+#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31)
+
+ /* command to bring ethernet interface up. Above parameters
+ (plus mtu & mac address) must have been exchanged prior
+ to issuing this command */
+ MXGEFW_CMD_ETHERNET_UP = 14,
+
+ /* command to bring ethernet interface down. No further sends
+ or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
+ is issued, and all interrupt queues must be flushed prior
+ to ack'ing this command */
+
+ MXGEFW_CMD_ETHERNET_DOWN = 15,
+
+ /* commands the driver may issue live, without resetting
+ the nic. Note that increasing the mtu "live" should
+ only be done if the driver has already supplied buffers
+ sufficiently large to handle the new mtu. Decreasing
+ the mtu live is safe */
+
+ MXGEFW_CMD_SET_MTU = 16,
+ MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */
+ MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */
+ MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */
+
+ MXGEFW_ENABLE_PROMISC = 20,
+ MXGEFW_DISABLE_PROMISC = 21,
+ MXGEFW_SET_MAC_ADDRESS = 22,
+
+ MXGEFW_ENABLE_FLOW_CONTROL = 23,
+ MXGEFW_DISABLE_FLOW_CONTROL = 24,
+
+ /* do a DMA test
+ data0,data1 = DMA address
+ data2 = RDMA length (MSH), WDMA length (LSH)
+ command return data = repetitions (MSH), 0.5-ms ticks (LSH)
+ */
+ MXGEFW_DMA_TEST = 25,
+
+ MXGEFW_ENABLE_ALLMULTI = 26,
+ MXGEFW_DISABLE_ALLMULTI = 27,
+
+ /* returns MXGEFW_CMD_ERROR_MULTICAST
+ if there is no room in the cache
+ data0,MSH(data1) = multicast group address */
+ MXGEFW_JOIN_MULTICAST_GROUP = 28,
+ /* returns MXGEFW_CMD_ERROR_MULTICAST
+ if the address is not in the cache,
+ or is equal to FF-FF-FF-FF-FF-FF
+ data0,MSH(data1) = multicast group address */
+ MXGEFW_LEAVE_MULTICAST_GROUP = 29,
+ MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30,
+
+ MXGEFW_CMD_SET_STATS_DMA_V2 = 31,
+ /* data0, data1 = bus addr,
+ * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
+ * adding new stuff to mcp_irq_data without changing the ABI
+ *
+ * If multiple slices are used, data2 contains both the size of the
+ * structure (in the lower 16 bits) and the slice number
+ * (in the upper 16 bits).
+ */
+
+ MXGEFW_CMD_UNALIGNED_TEST = 32,
+ /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
+ chipset */
+
+ MXGEFW_CMD_UNALIGNED_STATUS = 33,
+ /* return data = boolean, true if the chipset is known to be unaligned */
+
+ MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34,
+ /* data0 = number of big buffers to use. It must be 0 or a power of 2.
+ * 0 indicates that the NIC consumes as many buffers as they are required
+ * for packet. This is the default behavior.
+ * A power of 2 number indicates that the NIC always uses the specified
+ * number of buffers for each big receive packet.
+ * It is up to the driver to ensure that this value is big enough for
+ * the NIC to be able to receive maximum-sized packets.
+ */
+
+ MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35,
+ MXGEFW_CMD_ENABLE_RSS_QUEUES = 36,
+ /* data0 = number of slices n (0, 1, ..., n-1) to enable
+ * data1 = interrupt mode | use of multiple transmit queues.
+ * 0=share one INTx/MSI.
+ * 1=use one MSI-X per queue.
+ * If all queues share one interrupt, the driver must have set
+ * RSS_SHARED_INTERRUPT_DMA before enabling queues.
+ * 2=enable both receive and send queues.
+ * Without this bit set, only one send queue (slice 0's send queue)
+ * is enabled. The receive queues are always enabled.
+ */
+#define MXGEFW_SLICE_INTR_MODE_SHARED 0x0
+#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1
+#define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2
+
+ MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37,
+ MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38,
+ /* data0, data1 = bus address lsw, msw */
+ MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39,
+ /* get the offset of the indirection table */
+ MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40,
+ /* set the size of the indirection table */
+ MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41,
+ /* get the offset of the secret key */
+ MXGEFW_CMD_RSS_KEY_UPDATED = 42,
+ /* tell nic that the secret key's been updated */
+ MXGEFW_CMD_SET_RSS_ENABLE = 43,
+ /* data0 = enable/disable rss
+ * 0: disable rss. nic does not distribute receive packets.
+ * 1: enable rss. nic distributes receive packets among queues.
+ * data1 = hash type
+ * 1: IPV4 (required by RSS)
+ * 2: TCP_IPV4 (required by RSS)
+ * 3: IPV4 | TCP_IPV4 (required by RSS)
+ * 4: source port
+ * 5: source port + destination port
+ */
+#define MXGEFW_RSS_HASH_TYPE_IPV4 0x1
+#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2
+#define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4
+#define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5
+#define MXGEFW_RSS_HASH_TYPE_MAX 0x5
+
+ MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44,
+ /* Return data = the max. size of the entire headers of a IPv6 TSO packet.
+ * If the header size of a IPv6 TSO packet is larger than the specified
+ * value, then the driver must not use TSO.
+ * This size restriction only applies to IPv6 TSO.
+ * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC
+ * always has enough header buffer to store maximum-sized headers.
+ */
+
+ MXGEFW_CMD_SET_TSO_MODE = 45,
+ /* data0 = TSO mode.
+ * 0: Linux/FreeBSD style (NIC default)
+ * 1: NDIS/NetBSD style
+ */
+#define MXGEFW_TSO_MODE_LINUX 0
+#define MXGEFW_TSO_MODE_NDIS 1
+
+ MXGEFW_CMD_MDIO_READ = 46,
+ /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
+ MXGEFW_CMD_MDIO_WRITE = 47,
+ /* data0 = dev_addr, data1 = register/addr, data2 = value */
+
+ MXGEFW_CMD_I2C_READ = 48,
+ /* Starts to get a fresh copy of one byte or of the module i2c table, the
+ * obtained data is cached inside the xaui-xfi chip :
+ * data0 : 0 => get one byte, 1=> get 256 bytes
+ * data1 : If data0 == 0: location to refresh
+ * bit 7:0 register location
+ * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1)
+ * bit 23:16 is the i2c bus number (for multi-port NICs)
+ * If data0 == 1: unused
+ * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
+ * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts
+ * will return MXGEFW_CMD_ERROR_BUSY
+ */
+ MXGEFW_CMD_I2C_BYTE = 49,
+ /* Return the last obtained copy of a given byte in the xfp i2c table
+ * (copy cached during the last relevant MXGEFW_CMD_I2C_READ)
+ * data0 : index of the desired table entry
+ * Return data = the byte stored at the requested index in the table
+ */
+
+ MXGEFW_CMD_GET_VPUMP_OFFSET = 50,
+ /* Return data = NIC memory offset of mcp_vpump_public_global */
+ MXGEFW_CMD_RESET_VPUMP = 51,
+ /* Resets the VPUMP state */
+
+ MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52,
+ /* data0 = mcp_slot type to use.
+ * 0 = the default 4B mcp_slot
+ * 1 = 8B mcp_slot_8
+ */
+#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0
+#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1
+
+ MXGEFW_CMD_SET_THROTTLE_FACTOR = 53,
+ /* set the throttle factor for ethp_z8e
+ data0 = throttle_factor
+ throttle_factor = 256 * pcie-raw-speed / tx_speed
+ tx_speed = 256 * pcie-raw-speed / throttle_factor
+
+ For PCI-E x8: pcie-raw-speed == 16Gb/s
+ For PCI-E x4: pcie-raw-speed == 8Gb/s
+
+ ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
+ ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
+
+ with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
+ with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
+ */
+
+ MXGEFW_CMD_VPUMP_UP = 54,
+ /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
+ MXGEFW_CMD_GET_VPUMP_CLK = 55,
+ /* Get the lanai clock */
+
+ MXGEFW_CMD_GET_DCA_OFFSET = 56,
+ /* offset of dca control for WDMAs */
+
+ /* VMWare NetQueue commands */
+ MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57,
+ MXGEFW_CMD_NETQ_ADD_FILTER = 58,
+ /* data0 = filter_id << 16 | queue << 8 | type */
+ /* data1 = MS4 of MAC Addr */
+ /* data2 = LS2_MAC << 16 | VLAN_tag */
+ MXGEFW_CMD_NETQ_DEL_FILTER = 59,
+ /* data0 = filter_id */
+ MXGEFW_CMD_NETQ_QUERY1 = 60,
+ MXGEFW_CMD_NETQ_QUERY2 = 61,
+ MXGEFW_CMD_NETQ_QUERY3 = 62,
+ MXGEFW_CMD_NETQ_QUERY4 = 63,
+
+ MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64,
+ /* When set, small receive buffers can cross page boundaries.
+ * Both small and big receive buffers may start at any address.
+ * This option has performance implications, so use with caution.
+ */
+};
+typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t;
+
+
+enum myri10ge_mcp_cmd_status {
+ MXGEFW_CMD_OK = 0,
+ MXGEFW_CMD_UNKNOWN = 1,
+ MXGEFW_CMD_ERROR_RANGE = 2,
+ MXGEFW_CMD_ERROR_BUSY = 3,
+ MXGEFW_CMD_ERROR_EMPTY = 4,
+ MXGEFW_CMD_ERROR_CLOSED = 5,
+ MXGEFW_CMD_ERROR_HASH_ERROR = 6,
+ MXGEFW_CMD_ERROR_BAD_PORT = 7,
+ MXGEFW_CMD_ERROR_RESOURCES = 8,
+ MXGEFW_CMD_ERROR_MULTICAST = 9,
+ MXGEFW_CMD_ERROR_UNALIGNED = 10,
+ MXGEFW_CMD_ERROR_NO_MDIO = 11,
+ MXGEFW_CMD_ERROR_I2C_FAILURE = 12,
+ MXGEFW_CMD_ERROR_I2C_ABSENT = 13,
+ MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14
+};
+typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t;
+
+
+#define MXGEFW_OLD_IRQ_DATA_LEN 40
+
+struct mcp_irq_data {
+ /* add new counters at the beginning */
+ uint32_t future_use[1];
+ uint32_t dropped_pause;
+ uint32_t dropped_unicast_filtered;
+ uint32_t dropped_bad_crc32;
+ uint32_t dropped_bad_phy;
+ uint32_t dropped_multicast_filtered;
+/* 40 Bytes */
+ uint32_t send_done_count;
+
+#define MXGEFW_LINK_DOWN 0
+#define MXGEFW_LINK_UP 1
+#define MXGEFW_LINK_MYRINET 2
+#define MXGEFW_LINK_UNKNOWN 3
+ uint32_t link_up;
+ uint32_t dropped_link_overflow;
+ uint32_t dropped_link_error_or_filtered;
+ uint32_t dropped_runt;
+ uint32_t dropped_overrun;
+ uint32_t dropped_no_small_buffer;
+ uint32_t dropped_no_big_buffer;
+ uint32_t rdma_tags_available;
+
+ uint8_t tx_stopped;
+ uint8_t link_down;
+ uint8_t stats_updated;
+ uint8_t valid;
+};
+typedef struct mcp_irq_data mcp_irq_data_t;
+
+#ifdef MXGEFW_NDIS
+/* Exclusively used by NDIS drivers */
+struct mcp_rss_shared_interrupt {
+ uint8_t pad[2];
+ uint8_t queue;
+ uint8_t valid;
+};
+#endif
+
+/* definitions for NETQ filter type */
+#define MXGEFW_NETQ_FILTERTYPE_NONE 0
+#define MXGEFW_NETQ_FILTERTYPE_MACADDR 1
+#define MXGEFW_NETQ_FILTERTYPE_VLAN 2
+#define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3
+
+#endif /* _myri10ge_mcp_h */
diff --git a/usr/src/uts/common/io/myri10ge/firmware/rss_eth_z8e.h b/usr/src/uts/common/io/myri10ge/firmware/rss_eth_z8e.h
new file mode 100644
index 0000000000..0034c829c7
--- /dev/null
+++ b/usr/src/uts/common/io/myri10ge/firmware/rss_eth_z8e.h
@@ -0,0 +1,9403 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007-2009 Myricom, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
+
+const unsigned int rss_eth_z8e_uncompressed_length = 544748 ;
+const unsigned int rss_eth_z8e_length = 149961 ;
+const unsigned char rss_eth_z8e[149961 + 1] =
+ "\x78\x9c\xec\xbd\x7f\x78\x54\xd5\xb5\x3f\xbc\xe6\xcc\x00\x91\x06"
+ "\x66\x12\x23\x1d\x11\x75\x50\x68\xa3\xf2\x23\x2a\x5a\xb4\xa0\x51"
+ "\xa2\x85\x4a\x20\x28\xd8\xb4\xa2\x01\x0d\x18\x34\x42\x48\x22\x04"
+ "\x0c\x99\x30\xa0\x05\x1b\xc8\x24\xa6\x36\x4a\x48\x62\x8b\x2d\xb6"
+ "\xa8\xb4\xa5\xbd\xb9\xbd\x58\xc7\x12\xdf\x87\xde\x26\x99\xd8\x97"
+ "\xbe\x2f\xb7\x2f\xde\x0e\xdc\x48\x23\xdf\x00\x23\x19\xc8\x98\xcc"
+ "\xcc\xfe\x7e\xd6\xde\xe7\x24\x33\xc3\x04\xe5\xf6\x3e\xef\xf7\x9f"
+ "\xe6\x79\x26\xe7\x9c\x7d\xf6\x5e\x7b\xed\xb5\xd7\x5e\x7b\xad\xbd"
+ "\xd7\x5e\x87\xe8\x1f\xf8\xb3\x8c\xdb\xf6\x8f\x14\xff\xe7\xdf\x3f"
+ "\xff\xfe\xf9\xf7\xcf\xbf\x7f\xfe\xfd\xf3\xef\x9f\x7f\xff\x67\xfe"
+ "\xce\x69\x16\xfa\x83\x9b\xa8\xcf\x95\x64\xf7\xd1\xd9\xf2\x1f\xbd"
+ "\x22\x42\x48\x36\xf9\x28\xc9\xce\x57\xfd\x47\xb5\x48\xd7\xdc\x94"
+ "\x74\x83\x8d\x92\xe7\xec\x26\xaa\x1b\x27\x7a\x5e\x79\x55\xf8\xb7"
+ "\xbc\x2a\x7a\xb2\xde\x24\x6a\x9d\x44\xf4\xca\x38\x11\x00\x9c\xa5"
+ "\x3e\xfa\x6e\x17\xc3\xd9\x82\x67\x7e\xbf\x75\x9c\xf0\x23\xbd\xd4"
+ "\x47\xdf\x5b\xca\xe9\x9b\xc7\x01\x56\x1a\x91\xeb\x55\x11\x8c\x82"
+ "\x9b\xc4\xe5\x19\x66\xd6\x44\x89\xcf\x9e\x38\x38\x0c\xa3\x05\x30"
+ "\x8e\x5c\x02\x46\xb2\x81\x57\x40\x23\x13\xc3\xeb\x75\x91\x3d\xe0"
+ "\xf2\x5c\x85\xb2\x01\xb4\x29\x9d\xcb\x56\x23\x8f\x70\x91\xb9\xb5"
+ "\x2c\x44\x8e\x1b\xc8\x74\x92\xae\xf8\x14\x57\x0d\xd7\x8f\xb9\xbd"
+ "\x5b\x54\xb9\x49\x0c\x03\x65\x4d\x7d\xae\x2b\x32\x06\xcb\x02\xb6"
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+ "\x21\x47\xbd\x63\x45\x75\xcb\x52\xa5\x7f\xe3\xe3\xd5\x71\xe1\xb6"
+ "\x2d\x74\x03\xd4\xd3\xac\x6e\xe3\xd3\x90\x56\x28\xd6\x10\x58\xdf"
+ "\x32\x5e\x26\x47\xd9\x16\xdf\xb6\xf1\x76\x98\xdc\xd8\x0e\x9c\x13"
+ "\x41\xfd\x7b\x30\xee\xc1\xbd\xd0\xc0\x6e\xa6\x95\x75\xeb\x7c\xf8"
+ "\xc6\xb3\xeb\xd5\xf1\x95\x5c\x8c\xbe\x52\xcc\x3d\x6b\x20\xde\xb1"
+ "\xab\xd7\x62\x6e\xf9\xc1\x2c\x4b\xd6\xb2\x05\x4b\xb2\xe7\x4f\xb1"
+ "\x2c\x58\xb2\x20\x7b\xc1\xdc\x45\x0b\x56\xcd\xcd\x5e\xb0\x74\xc9"
+ "\xf8\xc5\x73\x1f\x58\x70\xbf\x65\xe5\xdc\xe5\x96\xe4\x9c\x71\x39"
+ "\x91\xc4\x4b\x7a\xb5\x65\xee\xf2\xe5\x0f\x2f\x9e\x97\x61\x59\xb2"
+ "\xe0\xfe\x09\xcb\xe6\x2d\x9f\x97\x6d\x99\xbb\x6c\xe9\xc3\x4b\x32"
+ "\x2c\xe3\x32\x26\x8e\x4b\xbe\x32\x23\x52\xbd\x86\x36\xc6\x48\x9a"
+ "\x3d\x5f\x35\x35\x15\x7e\x45\xf4\x06\x5d\xd6\x32\x43\xce\x82\x25"
+ "\x7c\xdd\x2e\xe1\x9e\x49\xc5\x24\x0b\xf7\x58\xc7\x3d\x70\x69\x51"
+ "\x7c\x16\x5c\x65\xa4\x83\x76\x5a\xca\x70\x9f\xf5\x04\x3a\xa2\xb5"
+ "\x28\xc1\xe2\x94\x87\xe9\xd9\xbe\xb4\x90\x0e\x6d\x1b\x41\xbf\xaa"
+ "\x69\x82\x98\x2d\x0b\x9f\xf9\x2e\xfb\x8a\x98\xec\x2b\x88\x0c\x67"
+ "\x14\x9c\x46\xdc\x83\x1d\xca\xcc\x76\xca\x43\xb2\xf8\xba\x68\x82"
+ "\xdb\x15\x7b\x55\x3e\xb5\x5f\x95\xcf\x71\x49\x38\xad\xac\x49\xdf"
+ "\xf6\x38\xb9\x0d\xf5\xf3\x88\x9c\xc0\xd6\xb2\x1f\x03\x5d\xc6\x35"
+ "\xd9\x96\x57\xae\x4b\x81\x78\xf0\xb0\x63\x18\xcb\x3b\xed\x96\x48"
+ "\x14\xc8\x25\xef\x5b\x93\x4c\x36\x41\x5d\xcb\xcd\x94\x42\x1d\x95"
+ "\xca\x7a\x1a\xb4\xc1\x08\x6d\x39\x24\xda\xb1\x95\xb5\x63\x0b\x4d"
+ "\x2c\x8e\x03\xf9\x8a\x98\x3c\x47\x95\x36\x80\xdc\x87\x40\xa6\x54"
+ "\x90\xd3\x88\x72\x05\x5a\xeb\xc3\xf5\xae\x63\xf2\x90\x09\x9e\x15"
+ "\xd0\x6f\xa3\xf8\x5e\x4a\x85\xdb\xb9\xfd\x41\xbb\x32\xca\xe0\x73"
+ "\xc1\x19\x12\xf5\x34\xee\xdd\xbd\x7e\x34\x7d\xc7\xdd\x49\xea\x33"
+ "\x0f\x11\xc3\x23\xd4\x45\x5f\x6a\x6a\xe2\x6d\x1a\x92\x86\xbe\xe1"
+ "\x0f\x0f\x1e\x92\xb1\x4d\x30\x56\x44\x95\x9d\xe9\x71\x6d\x51\xde"
+ "\x94\x40\xdd\x74\xab\x3a\xe6\x1a\xf2\x1a\xf6\x09\xc6\x5b\x2d\x30"
+ "\x4e\xb5\x16\x0d\xd9\x09\x75\x13\x11\x1b\xbb\x69\xc7\x1c\x55\x2c"
+ "\x35\x04\xf5\xcc\xdd\x03\x6f\xbd\xc2\x1b\xf7\x04\xc7\x32\x1c\x7f"
+ "\xf3\x04\x28\xe3\xf2\xf2\x37\xeb\xb5\xfc\x91\x27\x7c\x76\x29\xf5"
+ "\xf0\x79\xf8\x10\x8c\x09\x5c\xa0\xcb\xae\x1e\xea\x4b\x2c\xda\x42"
+ "\x1b\xeb\x21\xbd\xf0\x2c\x91\x81\xb6\xb1\x6c\x0b\xe3\x9f\xe9\x94"
+ "\xe3\x6b\x91\xff\x63\x09\x84\xe4\x03\x4d\x4b\xd1\x10\x82\xeb\xbb"
+ "\x90\x07\xf6\x1f\xd6\xa6\x5d\xb7\x16\xfa\x7c\xb5\x46\x9f\x53\x8a"
+ "\x30\x26\x2c\x06\xfe\xa0\x43\x85\x5f\x12\x9c\x6b\xd7\x4e\x2c\x26"
+ "\x49\x58\x0f\x7c\x6e\xc0\xf5\x10\xe0\x79\x48\xa9\x8f\x82\xfe\x17"
+ "\x78\xf8\x1a\x8c\xd0\xad\xf1\xf5\x39\x4d\xb8\xd7\x02\xdd\x07\xfe"
+ "\x1d\x65\x44\x1d\x6b\x2d\x1a\x1a\xa5\xe8\x14\xe8\x7a\x23\xd3\x2b"
+ "\x13\x49\xa2\x45\x66\x7b\x59\x1c\xd0\x81\x5e\x6d\x07\x7d\x42\xbd"
+ "\x02\xda\x69\x8a\x4e\x81\xae\x35\x20\x1d\xc8\x10\x59\xb1\x2a\x45"
+ "\x46\x1f\x79\x54\x1e\xba\x1b\x75\x8c\xfe\xfc\x87\x87\xe8\x90\xbb"
+ "\x0f\x71\x9c\x86\xee\xae\x6f\xe3\x18\x78\xfb\x7d\x68\x9e\xaa\xdf"
+ "\x1b\x40\x8f\x23\xb1\x9f\xf9\x5a\xf5\xd0\xdd\x20\x5b\x03\x8b\xc5"
+ "\x1f\x05\x0c\xd8\x58\x35\x74\x11\x96\x17\x7d\x58\xeb\xed\xc3\xa1"
+ "\x35\x81\xfa\x50\xd3\x77\x6c\x2f\x6a\x5a\x34\xb4\x11\x6d\x05\xca"
+ "\x74\x2a\xfb\x50\x07\xc2\x12\xea\x00\x0f\x46\xf4\x58\x47\xb5\x09"
+ "\xe9\x87\x8d\x0f\x54\x87\x56\x8f\xab\xcb\x09\xc1\xb5\x70\x2c\x97"
+ "\x68\xc2\x7e\x1d\x96\x11\x10\xdf\xfb\x7d\x64\x63\x27\x2d\x1a\x96"
+ "\xb5\x49\xec\xcb\x0d\xe5\x4a\xcf\x25\x5f\xa2\x85\x8f\x8b\x8e\x31"
+ "\xa8\xcf\xc3\xde\xab\x87\x48\x00\xd3\xc4\x7d\x75\x0b\x8c\x35\xda"
+ "\xf5\xfc\x9e\xbf\x5f\x18\x1e\xef\xfb\xfd\xc2\x70\xb9\xa7\xef\x17"
+ "\x7c\xeb\x1d\x7e\x3b\xd6\xeb\x29\x9b\xad\xf3\xd6\x3d\x7c\x86\x27"
+ "\x40\xdd\x4a\xf9\x89\xe5\xea\xf9\xcb\xf0\xe7\x50\x86\x3a\x18\x97"
+ "\xe8\xf0\xd9\x3a\x0a\x7c\xaa\xd9\x98\x3d\xbc\x9c\xc7\x2b\x18\x07"
+ "\x0d\xcf\x43\x1a\x6d\x3b\xba\x0f\xbd\x09\x7d\x05\x39\xcb\x6e\x06"
+ "\xdc\x48\xf0\x97\x68\x64\x58\xb9\x92\x2d\xf9\x10\x13\x1a\xe0\x26"
+ "\x8a\x90\xe1\x8c\x9e\xc2\xc1\x93\xc4\xbd\x8b\xdd\xc8\xdd\xf4\xdd"
+ "\xf9\xe7\x71\x0c\xe4\xf2\x32\x7e\x6d\x44\x27\xea\x73\xa8\x28\xae"
+ "\x3f\x47\x69\x4a\x94\x22\x81\x0e\x8c\x2a\xf3\x66\x0f\x00\x7e\x4e"
+ "\x46\x4c\x69\xa7\xe0\xaf\xdc\x53\xf5\x3d\xa6\xf8\xde\xc3\x11\x36"
+ "\x47\x55\xc1\xe8\xb0\x0c\xf6\xb8\xd6\xa8\xce\xee\x24\xa9\xdc\xe8"
+ "\x5b\x69\xde\x00\x76\x31\xe0\x9f\x1c\xe0\x97\x04\xf9\x23\xbc\xd9"
+ "\x61\xee\x75\x2a\xe2\xb7\xb9\xf8\x23\xa7\xf5\xdc\x88\x3e\x1f\xa3"
+ "\x54\x9f\x47\xf3\xcb\x88\xb6\x80\x94\x5f\xc7\x61\x69\x18\xa8\x7c"
+ "\xf4\xaa\xc7\xc8\x35\x81\x48\xbd\xfd\x3f\xf2\xb0\x92\xa4\xc6\xd3"
+ "\x9b\x7f\x59\x9a\xef\xfd\x58\xa3\xef\xfd\xb8\xd4\x0b\x21\xba\x03"
+ "\xff\xe4\x3a\x63\x09\x7a\x2a\xe5\x30\x68\x4c\xc6\x60\xd7\x98\x90"
+ "\xf7\x10\xd2\x84\x81\x3c\xa5\xaa\x64\x39\x30\xf5\xd7\x73\x0c\x5b"
+ "\x27\x3a\x70\xb4\xcb\xe8\x97\xa9\x4d\xc3\xfb\x70\x8b\x48\x9b\xfc"
+ "\x9a\x1f\x3d\x4b\xb3\xa8\xee\x75\x29\xf0\xa7\x1c\x0a\x6e\xb8\x10"
+ "\xb2\x5e\x3a\xfe\x0d\x0f\x1d\xda\xc7\xa5\xe3\x6b\x3a\x28\x1f\xc5"
+ "\xc1\x13\xb1\x0b\xfe\xa3\xdd\x8e\x92\x8a\x0c\x2a\x12\xa8\xf8\x70"
+ "\x41\xc6\xf1\x4b\xc7\xa5\xe3\xd2\x71\xe9\xb8\x74\x5c\x3a\x2e\x1d"
+ "\xfd\xe0\xd0\xa9\x27\xd6\x7a\x38\x23\xc4\x55\x3d\xff\xd1\x89\x53"
+ "\x9d\x26\x9d\x4f\x39\x2a\x0e\x92\x97\xe2\xb0\x94\xa7\x3b\x8d\xf6"
+ "\x59\x0d\xc9\x15\x59\x2e\xfd\x86\xd4\x9a\xa4\x9d\x99\x4d\xe6\x92"
+ "\xb4\x43\xd3\x2a\x73\xda\xe4\xfc\xeb\xab\x13\x77\x64\x1c\x35\x15"
+ "\xcf\x6e\xb4\xee\xc9\x76\x47\x6d\x9c\x59\x3b\x7e\xd7\xa2\xe6\x11"
+ "\xa5\x73\x0e\xcf\xa8\x5a\xd3\x29\xad\xbf\xee\xf5\x31\xbf\xbc\xef"
+ "\x48\x5c\xd1\x8f\x0e\x4e\xf9\xfd\xb2\x33\x91\x4f\xfd\xd7\xfe\x2b"
+ "\xfe\xef\xc1\xe3\xc3\x9e\xbd\xeb\xa3\xab\xff\xb4\xaa\x3d\xfc\x89"
+ "\x1b\xdf\xfc\xce\xaf\xe7\x1f\x4b\xd8\x72\xc7\xfb\x57\xbe\xb4\xe2"
+ "\xab\x98\x82\x5b\xeb\x26\xfe\x66\xc9\xa9\x51\xdb\xef\xfd\xdb\xf7"
+ "\x5f\x59\xeb\xd1\xad\xbb\xf6\xb5\xcb\x9e\x9b\xfb\x49\xec\x33\xb7"
+ "\x1f\x98\xfc\xbb\x87\x4e\x0f\x7c\xf2\xe6\xb7\x2e\x7f\x61\xc1\xe7"
+ "\x43\x7f\x71\xe7\x87\xd3\x5f\x7e\xe4\xec\x80\xc7\x6f\x78\x63\xdc"
+ "\xaf\xe6\x7d\x1a\xbf\xf9\xc7\xef\xd9\x5e\x7c\xf8\xcb\xe8\xa7\x6f"
+ "\x79\x67\xc2\xee\xc5\x27\x47\x6e\xbb\xe7\xe3\x6b\xf6\x3e\xda\x15"
+ "\xf6\xd8\x0f\xf6\x8d\x7d\xfe\xfe\x7f\x0c\xde\xf4\xdf\xef\x4e\xfd"
+ "\xc3\xf2\x96\x41\x3f\xfb\xe1\xdb\xdf\xfb\xff\x85\x27\x86\x6f\xbd"
+ "\xfb\xaf\xff\xf1\xe7\xd5\x1d\x11\xff\x73\xd3\x5f\xbe\xfb\xbf\x0f"
+ "\x7c\x36\xe4\xe7\x3f\xf9\xe0\xaa\x3f\xae\x6c\x35\x14\xde\x56\x3f"
+ "\xe9\xb7\x4b\xbf\x18\x5d\xf6\xd3\xbf\xff\xe7\xab\xb9\xf4\x7c\xfa"
+ "\x8f\xc8\x0b\xa7\x7e\xd3\xb8\xf1\xcb\xba\xbc\x50\xca\x53\x81\x3a"
+ "\xbf\xcd\xb3\x11\x9d\x9e\x84\xcb\x21\xcd\x13\x42\x6d\x6f\x0f\x87"
+ "\x45\x5d\xbe\xb7\x03\x7f\x17\x87\x7b\x5a\x63\xdf\x0f\x67\x29\xde"
+ "\x99\xff\xa8\x80\x25\xbe\x89\x43\x07\xed\x0c\x03\x49\x06\x90\x70"
+ "\xe8\x19\x3d\x19\x48\x22\xc9\x20\x12\x45\xa2\x49\x0c\x31\x10\x23"
+ "\x89\x25\x71\x64\x30\x31\x91\x78\x92\x40\x86\x10\x33\x19\x4a\x86"
+ "\x81\xf4\x23\xc8\xc8\xc0\x32\xe7\x91\x14\x33\xfc\x81\xff\xb3\x48"
+ "\x0a\xbb\x4f\xbf\x94\xfe\x8d\xa6\x3b\x44\x7a\x83\x48\x77\x5e\x4a"
+ "\xff\x46\xd3\x2d\xff\xe2\xeb\x65\xff\xd2\xab\x0e\xc2\x02\x1e\x19"
+ "\xf8\xc4\x07\xdd\x87\x36\x55\x27\x8e\xee\x7b\xd2\x4b\x79\x3f\x7e"
+ "\xbe\xe5\xb5\x47\x0a\x9c\x56\xfe\x31\x97\x10\xfe\x5d\x02\x55\x1f"
+ "\x9d\x3d\x95\x54\x8e\x92\x1c\x38\xf3\xe1\xb4\xc3\xb9\x09\xce\x32"
+ "\x38\x5f\x50\xf8\x10\xe2\x6a\x23\xe4\x0c\xf8\xf6\xd3\xc5\x70\xad"
+ "\x25\xa4\x25\x9d\x90\x2f\x9d\x84\xb8\xcb\x09\x69\xb5\xa8\x04\x8f"
+ "\xf2\x4a\xd4\x25\x6a\x85\x6c\x9d\x54\xac\xaa\xac\xaf\xe3\x53\xe5"
+ "\x0d\xb3\x53\x2d\x93\x27\x5a\x27\x5a\xa7\x5a\x26\x4c\xb0\x4c\x49"
+ "\x4e\x9e\x3e\x29\xd9\x36\x69\xca\x95\x96\x29\x53\xaf\xb6\x5d\x79"
+ "\xf5\x94\x69\x96\xc5\x8f\x2c\x5b\x30\x39\xf9\x81\x79\x96\x25\x19"
+ "\x0b\x96\x5b\xe6\x2f\x58\xb6\x78\xe5\xdc\x65\xf3\x7a\x6b\x75\x9f"
+ "\x0f\x68\x0a\x19\xd9\xc5\xc5\x54\xa3\xa1\x83\x51\x44\x1e\xeb\x22"
+ "\xf2\x55\x1b\x88\x37\x27\x49\x9c\x7e\xc7\xe2\xbb\xee\xf8\x68\xdc"
+ "\xdd\x31\xaf\x5f\xfb\xc0\xb8\x6b\x7e\xf0\x7c\x61\x05\x91\xae\xd1"
+ "\x13\xc9\xda\x40\xa4\x2b\x6a\x89\x34\x7a\x26\x91\xe2\x66\x11\x69"
+ "\xc5\x06\x22\x2d\x49\x21\x52\xc6\x78\x22\xa5\x95\x12\xe9\x87\x76"
+ "\xff\xb4\xc7\x13\x79\xda\x4b\xcd\x44\xda\x55\x49\xa4\xe7\xa2\x88"
+ "\xb4\xa9\x9a\xa7\xd5\x56\x11\xe9\xf5\xec\x0b\xde\x07\xe7\x7f\xf4"
+ "\x15\x7f\xdd\x3f\x01\x3a\x76\xe1\x43"
+ ;
diff --git a/usr/src/uts/common/io/myri10ge/firmware/rss_ethp_z8e.h b/usr/src/uts/common/io/myri10ge/firmware/rss_ethp_z8e.h
new file mode 100644
index 0000000000..22c0997fe0
--- /dev/null
+++ b/usr/src/uts/common/io/myri10ge/firmware/rss_ethp_z8e.h
@@ -0,0 +1,9488 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007-2009 Myricom, Inc. All rights reserved.
+ * Use is subject to license terms.
+ */
+
+const unsigned int rss_ethp_z8e_uncompressed_length = 555148 ;
+const unsigned int rss_ethp_z8e_length = 151319 ;
+const unsigned char rss_ethp_z8e[151319 + 1] =
+ "\x78\x9c\xec\xbd\x7f\x78\x54\xd5\xb5\x37\xbe\x32\x19\x60\xa4\x91"
+ "\x99\x84\x80\x23\xa2\x0e\x1a\xda\x88\x01\xa2\x62\x45\x0b\x1a\x25"
+ "\x5a\xf0\xf2\x4b\x05\x9b\x2a\x9a\x44\x13\x0c\x1a\x21\x92\x08\x03"
+ "\x86\x4c\x18\x7e\x88\x0a\x64\x12\x53\x8d\x12\x92\xd8\x62\x8b\x2d"
+ "\x2a\x6d\x69\x6f\x6e\x2f\xd6\x58\xe2\xfb\xd0\xdb\x24\x13\xfb\xa5"
+ "\xef\x9b\xeb\x17\x6f\x07\x6e\xa4\x91\x37\xc0\x48\x06\x66\x4c\x66"
+ "\x66\xbf\x9f\xb5\xf7\x39\xc9\xcc\x30\x41\xb9\xbd\xcf\xfb\xfe\xd3"
+ "\x3c\xcf\xe4\x9c\xb3\xcf\xde\x6b\xaf\xbd\xf6\xda\x6b\xaf\xb5\xf7"
+ "\xda\xeb\x10\xfd\x1d\x7f\xc6\x29\x9d\x7f\x4f\xf1\x7f\xfc\xfd\xe3"
+ "\xef\x1f\x7f\xff\xf8\xfb\xc7\xdf\x3f\xfe\xfe\xf1\xf7\xff\xe6\xef"
+ "\xac\xc1\x48\x7f\x70\x11\xf9\x9d\x26\xab\x87\xce\x94\xbf\xfe\xaa"
+ "\x08\x22\x39\xc1\x43\x26\x2b\x5f\xb5\x1f\xd5\x20\xdd\xe0\x22\xd3"
+ "\x75\x16\x4a\x9a\xb3\x9b\xa8\x76\xbc\xe8\x7d\xf5\x35\xe1\xdd\xf4"
+ "\x9a\xe8\xcd\x7e\x9b\xa8\x35\x8d\xe8\xd5\xf1\xc2\x07\x38\xcb\x3c"
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+ "\xe0\x9e\xb9\x16\x29\xaa\xde\xd7\xb3\x02\x88\x43\x92\xf2\x89\x3f"
+ "\xc6\x51\x19\xc4\xe4\x37\x79\x8b\xc3\x13\xc7\x95\xa5\x84\xa0\x2f"
+ "\x1c\xef\x0b\x0f\xc2\x72\x9d\x7e\xc4\x6b\xfd\x3e\xed\x96\x36\xb6"
+ "\x43\xda\x2a\x5e\x1b\x09\xb8\xe1\xe9\xab\xbf\x59\xfa\xc2\xf5\xbc"
+ "\x5f\x34\x85\x21\x9e\x67\x8c\x33\xc3\xe8\x16\xc3\xc4\x79\x40\x13"
+ "\xf4\x35\x9e\xfe\x7c\xdf\xcf\x17\x66\x3c\xe5\xfe\x7c\x61\xc6\x02"
+ "\x5f\xcf\x17\x3c\xe2\x3d\x88\xf1\x3a\x4b\x12\x55\x8a\xb8\xb3\x9d"
+ "\x5e\xe2\x96\xef\x9f\x5e\xaa\x1c\xbf\xcc\xf8\x12\xd3\x70\x1e\xfa"
+ "\x25\x3a\x36\x51\x45\x41\x4f\x25\xeb\xb3\x67\x34\x70\x7b\x05\xed"
+ "\xa0\x19\x55\x28\xe3\x99\x8f\xce\xcd\x3f\xe8\x14\x1e\xda\xd8\xc9"
+ "\x90\x1f\x13\x7c\xa3\x93\x8c\x29\x95\x2f\xab\xdd\x84\x09\xf5\x72"
+ "\x12\x40\xc8\x58\x26\x4f\x61\xe3\x41\xe2\xdc\xca\x4e\xa4\x4e\xf9"
+ "\xce\xeb\xfd\xd8\xee\xe6\xe9\x65\xfa\x5a\x89\x4a\xc4\x67\x52\x48"
+ "\xcc\xbd\xc9\xdd\x94\xc8\xb7\x78\xdb\x9e\x83\x3d\x33\x11\xec\xc6"
+ "\xb1\x16\x26\x4c\xa9\x43\xe8\x97\xcf\xa9\xf2\x1c\x43\xdc\xcf\x61"
+ "\xf3\x5b\xaa\x88\x60\x82\xdf\x4a\xf6\x9a\xd8\x78\x47\x67\x90\xba"
+ "\x54\xeb\x1e\x69\xe6\x10\x76\xd0\xe0\x9f\x74\xd0\x17\x09\xd7\x43"
+ "\x5d\x97\xfd\x6c\xbb\x15\xc2\xef\xf1\xe4\x8f\x8b\xf5\x9d\x89\x5e"
+ "\x6f\xe3\x15\xbf\x27\xf0\x43\x68\xab\x57\xc9\x5b\xb1\xe9\x6b\xee"
+ "\x96\x7f\xba\xe0\x31\x6e\x87\x37\x51\x57\xf9\x8f\xab\x93\x83\x94"
+ "\xf5\xe9\xba\x3e\x31\xc9\xfd\x7c\x92\xd6\xfd\x3c\xc2\x30\x10\x49"
+ "\x37\xe1\x9f\x0c\xcb\x08\x60\x8e\xa0\xce\x40\x8d\x47\x93\xd1\x18"
+ "\x3d\x9a\x90\x6b\x13\xa9\xf1\x83\xf4\x14\x29\x82\x25\xef\xd2\xb7"
+ "\x66\x1b\xb3\x5b\x14\xe0\x04\xab\xb6\xcb\x45\xcf\x30\x3c\x1f\xaa"
+ "\x17\x61\x33\x4f\x75\x91\x67\x61\x7a\xc5\xb9\x2a\x1e\xfe\x94\xc2"
+ "\x8d\x7b\x06\x22\xad\x77\xb6\xef\xe0\xa6\xc2\xf6\x71\x67\xbb\x45"
+ "\x1b\xe5\xbd\x38\x30\x11\x3b\xe0\x3f\xda\x49\x94\x54\x5c\xa0\x22"
+ "\x80\x8a\x1f\x03\xd2\x8f\xdf\xd9\xee\x6c\x77\xb6\x3b\xdb\x9d\xed"
+ "\xce\x76\x67\xbb\x0d\x36\x95\x72\x60\xed\x0f\xfb\x5d\xe2\xa8\x1c"
+ "\xff\xa8\xc4\xae\x0c\x53\xf7\xe7\x3e\x2a\x36\x92\x19\x6f\xd2\x97"
+ "\x2e\xb3\x68\x8d\x8b\x6b\x62\x8e\xa6\x5a\xfd\xf7\x18\xaa\x22\xcb"
+ "\x93\x1b\x74\x85\x49\xb5\xb1\x15\xe9\xad\x52\xf6\xdc\xca\xf0\xb2"
+ "\x95\xf5\x41\xf9\x89\x17\x67\x1f\xdb\x64\x0b\xd8\xb7\xa0\x3a\xea"
+ "\x48\xca\x95\xd0\xa2\xa5\x75\x71\xc7\x77\x38\xd4\x59\x3f\xfa\x63"
+ "\xd8\x2f\x57\x5c\x1a\x99\xf7\x0f\x7f\x9e\xf5\xef\x69\x37\x86\xbd"
+ "\x3c\xff\xec\xbd\xff\xba\xb6\x71\xcc\xeb\x4b\x3e\x7a\xe8\xff\x6d"
+ "\x6b\x1f\xfa\xd2\x8f\xff\x73\xf2\xbf\xac\xbe\x1c\x72\xe0\x89\xbf"
+ "\xdc\xff\x1f\x5b\xbe\x09\xcc\x59\x74\x7e\xfa\x6f\xd7\x5f\x1b\x5f"
+ "\xfc\xb3\x4f\x7e\x70\x72\x97\x53\xb5\xfb\x87\xa7\x26\xfe\x62\xf9"
+ "\xa7\x23\xf6\xff\xe4\xc2\xcc\x7f\x7b\xee\xeb\xbb\xf7\x26\xbc\x3b"
+ "\xf5\xcd\x35\x5f\x8e\x3e\xf8\xe4\x87\x0f\xfe\xe1\xf9\xb6\x21\x2f"
+ "\x3e\x72\x26\xe2\x8d\x55\x9f\x07\x17\x3c\xfe\xc1\x9c\xb7\x37\x37"
+ "\x0f\x7f\x75\xe1\xb9\xe8\xb7\xd6\x5d\x1d\x77\xf8\xa9\x8f\xbf\x7f"
+ "\x62\x67\x87\xdf\x0b\x0f\x9f\x9e\xf4\xab\xa7\x3f\xbb\xe7\xb5\x7f"
+ "\x7c\xff\xbe\xdf\x6f\x6c\xfa\xde\x2b\x8f\xbe\x37\xed\x37\xcf\x7e"
+ "\x35\xf6\xd0\x4f\xff\xf6\xbf\xfe\xff\x76\xfb\x5d\xff\x67\xde\x9f"
+ "\xa6\xfc\xfa\x99\x2f\x46\xfd\xf3\x3f\xfd\xf5\x81\xff\xbb\xb5\x45"
+ "\x93\xfb\x98\x79\xc6\xef\x36\x5c\x9f\x50\xf2\xf3\xbf\xff\xef\x77"
+ "\x32\x68\x7f\xca\x8f\x48\x19\xaf\x0d\x76\xbd\xf1\xc3\xee\xcc\xbe"
+ "\xdc\x4f\x45\xad\xf3\xd3\xcc\x39\x44\xe5\x4f\x86\x4a\x7d\x1a\x27"
+ "\xf4\x35\xbf\x3e\x36\xbd\xf2\xfe\xee\x36\xfc\x1e\x6f\x26\xec\xf7"
+ "\xc1\x3e\x96\x85\xb8\x46\xfe\xe3\xbd\xde\x31\x18\x9b\x0a\xf2\xe9"
+ "\x07\x29\x19\x42\x86\x42\xc9\xf8\x93\xbb\xc9\x30\xf2\x3d\x12\x40"
+ "\x86\x93\x40\xa2\x21\x5a\x32\x82\x8c\x24\xf7\x90\x20\x12\x4c\x42"
+ "\xc8\x28\xa2\x23\xa3\xc9\x18\x48\x7d\x28\x19\xe7\x3d\xcd\x99\x24"
+ "\x5e\x07\x7f\xe0\xff\x62\x12\xcf\xce\x97\xdd\x09\x1f\xd4\x70\x93"
+ "\x08\xaf\x11\xe1\x96\x3b\xe1\x83\x1a\xae\xff\x6f\x3e\x4e\xfc\x6f"
+ "\x3d\xaa\xc0\x2c\xe0\x96\x81\x9b\x7d\xd0\xb9\x79\x86\xaa\xc4\xd6"
+ "\x79\x4e\xba\xb9\xbf\x8b\x3e\xf7\xfb\x3d\xb7\x78\xd8\x67\xf3\x9f"
+ "\x19\x84\xf0\x67\x09\x54\xb9\x39\x7c\xdd\x29\x6f\x85\xe9\xb0\x67"
+ "\xc3\x6e\x84\x1d\xfa\xcd\xc2\x12\xd8\xdf\x94\xf5\x10\x62\x6d\x25"
+ "\xe4\x06\x70\xfb\xd7\xf9\x70\xac\x26\xa4\x69\x19\x21\xcd\x16\x42"
+ "\x6c\xa5\x84\xb4\xe8\x15\x09\x0f\x70\xa5\xa8\x43\xc4\x0a\x97\x55"
+ "\xea\x7c\x45\x64\xbd\xed\x9f\x2a\x1e\x49\x34\xe8\x67\x4e\x9f\x3d"
+ "\x7d\xf6\x7d\xfa\xe8\xc5\xd1\xfa\x59\x31\x31\x0f\xce\x88\x99\x33"
+ "\x63\xd6\xfd\xfa\x59\xf7\x3d\x34\xe7\xfe\x87\x66\xc5\xea\xd7\x3d"
+ "\x9f\xb6\x66\x66\xcc\x33\xab\xf4\xeb\x57\xae\xd9\xa8\x5f\xbd\x26"
+ "\x6d\xdd\xd6\xe5\x69\xab\xba\xcb\x76\x6f\x37\xc8\x0a\x19\xd7\xc1"
+ "\x93\xa9\xac\x0d\x15\xf4\x22\x52\x6c\x2c\x91\x1e\xad\x25\x9d\x57"
+ "\x54\x46\x91\x95\x48\xb1\x77\xd9\xd6\x2d\x79\xe2\xa3\x88\x9f\x06"
+ "\xfe\xf1\x87\xcf\x44\x7c\xff\xe1\x5f\xe5\x1e\x25\xea\x78\x3d\x51"
+ "\x3f\x50\x4d\xd4\xd1\xf9\x44\x3d\xb1\x92\xa8\x83\x96\x12\xf5\xf6"
+ "\x18\xa2\x4e\x83\xb0\xe4\x6c\xa2\x5e\x5a\x46\xd4\x8f\x45\x75\x0d"
+ "\x7b\x79\x31\x0f\x3b\x61\x24\xea\xdf\x47\x12\xf5\xaf\x41\xe6\x60"
+ "\x3a\x0f\x7b\xbf\x9e\xa8\xdf\x4d\x1e\xe8\xa2\x18\x80\xad\xb7\x38"
+ "\x50\xfd\x17\x1e\xf8\x64\x82"
+ ;
diff --git a/usr/src/uts/intel/Makefile.intel.shared b/usr/src/uts/intel/Makefile.intel.shared
index 85075459e0..bbfeb4a82f 100644
--- a/usr/src/uts/intel/Makefile.intel.shared
+++ b/usr/src/uts/intel/Makefile.intel.shared
@@ -214,6 +214,7 @@ DRV_KMODS += bscbus
DRV_KMODS += bscv
DRV_KMODS += chxge
DRV_KMODS += ntxn
+DRV_KMODS += myri10ge
DRV_KMODS += clone
DRV_KMODS += cmdk
DRV_KMODS += cn
diff --git a/usr/src/uts/intel/myri10ge/Makefile b/usr/src/uts/intel/myri10ge/Makefile
new file mode 100644
index 0000000000..da51d621b6
--- /dev/null
+++ b/usr/src/uts/intel/myri10ge/Makefile
@@ -0,0 +1,94 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+#
+# Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+#
+# Path to the base of the uts directory tree (usually /usr/src/uts).
+#
+UTSBASE = ../..
+
+#
+# Define the module and object file sets.
+#
+MODULE = myri10ge
+
+OBJECTS += $(MYRI10GE_OBJS:%=$(OBJS_DIR)/%)
+
+LINTS += $(MYRI10GE_OBJS:%.o=$(LINTS_DIR)/%.ln)
+
+ROOTMODULE = $(ROOT_DRV_DIR)/$(MODULE)
+
+#
+# Include common rules.
+#
+include $(UTSBASE)/intel/Makefile.intel
+
+#
+# Define targets
+#
+ALL_TARGET = $(BINARY)
+LINT_TARGET = $(MODULE).lint
+INSTALL_TARGET = $(BINARY) $(ROOTMODULE)
+
+#
+# Overrides
+#
+LINTTAGS += -DSOLARIS_S11 -erroff=E_STATIC_UNUSED
+
+#COPTIMIZE = -xO4
+
+INC_PATH += -I$(UTSBASE)/common/io/myri10ge -I$(UTSBASE)/common/io/myri10ge/firmware
+
+CFLAGS += -dalign -DSOLARIS_S11
+
+#
+# Driver depends on MAC
+#
+LDFLAGS += -dy -N misc/mac -N drv/ip
+
+#
+# Default build targets.
+#
+.KEEP_STATE:
+
+def: $(DEF_DEPS)
+
+all: $(ALL_DEPS)
+
+clean: $(CLEAN_DEPS)
+
+clobber: $(CLOBBER_DEPS)
+
+lint: $(LINT_DEPS)
+
+modlintlib: $(MODLINTLIB_DEPS)
+
+clean.lint: $(CLEAN_LINT_DEPS)
+
+install: $(INSTALL_DEPS)
+
+#
+# Include common targets.
+#
+include $(UTSBASE)/intel/Makefile.targ
diff --git a/usr/src/uts/intel/os/minor_perm b/usr/src/uts/intel/os/minor_perm
index 373dda492d..be895e09c9 100644
--- a/usr/src/uts/intel/os/minor_perm
+++ b/usr/src/uts/intel/os/minor_perm
@@ -121,6 +121,7 @@ lx_systrace:* 0644 root sys
clone:bge 0666 root sys
clone:igb 0666 root sys
clone:ixgbe 0666 root sys
+clone:myri10ge 0666 root sys
clone:rge 0666 root sys
clone:xge 0666 root sys
clone:nge 0666 root sys
@@ -155,6 +156,7 @@ clone:mxfe 0666 root sys
bge:* 0666 root sys
igb:* 0666 root sys
ixgbe:* 0666 root sys
+myri10ge:* 0666 root sys
rge:* 0666 root sys
xge:* 0666 root sys
nge:* 0666 root sys
diff --git a/usr/src/uts/sparc/Makefile.sparc.shared b/usr/src/uts/sparc/Makefile.sparc.shared
index 5ff4d10821..99fccfee09 100644
--- a/usr/src/uts/sparc/Makefile.sparc.shared
+++ b/usr/src/uts/sparc/Makefile.sparc.shared
@@ -284,6 +284,7 @@ DRV_KMODS += fcode
DRV_KMODS += mpt_sas
DRV_KMODS += socal
DRV_KMODS += sgen
+DRV_KMODS += myri10ge
DRV_KMODS += smp
DRV_KMODS += dad
DRV_KMODS += scsi_vhci
diff --git a/usr/src/uts/sparc/myri10ge/Makefile b/usr/src/uts/sparc/myri10ge/Makefile
new file mode 100644
index 0000000000..333e5c4bab
--- /dev/null
+++ b/usr/src/uts/sparc/myri10ge/Makefile
@@ -0,0 +1,94 @@
+#
+# CDDL HEADER START
+#
+# The contents of this file are subject to the terms of the
+# Common Development and Distribution License (the "License").
+# You may not use this file except in compliance with the License.
+#
+# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+# or http://www.opensolaris.org/os/licensing.
+# See the License for the specific language governing permissions
+# and limitations under the License.
+#
+# When distributing Covered Code, include this CDDL HEADER in each
+# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+# If applicable, add the following below this CDDL HEADER, with the
+# fields enclosed by brackets "[]" replaced with your own identifying
+# information: Portions Copyright [yyyy] [name of copyright owner]
+#
+# CDDL HEADER END
+#
+#
+# Copyright 2009 Sun Microsystems, Inc. All rights reserved.
+# Use is subject to license terms.
+#
+
+#
+# Path to the base of the uts directory tree (usually /usr/src/uts).
+#
+UTSBASE = ../..
+
+#
+# Define the module and object file sets.
+#
+MODULE = myri10ge
+
+OBJECTS += $(MYRI10GE_OBJS:%=$(OBJS_DIR)/%)
+
+LINTS += $(MYRI10GE_OBJS:%.o=$(LINTS_DIR)/%.ln)
+
+ROOTMODULE = $(ROOT_DRV_DIR)/$(MODULE)
+
+#
+# Include common rules.
+#
+include $(UTSBASE)/sparc/Makefile.sparc
+
+#
+# Define targets
+#
+ALL_TARGET = $(BINARY)
+LINT_TARGET = $(MODULE).lint
+INSTALL_TARGET = $(BINARY) $(ROOTMODULE)
+
+#
+# Overrides
+#
+LINTTAGS += -DSOLARIS_S11 -erroff=E_STATIC_UNUSED
+
+#COPTIMIZE = -xO4
+
+INC_PATH += -I$(UTSBASE)/common/io/myri10ge -I$(UTSBASE)/common/io/myri10ge/firmware
+
+CFLAGS += -dalign -DSOLARIS_S11
+
+#
+# Driver depends on MAC
+#
+LDFLAGS += -dy -N misc/mac -N drv/ip
+
+#
+# Default build targets.
+#
+.KEEP_STATE:
+
+def: $(DEF_DEPS)
+
+all: $(ALL_DEPS)
+
+clean: $(CLEAN_DEPS)
+
+clobber: $(CLOBBER_DEPS)
+
+lint: $(LINT_DEPS)
+
+modlintlib: $(MODLINTLIB_DEPS)
+
+clean.lint: $(CLEAN_LINT_DEPS)
+
+install: $(INSTALL_DEPS)
+
+#
+# Include common targets.
+#
+include $(UTSBASE)/sparc/Makefile.targ
diff --git a/usr/src/uts/sparc/os/minor_perm b/usr/src/uts/sparc/os/minor_perm
index b34b7f4fec..aeba76bb83 100644
--- a/usr/src/uts/sparc/os/minor_perm
+++ b/usr/src/uts/sparc/os/minor_perm
@@ -152,6 +152,7 @@ kssl:* 0666 root sys
clone:bge 0666 root sys
clone:igb 0666 root sys
clone:ixgbe 0666 root sys
+clone:myri10ge 0666 root sys
clone:rge 0666 root sys
clone:xge 0666 root sys
clone:nge 0666 root sys
@@ -169,6 +170,7 @@ clone:vnic 0666 root sys
bge:* 0666 root sys
igb:* 0666 root sys
ixgbe:* 0666 root sys
+myri10ge:* 0666 root sys
rge:* 0666 root sys
xge:* 0666 root sys
nge:* 0666 root sys