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-rw-r--r--usr/src/cmd/cxgbetool/Makefile13
-rw-r--r--usr/src/cmd/cxgbetool/cudbg_view.c5103
-rw-r--r--usr/src/cmd/cxgbetool/cudbg_view.h179
-rw-r--r--usr/src/cmd/cxgbetool/cudbg_view_compat.c50
-rw-r--r--usr/src/cmd/cxgbetool/cudbg_view_compat.h49
-rw-r--r--usr/src/cmd/cxgbetool/cudbg_view_entity.h8046
-rw-r--r--usr/src/cmd/cxgbetool/cxgbetool.c383
-rw-r--r--usr/src/cmd/cxgbetool/reg_defs_t5.c64811
-rw-r--r--usr/src/cmd/cxgbetool/reg_defs_t6.c56438
-rw-r--r--usr/src/pkg/manifests/driver-network-cxgbe.mf29
-rw-r--r--usr/src/uts/common/Makefile.files6
-rw-r--r--usr/src/uts/common/io/cxgbe/common/common.c124
-rw-r--r--usr/src/uts/common/io/cxgbe/common/common.h334
-rw-r--r--usr/src/uts/common/io/cxgbe/common/t4_chip_type.h58
-rw-r--r--usr/src/uts/common/io/cxgbe/common/t4_hw.c1989
-rw-r--r--usr/src/uts/common/io/cxgbe/common/t4_hw.h14
-rw-r--r--usr/src/uts/common/io/cxgbe/common/t4_msg.h8
-rw-r--r--usr/src/uts/common/io/cxgbe/common/t4_regs.h173
-rw-r--r--usr/src/uts/common/io/cxgbe/common/t4_regs_values.h7
-rw-r--r--usr/src/uts/common/io/cxgbe/firmware/t4_fw.c71425
-rw-r--r--usr/src/uts/common/io/cxgbe/firmware/t4_fw.h8
-rw-r--r--usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h626
-rw-r--r--usr/src/uts/common/io/cxgbe/firmware/t4fw_version.h4
-rw-r--r--usr/src/uts/common/io/cxgbe/firmware/t5_fw.c82593
-rw-r--r--usr/src/uts/common/io/cxgbe/firmware/t5_fw.h4
-rw-r--r--usr/src/uts/common/io/cxgbe/firmware/t5fw_version.h4
-rw-r--r--usr/src/uts/common/io/cxgbe/firmware/t6_fw.c88929
-rw-r--r--usr/src/uts/common/io/cxgbe/firmware/t6_fw.h4
-rw-r--r--usr/src/uts/common/io/cxgbe/firmware/t6fw_version.h4
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/adapter.h19
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/cudbg.c80
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/cudbg.h447
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/cudbg_common.c85
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/cudbg_entity.h980
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/cudbg_flash_utils.c509
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c4437
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.h263
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib_common.h153
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c1323
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/fastlz.c572
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/fastlz.h73
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/fastlz_api.c556
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c56
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/t4_mac.c120
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c9
-rw-r--r--usr/src/uts/common/io/cxgbe/t4nex/t4nex.h8
46 files changed, 269151 insertions, 121954 deletions
diff --git a/usr/src/cmd/cxgbetool/Makefile b/usr/src/cmd/cxgbetool/Makefile
index c8557b453f..f49b87aa56 100644
--- a/usr/src/cmd/cxgbetool/Makefile
+++ b/usr/src/cmd/cxgbetool/Makefile
@@ -10,20 +10,29 @@
#
#
-# Copyright (c) 2018 by Chelsio Communications, Inc.
+# Copyright (c) 2019 by Chelsio Communications, Inc.
#
# Copyright (c) 2018, Joyent, Inc.
PROG = cxgbetool
+OBJS = cxgbetool.o cudbg.o cudbg_view.o fastlz_api.o fastlz.o cudbg_common.o
+SRCS = $(OBJS:%.o=%.c)
+VPATH = $(SRC)/uts/common/io/cxgbe/t4nex/
include ../Makefile.cmd
-CFLAGS += $(CCVERBOSE) -I$(SRC)/uts/common/io/cxgbe/t4nex -I$(SRC)/uts/common/io/cxgbe/firmware
+CFLAGS += $(CCVERBOSE) -I$(SRC)/uts/common/io/cxgbe/t4nex -I$(SRC)/uts/common/io/cxgbe/firmware \
+ -I$(SRC)/uts/common/io/cxgbe/common
+
SMOFF += all_func_returns
all: $(PROG)
+$(PROG): $(OBJS)
+ $(LINK.c) $(OBJS) -o $@ $(LDLIBS)
+ $(POST_PROCESS)
+
install: all $(ROOTUSRSBINPROG)
clean:
diff --git a/usr/src/cmd/cxgbetool/cudbg_view.c b/usr/src/cmd/cxgbetool/cudbg_view.c
new file mode 100644
index 0000000000..5d4dd9f7a1
--- /dev/null
+++ b/usr/src/cmd/cxgbetool/cudbg_view.c
@@ -0,0 +1,5103 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright (c) 2019 by Chelsio Communications, Inc.
+ */
+
+#include <stdio.h>
+#include <stddef.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <assert.h>
+
+#include "t4_regs.h"
+#include "t4_chip_type.h"
+#include "cudbg_view.h"
+#include "osdep.h"
+#include "t4fw_interface.h"
+
+#include "cudbg_view_entity.h"
+#include "cudbg_entity.h"
+#include "cudbg.h"
+#include "cudbg_lib_common.h"
+#include "fastlz.h"
+
+extern struct reg_info t6_sge_regs[];
+extern struct reg_info t6_pcie_regs[];
+extern struct reg_info t6_dbg_regs[];
+extern struct reg_info t6_ma_regs[];
+extern struct reg_info t6_cim_regs[];
+extern struct reg_info t6_tp_regs[];
+extern struct reg_info t6_ulp_tx_regs[];
+extern struct reg_info t6_pm_rx_regs[];
+extern struct reg_info t6_pm_tx_regs[];
+extern struct reg_info t6_mps_regs[];
+extern struct reg_info t6_cpl_switch_regs[];
+extern struct reg_info t6_smb_regs[];
+extern struct reg_info t6_i2cm_regs[];
+extern struct reg_info t6_mi_regs[];
+extern struct reg_info t6_uart_regs[];
+extern struct reg_info t6_pmu_regs[];
+extern struct reg_info t6_ulp_rx_regs[];
+extern struct reg_info t6_sf_regs[];
+extern struct reg_info t6_pl_regs[];
+extern struct reg_info t6_le_regs[];
+extern struct reg_info t6_ncsi_regs[];
+extern struct reg_info t6_mac_regs[];
+extern struct reg_info t6_mc_0_regs[];
+extern struct reg_info t6_edc_t60_regs[];
+extern struct reg_info t6_edc_t61_regs[];
+extern struct reg_info t6_hma_t6_regs[];
+
+extern struct reg_info t5_sge_regs[];
+extern struct reg_info t5_pcie_regs[];
+extern struct reg_info t5_dbg_regs[];
+extern struct reg_info t5_ma_regs[];
+extern struct reg_info t5_cim_regs[];
+extern struct reg_info t5_tp_regs[];
+extern struct reg_info t5_ulp_tx_regs[];
+extern struct reg_info t5_pm_rx_regs[];
+extern struct reg_info t5_pm_tx_regs[];
+extern struct reg_info t5_mps_regs[];
+extern struct reg_info t5_cpl_switch_regs[];
+extern struct reg_info t5_smb_regs[];
+extern struct reg_info t5_i2cm_regs[];
+extern struct reg_info t5_mi_regs[];
+extern struct reg_info t5_uart_regs[];
+extern struct reg_info t5_pmu_regs[];
+extern struct reg_info t5_ulp_rx_regs[];
+extern struct reg_info t5_sf_regs[];
+extern struct reg_info t5_pl_regs[];
+extern struct reg_info t5_le_regs[];
+extern struct reg_info t5_ncsi_regs[];
+extern struct reg_info t5_mac_regs[];
+extern struct reg_info t5_mc_0_regs[];
+extern struct reg_info t5_mc_1_regs[];
+extern struct reg_info t5_edc_t50_regs[];
+extern struct reg_info t5_edc_t51_regs[];
+extern struct reg_info t5_hma_t5_regs[];
+
+#include "reg_defs_t5.c"
+#include "reg_defs_t6.c"
+
+#include <time.h>
+#include <stdarg.h>
+
+int is_t5(enum chip_type chip)
+{
+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
+}
+
+int is_t6(enum chip_type chip)
+{
+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
+}
+
+enum { /* adapter flags */
+ FULL_INIT_DONE = (1 << 0),
+ USING_MSI = (1 << 1),
+ USING_MSIX = (1 << 2),
+ QUEUES_BOUND = (1 << 3),
+ FW_OK = (1 << 4),
+ RSS_TNLALLLOOKUP = (1 << 5),
+ USING_SOFT_PARAMS = (1 << 6),
+ MASTER_PF = (1 << 7),
+ BYPASS_DROP = (1 << 8),
+ FW_OFLD_CONN = (1 << 9),
+};
+
+static struct ver_cs {
+ int major;
+ int minor;
+ int changeset;
+} ver_to_cs[] = {
+ {1, 9, 12852},
+ {1, 10, 13182},
+ {1, 11, 13257},
+ {1, 12, 13495},
+ {1, 13, 13905},
+ {1, 14, 13969},
+};
+
+static bool flash_info_banner = true;
+
+#include "cudbg_view_compat.c"
+
+int
+cudbg_sge_ctxt_check_valid(u32 *buf, int type)
+{
+ int index, bit, bit_pos = 0;
+
+ switch (type) {
+ case CTXT_EGRESS:
+ bit_pos = 176;
+ break;
+ case CTXT_INGRESS:
+ bit_pos = 141;
+ break;
+ case CTXT_FLM:
+ bit_pos = 89;
+ break;
+ }
+ index = bit_pos / 32;
+ bit = bit_pos % 32;
+ return buf[index] & (1U << bit);
+}
+
+int
+cudbg_view_decompress_buff(char *pbuf,
+ struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *c_buff,
+ struct cudbg_buffer *dc_buff)
+{
+ int rc = 0;
+
+ c_buff->data = pbuf + entity_hdr->start_offset;
+ /* Remove padding bytes, if any */
+ if (entity_hdr->num_pad)
+ c_buff->size = entity_hdr->size - entity_hdr->num_pad;
+ else
+ c_buff->size = entity_hdr->size;
+ c_buff->offset = 0;
+ memset(dc_buff, 0, sizeof(struct cudbg_buffer));
+
+ rc = validate_buffer(c_buff);
+ if (rc)
+ return rc;
+
+ rc = decompress_buffer_wrapper(c_buff, dc_buff);
+ if (rc) {
+ free(dc_buff->data);
+ return rc;
+ }
+ return rc;
+}
+
+int
+get_entity_rev(struct cudbg_ver_hdr *ver_hdr)
+{
+ if (ver_hdr->signature == CUDBG_ENTITY_SIGNATURE)
+ return ver_hdr->revision;
+ return 0;
+}
+
+/* Find Mercurial sw repo changeset number
+ * where major or minor number set to given number
+ * */
+int
+cudbg_find_changeset(int major, int minor)
+{
+ int i;
+
+ for (i = 0; i < sizeof(ver_to_cs)/sizeof(struct ver_cs); i++) {
+ if (ver_to_cs[i].major == major &&
+ ver_to_cs[i].minor == minor)
+ return ver_to_cs[i].changeset;
+ }
+
+ return -1;
+}
+
+/* Format a value in a unit that differs from the
+ * value's native unit by the
+ * given factor.
+ */
+static void
+unit_conv(char *buf, size_t len, unsigned int val,
+ unsigned int factor)
+{
+ unsigned int rem = val % factor;
+
+ if (rem == 0)
+ (void) snprintf(buf, len, "%u", val / factor);
+ else {
+ while (rem % 10 == 0)
+ rem /= 10;
+ (void) snprintf(buf, len, "%u.%u", val / factor, rem);
+ }
+}
+
+int
+validate_next_rec_offset(void *pinbuf, u32 inbuf_size, u32
+ next_rec_offset)
+{
+ struct cudbg_hdr *cudbg_hdr;
+
+ if (inbuf_size <= next_rec_offset)
+ return 0;
+
+ cudbg_hdr = (struct cudbg_hdr *)((char *)pinbuf + next_rec_offset);
+ if ((cudbg_hdr->signature != CUDBG_SIGNATURE) &&
+ (cudbg_hdr->signature != CUDBG_LEGACY_SIGNATURE))
+ return 0; /* no next rec */
+
+ return next_rec_offset;
+}
+
+int
+view_ext_entity(char *pinbuf, struct cudbg_entity_hdr *ent_hdr,
+ struct cudbg_buffer *cudbg_poutbuf,
+ enum chip_type chip)
+{
+ struct cudbg_entity_hdr *entity_hdr = NULL;
+ u32 size, total_size = 0;
+ u32 next_ext_offset = 0;
+ u32 entity_type;
+ int rc = 0;
+
+ entity_hdr = (struct cudbg_entity_hdr *)
+ (pinbuf + ent_hdr->start_offset);
+ /* Remove padding bytes, if any */
+ size = ent_hdr->num_pad ? ent_hdr->size - ent_hdr->num_pad :
+ ent_hdr->size;
+ while ((entity_hdr->flag & CUDBG_EXT_DATA_VALID)
+ && (total_size < size)) {
+ entity_type = entity_hdr->entity_type;
+ if (entity_hdr->sys_warn)
+ printf("Entity warning: Type %s , %d\n",
+ entity_list[entity_type].name,
+ entity_hdr->sys_warn);
+
+ if (entity_hdr->hdr_flags) {
+ printf("Entity error: Type %s, %s\n",
+ entity_list[entity_type].name,
+ err_msg[-entity_hdr->hdr_flags]);
+ if (entity_hdr->sys_err)
+ printf("System error %d\n",
+ entity_hdr->sys_err);
+
+ next_ext_offset = entity_hdr->next_ext_offset;
+ entity_hdr = (struct cudbg_entity_hdr *)
+ (pinbuf + ent_hdr->start_offset +
+ next_ext_offset);
+ continue;
+ }
+ if (entity_hdr->size > 0) {
+ total_size += entity_hdr->size +
+ sizeof(struct cudbg_entity_hdr);
+
+ rc = view_entity[entity_type - 1]
+ (pinbuf + ent_hdr->start_offset,
+ entity_hdr,
+ cudbg_poutbuf,
+ chip);
+ if (rc < 0)
+ goto out;
+ }
+ next_ext_offset = entity_hdr->next_ext_offset;
+ entity_hdr = (struct cudbg_entity_hdr *)
+ (pinbuf + ent_hdr->start_offset + next_ext_offset);
+ }
+
+ if (total_size != size)
+ printf("Entity warning: Extended entity size mismatch\n");
+
+out:
+ return rc;
+}
+
+static void
+cudbg_print_cudbg_header(struct cudbg_hdr *hdr)
+{
+ printf("\n/***************Header Information***************/\n");
+ printf("Library Version: %u.%u\n", hdr->major_ver, hdr->minor_ver);
+ printf("Compressed with: ");
+ printf("Chip Version: ");
+ switch (CHELSIO_CHIP_VERSION(hdr->chip_ver)) {
+ case CHELSIO_T4:
+ printf("T4 rev: %u\n", CHELSIO_CHIP_RELEASE(hdr->chip_ver));
+ break;
+ case CHELSIO_T5:
+ printf("T5 rev: %u\n", CHELSIO_CHIP_RELEASE(hdr->chip_ver));
+ break;
+ case CHELSIO_T6:
+ printf("T6 rev: %u\n", CHELSIO_CHIP_RELEASE(hdr->chip_ver));
+ break;
+ default:
+ printf("%u (unknown)\n", hdr->chip_ver);
+ break;
+ }
+ printf("/************************************************/\n\n");
+}
+
+void
+cudbg_print_flash_header(void *pinbuf)
+{
+ struct cudbg_flash_hdr *fl_hdr = (struct cudbg_flash_hdr *)pinbuf;
+
+ if (fl_hdr->signature == CUDBG_FL_SIGNATURE && flash_info_banner) {
+ printf("\n/***************Flash Header information***************/\n");
+ printf("Flash signature: %c%c%c%c\n",
+ (fl_hdr->signature >> 24) & 0xFF,
+ (fl_hdr->signature >> 16) & 0xFF,
+ (fl_hdr->signature >> 8) & 0xFF,
+ fl_hdr->signature & 0xFF);
+
+ printf("Flash payload timestamp (GMT): %s",
+ asctime(gmtime((time_t *)&fl_hdr->timestamp)));
+ printf("Flash payload size: %u bytes\n", fl_hdr->data_len);
+ printf("/******************************************************/\n");
+ flash_info_banner = false;
+ }
+}
+
+int
+cudbg_view(void *handle, void *pinbuf, u32 inbuf_size,
+ void *poutbuf, s64 *poutbuf_size)
+{
+
+ struct cudbg_buffer cudbg_poutbuf = {0};
+ struct cudbg_entity_hdr *entity_hdr;
+ u32 info, offset, max_entities, i;
+ struct cudbg_hdr *tmp_hdr;
+ u32 next_rec_offset = 0;
+ int index, bit, all;
+ int rc = 0, cs;
+ u8 *dbg_bitmap;
+ int count = 0;
+
+ dbg_bitmap = ((struct cudbg_private *)handle)->dbg_init.dbg_bitmap;
+ info = ((struct cudbg_private *)handle)->dbg_init.info;
+
+ if (inbuf_size < (sizeof(struct cudbg_entity_hdr) +
+ sizeof(struct cudbg_hdr))) {
+ printf("\n\tInvalid cudbg dump file\n");
+ return CUDBG_STATUS_NO_SIGNATURE;
+ }
+
+ tmp_hdr = (struct cudbg_hdr *)pinbuf;
+ if ((tmp_hdr->signature != CUDBG_SIGNATURE) &&
+ (tmp_hdr->signature != CUDBG_LEGACY_SIGNATURE)) {
+ printf("\n\tInvalid cudbg dump file\n");
+ return CUDBG_STATUS_NO_SIGNATURE;
+ }
+
+ if ((tmp_hdr->major_ver != CUDBG_MAJOR_VERSION) ||
+ (tmp_hdr->minor_ver != CUDBG_MINOR_VERSION)) {
+ printf("\n\tMeta data version mismatch\n");
+ printf("\tMeta data version expected %d.%d\n",
+ CUDBG_MAJOR_VERSION, CUDBG_MINOR_VERSION);
+ printf("\tMeta data version in dump %d.%d\n",
+ tmp_hdr->major_ver, tmp_hdr->minor_ver);
+
+ cs = cudbg_find_changeset(tmp_hdr->major_ver,
+ tmp_hdr->minor_ver);
+ if (cs != -1) {
+ printf("\n\tPlease use changeset %d in sw Mercurial "\
+ "repo to build cudbg_app with version %d.%d\n",
+ cs, tmp_hdr->major_ver, tmp_hdr->minor_ver);
+
+ printf("\n\tOr\n\n\tUse precompiled cudbg_app binary for RHEL 5.x from "\
+ "vnc52:/home/surendra/vnc52/"\
+ "cudbg_app/cudbg_app_<version>\"\n\n");
+
+
+ }
+ return CUDBG_METADATA_VERSION_MISMATCH;
+ }
+
+ if (info)
+ cudbg_print_cudbg_header(tmp_hdr);
+
+ next_rec_offset += tmp_hdr->data_len;
+ offset = tmp_hdr->hdr_len;
+ all = dbg_bitmap[0] & (1 << CUDBG_ALL);
+ max_entities = min(tmp_hdr->max_entities, CUDBG_MAX_ENTITY);
+
+ for (i = 1; i < max_entities; i++) {
+ index = i / 8;
+ bit = i % 8;
+
+ if (all || (dbg_bitmap[index] & (1 << bit))) {
+ entity_hdr =
+ (struct cudbg_entity_hdr *)((char *)pinbuf + offset);
+
+ if (entity_hdr->sys_warn)
+ printf("Entity warning: Type %s , %d\n",
+ entity_list[i].name,
+ entity_hdr->sys_warn);
+
+ if (entity_hdr->hdr_flags) {
+ offset += sizeof(struct cudbg_entity_hdr);
+ printf("Entity error: Type %s, %s\n",
+ entity_list[i].name,
+ err_msg[-entity_hdr->hdr_flags]);
+ if (entity_hdr->sys_err)
+ printf("System error %d\n",
+ entity_hdr->sys_err);
+
+ if (poutbuf)
+ *poutbuf_size = 0;
+
+ continue;
+ }
+ memset(&cudbg_poutbuf, 0, sizeof(cudbg_poutbuf));
+ if (entity_hdr->size > 0) {
+ if (poutbuf) {
+ cudbg_poutbuf.data = poutbuf;
+ /* poutbuf_size value should not be
+ * more than 32 bit value
+ */
+ assert(!((*poutbuf_size) >> 32));
+ cudbg_poutbuf.size = (u32)*poutbuf_size;
+ cudbg_poutbuf.offset = 0;
+ }
+
+ if (info)
+ printf("%-20s compressed size %u\n",
+ entity_list[i].name,
+ entity_hdr->size);
+ else {
+ if (entity_hdr->entity_type !=
+ CUDBG_EXT_ENTITY)
+ printf("%s() dbg entity : %s\n",
+ __func__,
+ entity_list[i].name);
+
+ rc = view_entity[i - 1]
+ ((char *)pinbuf,
+ entity_hdr,
+ &cudbg_poutbuf,
+ tmp_hdr->chip_ver);
+
+ count++;
+ }
+ } else if (!all && i !=
+ CUDBG_EXT_ENTITY) {
+ printf("%s() dbg entity : %s\n",
+ __func__, entity_list[i].name);
+ printf("\t%s not available\n",
+ entity_list[i].name);
+ }
+ if (rc < 0)
+ goto out;
+ }
+ offset += sizeof(struct cudbg_entity_hdr);
+ }
+
+ /* if max_entities in dump is less than current CUDBG_MAX_ENTITY
+ * it means entities after tmp_hdr->max_entities does not exist
+ * in that dump
+ */
+ if (tmp_hdr->max_entities < CUDBG_MAX_ENTITY) {
+ for (i = tmp_hdr->max_entities; i < CUDBG_MAX_ENTITY; i++) {
+ index = i / 8;
+ bit = i % 8;
+
+ if (all || (dbg_bitmap[index] & (1 << bit))) {
+ printf("%s() dbg entity : %s\n",
+ __func__, entity_list[i].name);
+ printf("\t%s does not Exist\n",
+ entity_list[i].name);
+ }
+ }
+ }
+ if (poutbuf) {
+ if (!count)
+ *poutbuf_size = 0;
+ else
+ *poutbuf_size = cudbg_poutbuf.size;
+ }
+
+ return validate_next_rec_offset(pinbuf, inbuf_size, next_rec_offset);
+
+out:
+ if (poutbuf)
+ *poutbuf_size = cudbg_poutbuf.size;
+ return rc;
+}
+
+int
+view_cim_q(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf,
+ enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ u32 i, *pdata = NULL;
+ int rc;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ pdata = (u32 *)dc_buff.data;
+ for (i = 0; i < dc_buff.offset / 4; i += 4)
+ printf("%#06x: %08x %08x %08x "\
+ "%08x\n", i * 4,
+ pdata[i + 0], pdata[i + 1],
+ pdata[i + 2], pdata[i + 3]);
+
+ return rc;
+}
+
+static int
+view_cim_la_t6(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ u32 i, *p, cfg, dc_size;
+ int rc;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ dc_size = dc_buff.offset;
+ p = (u32 *)((char *)dc_buff.data + sizeof(cfg));
+ cfg = *((u32 *)dc_buff.data);
+ dc_size -= sizeof(cfg);
+
+ if (cfg & F_UPDBGLACAPTPCONLY) {
+ printf("Status Inst Data "\
+ "PC\r\n");
+
+ for (i = 0; i < dc_size; i += 40, p += 10) {
+ printf(" %02x %08x %08x %08x\n",
+ p[3] & 0xff, p[2], p[1], p[0]);
+
+ printf(" %02x %02x%06x %02x%06x %02x%06x\n",
+ (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
+ p[5] & 0xff, p[4] >> 8, p[4] & 0xff,
+ p[3] >> 8);
+
+ printf(" %02x %04x%04x %04x%04x %04x%04x\n",
+ (p[9] >> 16) & 0xff, p[9] & 0xffff,
+ p[8] >> 16, p[8] & 0xffff, p[7] >> 16,
+ p[7] & 0xffff, p[6] >> 16);
+ }
+ goto err1;
+ }
+
+ printf("Status Inst Data PC "\
+ "LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data\n");
+
+ for (i = 0; i < dc_size; i += 40, p += 10) {
+ printf(" %02x %04x%04x %04x%04x "\
+ "%04x%04x %08x %08x %08x %08x %08x %08x\n",
+ (p[9] >> 16) & 0xff, /* Status */
+ p[9] & 0xffff, p[8] >> 16, /* Inst */
+ p[8] & 0xffff, p[7] >> 16, /* Data */
+ p[7] & 0xffff, p[6] >> 16, /* PC */
+ p[2], p[1], p[0], /* LS0 Stat, Addr
+ and Data */
+ p[5], p[4], p[3]); /* LS1 Stat, Addr
+ and Data */
+ }
+
+err1:
+ return rc;
+}
+
+static int
+view_cim_la_t5(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ u32 i, *p, cfg, dc_size;
+ int rc;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ dc_size = dc_buff.offset;
+ p = (u32 *)((char *)dc_buff.data + sizeof(cfg));
+ cfg = *((u32 *)dc_buff.data);
+ dc_size -= sizeof(cfg);
+
+ if (cfg & F_UPDBGLACAPTPCONLY) {
+ /* as per cim_la_show_3in1() (in
+ * sw\dev\linux\drv\cxgb4_main.c)*/
+ printf("Status Data PC\r\n");
+
+ for (i = 0; i < dc_size; i += 32, p += 8) {
+ printf(" %02X %08X %08X\r\n",
+ (p[5] & 0xFF), p[6], p[7]);
+
+ printf(
+ " %02X %02X%06X %02X%06X\n",
+ ((p[3] >> 8) & 0xFF), (p[3] & 0xFF),
+ (p[4] >> 8), (p[4] & 0xFF), (p[5] >> 8));
+
+ printf(
+ " %02X %X%07X %X%07X\r\n",
+ ((p[0] >> 4) & 0xFF), (p[0] & 0xF),
+ (p[1] >> 4), (p[1] & 0xF), (p[2] >> 4));
+ }
+ goto err1;
+ }
+
+ printf("Status Data PC LS0Stat "\
+ "LS0Addr LS0Data\n");
+
+ for (i = 0; i < dc_size; i += 32, p += 8) {
+ printf("%02x %x%07x %x%07x %08x "\
+ "%08x %08x%08x%08x%08x\n",
+ ((p[0] >> 4) & 0xFF), (p[0] & 0xF), (p[1] >> 4),
+ (p[1] & 0xF), (p[2] >> 4), (p[2] & 0xF), p[3],
+ p[4], p[5], p[6], p[7]);
+ }
+err1:
+ return rc;
+}
+
+int
+view_cim_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ int rc = -1;
+
+ if (is_t5(chip))
+ rc = view_cim_la_t5(pbuf, entity_hdr, cudbg_poutbuf);
+ else if (is_t6(chip))
+ rc = view_cim_la_t6(pbuf, entity_hdr, cudbg_poutbuf);
+
+ return rc;
+}
+
+int
+view_cim_ma_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc, i, j;
+ u32 *p;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ p = (u32 *)dc_buff.data;
+ for (i = 0; i <= CIM_MALA_SIZE; i++, p += 4) {
+ if (i < CIM_MALA_SIZE) {
+ printf(
+ "%02x%08x%08x%08x%08x\n",
+ p[4], p[3], p[2], p[1], p[0]);
+ } else {
+ printf("\nCnt ID Tag UE "\
+ " Data RDY VLD\n");
+ for (j = 0; j < CIM_MALA_SIZE ; j++, p += 3) {
+ printf(
+ "%3u %2u %x %u %08x%08x %u "\
+ "%u\n",
+ (p[2] >> 10) & 0xff,
+ (p[2] >> 7) & 7, (p[2] >> 3) & 0xf,
+ (p[2] >> 2) & 1,
+ (p[1] >> 2) | ((p[2] & 3) << 30),
+ (p[0] >> 2) | ((p[1] & 3) << 30),
+ (p[0] >> 1) & 1, p[0] & 1);
+ }
+ }
+ }
+
+ return rc;
+}
+
+int
+view_cim_qcfg(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ static const char * const pQname[] = {
+ "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",
+ "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI"
+ };
+ struct cudbg_buffer c_buff, dc_buff;
+ struct struct_cim_qcfg *q_cfg_data;
+ u32 *p, *wr;
+ int rc, i;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ q_cfg_data = (struct struct_cim_qcfg *) (dc_buff.data);
+ p = q_cfg_data->stat;
+ wr = q_cfg_data->obq_wr;
+
+ printf(" Queue Base Size Thres RdPtr "\
+ "WrPtr SOP EOP Avail\n");
+ for (i = 0; i < CIM_NUM_IBQ; i++, p += 4) {
+ printf("%5s %5x %5u %4u %6x %4x "\
+ "%4u %4u %5u\n",
+ pQname[i],
+ q_cfg_data->base[i], q_cfg_data->size[i],
+ q_cfg_data->thres[i], G_IBQRDADDR(p[0]),
+ G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]),
+ G_QUEEOPCNT(p[3]), G_QUEREMFLITS(p[2]) * 16);
+ }
+
+ for (; i < CIM_NUM_IBQ + CIM_NUM_OBQ; i++, p += 4, wr += 2) {
+ printf("%5s %5x %5u %11x %4x %4u "\
+ "%4u %5u\n",
+ pQname[i],
+ q_cfg_data->base[i], q_cfg_data->size[i],
+ G_QUERDADDR(p[0]) & 0x3fff,
+ wr[0] - q_cfg_data->base[i], G_QUESOPCNT(p[3]),
+ G_QUEEOPCNT(p[3]), G_QUEREMFLITS(p[2]) * 16);
+ }
+
+ return rc;
+}
+
+int
+decompress_buffer_wrapper(struct cudbg_buffer *pc_buff,
+ struct cudbg_buffer *pdc_buff)
+{
+ int rc = 0;
+ pdc_buff->data = malloc(2 * CUDBG_CHUNK_SIZE);
+ if (pdc_buff->data == NULL) {
+ rc = CUDBG_STATUS_NOSPACE;
+ goto err;
+ }
+ pdc_buff->size = 2 * CUDBG_CHUNK_SIZE;
+
+ rc = decompress_buffer(pc_buff, pdc_buff);
+ if (rc == CUDBG_STATUS_SMALL_BUFF) {
+ free(pdc_buff->data);
+ pdc_buff->data = malloc(pdc_buff->size);
+
+ if (pdc_buff->data == NULL) {
+ printf("malloc failed for size %u\n", pdc_buff->size);
+ rc = CUDBG_STATUS_NOSPACE;
+ goto err;
+ }
+ rc = decompress_buffer(pc_buff, pdc_buff);
+ }
+err:
+ return rc;
+}
+
+int
+copy_bin_data(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ const char *fname, struct cudbg_buffer *cudbg_poutbuf)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0;
+
+ if (cudbg_poutbuf->data == NULL)
+ return 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ if (dc_buff.size > cudbg_poutbuf->size) {
+ rc = CUDBG_STATUS_OUTBUFF_OVERFLOW;
+ cudbg_poutbuf->size = dc_buff.size;
+ goto err1;
+ }
+
+ memcpy(cudbg_poutbuf->data, dc_buff.data, dc_buff.size);
+ cudbg_poutbuf->size = dc_buff.size;
+
+err1:
+ return rc;
+}
+
+int
+view_edc0_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ return copy_bin_data(pbuf, ent_hdr, "_cudbg_edc0.bin", cudbg_poutbuf);
+}
+
+int
+view_edc1_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ return copy_bin_data(pbuf, ent_hdr, "_cudbg_edc1.bin", cudbg_poutbuf);
+}
+
+int
+view_mc0_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ return copy_bin_data(pbuf, ent_hdr, "_cudbg_mc0.bin", cudbg_poutbuf);
+}
+
+int
+view_mc1_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ return copy_bin_data(pbuf, ent_hdr, "_cudbg_mc1.bin", cudbg_poutbuf);
+}
+
+int
+view_hma_data(char *pbuf, struct cudbg_entity_hdr *ent_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ return copy_bin_data(pbuf, ent_hdr, "_cudbg_hma.bin", cudbg_poutbuf);
+}
+
+int
+view_sw_state(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ u8 os_type, *caller_string;
+ struct sw_state *swstate;
+ char *os, *fwstate;
+ u32 fw_state;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ swstate = (struct sw_state *) dc_buff.data;
+ fw_state = swstate->fw_state;
+ caller_string = swstate->caller_string;
+ os_type = swstate->os_type;
+
+ printf("\n");
+ if (fw_state & F_PCIE_FW_ERR && G_PCIE_FW_EVAL(fw_state) ==
+ PCIE_FW_EVAL_CRASH)
+ fwstate = "Crashed";
+ else
+ fwstate = "Alive";
+
+ switch (os_type) {
+ case CUDBG_OS_TYPE_WINDOWS:
+ os = "Windows";
+ break;
+ case CUDBG_OS_TYPE_LINUX:
+ os = "Linux";
+ break;
+ case CUDBG_OS_TYPE_ESX:
+ os = "ESX";
+ break;
+ case CUDBG_OS_TYPE_UNKNOWN:
+ default:
+ os = "Unknown";
+ }
+
+ printf("\tFW STATE : %s\n", fwstate);
+ printf("\tOS : %s\n", os);
+ printf("\tCALLER : %s\n", caller_string);
+ printf("\n");
+
+ return rc;
+}
+
+int
+view_cpl_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_tp_cpl_stats *tp_cpl_stats_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ struct tp_cpl_stats stats;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ tp_cpl_stats_buff = (struct struct_tp_cpl_stats *) dc_buff.data;
+ stats = tp_cpl_stats_buff->stats;
+ if (tp_cpl_stats_buff->nchan == NCHAN) {
+ printf(" channel 0"\
+ " channel 1 channel 2 channel 3\n");
+ printf("CPL requests: %10u %10u "\
+ "%10u %10u\n",
+ stats.req[0], stats.req[1], stats.req[2],
+ stats.req[3]);
+ printf("CPL responses: %10u %10u "\
+ "%10u %10u\n",
+ stats.rsp[0], stats.rsp[1], stats.rsp[2],
+ stats.rsp[3]);
+ } else {
+ printf(" channel 0"\
+ " channel 1\n");
+ printf("CPL requests: %10u %10u\n",
+ stats.req[0], stats.req[1]);
+ printf("CPL responses: %10u %10u\n",
+ stats.rsp[0], stats.rsp[1]);
+ }
+
+ return rc;
+}
+
+int
+view_ddp_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct tp_usm_stats *tp_usm_stats_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ tp_usm_stats_buff = (struct tp_usm_stats *) dc_buff.data;
+ printf("Frames: %u\n",
+ tp_usm_stats_buff->frames);
+ printf("Octets: %llu\n",
+ (unsigned long long)tp_usm_stats_buff->octets);
+ printf("Drops: %u\n",
+ tp_usm_stats_buff->drops);
+
+ return rc;
+}
+
+int
+view_macstats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_mac_stats_rev1 *macstats_buff1;
+ struct struct_mac_stats *mac_stats_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ struct port_stats *stats;
+ u32 port_count, i;
+ int rc = 0, rev;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data);
+ if (rev) {
+ macstats_buff1 = (struct struct_mac_stats_rev1 *)(dc_buff.data);
+ port_count = macstats_buff1->port_count;
+ stats = macstats_buff1->stats;
+
+ } else {
+ mac_stats_buff = (struct struct_mac_stats *)(dc_buff.data);
+ port_count = mac_stats_buff->port_count;
+ stats = mac_stats_buff->stats;
+ }
+
+ for (i = 0; i < port_count; i++) {
+ printf("\nMac %d Stats:\n", i);
+ printf("tx_octets "\
+ "%64llu\n", stats[i].tx_octets);
+ printf("tx_frames "\
+ "%64llu\n", stats[i].tx_frames);
+ printf("tx_bcast_frames "\
+ "%64llu\n", stats[i].tx_bcast_frames);
+ printf("tx_mcast_frames "\
+ "%64llu\n", stats[i].tx_mcast_frames);
+ printf("tx_ucast_frames "\
+ "%64llu\n", stats[i].tx_ucast_frames);
+ printf("tx_error_frames "\
+ "%64llu\n", stats[i].tx_error_frames);
+ printf("tx_frames_64 "\
+ "%64llu\n", stats[i].tx_frames_64);
+ printf("tx_frames_65_127 "\
+ "%64llu\n", stats[i].tx_frames_65_127);
+ printf("tx_frames_128_255 "\
+ "%64llu\n", stats[i].tx_frames_128_255);
+ printf("tx_frames_256_511 "\
+ "%64llu\n", stats[i].tx_frames_256_511);
+ printf("tx_frames_512_1023 "\
+ "%64llu\n", stats[i].tx_frames_512_1023);
+ printf("tx_frames_1024_1518 "\
+ "%64llu\n", stats[i].tx_frames_1024_1518);
+ printf("tx_frames_1519_max "\
+ "%64llu\n", stats[i].tx_frames_1519_max);
+ printf("tx_drop "\
+ "%64llu\n", stats[i].tx_drop);
+ printf("tx_pause "\
+ "%64llu\n", stats[i].tx_pause);
+ printf("tx_ppp0 "\
+ "%64llu\n", stats[i].tx_ppp0);
+ printf("tx_ppp1 "\
+ "%64llu\n", stats[i].tx_ppp1);
+ printf("tx_ppp2 "\
+ "%64llu\n", stats[i].tx_ppp2);
+ printf("tx_ppp3 "\
+ "%64llu\n", stats[i].tx_ppp3);
+ printf("tx_ppp4 "\
+ "%64llu\n", stats[i].tx_ppp4);
+ printf("tx_ppp5 "\
+ "%64llu\n", stats[i].tx_ppp5);
+ printf("tx_ppp6 "\
+ "%64llu\n", stats[i].tx_ppp6);
+ printf("tx_ppp7 "\
+ "%64llu\n", stats[i].tx_ppp7);
+ printf("rx_octets "\
+ "%64llu\n", stats[i].rx_octets);
+ printf("rx_frames "\
+ "%64llu\n", stats[i].rx_frames);
+ printf("rx_bcast_frames "\
+ "%64llu\n", stats[i].rx_bcast_frames);
+ printf("rx_mcast_frames "\
+ "%64llu\n", stats[i].rx_mcast_frames);
+ printf("rx_ucast_frames "\
+ "%64llu\n", stats[i].rx_ucast_frames);
+ printf("rx_too_long "\
+ "%64llu\n", stats[i].rx_too_long);
+ printf("rx_jabber "\
+ "%64llu\n", stats[i].rx_jabber);
+ printf("rx_fcs_err "\
+ "%64llu\n", stats[i].rx_fcs_err);
+ printf("rx_len_err "\
+ "%64llu\n", stats[i].rx_len_err);
+ printf("rx_symbol_err "\
+ "%64llu\n", stats[i].rx_symbol_err);
+ printf("rx_runt "\
+ "%64llu\n", stats[i].rx_runt);
+ printf("rx_frames_64 "\
+ "%64llu\n", stats[i].rx_frames_64);
+ printf("rx_frames_65_127 "\
+ "%64llu\n", stats[i].rx_frames_65_127);
+ printf("rx_frames_128_255 "\
+ "%64llu\n", stats[i].rx_frames_128_255);
+ printf("rx_frames_256_511 "\
+ "%64llu\n", stats[i].rx_frames_256_511);
+ printf("rx_frames_512_1023 "\
+ "%64llu\n", stats[i].rx_frames_512_1023);
+ printf("rx_frames_1024_1518 "\
+ "%64llu\n", stats[i].rx_frames_1024_1518);
+ printf("rx_frames_1519_max "\
+ "%64llu\n", stats[i].rx_frames_1519_max);
+ printf("rx_pause "\
+ "%64llu\n", stats[i].rx_pause);
+ printf("rx_ppp0 "\
+ "%64llu\n", stats[i].rx_ppp0);
+ printf("rx_ppp1 "\
+ "%64llu\n", stats[i].rx_ppp1);
+ printf("rx_ppp2 "\
+ "%64llu\n", stats[i].rx_ppp2);
+ printf("rx_ppp3 "\
+ "%64llu\n", stats[i].rx_ppp3);
+ printf("rx_ppp4 "\
+ "%64llu\n", stats[i].rx_ppp4);
+ printf("rx_ppp5 "\
+ "%64llu\n", stats[i].rx_ppp5);
+ printf("rx_ppp6 "\
+ "%64llu\n", stats[i].rx_ppp6);
+ printf("rx_ppp7 "\
+ "%64llu\n", stats[i].rx_ppp7);
+ printf("rx_ovflow0 "\
+ "%64llu\n", stats[i].rx_ovflow0);
+ printf("rx_ovflow1 "\
+ "%64llu\n", stats[i].rx_ovflow1);
+ printf("rx_ovflow2 "\
+ "%64llu\n", stats[i].rx_ovflow2);
+ printf("rx_ovflow3 "\
+ "%64llu\n", stats[i].rx_ovflow3);
+ printf("rx_trunc0 "\
+ "%64llu\n", stats[i].rx_trunc0);
+ printf("rx_trunc1 "\
+ "%64llu\n", stats[i].rx_trunc1);
+ printf("rx_trunc2 "\
+ "%64llu\n", stats[i].rx_trunc2);
+ printf("rx_trunc3 "\
+ "%64llu\n", stats[i].rx_trunc3);
+ }
+
+ return rc;
+}
+
+int
+view_ulptx_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_ulptx_la *ulptx_la_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ void *data;
+ int i, rc = 0, rev;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ data = dc_buff.data + sizeof(struct cudbg_ver_hdr);
+ rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data);
+ switch (rev) {
+ case 0:
+ /* for rev 0 there is no version hdr so
+ * passing dc_buff.data */
+ rc = view_ulptx_la_rev0(dc_buff.data, cudbg_poutbuf);
+ goto err1;
+ case CUDBG_ULPTX_LA_REV:
+ /* for rev 1, print first rev 0 and then remaining of rev 1 */
+ rc = view_ulptx_la_rev0(data, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ ulptx_la_buff = (struct struct_ulptx_la *)data;
+ break;
+ default:
+ printf("Unsupported revision %u. Only supports <= %u\n",
+ rev, CUDBG_ULPTX_LA_REV);
+ goto err1;
+ }
+
+ printf("\n=======================DUMPING ULP_TX_ASIC_DEBUG=======================\n\n");
+
+ for (i = 0; i < CUDBG_NUM_ULPTX_ASIC_READ; i++) {
+ printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
+ A_ULP_TX_ASIC_DEBUG_CTRL, i,
+ "A_ULP_TX_ASIC_DEBUG_CTRL",
+ ulptx_la_buff->rdptr_asic[i],
+ ulptx_la_buff->rdptr_asic[i]);
+ printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
+ A_ULP_TX_ASIC_DEBUG_0,
+ i, "A_ULP_TX_ASIC_DEBUG_0",
+ ulptx_la_buff->rddata_asic[i][0],
+ ulptx_la_buff->rddata_asic[i][0]);
+ printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
+ A_ULP_TX_ASIC_DEBUG_1,
+ i, "A_ULP_TX_ASIC_DEBUG_1",
+ ulptx_la_buff->rddata_asic[i][1],
+ ulptx_la_buff->rddata_asic[i][1]);
+ printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
+ A_ULP_TX_ASIC_DEBUG_2,
+ i, "A_ULP_TX_ASIC_DEBUG_2",
+ ulptx_la_buff->rddata_asic[i][2],
+ ulptx_la_buff->rddata_asic[i][2]);
+ printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
+ A_ULP_TX_ASIC_DEBUG_3,
+ i, "A_ULP_TX_ASIC_DEBUG_3",
+ ulptx_la_buff->rddata_asic[i][3],
+ ulptx_la_buff->rddata_asic[i][3]);
+ printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
+ A_ULP_TX_ASIC_DEBUG_4,
+ i, "A_ULP_TX_ASIC_DEBUG_4",
+ ulptx_la_buff->rddata_asic[i][4],
+ ulptx_la_buff->rddata_asic[i][4]);
+ printf("[0x%x][%#2x] %-24s %#-16x [%u]\n",
+ PM_RX_BASE_ADDR,
+ i, "PM_RX_BASE_ADDR",
+ ulptx_la_buff->rddata_asic[i][5],
+ ulptx_la_buff->rddata_asic[i][5]);
+ printf("\n");
+ }
+
+err1:
+ return rc;
+
+}
+
+int
+view_ulprx_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_ulprx_la *ulprx_la_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0;
+ u32 i, *p;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ ulprx_la_buff = (struct struct_ulprx_la *) dc_buff.data;
+ p = ulprx_la_buff->data;
+
+ printf(
+ " Pcmd Type Message Data\n");
+ for (i = 0; i < ulprx_la_buff->size; i++, p += 8)
+ printf(
+ "%08x%08x %4x %08x %08x%08x%08x%08x\n",
+ p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
+
+ return rc;
+}
+
+int
+view_wc_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_wc_stats *wc_stats_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ wc_stats_buff = (struct struct_wc_stats *) dc_buff.data;
+
+ printf("WriteCoalSuccess: %u\n",
+ wc_stats_buff->wr_cl_success);
+ printf("WriteCoalFail: %u\n",
+ wc_stats_buff->wr_cl_fail);
+
+ return rc;
+}
+
+static int
+field_desc_show(u64 v, const struct field_desc *p,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ int line_size = 0;
+ char buf[32];
+ int rc = 0;
+
+ while (p->name) {
+ u64 mask = (1ULL << p->width) - 1;
+ int len = snprintf(buf, sizeof(buf), "%s: %llu", p->name,
+ ((unsigned long long)v >> p->start) & mask);
+
+ if (line_size + len >= 79) {
+ line_size = 8;
+ printf("\n ");
+ }
+ printf("%s ", buf);
+ line_size += len + 1;
+ p++;
+ }
+ printf("\n");
+
+ return rc;
+}
+
+static int
+tp_la_show(void *v, int idx, struct cudbg_buffer *cudbg_poutbuf)
+{
+ const u64 *p = v;
+ int rc;
+
+ rc = field_desc_show(*p, tp_la0, cudbg_poutbuf);
+ return rc;
+}
+
+static int
+tp_la_show2(void *v, int idx, struct cudbg_buffer *cudbg_poutbuf)
+{
+ const u64 *p = v;
+ int rc;
+
+ if (idx)
+ printf("'\n");
+ rc = field_desc_show(p[0], tp_la0, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
+ rc = field_desc_show(p[1], tp_la0, cudbg_poutbuf);
+
+err1:
+ return rc;
+}
+
+static int
+tp_la_show3(void *v, int idx, struct cudbg_buffer *cudbg_poutbuf)
+{
+ const u64 *p = v;
+ int rc;
+
+ if (idx)
+ printf("\n");
+ rc = field_desc_show(p[0], tp_la0, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
+ rc = field_desc_show(p[1], (p[0] & BIT(17)) ? tp_la2 : tp_la1,
+ cudbg_poutbuf);
+
+err1:
+ return rc;
+}
+
+int
+view_tp_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ static int (*la_show) (void *v, int idx,
+ struct cudbg_buffer *cudbg_poutbuf);
+ struct cudbg_buffer c_buff, dc_buff;
+ struct struct_tp_la *tp_la_buff;
+ int i, rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ tp_la_buff = (struct struct_tp_la *) dc_buff.data;
+ switch (tp_la_buff->mode) {
+ case 2:
+ la_show = tp_la_show2;
+ break;
+ case 3:
+ la_show = tp_la_show3;
+ break;
+ default:
+ la_show = tp_la_show;
+ }
+
+ for (i = 0; i < TPLA_SIZE/2; i++) {
+ rc = la_show((u64 *)tp_la_buff->data + i*2, i, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ }
+
+err1:
+ return rc;
+}
+
+static unsigned long
+do_div(unsigned long *number, u32 divisor)
+{
+ unsigned long remainder = *number % divisor;
+
+ (*number) /= divisor;
+ return remainder;
+}
+
+static int
+string_get_size(unsigned long size,
+ const enum string_size_units units, char *buf,
+ int len)
+{
+ const char *units_10[] = {
+ "B", "kB", "MB", "GB", "TB", "PB",
+ "EB", "ZB", "YB", NULL
+ };
+ const char *units_2[] = {
+ "B", "KiB", "MiB", "GiB", "TiB", "PiB",
+ "EiB", "ZiB", "YiB", NULL
+ };
+ const char **units_str[2];/* = {units_10, units_2};*/
+ const u32 divisor[] = {1000, 1024};
+ unsigned long remainder = 0;
+ unsigned long sf_cap = 0;
+ char tmp[8] = {0};
+ int i, j;
+
+ tmp[0] = '\0';
+ i = 0;
+
+ units_str[STRING_UNITS_10] = units_10;
+ units_str[STRING_UNITS_2] = units_2;
+
+ if (size >= divisor[units]) {
+ while (size >= divisor[units] && units_str[units][i]) {
+ remainder = do_div(&size, divisor[units]);
+ i++;
+ }
+
+ sf_cap = size;
+
+ for (j = 0; sf_cap*10 < 1000; j++)
+ sf_cap *= 10;
+
+ if (j) {
+ remainder *= 1000;
+ do_div(&remainder, divisor[units]);
+
+ (void)snprintf(tmp, sizeof(tmp), ".%03lu",
+ (unsigned long)remainder);
+ tmp[j + 1] = '\0';
+ }
+ }
+
+ (void)snprintf(buf, len, "%lu%s %s", (unsigned long)size, tmp,
+ units_str[units][i]);
+
+ return 0;
+}
+
+static int
+mem_region_show(const char *name, u32 from, u32 to,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ char buf[40] = {0};
+ int rc = 0;
+
+ string_get_size((u64)to - from + 1, STRING_UNITS_2,
+ buf, sizeof(buf));
+ printf("%-14s %#x-%#x [%s]\n", name, from,
+ to, buf);
+
+ return rc;
+} /* mem_region_show */
+
+int
+view_meminfo(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_meminfo *meminfo_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ u32 i, lo, idx;
+ int rc = 0, rev;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data);
+ switch (rev) {
+ case 0:
+ meminfo_buff = (struct struct_meminfo *)dc_buff.data;
+ break;
+ case CUDBG_MEMINFO_REV:
+ meminfo_buff = (struct struct_meminfo *)
+ (dc_buff.data +
+ sizeof(struct cudbg_ver_hdr));
+ break;
+ default:
+ printf("Unsupported revision %u. Only supports <= %u\n",
+ rev, CUDBG_MEMINFO_REV);
+ goto err1;
+ }
+
+ for (lo = 0; lo < meminfo_buff->avail_c; lo++) {
+ idx = meminfo_buff->avail[lo].idx;
+ rc = mem_region_show(memory[idx], meminfo_buff->avail[lo].base,
+ meminfo_buff->avail[lo].limit - 1,
+ cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ }
+
+ for (i = 0; i < meminfo_buff->mem_c; i++) {
+ if (meminfo_buff->mem[i].idx >= ARRAY_SIZE(region))
+ continue; /* skip holes */
+ if (!(meminfo_buff->mem[i].limit))
+ meminfo_buff->mem[i].limit =
+ i < meminfo_buff->mem_c - 1 ?
+ meminfo_buff->mem[i + 1].base - 1 : ~0;
+
+ idx = meminfo_buff->mem[i].idx;
+ rc = mem_region_show(region[idx], meminfo_buff->mem[i].base,
+ meminfo_buff->mem[i].limit, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ }
+
+ rc = mem_region_show("uP RAM:", meminfo_buff->up_ram_lo,
+ meminfo_buff->up_ram_hi, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ rc = mem_region_show("uP Extmem2:", meminfo_buff->up_extmem2_lo,
+ meminfo_buff->up_extmem2_hi, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+
+ if (rev == 0) {
+ struct struct_meminfo_rev0 *meminfo_buff_rev0 =
+ (struct struct_meminfo_rev0 *)meminfo_buff;
+
+ printf("\n%u Rx pages of size %uKiB for %u channels\n",
+ meminfo_buff_rev0->rx_pages_data[0],
+ meminfo_buff_rev0->rx_pages_data[1],
+ meminfo_buff_rev0->rx_pages_data[2]);
+ printf("%u Tx pages of size %u%ciB for %u channels\n\n",
+ meminfo_buff_rev0->tx_pages_data[0],
+ meminfo_buff_rev0->tx_pages_data[1],
+ meminfo_buff_rev0->tx_pages_data[2],
+ meminfo_buff_rev0->tx_pages_data[3]);
+ } else if (rev == CUDBG_MEMINFO_REV) {
+ printf("\n%u Rx pages (%u free) of size %uKiB for %u channels\n",
+ meminfo_buff->rx_pages_data[0],
+ meminfo_buff->free_rx_cnt,
+ meminfo_buff->rx_pages_data[1],
+ meminfo_buff->rx_pages_data[2]);
+ printf("%u Tx pages (%u free) of size %u%ciB for %u channels\n",
+ meminfo_buff->tx_pages_data[0],
+ meminfo_buff->free_tx_cnt,
+ meminfo_buff->tx_pages_data[1],
+ meminfo_buff->tx_pages_data[2],
+ meminfo_buff->tx_pages_data[3]);
+ printf("%u p-structs (%u free)\n\n",
+ meminfo_buff->p_structs,
+ meminfo_buff->pstructs_free_cnt);
+ }
+
+ for (i = 0; i < 4; i++) {
+ printf("Port %d using %u pages out "\
+ "of %u allocated\n",
+ i, meminfo_buff->port_used[i],
+ meminfo_buff->port_alloc[i]);
+ }
+
+ for (i = 0; i < NCHAN; i++) {
+ printf("Loopback %d using %u pages "\
+ "out of %u allocated\n",
+ i, meminfo_buff->loopback_used[i],
+ meminfo_buff->loopback_alloc[i]);
+ }
+
+err1:
+ return rc;
+}
+
+int
+view_lb_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_lb_stats *lb_stats_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ struct lb_port_stats *tmp_stats;
+ int i, j, rc = 0;
+ u64 *p0, *p1;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ lb_stats_buff = (struct struct_lb_stats *) dc_buff.data;
+ tmp_stats = lb_stats_buff->s;
+ for (i = 0; i < lb_stats_buff->nchan; i += 2, tmp_stats += 2) {
+ p0 = &(tmp_stats[0].octets);
+ p1 = &(tmp_stats[1].octets);
+ printf("%s "\
+ "Loopback %u Loopback %u\n",
+ i == 0 ? "" : "\n", i, i + 1);
+
+ for (j = 0; j < ARRAY_SIZE(lb_stat_name); j++)
+ printf("%-17s %20llu "\
+ "%20llu\n", lb_stat_name[j],
+ (unsigned long long)*p0++,
+ (unsigned long long)*p1++);
+ }
+
+ return rc;
+}
+
+int
+view_rdma_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct tp_rdma_stats *rdma_stats_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ rdma_stats_buff = (struct tp_rdma_stats *) dc_buff.data;
+ printf("NoRQEModDefferals: %u\n",
+ rdma_stats_buff->rqe_dfr_mod);
+ printf("NoRQEPktDefferals: %u\n",
+ rdma_stats_buff->rqe_dfr_pkt);
+
+ return rc;
+}
+
+int
+view_clk_info(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_clk_info *clk_info_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ char tmp[32] = { 0 };
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ clk_info_buff = (struct struct_clk_info *) dc_buff.data;
+
+ unit_conv(tmp, 32, clk_info_buff->cclk_ps, 1000);
+ printf("Core clock period: %s ns\n", tmp);
+
+ unit_conv(tmp, 32, clk_info_buff->cclk_ps << clk_info_buff->tre,
+ 1000000);
+ printf("TP timer tick: %s us\n", tmp);
+
+ unit_conv(tmp, 32,
+ clk_info_buff->cclk_ps << G_TIMESTAMPRESOLUTION(clk_info_buff->res),
+ 1000000);
+ printf("TCP timestamp tick: %s us\n", tmp);
+
+ unit_conv(tmp, 32, clk_info_buff->cclk_ps << clk_info_buff->dack_re,
+ 1000000);
+ printf("DACK tick: %s us\n", tmp);
+
+ printf("DACK timer: %u us\n",
+ clk_info_buff->dack_timer);
+ printf("Retransmit min: %llu us\n",
+ clk_info_buff->retransmit_min);
+ printf("Retransmit max: %llu us\n",
+ clk_info_buff->retransmit_max);
+ printf("Persist timer min: %llu us\n",
+ clk_info_buff->persist_timer_min);
+ printf("Persist timer max: %llu us\n",
+ clk_info_buff->persist_timer_max);
+ printf("Keepalive idle timer: %llu us\n",
+ clk_info_buff->keepalive_idle_timer);
+ printf("Keepalive interval: %llu us\n",
+ clk_info_buff->keepalive_interval);
+ printf("Initial SRTT: %llu us\n",
+ clk_info_buff->initial_srtt);
+ printf("FINWAIT2 timer: %llu us\n",
+ clk_info_buff->finwait2_timer);
+
+ return rc;
+}
+
+int
+view_cim_pif_la(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct cim_pif_la *cim_pif_la_buff;
+ int i, rc = 0;
+ u32 *p;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ cim_pif_la_buff = (struct cim_pif_la *) dc_buff.data;
+ p = (u32 *)cim_pif_la_buff->data;
+
+ printf("Cntl ID DataBE Addr "\
+ " Data\n");
+ for (i = 0; i < cim_pif_la_buff->size; i++, p = p + 6)
+ printf(" %02x %02x %04x %08x "\
+ "%08x%08x%08x%08x\n",
+ (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f,
+ p[5] & 0xffff, p[4], p[3], p[2], p[1], p[0]);
+
+ p = (u32 *) cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE;
+
+ printf("\nCntl ID Data\n");
+ for (i = 0; i < cim_pif_la_buff->size; i++, p = p + 6)
+ printf(" %02x %02x "\
+ "%08x%08x%08x%08x\n",
+ (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1],
+ p[0]);
+
+ return rc;
+}
+
+int
+view_fcoe_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_tp_fcoe_stats *tp_fcoe_stats_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ struct tp_fcoe_stats stats[4];
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ tp_fcoe_stats_buff = (struct struct_tp_fcoe_stats *) dc_buff.data;
+ memcpy(stats, tp_fcoe_stats_buff->stats, sizeof(stats));
+
+ if (tp_fcoe_stats_buff->nchan == NCHAN) {
+ printf(" channel "\
+ "0 channel 1 channel 2 "\
+ "channel 3\n");
+ printf("octetsDDP: %16llu %16llu "\
+ "%16llu %16llu\n",
+ stats[0].octets_ddp, stats[1].octets_ddp,
+ stats[2].octets_ddp, stats[3].octets_ddp);
+ printf("framesDDP: %16u %16u %16u "\
+ "%16u\n",
+ stats[0].frames_ddp, stats[1].frames_ddp,
+ stats[2].frames_ddp, stats[3].frames_ddp);
+ printf("framesDrop: %16u %16u %16u "\
+ "%16u\n",
+ stats[0].frames_drop, stats[1].frames_drop,
+ stats[2].frames_drop, stats[3].frames_drop);
+ } else {
+ printf(" channel "\
+ "0 channel 1\n");
+ printf("octetsDDP: %16llu "\
+ "%16llu\n",
+ stats[0].octets_ddp, stats[1].octets_ddp);
+ printf("framesDDP: %16u %16u\n",
+ stats[0].frames_ddp, stats[1].frames_ddp);
+ printf("framesDrop: %16u %16u\n",
+ stats[0].frames_drop, stats[1].frames_drop);
+ }
+
+ return rc;
+}
+
+int
+view_tp_err_stats_show(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf,
+ enum chip_type chip)
+{
+ struct struct_tp_err_stats *tp_err_stats_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ struct tp_err_stats stats;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ tp_err_stats_buff = (struct struct_tp_err_stats *) dc_buff.data;
+ stats = tp_err_stats_buff->stats;
+ if (tp_err_stats_buff->nchan == NCHAN) {
+ printf(" channel 0"\
+ " channel 1 channel 2 channel 3\n");
+ printf("macInErrs: %10u %10u "\
+ "%10u %10u\n",
+ stats.mac_in_errs[0], stats.mac_in_errs[1],
+ stats.mac_in_errs[2], stats.mac_in_errs[3]);
+ printf("hdrInErrs: %10u %10u "\
+ "%10u %10u\n",
+ stats.hdr_in_errs[0], stats.hdr_in_errs[1],
+ stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
+ printf("tcpInErrs: %10u %10u "\
+ "%10u %10u\n",
+ stats.tcp_in_errs[0], stats.tcp_in_errs[1],
+ stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
+ printf("tcp6InErrs: %10u %10u "\
+ "%10u %10u\n",
+ stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
+ stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
+ printf("tnlCongDrops: %10u %10u "\
+ "%10u %10u\n",
+ stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
+ stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
+ printf("tnlTxDrops: %10u %10u "\
+ "%10u %10u\n",
+ stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
+ stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
+ printf("ofldVlanDrops: %10u %10u "\
+ "%10u %10u\n",
+ stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
+ stats.ofld_vlan_drops[2],
+ stats.ofld_vlan_drops[3]);
+ printf("ofldChanDrops: %10u %10u "\
+ "%10u %10u\n\n",
+ stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
+ stats.ofld_chan_drops[2],
+ stats.ofld_chan_drops[3]);
+ } else {
+ printf(" channel 0"\
+ " channel 1\n");
+ printf("macInErrs: %10u %10u\n",
+ stats.mac_in_errs[0], stats.mac_in_errs[1]);
+ printf("hdrInErrs: %10u %10u\n",
+ stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
+ printf("tcpInErrs: %10u %10u\n",
+ stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
+ printf("tcp6InErrs: %10u %10u\n",
+ stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
+ printf("tnlCongDrops: %10u %10u\n",
+ stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
+ printf("tnlTxDrops: %10u %10u\n",
+ stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
+ printf("ofldVlanDrops: %10u %10u\n",
+ stats.ofld_vlan_drops[0],
+ stats.ofld_vlan_drops[1]);
+ printf("ofldChanDrops: %10u %10u"\
+ "\n\n", stats.ofld_chan_drops[0],
+ stats.ofld_chan_drops[1]);
+ }
+
+ printf("ofldNoNeigh: %u\nofldCongDefer: "\
+ " %u\n", stats.ofld_no_neigh, stats.ofld_cong_defer);
+
+ return rc;
+}
+
+int
+view_tcp_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_tcp_stats *tcp_stats_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ tcp_stats_buff = (struct struct_tcp_stats *) dc_buff.data;
+ printf(" IP"\
+ " IPv6\n");
+ printf("OutRsts: %20u %20u\n",
+ tcp_stats_buff->v4.tcp_out_rsts,
+ tcp_stats_buff->v6.tcp_out_rsts);
+ printf("InSegs: %20llu %20llu\n",
+ (unsigned long long)(tcp_stats_buff->v4.tcp_in_segs),
+ (unsigned long long)(tcp_stats_buff->v6.tcp_in_segs));
+ printf("OutSegs: %20llu %20llu\n",
+ (unsigned long long)(tcp_stats_buff->v4.tcp_out_segs),
+ (unsigned long long)(tcp_stats_buff->v6.tcp_out_segs));
+ printf("RetransSegs: %20llu %20llu\n",
+ (unsigned long long)(tcp_stats_buff->v4.tcp_retrans_segs),
+ (unsigned long long)(tcp_stats_buff->v6.tcp_retrans_segs));
+
+ return rc;
+}
+
+int
+view_hw_sched(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct struct_hw_sched *hw_sched_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ int i, rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ hw_sched_buff = (struct struct_hw_sched *)dc_buff.data;
+
+ printf("Scheduler Mode Channel Rate "\
+ "(Kbps) Class IPG (0.1 ns) Flow IPG (us)\n");
+ for (i = 0; i < NTX_SCHED; ++i, hw_sched_buff->map >>= 2) {
+ printf(" %u %-5s %u"\
+ " ", i,
+ (hw_sched_buff->mode & (1 << i)) ?
+ "flow" : "class",
+ hw_sched_buff->map & 3);
+ if (hw_sched_buff->kbps[i]) {
+ printf("%9u ",
+ hw_sched_buff->kbps[i]);
+ } else {
+ printf(" disabled ");
+ }
+
+ if (hw_sched_buff->ipg[i]) {
+ printf("%13u ",
+ hw_sched_buff->ipg[i]);
+ } else {
+ printf(" disabled "\
+ " ");
+ }
+
+ if (hw_sched_buff->pace_tab[i]) {
+ printf("%10u\n",
+ hw_sched_buff->pace_tab[i]);
+ } else {
+ printf(" disabled\n");
+ }
+ }
+
+ return rc;
+}
+
+int
+view_pm_stats(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ static const char * const tx_pm_stats[] = {
+ "Read:", "Write bypass:", "Write mem:", "Bypass + mem:"
+ };
+ static const char * const rx_pm_stats[] = {
+ "Read:", "Write bypass:", "Write mem:", "Flush:"
+ };
+ struct struct_pm_stats *pm_stats_buff;
+ struct cudbg_buffer c_buff, dc_buff;
+ int i, rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ pm_stats_buff = (struct struct_pm_stats *)dc_buff.data;
+
+ printf("%13s %10s %20s\n", " ", "Tx pcmds",
+ "Tx bytes");
+ for (i = 0; i < PM_NSTATS - 1; i++)
+ printf("%-13s %10u %20llu\n",
+ tx_pm_stats[i], pm_stats_buff->tx_cnt[i],
+ pm_stats_buff->tx_cyc[i]);
+
+ printf("%13s %10s %20s\n", " ", "Rx pcmds",
+ "Rx bytes");
+ for (i = 0; i < PM_NSTATS - 1; i++)
+ printf("%-13s %10u %20llu\n",
+ rx_pm_stats[i], pm_stats_buff->rx_cnt[i],
+ pm_stats_buff->rx_cyc[i]);
+
+ if (CHELSIO_CHIP_VERSION(chip) > CHELSIO_T5) {
+ /* In T5 the granularity of the total wait is too fine.
+ * It is not useful as it reaches the max value too fast.
+ * Hence display this Input FIFO wait for T6 onwards.
+ */
+ printf("%13s %10s %20s\n",
+ " ", "Total wait", "Total Occupancy");
+ printf("Tx FIFO wait "
+ "%10u %20llu\n", pm_stats_buff->tx_cnt[i],
+ pm_stats_buff->tx_cyc[i]);
+ printf("Rx FIFO wait %10u "
+ "%20llu\n", pm_stats_buff->rx_cnt[i],
+ pm_stats_buff->rx_cyc[i]);
+
+ /* Skip index 6 as there is nothing useful here */
+ i += 2;
+
+ /* At index 7, a new stat for read latency (count, total wait)
+ * is added.
+ */
+ printf("%13s %10s %20s\n",
+ " ", "Reads", "Total wait");
+ printf("Tx latency "
+ "%10u %20llu\n", pm_stats_buff->tx_cnt[i],
+ pm_stats_buff->tx_cyc[i]);
+ printf("Rx latency "
+ "%10u %20llu\n", pm_stats_buff->rx_cnt[i],
+ pm_stats_buff->rx_cyc[i]);
+ }
+
+ return rc;
+}
+
+int
+view_path_mtu(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0;
+ u16 *mtus;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ mtus = (u16 *)dc_buff.data;
+ printf("%u %u %u %u %u %u %u %u %u %u %u %u"\
+ " %u %u %u %u\n",
+ mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5],
+ mtus[6], mtus[7], mtus[8], mtus[9], mtus[10], mtus[11],
+ mtus[12], mtus[13], mtus[14], mtus[15]);
+
+ return rc;
+}
+
+int
+view_rss_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ static const char * const keymode[] = {
+ "global",
+ "global and per-VF scramble",
+ "per-PF and per-VF scramble",
+ "per-VF and per-VF scramble",
+ };
+ struct cudbg_buffer c_buff, dc_buff;
+ struct rss_config *struct_rss_conf;
+ u32 rssconf;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ struct_rss_conf = (struct rss_config *)dc_buff.data;
+ rssconf = struct_rss_conf->tp_rssconf;
+ printf("TP_RSS_CONFIG: %#x\n", rssconf);
+ printf(" Tnl4TupEnIpv6: %3s\n",
+ yesno(rssconf & F_TNL4TUPENIPV6));
+ printf(" Tnl2TupEnIpv6: %3s\n",
+ yesno(rssconf & F_TNL2TUPENIPV6));
+ printf(" Tnl4TupEnIpv4: %3s\n",
+ yesno(rssconf & F_TNL4TUPENIPV4));
+ printf(" Tnl2TupEnIpv4: %3s\n",
+ yesno(rssconf & F_TNL2TUPENIPV4));
+ printf(" TnlTcpSel: %3s\n",
+ yesno(rssconf & F_TNLTCPSEL));
+ printf(" TnlIp6Sel: %3s\n",
+ yesno(rssconf & F_TNLIP6SEL));
+ printf(" TnlVrtSel: %3s\n",
+ yesno(rssconf & F_TNLVRTSEL));
+ printf(" TnlMapEn: %3s\n",
+ yesno(rssconf & F_TNLMAPEN));
+ printf(" OfdHashSave: %3s\n",
+ yesno(rssconf & F_OFDHASHSAVE));
+ printf(" OfdVrtSel: %3s\n",
+ yesno(rssconf & F_OFDVRTSEL));
+ printf(" OfdMapEn: %3s\n",
+ yesno(rssconf & F_OFDMAPEN));
+ printf(" OfdLkpEn: %3s\n",
+ yesno(rssconf & F_OFDLKPEN));
+ printf(" Syn4TupEnIpv6: %3s\n",
+ yesno(rssconf & F_SYN4TUPENIPV6));
+ printf(" Syn2TupEnIpv6: %3s\n",
+ yesno(rssconf & F_SYN2TUPENIPV6));
+ printf(" Syn4TupEnIpv4: %3s\n",
+ yesno(rssconf & F_SYN4TUPENIPV4));
+ printf(" Syn2TupEnIpv4: %3s\n",
+ yesno(rssconf & F_SYN2TUPENIPV4));
+ printf(" Syn4TupEnIpv6: %3s\n",
+ yesno(rssconf & F_SYN4TUPENIPV6));
+ printf(" SynIp6Sel: %3s\n",
+ yesno(rssconf & F_SYNIP6SEL));
+ printf(" SynVrt6Sel: %3s\n",
+ yesno(rssconf & F_SYNVRTSEL));
+ printf(" SynMapEn: %3s\n",
+ yesno(rssconf & F_SYNMAPEN));
+ printf(" SynLkpEn: %3s\n",
+ yesno(rssconf & F_SYNLKPEN));
+ printf(" ChnEn: %3s\n",
+ yesno(rssconf & F_CHANNELENABLE));
+ printf(" PrtEn: %3s\n",
+ yesno(rssconf & F_PORTENABLE));
+ printf(" TnlAllLkp: %3s\n",
+ yesno(rssconf & F_TNLALLLOOKUP));
+ printf(" VrtEn: %3s\n",
+ yesno(rssconf & F_VIRTENABLE));
+ printf(" CngEn: %3s\n",
+ yesno(rssconf & F_CONGESTIONENABLE));
+ printf(" HashToeplitz: %3s\n",
+ yesno(rssconf & F_HASHTOEPLITZ));
+ printf(" Udp4En: %3s\n",
+ yesno(rssconf & F_UDPENABLE));
+ printf(" Disable: %3s\n",
+ yesno(rssconf & F_DISABLE));
+
+ rssconf = struct_rss_conf->tp_rssconf_tnl;
+ printf("TP_RSS_CONFIG_TNL: %#x\n",
+ rssconf);
+ printf(" MaskSize: %3d\n",
+ G_MASKSIZE(rssconf));
+ printf(" MaskFilter: %3d\n",
+ G_MASKFILTER(rssconf));
+ if (CHELSIO_CHIP_VERSION(struct_rss_conf->chip) > CHELSIO_T5) {
+ printf(" HashAll: %3s\n",
+ yesno(rssconf & F_HASHALL));
+ printf(" HashEth: %3s\n",
+ yesno(rssconf & F_HASHETH));
+ }
+ printf(" UseWireCh: %3s\n",
+ yesno(rssconf & F_USEWIRECH));
+
+ rssconf = struct_rss_conf->tp_rssconf_ofd;
+ printf("TP_RSS_CONFIG_OFD: %#x\n",
+ rssconf);
+ printf(" MaskSize: %3d\n",
+ G_MASKSIZE(rssconf));
+ printf(" RRCplMapEn: %3s\n",
+ yesno(rssconf & F_RRCPLMAPEN));
+ printf(" RRCplQueWidth: %3d\n",
+ G_RRCPLQUEWIDTH(rssconf));
+
+ rssconf = struct_rss_conf->tp_rssconf_syn;
+ printf("TP_RSS_CONFIG_SYN: %#x\n",
+ rssconf);
+ printf(" MaskSize: %3d\n",
+ G_MASKSIZE(rssconf));
+ printf(" UseWireCh: %3s\n",
+ yesno(rssconf & F_USEWIRECH));
+
+ rssconf = struct_rss_conf->tp_rssconf_vrt;
+ printf("TP_RSS_CONFIG_VRT: %#x\n",
+ rssconf);
+ if (CHELSIO_CHIP_VERSION(struct_rss_conf->chip) > CHELSIO_T5) {
+ printf(" KeyWrAddrX: %3d\n",
+ G_KEYWRADDRX(rssconf));
+ printf(" KeyExtend: %3s\n",
+ yesno(rssconf & F_KEYEXTEND));
+ }
+ printf(" VfRdRg: %3s\n",
+ yesno(rssconf & F_VFRDRG));
+ printf(" VfRdEn: %3s\n",
+ yesno(rssconf & F_VFRDEN));
+ printf(" VfPerrEn: %3s\n",
+ yesno(rssconf & F_VFPERREN));
+ printf(" KeyPerrEn: %3s\n",
+ yesno(rssconf & F_KEYPERREN));
+ printf(" DisVfVlan: %3s\n",
+ yesno(rssconf & F_DISABLEVLAN));
+ printf(" EnUpSwt: %3s\n",
+ yesno(rssconf & F_ENABLEUP0));
+ printf(" HashDelay: %3d\n",
+ G_HASHDELAY(rssconf));
+ if (CHELSIO_CHIP_VERSION(struct_rss_conf->chip) <= CHELSIO_T5) {
+ printf(" VfWrAddr: %3d\n",
+ G_VFWRADDR(rssconf));
+ } else {
+ printf(" VfWrAddr: %3d\n",
+ G_T6_VFWRADDR(rssconf));
+ }
+ printf(" KeyMode: %s\n",
+ keymode[G_KEYMODE(rssconf)]);
+ printf(" VfWrEn: %3s\n",
+ yesno(rssconf & F_VFWREN));
+ printf(" KeyWrEn: %3s\n",
+ yesno(rssconf & F_KEYWREN));
+ printf(" KeyWrAddr: %3d\n",
+ G_KEYWRADDR(rssconf));
+
+ rssconf = struct_rss_conf->tp_rssconf_cng;
+ printf("TP_RSS_CONFIG_CNG: %#x\n",
+ rssconf);
+ printf(" ChnCount3: %3s\n",
+ yesno(rssconf & F_CHNCOUNT3));
+ printf(" ChnCount2: %3s\n",
+ yesno(rssconf & F_CHNCOUNT2));
+ printf(" ChnCount1: %3s\n",
+ yesno(rssconf & F_CHNCOUNT1));
+ printf(" ChnCount0: %3s\n",
+ yesno(rssconf & F_CHNCOUNT0));
+ printf(" ChnUndFlow3: %3s\n",
+ yesno(rssconf & F_CHNUNDFLOW3));
+ printf(" ChnUndFlow2: %3s\n",
+ yesno(rssconf & F_CHNUNDFLOW2));
+ printf(" ChnUndFlow1: %3s\n",
+ yesno(rssconf & F_CHNUNDFLOW1));
+ printf(" ChnUndFlow0: %3s\n",
+ yesno(rssconf & F_CHNUNDFLOW0));
+ printf(" RstChn3: %3s\n",
+ yesno(rssconf & F_RSTCHN3));
+ printf(" RstChn2: %3s\n",
+ yesno(rssconf & F_RSTCHN2));
+ printf(" RstChn1: %3s\n",
+ yesno(rssconf & F_RSTCHN1));
+ printf(" RstChn0: %3s\n",
+ yesno(rssconf & F_RSTCHN0));
+ printf(" UpdVld: %3s\n",
+ yesno(rssconf & F_UPDVLD));
+ printf(" Xoff: %3s\n",
+ yesno(rssconf & F_XOFF));
+ printf(" UpdChn3: %3s\n",
+ yesno(rssconf & F_UPDCHN3));
+ printf(" UpdChn2: %3s\n",
+ yesno(rssconf & F_UPDCHN2));
+ printf(" UpdChn1: %3s\n",
+ yesno(rssconf & F_UPDCHN1));
+ printf(" UpdChn0: %3s\n",
+ yesno(rssconf & F_UPDCHN0));
+ printf(" Queue: %3d\n",
+ G_QUEUE(rssconf));
+
+ return rc;
+}
+
+int
+view_rss_key(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0;
+ u32 *key;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ key = (u32 *)dc_buff.data;
+ printf(
+ "%08x%08x%08x%08x%08x%08x%08x%08x%08x%08x\n",
+ key[9], key[8], key[7], key[6], key[5], key[4],
+ key[3], key[2], key[1], key[0]);
+
+ return rc;
+}
+
+int
+view_rss_vf_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct rss_vf_conf *vfconf;
+ int i, rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ vfconf = (struct rss_vf_conf *) dc_buff.data;
+ printf(" RSS Hash "\
+ "Tuple Enable\n");
+ printf(" Enable IVF Dis Enb IPv6 "\
+ " IPv4 UDP Def Secret Key\n");
+ printf(" VF Chn Prt Map VLAN uP Four "\
+ "Two Four Two Four Que Idx Hash\n");
+ for (i = 0; i < dc_buff.offset/sizeof(*vfconf); i += 1) {
+ printf("%3d %3s %3s %3d %3s %3s"\
+ " %3s %3s %3s %3s %3s %4d %3d %#10x\n",
+ i, yesno(vfconf->rss_vf_vfh & F_VFCHNEN),
+ yesno(vfconf->rss_vf_vfh & F_VFPRTEN),
+ G_VFLKPIDX(vfconf->rss_vf_vfh),
+ yesno(vfconf->rss_vf_vfh & F_VFVLNEX),
+ yesno(vfconf->rss_vf_vfh & F_VFUPEN),
+ yesno(vfconf->rss_vf_vfh & F_VFIP4FOURTUPEN),
+ yesno(vfconf->rss_vf_vfh & F_VFIP6TWOTUPEN),
+ yesno(vfconf->rss_vf_vfh & F_VFIP4FOURTUPEN),
+ yesno(vfconf->rss_vf_vfh & F_VFIP4TWOTUPEN),
+ yesno(vfconf->rss_vf_vfh & F_ENABLEUDPHASH),
+ G_DEFAULTQUEUE(vfconf->rss_vf_vfh),
+ G_KEYINDEX(vfconf->rss_vf_vfh),
+ vfconf->rss_vf_vfl);
+
+ vfconf++;
+ }
+
+ return rc;
+}
+
+int
+view_rss_pf_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct rss_pf_conf *pfconf;
+ int i, rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ pfconf = (struct rss_pf_conf *) dc_buff.data;
+ printf("PF Map Index Size = %d\n\n",
+ G_LKPIDXSIZE(pfconf->rss_pf_map));
+ printf(" RSS PF VF "\
+ "Hash Tuple Enable Default\n");
+ printf(" Enable IPF Mask Mask "\
+ "IPv6 IPv4 UDP Queue\n");
+ printf(" PF Map Chn Prt Map Size Size "\
+ "Four Two Four Two Four Ch1 Ch0\n");
+
+#define G_PFnLKPIDX(map, n) \
+ (((map) >> S_PF1LKPIDX*(n)) & M_PF0LKPIDX)
+#define G_PFnMSKSIZE(mask, n) \
+ (((mask) >> S_PF1MSKSIZE*(n)) & M_PF1MSKSIZE)
+
+ for (i = 0; i < dc_buff.offset/sizeof(*pfconf); i += 1) {
+ printf("%3d %3s %3s %3s %3d %3d"\
+ " %3d %3s %3s %3s %3s %3s %3d %3d\n",
+ i, yesno(pfconf->rss_pf_config & F_MAPENABLE),
+ yesno(pfconf->rss_pf_config & F_CHNENABLE),
+ yesno(pfconf->rss_pf_config & F_PRTENABLE),
+ G_PFnLKPIDX(pfconf->rss_pf_map, i),
+ G_PFnMSKSIZE(pfconf->rss_pf_mask, i),
+ G_IVFWIDTH(pfconf->rss_pf_config),
+ yesno(pfconf->rss_pf_config & F_IP6FOURTUPEN),
+ yesno(pfconf->rss_pf_config & F_IP6TWOTUPEN),
+ yesno(pfconf->rss_pf_config & F_IP4FOURTUPEN),
+ yesno(pfconf->rss_pf_config & F_IP4TWOTUPEN),
+ yesno(pfconf->rss_pf_config & F_UDPFOURTUPEN),
+ G_CH1DEFAULTQUEUE(pfconf->rss_pf_config),
+ G_CH0DEFAULTQUEUE(pfconf->rss_pf_config));
+
+ pfconf++;
+ }
+#undef G_PFnLKPIDX
+#undef G_PFnMSKSIZE
+
+ return rc;
+}
+
+int
+view_rss(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ u16 *pdata = NULL;
+ int rc = 0;
+ u32 i;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ pdata = (u16 *) dc_buff.data;
+ for (i = 0; i < dc_buff.offset / 2; i += 8) {
+ printf("%4d: %4u %4u %4u %4u "\
+ "%4u %4u %4u %4u\n",
+ i, pdata[i + 0], pdata[i + 1], pdata[i + 2],
+ pdata[i + 3], pdata[i + 4], pdata[i + 5],
+ pdata[i + 6], pdata[i + 7]);
+ }
+
+ return rc;
+}
+
+int
+view_fw_devlog(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct fw_devlog_e *e, *devlog;
+ unsigned long index;
+ u32 num_entries = 0;
+ u32 first_entry = 0;
+ int rc = 0;
+ u32 itr;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ translate_fw_devlog(dc_buff.data, dc_buff.offset,
+ &num_entries, &first_entry);
+
+ devlog = (struct fw_devlog_e *)(dc_buff.data);
+ printf("%10s %15s %8s %8s %s\n",
+ "Seq#", "Tstamp", "Level", "Facility", "Message");
+
+ index = first_entry;
+ for (itr = 0; itr < num_entries; itr++) {
+ if (index >= num_entries)
+ index = 0;
+
+ e = &devlog[index++];
+ if (e->timestamp == 0)
+ break;
+ printf("%10d %15llu %8s %8s ",
+ e->seqno, e->timestamp,
+ (e->level < ARRAY_SIZE(devlog_level_strings)
+ ? devlog_level_strings[e->level] : "UNKNOWN"),
+ (e->facility < ARRAY_SIZE(devlog_facility_strings)
+ ? devlog_facility_strings[e->facility]
+ : "UNKNOWN"));
+ printf((const char *)e->fmt,
+ e->params[0], e->params[1], e->params[2],
+ e->params[3], e->params[4], e->params[5],
+ e->params[6], e->params[7]);
+ }
+
+ return rc;
+}
+
+void
+translate_fw_devlog(void *pbuf, u32 io_size,
+ u32 *num_entries, u32 *first_entry)
+{
+ struct fw_devlog_e *e = NULL;
+ u64 ftstamp;
+ u32 index;
+
+ *num_entries = (io_size / sizeof(struct fw_devlog_e));
+ *first_entry = 0;
+ e = (struct fw_devlog_e *)pbuf;
+ for (ftstamp = ~0ULL, index = 0; index < *num_entries; index++) {
+ int i;
+
+ if (e->timestamp == 0)
+ continue;
+
+ e->timestamp = ntohll(e->timestamp);
+ e->seqno = ntohl(e->seqno);
+ for (i = 0; i < 8; i++)
+ e->params[i] = ntohl(e->params[i]);
+
+ if (e->timestamp < ftstamp) {
+ ftstamp = e->timestamp;
+ *first_entry = index;
+ }
+
+ e++;
+ }
+}
+
+/* Regdump function */
+static uint32_t
+xtract(uint32_t val, int shift, int len)
+{
+ return (val >> shift) & ((1L << len) - 1);
+}
+
+static int
+dump_block_regs(const struct reg_info *reg_array, const u32 *regs,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ uint32_t reg_val = 0; /* silence compiler warning*/
+ int rc = 0;
+
+ for (; reg_array->name; ++reg_array) {
+ if (!reg_array->len) {
+ reg_val = regs[reg_array->addr / 4];
+ printf("[%#7x] %-47s %#-10x"\
+ " %u\n", reg_array->addr, reg_array->name,
+ reg_val, reg_val);
+ } else {
+ uint32_t v = xtract(reg_val, reg_array->addr,
+ reg_array->len);
+
+ printf(" %*u:%u %-47s "\
+ "%#-10x %u\n",
+ reg_array->addr < 10 ? 3 : 2,
+ reg_array->addr + reg_array->len - 1,
+ reg_array->addr, reg_array->name, v, v);
+ }
+ }
+
+ return 1;
+
+ return rc;
+}
+
+static int
+dump_regs_table(const u32 *regs, const struct mod_regs *modtab,
+ int nmodules, const char *modnames,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ int match = 0;
+ int rc = 0;
+
+ for (; nmodules; nmodules--, modtab++) {
+ rc = dump_block_regs(modtab->ri,
+ regs + modtab->offset, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ match += rc;
+ }
+
+err1:
+ return rc;
+}
+
+#define T6_MODREGS(name) { #name, t6_##name##_regs }
+static int
+dump_regs_t6(const u32 *regs, struct cudbg_buffer *cudbg_poutbuf)
+{
+ static struct mod_regs t6_mod[] = {
+ T6_MODREGS(sge),
+ { "pci", t6_pcie_regs },
+ T6_MODREGS(dbg),
+ { "mc0", t6_mc_0_regs },
+ T6_MODREGS(ma),
+ { "edc0", t6_edc_t60_regs },
+ { "edc1", t6_edc_t61_regs },
+ T6_MODREGS(cim),
+ T6_MODREGS(tp),
+ { "ulprx", t6_ulp_rx_regs },
+ { "ulptx", t6_ulp_tx_regs },
+ { "pmrx", t6_pm_rx_regs },
+ { "pmtx", t6_pm_tx_regs },
+ T6_MODREGS(mps),
+ { "cplsw", t6_cpl_switch_regs },
+ T6_MODREGS(smb),
+ { "i2c", t6_i2cm_regs },
+ T6_MODREGS(mi),
+ T6_MODREGS(uart),
+ T6_MODREGS(pmu),
+ T6_MODREGS(sf),
+ T6_MODREGS(pl),
+ T6_MODREGS(le),
+ T6_MODREGS(ncsi),
+ T6_MODREGS(mac),
+ { "hma", t6_hma_t6_regs }
+ };
+
+ return dump_regs_table(regs, t6_mod,
+ ARRAY_SIZE(t6_mod),
+ "sge, pci, dbg, mc0, ma, edc0, edc1, cim, "\
+ "tp, ulprx, ulptx, pmrx, pmtx, mps, cplsw, smb, "\
+ "i2c, mi, uart, pmu, sf, pl, le, ncsi, "\
+ "mac, hma", cudbg_poutbuf);
+}
+#undef T6_MODREGS
+
+#define T5_MODREGS(name) { #name, t5_##name##_regs }
+
+static int
+dump_regs_t5(const u32 *regs, struct cudbg_buffer *cudbg_poutbuf)
+{
+ static struct mod_regs t5_mod[] = {
+ T5_MODREGS(sge),
+ { "pci", t5_pcie_regs },
+ T5_MODREGS(dbg),
+ { "mc0", t5_mc_0_regs },
+ { "mc1", t5_mc_1_regs },
+ T5_MODREGS(ma),
+ { "edc0", t5_edc_t50_regs },
+ { "edc1", t5_edc_t51_regs },
+ T5_MODREGS(cim),
+ T5_MODREGS(tp),
+ { "ulprx", t5_ulp_rx_regs },
+ { "ulptx", t5_ulp_tx_regs },
+ { "pmrx", t5_pm_rx_regs },
+ { "pmtx", t5_pm_tx_regs },
+ T5_MODREGS(mps),
+ { "cplsw", t5_cpl_switch_regs },
+ T5_MODREGS(smb),
+ { "i2c", t5_i2cm_regs },
+ T5_MODREGS(mi),
+ T5_MODREGS(uart),
+ T5_MODREGS(pmu),
+ T5_MODREGS(sf),
+ T5_MODREGS(pl),
+ T5_MODREGS(le),
+ T5_MODREGS(ncsi),
+ T5_MODREGS(mac),
+ { "hma", t5_hma_t5_regs }
+ };
+
+ return dump_regs_table(regs, t5_mod,
+ ARRAY_SIZE(t5_mod),
+ "sge, pci, dbg, mc0, mc1, ma, edc0, edc1, cim, "\
+ "tp, ulprx, ulptx, pmrx, pmtx, mps, cplsw, smb, "\
+ "i2c, mi, uart, pmu, sf, pl, le, ncsi, "\
+ "mac, hma", cudbg_poutbuf);
+}
+#undef T5_MODREGS
+
+int
+view_reg_dump(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0;
+ u32 *regs;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ regs = (u32 *) ((unsigned int *)dc_buff.data);
+ if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
+ rc = dump_regs_t5((u32 *)regs, cudbg_poutbuf);
+ else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
+ rc = dump_regs_t6((u32 *)regs, cudbg_poutbuf);
+ return rc;
+}
+
+static int
+t6_view_wtp(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct wtp_data *wtp = NULL;
+ int rc = 0;
+ int i = 0;
+ /****Rx****/
+ u32 pcie_core_dmaw_sop = 0;
+ u32 sge_pcie_sop = 0;
+ u32 csw_sge_sop = 0;
+ u32 tp_csw_sop = 0;
+ u32 tpcside_csw_sop = 0;
+ u32 ulprx_tpcside_sop = 0;
+ u32 pmrx_ulprx_sop = 0;
+ u32 mps_tpeside_sop = 0;
+ u32 mps_tp_sop = 0;
+ u32 xgm_mps_sop = 0;
+ u32 rx_xgm_xgm_sop = 0;
+ u32 wire_xgm_sop = 0;
+ u32 rx_wire_macok_sop = 0;
+
+ u32 pcie_core_dmaw_eop = 0;
+ u32 sge_pcie_eop = 0;
+ u32 csw_sge_eop = 0;
+ u32 tp_csw_eop = 0;
+ u32 tpcside_csw_eop = 0;
+ u32 ulprx_tpcside_eop = 0;
+ u32 pmrx_ulprx_eop = 0;
+ u32 mps_tpeside_eop = 0;
+ u32 mps_tp_eop = 0;
+ u32 xgm_mps_eop = 0;
+ u32 rx_xgm_xgm_eop = 0;
+ u32 wire_xgm_eop = 0;
+ u32 rx_wire_macok_eop = 0;
+
+ /****Tx****/
+ u32 core_pcie_dma_rsp_sop = 0;
+ u32 pcie_sge_dma_rsp_sop = 0;
+ u32 sge_debug_index6_sop = 0;
+ u32 sge_utx_sop = 0;
+ u32 utx_tp_sop = 0;
+ u32 sge_work_req_sop = 0;
+ u32 utx_tpcside_sop = 0;
+ u32 tpcside_rxarb_sop = 0;
+ u32 tpeside_mps_sop = 0;
+ u32 tp_mps_sop = 0;
+ u32 mps_xgm_sop = 0;
+ u32 tx_xgm_xgm_sop = 0;
+ u32 xgm_wire_sop = 0;
+ u32 tx_macok_wire_sop = 0;
+
+ u32 core_pcie_dma_rsp_eop = 0;
+ u32 pcie_sge_dma_rsp_eop = 0;
+ u32 sge_debug_index6_eop = 0;
+ u32 sge_utx_eop = 0;
+ u32 utx_tp_eop = 0;
+ u32 utx_tpcside_eop = 0;
+ u32 tpcside_rxarb_eop = 0;
+ u32 tpeside_mps_eop = 0;
+ u32 tp_mps_eop = 0;
+ u32 mps_xgm_eop = 0;
+ u32 tx_xgm_xgm_eop = 0;
+ u32 xgm_wire_eop = 0;
+ u32 tx_macok_wire_eop = 0;
+
+ u32 pcie_core_cmd_req_sop = 0;
+ u32 sge_pcie_cmd_req_sop = 0;
+ u32 core_pcie_cmd_rsp_sop = 0;
+ u32 pcie_sge_cmd_rsp_sop = 0;
+ u32 sge_cim_sop = 0;
+ u32 pcie_core_dma_req_sop = 0;
+ u32 sge_pcie_dma_req_sop = 0;
+ u32 utx_sge_dma_req_sop = 0;
+
+ u32 sge_pcie_cmd_req_eop = 0;
+ u32 pcie_core_cmd_req_eop = 0;
+ u32 core_pcie_cmd_rsp_eop = 0;
+ u32 pcie_sge_cmd_rsp_eop = 0;
+ u32 sge_cim_eop = 0;
+ u32 pcie_core_dma_req_eop = 0;
+ u32 sge_pcie_dma_req_eop = 0;
+ u32 utx_sge_dma_req_eop = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ wtp = (struct wtp_data *) dc_buff.data;
+ /*Add up the sop/eop of all channels.*/
+ for (i = 0; i < 8; i++) {
+ if (i < 2) {
+ /*Rx Path*/
+ csw_sge_sop +=
+ (wtp->sge_debug_data_high_indx1.sop[i]);
+ tp_csw_sop +=
+ (wtp->sge_debug_data_high_indx9.sop[i]);
+
+ csw_sge_eop += (wtp->csw_sge.eop[i]);
+ tp_csw_eop += (wtp->tp_csw.eop[i]);
+ rx_wire_macok_sop +=
+ wtp->mac_porrx_etherstatspkts.sop[i];
+ rx_wire_macok_eop +=
+ wtp->mac_porrx_etherstatspkts.eop[i];
+
+ /*Tx Path*/
+ sge_pcie_cmd_req_sop += wtp->sge_pcie_cmd_req.sop[i];
+ pcie_sge_cmd_rsp_sop += wtp->pcie_sge_cmd_rsp.sop[i];
+ sge_cim_sop += wtp->sge_cim.sop[i];
+ tpcside_csw_sop += (wtp->utx_tpcside_tx.sop[i]);
+ sge_work_req_sop += wtp->sge_work_req_pkt.sop[i];
+ tx_macok_wire_sop +=
+ wtp->mac_portx_etherstatspkts.sop[i];
+ tx_macok_wire_eop +=
+ wtp->mac_portx_etherstatspkts.eop[i];
+
+ sge_pcie_cmd_req_eop += wtp->sge_pcie_cmd_req.eop[i];
+ pcie_sge_cmd_rsp_eop += wtp->pcie_sge_cmd_rsp.eop[i];
+ sge_cim_eop += wtp->sge_cim.eop[i];
+
+ }
+
+ if (i < 3) {
+ pcie_core_cmd_req_sop += wtp->pcie_cmd_stat2.sop[i];
+ core_pcie_cmd_rsp_sop += wtp->pcie_cmd_stat3.sop[i];
+
+ core_pcie_cmd_rsp_eop += wtp->pcie_cmd_stat3.eop[i];
+ pcie_core_cmd_req_eop += wtp->pcie_cmd_stat2.eop[i];
+ }
+
+ if (i < 4) {
+ /*Rx Path*/
+ pcie_core_dmaw_sop +=
+ (wtp->pcie_dma1_stat2.sop[i]);
+ sge_pcie_sop +=
+ (wtp->sge_debug_data_high_indx7.sop[i]);
+ ulprx_tpcside_sop += (wtp->ulprx_tpcside.sop[i]);
+ pmrx_ulprx_sop += (wtp->pmrx_ulprx.sop[i]);
+ mps_tpeside_sop +=
+ (wtp->tp_dbg_eside_pktx.sop[i]);
+ rx_xgm_xgm_sop +=
+ (wtp->mac_porrx_pkt_count.sop[i]);
+ wire_xgm_sop +=
+ (wtp->mac_porrx_aframestra_ok.sop[i]);
+
+ pcie_core_dmaw_eop +=
+ (wtp->pcie_dma1_stat2.eop[i]);
+ sge_pcie_eop += (wtp->sge_pcie.eop[i]);
+ tpcside_csw_eop += (wtp->tpcside_csw.eop[i]);
+ ulprx_tpcside_eop += (wtp->ulprx_tpcside.eop[i]);
+ pmrx_ulprx_eop += (wtp->pmrx_ulprx.eop[i]);
+ mps_tpeside_eop += (wtp->mps_tpeside.eop[i]);
+ rx_xgm_xgm_eop +=
+ (wtp->mac_porrx_pkt_count.eop[i]);
+ wire_xgm_eop +=
+ (wtp->mac_porrx_aframestra_ok.eop[i]);
+
+ /*special case type 3:*/
+ mps_tp_sop += (wtp->mps_tp.sop[i]);
+ mps_tp_eop += (wtp->mps_tp.eop[i]);
+
+ /*Tx Path*/
+ core_pcie_dma_rsp_sop +=
+ wtp->pcie_t5_dma_stat3.sop[i];
+ pcie_sge_dma_rsp_sop += wtp->pcie_sge_dma_rsp.sop[i];
+ sge_debug_index6_sop +=
+ wtp->sge_debug_data_high_index_6.sop[i];
+ sge_utx_sop += wtp->ulp_se_cnt_chx.sop[i];
+ utx_tp_sop += wtp->utx_tp.sop[i];
+ utx_tpcside_sop += wtp->utx_tpcside.sop[i];
+ tpcside_rxarb_sop += wtp->tpcside_rxarb.sop[i];
+ tpeside_mps_sop += wtp->tpeside_mps.sop[i];
+ tx_xgm_xgm_sop +=
+ wtp->mac_portx_pkt_count.sop[i];
+ xgm_wire_sop +=
+ wtp->mac_portx_aframestra_ok.sop[i];
+
+ core_pcie_dma_rsp_eop +=
+ wtp->pcie_t5_dma_stat3.eop[i];
+ pcie_sge_dma_rsp_eop += wtp->pcie_sge_dma_rsp.eop[i];
+ sge_debug_index6_eop +=
+ wtp->sge_debug_data_high_index_6.eop[i];
+ sge_utx_eop += wtp->sge_utx.eop[i];
+ utx_tp_eop += wtp->utx_tp.eop[i];
+ utx_tpcside_eop += wtp->utx_tpcside.eop[i];
+ tpcside_rxarb_eop += wtp->tpcside_rxarb.eop[i];
+ tpeside_mps_eop += wtp->tpeside_mps.eop[i];
+ tx_xgm_xgm_eop +=
+ wtp->mac_portx_pkt_count.eop[i];
+ xgm_wire_eop +=
+ wtp->mac_portx_aframestra_ok.eop[i];
+
+ /*special case type 3:*/
+ tp_mps_sop += wtp->tp_mps.sop[i];
+ mps_xgm_sop += wtp->mps_xgm.sop[i];
+
+ tp_mps_eop += wtp->tp_mps.eop[i];
+ mps_xgm_eop += wtp->mps_xgm.eop[i];
+
+ pcie_core_dma_req_sop +=
+ wtp->pcie_dma1_stat2_core.sop[i];
+ sge_pcie_dma_req_sop +=
+ wtp->sge_debug_data_high_indx5.sop[i];
+ utx_sge_dma_req_sop += wtp->utx_sge_dma_req.sop[i];
+
+ pcie_core_dma_req_eop +=
+ wtp->pcie_dma1_stat2_core.eop[i];
+ sge_pcie_dma_req_eop +=
+ wtp->sge_debug_data_high_indx5.eop[i];
+ utx_sge_dma_req_eop += wtp->utx_sge_dma_req.eop[i];
+ }
+
+ if (i < 5) {
+ xgm_mps_sop += (wtp->xgm_mps.sop[i]);
+ xgm_mps_eop += (wtp->xgm_mps.eop[i]);
+ }
+ }
+ printf("ifaces = nic0 nic1\n");
+ printf("*************************EGGRESS (TX) PATH **********************************\n");
+ printf("MOD : core---->PCIE---->SGE<-| #Ring Doorbell\n");
+ printf("SOP ? ??? |\n");
+ printf("EOP ? ??? |\n");
+ printf("MOD |<-core<----PCIE<----SGE<-| #Request Work Request\n");
+ printf("SOP_CH0 %02X %02x\n",
+ wtp->pcie_cmd_stat2.sop[0], wtp->sge_pcie_cmd_req.sop[0]);
+ printf("SOP | %02X %02X\n",
+ pcie_core_cmd_req_sop, sge_pcie_cmd_req_sop);
+ printf("EOP | %2X %2X\n",
+ pcie_core_cmd_req_eop, sge_pcie_cmd_req_eop);
+ printf("MOD |->core---->PCIE---->SGE------>CIM/uP->| uP<-CIM<-CSW #->Work req. <-Pkts\n");
+ printf("SOP_CH0 %02X %02X %02X"\
+ " | %2X\n",
+ wtp->pcie_cmd_stat3.sop[0], wtp->pcie_sge_cmd_rsp.sop[1],
+ wtp->sge_cim.sop[0], wtp->sge_work_req_pkt.sop[0]);
+
+ printf("SOP_CH1 %02X"\
+ " |\n", wtp->pcie_sge_cmd_rsp.sop[1]);
+ printf("SOP %02X %02X %2X"\
+ " | %2X\n", core_pcie_cmd_rsp_sop,
+ pcie_sge_cmd_rsp_sop, sge_cim_sop, sge_work_req_sop);
+ printf("EOP %2X %2X %2X"\
+ " |\n", core_pcie_cmd_rsp_eop,
+ pcie_sge_cmd_rsp_eop, sge_cim_eop);
+ printf("MOD |<-core<----PCIE<----SGE<------UTX<--------|#data dma requests\n");
+ printf("SOP_CH0 %02X\n",
+ wtp->pcie_dma1_stat2_core.sop[0]);
+ printf("SOP_CH1 %02X\n",
+ wtp->pcie_dma1_stat2_core.sop[1]);
+ printf("SOP | %2X\n",
+ pcie_core_dma_req_sop);
+ printf("EOP | %2X\n",
+ pcie_core_dma_req_eop);
+
+ printf("MOD |->core-->PCIE-->SGE-->UTX---->TPC------->TPE---->MPS--->MAC--->MACOK->wire\n");
+ printf("SOP_CH0 %02X %2X "\
+ " %2X %2X %2X %02X %02X %02X %02X "\
+ " %02X\n",
+ wtp->pcie_t5_dma_stat3.sop[0], wtp->ulp_se_cnt_chx.sop[0],
+ wtp->utx_tpcside.sop[0], wtp->tpcside_rxarb.sop[0],
+ wtp->tpeside_mps.sop[0], wtp->tp_mps.sop[0],
+ wtp->mps_xgm.sop[0], wtp->mac_portx_pkt_count.sop[0],
+ wtp->mac_portx_aframestra_ok.sop[0],
+ wtp->mac_portx_etherstatspkts.sop[0]);
+
+ printf("EOP_CH0 %02X %2X "\
+ " %2X %2X %2X %02X %02X %02X %02X"\
+ " %02X\n",
+ wtp->pcie_t5_dma_stat3.eop[0], wtp->ulp_se_cnt_chx.eop[0],
+ wtp->utx_tpcside.eop[0], wtp->tpcside_rxarb.eop[0],
+ wtp->tpeside_mps.eop[0], wtp->tp_mps.eop[0],
+ wtp->mps_xgm.eop[0], wtp->mac_portx_pkt_count.eop[0],
+ wtp->mac_portx_aframestra_ok.eop[0],
+ wtp->mac_portx_etherstatspkts.eop[0]);
+ printf("SOP_CH1 %02X %2X "\
+ " %2X %2X %2X %02X %02X %02X %02X "\
+ "%02X\n",
+ wtp->pcie_t5_dma_stat3.sop[1], wtp->ulp_se_cnt_chx.sop[1],
+ wtp->utx_tpcside.sop[1], wtp->tpcside_rxarb.sop[1],
+ wtp->tpeside_mps.sop[1], wtp->tp_mps.sop[1],
+ wtp->mps_xgm.sop[1], wtp->mac_portx_pkt_count.sop[1],
+ wtp->mac_portx_aframestra_ok.sop[1],
+ wtp->mac_portx_etherstatspkts.sop[1]);
+
+ printf("EOP_CH1 %02X %2X "\
+ " %2X %2X %2X %02X %02X %02X %02X"\
+ " %02X\n",
+ wtp->pcie_t5_dma_stat3.eop[1], wtp->ulp_se_cnt_chx.eop[1],
+ wtp->utx_tpcside.eop[1], wtp->tpcside_rxarb.eop[1],
+ wtp->tpeside_mps.eop[1], wtp->tp_mps.eop[1],
+ wtp->mps_xgm.eop[1], wtp->mac_portx_pkt_count.eop[1],
+ wtp->mac_portx_aframestra_ok.eop[1],
+ wtp->mac_portx_etherstatspkts.eop[1]);
+ printf("SOP_CH2 %02X %2X "\
+ " %2X %2X %2X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.sop[2], wtp->ulp_se_cnt_chx.sop[2],
+ wtp->utx_tpcside.sop[2], wtp->tpcside_rxarb.sop[2],
+ wtp->tpeside_mps.sop[2], wtp->tp_mps.sop[2],
+ wtp->mps_xgm.sop[2]);
+
+ printf("EOP_CH2 %02X %2X "\
+ " %2X %2X %2X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.eop[2], wtp->ulp_se_cnt_chx.eop[2],
+ wtp->utx_tpcside.eop[2], wtp->tpcside_rxarb.eop[2],
+ wtp->tpeside_mps.eop[2], wtp->tp_mps.eop[2],
+ wtp->mps_xgm.eop[2]);
+ printf("SOP_CH3 %02X %2X "\
+ " %2X %2X %2X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.sop[3], wtp->ulp_se_cnt_chx.sop[3],
+ wtp->utx_tpcside.sop[3], wtp->tpcside_rxarb.sop[3],
+ wtp->tpeside_mps.sop[3], wtp->tp_mps.sop[3],
+ wtp->mps_xgm.sop[3]);
+
+ printf("EOP_CH3 %02X %2X "\
+ " %2X %2X %2X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.eop[3], wtp->ulp_se_cnt_chx.eop[3],
+ wtp->utx_tpcside.eop[3], wtp->tpcside_rxarb.eop[3],
+ wtp->tpeside_mps.eop[3], wtp->tp_mps.eop[3],
+ wtp->mps_xgm.eop[3]);
+ printf("SOP %2X %2X "\
+ " %2X %2X %2X %2X %2X %2X %2X %2X\n",
+ core_pcie_dma_rsp_sop, sge_utx_sop, utx_tp_sop,
+ tpcside_rxarb_sop, tpeside_mps_sop, tp_mps_sop,
+ mps_xgm_sop, tx_xgm_xgm_sop, xgm_wire_sop,
+ tx_macok_wire_sop);
+ printf("EOP %2X %2X "\
+ " %2X %2X %2X %2X %2X %2X %2X "\
+ " %2X\n",
+ core_pcie_dma_rsp_eop, sge_utx_eop, utx_tp_eop,
+ tpcside_rxarb_eop, tpeside_mps_eop, tp_mps_eop,
+ mps_xgm_eop, tx_xgm_xgm_eop, xgm_wire_eop,
+ tx_macok_wire_eop);
+ printf("*************************INGRESS (RX) PATH **********************************\n");
+
+ printf("MOD core<-PCIE<---SGE<--CSW<-----TPC<-URX<-LE-TPE<-----MPS<--MAC<-MACOK<--wire\n");
+
+ printf("SOP_CH0 %2X %2X %2X %2X"\
+ " %2X %2X %2X %2X %2X %2X %02X %02X "\
+ " %02X %02X\n",
+ wtp->pcie_dma1_stat2.sop[0],
+ wtp->sge_debug_data_high_indx7.sop[0],
+ wtp->sge_debug_data_high_indx1.sop[0],
+ wtp->sge_debug_data_high_indx9.sop[0],
+ wtp->utx_tpcside_tx.sop[0], wtp->ulprx_tpcside.sop[0],
+ wtp->pmrx_ulprx.sop[0], wtp->le_db_rsp_cnt.sop,
+ wtp->tp_dbg_eside_pktx.sop[0], wtp->mps_tp.sop[0],
+ wtp->xgm_mps.sop[0], wtp->mac_porrx_pkt_count.sop[0],
+ wtp->mac_porrx_aframestra_ok.sop[0],
+ wtp->mac_porrx_etherstatspkts.sop[0]);
+
+ printf("EOP_CH0 %2X %2X %2X "\
+ "%2X %2X %2X %2X %2X %2X %2X %02X %02X "\
+ " %02X %02X\n",
+ wtp->pcie_dma1_stat2.eop[0],
+ wtp->sge_debug_data_high_indx7.eop[0],
+ wtp->sge_debug_data_high_indx1.eop[0],
+ wtp->sge_debug_data_high_indx9.eop[0],
+ wtp->utx_tpcside_tx.eop[0], wtp->ulprx_tpcside.eop[0],
+ wtp->pmrx_ulprx.eop[0], wtp->le_db_rsp_cnt.eop,
+ wtp->tp_dbg_eside_pktx.eop[0], wtp->mps_tp.eop[0],
+ wtp->xgm_mps.eop[0], wtp->mac_porrx_pkt_count.eop[0],
+ wtp->mac_porrx_aframestra_ok.eop[0],
+ wtp->mac_porrx_etherstatspkts.eop[0]);
+ printf("SOP_CH1 %2X %2X %2X "\
+ " %2X %2X %2X %2X %2X %2X %02X %02X "\
+ " %02X %02X\n",
+ wtp->pcie_dma1_stat2.sop[1],
+ wtp->sge_debug_data_high_indx7.sop[1],
+ wtp->sge_debug_data_high_indx1.sop[1],
+ wtp->sge_debug_data_high_indx9.sop[1],
+ wtp->utx_tpcside_tx.sop[1], wtp->ulprx_tpcside.sop[1],
+ wtp->pmrx_ulprx.sop[1], wtp->tp_dbg_eside_pktx.sop[1],
+ wtp->mps_tp.sop[1], wtp->xgm_mps.sop[1],
+ wtp->mac_porrx_pkt_count.sop[1],
+ wtp->mac_porrx_aframestra_ok.sop[1],
+ wtp->mac_porrx_etherstatspkts.sop[1]);
+
+ printf("EOP_CH1 %2X %2X %2X %2X"\
+ " %2X %2X %2X %2X %2X %02X %02X "\
+ "%02X %02X\n",
+ wtp->pcie_dma1_stat2.eop[1],
+ wtp->sge_debug_data_high_indx7.eop[1],
+ wtp->sge_debug_data_high_indx1.eop[1],
+ wtp->sge_debug_data_high_indx9.eop[1],
+ wtp->utx_tpcside_tx.eop[1], wtp->ulprx_tpcside.eop[1],
+ wtp->pmrx_ulprx.eop[1], wtp->tp_dbg_eside_pktx.eop[1],
+ wtp->mps_tp.eop[1], wtp->xgm_mps.eop[1],
+ wtp->mac_porrx_pkt_count.eop[1],
+ wtp->mac_porrx_aframestra_ok.eop[1],
+ wtp->mac_porrx_etherstatspkts.eop[1]);
+ printf("SOP_CH2 "\
+ " %2X %02X\n",
+ wtp->tp_dbg_eside_pktx.sop[2], wtp->xgm_mps.sop[2]);
+
+ printf("EOP_CH2 "\
+ " %2X %02X\n",
+ wtp->tp_dbg_eside_pktx.eop[2], wtp->xgm_mps.eop[2]);
+ printf("SOP_CH3 "\
+ " %2X %02X\n",
+ wtp->tp_dbg_eside_pktx.sop[3],
+ wtp->xgm_mps.sop[3]);
+
+ printf("EOP_CH3 "\
+ " %2X %02X\n",
+ wtp->tp_dbg_eside_pktx.eop[3], wtp->xgm_mps.eop[3]);
+ printf("SOP_CH4 "\
+ " %02X\n",
+ wtp->xgm_mps.sop[4]);
+ printf("EOP_CH4 "\
+ " %02X\n",
+ wtp->xgm_mps.eop[4]);
+ printf("SOP_CH5 "\
+ " %02X\n",
+ wtp->xgm_mps.sop[5]);
+ printf("EOP_CH5 "\
+ " %02X\n",
+ wtp->xgm_mps.eop[5]);
+ printf("SOP_CH6\n");
+ printf("EOP_CH6\n");
+ printf("SOP_CH7\n");
+ printf("EOP_CH7\n");
+
+ printf("SOP %2X %2X %2X %2X"\
+ " %2X %2X %2X %2X %2X %2X %2X %2X "\
+ " %2X\n",
+ pcie_core_dmaw_sop, sge_pcie_sop, csw_sge_sop,
+ tp_csw_sop, tpcside_csw_sop, ulprx_tpcside_sop,
+ pmrx_ulprx_sop, mps_tpeside_sop,
+ mps_tp_sop, xgm_mps_sop, rx_xgm_xgm_sop,
+ wire_xgm_sop, rx_wire_macok_sop);
+ printf("EOP %2X %2X %2X "\
+ "%2X %2X %2X %2X %2X %2X %2X %2X "\
+ " %2X %2X\n",
+ pcie_core_dmaw_eop, sge_pcie_eop, csw_sge_eop,
+ tp_csw_eop, tpcside_csw_eop, ulprx_tpcside_eop,
+ pmrx_ulprx_eop, mps_tpeside_eop, mps_tp_eop,
+ xgm_mps_eop, rx_xgm_xgm_eop, wire_xgm_eop,
+ rx_wire_macok_eop);
+ printf("DROP: ??? ??? ??? "\
+ "%2X(mib) %2X(err) %2X(oflow) %X(cls)\n",
+ (wtp->mps_tp.drops & 0xFF), (wtp->xgm_mps.err & 0xFF),
+ (wtp->xgm_mps.drop & 0xFF),
+ (wtp->xgm_mps.cls_drop & 0xFF));
+ printf("INTS: ");
+ for (i = 0; i < 2; i++) {
+ printf("%2X<- %2X ",
+ (wtp->pcie_core_dmai.sop[i] & 0xF),
+ (wtp->sge_pcie_ints.sop[i] & 0xF));
+ }
+ printf("(PCIE<-SGE, channels 0 to 1)\n");
+
+ return rc;
+}
+
+static int
+t5_view_wtp(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct wtp_data *wtp = NULL;
+ int rc = 0;
+ int i = 0;
+ /****Rx****/
+ u32 pcie_core_dmaw_sop = 0;
+ u32 sge_pcie_sop = 0;
+ u32 csw_sge_sop = 0;
+ u32 tp_csw_sop = 0;
+ u32 tpcside_csw_sop = 0;
+ u32 ulprx_tpcside_sop = 0;
+ u32 pmrx_ulprx_sop = 0;
+ u32 mps_tpeside_sop = 0;
+ u32 mps_tp_sop = 0;
+ u32 xgm_mps_sop = 0;
+ u32 rx_xgm_xgm_sop = 0;
+ u32 wire_xgm_sop = 0;
+
+ u32 pcie_core_dmaw_eop = 0;
+ u32 sge_pcie_eop = 0;
+ u32 csw_sge_eop = 0;
+ u32 tp_csw_eop = 0;
+ u32 tpcside_csw_eop = 0;
+ u32 ulprx_tpcside_eop = 0;
+ u32 pmrx_ulprx_eop = 0;
+ u32 mps_tpeside_eop = 0;
+ u32 mps_tp_eop = 0;
+ u32 xgm_mps_eop = 0;
+ u32 rx_xgm_xgm_eop = 0;
+ u32 wire_xgm_eop = 0;
+
+ /****Tx****/
+ u32 core_pcie_dma_rsp_sop = 0;
+ u32 pcie_sge_dma_rsp_sop = 0;
+ u32 sge_debug_index6_sop = 0;
+ u32 sge_utx_sop = 0;
+ u32 utx_tp_sop = 0;
+ u32 sge_work_req_sop = 0;
+ u32 utx_tpcside_sop = 0;
+ u32 tpcside_rxarb_sop = 0;
+ u32 tpeside_mps_sop = 0;
+ u32 tp_mps_sop = 0;
+ u32 mps_xgm_sop = 0;
+ u32 tx_xgm_xgm_sop = 0;
+ u32 xgm_wire_sop = 0;
+
+ u32 core_pcie_dma_rsp_eop = 0;
+ u32 pcie_sge_dma_rsp_eop = 0;
+ u32 sge_debug_index6_eop = 0;
+ u32 sge_utx_eop = 0;
+ u32 utx_tp_eop = 0;
+ u32 utx_tpcside_eop = 0;
+ u32 tpcside_rxarb_eop = 0;
+ u32 tpeside_mps_eop = 0;
+ u32 tp_mps_eop = 0;
+ u32 mps_xgm_eop = 0;
+ u32 tx_xgm_xgm_eop = 0;
+ u32 xgm_wire_eop = 0;
+
+ u32 pcie_core_cmd_req_sop = 0;
+ u32 sge_pcie_cmd_req_sop = 0;
+ u32 core_pcie_cmd_rsp_sop = 0;
+ u32 pcie_sge_cmd_rsp_sop = 0;
+ u32 sge_cim_sop = 0;
+ u32 pcie_core_dma_req_sop = 0;
+ u32 sge_pcie_dma_req_sop = 0;
+ u32 utx_sge_dma_req_sop = 0;
+
+ u32 sge_pcie_cmd_req_eop = 0;
+ u32 pcie_core_cmd_req_eop = 0;
+ u32 core_pcie_cmd_rsp_eop = 0;
+ u32 pcie_sge_cmd_rsp_eop = 0;
+ u32 sge_cim_eop = 0;
+ u32 pcie_core_dma_req_eop = 0;
+ u32 sge_pcie_dma_req_eop = 0;
+ u32 utx_sge_dma_req_eop = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ wtp = (struct wtp_data *) dc_buff.data;
+ /*Add up the sop/eop of all channels.*/
+ for (i = 0; i < 8; i++) {
+ if (i < 2) {
+ /*Rx Path*/
+ csw_sge_sop +=
+ (wtp->sge_debug_data_high_indx1.sop[i]);
+ tp_csw_sop +=
+ (wtp->sge_debug_data_high_indx9.sop[i]);
+
+ csw_sge_eop += (wtp->csw_sge.eop[i]);
+ tp_csw_eop += (wtp->tp_csw.eop[i]);
+
+ /*Tx Path*/
+ sge_pcie_cmd_req_sop += wtp->sge_pcie_cmd_req.sop[i];
+ pcie_sge_cmd_rsp_sop += wtp->pcie_sge_cmd_rsp.sop[i];
+ sge_cim_sop += wtp->sge_cim.sop[i];
+ tpcside_csw_sop += (wtp->utx_tpcside_tx.sop[i]);
+ sge_work_req_sop += wtp->sge_work_req_pkt.sop[i];
+
+ sge_pcie_cmd_req_eop += wtp->sge_pcie_cmd_req.eop[i];
+ pcie_sge_cmd_rsp_eop += wtp->pcie_sge_cmd_rsp.eop[i];
+ sge_cim_eop += wtp->sge_cim.eop[i];
+
+ }
+
+ if (i < 3) {
+ pcie_core_cmd_req_sop += wtp->pcie_cmd_stat2.sop[i];
+ core_pcie_cmd_rsp_sop += wtp->pcie_cmd_stat3.sop[i];
+
+ core_pcie_cmd_rsp_eop += wtp->pcie_cmd_stat3.eop[i];
+ pcie_core_cmd_req_eop += wtp->pcie_cmd_stat2.eop[i];
+ }
+
+ if (i < 4) {
+ /*Rx Path*/
+ pcie_core_dmaw_sop +=
+ (wtp->pcie_dma1_stat2.sop[i]);
+ sge_pcie_sop +=
+ (wtp->sge_debug_data_high_indx7.sop[i]);
+ ulprx_tpcside_sop += (wtp->ulprx_tpcside.sop[i]);
+ pmrx_ulprx_sop += (wtp->pmrx_ulprx.sop[i]);
+ mps_tpeside_sop +=
+ (wtp->tp_dbg_eside_pktx.sop[i]);
+ rx_xgm_xgm_sop +=
+ (wtp->mac_porrx_pkt_count.sop[i]);
+ wire_xgm_sop +=
+ (wtp->mac_porrx_aframestra_ok.sop[i]);
+
+ pcie_core_dmaw_eop +=
+ (wtp->pcie_dma1_stat2.eop[i]);
+ sge_pcie_eop += (wtp->sge_pcie.eop[i]);
+ tpcside_csw_eop += (wtp->tpcside_csw.eop[i]);
+ ulprx_tpcside_eop += (wtp->ulprx_tpcside.eop[i]);
+ pmrx_ulprx_eop += (wtp->pmrx_ulprx.eop[i]);
+ mps_tpeside_eop += (wtp->mps_tpeside.eop[i]);
+ rx_xgm_xgm_eop +=
+ (wtp->mac_porrx_pkt_count.eop[i]);
+ wire_xgm_eop += (wtp->xgm_mps.eop[i]);
+
+ /*special case type 3:*/
+ mps_tp_sop += (wtp->mps_tp.sop[i]);
+ mps_tp_eop += (wtp->mps_tp.eop[i]);
+
+ /*Tx Path*/
+ core_pcie_dma_rsp_sop +=
+ wtp->pcie_t5_dma_stat3.sop[i];
+ pcie_sge_dma_rsp_sop += wtp->pcie_sge_dma_rsp.sop[i];
+ sge_debug_index6_sop +=
+ wtp->sge_debug_data_high_index_6.sop[i];
+ sge_utx_sop += wtp->ulp_se_cnt_chx.sop[i];
+ utx_tp_sop += wtp->utx_tp.sop[i];
+ utx_tpcside_sop += wtp->utx_tpcside.sop[i];
+ tpcside_rxarb_sop += wtp->tpcside_rxarb.sop[i];
+ tpeside_mps_sop += wtp->tpeside_mps.sop[i];
+ tx_xgm_xgm_sop +=
+ wtp->mac_portx_pkt_count.sop[i];
+ xgm_wire_sop +=
+ wtp->mac_portx_aframestra_ok.sop[i];
+
+ core_pcie_dma_rsp_eop +=
+ wtp->pcie_t5_dma_stat3.eop[i];
+ pcie_sge_dma_rsp_eop += wtp->pcie_sge_dma_rsp.eop[i];
+ sge_debug_index6_eop +=
+ wtp->sge_debug_data_high_index_6.eop[i];
+ sge_utx_eop += wtp->sge_utx.eop[i];
+ utx_tp_eop += wtp->utx_tp.eop[i];
+ utx_tpcside_eop += wtp->utx_tpcside.eop[i];
+ tpcside_rxarb_eop += wtp->tpcside_rxarb.eop[i];
+ tpeside_mps_eop += wtp->tpeside_mps.eop[i];
+ tx_xgm_xgm_eop +=
+ wtp->mac_portx_pkt_count.eop[i];
+ xgm_wire_eop +=
+ wtp->mac_portx_aframestra_ok.eop[i];
+
+ /*special case type 3:*/
+ tp_mps_sop += wtp->tp_mps.sop[i];
+ mps_xgm_sop += wtp->mps_xgm.sop[i];
+
+ tp_mps_eop += wtp->tp_mps.eop[i];
+ mps_xgm_eop += wtp->mps_xgm.eop[i];
+
+ pcie_core_dma_req_sop +=
+ wtp->pcie_dma1_stat2_core.sop[i];
+ sge_pcie_dma_req_sop +=
+ wtp->sge_debug_data_high_indx5.sop[i];
+ utx_sge_dma_req_sop += wtp->utx_sge_dma_req.sop[i];
+
+ pcie_core_dma_req_eop +=
+ wtp->pcie_dma1_stat2_core.eop[i];
+ sge_pcie_dma_req_eop +=
+ wtp->sge_debug_data_high_indx5.eop[i];
+ utx_sge_dma_req_eop += wtp->utx_sge_dma_req.eop[i];
+ }
+
+ xgm_mps_sop += (wtp->xgm_mps.sop[i]);
+ xgm_mps_eop += (wtp->xgm_mps.eop[i]);
+ }
+ printf("ifaces = nic0 nic1\n");
+ printf("*************************EGGRESS (TX) PATH **********************************\n");
+ printf("MOD : core---->PCIE---->SGE<-| #Ring Doorbell\n");
+ printf("SOP ? ??? |\n");
+ printf("EOP ? ??? |\n");
+ printf("MOD |<-core<----PCIE<----SGE<-| #Request Work Request\n");
+ printf("SOP_CH0 %02X %02x\n",
+ wtp->pcie_cmd_stat2.sop[0],
+ wtp->sge_pcie_cmd_req.sop[0]);
+ printf("SOP_CH1 %02X %02X\n",
+ wtp->pcie_cmd_stat2.sop[1], wtp->sge_pcie_cmd_req.sop[1]);
+ printf("SOP_CH2 %02X\n",
+ wtp->pcie_cmd_stat2.sop[2]);
+ printf("SOP | %02X %02X\n",
+ pcie_core_cmd_req_sop, sge_pcie_cmd_req_sop);
+ printf("EOP | %2X %2X\n",
+ pcie_core_cmd_req_eop, sge_pcie_cmd_req_eop);
+ printf("MOD |->core---->PCIE---->SGE------>CIM/uP->| uP<-CIM<-CSW #->Work req. <-Pkts\n");
+ printf("SOP_CH0 %02X %02X %02X"\
+ " | %2X\n",
+ wtp->pcie_cmd_stat3.sop[0], wtp->pcie_sge_cmd_rsp.sop[0],
+ wtp->sge_cim.sop[0], wtp->sge_work_req_pkt.sop[0]);
+ printf("SOP_CH1 %02X %02X %02X"\
+ " | %2X\n",
+ wtp->pcie_cmd_stat3.sop[1], wtp->pcie_sge_cmd_rsp.sop[1],
+ wtp->sge_cim.sop[1], wtp->sge_work_req_pkt.sop[1]);
+ printf("SOP_CH2 %02X "\
+ " |\n", wtp->pcie_cmd_stat3.sop[2]);
+ printf("SOP %02X %02X %2X "\
+ " | %2X\n",
+ core_pcie_cmd_rsp_sop, pcie_sge_cmd_rsp_sop,
+ sge_cim_sop, sge_work_req_sop);
+ printf("EOP %2X %2X %2X "\
+ " |\n",
+ core_pcie_cmd_rsp_eop,
+ pcie_sge_cmd_rsp_eop, sge_cim_eop);
+ printf("MOD |<-core<----PCIE<----SGE<------UTX<--------|#data dma requests\n");
+ printf("SOP_CH0 %02X %02X "\
+ "%02X\n", wtp->pcie_dma1_stat2_core.sop[0],
+ wtp->sge_debug_data_high_indx5.sop[0],
+ wtp->utx_sge_dma_req.sop[0]);
+ printf("SOP_CH1 %02X %02X "\
+ "%02X\n", wtp->pcie_dma1_stat2_core.sop[1],
+ wtp->sge_debug_data_high_indx5.sop[1],
+ wtp->utx_sge_dma_req.sop[1]);
+ printf("SOP_CH2 %02X %02X "\
+ "%02X\n", wtp->pcie_dma1_stat2_core.sop[2],
+ wtp->sge_debug_data_high_indx5.sop[2],
+ wtp->utx_sge_dma_req.sop[2]);
+ printf("SOP_CH3 %02X %02X "\
+ "%02X\n", wtp->pcie_dma1_stat2_core.sop[3],
+ wtp->sge_debug_data_high_indx5.sop[3],
+ wtp->utx_sge_dma_req.sop[3]);
+ printf("SOP | %2X %2X %2X\n",
+ pcie_core_dma_req_sop/*eop in perl??*/,
+ sge_pcie_dma_req_sop, utx_sge_dma_req_sop);
+ printf("EOP | %2X %2X %2X\n",
+ pcie_core_dma_req_eop,
+ sge_pcie_dma_req_eop, utx_sge_dma_req_eop);
+ printf("MOD |->core-->PCIE-->SGE-->UTX---->TPC------->TPE---->MPS--->MAC--->wire\n");
+ printf("SOP_CH0 %02X %2X %2X %2X"\
+ " %2X %2X %2X %02X %02X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.sop[0],
+ wtp->sge_debug_data_high_index_6.sop[0],
+ wtp->sge_debug_data_high_index_3.sop[0],
+ wtp->ulp_se_cnt_chx.sop[0], wtp->utx_tpcside.sop[0],
+ wtp->tpcside_rxarb.sop[0], wtp->tpeside_mps.sop[0],
+ wtp->tp_mps.sop[0], wtp->mps_xgm.sop[0],
+ wtp->mac_portx_pkt_count.sop[0],
+ wtp->mac_portx_aframestra_ok.sop[0]);
+
+ printf("EOP_CH0 %02X %2X %2X %2X"\
+ " %2X %2X %2X %02X %02X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.eop[0],
+ wtp->sge_debug_data_high_index_6.eop[0],
+ wtp->sge_debug_data_high_index_3.eop[0],
+ wtp->ulp_se_cnt_chx.eop[0], wtp->utx_tpcside.eop[0],
+ wtp->tpcside_rxarb.eop[0], wtp->tpeside_mps.eop[0],
+ wtp->tp_mps.eop[0], wtp->mps_xgm.eop[0],
+ wtp->mac_portx_pkt_count.eop[0],
+ wtp->mac_portx_aframestra_ok.eop[0]);
+ printf("SOP_CH1 %02X %2X %2X %2X"\
+ " %2X %2X %2X %02X %02X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.sop[1],
+ wtp->sge_debug_data_high_index_6.sop[1],
+ wtp->sge_debug_data_high_index_3.sop[1],
+ wtp->ulp_se_cnt_chx.sop[1], wtp->utx_tpcside.sop[1],
+ wtp->tpcside_rxarb.sop[1], wtp->tpeside_mps.sop[1],
+ wtp->tp_mps.sop[1], wtp->mps_xgm.sop[1],
+ wtp->mac_portx_pkt_count.sop[1],
+ wtp->mac_portx_aframestra_ok.sop[1]);
+
+ printf("EOP_CH1 %02X %2X %2X %2X"\
+ " %2X %2X %2X %02X %02X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.eop[1],
+ wtp->sge_debug_data_high_index_6.eop[1],
+ wtp->sge_debug_data_high_index_3.eop[1],
+ wtp->ulp_se_cnt_chx.eop[1], wtp->utx_tpcside.eop[1],
+ wtp->tpcside_rxarb.eop[1], wtp->tpeside_mps.eop[1],
+ wtp->tp_mps.eop[1], wtp->mps_xgm.eop[1],
+ wtp->mac_portx_pkt_count.eop[1],
+ wtp->mac_portx_aframestra_ok.eop[1]);
+ printf("SOP_CH2 %02X %2X %2X %2X"\
+ " %2X %2X %2X %02X %02X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.sop[2],
+ wtp->sge_debug_data_high_index_6.sop[2],
+ wtp->sge_debug_data_high_index_3.sop[2],
+ wtp->ulp_se_cnt_chx.sop[2], wtp->utx_tpcside.sop[2],
+ wtp->tpcside_rxarb.sop[2], wtp->tpeside_mps.sop[2],
+ wtp->tp_mps.sop[2], wtp->mps_xgm.sop[2],
+ wtp->mac_portx_pkt_count.sop[2],
+ wtp->mac_portx_aframestra_ok.sop[2]);
+
+ printf("EOP_CH2 %02X %2X %2X %2X"\
+ " %2X %2X %2X %02X %02X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.eop[2],
+ wtp->sge_debug_data_high_index_6.eop[2],
+ wtp->sge_debug_data_high_index_3.eop[2],
+ wtp->ulp_se_cnt_chx.eop[2], wtp->utx_tpcside.eop[2],
+ wtp->tpcside_rxarb.eop[2], wtp->tpeside_mps.eop[2],
+ wtp->tp_mps.eop[2], wtp->mps_xgm.eop[2],
+ wtp->mac_portx_pkt_count.eop[2],
+ wtp->mac_portx_aframestra_ok.eop[2]);
+ printf("SOP_CH3 %02X %2X %2X %2X"\
+ " %2X %2X %2X %02X %02X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.sop[3],
+ wtp->sge_debug_data_high_index_6.sop[3],
+ wtp->sge_debug_data_high_index_3.sop[3],
+ wtp->ulp_se_cnt_chx.sop[3], wtp->utx_tpcside.sop[3],
+ wtp->tpcside_rxarb.sop[3], wtp->tpeside_mps.sop[3],
+ wtp->tp_mps.sop[3], wtp->mps_xgm.sop[3],
+ wtp->mac_portx_pkt_count.sop[3],
+ wtp->mac_portx_aframestra_ok.sop[3]);
+
+ printf("EOP_CH3 %02X %2X %2X %2X"\
+ " %2X %2X %2X %02X %02X %02X %02X\n",
+ wtp->pcie_t5_dma_stat3.eop[3],
+ wtp->sge_debug_data_high_index_6.eop[3],
+ wtp->sge_debug_data_high_index_3.eop[3],
+ wtp->ulp_se_cnt_chx.eop[3], wtp->utx_tpcside.eop[3],
+ wtp->tpcside_rxarb.eop[3], wtp->tpeside_mps.eop[3],
+ wtp->tp_mps.eop[3], wtp->mps_xgm.eop[3],
+ wtp->mac_portx_pkt_count.eop[3],
+ wtp->mac_portx_aframestra_ok.eop[3]);
+ printf("SOP %2X %2X %2X %2X "\
+ " %2X %2X %2X %2X %2X %2X %2X\n",
+ core_pcie_dma_rsp_sop, sge_debug_index6_sop,
+ pcie_sge_dma_rsp_sop, sge_utx_sop, utx_tp_sop,
+ tpcside_rxarb_sop, tpeside_mps_sop, tp_mps_sop,
+ mps_xgm_sop, tx_xgm_xgm_sop, xgm_wire_sop);
+ printf("EOP %2X %2X %2X %2X "\
+ " %2X %2X %2X %2X %2X %2X %2X\n",
+ core_pcie_dma_rsp_eop, sge_debug_index6_eop,
+ pcie_sge_dma_rsp_eop, sge_utx_eop, utx_tp_eop,
+ tpcside_rxarb_eop, tpeside_mps_eop, tp_mps_eop,
+ mps_xgm_eop, tx_xgm_xgm_eop, xgm_wire_eop);
+ printf("*************************INGRESS (RX) PATH **********************************\n");
+
+ printf("MOD core<-PCIE<---SGE<--CSW<-----TPC<-URX<-LE-TPE<-----MPS<--MAC<---wire\n");
+
+ printf("SOP_CH0 %2X %2X %2X %2X"\
+ " %2X %2X %2X %2X %2X %2X %02X %02X "\
+ "%02X\n",
+ wtp->pcie_dma1_stat2.sop[0],
+ wtp->sge_debug_data_high_indx7.sop[0],
+ wtp->sge_debug_data_high_indx1.sop[0],
+ wtp->sge_debug_data_high_indx9.sop[0],
+ wtp->utx_tpcside_tx.sop[0], wtp->ulprx_tpcside.sop[0],
+ wtp->pmrx_ulprx.sop[0], wtp->le_db_rsp_cnt.sop,
+ wtp->tp_dbg_eside_pktx.sop[0], wtp->mps_tp.sop[0],
+ wtp->xgm_mps.sop[0], wtp->mac_porrx_pkt_count.sop[0],
+ wtp->mac_porrx_aframestra_ok.sop[0]);
+
+ printf("EOP_CH0 %2X %2X %2X "\
+ "%2X %2X %2X %2X %2X %2X %2X %02X %02X "\
+ " %02X\n",
+ wtp->pcie_dma1_stat2.eop[0],
+ wtp->sge_debug_data_high_indx7.eop[0],
+ wtp->sge_debug_data_high_indx1.eop[0],
+ wtp->sge_debug_data_high_indx9.eop[0],
+ wtp->utx_tpcside_tx.eop[0], wtp->ulprx_tpcside.eop[0],
+ wtp->pmrx_ulprx.eop[0], wtp->le_db_rsp_cnt.eop,
+ wtp->tp_dbg_eside_pktx.eop[0], wtp->mps_tp.eop[0],
+ wtp->xgm_mps.eop[0], wtp->mac_porrx_pkt_count.eop[0],
+ wtp->mac_porrx_aframestra_ok.eop[0]);
+ printf("SOP_CH1 %2X %2X %2X "\
+ "%2X %2X %2X %2X %2X %2X %02X %02X "\
+ " %02X\n",
+ wtp->pcie_dma1_stat2.sop[1],
+ wtp->sge_debug_data_high_indx7.sop[1],
+ wtp->sge_debug_data_high_indx1.sop[1],
+ wtp->sge_debug_data_high_indx9.sop[1],
+ wtp->utx_tpcside_tx.sop[1], wtp->ulprx_tpcside.sop[1],
+ wtp->pmrx_ulprx.sop[1], wtp->tp_dbg_eside_pktx.sop[1],
+ wtp->mps_tp.sop[1], wtp->xgm_mps.sop[1],
+ wtp->mac_porrx_pkt_count.sop[1],
+ wtp->mac_porrx_aframestra_ok.sop[1]);
+
+ printf("EOP_CH1 %2X %2X %2X "\
+ "%2X %2X %2X %2X %2X %2X %02X %02X "\
+ " %02X\n",
+ wtp->pcie_dma1_stat2.eop[1],
+ wtp->sge_debug_data_high_indx7.eop[1],
+ wtp->sge_debug_data_high_indx1.eop[1],
+ wtp->sge_debug_data_high_indx9.eop[1],
+ wtp->utx_tpcside_tx.eop[1], wtp->ulprx_tpcside.eop[1],
+ wtp->pmrx_ulprx.eop[1], wtp->tp_dbg_eside_pktx.eop[1],
+ wtp->mps_tp.eop[1], wtp->xgm_mps.eop[1],
+ wtp->mac_porrx_pkt_count.eop[1],
+ wtp->mac_porrx_aframestra_ok.eop[1]);
+ printf("SOP_CH2 %2X %2X "\
+ " %2X %2X %02X %02X %02X\n",
+ wtp->pcie_dma1_stat2.sop[2],
+ wtp->sge_debug_data_high_indx7.sop[2],
+ wtp->tp_dbg_eside_pktx.sop[2], wtp->mps_tp.sop[2],
+ wtp->xgm_mps.sop[2], wtp->mac_porrx_pkt_count.sop[2],
+ wtp->mac_porrx_aframestra_ok.sop[2]);
+
+ printf("EOP_CH2 %2X %2X "\
+ " %2X %2X %02X %02X %02X\n",
+ wtp->pcie_dma1_stat2.eop[2],
+ wtp->sge_debug_data_high_indx7.eop[2],
+ wtp->tp_dbg_eside_pktx.eop[2], wtp->mps_tp.eop[2],
+ wtp->xgm_mps.eop[2], wtp->mac_porrx_pkt_count.eop[2],
+ wtp->mac_porrx_aframestra_ok.eop[2]);
+ printf("SOP_CH3 %2X %2X "\
+ " %2X %2X %02X %02X %02X\n",
+ wtp->pcie_dma1_stat2.sop[3],
+ wtp->sge_debug_data_high_indx7.sop[3],
+ wtp->tp_dbg_eside_pktx.sop[3], wtp->mps_tp.sop[3],
+ wtp->xgm_mps.sop[3], wtp->mac_porrx_pkt_count.sop[3],
+ wtp->mac_porrx_aframestra_ok.sop[3]);
+
+ printf("EOP_CH3 %2X %2X "\
+ " %2X %2X %02X %02X %02X\n",
+ wtp->pcie_dma1_stat2.eop[3],
+ wtp->sge_debug_data_high_indx7.eop[3],
+ wtp->tp_dbg_eside_pktx.eop[3], wtp->mps_tp.eop[3],
+ wtp->xgm_mps.eop[3], wtp->mac_porrx_pkt_count.eop[3],
+ wtp->mac_porrx_aframestra_ok.eop[3]);
+ printf("SOP_CH4 "\
+ " %02X\n",
+ wtp->xgm_mps.sop[4]);
+ printf("EOP_CH4 "\
+ " %02X\n",
+ wtp->xgm_mps.eop[4]);
+ printf("SOP_CH5 "\
+ " %02X\n",
+ wtp->xgm_mps.sop[5]);
+ printf("EOP_CH5 "\
+ " %02X\n",
+ wtp->xgm_mps.eop[5]);
+ printf("SOP_CH6 "\
+ " %02X\n",
+ wtp->xgm_mps.sop[6]);
+ printf("EOP_CH6 "\
+ " %02X\n",
+ wtp->xgm_mps.eop[6]);
+ printf("SOP_CH7 "\
+ " %02X\n",
+ wtp->xgm_mps.sop[7]);
+ printf("EOP_CH7 "\
+ " %02X\n",
+ wtp->xgm_mps.eop[7]);
+
+ printf("SOP %2X %2X %2X "\
+ "%2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
+ pcie_core_dmaw_sop, sge_pcie_sop, csw_sge_sop,
+ tp_csw_sop, tpcside_csw_sop, ulprx_tpcside_sop,
+ pmrx_ulprx_sop, mps_tpeside_sop, mps_tp_sop,
+ xgm_mps_sop, rx_xgm_xgm_sop, wire_xgm_sop);
+ printf("EOP %2X %2X %2X "\
+ "%2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
+ pcie_core_dmaw_eop, sge_pcie_eop,
+ csw_sge_eop, tp_csw_eop,
+ tpcside_csw_eop, ulprx_tpcside_eop,
+ pmrx_ulprx_eop, mps_tpeside_eop,
+ mps_tp_eop, xgm_mps_eop, rx_xgm_xgm_eop,
+ wire_xgm_eop);
+ printf("DROP: ??? ??? ??? "\
+ "%2X(mib) %2X(err) %2X(oflow) %X(cls)\n",
+ (wtp->mps_tp.drops & 0xFF),
+ (wtp->xgm_mps.err & 0xFF),
+ (wtp->xgm_mps.drop & 0xFF),
+ (wtp->xgm_mps.cls_drop & 0xFF));
+ printf("INTS: ");
+ for (i = 0; i < 4; i++) {
+ printf("%2X<- %2X ",
+ (wtp->pcie_core_dmai.sop[i] & 0xF),
+ (wtp->sge_pcie_ints.sop[i] & 0xF));
+ }
+ printf("(PCIE<-SGE, channels 0 to 3)\n");
+
+ return rc;
+}
+
+int
+view_wtp(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ int rc = -1;
+
+ if (is_t5(chip))
+ rc = t5_view_wtp(pbuf, entity_hdr, cudbg_poutbuf);
+ else if (is_t6(chip))
+ rc = t6_view_wtp(pbuf, entity_hdr, cudbg_poutbuf);
+
+ return rc;
+}
+
+/*
+ * * Small utility function to return the strings "yes" or "no" if the
+ * supplied
+ * * argument is non-zero.
+ * */
+static const char *
+yesno(int x)
+{
+ static const char *yes = "yes";
+ static const char *no = "no";
+
+ return x ? yes : no;
+}
+
+static int
+dump_indirect_regs(const struct cudbg_reg_info *reg_array,
+ u32 indirect_addr, const u32 *regs,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ uint32_t reg_val = 0; /* silence compiler warning*/
+ int i, rc;
+
+ for (i = 0 ; reg_array->name; ++reg_array) {
+ if (!reg_array->len) {
+ reg_val = regs[i];
+ i++;
+ printf("[0x%05x:0x%05x] "\
+ "%-47s %#-14x %u\n",
+ indirect_addr, reg_array->addr,
+ reg_array->name, reg_val, reg_val);
+ } else {
+ uint32_t v = xtract(reg_val, reg_array->addr,
+ reg_array->len);
+ printf(" %*u:%u %-55s "\
+ "%#-14x %u\n",
+ reg_array->addr < 10 ? 3 : 2,
+ reg_array->addr + reg_array->len - 1,
+ reg_array->addr, reg_array->name, v, v);
+ }
+ }
+
+ return 1;
+
+ return rc;
+}
+
+int
+view_cctrl(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ u16 (*incr)[NCCTRL_WIN];
+ int rc = 0;
+ u32 i = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ incr = (void *)dc_buff.data;
+ for (i = 0; i < NCCTRL_WIN; i++) {
+ printf("%2d: %4u %4u %4u %4u %4u "\
+ "%4u %4u %4u\n", i,
+ incr[0][i], incr[1][i], incr[2][i], incr[3][i],
+ incr[4][i], incr[5][i], incr[6][i], incr[7][i]);
+ printf("%8u %4u %4u %4u %4u %4u %4u"\
+ " %4u\n", incr[8][i], incr[9][i], incr[10][i],
+ incr[11][i], incr[12][i], incr[13][i],
+ incr[14][i], incr[15][i]);
+ }
+
+ return rc;
+}
+
+int
+view_up_cim_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf,
+ enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct ireg_buf *up_cim_indr;
+ u32 indirect_addr;
+ int rc = 0;
+ int i = 0;
+ int n = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ indirect_addr = A_CIM_HOST_ACC_CTRL;
+ up_cim_indr = (struct ireg_buf *)dc_buff.data;
+ if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5)
+ n = sizeof(t5_up_cim_reg_array) / (5 * sizeof(u32));
+ else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
+ n = sizeof(t6_up_cim_reg_array) / (5 * sizeof(u32));
+
+ for (i = 0; i < n; i++) {
+ u32 *buff = up_cim_indr->outbuf;
+
+ if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5)
+ rc = dump_indirect_regs(t5_up_cim_reg_ptr[i],
+ indirect_addr,
+ (const u32 *)buff,
+ cudbg_poutbuf);
+ else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
+ rc = dump_indirect_regs(t6_up_cim_reg_ptr[i],
+ indirect_addr,
+ (const u32 *)buff,
+ cudbg_poutbuf);
+
+ if (rc < 0)
+ goto err1;
+ up_cim_indr++;
+
+ /* Prohibit accessing data beyond entity size. This helps
+ * new app and old dump compatibily scenario
+ */
+ if ((char *)up_cim_indr >= (dc_buff.data + dc_buff.size))
+ break;
+ }
+
+err1:
+ return rc;
+}
+
+static int
+print_pbt_addr_entry(struct cudbg_buffer *cudbg_poutbuf, u32 val)
+{
+ char *fmts = "\n [%2u:%2u] %-10s ";
+ u32 vld, alloc, pending, address;
+ int rc = 0;
+
+ vld = (val >> 28) & 1;
+ printf(fmts, 28, 28, "vld");
+ printf("%d", vld);
+
+ alloc = (val >> 27) & 1;
+ printf(fmts, 27, 27, "alloc");
+ printf("%d", alloc);
+
+ pending = (val >> 26) & 1;
+ printf(fmts, 26, 26, "pending");
+ printf("%d", pending);
+
+ address = val & 0x1FFFFFF;
+ printf(fmts, 25, 0, "address<<6");
+ printf("0x%08x", address<<6);
+ printf("\n");
+
+
+ return rc;
+}
+
+int
+view_mbox_log(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_mbox_log *mboxlog = NULL;
+ struct cudbg_buffer c_buff, dc_buff;
+ u16 mbox_cmds;
+ int rc, i, k;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ mbox_cmds = (u16)dc_buff.size / sizeof(struct cudbg_mbox_log);
+ mboxlog = (struct cudbg_mbox_log *)dc_buff.data;
+ printf(
+ "%10s %15s %5s %5s %s\n", "Seq", "Tstamp", "Atime",
+ "Etime", "Command/Reply");
+
+ for (i = 0; i < mbox_cmds && mboxlog->entry.timestamp; i++) {
+ printf("%10u %15llu %5d %5d",
+ mboxlog->entry.seqno, mboxlog->entry.timestamp,
+ mboxlog->entry.access, mboxlog->entry.execute);
+
+ for (k = 0; k < MBOX_LEN / 8; k++)
+ printf(" %08x %08x",
+ mboxlog->hi[k], mboxlog->lo[k]);
+
+ printf("\n");
+ mboxlog++;
+ }
+
+ return rc;
+}
+
+int
+view_pbt_tables(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct cudbg_pbt_tables *pbt;
+ int rc = 0;
+ int i = 0;
+ u32 addr;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ pbt = (struct cudbg_pbt_tables *)dc_buff.data;
+ /* PBT dynamic entries */
+ addr = CUDBG_CHAC_PBT_ADDR;
+ for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) {
+ printf("Dynamic ");
+ printf("Addr Table [0x%03x]: 0x%08x",
+ (addr + (i * 4) - CUDBG_CHAC_PBT_ADDR),
+ pbt->pbt_dynamic[i]);
+ rc = print_pbt_addr_entry(cudbg_poutbuf, pbt->pbt_dynamic[i]);
+ if (rc < 0)
+ goto err1;
+ }
+
+ /* PBT static entries */
+ addr = CUDBG_CHAC_PBT_ADDR + (1 << 6);
+ for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) {
+ printf("Static ");
+ printf("Addr Table [0x%03x]: 0x%08x",
+ (addr + (i * 4) - CUDBG_CHAC_PBT_ADDR),
+ pbt->pbt_static[i]);
+ rc = print_pbt_addr_entry(cudbg_poutbuf, pbt->pbt_static[i]);
+ if (rc < 0)
+ goto err1;
+ }
+
+ /* PBT lrf entries */
+ addr = CUDBG_CHAC_PBT_LRF;
+ for (i = 0; i < CUDBG_LRF_ENTRIES; i++) {
+ printf(
+ "LRF Table [0x%03x]: 0x%08x\n",
+ (addr + (i * 4) - CUDBG_CHAC_PBT_LRF),
+ pbt->lrf_table[i]);
+ }
+
+ /* PBT data entries */
+ addr = CUDBG_CHAC_PBT_DATA;
+ for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) {
+ printf(
+ "DATA Table [0x%03x]: 0x%08x\n",
+ (addr + (i * 4) - CUDBG_CHAC_PBT_DATA),
+ pbt->pbt_data[i]);
+ }
+
+err1:
+ return rc;
+}
+
+int
+view_ma_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct ireg_buf *ma_indr;
+ u32 indirect_addr;
+ int rc = 0;
+ int i = 0;
+ int n;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ indirect_addr = A_MA_LOCAL_DEBUG_CFG;
+ ma_indr = (struct ireg_buf *)dc_buff.data;
+ n = sizeof(t6_ma_ireg_array) / (4 * sizeof(u32));
+ n += sizeof(t6_ma_ireg_array2) / (4 * sizeof(u32));
+ for (i = 0; i < n; i++) {
+ u32 *buff = ma_indr->outbuf;
+
+ rc = dump_indirect_regs(t6_ma_ptr[i], indirect_addr,
+ (const u32 *) buff, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ ma_indr++;
+ }
+
+err1:
+ return rc;
+}
+
+int
+view_hma_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct ireg_buf *hma_indr;
+ u32 indirect_addr;
+ int rc = 0;
+ int i = 0;
+ int n;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ indirect_addr = A_HMA_LOCAL_DEBUG_CFG;
+ hma_indr = (struct ireg_buf *)dc_buff.data;
+ n = sizeof(t6_hma_ireg_array) / (4 * sizeof(u32));
+ for (i = 0; i < n; i++) {
+ u32 *buff = hma_indr->outbuf;
+
+ rc = dump_indirect_regs(t6_hma_ptr[i], indirect_addr,
+ (const u32 *) buff, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ hma_indr++;
+ }
+
+err1:
+ return rc;
+}
+
+int
+view_pm_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct ireg_buf *ch_pm;
+ u32 indirect_addr;
+ int rc = 0;
+ int i = 0;
+ int n;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ ch_pm = (struct ireg_buf *)dc_buff.data;
+
+ if (!cudbg_poutbuf->data)
+ printf("\n\nPM_RX\n\n");
+
+ indirect_addr = PM_RX_INDIRECT;
+ n = sizeof(t5_pm_rx_array)/(4 * sizeof(u32));
+ for (i = 0; i < n; i++) {
+ u32 *buff = ch_pm->outbuf;
+
+ rc = dump_indirect_regs(t5_pm_rx_ptr[i], indirect_addr,
+ (const u32 *) buff, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+
+ ch_pm++;
+ }
+
+ if (!cudbg_poutbuf->data)
+ printf("\n\nPM_TX\n\n");
+
+ indirect_addr = PM_TX_INDIRECT;
+ n = sizeof(t5_pm_tx_array)/(4 * sizeof(u32));
+ for (i = 0; i < n; i++) {
+ u32 *buff = ch_pm->outbuf;
+
+ rc = dump_indirect_regs(t5_pm_tx_ptr[i], indirect_addr,
+ (const u32 *) buff, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ ch_pm++;
+ }
+
+err1:
+ return rc;
+}
+
+int
+view_tx_rate(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct tx_rate *tx_rate;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ tx_rate = (struct tx_rate *)dc_buff.data;
+ printf("\n\n\t\tTX_RATE\n\n");
+ if (tx_rate->nchan == NCHAN) {
+ printf(" channel 0 channel 1 channel 2 channel 3\n");
+ printf("NIC B/s: %10llu %10llu"\
+ " %10llu %10llu\n",
+ (unsigned long long)tx_rate->nrate[0],
+ (unsigned long long)tx_rate->nrate[1],
+ (unsigned long long)tx_rate->nrate[2],
+ (unsigned long long)tx_rate->nrate[3]);
+ printf("Offload B/s: %10llu %10llu"\
+ " %10llu %10llu\n",
+ (unsigned long long)tx_rate->orate[0],
+ (unsigned long long)tx_rate->orate[1],
+ (unsigned long long)tx_rate->orate[2],
+ (unsigned long long)tx_rate->orate[3]);
+ } else {
+ printf(" channel 0 "\
+ "channel 1\n");
+ printf("NIC B/s: %10llu "\
+ "%10llu\n",
+ (unsigned long long)tx_rate->nrate[0],
+ (unsigned long long)tx_rate->nrate[1]);
+ printf("Offload B/s: %10llu "\
+ "%10llu\n",
+ (unsigned long long)tx_rate->orate[0],
+ (unsigned long long)tx_rate->orate[1]);
+ }
+
+ return rc;
+}
+
+int
+view_tid(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct tid_info_region_rev1 *tid1;
+ struct tid_info_region *tid;
+ u32 tid_start = 0;
+ int rc = 0, rev;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ rev = get_entity_rev((struct cudbg_ver_hdr *)dc_buff.data);
+ if (rev) {
+ tid1 = (struct tid_info_region_rev1 *)(dc_buff.data);
+ tid_start = tid1->tid_start;
+ tid = &(tid1->tid);
+ } else
+ tid = (struct tid_info_region *)dc_buff.data;
+
+ printf("\n\n\tTID INFO\n\n");
+ if (tid->le_db_conf & F_HASHEN) {
+ if (tid->sb) {
+ printf("TID range: "\
+ "%u..%u/%u..%u\n", tid_start, tid->sb - 1,
+ tid->hash_base, tid->ntids - 1);
+ } else if (tid->flags & FW_OFLD_CONN) {
+ printf("TID range: "\
+ "%u..%u/%u..%u\n", tid->aftid_base,
+ tid->aftid_end, tid->hash_base,
+ tid->ntids - 1);
+
+ } else {
+ printf("TID range: "\
+ "%u..%u\n", tid->hash_base,
+ tid->ntids - 1);
+ }
+ } else if (tid->ntids) {
+ printf("TID range: %u..%u\n",
+ tid_start, tid->ntids - 1);
+ }
+
+ if (tid->nstids)
+ printf("STID range: %u..%u\n",
+ tid->stid_base, tid->stid_base + tid->nstids - 1);
+
+#if 0 /*For T4 cards*/
+ if (tid->nsftids)
+ printf("SFTID range: %u..%u\n",
+ tid->sftid_base,
+ tid->sftid_base + tid->nsftids - 2);
+#endif
+
+ if (tid->nuotids)
+ printf("UOTID range: %u..%u\n",
+ tid->uotid_base,
+ tid->uotid_base + tid->nuotids - 1);
+
+ if (tid->nhpftids && is_t6(chip))
+ printf("HPFTID range: %u..%u\n",
+ tid->hpftid_base,
+ tid->hpftid_base + tid->nhpftids - 1);
+ if (tid->ntids)
+ printf("HW TID usage: %u IP users, "\
+ "%u IPv6 users\n",
+ tid->IP_users, tid->IPv6_users);
+
+ return rc;
+}
+
+static int
+show_cntxt(struct cudbg_ch_cntxt *context,
+ struct cudbg_cntxt_field *field,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ char str[8];
+ int rc = 0;
+
+ if (context->cntxt_type == CTXT_EGRESS)
+ strcpy(str, "egress");
+ if (context->cntxt_type == CTXT_INGRESS)
+ strcpy(str, "ingress");
+ if (context->cntxt_type == CTXT_FLM)
+ strcpy(str, "fl");
+ if (context->cntxt_type == CTXT_CNM)
+ strcpy(str, "cong");
+ printf("\n\nContext type: %-47s\nQueue ID: "\
+ "%-10d\n", str, context->cntxt_id);
+
+ while (field->name) {
+ unsigned long long data;
+
+ u32 index = field->start_bit / 32;
+ u32 bits = field->start_bit % 32;
+ u32 width = field->end_bit - field->start_bit + 1;
+ u32 mask = (1ULL << width) - 1;
+
+ data = (unsigned long long)((context->data[index] >> bits) |
+ ((u64)context->data[index + 1] << (32 - bits)));
+ if (bits)
+ data |= ((u64)context->data[index + 2] << (64 - bits));
+ data &= mask;
+
+ if (field->islog2)
+ data = (unsigned long long)1 << data;
+
+ printf("%-47s %#-10llx\n",
+ field->name, data << field->shift);
+ field++;
+ }
+
+ return rc;
+}
+
+int
+view_mps_tcam(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct cudbg_mps_tcam *tcam;
+ int rc = 0;
+ int n, i;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ n = dc_buff.size / sizeof(struct cudbg_mps_tcam);
+ tcam = (struct cudbg_mps_tcam *)dc_buff.data;
+ if (is_t6(chip)) {
+ printf("Idx Ethernet address "\
+ "Mask VNI Mask IVLAN Vld DIP_Hit "\
+ "Lookup Port Vld Ports PF VF "\
+ " Replication "\
+ " P0 P1 P2 P3 ML\n");
+ } else if (is_t5(chip)) {
+ if (tcam->rplc_size > CUDBG_MAX_RPLC_SIZE) {
+ printf("Idx Ethernet "\
+ "address Mask Vld Ports PF VF "\
+ " Replication "\
+ " P0 P1 "\
+ "P2 P3 ML\n");
+ } else {
+ printf("Idx Ethernet "\
+ "address Mask Vld Ports PF VF "\
+ " Replication P0"\
+ " P1 P2 P3 ML\n");
+ }
+ }
+
+ for (i = 0; i < n; i++, tcam++) {
+ /* Print only valid MPS TCAM entries */
+ if (i && !tcam->idx)
+ continue;
+
+ if (is_t6(chip)) {
+ /* Inner header lookup */
+ if (tcam->lookup_type && (tcam->lookup_type !=
+ M_DATALKPTYPE)) {
+ printf("%3u "\
+ "%02x:%02x:%02x:%02x:%02x:%02x "\
+ "%012llx %06x %06x - - "\
+ "%3c %3c %4x %3c "\
+ "%#x%4u%4d",
+ tcam->idx, tcam->addr[0],
+ tcam->addr[1], tcam->addr[2],
+ tcam->addr[3], tcam->addr[4],
+ tcam->addr[5],
+ (unsigned long long)tcam->mask,
+ tcam->vniy, (tcam->vnix | tcam->vniy),
+ tcam->dip_hit ? 'Y' : 'N',
+ tcam->lookup_type ? 'I' : 'O',
+ tcam->port_num,
+ (tcam->cls_lo & F_T6_SRAM_VLD)
+ ? 'Y' : 'N',
+ G_PORTMAP(tcam->cls_hi),
+ G_T6_PF(tcam->cls_lo),
+ (tcam->cls_lo & F_T6_VF_VALID)
+ ?
+ G_T6_VF(tcam->cls_lo) : -1);
+ } else {
+ printf("%3u "\
+ "%02x:%02x:%02x:%02x:%02x:%02x"\
+ " %012llx - - ",
+ tcam->idx, tcam->addr[0],
+ tcam->addr[1], tcam->addr[2],
+ tcam->addr[3], tcam->addr[4],
+ tcam->addr[5],
+ (unsigned long long)tcam->mask);
+
+ if (tcam->vlan_vld) {
+ printf(
+ "%4u Y ",
+ tcam->ivlan);
+ } else {
+ printf(
+ " - N ");
+ }
+
+ printf(
+ "- %3c %4x %3c "\
+ "%#x%4u%4d",
+ tcam->lookup_type ? 'I' : 'O',
+ tcam->port_num,
+ (tcam->cls_lo & F_T6_SRAM_VLD)
+ ? 'Y' : 'N',
+ G_PORTMAP(tcam->cls_hi),
+ G_T6_PF(tcam->cls_lo),
+ (tcam->cls_lo & F_T6_VF_VALID)
+ ?
+ G_T6_VF(tcam->cls_lo) : -1);
+ }
+ } else if (is_t5(chip)) {
+ printf("%3u "\
+ "%02x:%02x:%02x:%02x:%02x:%02x %012llx%3c"\
+ " %#x%4u%4d",
+ tcam->idx, tcam->addr[0], tcam->addr[1],
+ tcam->addr[2], tcam->addr[3],
+ tcam->addr[4], tcam->addr[5],
+ (unsigned long long)tcam->mask,
+ (tcam->cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
+ G_PORTMAP(tcam->cls_hi),
+ G_PF(tcam->cls_lo),
+ (tcam->cls_lo & F_VF_VALID) ?
+ G_VF(tcam->cls_lo) : -1);
+ }
+
+ if (tcam->repli) {
+ if (tcam->rplc_size > CUDBG_MAX_RPLC_SIZE) {
+ printf(" %08x %08x "\
+ "%08x %08x %08x %08x %08x %08x",
+ tcam->rplc[7], tcam->rplc[6],
+ tcam->rplc[5], tcam->rplc[4],
+ tcam->rplc[3], tcam->rplc[2],
+ tcam->rplc[1], tcam->rplc[0]);
+ } else {
+ printf(" %08x %08x "\
+ "%08x %08x", tcam->rplc[3],
+ tcam->rplc[2], tcam->rplc[1],
+ tcam->rplc[0]);
+ }
+ } else {
+ if (tcam->rplc_size > CUDBG_MAX_RPLC_SIZE)
+ printf("%72c", ' ');
+ else
+ printf("%36c", ' ');
+ }
+ if (is_t6(chip)) {
+ printf( "%4u%3u%3u%3u %#x\n",
+ G_T6_SRAM_PRIO0(tcam->cls_lo),
+ G_T6_SRAM_PRIO1(tcam->cls_lo),
+ G_T6_SRAM_PRIO2(tcam->cls_lo),
+ G_T6_SRAM_PRIO3(tcam->cls_lo),
+ (tcam->cls_lo >> S_T6_MULTILISTEN0) & 0xf);
+ } else if (is_t5(chip)) {
+ printf("%4u%3u%3u%3u %#x\n",
+ G_SRAM_PRIO0(tcam->cls_lo),
+ G_SRAM_PRIO1(tcam->cls_lo),
+ G_SRAM_PRIO2(tcam->cls_lo),
+ G_SRAM_PRIO3(tcam->cls_lo),
+ (tcam->cls_lo >> S_MULTILISTEN0) & 0xf);
+ }
+ }
+
+ return rc;
+}
+
+int
+view_dump_context(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct cudbg_ch_cntxt *context;
+ int rc = 0;
+ int n, i;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ n = dc_buff.size / sizeof(struct cudbg_ch_cntxt);
+ context = (struct cudbg_ch_cntxt *)dc_buff.data;
+ for (i = 0; i < n; i++, context++) {
+ /* Only print valid contexts */
+ if (context->cntxt_type != CTXT_CNM) {
+ rc = cudbg_sge_ctxt_check_valid(context->data,
+ context->cntxt_type);
+ if (!rc)
+ continue;
+ }
+
+ if (context->cntxt_type == CTXT_EGRESS) {
+ if (is_t5(chip))
+ rc = show_cntxt(context, t5_egress_cntxt,
+ cudbg_poutbuf);
+ else if (is_t6(chip))
+ rc = show_cntxt(context, t6_egress_cntxt,
+ cudbg_poutbuf);
+ } else if (context->cntxt_type == CTXT_INGRESS) {
+ if (is_t5(chip))
+ rc = show_cntxt(context, t5_ingress_cntxt,
+ cudbg_poutbuf);
+ else if (is_t6(chip))
+ rc = show_cntxt(context, t6_ingress_cntxt,
+ cudbg_poutbuf);
+ } else if (context->cntxt_type == CTXT_CNM)
+ rc = show_cntxt(context, t5_cnm_cntxt, cudbg_poutbuf);
+ else if (context->cntxt_type == CTXT_FLM) {
+ if (is_t5(chip))
+ rc = show_cntxt(context, t5_flm_cntxt,
+ cudbg_poutbuf);
+ else if (is_t6(chip))
+ rc = show_cntxt(context, t6_flm_cntxt,
+ cudbg_poutbuf);
+ }
+
+ if (rc < 0)
+ goto err1;
+ }
+
+err1:
+ return rc;
+}
+
+int
+view_le_tcam(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ char *le_region[] = {
+ "active", "server", "filter", "clip", "routing"
+ };
+ struct cudbg_tid_data *tid_data = NULL;
+ struct cudbg_tcam *tcam_region = NULL;
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0, j;
+ u32 i;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ tcam_region = (struct cudbg_tcam *)dc_buff.data;
+ tid_data = (struct cudbg_tid_data *)(tcam_region + 1);
+ printf("\n\nRouting table index: 0x%X\n",
+ tcam_region->routing_start);
+ printf("Lip comp table index: 0x%X\n",
+ tcam_region->clip_start);
+ printf("Filter table index: 0x%X\n",
+ tcam_region->filter_start);
+ printf("Server index: 0x%X\n\n",
+ tcam_region->server_start);
+
+ printf("tid start: %d\n\n", 0);
+ printf("tid end: %d\n\n",
+ tcam_region->max_tid);
+
+ for (i = 0; i < tcam_region->max_tid; i++) {
+ printf(
+ "======================================================================================\n");
+ printf("This is a LE_DB_DATA_READ "\
+ "command: on TID %d at index %d\n", i, i * 4);
+ if (i < tcam_region->server_start / 4) {
+ printf("Region: %s\n\n",
+ le_region[0]);
+ } else if ((i >= tcam_region->server_start / 4) &&
+ (i < tcam_region->filter_start / 4)) {
+ printf("Region: %s\n\n",
+ le_region[1]);
+ } else if ((i >= tcam_region->filter_start / 4) &&
+ (i < tcam_region->clip_start / 4)) {
+ printf("Region: %s\n\n",
+ le_region[2]);
+ } else if ((i >= tcam_region->clip_start / 4) &&
+ (i < tcam_region->routing_start / 4)) {
+ printf("Region: %s\n\n",
+ le_region[3]);
+ } else if (i >= tcam_region->routing_start / 4) {
+ printf("Region: %s\n\n",
+ le_region[4]);
+ }
+
+ printf("READ:\n");
+ printf("DBGICMDMODE: %s\n",
+ (tid_data->dbig_conf & 1) ? "LE" : "TCAM");
+ printf("READING TID: 0x%X\n",
+ tid_data->tid);
+ printf("Write: "\
+ "LE_DB_DBGI_REQ_TCAM_CMD: 0x%X\n",
+ tid_data->dbig_cmd);
+ printf("Write: LE_DB_DBGI_CONFIG "\
+ "0x%X\n", tid_data->dbig_conf);
+ printf("Polling: LE_DB_DBGI_CONFIG:"\
+ " busy bit\n");
+ printf("Read: "\
+ "LE_DB_DBGI_RSP_STATUS: 0x%X [%d]\n",
+ tid_data->dbig_rsp_stat & 1,
+ tid_data->dbig_rsp_stat & 1);
+ printf("Read: "\
+ "LE_DB_DBGI_RSP_DATA:\n");
+ printf("Response data for TID "\
+ "0x%X:\n", i);
+
+ for (j = 0; j < CUDBG_NUM_REQ_REGS; j++) {
+ printf("\t0x%X: 0x%08X\n",
+ A_LE_DB_DBGI_RSP_DATA + (j << 2),
+ tid_data->data[j]);
+ }
+
+ printf("DATA READ: ");
+ for (j = CUDBG_NUM_REQ_REGS - 1; j >= 0; j--) {
+ printf("%08X",
+ tid_data->data[j]);
+ }
+ printf("\n\n");
+
+ tid_data++;
+ }
+
+ return rc;
+}
+
+int
+view_pcie_config(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ u32 *pcie_config;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ if (!cudbg_poutbuf->data)
+ printf("\n\t\t\tPCIE CONFIG\n\n");
+
+ pcie_config = (u32 *)dc_buff.data;
+ rc = dump_indirect_regs(t5_pcie_config_ptr[0], 0,
+ (const u32 *)pcie_config, cudbg_poutbuf);
+
+ return rc;
+}
+
+int
+view_pcie_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct ireg_buf *ch_pcie;
+ u32 indirect_addr;
+ int rc = 0;
+ int i = 0;
+ int n;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ if (!cudbg_poutbuf->data)
+ printf("\n\nPCIE_PDBG\n\n");
+
+ indirect_addr = PCIE_PDEBUG_INDIRECT;
+ ch_pcie = (struct ireg_buf *)dc_buff.data;
+ n = sizeof(t5_pcie_pdbg_array)/(4 * sizeof(u32));
+ for (i = 0; i < n; i++) {
+ u32 *buff = ch_pcie->outbuf;
+
+ rc = dump_indirect_regs(t5_pcie_pdbg_ptr[i], indirect_addr,
+ (const u32 *) buff, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ ch_pcie++;
+ }
+
+ if (!cudbg_poutbuf->data)
+ printf("\n\nPCIE_CDBG\n\n");
+
+ indirect_addr = PCIE_CDEBUG_INDIRECT;
+ n = sizeof(t5_pcie_cdbg_array)/(4 * sizeof(u32));
+ for (i = 0; i < n; i++) {
+ u32 *buff = ch_pcie->outbuf;
+
+ rc = dump_indirect_regs(t5_pcie_cdbg_ptr[i], indirect_addr,
+ (const u32 *) buff, cudbg_poutbuf);
+ if (rc < 0)
+ goto err1;
+ ch_pcie++;
+ }
+
+err1:
+ return rc;
+}
+
+int
+view_tp_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ int j = 0, k, l, len, n = 0;
+ struct ireg_buf *ch_tp_pio;
+ u32 indirect_addr;
+ u32 *pkey = NULL;
+ int rc = 0;
+ int i = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ ch_tp_pio = (struct ireg_buf *)dc_buff.data;
+ l = 0;
+
+ indirect_addr = TP_PIO;
+ if (!cudbg_poutbuf->data)
+ printf("\n\nTP_PIO\n\n");
+
+ if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
+ n = sizeof(t5_tp_pio_array)/(4 * sizeof(u32));
+ else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
+ n = sizeof(t6_tp_pio_array)/(4 * sizeof(u32));
+
+ for (i = 0; i < n; i++) {
+ u32 *buff = ch_tp_pio->outbuf;
+
+ if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
+ rc = dump_indirect_regs(t5_tp_pio_ptr[i], indirect_addr,
+ (const u32 *) buff,
+ cudbg_poutbuf);
+ else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
+ rc = dump_indirect_regs(t6_tp_pio_ptr[i], indirect_addr,
+ (const u32 *) buff,
+ cudbg_poutbuf);
+
+ if (rc < 0)
+ goto err1;
+
+ ch_tp_pio++;
+ }
+
+ indirect_addr = TP_TM_PIO_ADDR;
+ if (!cudbg_poutbuf->data)
+ printf("\n\nTP_TM_PIO\n\n");
+
+ l = 0;
+ if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
+ n = sizeof(t5_tp_tm_pio_array)/(4 * sizeof(u32));
+ else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
+ n = sizeof(t6_tp_tm_pio_array)/(4 * sizeof(u32));
+
+ for (i = 0; i < n; i++) {
+ u32 *buff = ch_tp_pio->outbuf;
+
+ if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
+ rc = dump_indirect_regs(t5_tp_tm_regs, indirect_addr,
+ (const u32 *)buff,
+ cudbg_poutbuf);
+ else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
+ rc = dump_indirect_regs(t6_tp_tm_regs, indirect_addr,
+ (const u32 *)buff,
+ cudbg_poutbuf);
+
+ if (rc < 0)
+ goto err1;
+
+ ch_tp_pio++;
+ }
+ indirect_addr = TP_MIB_INDEX;
+ if (!cudbg_poutbuf->data)
+ printf("\n\nTP_MIB_INDEX\n\n");
+
+ l = 0;
+ if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
+ n = sizeof(t5_tp_mib_index_array)/(4 * sizeof(u32));
+ else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
+ n = sizeof(t6_tp_mib_index_array)/(4 * sizeof(u32));
+ for (i = 0; i < n ; i++) {
+ u32 *buff = ch_tp_pio->outbuf;
+
+ pkey = (u32 *) buff;
+ if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
+ j = l + t5_tp_mib_index_array[i][3];
+ else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6)
+ j = l + t6_tp_mib_index_array[i][3];
+
+ len = 0;
+ for (k = l; k < j; k++) {
+ if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) {
+ printf("[0x%x:%2s]"\
+ " %-47s %#-10x %u\n",
+ indirect_addr,
+ t5_tp_mib_index_reg_array[k].addr,
+ t5_tp_mib_index_reg_array[k].name,
+ pkey[len], pkey[len]);
+ } else if (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6) {
+ printf("[0x%x:%2s]"\
+ " %-47s %#-10x %u\n",
+ indirect_addr,
+ t6_tp_mib_index_reg_array[k].addr,
+ t6_tp_mib_index_reg_array[k].name,
+ pkey[len], pkey[len]);
+ }
+ len++;
+ }
+ l = k;
+ ch_tp_pio++;
+ }
+
+err1:
+ return rc;
+}
+
+int
+find_index_in_t6_sge_regs(u32 addr)
+{
+ u32 i = 0;
+
+ while (t6_sge_regs[i].name) {
+ if (t6_sge_regs[i].addr == addr)
+ return i;
+ i++;
+ }
+
+ return -1;
+}
+
+void
+print_t6_sge_reg_value(u32 reg_addr, u32 reg_data, u32 data_value,
+ int idx_map, struct cudbg_buffer *cudbg_poutbuf)
+{
+ struct reg_info *reg_array = &t6_sge_regs[idx_map];
+ u32 value;
+
+ printf("[0x%x:0x%x] %-47s %#-10x %u\n",
+ reg_addr, reg_data, reg_array->name, data_value,
+ data_value);
+
+ reg_array++;
+ while (reg_array->len) {
+ value = xtract(data_value, reg_array->addr, reg_array->len);
+
+ printf(" %-3u:%3u %-47s "\
+ "%#-10x %u\n",
+ reg_array->addr + reg_array->len - 1,
+ reg_array->addr, reg_array->name, value, value);
+
+ reg_array++;
+ }
+
+
+ return;
+}
+
+void
+print_sge_qbase(struct sge_qbase_reg_field *sge_qbase, u32 pf_vf_count,
+ int isPF, struct cudbg_buffer *cudbg_poutbuf)
+{
+ u32 *data_value;
+ u32 f;
+ int idx_map0, idx_map1, idx_map2, idx_map3;
+
+ idx_map0 = find_index_in_t6_sge_regs(sge_qbase->reg_data[0]);
+ idx_map1 = find_index_in_t6_sge_regs(sge_qbase->reg_data[1]);
+ idx_map2 = find_index_in_t6_sge_regs(sge_qbase->reg_data[2]);
+ idx_map3 = find_index_in_t6_sge_regs(sge_qbase->reg_data[3]);
+
+ if (idx_map0 < 0 || idx_map1 < 0 || idx_map2 < 0 || idx_map3 < 0) {
+ printf("Error: one of these addr is "\
+ "wrong: 0x%x 0x%x 0x%x 0x%x\n", sge_qbase->reg_data[0],
+ sge_qbase->reg_data[1], sge_qbase->reg_data[2],
+ sge_qbase->reg_data[3]);
+ return;
+ }
+
+ for (f = 0; f < pf_vf_count; f++) {
+ if (isPF)
+ data_value = (u32 *)sge_qbase->pf_data_value[f];
+ else
+ data_value = (u32 *)sge_qbase->vf_data_value[f];
+ printf("\nSGE_QBASE_INDEX for %s %d\n",
+ isPF ? "pf" : "vf", f);
+ print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[0],
+ data_value[0], idx_map0, cudbg_poutbuf);
+
+ print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[1],
+ data_value[1], idx_map1, cudbg_poutbuf);
+
+ print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[2],
+ data_value[2], idx_map2, cudbg_poutbuf);
+
+ print_t6_sge_reg_value(sge_qbase->reg_addr, sge_qbase->reg_data[3],
+ data_value[3], idx_map3, cudbg_poutbuf);
+ }
+
+ return;
+}
+
+int
+view_sge_indirect(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct sge_qbase_reg_field *sge_qbase;
+ u32 indirect_addr;
+ u32 *pkey = NULL;
+ int j, k, len;
+ int rc = 0;
+ int i = 0;
+ int l = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ pkey = (u32 *) (dc_buff.data + sizeof(struct ireg_field));
+ indirect_addr = SGE_DEBUG_DATA_INDIRECT;
+ for (i = 0; i < 2; i++) {
+ printf("\n");
+ j = l + t5_sge_dbg_index_array[i][3];
+ len = 0;
+ for (k = l; k < j; k++) {
+ if (i == 0) {
+ printf("[0x%x:0x%x]"\
+ " %-47s %#-10x %u\n",
+ indirect_addr,
+ sge_debug_data_high[k].addr,
+ sge_debug_data_high[k].name,
+ pkey[len], pkey[len]);
+ } else {
+ printf("[0x%x:0x%x]"\
+ " %-47s %#-10x %u\n",
+ indirect_addr,
+ sge_debug_data_low[k].addr,
+ sge_debug_data_low[k].name,
+ pkey[len], pkey[len]);
+ }
+ len++;
+ }
+ pkey = (u32 *)((char *)pkey + sizeof(struct ireg_buf));
+ }
+
+ if (is_t6(chip)) {
+ dc_buff.offset = 2 * sizeof(struct ireg_buf);
+
+ if (dc_buff.size <= dc_buff.offset)
+ goto err1;
+
+ sge_qbase = (struct sge_qbase_reg_field *)(dc_buff.data +
+ dc_buff.offset);
+ print_sge_qbase(sge_qbase, 8, 1, cudbg_poutbuf);
+ print_sge_qbase(sge_qbase, sge_qbase->vfcount, 0,
+ cudbg_poutbuf);
+ }
+
+err1:
+ return rc;
+}
+
+static int
+view_full_t6(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ u32 pcie_c0rd_full, pcie_c0wr_full, pcie_c0rsp_full;
+ u32 pcie_c1rd_full, pcie_c1wr_full, pcie_c1rsp_full;
+ u32 rx_fifo_cng, rx_pcmd_cng, rx_hdr_cng;
+ u32 tx, rx, cs, es, pcie, pcie1, sge;
+ struct cudbg_buffer c_buff, dc_buff;
+ u32 sge_req_full = 0, sge_rx_full;
+ u32 cng0, cng1;
+ int rc = 0;
+ u32 *sp;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ sp = (u32 *)dc_buff.data;
+
+ /* Collect Registers:
+ * TP_DBG_SCHED_TX (0x7e40 + 0x6a),
+ * TP_DBG_SCHED_RX (0x7e40 + 0x6b),
+ * TP_DBG_CSIDE_INT (0x7e40 + 0x23f),
+ * TP_DBG_ESIDE_INT (0x7e40 + 0x148),
+ * PCIE_CDEBUG_INDEX[AppData0] (0x5a10 + 2),
+ * PCIE_CDEBUG_INDEX[AppData1] (0x5a10 + 3),
+ * SGE_DEBUG_DATA_HIGH_INDEX_10 (0x12a8)
+ **/
+ tx = *sp;
+ rx = *(sp + 1);
+ cs = *(sp + 2);
+ es = *(sp + 3);
+ pcie = *(sp + 4);
+ pcie1 = *(sp + 5);
+ sge = *(sp + 6);
+
+ pcie_c0wr_full = pcie & 1;
+ pcie_c0rd_full = (pcie >> 2) & 1;
+ pcie_c0rsp_full = (pcie >> 4) & 1;
+
+ pcie_c1wr_full = pcie1 & 1;
+ pcie_c1rd_full = (pcie1 >> 2) & 1;
+ pcie_c1rsp_full = (pcie1 >> 4) & 1;
+
+ /* sge debug_PD_RdRspAFull_d for each channel */
+ sge_rx_full = (sge >> 30) & 0x3;
+
+ rx_fifo_cng = (rx >> 20) & 0xf;
+ rx_pcmd_cng = (rx >> 14) & 0x3;
+ rx_hdr_cng = (rx >> 8) & 0xf;
+ cng0 = (rx_fifo_cng & 1) | (rx_pcmd_cng & 1) | (rx_hdr_cng & 1);
+ cng1 = ((rx_fifo_cng & 2) >> 1) | ((rx_pcmd_cng & 2) >> 1) |
+ ((rx_hdr_cng & 2) >> 1);
+
+ printf("\n");
+ /* TP resource reservation */
+ printf("Tx0 ==%1u=> T <=%1u= Rx0\n",
+ ((tx >> 28) & 1), ((rx >> 28) & 1));
+ printf("Tx1 ==%1u=> P <=%1u= Rx1\n",
+ ((tx >> 29) & 1), ((rx >> 29) & 1));
+ printf("\n");
+
+ /* TX path */
+ /* pcie bits 19:16 are D_RspAFull for each channel */
+ /* Tx is blocked when Responses from system cannot flow toward TP. */
+ printf("Tx0 P =%1u=> S ? U =>%1u=> T\n",
+ pcie_c0rsp_full, ((cs >> 24) & 1));
+ printf("Tx1 C =%1u=> G ? T =>%1u=> P\n",
+ pcie_c1rsp_full, ((cs >> 25) & 1));
+
+ /* RX path */
+ /* Rx is blocked when sge and/or pcie cannot send requests to system.
+ * */
+ printf(" Rd Wr\n");
+ printf("RX0 P <=%1u=%1u=%1u S <=%1u= C "\
+ "<=%1u= T <=T <=%1u= T <=%1u= M\n",
+ ((pcie_c0rd_full >> 0) & 1), ((pcie_c0wr_full >> 0) & 1),
+ ((sge_req_full >> 0) & 1), ((sge_rx_full >> 0) & 1),
+ cng0, ((cs >> 20) & 1), ((es >> 16) & 1));
+#ifndef __CHECKER__
+ printf("RX1 C <=%1u=%1u=%1u G <=%1u= X "\
+ "<=%1u= C <=P <=%1u= E <=%1u= P\n",
+ ((pcie_c1rd_full >> 1) & 1), ((pcie_c1wr_full >> 1) & 1),
+ ((sge_req_full >> 1) & 1), ((sge_rx_full >> 1) & 1),
+ cng1, ((cs >> 21) & 1), ((es >> 17) & 1));
+#endif
+ printf("\n");
+
+
+ return rc;
+}
+
+static int
+view_full_t5(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf)
+{
+ u32 sge_rsp_full, sge_req_full, sge_rx_full;
+ u32 rx_fifo_cng, rx_pcmd_cng, rx_hdr_cng;
+ struct cudbg_buffer c_buff, dc_buff;
+ u32 pcie_rd_full, pcie_wr_full;
+ u32 tx, rx, cs, es, pcie, sge;
+ u32 cng0, cng1;
+ int rc = 0;
+ u32 *sp;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ sp = (u32 *)dc_buff.data;
+
+ /* Collect Registers:
+ * TP_DBG_SCHED_TX (0x7e40 + 0x6a),
+ * TP_DBG_SCHED_RX (0x7e40 + 0x6b),
+ * TP_DBG_CSIDE_INT (0x7e40 + 0x23f),
+ * TP_DBG_ESIDE_INT (0x7e40 + 0x148),
+ * PCIE_CDEBUG_INDEX[AppData0] (0x5a10 + 2),
+ * SGE_DEBUG_DATA_HIGH_INDEX_10 (0x12a8)
+ **/
+ tx = *sp;
+ rx = *(sp + 1);
+ cs = *(sp + 2);
+ es = *(sp + 3);
+ pcie = *(sp + 4);
+ sge = *(sp + 5);
+
+ pcie_rd_full = (pcie >> 8) & 0xf;
+ pcie_wr_full = pcie & 0xf;
+
+ /* OR together D_RdReqAFull and D_WrReqAFull for pcie */
+
+ /* sge debug_PD_RdRspAFull_d for each channel */
+ sge_rsp_full = ((sge >> 26) & 0xf);
+ /* OR together sge debug_PD_RdReqAFull_d and debug PD_WrReqAFull_d */
+ sge_req_full = ((sge >> 22) & 0xf) | ((sge >> 18) & 0xf);
+ sge_rx_full = (sge >> 30) & 0x3;
+
+ rx_fifo_cng = (rx >> 20) & 0xf;
+ rx_pcmd_cng = (rx >> 14) & 0x3;
+ rx_hdr_cng = (rx >> 8) & 0xf;
+ cng0 = (rx_fifo_cng & 1) | (rx_pcmd_cng & 1) | (rx_hdr_cng & 1);
+ cng1 = ((rx_fifo_cng & 2) >> 1) | ((rx_pcmd_cng & 2) >> 1) |
+ ((rx_hdr_cng & 2) >> 1);
+
+ printf("\n");
+ /* TP resource reservation */
+ printf("Tx0 ==%1u=\\ /=%1u= Rx0\n",
+ ((tx >> 28) & 1), ((rx >> 28) & 1));
+ printf("Tx1 ==%1u= | T | =%1u= Rx1\n",
+ ((tx >> 29) & 1), ((rx >> 29) & 1));
+ printf("Tx2 ==%1u= | P | =%1u= Rx2\n",
+ ((tx >> 30) & 1), ((rx >> 30) & 1));
+ printf("Tx3 ==%1u=/ \\=%1u= Rx3\n",
+ ((tx >> 31) & 1), ((rx >> 31) & 1));
+ printf("\n");
+
+ /* TX path */
+ /* pcie bits 19:16 are D_RspAFull for each channel */
+ /* Tx is blocked when Responses from system cannot flow toward TP. */
+ printf("Tx0 P =%1u=%1u=\\ S ? U ==%1u=\\\n",
+ ((pcie >> 16) & 1), (sge_rsp_full & 1), ((cs >> 24) & 1));
+ printf("Tx1 C =%1u=%1u= |G ? T ==%1u= | T\n",
+ ((pcie >> 17) & 1), ((sge_rsp_full >> 1) & 1),
+ ((cs >> 25) & 1));
+ printf("Tx2 I =%1u=%1u= |E ? X ==%1u= | P\n",
+ ((pcie >> 18) & 1), ((sge_rsp_full >> 2) & 1),
+ ((cs >> 26) & 1));
+ printf("Tx3 E =%1u=%1u=/ ? ==%1u=/\n",
+ ((pcie >> 19) & 1), ((sge_rsp_full >> 3) & 1),
+ ((cs >> 27) & 1));
+ printf("\n");
+
+ /* RX path */
+ /* Rx is blocked when sge and/or pcie cannot send requests to system.
+ * */
+ printf(" Rd Wr\n");
+ printf("RX0 P /=%1u=%1u=%1u S <=%1u= C "\
+ "<=%1u= T <=T <=%1u= T /=%1u= M\n",
+ ((pcie_rd_full >> 0) & 1), ((pcie_wr_full >> 0) & 1),
+ ((sge_req_full >> 0) & 1), ((sge_rx_full >> 0) & 1),
+ cng0, ((cs >> 20) & 1), ((es >> 16) & 1));
+ printf("RX1 C| =%1u=%1u=%1u G <=%1u= X "\
+ "<=%1u= C <=P <=%1u= E| =%1u= P\n",
+ ((pcie_rd_full >> 1) & 1), ((pcie_wr_full >> 1) & 1),
+ ((sge_req_full >> 1) & 1), ((sge_rx_full >> 1) & 1),
+ cng1, ((cs >> 21) & 1), ((es >> 17) & 1));
+ printf("RX2 I| =%1u=%1u=%1u E "\
+ " | =%1u= S\n",
+ ((pcie_rd_full >> 2) & 1), ((pcie_wr_full >> 2) & 1),
+ ((sge_req_full >> 2) & 1), ((es >> 18) & 1));
+ printf("RX3 E \\=%1u=%1u=%1u "\
+ " \\=%1u=\n",
+ ((pcie_rd_full >> 3) & 1), ((pcie_wr_full >> 3) & 1),
+ ((sge_req_full >> 3) & 1), ((es >> 19) & 1));
+ printf("\n");
+
+ return rc;
+}
+
+int
+view_full(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ int rc = -1;
+
+ if (is_t5(chip))
+ rc = view_full_t5(pbuf, entity_hdr, cudbg_poutbuf);
+ else if (is_t6(chip))
+ rc = view_full_t6(pbuf, entity_hdr, cudbg_poutbuf);
+
+ return rc;
+}
+
+int
+view_vpd_data(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ struct struct_vpd_data *vpd_data;
+ int rc = 0;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ vpd_data = (struct struct_vpd_data *) dc_buff.data;
+ printf("MN %s\n", vpd_data->mn);
+ printf("SN %s\n", vpd_data->sn);
+ printf("BN %s\n", vpd_data->bn);
+ printf("NA %s\n", vpd_data->na);
+ printf("SCFG Version 0x%x\n",
+ vpd_data->scfg_vers);
+ printf("VPD Version 0x%x\n",
+ vpd_data->vpd_vers);
+
+ printf("Firmware Version: %d.%d.%d.%d\n",
+ vpd_data->fw_major, vpd_data->fw_minor, vpd_data->fw_micro,
+ vpd_data->fw_build);
+
+ return rc;
+}
+
+int
+view_upload(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_buffer c_buff, dc_buff;
+ int rc = 0;
+ u32 *value;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ value = (u32 *) dc_buff.data;
+ if (*value == 0xffffffff) {
+ printf("uP load: <not available>\n");
+ goto err1;
+ }
+
+ printf("uP load: %d, %d, %d\n",
+ (*value >> 0) & 0xff,
+ (*value >> 8) & 0xff,
+ (*value >> 16) & 0xff);
+
+err1:
+ return rc;
+}
+
+static const char *
+cudbg_qdesc_qtype_to_str(enum cudbg_qdesc_qtype qtype)
+{
+ switch (qtype) {
+ case CUDBG_QTYPE_NIC_TXQ:
+ return "ETHERNET-TXQ";
+ case CUDBG_QTYPE_NIC_RXQ:
+ return "ETHERNET-RXQ";
+ case CUDBG_QTYPE_NIC_FLQ:
+ return "ETHERNET-FL";
+ case CUDBG_QTYPE_CTRLQ:
+ return "ETHERNET-CTRLQ";
+ case CUDBG_QTYPE_FWEVTQ:
+ return "FIRMWARE-EVENT-QUEUE";
+ case CUDBG_QTYPE_INTRQ:
+ return "NON-DATA-INTERRUPT-QUEUE";
+ case CUDBG_QTYPE_PTP_TXQ:
+ return "PTP-TXQ";
+ case CUDBG_QTYPE_OFLD_TXQ:
+ return "OFFLOAD-TXQ";
+ case CUDBG_QTYPE_RDMA_RXQ:
+ return "RDMA-RXQ";
+ case CUDBG_QTYPE_RDMA_FLQ:
+ return "RDMA-FL";
+ case CUDBG_QTYPE_RDMA_CIQ:
+ return "RDMA-CIQ";
+ case CUDBG_QTYPE_ISCSI_RXQ:
+ return "iSCSI-RXQ";
+ case CUDBG_QTYPE_ISCSI_FLQ:
+ return "iSCSI-FL";
+ case CUDBG_QTYPE_ISCSIT_RXQ:
+ return "iSCSIT-RXQ";
+ case CUDBG_QTYPE_ISCSIT_FLQ:
+ return "iSCSIT-FL";
+ case CUDBG_QTYPE_CRYPTO_TXQ:
+ return "CRYPTO-TXQ";
+ case CUDBG_QTYPE_CRYPTO_RXQ:
+ return "CRYPTO-RXQ";
+ case CUDBG_QTYPE_CRYPTO_FLQ:
+ return "CRYPTO-FL";
+ case CUDBG_QTYPE_TLS_RXQ:
+ return "TLS-RXQ";
+ case CUDBG_QTYPE_TLS_FLQ:
+ return "TLS-FL";
+ case CUDBG_QTYPE_UNKNOWN:
+ case CUDBG_QTYPE_MAX:
+ return "UNKNOWN";
+ }
+
+ return "UNKNOWN";
+}
+
+static struct cudbg_qdesc_entry *
+cudbg_next_qdesc(struct cudbg_qdesc_entry *e)
+{
+ return (struct cudbg_qdesc_entry *)
+ ((u8 *)e + sizeof(*e) + e->data_size);
+}
+
+int
+view_qdesc(char *pbuf, struct cudbg_entity_hdr *entity_hdr,
+ struct cudbg_buffer *cudbg_poutbuf, enum chip_type chip)
+{
+ struct cudbg_qdesc_entry *qdesc_entry;
+ struct cudbg_qdesc_info *qdesc_info;
+ struct cudbg_buffer c_buff, dc_buff;
+ u8 zero_memory_128[128] = { 0 };
+ struct cudbg_ver_hdr *ver_hdr;
+ u32 i, j, k, l, max_desc;
+ u32 star_count = 0;
+ int rc = 0;
+ u8 *p;
+
+ rc = cudbg_view_decompress_buff(pbuf, entity_hdr, &c_buff, &dc_buff);
+ if (rc)
+ return rc;
+
+ ver_hdr = (struct cudbg_ver_hdr *)dc_buff.data;
+ qdesc_info = (struct cudbg_qdesc_info *)
+ (dc_buff.data + sizeof(*ver_hdr));
+
+ if (!qdesc_info->num_queues) {
+ printf("No queues found\n");
+ goto err1;
+ }
+
+ qdesc_entry = (struct cudbg_qdesc_entry *)
+ ((u8 *)qdesc_info + ver_hdr->size);
+
+ for (i = 0; i < qdesc_info->num_queues; i++) {
+ star_count = 0;
+ printf(
+ "\n\nQueue - %s, context-id: %u, desc-size: %u, desc-num: %u\n",
+ cudbg_qdesc_qtype_to_str(qdesc_entry->qtype),
+ qdesc_entry->qid,
+ qdesc_entry->desc_size,
+ qdesc_entry->num_desc);
+ p = (u8 *)qdesc_entry + qdesc_info->qdesc_entry_size;
+
+ for (j = 0; j < qdesc_entry->num_desc; j++) {
+ k = 0;
+ /* Below logic skips printing descriptors filled with
+ * all zeros and replaces it with star
+ */
+ if (!memcmp(p, zero_memory_128, qdesc_entry->desc_size)) {
+ star_count++;
+ if (star_count >= 2 &&
+ j != (qdesc_entry->num_desc - 1)) {
+ /* Skip all consecutive descriptors
+ * filled with zeros until the last
+ * descriptor.
+ */
+ p += qdesc_entry->desc_size;
+
+ if (star_count == 2) {
+ /* Print * for the second
+ * consecutive descriptor
+ * filled with zeros.
+ */
+ printf("\n%-8s\n", "*");
+ }
+ continue;
+ }
+ } else {
+ /* Descriptor doesn't contain all zeros, so
+ * restart skip logic.
+ */
+ star_count = 0;
+ }
+
+ printf("\n%-8d:", j);
+ while (k < qdesc_entry->desc_size) {
+ max_desc = min(qdesc_entry->desc_size - k,
+ sizeof(u32));
+ if (k && !(k % 32))
+ printf("\n%-9s", " ");
+ if (!(k % 4))
+ printf(" ");
+ for (l = 0; l < max_desc; l++, k++, p++)
+ printf("%02x", *p);
+ }
+ }
+ qdesc_entry = cudbg_next_qdesc(qdesc_entry);
+ }
+
+err1:
+ return rc;
+}
diff --git a/usr/src/cmd/cxgbetool/cudbg_view.h b/usr/src/cmd/cxgbetool/cudbg_view.h
new file mode 100644
index 0000000000..f710cf16f3
--- /dev/null
+++ b/usr/src/cmd/cxgbetool/cudbg_view.h
@@ -0,0 +1,179 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright (c) 2019 by Chelsio Communications, Inc.
+ */
+
+#ifndef __CUDBG_VIEW_H__
+#define __CUDBG_VIEW_H__
+
+#include "t4_hw.h"
+#include "cudbg_lib_common.h"
+
+#if defined(WIN32) || defined(__NT__) || defined(_WIN32) || defined(__WIN32__)
+typedef boolean_t bool;
+#endif
+
+#define DECLARE_VIEW_FUNC(FOO) \
+ int view_##FOO(char *, struct cudbg_entity_hdr *, \
+ struct cudbg_buffer *, enum chip_type);
+DECLARE_VIEW_FUNC(cim_q);
+DECLARE_VIEW_FUNC(cim_la);
+DECLARE_VIEW_FUNC(reg_dump);
+DECLARE_VIEW_FUNC(cim_qcfg);
+DECLARE_VIEW_FUNC(mc0_data);
+DECLARE_VIEW_FUNC(mc1_data);
+DECLARE_VIEW_FUNC(fw_devlog);
+DECLARE_VIEW_FUNC(cim_ma_la);
+DECLARE_VIEW_FUNC(edc0_data);
+DECLARE_VIEW_FUNC(edc1_data);
+DECLARE_VIEW_FUNC(rss);
+DECLARE_VIEW_FUNC(rss_pf_config);
+DECLARE_VIEW_FUNC(rss_key);
+DECLARE_VIEW_FUNC(rss_vf_config);
+DECLARE_VIEW_FUNC(rss_config);
+DECLARE_VIEW_FUNC(path_mtu);
+DECLARE_VIEW_FUNC(sw_state);
+DECLARE_VIEW_FUNC(wtp);
+DECLARE_VIEW_FUNC(pm_stats);
+DECLARE_VIEW_FUNC(tcp_stats);
+DECLARE_VIEW_FUNC(hw_sched);
+DECLARE_VIEW_FUNC(tp_err_stats_show);
+DECLARE_VIEW_FUNC(fcoe_stats);
+DECLARE_VIEW_FUNC(rdma_stats);
+DECLARE_VIEW_FUNC(tp_indirect);
+DECLARE_VIEW_FUNC(sge_indirect);
+DECLARE_VIEW_FUNC(cpl_stats);
+DECLARE_VIEW_FUNC(ddp_stats);
+DECLARE_VIEW_FUNC(wc_stats);
+DECLARE_VIEW_FUNC(ulprx_la);
+DECLARE_VIEW_FUNC(lb_stats);
+DECLARE_VIEW_FUNC(tp_la);
+DECLARE_VIEW_FUNC(meminfo);
+DECLARE_VIEW_FUNC(cim_pif_la);
+DECLARE_VIEW_FUNC(clk_info);
+DECLARE_VIEW_FUNC(macstats);
+DECLARE_VIEW_FUNC(pcie_indirect);
+DECLARE_VIEW_FUNC(pm_indirect);
+DECLARE_VIEW_FUNC(full);
+DECLARE_VIEW_FUNC(tx_rate);
+DECLARE_VIEW_FUNC(tid);
+DECLARE_VIEW_FUNC(pcie_config);
+DECLARE_VIEW_FUNC(dump_context);
+DECLARE_VIEW_FUNC(mps_tcam);
+DECLARE_VIEW_FUNC(vpd_data);
+DECLARE_VIEW_FUNC(le_tcam);
+DECLARE_VIEW_FUNC(cctrl);
+DECLARE_VIEW_FUNC(ma_indirect);
+DECLARE_VIEW_FUNC(ulptx_la);
+DECLARE_VIEW_FUNC(ext_entity);
+DECLARE_VIEW_FUNC(up_cim_indirect);
+DECLARE_VIEW_FUNC(pbt_tables);
+DECLARE_VIEW_FUNC(mbox_log);
+DECLARE_VIEW_FUNC(hma_indirect);
+DECLARE_VIEW_FUNC(hma_data);
+DECLARE_VIEW_FUNC(upload);
+DECLARE_VIEW_FUNC(qdesc);
+
+static int (*view_entity[]) (char *, struct cudbg_entity_hdr *,
+ struct cudbg_buffer *, enum chip_type) = {
+ view_reg_dump,
+ view_fw_devlog,
+ view_cim_la,
+ view_cim_ma_la,
+ view_cim_qcfg,
+ view_cim_q,
+ view_cim_q,
+ view_cim_q,
+ view_cim_q,
+ view_cim_q,
+ view_cim_q,
+ view_cim_q,
+ view_cim_q,
+ view_cim_q,
+ view_cim_q,
+ view_cim_q,
+ view_cim_q,
+ view_edc0_data,
+ view_edc1_data,
+ view_mc0_data,
+ view_mc1_data,
+ view_rss, /*22*/
+ view_rss_pf_config, /*23*/
+ view_rss_key, /*24*/
+ view_rss_vf_config,
+ view_rss_config,
+ view_path_mtu,
+ view_sw_state,
+ view_wtp,
+ view_pm_stats,
+ view_hw_sched,
+ view_tcp_stats,
+ view_tp_err_stats_show,
+ view_fcoe_stats,
+ view_rdma_stats,
+ view_tp_indirect,
+ view_sge_indirect,
+ view_cpl_stats,
+ view_ddp_stats,
+ view_wc_stats,
+ view_ulprx_la,
+ view_lb_stats,
+ view_tp_la,
+ view_meminfo,
+ view_cim_pif_la,
+ view_clk_info,
+ view_cim_q,
+ view_cim_q,
+ view_macstats,
+ view_pcie_indirect,
+ view_pm_indirect,
+ view_full,
+ view_tx_rate,
+ view_tid,
+ view_pcie_config,
+ view_dump_context,
+ view_mps_tcam,
+ view_vpd_data,
+ view_le_tcam,
+ view_cctrl,
+ view_ma_indirect,
+ view_ulptx_la,
+ view_ext_entity,
+ view_up_cim_indirect,
+ view_pbt_tables,
+ view_mbox_log,
+ view_hma_indirect,
+ view_hma_data,
+ view_upload,
+ view_qdesc,
+};
+
+struct reg_info {
+ const char *name;
+ uint32_t addr;
+ uint32_t len;
+};
+
+struct mod_regs {
+ const char *name;
+ const struct reg_info *ri;
+ unsigned int offset;
+};
+
+static const char *yesno(int);
+void translate_fw_devlog(void *, u32, u32 *, u32 *);
+#define BIT(n) (1U << n)
+
+void cudbg_view_release_buff(char *pbuf, struct cudbg_buffer *dc_buff);
+void cudbg_print_flash_header(void *pinbuf);
+#endif
diff --git a/usr/src/cmd/cxgbetool/cudbg_view_compat.c b/usr/src/cmd/cxgbetool/cudbg_view_compat.c
new file mode 100644
index 0000000000..fc564b4d8f
--- /dev/null
+++ b/usr/src/cmd/cxgbetool/cudbg_view_compat.c
@@ -0,0 +1,50 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright (c) 2019 by Chelsio Communications, Inc.
+ */
+
+#include "cudbg_view_compat.h"
+#include "cudbg.h"
+
+int
+view_ulptx_la_rev0(void *data, struct cudbg_buffer *cudbg_poutbuf)
+{
+ struct cudbg_ulptx_la_rev0 *ulptx_la_buff;
+ int i, j, rc = 0;
+
+ ulptx_la_buff = (struct cudbg_ulptx_la_rev0 *)data;
+
+ for (i = 0; i < CUDBG_NUM_ULPTX; i++) {
+ printf("==============================\n");
+ printf("DUMPING ULP_TX_LA_%d\n", i);
+ printf("==============================\n");
+
+ printf("[0x%x] %-24s %#x\n",
+ (A_ULP_TX_LA_RDPTR_0 + 0x10 * i),
+ cudbg_ulptx_rdptr[i], ulptx_la_buff->rdptr[i]);
+ printf("[0x%x] %-24s %#x\n",
+ (A_ULP_TX_LA_WRPTR_0 + 0x10 * i),
+ cudbg_ulptx_wrptr[i], ulptx_la_buff->wrptr[i]);
+ printf("[0x%x] %-24s %#-13x\n",
+ (A_ULP_TX_LA_RDDATA_0 + 0x10 * i),
+ cudbg_ulptx_rddata[i], ulptx_la_buff->rddata[i]);
+
+ for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++) {
+ printf("[%#x] %#-16x [%u]\n",
+ j, ulptx_la_buff->rd_data[i][j],
+ ulptx_la_buff->rd_data[i][j]);
+ }
+ }
+
+ return rc;
+}
diff --git a/usr/src/cmd/cxgbetool/cudbg_view_compat.h b/usr/src/cmd/cxgbetool/cudbg_view_compat.h
new file mode 100644
index 0000000000..efddb8987c
--- /dev/null
+++ b/usr/src/cmd/cxgbetool/cudbg_view_compat.h
@@ -0,0 +1,49 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright (c) 2019 by Chelsio Communications, Inc.
+ */
+
+#ifndef __CUDBG_ENTITY_COMPAT_H__
+#define __CUDBG_ENTITY_COMPAT_H__
+
+#include "cudbg_entity.h"
+
+struct cudbg_ulptx_la_rev0 {
+ u32 rdptr[CUDBG_NUM_ULPTX];
+ u32 wrptr[CUDBG_NUM_ULPTX];
+ u32 rddata[CUDBG_NUM_ULPTX];
+ u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
+};
+
+struct struct_meminfo_rev0 {
+ struct struct_mem_desc avail[4];
+ struct struct_mem_desc mem[ARRAY_SIZE(region) + 3];
+ u32 avail_c;
+ u32 mem_c;
+ u32 up_ram_lo;
+ u32 up_ram_hi;
+ u32 up_extmem2_lo;
+ u32 up_extmem2_hi;
+ u32 rx_pages_data[3];
+ u32 tx_pages_data[4];
+ u32 p_structs;
+ struct struct_port_usage port_data[4];
+ u32 port_used[4];
+ u32 port_alloc[4];
+ u32 loopback_used[NCHAN];
+ u32 loopback_alloc[NCHAN];
+};
+
+int view_ulptx_la_rev0(void *, struct cudbg_buffer *);
+
+#endif
diff --git a/usr/src/cmd/cxgbetool/cudbg_view_entity.h b/usr/src/cmd/cxgbetool/cudbg_view_entity.h
new file mode 100644
index 0000000000..5167b83a1f
--- /dev/null
+++ b/usr/src/cmd/cxgbetool/cudbg_view_entity.h
@@ -0,0 +1,8046 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright (c) 2019 by Chelsio Communications, Inc.
+ */
+
+#ifndef __CUDBG_VIEW_ENTITY_H__
+#define __CUDBG_VIEW_ENTITY_H__
+
+#include "cudbg_entity.h"
+
+static const char * const memory[] = { "EDC0:", "EDC1:", "MC:",
+ "MC0:", "MC1:", "HMA:"};
+
+static const char * const lb_stat_name[] = {
+ "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
+ "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
+ "Frames128To255:", "Frames256To511:", "Frames512To1023:",
+ "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
+ "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
+ "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
+ "BG2FramesTrunc:", "BG3FramesTrunc:"
+};
+
+
+static struct field_desc tp_la0[] = {
+ { "RcfOpCodeOut", 60, 4 },
+ { "State", 56, 4 },
+ { "WcfState", 52, 4 },
+ { "RcfOpcSrcOut", 50, 2 },
+ { "CRxError", 49, 1 },
+ { "ERxError", 48, 1 },
+ { "SanityFailed", 47, 1 },
+ { "SpuriousMsg", 46, 1 },
+ { "FlushInputMsg", 45, 1 },
+ { "FlushInputCpl", 44, 1 },
+ { "RssUpBit", 43, 1 },
+ { "RssFilterHit", 42, 1 },
+ { "Tid", 32, 10 },
+ { "InitTcb", 31, 1 },
+ { "LineNumber", 24, 7 },
+ { "Emsg", 23, 1 },
+ { "EdataOut", 22, 1 },
+ { "Cmsg", 21, 1 },
+ { "CdataOut", 20, 1 },
+ { "EreadPdu", 19, 1 },
+ { "CreadPdu", 18, 1 },
+ { "TunnelPkt", 17, 1 },
+ { "RcfPeerFin", 16, 1 },
+ { "RcfReasonOut", 12, 4 },
+ { "TxCchannel", 10, 2 },
+ { "RcfTxChannel", 8, 2 },
+ { "RxEchannel", 6, 2 },
+ { "RcfRxChannel", 5, 1 },
+ { "RcfDataOutSrdy", 4, 1 },
+ { "RxDvld", 3, 1 },
+ { "RxOoDvld", 2, 1 },
+ { "RxCongestion", 1, 1 },
+ { "TxCongestion", 0, 1 },
+ { NULL }
+};
+
+static struct field_desc tp_la1[] = {
+ { "CplCmdIn", 56, 8 },
+ { "CplCmdOut", 48, 8 },
+ { "ESynOut", 47, 1 },
+ { "EAckOut", 46, 1 },
+ { "EFinOut", 45, 1 },
+ { "ERstOut", 44, 1 },
+ { "SynIn", 43, 1 },
+ { "AckIn", 42, 1 },
+ { "FinIn", 41, 1 },
+ { "RstIn", 40, 1 },
+ { "DataIn", 39, 1 },
+ { "DataInVld", 38, 1 },
+ { "PadIn", 37, 1 },
+ { "RxBufEmpty", 36, 1 },
+ { "RxDdp", 35, 1 },
+ { "RxFbCongestion", 34, 1 },
+ { "TxFbCongestion", 33, 1 },
+ { "TxPktSumSrdy", 32, 1 },
+ { "RcfUlpType", 28, 4 },
+ { "Eread", 27, 1 },
+ { "Ebypass", 26, 1 },
+ { "Esave", 25, 1 },
+ { "Static0", 24, 1 },
+ { "Cread", 23, 1 },
+ { "Cbypass", 22, 1 },
+ { "Csave", 21, 1 },
+ { "CPktOut", 20, 1 },
+ { "RxPagePoolFull", 18, 2 },
+ { "RxLpbkPkt", 17, 1 },
+ { "TxLpbkPkt", 16, 1 },
+ { "RxVfValid", 15, 1 },
+ { "SynLearned", 14, 1 },
+ { "SetDelEntry", 13, 1 },
+ { "SetInvEntry", 12, 1 },
+ { "CpcmdDvld", 11, 1 },
+ { "CpcmdSave", 10, 1 },
+ { "RxPstructsFull", 8, 2 },
+ { "EpcmdDvld", 7, 1 },
+ { "EpcmdFlush", 6, 1 },
+ { "EpcmdTrimPrefix", 5, 1 },
+ { "EpcmdTrimPostfix", 4, 1 },
+ { "ERssIp4Pkt", 3, 1 },
+ { "ERssIp6Pkt", 2, 1 },
+ { "ERssTcpUdpPkt", 1, 1 },
+ { "ERssFceFipPkt", 0, 1 },
+ { NULL }
+};
+
+static struct field_desc tp_la2[] = {
+ { "CplCmdIn", 56, 8 },
+ { "MpsVfVld", 55, 1 },
+ { "MpsPf", 52, 3 },
+ { "MpsVf", 44, 8 },
+ { "SynIn", 43, 1 },
+ { "AckIn", 42, 1 },
+ { "FinIn", 41, 1 },
+ { "RstIn", 40, 1 },
+ { "DataIn", 39, 1 },
+ { "DataInVld", 38, 1 },
+ { "PadIn", 37, 1 },
+ { "RxBufEmpty", 36, 1 },
+ { "RxDdp", 35, 1 },
+ { "RxFbCongestion", 34, 1 },
+ { "TxFbCongestion", 33, 1 },
+ { "TxPktSumSrdy", 32, 1 },
+ { "RcfUlpType", 28, 4 },
+ { "Eread", 27, 1 },
+ { "Ebypass", 26, 1 },
+ { "Esave", 25, 1 },
+ { "Static0", 24, 1 },
+ { "Cread", 23, 1 },
+ { "Cbypass", 22, 1 },
+ { "Csave", 21, 1 },
+ { "CPktOut", 20, 1 },
+ { "RxPagePoolFull", 18, 2 },
+ { "RxLpbkPkt", 17, 1 },
+ { "TxLpbkPkt", 16, 1 },
+ { "RxVfValid", 15, 1 },
+ { "SynLearned", 14, 1 },
+ { "SetDelEntry", 13, 1 },
+ { "SetInvEntry", 12, 1 },
+ { "CpcmdDvld", 11, 1 },
+ { "CpcmdSave", 10, 1 },
+ { "RxPstructsFull", 8, 2 },
+ { "EpcmdDvld", 7, 1 },
+ { "EpcmdFlush", 6, 1 },
+ { "EpcmdTrimPrefix", 5, 1 },
+ { "EpcmdTrimPostfix", 4, 1 },
+ { "ERssIp4Pkt", 3, 1 },
+ { "ERssIp6Pkt", 2, 1 },
+ { "ERssTcpUdpPkt", 1, 1 },
+ { "ERssFceFipPkt", 0, 1 },
+ { NULL }
+};
+
+static const char * const devlog_level_strings[] = {
+ /*[FW_DEVLOG_LEVEL_EMERG] =*/ "EMERG",
+ /*[FW_DEVLOG_LEVEL_CRIT] =*/ "CRIT",
+ /*[FW_DEVLOG_LEVEL_ERR] =*/ "ERR",
+ /*[FW_DEVLOG_LEVEL_NOTICE] =*/ "NOTICE",
+ /*[FW_DEVLOG_LEVEL_INFO] =*/ "INFO",
+ /*[FW_DEVLOG_LEVEL_DEBUG] =*/ "DEBUG",
+ /*[FW_DEVLOG_LEVEL_MAX] =*/ "MAX"
+};
+
+static const char * const devlog_facility_strings[] = {
+ /*[FW_DEVLOG_FACILITY_CORE] =*/ "CORE",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_SCHED] =*/ "SCHED",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_TIMER] =*/ "TIMER",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_RES] =*/ "RES",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_HW] =*/ "HW",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_FLR] =*/ "FLR",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_DMAQ] =*/ "DMAQ",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_PHY] =*/ "PHY",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_MAC] =*/ "MAC",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_PORT] =*/ "PORT",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_VI] =*/ "VI",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_FILTER] =*/ "FILTER",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_ACL] =*/ "ACL",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_TM] =*/ "TM",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_QFC] =*/ "QFC",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_DCB] =*/ "DCB",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_ETH] =*/ "ETH",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_OFLD] =*/ "OFLD",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_RI] =*/ "RI",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_ISCSI] =*/ "ISCSI",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_FCOE] =*/ "FCOE",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_FOISCSI] =*/ "FOISCSI",
+ /*[FW_DEVLOG_FACILITY_DUMMY] =*/ "DUMMY",
+ /*[FW_DEVLOG_FACILITY_FOFCOE] =*/ "FOFCOE",
+ /*[FW_DEVLOG_FACILITY_MAX] =*/ "MAX"
+};
+
+static struct tp1_reg_info t6_tp_mib_index_reg_array[] = {
+ {"0x0", "TP_MIB_MAC_IN_ERR_0"},
+ {"0x1", "TP_MIB_MAC_IN_ERR_1"},
+ {"0x2", "TP_MIB_MAC_IN_ERR_2"},
+ {"0x3", "TP_MIB_MAC_IN_ERR_3"},
+ {"0x4", "TP_MIB_HDR_IN_ERR_0"},
+ {"0x5", "TP_MIB_HDR_IN_ERR_1"},
+ {"0x6", "TP_MIB_HDR_IN_ERR_2"},
+ {"0x7", "TP_MIB_HDR_IN_ERR_3"},
+ {"0x8", "TP_MIB_TCP_IN_ERR_0"},
+ {"0x9", "TP_MIB_TCP_IN_ERR_1"},
+ {"0xA", "TP_MIB_TCP_IN_ERR_2"},
+ {"0xB", "TP_MIB_TCP_IN_ERR_3"},
+ {"0xC", "TP_MIB_TCP_OUT_RST"},
+ {"0x10", "TP_MIB_TCP_IN_SEG_HI"},
+ {"0x11", "TP_MIB_TCP_IN_SEG_LO"},
+ {"0x12", "TP_MIB_TCP_OUT_SEG_HI"},
+ {"0x13", "TP_MIB_TCP_OUT_SEG_LO"},
+ {"0x14", "TP_MIB_TCP_RXT_SEG_HI"},
+ {"0x15", "TP_MIB_TCP_RXT_SEG_LO"},
+ {"0x18", "TP_MIB_TNL_CNG_DROP_0"},
+ {"0x19", "TP_MIB_TNL_CNG_DROP_1"},
+ {"0x1A", "TP_MIB_TNL_CNG_DROP_2"},
+ {"0x1B", "TP_MIB_TNL_CNG_DROP_3"},
+ {"0x1C", "TP_MIB_OFD_CHN_DROP_0"},
+ {"0x1D", "TP_MIB_OFD_CHN_DROP_1"},
+ {"0x1E", "TP_MIB_OFD_CHN_DROP_2"},
+ {"0x1F", "TP_MIB_OFD_CHN_DROP_3"},
+ {"0x20", "TP_MIB_TNL_OUT_PKT_0"},
+ {"0x21", "TP_MIB_TNL_OUT_PKT_1"},
+ {"0x22", "TP_MIB_TNL_OUT_PKT_2"},
+ {"0x23", "TP_MIB_TNL_OUT_PKT_3"},
+ {"0x24", "TP_MIB_TNL_IN_PKT_0"},
+ {"0x25", "TP_MIB_TNL_IN_PKT_1"},
+ {"0x26", "TP_MIB_TNL_IN_PKT_2"},
+ {"0x27", "TP_MIB_TNL_IN_PKT_3"},
+ {"0x28", "TP_MIB_TCP_V6IN_ERR_0"},
+ {"0x29", "TP_MIB_TCP_V6IN_ERR_1"},
+ {"0x2A", "TP_MIB_TCP_V6IN_ERR_2"},
+ {"0x2B", "TP_MIB_TCP_V6IN_ERR_3"},
+ {"0x2C", "TP_MIB_TCP_V6OUT_RST"},
+ {"0x30", "TP_MIB_TCP_V6IN_SEG_HI"},
+ {"0x31", "TP_MIB_TCP_V6IN_SEG_LO"},
+ {"0x32", "TP_MIB_TCP_V6OUT_SEG_HI"},
+ {"0x33", "TP_MIB_TCP_V6OUT_SEG_LO"},
+ {"0x34", "TP_MIB_TCP_V6RXT_SEG_HI"},
+ {"0x35", "TP_MIB_TCP_V6RXT_SEG_LO"},
+ {"0x36", "TP_MIB_OFD_ARP_DROP"},
+ {"0x37", "TP_MIB_OFD_DFR_DROP"},
+ {"0x38", "TP_MIB_CPL_IN_REQ_0"},
+ {"0x39", "TP_MIB_CPL_IN_REQ_1"},
+ {"0x3A", "TP_MIB_CPL_IN_REQ_2"},
+ {"0x3B", "TP_MIB_CPL_IN_REQ_3"},
+ {"0x3C", "TP_MIB_CPL_OUT_RSP_0"},
+ {"0x3D", "TP_MIB_CPL_OUT_RSP_1"},
+ {"0x3E", "TP_MIB_CPL_OUT_RSP_2"},
+ {"0x3F", "TP_MIB_CPL_OUT_RSP_3"},
+ {"0x40", "TP_MIB_TNL_LPBK_0"},
+ {"0x41", "TP_MIB_TNL_LPBK_1"},
+ {"0x42", "TP_MIB_TNL_LPBK_2"},
+ {"0x43", "TP_MIB_TNL_LPBK_3"},
+ {"0x44", "TP_MIB_TNL_DROP_0"},
+ {"0x45", "TP_MIB_TNL_DROP_1"},
+ {"0x46", "TP_MIB_TNL_DROP_2"},
+ {"0x47", "TP_MIB_TNL_DROP_3"},
+ {"0x48", "TP_MIB_FCOE_DDP_0"},
+ {"0x49", "TP_MIB_FCOE_DDP_1"},
+ {"0x4A", "TP_MIB_FCOE_DDP_2"},
+ {"0x4B", "TP_MIB_FCOE_DDP_3"},
+ {"0x4C", "TP_MIB_FCOE_DROP_0"},
+ {"0x4D", "TP_MIB_FCOE_DROP_1"},
+ {"0x4E", "TP_MIB_FCOE_DROP_2"},
+ {"0x4F", "TP_MIB_FCOE_DROP_3"},
+ {"0x50", "TP_MIB_FCOE_BYTE_0_HI"},
+ {"0x51", "TP_MIB_FCOE_BYTE_0_LO"},
+ {"0x52", "TP_MIB_FCOE_BYTE_1_HI"},
+ {"0x53", "TP_MIB_FCOE_BYTE_1_LO"},
+ {"0x54", "TP_MIB_FCOE_BYTE_2_HI"},
+ {"0x55", "TP_MIB_FCOE_BYTE_2_LO"},
+ {"0x56", "TP_MIB_FCOE_BYTE_3_HI"},
+ {"0x57", "TP_MIB_FCOE_BYTE_3_LO"},
+ {"0x58", "TP_MIB_OFD_VLN_DROP_0"},
+ {"0x59", "TP_MIB_OFD_VLN_DROP_1"},
+ {"0x5A", "TP_MIB_OFD_VLN_DROP_2"},
+ {"0x5B", "TP_MIB_OFD_VLN_DROP_3"},
+ {"0x5C", "TP_MIB_USM_PKTS"},
+ {"0x5D", "TP_MIB_USM_DROP"},
+ {"0x5E", "TP_MIB_USM_BYTES_HI"},
+ {"0x5F", "TP_MIB_USM_BYTES_LO"},
+ {"0x60", "TP_MIB_TID_DEL"},
+ {"0x61", "TP_MIB_TID_INV"},
+ {"0x62", "TP_MIB_TID_ACT"},
+ {"0x63", "TP_MIB_TID_PAS"},
+ {"0x64", "TP_MIB_RQE_DFR_PKT"},
+ {"0x65", "TP_MIB_RQE_DFR_MOD"},
+ {"0x68", "TP_MIB_CPL_OUT_ERR_0"},
+ {"0x69", "TP_MIB_CPL_OUT_ERR_1"},
+ {"0x6A", "TP_MIB_CPL_OUT_ERR_2"},
+ {"0x6B", "TP_MIB_CPL_OUT_ERR_3"},
+ {"0x6c", "TP_MIB_ENG_LINE_0"},
+ {"0x6d", "TP_MIB_ENG_LINE_1"},
+ {"0x6e", "TP_MIB_ENG_LINE_2"},
+ {"0x6f", "TP_MIB_ENG_LINE_3"},
+ {"0x70", "TP_MIB_TNL_ERR_0"},
+ {"0x71", "TP_MIB_TNL_ERR_1"},
+ {"0x72", "TP_MIB_TNL_ERR_2"},
+ {"0x73", "TP_MIB_TNL_ERR_3"}
+};
+
+static struct tp1_reg_info t5_tp_mib_index_reg_array[] = {
+ {"0x0", "TP_MIB_MAC_IN_ERR_0"},
+ {"0x1", "TP_MIB_MAC_IN_ERR_1"},
+ {"0x2", "TP_MIB_MAC_IN_ERR_2"},
+ {"0x3", "TP_MIB_MAC_IN_ERR_3"},
+ {"0x4", "TP_MIB_HDR_IN_ERR_0"},
+ {"0x5", "TP_MIB_HDR_IN_ERR_1"},
+ {"0x6", "TP_MIB_HDR_IN_ERR_2"},
+ {"0x7", "TP_MIB_HDR_IN_ERR_3"},
+ {"0x8", "TP_MIB_TCP_IN_ERR_0"},
+ {"0x9", "TP_MIB_TCP_IN_ERR_1"},
+ {"0xA", "TP_MIB_TCP_IN_ERR_2"},
+ {"0xB", "TP_MIB_TCP_IN_ERR_3"},
+ {"0xC", "TP_MIB_TCP_OUT_RST"},
+ {"0x10", "TP_MIB_TCP_IN_SEG_HI"},
+ {"0x11", "TP_MIB_TCP_IN_SEG_LO"},
+ {"0x12", "TP_MIB_TCP_OUT_SEG_HI"},
+ {"0x13", "TP_MIB_TCP_OUT_SEG_LO"},
+ {"0x14", "TP_MIB_TCP_RXT_SEG_HI"},
+ {"0x15", "TP_MIB_TCP_RXT_SEG_LO"},
+ {"0x18", "TP_MIB_TNL_CNG_DROP_0"},
+ {"0x19", "TP_MIB_TNL_CNG_DROP_1"},
+ {"0x1A", "TP_MIB_TNL_CNG_DROP_2"},
+ {"0x1B", "TP_MIB_TNL_CNG_DROP_3"},
+ {"0x1C", "TP_MIB_OFD_CHN_DROP_0"},
+ {"0x1D", "TP_MIB_OFD_CHN_DROP_1"},
+ {"0x1E", "TP_MIB_OFD_CHN_DROP_2"},
+ {"0x1F", "TP_MIB_OFD_CHN_DROP_3"},
+ {"0x20", "TP_MIB_TNL_OUT_PKT_0"},
+ {"0x21", "TP_MIB_TNL_OUT_PKT_1"},
+ {"0x22", "TP_MIB_TNL_OUT_PKT_2"},
+ {"0x23", "TP_MIB_TNL_OUT_PKT_3"},
+ {"0x24", "TP_MIB_TNL_IN_PKT_0"},
+ {"0x25", "TP_MIB_TNL_IN_PKT_1"},
+ {"0x26", "TP_MIB_TNL_IN_PKT_2"},
+ {"0x27", "TP_MIB_TNL_IN_PKT_3"},
+ {"0x28", "TP_MIB_TCP_V6IN_ERR_0"},
+ {"0x29", "TP_MIB_TCP_V6IN_ERR_1"},
+ {"0x2A", "TP_MIB_TCP_V6IN_ERR_2"},
+ {"0x2B", "TP_MIB_TCP_V6IN_ERR_3"},
+ {"0x2C", "TP_MIB_TCP_V6OUT_RST"},
+ {"0x30", "TP_MIB_TCP_V6IN_SEG_HI"},
+ {"0x31", "TP_MIB_TCP_V6IN_SEG_LO"},
+ {"0x32", "TP_MIB_TCP_V6OUT_SEG_HI"},
+ {"0x33", "TP_MIB_TCP_V6OUT_SEG_LO"},
+ {"0x34", "TP_MIB_TCP_V6RXT_SEG_HI"},
+ {"0x35", "TP_MIB_TCP_V6RXT_SEG_LO"},
+ {"0x36", "TP_MIB_OFD_ARP_DROP"},
+ {"0x37", "TP_MIB_OFD_DFR_DROP"},
+ {"0x38", "TP_MIB_CPL_IN_REQ_0"},
+ {"0x39", "TP_MIB_CPL_IN_REQ_1"},
+ {"0x3A", "TP_MIB_CPL_IN_REQ_2"},
+ {"0x3B", "TP_MIB_CPL_IN_REQ_3"},
+ {"0x3C", "TP_MIB_CPL_OUT_RSP_0"},
+ {"0x3D", "TP_MIB_CPL_OUT_RSP_1"},
+ {"0x3E", "TP_MIB_CPL_OUT_RSP_2"},
+ {"0x3F", "TP_MIB_CPL_OUT_RSP_3"},
+ {"0x40", "TP_MIB_TNL_LPBK_0"},
+ {"0x41", "TP_MIB_TNL_LPBK_1"},
+ {"0x42", "TP_MIB_TNL_LPBK_2"},
+ {"0x43", "TP_MIB_TNL_LPBK_3"},
+ {"0x44", "TP_MIB_TNL_DROP_0"},
+ {"0x45", "TP_MIB_TNL_DROP_1"},
+ {"0x46", "TP_MIB_TNL_DROP_2"},
+ {"0x47", "TP_MIB_TNL_DROP_3"},
+ {"0x48", "TP_MIB_FCOE_DDP_0"},
+ {"0x49", "TP_MIB_FCOE_DDP_1"},
+ {"0x4A", "TP_MIB_FCOE_DDP_2"},
+ {"0x4B", "TP_MIB_FCOE_DDP_3"},
+ {"0x4C", "TP_MIB_FCOE_DROP_0"},
+ {"0x4D", "TP_MIB_FCOE_DROP_1"},
+ {"0x4E", "TP_MIB_FCOE_DROP_2"},
+ {"0x4F", "TP_MIB_FCOE_DROP_3"},
+ {"0x50", "TP_MIB_FCOE_BYTE_0_HI"},
+ {"0x51", "TP_MIB_FCOE_BYTE_0_LO"},
+ {"0x52", "TP_MIB_FCOE_BYTE_1_HI"},
+ {"0x53", "TP_MIB_FCOE_BYTE_1_LO"},
+ {"0x54", "TP_MIB_FCOE_BYTE_2_HI"},
+ {"0x55", "TP_MIB_FCOE_BYTE_2_LO"},
+ {"0x56", "TP_MIB_FCOE_BYTE_3_HI"},
+ {"0x57", "TP_MIB_FCOE_BYTE_3_LO"},
+ {"0x58", "TP_MIB_OFD_VLN_DROP_0"},
+ {"0x59", "TP_MIB_OFD_VLN_DROP_1"},
+ {"0x5A", "TP_MIB_OFD_VLN_DROP_2"},
+ {"0x5B", "TP_MIB_OFD_VLN_DROP_3"},
+ {"0x5C", "TP_MIB_USM_PKTS"},
+ {"0x5D", "TP_MIB_USM_DROP"},
+ {"0x5E", "TP_MIB_USM_BYTES_HI"},
+ {"0x5F", "TP_MIB_USM_BYTES_LO"},
+ {"0x60", "TP_MIB_TID_DEL"},
+ {"0x61", "TP_MIB_TID_INV"},
+ {"0x62", "TP_MIB_TID_ACT"},
+ {"0x63", "TP_MIB_TID_PAS"},
+ {"0x64", "TP_MIB_RQE_DFR_PKT"},
+ {"0x65", "TP_MIB_RQE_DFR_MOD"},
+ {"0x68", "TP_MIB_CPL_OUT_ERR_0"},
+ {"0x69", "TP_MIB_CPL_OUT_ERR_1"},
+ {"0x6A", "TP_MIB_CPL_OUT_ERR_2"},
+ {"0x6B", "TP_MIB_CPL_OUT_ERR_3"}
+};
+
+static struct cudbg_reg_info t6_tp_tm_regs[] = {
+ { "TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR", 0x0, 0 },
+ { "S_TXTIMERSEPQ7", 16, 16 },
+ { "S_TXTIMERSEPQ6", 0, 16 },
+ { "TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR", 0x1, 0 },
+ { "S_TXTIMERSEPQ4", 16, 16 },
+ { "S_TXTIMERSEPQ4", 0, 16 },
+ { "TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR", 0x2, 0 },
+ { "S_TXTIMERSEPQ3", 16, 16 },
+ { "S_TXTIMERSEPQ2", 0, 16 },
+ { "TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x3, 0 },
+ { "S_TXTIMERSEPQ1", 16, 16 },
+ { "S_TXTIMERSEPQ0", 0, 16 },
+ { "TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x4, 0 },
+ { "S_RXTIMERSEPQ1", 16, 16 },
+ { "S_RXTIMERSEPQ0", 0, 16 },
+ { "TP_TX_MOD_Q7_Q6_RATE_LIMIT", 0x5, 0 },
+ { "S_TXRATEINCQ7", 24, 8 },
+ { "S_TXRATETCKQ7", 16, 8 },
+ { "S_TXRATEINCQ6", 8, 8 },
+ { "S_TXRATETCKQ6", 0, 8 },
+ { "TP_TX_MOD_Q5_Q4_RATE_LIMIT", 0x6, 0 },
+ { "S_TXRATEINCQ5", 24, 8 },
+ { "S_TXRATETCKQ5", 16, 8 },
+ { "S_TXRATEINCQ4", 8, 8 },
+ { "S_TXRATETCKQ4", 0, 8 },
+ { "TP_TX_MOD_Q3_Q2_RATE_LIMIT", 0x7, 0 },
+ { "S_TXRATEINCQ3", 24, 8 },
+ { "S_TXRATETCKQ3", 16, 8 },
+ { "S_TXRATEINCQ2", 8, 8 },
+ { "S_TXRATETCKQ2", 0, 8 },
+ { "TP_TX_MOD_Q1_Q0_RATE_LIMIT", 0x8, 0 },
+ { "S_TXRATEINCQ1", 24, 8 },
+ { "S_TXRATETCKQ1", 16, 8 },
+ { "S_TXRATEINCQ0", 8, 8 },
+ { "S_TXRATETCKQ0", 0, 8 },
+ { "TP_RX_MOD_Q1_Q0_RATE_LIMIT", 0x9, 0 },
+ { "S_RXRATEINCQ1", 24, 8 },
+ { "S_RXRATETCKQ1", 16, 8 },
+ { "S_RXRATEINCQ0", 8, 8 },
+ { "S_RXRATETCKQ0", 0, 8 },
+ { "TP_TX_MOD_C3_C2_RATE_LIMIT", 0xA, 0 },
+ { "TP_TX_MOD_C1_C0_RATE_LIMIT", 0xB, 0 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_tm_regs[] = {
+ { "TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR", 0x0, 0 },
+ { "S_TXTIMERSEPQ7", 16, 16 },
+ { "S_TXTIMERSEPQ6", 0, 16 },
+ { "TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR", 0x1, 0 },
+ { "S_TXTIMERSEPQ4", 16, 16 },
+ { "S_TXTIMERSEPQ4", 0, 16 },
+ { "TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR", 0x2, 0 },
+ { "S_TXTIMERSEPQ3", 16, 16 },
+ { "S_TXTIMERSEPQ2", 0, 16 },
+ { "TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x3, 0 },
+ { "S_TXTIMERSEPQ1", 16, 16 },
+ { "S_TXTIMERSEPQ0", 0, 16 },
+ { "TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x4, 0 },
+ { "S_RXTIMERSEPQ1", 16, 16 },
+ { "S_RXTIMERSEPQ0", 0, 16 },
+ { "TP_TX_MOD_Q7_Q6_RATE_LIMIT", 0x5, 0 },
+ { "S_TXRATEINCQ7", 24, 8 },
+ { "S_TXRATETCKQ7", 16, 8 },
+ { "S_TXRATEINCQ6", 8, 8 },
+ { "S_TXRATETCKQ6", 0, 8 },
+ { "TP_TX_MOD_Q5_Q4_RATE_LIMIT", 0x6, 0 },
+ { "S_TXRATEINCQ5", 24, 8 },
+ { "S_TXRATETCKQ5", 16, 8 },
+ { "S_TXRATEINCQ4", 8, 8 },
+ { "S_TXRATETCKQ4", 0, 8 },
+ { "TP_TX_MOD_Q3_Q2_RATE_LIMIT", 0x7, 0 },
+ { "S_TXRATEINCQ3", 24, 8 },
+ { "S_TXRATETCKQ3", 16, 8 },
+ { "S_TXRATEINCQ2", 8, 8 },
+ { "S_TXRATETCKQ2", 0, 8 },
+ { "TP_TX_MOD_Q1_Q0_RATE_LIMIT", 0x8, 0 },
+ { "S_TXRATEINCQ1", 24, 8 },
+ { "S_TXRATETCKQ1", 16, 8 },
+ { "S_TXRATEINCQ0", 8, 8 },
+ { "S_TXRATETCKQ0", 0, 8 },
+ { "TP_RX_MOD_Q1_Q0_RATE_LIMIT", 0x9, 0 },
+ { "S_RXRATEINCQ1", 24, 8 },
+ { "S_RXRATETCKQ1", 16, 8 },
+ { "S_RXRATEINCQ0", 8, 8 },
+ { "S_RXRATETCKQ0", 0, 8 },
+ { "TP_TX_MOD_C3_C2_RATE_LIMIT", 0xA, 0 },
+ { "TP_TX_MOD_C1_C0_RATE_LIMIT", 0xB, 0 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_20_to_3b[] = {
+ { "TP_RX_SCHED_MAP", 0x20, 0 },
+ { "S_RXMAPCHANNEL3", 24, 8 },
+ { "S_RXMAPCHANNEL2", 16, 8 },
+ { "S_RXMAPCHANNEL1", 8, 8 },
+ { "S_RXMAPCHANNEL0", 0, 8 },
+ { "TP_RX_SCHED_SGE", 0x21, 0 },
+ { "S_RXSGEMOD1", 12, 4 },
+ { "S_RXSGEMOD0", 8, 4 },
+ { "S_RXSGECHANNEL3", 3, 1 },
+ { "S_RXSGECHANNEL2", 2, 1 },
+ { "S_RXSGECHANNEL1", 1, 1 },
+ { "S_RXSGECHANNEL0", 0, 1 },
+ { "TP_TX_SCHED_MAP", 0x22, 0 },
+ { "S_TXMAPCHANNEL3", 12, 4 },
+ { "S_TXMAPCHANNEL2", 8, 4 },
+ { "S_TXMAPCHANNEL1", 4, 4 },
+ { "S_TXMAPCHANNEL0", 0, 4 },
+ { "TP_TX_SCHED_HDR", 0x23, 0 },
+ { "S_TXMAPHDRCHANNEL7", 28, 4 },
+ { "S_TXMAPHDRCHANNEL6", 24, 4 },
+ { "S_TXMAPHDRCHANNEL5", 20, 4 },
+ { "S_TXMAPHDRCHANNEL4", 16, 4 },
+ { "S_TXMAPHDRCHANNEL3", 12, 4 },
+ { "S_TXMAPHDRCHANNEL2", 8, 4 },
+ { "S_TXMAPHDRCHANNEL1", 4, 4 },
+ { "S_TXMAPHDRCHANNEL0", 0, 4 },
+ { "TP_TX_SCHED_FIFO", 0x24, 0 },
+ { "S_TXMAPFIFOCHANNEL7", 28, 4 },
+ { "S_TXMAPFIFOCHANNEL6", 24, 4 },
+ { "S_TXMAPFIFOCHANNEL5", 20, 4 },
+ { "S_TXMAPFIFOCHANNEL4", 16, 4 },
+ { "S_TXMAPFIFOCHANNEL3", 12, 4 },
+ { "S_TXMAPFIFOCHANNEL2", 8, 4 },
+ { "S_TXMAPFIFOCHANNEL1", 4, 4 },
+ { "S_TXMAPFIFOCHANNEL0", 0, 4 },
+ { "TP_TX_SCHED_PCMD", 0x25, 0 },
+ { "S_TXMAPPCMDCHANNEL7", 28, 4 },
+ { "S_TXMAPPCMDCHANNEL6", 24, 4 },
+ { "S_TXMAPPCMDCHANNEL5", 20, 4 },
+ { "S_TXMAPPCMDCHANNEL4", 16, 4 },
+ { "S_TXMAPPCMDCHANNEL3", 12, 4 },
+ { "S_TXMAPPCMDCHANNEL2", 8, 4 },
+ { "S_TXMAPPCMDCHANNEL1", 4, 4 },
+ { "S_TXMAPPCMDCHANNEL0", 0, 4 },
+ { "TP_TX_SCHED_LPBK", 0x26, 0 },
+ { "S_TXMAPLPBKCHANNEL7", 28, 4 },
+ { "S_TXMAPLPBKCHANNEL6", 24, 4 },
+ { "S_TXMAPLPBKCHANNEL5", 20, 4 },
+ { "S_TXMAPLPBKCHANNEL4", 16, 4 },
+ { "S_TXMAPLPBKCHANNEL3", 12, 4 },
+ { "S_TXMAPLPBKCHANNEL2", 8, 4 },
+ { "S_TXMAPLPBKCHANNEL1", 4, 4 },
+ { "S_TXMAPLPBKCHANNEL0", 0, 4 },
+ { "TP_CHANNEL_MAP", 0x27, 0 },
+ { "RxMapChannelELN", 16, 4 },
+ { "RxMapE2LChannel3", 14, 2 },
+ { "RxMapE2LChannel2", 12, 2 },
+ { "RxMapE2LChannel1", 10, 2 },
+ { "RxMapE2LChannel0", 8, 2 },
+ { "RxMapC2CChannel3", 7, 1 },
+ { "RxMapC2CChannel2", 6, 1 },
+ { "RxMapC2CChannel1", 5, 1 },
+ { "RxMapC2CChannel0", 4, 1 },
+ { "RxMapE2CChannel3", 3, 1 },
+ { "RxMapE2CChannel2", 2, 1 },
+ { "RxMapE2CChannel1", 1, 1 },
+ { "RxMapE2CChannel0", 0, 1 },
+ { "TP_RX_LPBK", 0x28, 0 },
+ { "CommitReset3", 31, 1 },
+ { "CommitReset2", 30, 1 },
+ { "CommitReset1", 29, 1 },
+ { "CommitReset0", 28, 1 },
+ { "ForceCong3", 27, 1 },
+ { "ForceCong2", 26, 1 },
+ { "ForceCong1", 25, 1 },
+ { "ForceCong0", 24, 1 },
+ { "CommitLimit3", 18, 6 },
+ { "CommitLimit2", 12, 6},
+ { "CommitLimit1", 6, 6 },
+ { "CommitLimit0", 0, 6 },
+ { "TP_TX_LPBK", 0x29, 0 },
+ { "CommitReset3", 31, 1 },
+ { "CommitReset2", 30, 1 },
+ { "CommitReset1", 29, 1 },
+ { "CommitReset0", 28, 1 },
+ { "ForceCong3", 27, 1 },
+ { "ForceCong2", 26, 1 },
+ { "ForceCong1", 25, 1 },
+ { "ForceCong0", 24, 1 },
+ { "CommitLimit3", 18, 6 },
+ { "CommitLimit2", 12, 6},
+ { "CommitLimit1", 6, 6 },
+ { "CommitLimit0", 0, 6 },
+
+ { "TP_TX_SCHED_PPP", 0x2A, 0 },
+ { "S_TXPPPENPORT3", 24, 8 },
+ { "S_TXPPPENPORT2", 16, 8 },
+ { "S_TXPPPENPORT1", 8, 8 },
+ { "S_TXPPPENPORT0", 0, 8 },
+ { "TP_RX_SCHED_FIFO", 0x2B, 0 },
+ { "S_COMMITLIMIT1H", 24, 8 },
+ { "S_COMMITLIMIT1L", 16, 8 },
+ { "S_COMMITLIMIT0H", 8, 8 },
+ { "S_COMMITLIMIT0L", 0, 8 },
+ { "TP_IPMI_CFG1", 0x2E, 0 },
+ { "S_VLANENABLE", 31, 1 },
+ { "S_PRIMARYPORTENABLE", 30, 1 },
+ { "S_SECUREPORTENABLE", 29, 1 },
+ { "S_ARPENABLE", 28, 1 },
+ { "S_IPMI_VLAN", 0, 16 },
+ { "TP_IPMI_CFG2", 0x2F, 0 },
+ { "S_SECUREPORT", 16, 16 },
+ { "S_PRIMARYPORT", 0, 16 },
+ { "TP_RSS_PF0_CONFIG", 0x30, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_CHNENABLE", 30, 1 },
+ { "S_PRTENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF1_CONFIG", 0x31, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_CHNENABLE", 30, 1 },
+ { "S_PRTENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF2_CONFIG", 0x32, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_CHNENABLE", 30, 1 },
+ { "S_PRTENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF3_CONFIG", 0x33, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_CHNENABLE", 30, 1 },
+ { "S_PRTENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF4_CONFIG", 0x34, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_CHNENABLE", 30, 1 },
+ { "S_PRTENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF5_CONFIG", 0x35, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_CHNENABLE", 30, 1 },
+ { "S_PRTENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF6_CONFIG", 0x36, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_CHNENABLE", 30, 1 },
+ { "S_PRTENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF7_CONFIG", 0x37, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_CHNENABLE", 30, 1 },
+ { "S_PRTENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF_MAP", 0x38, 0 },
+ { "S_LKPIDXSIZE", 24, 2 },
+ { "S_PF7LKPIDX", 21, 3 },
+ { "S_PF6LKPIDX", 18, 3 },
+ { "S_PF5LKPIDX", 15, 3 },
+ { "S_PF4LKPIDX", 12, 3 },
+ { "S_PF3LKPIDX", 9, 3 },
+ { "S_PF2LKPIDX", 6, 3 },
+ { "S_PF1LKPIDX", 3, 3 },
+ { "S_PF0LKPIDX", 0, 3 },
+ { "TP_RSS_PF_MSK", 0x39, 0 },
+ { "S_PF7MSKSIZE", 28, 4 },
+ { "S_PF6MSKSIZE", 24, 4 },
+ { "S_PF5MSKSIZE", 20, 4 },
+ { "S_PF4MSKSIZE", 16, 4 },
+ { "S_PF3MSKSIZE", 12, 4 },
+ { "S_PF2MSKSIZE", 8, 4 },
+ { "S_PF1MSKSIZE", 4, 4 },
+ { "S_PF0MSKSIZE", 0, 4 },
+ { "TP_RSS_VFL_CONFIG", 0x3A, 0 },
+ { "S_KEYSCRAMBLE", 0, 32 },
+ { "TP_RSS_VFH_CONFIG", 0x3B, 0 },
+ { "S_ENABLEUDPHASH", 31, 1 },
+ { "S_VFUPEN", 30, 1 },
+ { "S_RESERVED", 29, 1 },
+ { "S_VFVLNEX", 28, 1 },
+ { "S_VFPRTEN", 27, 1 },
+ { "S_VFCHNEN", 26, 1 },
+ { "S_DEFAULTQUEUE", 16, 10 },
+ { "S_VFLKPIDX", 8, 8 },
+ { "S_VFIP6FOURTUPEN", 7, 1 },
+ { "S_VFIP6TWOTUPEN", 6, 1 },
+ { "S_VFIP4FOURTUPEN", 5, 1 },
+ { "S_VFIP4TWOTUPEN", 4, 1 },
+ { "S_KEYINDEX", 0, 4 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_pio_regs_20_to_3b[] = {
+ { "TP_RX_SCHED_MAP", 0x20, 0 },
+ { "S_RXMAPCHANNEL3", 24, 8 },
+ { "S_RXMAPCHANNEL2", 16, 8 },
+ { "S_RXMAPCHANNEL1", 8, 8 },
+ { "S_RXMAPCHANNEL0", 0, 8 },
+ { "TP_RX_SCHED_SGE", 0x21, 0 },
+ { "S_RXSGEMOD1", 12, 4 },
+ { "S_RXSGEMOD0", 8, 4 },
+ { "S_RXSGECHANNEL3", 3, 1 },
+ { "S_RXSGECHANNEL2", 2, 1 },
+ { "S_RXSGECHANNEL1", 1, 1 },
+ { "S_RXSGECHANNEL0", 0, 1 },
+ { "TP_TX_SCHED_MAP", 0x22, 0 },
+ { "S_TXMAPCHANNEL3", 12, 4 },
+ { "S_TXMAPCHANNEL2", 8, 4 },
+ { "S_TXMAPCHANNEL1", 4, 4 },
+ { "S_TXMAPCHANNEL0", 0, 4 },
+ { "TP_TX_SCHED_HDR", 0x23, 0 },
+ { "S_TXMAPHDRCHANNEL7", 28, 4 },
+ { "S_TXMAPHDRCHANNEL6", 24, 4 },
+ { "S_TXMAPHDRCHANNEL5", 20, 4 },
+ { "S_TXMAPHDRCHANNEL4", 16, 4 },
+ { "S_TXMAPHDRCHANNEL3", 12, 4 },
+ { "S_TXMAPHDRCHANNEL2", 8, 4 },
+ { "S_TXMAPHDRCHANNEL1", 4, 4 },
+ { "S_TXMAPHDRCHANNEL0", 0, 4 },
+ { "TP_TX_SCHED_FIFO", 0x24, 0 },
+ { "S_TXMAPFIFOCHANNEL7", 28, 4 },
+ { "S_TXMAPFIFOCHANNEL6", 24, 4 },
+ { "S_TXMAPFIFOCHANNEL5", 20, 4 },
+ { "S_TXMAPFIFOCHANNEL4", 16, 4 },
+ { "S_TXMAPFIFOCHANNEL3", 12, 4 },
+ { "S_TXMAPFIFOCHANNEL2", 8, 4 },
+ { "S_TXMAPFIFOCHANNEL1", 4, 4 },
+ { "S_TXMAPFIFOCHANNEL0", 0, 4 },
+ { "TP_TX_SCHED_PCMD", 0x25, 0 },
+ { "S_TXMAPPCMDCHANNEL7", 28, 4 },
+ { "S_TXMAPPCMDCHANNEL6", 24, 4 },
+ { "S_TXMAPPCMDCHANNEL5", 20, 4 },
+ { "S_TXMAPPCMDCHANNEL4", 16, 4 },
+ { "S_TXMAPPCMDCHANNEL3", 12, 4 },
+ { "S_TXMAPPCMDCHANNEL2", 8, 4 },
+ { "S_TXMAPPCMDCHANNEL1", 4, 4 },
+ { "S_TXMAPPCMDCHANNEL0", 0, 4 },
+ { "TP_TX_SCHED_LPBK", 0x26, 0 },
+ { "S_TXMAPLPBKCHANNEL7", 28, 4 },
+ { "S_TXMAPLPBKCHANNEL6", 24, 4 },
+ { "S_TXMAPLPBKCHANNEL5", 20, 4 },
+ { "S_TXMAPLPBKCHANNEL4", 16, 4 },
+ { "S_TXMAPLPBKCHANNEL3", 12, 4 },
+ { "S_TXMAPLPBKCHANNEL2", 8, 4 },
+ { "S_TXMAPLPBKCHANNEL1", 4, 4 },
+ { "S_TXMAPLPBKCHANNEL0", 0, 4 },
+ { "TP_CHANNEL_MAP", 0x27, 0 },
+ { "RxMapChannelELN", 16, 4 },
+ { "RxMapE2LChannel3", 14, 2 },
+ { "RxMapE2LChannel2", 12, 2 },
+ { "RxMapE2LChannel1", 10, 2 },
+ { "RxMapE2LChannel0", 8, 2 },
+ { "RxMapC2CChannel3", 7, 1 },
+ { "RxMapC2CChannel2", 6, 1 },
+ { "RxMapC2CChannel1", 5, 1 },
+ { "RxMapC2CChannel0", 4, 1 },
+ { "RxMapE2CChannel3", 3, 1 },
+ { "RxMapE2CChannel2", 2, 1 },
+ { "RxMapE2CChannel1", 1, 1 },
+ { "RxMapE2CChannel0", 0, 1 },
+ { "TP_RX_LPBK", 0x28, 0 },
+ { "TP_TX_LPBK", 0x29, 0 },
+ { "TP_TX_SCHED_PPP", 0x2A, 0 },
+ { "S_TXPPPENPORT3", 24, 8 },
+ { "S_TXPPPENPORT2", 16, 8 },
+ { "S_TXPPPENPORT1", 8, 8 },
+ { "S_TXPPPENPORT0", 0, 8 },
+ { "TP_RX_SCHED_FIFO", 0x2B, 0 },
+ { "S_COMMITLIMIT1H", 24, 8 },
+ { "S_COMMITLIMIT1L", 16, 8 },
+ { "S_COMMITLIMIT0H", 8, 8 },
+ { "S_COMMITLIMIT0L", 0, 8 },
+ { "TP_IPMI_CFG1", 0x2E, 0 },
+ { "S_VLANENABLE", 31, 1 },
+ { "S_PRIMARYPORTENABLE", 30, 1 },
+ { "S_SECUREPORTENABLE", 29, 1 },
+ { "S_ARPENABLE", 28, 1 },
+ { "S_IPMI_VLAN", 0, 16 },
+ { "TP_IPMI_CFG2", 0x2F, 0 },
+ { "S_SECUREPORT", 16, 16 },
+ { "S_PRIMARYPORT", 0, 16 },
+ { "TP_RSS_PF0_CONFIG", 0x30, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_PRTENABLE", 30, 1 },
+ { "S_CHNENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF1_CONFIG", 0x31, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_PRTENABLE", 30, 1 },
+ { "S_CHNENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF2_CONFIG", 0x32, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_PRTENABLE", 30, 1 },
+ { "S_CHNENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF3_CONFIG", 0x33, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_PRTENABLE", 30, 1 },
+ { "S_CHNENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF4_CONFIG", 0x34, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_PRTENABLE", 30, 1 },
+ { "S_CHNENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF5_CONFIG", 0x35, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_PRTENABLE", 30, 1 },
+ { "S_CHNENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF6_CONFIG", 0x36, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_PRTENABLE", 30, 1 },
+ { "S_CHNENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF7_CONFIG", 0x37, 0 },
+ { "S_MAPENABLE", 31, 1 },
+ { "S_PRTENABLE", 30, 1 },
+ { "S_CHNENABLE", 29, 1 },
+ { "S_UDPFOURTUPEN", 28, 1 },
+ { "S_IP6FOURTUPEN", 27, 1 },
+ { "S_IP6TWOTUPEN", 26, 1 },
+ { "S_IP4FOURTUPEN", 25, 1 },
+ { "S_IP4TWOTUPEN", 24, 1 },
+ { "S_IVFWIDTH", 20, 4 },
+ { "S_CH1DEFAULTQUEUE", 10, 10 },
+ { "S_CH0DEFAULTQUEUE", 0, 10 },
+ { "TP_RSS_PF_MAP", 0x38, 0 },
+ { "S_LKPIDXSIZE", 24, 2 },
+ { "S_PF7LKPIDX", 21, 3 },
+ { "S_PF6LKPIDX", 18, 3 },
+ { "S_PF5LKPIDX", 15, 3 },
+ { "S_PF4LKPIDX", 12, 3 },
+ { "S_PF3LKPIDX", 9, 3 },
+ { "S_PF2LKPIDX", 6, 3 },
+ { "S_PF1LKPIDX", 3, 3 },
+ { "S_PF0LKPIDX", 0, 3 },
+ { "TP_RSS_PF_MSK", 0x39, 0 },
+ { "S_PF7MSKSIZE", 28, 4 },
+ { "S_PF6MSKSIZE", 24, 4 },
+ { "S_PF5MSKSIZE", 20, 4 },
+ { "S_PF4MSKSIZE", 16, 4 },
+ { "S_PF3MSKSIZE", 12, 4 },
+ { "S_PF2MSKSIZE", 8, 4 },
+ { "S_PF1MSKSIZE", 4, 4 },
+ { "S_PF0MSKSIZE", 0, 4 },
+ { "TP_RSS_VFL_CONFIG", 0x3A, 0 },
+ { "S_KEYSCRAMBLE", 0, 32 },
+ { "TP_RSS_VFH_CONFIG", 0x3B, 0 },
+ { "S_ENABLEUDPHASH", 31, 1 },
+ { "S_VFUPEN", 30, 1 },
+ { "S_RESERVED", 29, 1 },
+ { "S_VFVLNEX", 28, 1 },
+ { "S_VFPRTEN", 27, 1 },
+ { "S_VFCHNEN", 26, 1 },
+ { "S_DEFAULTQUEUE", 16, 10 },
+ { "S_VFLKPIDX", 8, 8 },
+ { "S_VFIP6FOURTUPEN", 7, 1 },
+ { "S_VFIP6TWOTUPEN", 6, 1 },
+ { "S_VFIP4FOURTUPEN", 5, 1 },
+ { "S_VFIP4TWOTUPEN", 4, 1 },
+ { "S_KEYINDEX", 0, 4 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_40_to_49[] = {
+ { "TP_RSS_SECRET_KEY0", 0x40, 0 },
+ { "TP_RSS_SECRET_KEY1", 0x41, 0 },
+ { "TP_RSS_SECRET_KEY2", 0x42, 0 },
+ { "TP_RSS_SECRET_KEY3", 0x43, 0 },
+ { "TP_RSS_SECRET_KEY4", 0x44, 0 },
+ { "TP_RSS_SECRET_KEY5", 0x45, 0 },
+ { "TP_RSS_SECRET_KEY6", 0x46, 0 },
+ { "TP_RSS_SECRET_KEY7", 0x47, 0 },
+ { "TP_RSS_SECRET_KEY8", 0x48, 0 },
+ { "TP_RSS_SECRET_KEY9", 0x49, 0 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_50_to_59[] = {
+ { "TP_ETHER_TYPE_VL", 0x50, 0 },
+ { "S_CQFCTYPE", 16, 16 },
+ { "S_VLANTYPE", 0, 16 },
+ { "TP_ETHER_TYPE_IP", 0x51, 0 },
+ { "S_IPV6TYPE", 16, 16 },
+ { "S_IPV4TYPE", 0, 16 },
+ { "TP_ETHER_TYPE_FW", 0x52, 0 },
+ { "S_ETHTYPE1", 16, 16 },
+ { "S_ETHTYPE0", 0, 16 },
+ { "TP_VXLAN_HEADER", 0x53, 0 },
+ { "S_VXLANPORT", 0, 16 },
+ { "TP_CORE_POWER", 0x54, 0 },
+ { "S_SLEEPRDYVNT", 12, 1 },
+ { "S_SLEEPRDYTBL", 11, 1 },
+ { "S_SLEEPRDYMIB", 10, 1 },
+ { "S_SLEEPRDYARP", 9, 1 },
+ { "S_SLEEPRDYRSS", 8, 1 },
+ { "S_SLEEPREQVNT", 4, 1 },
+ { "S_SLEEPREQTBL", 3, 1 },
+ { "S_SLEEPREQMIB", 2, 1 },
+ { "S_SLEEPREQARP", 1, 1 },
+ { "S_SLEEPREQRSS", 0, 1 },
+ { "TP_CORE_RDMA", 0x55, 0 },
+ { "S_SHAREDRQEN", 31, 1 },
+ { "S_SHAREDXRC", 30, 1 },
+ { "S_IMMEDIATEOP", 20, 4 },
+ { "S_IMMEDIATESE", 16, 4 },
+ { "S_ATOMICREQOP", 12, 4 },
+ { "S_ATOMICRSPOP", 8, 4 },
+ { "S_IMMEDIASEEN", 1, 1 },
+ { "S_IMMEDIATEEN", 0, 1 },
+ { "TP_FRAG_CONFIG", 0x56, 0 },
+ { "Reserved", 16, 16 },
+ { "UserMode", 14, 2 },
+ { "FcoeMode", 12, 2 },
+ { "IandpMode", 10, 2 },
+ { "RddpMode", 8, 2 },
+ { "IwarpMode", 6, 2 },
+ { "IscsiMode", 4, 2 },
+ { "DdpMode", 2, 2 },
+ { "PassMode", 0, 2 },
+ { "TP_CMM_CONFIG", 0x57, 0 },
+ { "WrCntIdle", 16, 16 },
+ { "RdThreshold", 8, 7 },
+ { "WrThrLevel2", 7, 1 },
+ { "WrThrLevel1", 6, 1 },
+ { "WrThrThreshEn", 5, 1 },
+ { "WrThrThresh", 0, 5},
+ { "TP_VXLAN_CONFIG", 0x58, 0 },
+ { "VxLanFlags", 16, 16},
+ { "VxLanType", 0, 16},
+ { "TP_NVGRE_CONFIG", 0x59, 0 },
+ { "GreFlags", 16, 16 },
+ { "GreType", 0, 16 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_pio_regs_40_to_52[] = {
+ { "TP_RSS_SECRET_KEY0", 0x40, 0 },
+ { "TP_RSS_SECRET_KEY1", 0x41, 0 },
+ { "TP_RSS_SECRET_KEY2", 0x42, 0 },
+ { "TP_RSS_SECRET_KEY3", 0x43, 0 },
+ { "TP_RSS_SECRET_KEY4", 0x44, 0 },
+ { "TP_RSS_SECRET_KEY5", 0x45, 0 },
+ { "TP_RSS_SECRET_KEY6", 0x46, 0 },
+ { "TP_RSS_SECRET_KEY7", 0x47, 0 },
+ { "TP_RSS_SECRET_KEY8", 0x48, 0 },
+ { "TP_RSS_SECRET_KEY9", 0x49, 0 },
+ { "TP_ETHER_TYPE_VL", 0x50, 0 },
+ { "S_CQFCTYPE", 16, 16 },
+ { "S_VLANTYPE", 0, 16 },
+ { "TP_ETHER_TYPE_IP", 0x51, 0 },
+ { "S_IPV6TYPE", 16, 16 },
+ { "S_IPV4TYPE", 0, 16 },
+ { "TP_ETHER_TYPE_FW", 0x52, 0 },
+ { "S_ETHTYPE1", 16, 16 },
+ { "S_ETHTYPE0", 0, 16 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_pio_regs_54_to_55[] = {
+ { "TP_CORE_POWER", 0x54, 0 },
+ { "S_SLEEPRDYVNT", 12, 1 },
+ { "S_SLEEPRDYTBL", 11, 1 },
+ { "S_SLEEPRDYMIB", 10, 1 },
+ { "S_SLEEPRDYARP", 9, 1 },
+ { "S_SLEEPRDYRSS", 8, 1 },
+ { "S_SLEEPREQVNT", 4, 1 },
+ { "S_SLEEPREQTBL", 3, 1 },
+ { "S_SLEEPREQMIB", 2, 1 },
+ { "S_SLEEPREQARP", 1, 1 },
+ { "S_SLEEPREQRSS", 0, 1 },
+ { "TP_CORE_RDMA", 0x55, 0 },
+ { "S_IMMEDIATEOP", 20, 4 },
+ { "S_IMMEDIATESE", 16, 4 },
+ { "S_ATOMICREQOP", 12, 4 },
+ { "S_ATOMICRSPOP", 8, 4 },
+ { "S_IMMEDIASEEN", 1, 1 },
+ { "S_IMMEDIATEEN", 0, 1 },
+ { NULL }
+};
+
+static struct cudbg_reg_info sge_debug_data_high[] = {
+ {"SGE_DEBUG_DATA_HIGH_INDEX_0", 0x1280},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_1", 0x1284},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_2", 0x1288},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_3", 0x128c},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_4", 0x1290},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_5", 0x1294},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_6", 0x1298},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_7", 0x129c},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_8", 0x12a0},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_9", 0x12a4},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_10", 0x12a8},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_11", 0x12ac},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_12", 0x12b0},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_13", 0x12b4},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_14", 0x12b8},
+ {"SGE_DEBUG_DATA_HIGH_INDEX_15", 0x12bc},
+
+};
+
+static struct cudbg_reg_info sge_debug_data_low[] = {
+ {"SGE_DEBUG_DATA_LOW_INDEX_0", 0x12c0},
+ {"SGE_DEBUG_DATA_LOW_INDEX_1", 0x12c4},
+ {"SGE_DEBUG_DATA_LOW_INDEX_2", 0x12c8},
+ {"SGE_DEBUG_DATA_LOW_INDEX_3", 0x12cc},
+ {"SGE_DEBUG_DATA_LOW_INDEX_4", 0x12d0},
+ {"SGE_DEBUG_DATA_LOW_INDEX_5", 0x12d4},
+ {"SGE_DEBUG_DATA_LOW_INDEX_6", 0x12d8},
+ {"SGE_DEBUG_DATA_LOW_INDEX_7", 0x12dc},
+ {"SGE_DEBUG_DATA_LOW_INDEX_8", 0x12e0},
+ {"SGE_DEBUG_DATA_LOW_INDEX_9", 0x12e4},
+ {"SGE_DEBUG_DATA_LOW_INDEX_10", 0x12e8},
+ {"SGE_DEBUG_DATA_LOW_INDEX_11", 0x12ec},
+ {"SGE_DEBUG_DATA_LOW_INDEX_12", 0x12f0},
+ {"SGE_DEBUG_DATA_LOW_INDEX_13", 0x12f4},
+ {"SGE_DEBUG_DATA_LOW_INDEX_14", 0x12f8},
+ {"SGE_DEBUG_DATA_LOW_INDEX_15", 0x12fc},
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_60_to_6d[] = {
+ { "TP_DBG_CLEAR", 0x60, 0 },
+ { "TP_DBG_CORE_HDR0", 0x61, 0 },
+ { "S_RESERVED", 17, 15 },
+ { "S_E_TCP_OP_SRDY", 16, 1 },
+ { "S_E_PLD_TXZEROP_SRDY", 15, 1 },
+ { "S_E_PLD_RX_SRDY", 14, 1 },
+ { "S_E_RX_ERROR_SRDY", 13, 1 },
+ { "S_E_RX_ISS_SRDY", 12, 1 },
+ { "S_C_TCP_OP_SRDY", 11, 1 },
+ { "S_C_PLD_TXZEROP_SRDY", 10, 1 },
+ { "S_C_PLD_RX_SRDY", 9, 1 },
+ { "S_C_RX_ERROR_SRDY", 8, 1 },
+ { "S_C_RX_ISS_SRDY", 7, 1 },
+ { "S_E_CPL5_TXVALID", 6, 1 },
+ { "S_E_ETH_TXVALID", 5, 1 },
+ { "S_E_IP_TXVALID", 4, 1 },
+ { "S_E_TCP_TXVALID", 3, 1 },
+ { "S_C_CPL5_RXVALID", 2, 1 },
+ { "S_C_CPL5_TXVALID", 1, 1 },
+ { "S_E_TCP_OPT_RXVALID", 0, 1 },
+ { "TP_DBG_CORE_HDR1", 0x62, 0 },
+ { "S_RESERVED", 7, 25 },
+ { "S_E_CPL5_TXFULL", 6, 1 },
+ { "S_E_ETH_TXFULL", 5, 1 },
+ { "S_E_IP_TXFULL", 4, 1 },
+ { "S_E_TCP_TXFULL", 3, 1 },
+ { "S_C_CPL5_RXFULL", 2, 1 },
+ { "S_C_CPL5_TXFULL", 1, 1 },
+ { "S_E_TCP_OPT_RXFULL", 0, 1 },
+ { "TP_DBG_CORE_FATAL", 0x63, 0 },
+ { "S_EMSGFATAL", 31, 1 },
+ { "S_CMSGFATAL", 30, 1 },
+ { "S_PAWSFATAL", 29, 1 },
+ { "S_SRAMFATAL", 28, 1 },
+ { "S_CPCMDCONG", 24, 4 },
+ { "S_EPCMDCONG", 22, 2 },
+ { "S_CPCMDLENFATAL", 21, 1 },
+ { "S_EPCMDLENFATAL", 20, 1 },
+ { "S_CPCMDVALID", 16, 4 },
+ { "S_CPCMDAFULL", 12, 4 },
+ { "S_EPCMDVALID", 10, 2 },
+ { "S_EPCMDAFULL", 8, 2 },
+ { "S_CPCMDEOIFATAL", 7, 1 },
+ { "S_CPCMDTTLFATAL", 6, 1 },
+ { "S_CDATACHNFATAL", 5, 1 },
+ { "S_RESERVED", 4, 1 },
+ { "S_CNONZEROPPOPCNT", 2, 2 },
+ { "S_CPCMDEOICNT", 0, 2 },
+ { "TP_DBG_CORE_OUT", 0x64, 0 },
+ { "S_CRXBUSYOUT", 31, 1 },
+ { "S_CTXBUSYOUT", 30, 1 },
+ { "S_CRDCPLPKT", 29, 1 },
+ { "S_CRDTCPPKT", 28, 1 },
+ { "S_CNEWMSG", 27, 1 },
+ { "S_CCPLENC", 26, 1 },
+ { "S_CWRCPLPKT", 25, 1 },
+ { "S_CWRETHPKT", 24, 1 },
+ { "S_CWRIPPKT", 23, 1 },
+ { "S_CWRTCPPKT", 22, 1 },
+ { "S_CWRZEROP", 21, 1 },
+ { "S_CCPLTXFULL", 20, 1 },
+ { "S_CETHTXFULL", 19, 1 },
+ { "S_CIPTXFULL", 18, 1 },
+ { "S_CTCPTXFULL", 17, 1 },
+ { "S_CPLDTXZEROPDRDY", 16, 1 },
+ { "S_ERXBUSYOUT", 15, 1 },
+ { "S_ETXBUSYOUT", 14, 1 },
+ { "S_ERDCPLPKT", 13, 1 },
+ { "S_ERDTCPPKT", 12, 1 },
+ { "S_ENEWMSG", 11, 1 },
+ { "S_RESERVED1", 10, 1 },
+ { "S_EWRCPLPKT", 9, 1 },
+ { "S_EWRETHPKT", 8, 1 },
+ { "S_EWRIPPKT", 7, 1 },
+ { "S_EWRTCPPKT", 6, 1 },
+ { "S_EWRZEROP", 5, 1 },
+ { "S_ECPLTXFULL", 4, 1 },
+ { "S_EETHTXFULL", 3, 1 },
+ { "S_EIPTXFULL", 2, 1 },
+ { "S_ETCPTXFULL", 1, 1 },
+ { "S_EPLDTXZEROPDRDY", 0, 1 },
+ { "TP_DBG_CORE_TID", 0x65, 0 },
+ { "S_LINENUMBER", 24, 7 },
+ { "S_SPURIOUSMSG", 23, 1 },
+ { "S_SRC", 21, 2 },
+ { "S_SYNLEARNED", 20, 1 },
+ { "S_TIDVALUE", 0, 20 },
+ { "TP_DBG_ENG_RES0", 0x66, 0 },
+ { "S_RESOURCESREADY", 31, 1 },
+ { "S_RCFOPCODEOUTSRDY", 30, 1 },
+ { "S_RCFDATAOUTSRDY", 29, 1 },
+ { "S_FLUSHINPUTMSG", 28, 1 },
+ { "S_RCFOPSRCOUT", 26, 2 },
+ { "S_C_MSG", 25, 1 },
+ { "S_E_MSG", 24, 1 },
+ { "S_RCFOPCODEOUT", 20, 4 },
+ { "S_EFFRCFOPCODEOUT", 16, 4 },
+ { "S_SEENRESOURCESREADY", 15, 1 },
+ { "S_DELDRDY", 14, 1 },
+ { "S_OPCODEWAITSFORDATA", 13, 1 },
+ { "S_CPLDRXSRDY", 12, 1 },
+ { "S_CPLDRXZEROPSRDY", 11, 1 },
+ { "S_EPLDRXZEROPSRDY", 10, 1 },
+ { "S_ERXERRORSRDY", 9, 1 },
+ { "S_EPLDRXSRDY", 8, 1 },
+ { "S_CRXBUSY", 7, 1 },
+ { "S_ERXBUSY", 6, 1 },
+ { "S_TIMERINSERTBUSY", 5, 1 },
+ { "S_WCFBUSY", 4, 1 },
+ { "S_CTXBUSY", 3, 1 },
+ { "S_CPCMDBUSY", 2, 1 },
+ { "S_ETXBUSY", 1, 1 },
+ { "S_EPCMDBUSY", 0, 1 },
+ { "TP_DBG_ENG_RES1", 0x67, 0 },
+ { "S_RXCPLSRDY", 31, 1 },
+ { "S_RXOPTSRDY", 30, 1 },
+ { "S_RXPLDLENSRDY", 29, 1 },
+ { "S_RXISSSRDY", 28, 1 },
+ { "S_CPLCMDIN", 20, 8 },
+ { "S_RCFPTIDSRDY", 19, 1 },
+ { "S_EPDUHDRSRDY", 18, 1 },
+ { "S_TUNNELPKTREG", 17, 1 },
+ { "S_TXPKTCSUMSRDY", 16, 1 },
+ { "S_TABLEACCESSLATENCY", 12, 4 },
+ { "S_MMGRDONE", 11, 1 },
+ { "S_SEENMMGRDONE", 10, 1 },
+ { "S_RXERRORSRDY", 9, 1 },
+ { "S_RCFOPTIONSTCPSRDY", 8, 1 },
+ { "S_ENGINESTATE", 6, 2 },
+ { "S_TABLEACCESINCREMENT", 5, 1 },
+ { "S_TABLEACCESCOMPLETE", 4, 1 },
+ { "S_RCFOPCODEOUTUSABLE", 3, 1 },
+ { "S_RCFDATAOUTUSABLE", 2, 1 },
+ { "TP_DBG_ENG_RES2", 0x68, 0 },
+ { "S_CPLCMDRAW", 24, 8 },
+ { "S_RXMACPORT", 20, 4 },
+ { "S_TXECHANNEL", 18, 2 },
+ { "S_RXECHANNEL", 16, 2 },
+ { "S_CDATAOUT", 15, 1 },
+ { "S_CREADPDU", 14, 1 },
+ { "S_EDATAOUT", 13, 1 },
+ { "S_EREADPDU", 12, 1 },
+ { "S_ETCPOPSRDY", 11, 1 },
+ { "S_CTCPOPSRDY", 10, 1 },
+ { "S_CPKTOUT", 9, 1 },
+ { "S_CMDBRSPSRDY", 8, 1 },
+ { "S_RXPSTRUCTSFULL", 6, 2 },
+ { "S_RXPAGEPOOLFULL", 4, 2 },
+ { "S_RCFREASONOUT", 0, 4 },
+ { "TP_DBG_CORE_PCMD", 0x69, 0 },
+ { "S_CPCMDEOPCNT", 30, 2 },
+ { "S_CPCMDLENSAVE", 16, 14 },
+ { "S_EPCMDEOPCNT", 14, 2 },
+ { "S_EPCMDLENSAVE", 0, 14 },
+ { "TP_DBG_SCHED_TX", 0x6A, 0 },
+ { "S_TXCHNXOFF", 28, 4 },
+ { "S_TXFIFOCNG", 24, 4 },
+ { "S_TXPCMDCNG", 20, 4 },
+ { "S_TXLPBKCNG", 16, 4 },
+ { "S_TXHDRCNG", 8, 8 },
+ { "S_TXMODXOFF", 0, 8 },
+ { "TP_DBG_SCHED_RX", 0x6B, 0 },
+ { "S_RXCHNXOFF", 28, 4 },
+ { "S_RXSGECNG", 24, 4 },
+ { "S_RXFIFOCNG", 20, 4 },
+ { "S_RXLPBKCNG", 16, 4 },
+ { "S_RXPCMDCNG", 14, 2 },
+ { "S_RESERVED0", 12, 2 },
+ { "S_RXHDRCNG", 8, 4 },
+ { "S_RESERVED0", 2, 6 },
+ { "S_RXMODXOFF", 0, 2 },
+ { "TP_DBG_ERROR_CNT", 0x6C, 0 },
+ { "TP_DBG_CORE_CPL", 0x6d, 0 },
+ { "CplCmdOut3", 24, 8 },
+ { "CplCmdOut2", 16, 8 },
+ { "CplCmdOut1", 8, 8 },
+ { "CplCmdOut0", 0, 8 },
+ { NULL }
+};
+
+
+static struct cudbg_reg_info t5_tp_pio_regs_60_to_6c[] = {
+ { "TP_DBG_CLEAR", 0x60, 0 },
+ { "TP_DBG_CORE_HDR0", 0x61, 0 },
+ { "S_RESERVED", 17, 15 },
+ { "S_E_TCP_OP_SRDY", 16, 1 },
+ { "S_E_PLD_TXZEROP_SRDY", 15, 1 },
+ { "S_E_PLD_RX_SRDY", 14, 1 },
+ { "S_E_RX_ERROR_SRDY", 13, 1 },
+ { "S_E_RX_ISS_SRDY", 12, 1 },
+ { "S_C_TCP_OP_SRDY", 11, 1 },
+ { "S_C_PLD_TXZEROP_SRDY", 10, 1 },
+ { "S_C_PLD_RX_SRDY", 9, 1 },
+ { "S_C_RX_ERROR_SRDY", 8, 1 },
+ { "S_C_RX_ISS_SRDY", 7, 1 },
+ { "S_E_CPL5_TXVALID", 6, 1 },
+ { "S_E_ETH_TXVALID", 5, 1 },
+ { "S_E_IP_TXVALID", 4, 1 },
+ { "S_E_TCP_TXVALID", 3, 1 },
+ { "S_C_CPL5_RXVALID", 2, 1 },
+ { "S_C_CPL5_TXVALID", 1, 1 },
+ { "S_E_TCP_OPT_RXVALID", 0, 1 },
+ { "TP_DBG_CORE_HDR1", 0x62, 0 },
+ { "S_RESERVED", 7, 25 },
+ { "S_E_CPL5_TXFULL", 6, 1 },
+ { "S_E_ETH_TXFULL", 5, 1 },
+ { "S_E_IP_TXFULL", 4, 1 },
+ { "S_E_TCP_TXFULL", 3, 1 },
+ { "S_C_CPL5_RXFULL", 2, 1 },
+ { "S_C_CPL5_TXFULL", 1, 1 },
+ { "S_E_TCP_OPT_RXFULL", 0, 1 },
+ { "TP_DBG_CORE_FATAL", 0x63, 0 },
+ { "S_EMSGFATAL", 31, 1 },
+ { "S_CMSGFATAL", 30, 1 },
+ { "S_PAWSFATAL", 29, 1 },
+ { "S_SRAMFATAL", 28, 1 },
+ { "S_CPCMDCONG", 24, 4 },
+ { "S_EPCMDCONG", 22, 2 },
+ { "S_CPCMDLENFATAL", 21, 1 },
+ { "S_EPCMDLENFATAL", 20, 1 },
+ { "S_CPCMDVALID", 16, 4 },
+ { "S_CPCMDAFULL", 12, 4 },
+ { "S_EPCMDVALID", 10, 2 },
+ { "S_EPCMDAFULL", 8, 2 },
+ { "S_CPCMDEOIFATAL", 7, 1 },
+ { "S_CPCMDTTLFATAL", 6, 1 },
+ { "S_CDATACHNFATAL", 5, 1 },
+ { "S_RESERVED", 4, 1 },
+ { "S_CNONZEROPPOPCNT", 2, 2 },
+ { "S_CPCMDEOICNT", 0, 2 },
+ { "TP_DBG_CORE_OUT", 0x64, 0 },
+ { "S_CRXBUSYOUT", 31, 1 },
+ { "S_CTXBUSYOUT", 30, 1 },
+ { "S_CRDCPLPKT", 29, 1 },
+ { "S_CRDTCPPKT", 28, 1 },
+ { "S_CNEWMSG", 27, 1 },
+ { "S_CCPLENC", 26, 1 },
+ { "S_CWRCPLPKT", 25, 1 },
+ { "S_CWRETHPKT", 24, 1 },
+ { "S_CWRIPPKT", 23, 1 },
+ { "S_CWRTCPPKT", 22, 1 },
+ { "S_CWRZEROP", 21, 1 },
+ { "S_CCPLTXFULL", 20, 1 },
+ { "S_CETHTXFULL", 19, 1 },
+ { "S_CIPTXFULL", 18, 1 },
+ { "S_CTCPTXFULL", 17, 1 },
+ { "S_CPLDTXZEROPDRDY", 16, 1 },
+ { "S_RESERVED1", 10, 1 },
+ { "S_EWRCPLPKT", 9, 1 },
+ { "S_EWRETHPKT", 8, 1 },
+ { "S_EWRIPPKT", 7, 1 },
+ { "S_EWRTCPPKT", 6, 1 },
+ { "S_EWRZEROP", 5, 1 },
+ { "S_ECPLTXFULL", 4, 1 },
+ { "S_EETHTXFULL", 3, 1 },
+ { "S_EIPTXFULL", 2, 1 },
+ { "S_ETCPTXFULL", 1, 1 },
+ { "S_EPLDTXZEROPDRDY", 0, 1 },
+ { "TP_DBG_CORE_TID", 0x65, 0 },
+ { "S_LINENUMBER", 24, 7 },
+ { "S_SPURIOUSMSG", 23, 1 },
+ { "S_SRC", 21, 2 },
+ { "S_SYNLEARNED", 20, 1 },
+ { "S_TIDVALUE", 0, 20 },
+ { "TP_DBG_ENG_RES0", 0x66, 0 },
+ { "S_RESOURCESREADY", 31, 1 },
+ { "S_RCFOPCODEOUTSRDY", 30, 1 },
+ { "S_RCFDATAOUTSRDY", 29, 1 },
+ { "S_FLUSHINPUTMSG", 28, 1 },
+ { "S_RCFOPSRCOUT", 26, 2 },
+ { "S_C_MSG", 25, 1 },
+ { "S_E_MSG", 24, 1 },
+ { "S_RCFOPCODEOUT", 20, 4 },
+ { "S_EFFRCFOPCODEOUT", 16, 4 },
+ { "S_SEENRESOURCESREADY", 15, 1 },
+ { "S_DELDRDY", 14, 1 },
+ { "S_OPCODEWAITSFORDATA", 13, 1 },
+ { "S_CPLDRXSRDY", 12, 1 },
+ { "S_CPLDRXZEROPSRDY", 11, 1 },
+ { "S_EPLDRXZEROPSRDY", 10, 1 },
+ { "S_ERXERRORSRDY", 9, 1 },
+ { "S_EPLDRXSRDY", 8, 1 },
+ { "S_CRXBUSY", 7, 1 },
+ { "S_ERXBUSY", 6, 1 },
+ { "S_TIMERINSERTBUSY", 5, 1 },
+ { "S_WCFBUSY", 4, 1 },
+ { "S_CTXBUSY", 3, 1 },
+ { "S_CPCMDBUSY", 2, 1 },
+ { "S_ETXBUSY", 1, 1 },
+ { "S_EPCMDBUSY", 0, 1 },
+ { "TP_DBG_ENG_RES1", 0x67, 0 },
+ { "S_RXCPLSRDY", 31, 1 },
+ { "S_RXOPTSRDY", 30, 1 },
+ { "S_RXPLDLENSRDY", 29, 1 },
+ { "S_RXNOTBUSY", 28, 1 },
+ { "S_CPLCMDIN", 20, 8 },
+ { "S_RCFPTIDSRDY", 19, 1 },
+ { "S_EPDUHDRSRDY", 18, 1 },
+ { "S_TUNNELPKTREG", 17, 1 },
+ { "S_TXPKTCSUMSRDY", 16, 1 },
+ { "S_TABLEACCESSLATENCY", 12, 4 },
+ { "S_MMGRDONE", 11, 1 },
+ { "S_SEENMMGRDONE", 10, 1 },
+ { "S_RXERRORSRDY", 9, 1 },
+ { "S_RCFOPTIONSTCPSRDY", 8, 1 },
+ { "S_ENGINESTATE", 6, 2 },
+ { "S_TABLEACCESINCREMENT", 5, 1 },
+ { "S_TABLEACCESCOMPLETE", 4, 1 },
+ { "S_RCFOPCODEOUTUSABLE", 3, 1 },
+ { "S_RCFDATAOUTUSABLE", 2, 1 },
+ { "S_RCFDATAWAITAFTERRD", 1, 1 },
+ { "S_RCFDATACMRDY", 0, 1 },
+ { "TP_DBG_ENG_RES2", 0x68, 0 },
+ { "S_CPLCMDRAW", 24, 8 },
+ { "S_RXMACPORT", 20, 4 },
+ { "S_TXECHANNEL", 18, 2 },
+ { "S_RXECHANNEL", 16, 2 },
+ { "S_CDATAOUT", 15, 1 },
+ { "S_CREADPDU", 14, 1 },
+ { "S_EDATAOUT", 13, 1 },
+ { "S_EREADPDU", 12, 1 },
+ { "S_ETCPOPSRDY", 11, 1 },
+ { "S_CTCPOPSRDY", 10, 1 },
+ { "S_CPKTOUT", 9, 1 },
+ { "S_CMDBRSPSRDY", 8, 1 },
+ { "S_RXPSTRUCTSFULL", 6, 2 },
+ { "S_RXPAGEPOOLFULL", 4, 2 },
+ { "S_RCFREASONOUT", 0, 4 },
+ { "TP_DBG_CORE_PCMD", 0x69, 0 },
+ { "S_CPCMDEOPCNT", 30, 2 },
+ { "S_CPCMDLENSAVE", 16, 14 },
+ { "S_EPCMDEOPCNT", 14, 2 },
+ { "S_EPCMDLENSAVE", 0, 14 },
+ { "TP_DBG_SCHED_TX", 0x6A, 0 },
+ { "S_TXCHNXOFF", 28, 4 },
+ { "S_TXFIFOCNG", 24, 4 },
+ { "S_TXPCMDCNG", 20, 4 },
+ { "S_TXLPBKCNG", 16, 4 },
+ { "S_TXHDRCNG", 8, 8 },
+ { "S_TXMODXOFF", 0, 8 },
+ { "TP_DBG_SCHED_RX", 0x6B, 0 },
+ { "S_RXCHNXOFF", 28, 4 },
+ { "S_RXSGECNG", 24, 4 },
+ { "S_RXFIFOCNG", 20, 4 },
+ { "S_RXLPBKCNG", 16, 4 },
+ { "S_RXPCMDCNG", 14, 2 },
+ { "S_RESERVED0", 12, 2 },
+ { "S_RXHDRCNG", 8, 4 },
+ { "S_RESERVED0", 2, 6 },
+ { "S_RXMODXOFF", 0, 2 },
+ { "TP_DBG_ERROR_CNT", 0x6C, 0 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_6f[] = {
+ { "TP_MIB_DEBUG", 0x6F, 0 },
+ { "S_SRC3", 31, 1 },
+ { "S_LINENUM3", 24, 7 },
+ { "S_SRC2", 23, 1 },
+ { "S_LINENUM2", 16, 7 },
+ { "S_SRC1", 15, 1 },
+ { "S_LINENUM1", 8, 7 },
+ { "S_SRC0", 7, 1 },
+ { "S_LINENUM0", 0, 7 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_130_to_141[] = {
+ { "TP_DBG_ESIDE_PKT0", 0x130, 0 },
+ { "S_ETXSOPCNT", 28, 4 },
+ { "S_ETXEOPCNT", 24, 4 },
+ { "S_ETXPLDSOPCNT", 20, 4 },
+ { "S_ETXPLDEOPCNT", 16, 4 },
+ { "S_ERXSOPCNT", 12, 4 },
+ { "S_ERXEOPCNT", 8, 4 },
+ { "S_ERXPLDSOPCNT", 4, 4 },
+ { "S_ERXPLDEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_PKT1", 0x131, 0 },
+ { "S_ETXSOPCNT", 28, 4 },
+ { "S_ETXEOPCNT", 24, 4 },
+ { "S_ETXPLDSOPCNT", 20, 4 },
+ { "S_ETXPLDEOPCNT", 16, 4 },
+ { "S_ERXSOPCNT", 12, 4 },
+ { "S_ERXEOPCNT", 8, 4 },
+ { "S_ERXPLDSOPCNT", 4, 4 },
+ { "S_ERXPLDEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_PKT2", 0x132, 0 },
+ { "S_ETXSOPCNT", 28, 4 },
+ { "S_ETXEOPCNT", 24, 4 },
+ { "S_ETXPLDSOPCNT", 20, 4 },
+ { "S_ETXPLDEOPCNT", 16, 4 },
+ { "S_ERXSOPCNT", 12, 4 },
+ { "S_ERXEOPCNT", 8, 4 },
+ { "S_ERXPLDSOPCNT", 4, 4 },
+ { "S_ERXPLDEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_PKT3", 0x133, 0 },
+ { "S_ETXSOPCNT", 28, 4 },
+ { "S_ETXEOPCNT", 24, 4 },
+ { "S_ETXPLDSOPCNT", 20, 4 },
+ { "S_ETXPLDEOPCNT", 16, 4 },
+ { "S_ERXSOPCNT", 12, 4 },
+ { "S_ERXEOPCNT", 8, 4 },
+ { "S_ERXPLDSOPCNT", 4, 4 },
+ { "S_ERXPLDEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_FIFO0", 0x134, 0 },
+ { "S_PLDRXCSUMVALID1", 31, 1 },
+ { "S_PLDRXZEROPSRDY1", 30, 1 },
+ { "S_PLDRXVALID1", 29, 1 },
+ { "S_TCPRXVALID1", 28, 1 },
+ { "S_IPRXVALID1", 27, 1 },
+ { "S_ETHRXVALID1", 26, 1 },
+ { "S_CPLRXVALID1", 25, 1 },
+ { "S_FSTATIC1", 24, 1 },
+ { "S_ERRORSRDY1", 23, 1 },
+ { "S_PLDTXSRDY1", 22, 1 },
+ { "S_DBVLD1", 21, 1 },
+ { "S_PLDTXVALID1", 20, 1 },
+ { "S_ETXVALID1", 19, 1 },
+ { "S_ETXFULL1", 18, 1 },
+ { "S_ERXVALID1", 17, 1 },
+ { "S_ERXFULL1", 16, 1 },
+ { "S_PLDRXCSUMVALID0", 15, 1 },
+ { "S_PLDRXZEROPSRDY0", 14, 1},
+ { "S_PLDRXVALID0", 13, 1 },
+ { "S_TCPRXVALID0", 12, 1 },
+ { "S_IPRXVALID0", 11, 1 },
+ { "S_ETHRXVALID0", 10, 1 },
+ { "S_CPLRXVALID0", 9, 1 },
+ { "S_FSTATIC0", 8, 1 },
+ { "S_ERRORSRDY0", 7, 1 },
+ { "S_PLDTXSRDY0", 6, 1 },
+ { "S_DBVLD0", 5, 1 },
+ { "S_PLDTXVALID0", 4, 1 },
+ { "S_ETXVALID0", 3, 1 },
+ { "S_ETXFULL0", 2, 1 },
+ { "S_ERXVALID0", 1, 1 },
+ { "S_ERXFULL0", 0, 1 },
+ { "TP_DBG_ESIDE_FIFO1", 0x135, 0 },
+ { "S_PLDRXCSUMVALID3", 31, 1 },
+ { "S_PLDRXZEROPSRDY3", 30, 1 },
+ { "S_PLDRXVALID3", 29, 1 },
+ { "S_TCPRXVALID3", 28, 1 },
+ { "S_IPRXVALID3", 27, 1 },
+ { "S_ETHRXVALID3", 26, 1 },
+ { "S_CPLRXVALID3", 25, 1 },
+ { "S_FSTATIC3", 24, 1 },
+ { "S_ERRORSRDY3", 23, 1 },
+ { "S_PLDTXSRDY3", 22, 1 },
+ { "S_DBVLD3", 21, 1 },
+ { "S_PLDTXVALID3", 20, 1 },
+ { "S_ETXVALID3", 19, 1 },
+ { "S_ETXFULL3", 18, 1 },
+ { "S_ERXVALID3", 17, 1 },
+ { "S_ERXFULL3", 16, 1 },
+ { "S_PLDRXCSUMVALID2", 15, 1 },
+ { "S_PLDRXZEROPSRDY2", 14, 1},
+ { "S_PLDRXVALID2", 13, 1 },
+ { "S_TCPRXVALID2", 12, 1 },
+ { "S_IPRXVALID2", 11, 1 },
+ { "S_ETHRXVALID2", 10, 1 },
+ { "S_CPLRXVALID2", 9, 1 },
+ { "S_FSTATIC2", 8, 1 },
+ { "S_ERRORSRDY2", 7, 1 },
+ { "S_PLDTXSRDY2", 6, 1 },
+ { "S_DBVLD2", 5, 1 },
+ { "S_PLDTXVALID2", 4, 1 },
+ { "S_ETXVALID2", 3, 1 },
+ { "S_ETXFULL2", 2, 1 },
+ { "S_ERXVALID2", 1, 1 },
+ { "S_ERXFULL2", 0, 1 },
+ { "TP_DBG_ESIDE_DISP0", 0x136, 0 },
+ { "S_RESRDY", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_FIFOCPL5RXVALID", 27, 1 },
+ { "S_FIFOETHRXVALID", 26, 1 },
+ { "S_FIFOETHRXSOCP", 25, 1 },
+ { "S_FIFOPLDRXZEROP", 24, 1 },
+ { "S_PLDRXVALID", 23, 1 },
+ { "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
+ { "S_FIFOIPRXVALID", 21, 1 },
+ { "S_FIFOTCPRXVALID", 20, 1 },
+ { "S_PLDRXCSUMVALID", 19, 1 },
+ { "S_FIFOIPCSUMSRDY", 18, 1 },
+ { "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
+ { "S_FIFOTCPCSUMSRDY", 16, 1 },
+ { "S_FIFOGRERXVALID", 15, 1 },
+ { "S_FIFOGRERXREADY", 14, 1 },
+ { "S_FIFOGRERXSOCP", 13, 1 },
+ { "S_ESTATIC4", 12, 1 },
+ { "S_FIFOCPLSOCPCNT", 10, 2 },
+ { "S_FIFOETHSOCPCNT", 8, 2 },
+ { "S_FIFOIPSOCPCNT", 6, 2},
+ { "S_FIFOTCPSOCPCNT", 4, 2 },
+ { "S_PLD_RXZEROP_CNT", 2, 2 },
+ { "S_ESTATIC6", 1, 1 },
+ { "S_TXFULL", 0, 1 },
+ { "TP_DBG_ESIDE_DISP1", 0x137, 0 },
+ { "S_RESRDY", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_FIFOCPL5RXVALID", 27, 1 },
+ { "S_FIFOETHRXVALID", 26, 1 },
+ { "S_FIFOETHRXSOCP", 25, 1 },
+ { "S_FIFOPLDRXZEROP", 24, 1 },
+ { "S_PLDRXVALID", 23, 1 },
+ { "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
+ { "S_FIFOIPRXVALID", 21, 1 },
+ { "S_FIFOTCPRXVALID", 20, 1 },
+ { "S_PLDRXCSUMVALID", 19, 1 },
+ { "S_FIFOIPCSUMSRDY", 18, 1 },
+ { "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
+ { "S_FIFOTCPCSUMSRDY", 16, 1 },
+ { "S_FIFOGRERXVALID", 15, 1 },
+ { "S_FIFOGRERXREADY", 14, 1 },
+ { "S_FIFOGRERXSOCP", 13, 1 },
+ { "S_ESTATIC4", 12, 1 },
+ { "S_FIFOCPLSOCPCNT", 10, 2 },
+ { "S_FIFOETHSOCPCNT", 8, 2 },
+ { "S_FIFOIPSOCPCNT", 6, 2},
+ { "S_FIFOTCPSOCPCNT", 4, 2 },
+ { "S_PLD_RXZEROP_CNT", 2, 2 },
+ { "S_ESTATIC6", 1, 1 },
+ { "S_TXFULL", 0, 1 },
+ { "TP_MAC_MATCH_MAP0", 0x138, 0 },
+ { "S_MAPVALUEWR", 16, 8 },
+ { "S_RESERVED", 11, 5 },
+ { "S_MAPINDEX", 2, 9 },
+ { "S_MAPREAD", 1, 1 },
+ { "S_MAPWRITE", 0, 1 },
+ { "TP_MAC_MATCH_MAP1", 0x139, 0 },
+ { "S_RESERVED", 9, 15 },
+ { "S_MAPVALUERD", 0, 9 },
+ { "TP_DBG_ESIDE_DISP2", 0x13A, 0 },
+ { "S_RESRDY", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_FIFOCPL5RXVALID", 27, 1 },
+ { "S_FIFOETHRXVALID", 26, 1 },
+ { "S_FIFOETHRXSOCP", 25, 1 },
+ { "S_FIFOPLDRXZEROP", 24, 1 },
+ { "S_PLDRXVALID", 23, 1 },
+ { "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
+ { "S_FIFOIPRXVALID", 21, 1 },
+ { "S_FIFOTCPRXVALID", 20, 1 },
+ { "S_PLDRXCSUMVALID", 19, 1 },
+ { "S_FIFOIPCSUMSRDY", 18, 1 },
+ { "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
+ { "S_FIFOTCPCSUMSRDY", 16, 1 },
+ { "S_FIFOGRERXVALID", 15, 1 },
+ { "S_FIFOGRERXREADY", 14, 1 },
+ { "S_FIFOGRERXSOCP", 13, 1 },
+ { "S_ESTATIC4", 12, 1 },
+ { "S_FIFOCPLSOCPCNT", 10, 2 },
+ { "S_FIFOETHSOCPCNT", 8, 2 },
+ { "S_FIFOIPSOCPCNT", 6, 2},
+ { "S_FIFOTCPSOCPCNT", 4, 2 },
+ { "S_PLD_RXZEROP_CNT", 2, 2 },
+ { "S_ESTATIC6", 1, 1 },
+ { "S_TXFULL", 0, 1 },
+ { "TP_DBG_ESIDE_DISP3", 0x13B, 0 },
+ { "S_RESRDY", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_FIFOCPL5RXVALID", 27, 1 },
+ { "S_FIFOETHRXVALID", 26, 1 },
+ { "S_FIFOETHRXSOCP", 25, 1 },
+ { "S_FIFOPLDRXZEROP", 24, 1 },
+ { "S_PLDRXVALID", 23, 1 },
+ { "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
+ { "S_FIFOIPRXVALID", 21, 1 },
+ { "S_FIFOTCPRXVALID", 20, 1 },
+ { "S_PLDRXCSUMVALID", 19, 1 },
+ { "S_FIFOIPCSUMSRDY", 18, 1 },
+ { "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
+ { "S_FIFOTCPCSUMSRDY", 16, 1 },
+ { "S_FIFOGRERXVALID", 15, 1 },
+ { "S_FIFOGRERXREADY", 14, 1 },
+ { "S_FIFOGRERXSOCP", 13, 1 },
+ { "S_ESTATIC4", 12, 1 },
+ { "S_FIFOCPLSOCPCNT", 10, 2 },
+ { "S_FIFOETHSOCPCNT", 8, 2 },
+ { "S_FIFOIPSOCPCNT", 6, 2},
+ { "S_FIFOTCPSOCPCNT", 4, 2 },
+ { "S_PLD_RXZEROP_CNT", 2, 2 },
+ { "S_ESTATIC6", 1, 1 },
+ { "S_TXFULL", 0, 1 },
+ { "TP_DBG_ESIDE_HDR0", 0x13C, 0 },
+ { "S_TCPSOPCNT", 28, 4 },
+ { "S_TCPEOPCNT", 24, 4 },
+ { "S_IPSOPCNT", 20, 4 },
+ { "S_IPEOPCNT", 16, 4 },
+ { "S_ETHSOPCNT", 12, 4 },
+ { "S_ETHEOPCNT", 8, 4 },
+ { "S_CPLSOPCNT", 4, 4 },
+ { "S_CPLEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_HDR1", 0x13D, 0 },
+ { "S_TCPSOPCNT", 28, 4 },
+ { "S_TCPEOPCNT", 24, 4 },
+ { "S_IPSOPCNT", 20, 4 },
+ { "S_IPEOPCNT", 16, 4 },
+ { "S_ETHSOPCNT", 12, 4 },
+ { "S_ETHEOPCNT", 8, 4 },
+ { "S_CPLSOPCNT", 4, 4 },
+ { "S_CPLEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_HDR2", 0x13E, 0 },
+ { "S_TCPSOPCNT", 28, 4 },
+ { "S_TCPEOPCNT", 24, 4 },
+ { "S_IPSOPCNT", 20, 4 },
+ { "S_IPEOPCNT", 16, 4 },
+ { "S_ETHSOPCNT", 12, 4 },
+ { "S_ETHEOPCNT", 8, 4 },
+ { "S_CPLSOPCNT", 4, 4 },
+ { "S_CPLEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_HDR3", 0x13F, 0 },
+ { "S_TCPSOPCNT", 28, 4 },
+ { "S_TCPEOPCNT", 24, 4 },
+ { "S_IPSOPCNT", 20, 4 },
+ { "S_IPEOPCNT", 16, 4 },
+ { "S_ETHSOPCNT", 12, 4 },
+ { "S_ETHEOPCNT", 8, 4 },
+ { "S_CPLSOPCNT", 4, 4 },
+ { "S_CPLEOPCNT", 0, 4 },
+ { "TP_VLAN_PRI_MAP", 0x140, 0 },
+ { "S_FILTERMODE", 15, 1 },
+ { "S_FCOEMASK", 14, 1 },
+ { "S_SRVRSRAM", 13, 1 },
+ { "S_FRAGMENTATION", 9, 1 },
+ { "S_MPSHITTYPE", 8, 1 },
+ { "S_MACMATCH", 7, 1 },
+ { "S_ETHERTYPE", 6, 1 },
+ { "S_PROTOCOL", 5, 1 },
+ { "S_TOS", 4, 1},
+ { "S_VLAN", 3, 1 },
+ { "S_VNIC_ID", 2, 1 },
+ { "S_PORT", 1, 1 },
+ { "S_FCOE", 0, 1 },
+ { "TP_INGRESS_CONFIG", 0x141, 0 },
+ { "S_OPAQUE_TYPE", 16, 16 },
+ { "S_OPAQUE_RM", 15, 1 },
+ { "S_OPAQUE_HDR_SIZE", 14, 1},
+ { "S_OPAQUE_RM_MAC_IN_MAC", 13, 1 },
+ { "S_FRAG_LEN_MOD8_COMPAT", 12, 1 },
+ { "S_VNIC", 11, 1 },
+ { "S_CSUM_HAS_PSEUDO_HDR", 10, 1 },
+ { "S_RM_OVLAN", 9, 1 },
+ { "S_LOOKUPEVERYPKT", 8, 1 },
+ { "S_IPV6_EXT_HDR_SKIP", 0, 8 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_145_to_157[] = {
+ { "TP_INGRESS_CONFIG2", 0x145, 0 },
+ { "S_IPV6_UDP_CSUM_COMPAT", 31, 1 },
+ { "S_VNTAGPLDENABLE", 30, 1 },
+ { "S_TCP_PLD_FILTER_OFFSET", 20, 10},
+ { "S_UDP_PLD_FILTER_OFFSET", 10, 10 },
+ { "S_TNL_PLD_FILTER_OFFSET", 0, 10 },
+ { "TP_EHDR_CONFIG_LO", 0x146, 0 },
+ { "S_CPLLIMIT", 24, 8 },
+ { "S_ETHLIMIT", 16, 8 },
+ { "S_IPLIMIT", 8, 8 },
+ { "S_TCPLIMIT", 0, 8 },
+ { "TP_EHDR_CONFIG_HI", 0x147, 0 },
+ { "S_CPLLIMIT", 24, 8 },
+ { "S_ETHLIMIT", 16, 8 },
+ { "S_IPLIMIT", 8, 8 },
+ { "S_TCPLIMIT", 0, 8 },
+ { "TP_DBG_ESIDE_INT", 0x148, 0 },
+ { "S_ERXSOP2X", 28, 4 },
+ { "S_ERXEOP2X", 24, 4 },
+ { "S_ERXVALID2X", 20, 4 },
+ { "S_ERXAFULL2X", 16, 4 },
+ { "S_PLD2XTXVALID", 12, 4 },
+ { "S_PLD2XTXAFULL", 8, 4 },
+ { "S_ERRORSRDY", 7, 1 },
+ { "S_ERRORDRDY", 6, 1 },
+ { "S_TCPOPSRDY", 5, 1 },
+ { "S_TCPOPDRDY", 4, 1 },
+ { "S_PLDTXSRDY", 3, 1 },
+ { "S_PLDTXDRDY", 2, 1 },
+ { "S_TCPOPTTXVALID", 1, 1 },
+ { "S_TCPOPTTXFULL", 0, 1 },
+ { "TP_DBG_ESIDE_DEMUX", 0x149, 0 },
+ { "S_EALLDONE", 28, 4 },
+ { "S_EFIFOPLDDONE", 24, 4 },
+ { "S_EDBDONE", 20, 4 },
+ { "S_EISSFIFODONE", 16, 4 },
+ { "S_EACKERRFIFODONE", 12, 4 },
+ { "S_EFIFOERRORDONE", 8, 4 },
+ { "S_ERXPKTATTRFIFOFDONE", 4, 4 },
+ { "S_ETCPOPDONE", 0, 4 },
+ { "TP_DBG_ESIDE_IN0", 0x14A, 0 },
+ { "S_RXVALID", 31, 1 },
+ { "S_RXFULL", 30, 1 },
+ { "S_RXSOCP", 29, 1 },
+ { "S_RXEOP", 28, 1 },
+ { "S_RXVALID_I", 27, 1 },
+ { "S_RXFULL_I", 26, 1 },
+ { "S_RXRUNT", 25, 1 },
+ { "S_RXRUNTPARSER", 24, 1 },
+ { "S_RXVALID_I2", 23, 1 },
+ { "S_RXFULL_I2", 22, 1 },
+ { "S_RXSOCP_I2", 21, 1 },
+ { "S_RXEOP_I2", 20, 1 },
+ { "S_CT_MPA_TXVALID_FIFO", 19, 1 },
+ { "S_CT_MPA_TXFULL_FIFO", 18, 1 },
+ { "S_CT_MPA_TXVALID", 17, 1 },
+ { "S_CT_MPA_TXFULL", 16, 1 },
+ { "S_RXVALID_BUF", 15, 1 },
+ { "S_RXFULL_BUF", 14, 1 },
+ { "S_PLD_TXVALID", 13, 1 },
+ { "S_PLD_TXFULL", 12, 1 },
+ { "S_ISS_FIFO_SRDY", 11, 1 },
+ { "S_ISS_FIFO_DRDY", 10, 1 },
+ { "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
+ { "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
+ { "S_P2CSUMERROR_SRDY", 7, 1 },
+ { "S_P2CSUMERROR_DRDY", 6, 1 },
+ { "S_ERROR_SRDY", 5, 1 },
+ { "S_ERROR_DRDY", 4, 1 },
+ { "S_PLD_SRDY", 3, 1 },
+ { "S_PLD_DRDY", 2, 1 },
+ { "S_RX_PKT_ATTR_SRDY", 1, 1 },
+ { "S_RX_PKT_ATTR_DRDY", 0, 1 },
+ { "TP_DBG_ESIDE_IN1", 0x14B, 0 },
+ { "S_RXVALID", 31, 1 },
+ { "S_RXFULL", 30, 1 },
+ { "S_RXSOCP", 29, 1 },
+ { "S_RXEOP", 28, 1 },
+ { "S_RXVALID_I", 27, 1 },
+ { "S_RXFULL_I", 26, 1 },
+ { "S_RXRUNT", 25, 1 },
+ { "S_RXRUNTPARSER", 24, 1 },
+ { "S_RXVALID_I2", 23, 1 },
+ { "S_RXFULL_I2", 22, 1 },
+ { "S_RXSOCP_I2", 21, 1 },
+ { "S_RXEOP_I2", 20, 1 },
+ { "S_CT_MPA_TXVALID_FIFO", 19, 1 },
+ { "S_CT_MPA_TXFULL_FIFO", 18, 1 },
+ { "S_CT_MPA_TXVALID", 17, 1 },
+ { "S_CT_MPA_TXFULL", 16, 1 },
+ { "S_RXVALID_BUF", 15, 1 },
+ { "S_RXFULL_BUF", 14, 1 },
+ { "S_PLD_TXVALID", 13, 1 },
+ { "S_PLD_TXFULL", 12, 1 },
+ { "S_ISS_FIFO_SRDY", 11, 1 },
+ { "S_ISS_FIFO_DRDY", 10, 1 },
+ { "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
+ { "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
+ { "S_P2CSUMERROR_SRDY", 7, 1 },
+ { "S_P2CSUMERROR_DRDY", 6, 1 },
+ { "S_ERROR_SRDY", 5, 1 },
+ { "S_ERROR_DRDY", 4, 1 },
+ { "S_PLD_SRDY", 3, 1 },
+ { "S_PLD_DRDY", 2, 1 },
+ { "S_RX_PKT_ATTR_SRDY", 1, 1 },
+ { "S_RX_PKT_ATTR_DRDY", 0, 1 },
+ { "TP_DBG_ESIDE_IN2", 0x14C, 0 },
+ { "S_RXVALID", 31, 1 },
+ { "S_RXFULL", 30, 1 },
+ { "S_RXSOCP", 29, 1 },
+ { "S_RXEOP", 28, 1 },
+ { "S_RXVALID_I", 27, 1 },
+ { "S_RXFULL_I", 26, 1 },
+ { "S_RXRUNT", 25, 1 },
+ { "S_RXRUNTPARSER", 24, 1 },
+ { "S_RXVALID_I2", 23, 1 },
+ { "S_RXFULL_I2", 22, 1 },
+ { "S_RXSOCP_I2", 21, 1 },
+ { "S_RXEOP_I2", 20, 1 },
+ { "S_CT_MPA_TXVALID_FIFO", 19, 1 },
+ { "S_CT_MPA_TXFULL_FIFO", 18, 1 },
+ { "S_CT_MPA_TXVALID", 17, 1 },
+ { "S_CT_MPA_TXFULL", 16, 1 },
+ { "S_RXVALID_BUF", 15, 1 },
+ { "S_RXFULL_BUF", 14, 1 },
+ { "S_PLD_TXVALID", 13, 1 },
+ { "S_PLD_TXFULL", 12, 1 },
+ { "S_ISS_FIFO_SRDY", 11, 1 },
+ { "S_ISS_FIFO_DRDY", 10, 1 },
+ { "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
+ { "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
+ { "S_P2CSUMERROR_SRDY", 7, 1 },
+ { "S_P2CSUMERROR_DRDY", 6, 1 },
+ { "S_ERROR_SRDY", 5, 1 },
+ { "S_ERROR_DRDY", 4, 1 },
+ { "S_PLD_SRDY", 3, 1 },
+ { "S_PLD_DRDY", 2, 1 },
+ { "S_RX_PKT_ATTR_SRDY", 1, 1 },
+ { "S_RX_PKT_ATTR_DRDY", 0, 1 },
+ { "TP_DBG_ESIDE_IN3", 0x14D, 0 },
+ { "S_RXVALID", 31, 1 },
+ { "S_RXFULL", 30, 1 },
+ { "S_RXSOCP", 29, 1 },
+ { "S_RXEOP", 28, 1 },
+ { "S_RXVALID_I", 27, 1 },
+ { "S_RXFULL_I", 26, 1 },
+ { "S_RXRUNT", 25, 1 },
+ { "S_RXRUNTPARSER", 24, 1 },
+ { "S_RXVALID_I2", 23, 1 },
+ { "S_RXFULL_I2", 22, 1 },
+ { "S_RXSOCP_I2", 21, 1 },
+ { "S_RXEOP_I2", 20, 1 },
+ { "S_CT_MPA_TXVALID_FIFO", 19, 1 },
+ { "S_CT_MPA_TXFULL_FIFO", 18, 1 },
+ { "S_CT_MPA_TXVALID", 17, 1 },
+ { "S_CT_MPA_TXFULL", 16, 1 },
+ { "S_RXVALID_BUF", 15, 1 },
+ { "S_RXFULL_BUF", 14, 1 },
+ { "S_PLD_TXVALID", 13, 1 },
+ { "S_PLD_TXFULL", 12, 1 },
+ { "S_ISS_FIFO_SRDY", 11, 1 },
+ { "S_ISS_FIFO_DRDY", 10, 1 },
+ { "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
+ { "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
+ { "S_P2CSUMERROR_SRDY", 7, 1 },
+ { "S_P2CSUMERROR_DRDY", 6, 1 },
+ { "S_ERROR_SRDY", 5, 1 },
+ { "S_ERROR_DRDY", 4, 1 },
+ { "S_PLD_SRDY", 3, 1 },
+ { "S_PLD_DRDY", 2, 1 },
+ { "S_RX_PKT_ATTR_SRDY", 1, 1 },
+ { "S_RX_PKT_ATTR_DRDY", 0, 1 },
+ { "TP_DBG_ESIDE_FRM", 0x14E, 0 },
+ { "S_ERX2XERROR", 28, 4 },
+ { "S_EPLDTX2XERROR", 24, 4 },
+ { "S_ETXERROR", 20, 4 },
+ { "S_EPLDRXERROR", 16, 4 },
+ { "S_ERXSIZEERROR3", 12, 4 },
+ { "S_ERXSIZEERROR2", 8, 4 },
+ { "S_ERXSIZEERROR1", 4, 4 },
+ { "S_ERXSIZEERROR0", 0, 4 },
+ { "TP_DBG_ESIDE_DRP", 0x14F, 0 },
+ { "S_RXDROP3", 24, 8 },
+ { "S_RXDROP2", 16, 8 },
+ { "S_RXDROP1", 8, 8 },
+ { "S_RXDROP0", 0, 8 },
+ { "TP_DBG_ESIDE_TX", 0x150, 0 },
+ { "TXERRORCNT", 8, 24 },
+ { "S_ETXVALID", 4, 4 },
+ { "S_ETXFULL", 0, 4 },
+ { "TP_ESIDE_SVID_MASK", 0x151, 0 },
+ { "TP_ESIDE_DVID_MASK", 0x152, 0 },
+ { "TP_ESIDE_ALIGN_MASK", 0x153, 0 },
+ { "S_USE_LOOP_BIT", 24, 1 },
+ { "S_LOOP_OFFSET", 16, 8 },
+ { "S_DVID_ID_OFFSET", 8, 8 },
+ { "S_SVID_ID_OFFSET", 0, 8 },
+ { "TP_DBG_ESIDE_OP", 0x154, 0 },
+ { "S_RESERVED0", 30, 2 },
+ { "S_OPT_PARSER_FATAL_CHANNEL0", 29, 1 },
+ { "S_OPT_PARSER_BUSY_CHANNEL0", 28, 1 },
+ { "S_OPT_PARSER_ITCP_STATE_CHANNEL0", 26, 2 },
+ { "S_OPT_PARSER_OTK_STATE_CHANNEL0", 24, 2 },
+ { "S_RESERVED1", 22, 2 },
+ { "S_OPT_PARSER_FATAL_CHANNEL1", 21, 1 },
+ { "S_OPT_PARSER_BUSY_CHANNEL1", 20, 1 },
+ { "S_OPT_PARSER_ITCP_STATE_CHANNEL1", 18, 2 },
+ { "S_OPT_PARSER_OTK_STATE_CHANNEL1", 16, 2 },
+ { "S_RESERVED2", 14, 2 },
+ { "S_OPT_PARSER_FATAL_CHANNEL2", 13, 1 },
+ { "S_OPT_PARSER_BUSY_CHANNEL2", 12, 1 },
+ { "S_OPT_PARSER_ITCP_STATE_CHANNEL2", 10, 2 },
+ { "S_OPT_PARSER_OTK_STATE_CHANNEL2", 8, 2 },
+ { "S_RESERVED3", 6, 2 },
+ { "S_OPT_PARSER_FATAL_CHANNEL3", 5, 1 },
+ { "S_OPT_PARSER_BUSY_CHANNEL3", 4, 1 },
+ { "S_OPT_PARSER_ITCP_STATE_CHANNEL3", 2, 2 },
+ { "S_OPT_PARSER_OTK_STATE_CHANNEL3", 0, 2 },
+ { "TP_DBG_ESIDE_OP_ALT", 0x155, 0 },
+ { "S_RESERVED0", 30, 2 },
+ { "S_OPT_PARSER_PSTATE_FATAL_CHANNEL0", 29, 1 },
+ { "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0", 24, 5 },
+ { "S_RESERVED1", 22, 2 },
+ { "S_OPT_PARSER_PSTATE_FATAL_CHANNEL1", 21, 1 },
+ { "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1", 16, 5 },
+ { "S_RESERVED2", 14, 2 },
+ { "S_OPT_PARSER_PSTATE_FATAL_CHANNEL2", 13, 1 },
+ { "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2", 8, 5 },
+ { "S_RESERVED3", 6, 2 },
+ { "S_OPT_PARSER_PSTATE_FATAL_CHANNEL3", 5, 1 },
+ { "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3", 0, 5 },
+ { "TP_DBG_ESIDE_OP_BUSY", 0x156, 0 },
+ { "S_OPT_PARSER_BUSY_VEC_CHANNEL3", 24, 8 },
+ { "S_OPT_PARSER_BUSY_VEC_CHANNEL2", 16, 8 },
+ { "S_OPT_PARSER_BUSY_VEC_CHANNEL1", 8, 8 },
+ { "S_OPT_PARSER_BUSY_VEC_CHANNEL0", 0, 8 },
+ { "TP_DBG_ESIDE_OP_COOKIE", 0x157, 0 },
+ { "S_OPT_PARSER_COOKIE_CHANNEL3", 24, 8 },
+ { "S_OPT_PARSER_COOKIE_CHANNEL2", 16, 8 },
+ { "S_OPT_PARSER_COOKIE_CHANNEL1", 8, 8 },
+ { "S_OPT_PARSER_COOKIE_CHANNEL0", 0, 8 },
+ { NULL }
+
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_160[] = {
+ { "TP_ESIDE_CONFIG", 0x160, 0 },
+ { "VNI_EN", 26, 1 },
+ { "ENC_RX_EN", 25, 1 },
+ { "TNL_LKP_INNER_SEL", 24, 1 },
+ { "AttackFilterEnable", 23, 1 },
+ { "PingDrop", 20, 1 },
+ { "FragmentDrop", 19, 1 },
+ { "RoCEv2UDPPort", 0, 16 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_70_to_75[] = {
+ { "TP_DBG_CACHE_WR_ALL", 0x70, 0 },
+ { "TP_DBG_CACHE_WR_HIT", 0x71, 0 },
+ { "TP_DBG_CACHE_RD_ALL", 0x72, 0 },
+ { "TP_DBG_CACHE_RD_HIT", 0x73, 0 },
+ { "TP_DBG_CACHE_MC_REQ", 0x74, 0 },
+ { "TP_DBG_CACHE_MC_RSP", 0x75, 0 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_pio_regs_6f[] = {
+ { "TP_MIB_DEBUG", 0x6F, 0 },
+ { "S_SRC3", 31, 1 },
+ { "S_LINENUM3", 24, 7 },
+ { "S_SRC2", 23, 1 },
+ { "S_LINENUM2", 16, 7 },
+ { "S_SRC1", 15, 1 },
+ { "S_LINENUM1", 8, 7 },
+ { "S_SRC0", 7, 1 },
+ { "S_LINENUM0", 0, 7 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_pio_regs_120_to_123[] = {
+ { "TP_TX_DROP_CNT_CH0", 0x120, 0 },
+ { "TP_TX_DROP_CNT_CH1", 0x121, 0 },
+ { "TP_TX_DROP_CNT_CH2", 0x122, 0 },
+ { "TP_TX_DROP_CNT_CH3", 0x123, 0 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_pio_regs_12b_to_12c[] = {
+ { "TP_TX_DROP_CFG_CH0", 0x12B, 0 },
+ { "S_TIMERENABLED", 31, 1 },
+ { "S_TIMERERRORENABLE", 30, 1 },
+ { "S_TIMERTHRESHOLD", 4, 26 },
+ { "S_PACKETDROPS", 0, 4 },
+ { "TP_TX_DROP_CFG_CH1", 0x12C, 0 },
+ { "S_TIMERENABLED", 31, 1 },
+ { "S_TIMERERRORENABLE", 30, 1 },
+ { "S_TIMERTHRESHOLD", 4, 26 },
+ { "S_PACKETDROPS", 0, 4 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_pio_regs_12f_to_143[] = {
+ { "TP_TX_DROP_MODE", 0x12F, 0 },
+ { "S_TXDROPMODECH3", 3, 1 },
+ { "S_TXDROPMODECH2", 2, 1 },
+ { "S_TXDROPMODECH1", 1, 1 },
+ { "S_TXDROPMODECH0", 0, 1 },
+ { "TP_DBG_ESIDE_PKT0", 0x130, 0 },
+ { "S_ETXSOPCNT", 28, 4 },
+ { "S_ETXEOPCNT", 24, 4 },
+ { "S_ETXPLDSOPCNT", 20, 4 },
+ { "S_ETXPLDEOPCNT", 16, 4 },
+ { "S_ERXSOPCNT", 12, 4 },
+ { "S_ERXEOPCNT", 8, 4 },
+ { "S_ERXPLDSOPCNT", 4, 4 },
+ { "S_ERXPLDEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_PKT1", 0x131, 0 },
+ { "S_ETXSOPCNT", 28, 4 },
+ { "S_ETXEOPCNT", 24, 4 },
+ { "S_ETXPLDSOPCNT", 20, 4 },
+ { "S_ETXPLDEOPCNT", 16, 4 },
+ { "S_ERXSOPCNT", 12, 4 },
+ { "S_ERXEOPCNT", 8, 4 },
+ { "S_ERXPLDSOPCNT", 4, 4 },
+ { "S_ERXPLDEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_PKT2", 0x132, 0 },
+ { "S_ETXSOPCNT", 28, 4 },
+ { "S_ETXEOPCNT", 24, 4 },
+ { "S_ETXPLDSOPCNT", 20, 4 },
+ { "S_ETXPLDEOPCNT", 16, 4 },
+ { "S_ERXSOPCNT", 12, 4 },
+ { "S_ERXEOPCNT", 8, 4 },
+ { "S_ERXPLDSOPCNT", 4, 4 },
+ { "S_ERXPLDEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_PKT3", 0x133, 0 },
+ { "S_ETXSOPCNT", 28, 4 },
+ { "S_ETXEOPCNT", 24, 4 },
+ { "S_ETXPLDSOPCNT", 20, 4 },
+ { "S_ETXPLDEOPCNT", 16, 4 },
+ { "S_ERXSOPCNT", 12, 4 },
+ { "S_ERXEOPCNT", 8, 4 },
+ { "S_ERXPLDSOPCNT", 4, 4 },
+ { "S_ERXPLDEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_FIFO0", 0x134, 0 },
+ { "S_PLDRXCSUMVALID1", 31, 1 },
+ { "S_PLDRXZEROPSRDY1", 30, 1 },
+ { "S_PLDRXVALID1", 29, 1 },
+ { "S_TCPRXVALID1", 28, 1 },
+ { "S_IPRXVALID1", 27, 1 },
+ { "S_ETHRXVALID1", 26, 1 },
+ { "S_CPLRXVALID1", 25, 1 },
+ { "S_FSTATIC1", 24, 1 },
+ { "S_ERRORSRDY1", 23, 1 },
+ { "S_PLDTXSRDY1", 22, 1 },
+ { "S_DBVLD1", 21, 1 },
+ { "S_PLDTXVALID1", 20, 1 },
+ { "S_ETXVALID1", 19, 1 },
+ { "S_ETXFULL1", 18, 1 },
+ { "S_ERXVALID1", 17, 1 },
+ { "S_ERXFULL1", 16, 1 },
+ { "S_PLDRXCSUMVALID0", 15, 1 },
+ { "S_PLDRXZEROPSRDY0", 14, 1},
+ { "S_PLDRXVALID0", 13, 1 },
+ { "S_TCPRXVALID0", 12, 1 },
+ { "S_IPRXVALID0", 11, 1 },
+ { "S_ETHRXVALID0", 10, 1 },
+ { "S_CPLRXVALID0", 9, 1 },
+ { "S_FSTATIC0", 8, 1 },
+ { "S_ERRORSRDY0", 7, 1 },
+ { "S_PLDTXSRDY0", 6, 1 },
+ { "S_DBVLD0", 5, 1 },
+ { "S_PLDTXVALID0", 4, 1 },
+ { "S_ETXVALID0", 3, 1 },
+ { "S_ETXFULL0", 2, 1 },
+ { "S_ERXVALID0", 1, 1 },
+ { "S_ERXFULL0", 0, 1 },
+ { "TP_DBG_ESIDE_FIFO1", 0x135, 0 },
+ { "S_PLDRXCSUMVALID3", 31, 1 },
+ { "S_PLDRXZEROPSRDY3", 30, 1 },
+ { "S_PLDRXVALID3", 29, 1 },
+ { "S_TCPRXVALID3", 28, 1 },
+ { "S_IPRXVALID3", 27, 1 },
+ { "S_ETHRXVALID3", 26, 1 },
+ { "S_CPLRXVALID3", 25, 1 },
+ { "S_FSTATIC3", 24, 1 },
+ { "S_ERRORSRDY3", 23, 1 },
+ { "S_PLDTXSRDY3", 22, 1 },
+ { "S_DBVLD3", 21, 1 },
+ { "S_PLDTXVALID3", 20, 1 },
+ { "S_ETXVALID3", 19, 1 },
+ { "S_ETXFULL3", 18, 1 },
+ { "S_ERXVALID3", 17, 1 },
+ { "S_ERXFULL3", 16, 1 },
+ { "S_PLDRXCSUMVALID2", 15, 1 },
+ { "S_PLDRXZEROPSRDY2", 14, 1},
+ { "S_PLDRXVALID2", 13, 1 },
+ { "S_TCPRXVALID2", 12, 1 },
+ { "S_IPRXVALID2", 11, 1 },
+ { "S_ETHRXVALID2", 10, 1 },
+ { "S_CPLRXVALID2", 9, 1 },
+ { "S_FSTATIC2", 8, 1 },
+ { "S_ERRORSRDY2", 7, 1 },
+ { "S_PLDTXSRDY2", 6, 1 },
+ { "S_DBVLD2", 5, 1 },
+ { "S_PLDTXVALID2", 4, 1 },
+ { "S_ETXVALID2", 3, 1 },
+ { "S_ETXFULL2", 2, 1 },
+ { "S_ERXVALID2", 1, 1 },
+ { "S_ERXFULL2", 0, 1 },
+ { "TP_DBG_ESIDE_DISP0", 0x136, 0 },
+ { "S_RESRDY", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_FIFOCPL5RXVALID", 27, 1 },
+ { "S_FIFOETHRXVALID", 26, 1 },
+ { "S_FIFOETHRXSOCP", 25, 1 },
+ { "S_FIFOPLDRXZEROP", 24, 1 },
+ { "S_PLDRXVALID", 23, 1 },
+ { "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
+ { "S_FIFOIPRXVALID", 21, 1 },
+ { "S_FIFOTCPRXVALID", 20, 1 },
+ { "S_PLDRXCSUMVALID", 19, 1 },
+ { "S_FIFOIPCSUMSRDY", 18, 1 },
+ { "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
+ { "S_FIFOTCPCSUMSRDY", 16, 1 },
+ { "S_ESTATIC4", 12, 4 },
+ { "S_FIFOCPLSOCPCNT", 10, 2 },
+ { "S_FIFOETHSOCPCNT", 8, 2 },
+ { "S_FIFOIPSOCPCNT", 6, 2},
+ { "S_FIFOTCPSOCPCNT", 4, 2 },
+ { "S_PLD_RXZEROP_CNT", 2, 2 },
+ { "S_ESTATIC6", 1, 1 },
+ { "S_TXFULL", 0, 1 },
+ { "TP_DBG_ESIDE_DISP1", 0x137, 0 },
+ { "S_RESRDY", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_FIFOCPL5RXVALID", 27, 1 },
+ { "S_FIFOETHRXVALID", 26, 1 },
+ { "S_FIFOETHRXSOCP", 25, 1 },
+ { "S_FIFOPLDRXZEROP", 24, 1 },
+ { "S_PLDRXVALID", 23, 1 },
+ { "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
+ { "S_FIFOIPRXVALID", 21, 1 },
+ { "S_FIFOTCPRXVALID", 20, 1 },
+ { "S_PLDRXCSUMVALID", 19, 1 },
+ { "S_FIFOIPCSUMSRDY", 18, 1 },
+ { "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
+ { "S_FIFOTCPCSUMSRDY", 16, 1 },
+ { "S_ESTATIC4", 12, 4 },
+ { "S_FIFOCPLSOCPCNT", 10, 2 },
+ { "S_FIFOETHSOCPCNT", 8, 2 },
+ { "S_FIFOIPSOCPCNT", 6, 2},
+ { "S_FIFOTCPSOCPCNT", 4, 2 },
+ { "S_PLD_RXZEROP_CNT", 2, 2 },
+ { "S_ESTATIC6", 1, 1 },
+ { "S_TXFULL", 0, 1 },
+ { "TP_MAC_MATCH_MAP0", 0x138, 0 },
+ { "S_MAPVALUEWR", 16, 8 },
+ { "S_RESERVED", 11, 5 },
+ { "S_MAPINDEX", 2, 9 },
+ { "S_MAPREAD", 1, 1 },
+ { "S_MAPWRITE", 0, 1 },
+ { "TP_MAC_MATCH_MAP1", 0x139, 0 },
+ { "S_RESERVED", 9, 15 },
+ { "S_MAPVALUERD", 0, 9 },
+ { "TP_DBG_ESIDE_DISP2", 0x13A, 0 },
+ { "S_RESRDY", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_FIFOCPL5RXVALID", 27, 1 },
+ { "S_FIFOETHRXVALID", 26, 1 },
+ { "S_FIFOETHRXSOCP", 25, 1 },
+ { "S_FIFOPLDRXZEROP", 24, 1 },
+ { "S_PLDRXVALID", 23, 1 },
+ { "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
+ { "S_FIFOIPRXVALID", 21, 1 },
+ { "S_FIFOTCPRXVALID", 20, 1 },
+ { "S_PLDRXCSUMVALID", 19, 1 },
+ { "S_FIFOIPCSUMSRDY", 18, 1 },
+ { "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
+ { "S_FIFOTCPCSUMSRDY", 16, 1 },
+ { "S_ESTATIC4", 12, 4 },
+ { "S_FIFOCPLSOCPCNT", 10, 2 },
+ { "S_FIFOETHSOCPCNT", 8, 2 },
+ { "S_FIFOIPSOCPCNT", 6, 2},
+ { "S_FIFOTCPSOCPCNT", 4, 2 },
+ { "S_PLD_RXZEROP_CNT", 2, 2 },
+ { "S_ESTATIC6", 1, 1 },
+ { "S_TXFULL", 0, 1 },
+ { "TP_DBG_ESIDE_DISP3", 0x13B, 0 },
+ { "S_RESRDY", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_FIFOCPL5RXVALID", 27, 1 },
+ { "S_FIFOETHRXVALID", 26, 1 },
+ { "S_FIFOETHRXSOCP", 25, 1 },
+ { "S_FIFOPLDRXZEROP", 24, 1 },
+ { "S_PLDRXVALID", 23, 1 },
+ { "S_FIFOPLDRXZEROP_SRDY", 22, 1 },
+ { "S_FIFOIPRXVALID", 21, 1 },
+ { "S_FIFOTCPRXVALID", 20, 1 },
+ { "S_PLDRXCSUMVALID", 19, 1 },
+ { "S_FIFOIPCSUMSRDY", 18, 1 },
+ { "S_FIFOIPPSEUDOCSUMSRDY", 17, 1 },
+ { "S_FIFOTCPCSUMSRDY", 16, 1 },
+ { "S_ESTATIC4", 12, 4 },
+ { "S_FIFOCPLSOCPCNT", 10, 2 },
+ { "S_FIFOETHSOCPCNT", 8, 2 },
+ { "S_FIFOIPSOCPCNT", 6, 2},
+ { "S_FIFOTCPSOCPCNT", 4, 2 },
+ { "S_PLD_RXZEROP_CNT", 2, 2 },
+ { "S_ESTATIC6", 1, 1 },
+ { "S_TXFULL", 0, 1 },
+ { "TP_DBG_ESIDE_HDR0", 0x13C, 0 },
+ { "S_TCPSOPCNT", 28, 4 },
+ { "S_TCPEOPCNT", 24, 4 },
+ { "S_IPSOPCNT", 20, 4 },
+ { "S_IPEOPCNT", 16, 4 },
+ { "S_ETHSOPCNT", 12, 4 },
+ { "S_ETHEOPCNT", 8, 4 },
+ { "S_CPLSOPCNT", 4, 4 },
+ { "S_CPLEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_HDR1", 0x13D, 0 },
+ { "S_TCPSOPCNT", 28, 4 },
+ { "S_TCPEOPCNT", 24, 4 },
+ { "S_IPSOPCNT", 20, 4 },
+ { "S_IPEOPCNT", 16, 4 },
+ { "S_ETHSOPCNT", 12, 4 },
+ { "S_ETHEOPCNT", 8, 4 },
+ { "S_CPLSOPCNT", 4, 4 },
+ { "S_CPLEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_HDR2", 0x13E, 0 },
+ { "S_TCPSOPCNT", 28, 4 },
+ { "S_TCPEOPCNT", 24, 4 },
+ { "S_IPSOPCNT", 20, 4 },
+ { "S_IPEOPCNT", 16, 4 },
+ { "S_ETHSOPCNT", 12, 4 },
+ { "S_ETHEOPCNT", 8, 4 },
+ { "S_CPLSOPCNT", 4, 4 },
+ { "S_CPLEOPCNT", 0, 4 },
+ { "TP_DBG_ESIDE_HDR3", 0x13F, 0 },
+ { "S_TCPSOPCNT", 28, 4 },
+ { "S_TCPEOPCNT", 24, 4 },
+ { "S_IPSOPCNT", 20, 4 },
+ { "S_IPEOPCNT", 16, 4 },
+ { "S_ETHSOPCNT", 12, 4 },
+ { "S_ETHEOPCNT", 8, 4 },
+ { "S_CPLSOPCNT", 4, 4 },
+ { "S_CPLEOPCNT", 0, 4 },
+ { "TP_VLAN_PRI_MAP", 0x140, 0 },
+ { "S_FILTERMODE", 15, 1 },
+ { "S_FCOEMASK", 14, 1 },
+ { "S_SRVRSRAM", 13, 1 },
+ { "S_FRAGMENTATION", 9, 1 },
+ { "S_MPSHITTYPE", 8, 1 },
+ { "S_MACMATCH", 7, 1 },
+ { "S_ETHERTYPE", 6, 1 },
+ { "S_PROTOCOL", 5, 1 },
+ { "S_TOS", 4, 1},
+ { "S_VLAN", 3, 1 },
+ { "S_VNIC_ID", 2, 1 },
+ { "S_PORT", 1, 1 },
+ { "S_FCOE", 0, 1 },
+ { "TP_INGRESS_CONFIG", 0x141, 0 },
+ { "S_OPAQUE_TYPE", 16, 16 },
+ { "S_OPAQUE_RM", 15, 1 },
+ { "S_OPAQUE_HDR_SIZE", 14, 1},
+ { "S_OPAQUE_RM_MAC_IN_MAC", 13, 1 },
+ { "S_FRAG_LEN_MOD8_COMPAT", 12, 1 },
+ { "S_VNIC", 11, 1 },
+ { "S_CSUM_HAS_PSEUDO_HDR", 10, 1 },
+ { "S_RM_OVLAN", 9, 1 },
+ { "S_LOOKUPEVERYPKT", 8, 1 },
+ { "S_IPV6_EXT_HDR_SKIP", 0, 8 },
+ { "TP_TX_DROP_CFG_CH2", 0x142, 0 },
+ { "S_TIMERENABLED", 31, 1 },
+ { "S_TIMERERRORENABLE", 30, 1 },
+ { "S_TIMERTHRESHOLD", 4, 26 },
+ { "S_PACKETDROPS", 0, 4 },
+ { "TP_TX_DROP_CFG_CH3", 0x143, 0 },
+ { "S_TIMERENABLED", 31, 1 },
+ { "S_TIMERERRORENABLE", 30, 1 },
+ { "S_TIMERTHRESHOLD", 4, 26 },
+ { "S_PACKETDROPS", 0, 4 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_pio_regs_145_to_157[] = {
+ { "TP_INGRESS_CONFIG2", 0x145, 0 },
+ { "S_IPV6_UDP_CSUM_COMPAT", 31, 1 },
+ { "S_VNTAGPLDENABLE", 30, 1 },
+ { "S_TCP_PLD_FILTER_OFFSET", 20, 10},
+ { "S_UDP_PLD_FILTER_OFFSET", 10, 10 },
+ { "S_TNL_PLD_FILTER_OFFSET", 0, 10 },
+ { "TP_EHDR_CONFIG_LO", 0x146, 0 },
+ { "S_CPLLIMIT", 24, 8 },
+ { "S_ETHLIMIT", 16, 8 },
+ { "S_IPLIMIT", 8, 8 },
+ { "S_TCPLIMIT", 0, 8 },
+ { "TP_EHDR_CONFIG_HI", 0x147, 0 },
+ { "S_CPLLIMIT", 24, 8 },
+ { "S_ETHLIMIT", 16, 8 },
+ { "S_IPLIMIT", 8, 8 },
+ { "S_TCPLIMIT", 0, 8 },
+ { "TP_DBG_ESIDE_INT", 0x148, 0 },
+ { "S_ERXSOP2X", 28, 4 },
+ { "S_ERXEOP2X", 24, 4 },
+ { "S_ERXVALID2X", 20, 4 },
+ { "S_ERXAFULL2X", 16, 4 },
+ { "S_PLD2XTXVALID", 12, 4 },
+ { "S_PLD2XTXAFULL", 8, 4 },
+ { "S_ERRORSRDY", 7, 1 },
+ { "S_ERRORDRDY", 6, 1 },
+ { "S_TCPOPSRDY", 5, 1 },
+ { "S_TCPOPDRDY", 4, 1 },
+ { "S_PLDTXSRDY", 3, 1 },
+ { "S_PLDTXDRDY", 2, 1 },
+ { "S_TCPOPTTXVALID", 1, 1 },
+ { "S_TCPOPTTXFULL", 0, 1 },
+ { "TP_DBG_ESIDE_DEMUX", 0x149, 0 },
+ { "S_EALLDONE", 28, 4 },
+ { "S_EFIFOPLDDONE", 24, 4 },
+ { "S_EDBDONE", 20, 4 },
+ { "S_EISSFIFODONE", 16, 4 },
+ { "S_EACKERRFIFODONE", 12, 4 },
+ { "S_EFIFOERRORDONE", 8, 4 },
+ { "S_ERXPKTATTRFIFOFDONE", 4, 4 },
+ { "S_ETCPOPDONE", 0, 4 },
+ { "TP_DBG_ESIDE_IN0", 0x14A, 0 },
+ { "S_RXVALID", 31, 1 },
+ { "S_RXFULL", 30, 1 },
+ { "S_RXSOCP", 29, 1 },
+ { "S_RXEOP", 28, 1 },
+ { "S_RXVALID_I", 27, 1 },
+ { "S_RXFULL_I", 26, 1 },
+ { "S_RXRUNT", 25, 1 },
+ { "S_RXRUNTPARSER", 24, 1 },
+ { "S_RXVALID_I2", 23, 1 },
+ { "S_RXFULL_I2", 22, 1 },
+ { "S_RXSOCP_I2", 21, 1 },
+ { "S_RXEOP_I2", 20, 1 },
+ { "S_CT_MPA_TXVALID_FIFO", 19, 1 },
+ { "S_CT_MPA_TXFULL_FIFO", 18, 1 },
+ { "S_CT_MPA_TXVALID", 17, 1 },
+ { "S_CT_MPA_TXFULL", 16, 1 },
+ { "S_RXVALID_BUF", 15, 1 },
+ { "S_RXFULL_BUF", 14, 1 },
+ { "S_PLD_TXVALID", 13, 1 },
+ { "S_PLD_TXFULL", 12, 1 },
+ { "S_ISS_FIFO_SRDY", 11, 1 },
+ { "S_ISS_FIFO_DRDY", 10, 1 },
+ { "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
+ { "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
+ { "S_P2CSUMERROR_SRDY", 7, 1 },
+ { "S_P2CSUMERROR_DRDY", 6, 1 },
+ { "S_ERROR_SRDY", 5, 1 },
+ { "S_ERROR_DRDY", 4, 1 },
+ { "S_PLD_SRDY", 3, 1 },
+ { "S_PLD_DRDY", 2, 1 },
+ { "S_RX_PKT_ATTR_SRDY", 1, 1 },
+ { "S_RX_PKT_ATTR_DRDY", 0, 1 },
+ { "TP_DBG_ESIDE_IN1", 0x14B, 0 },
+ { "S_RXVALID", 31, 1 },
+ { "S_RXFULL", 30, 1 },
+ { "S_RXSOCP", 29, 1 },
+ { "S_RXEOP", 28, 1 },
+ { "S_RXVALID_I", 27, 1 },
+ { "S_RXFULL_I", 26, 1 },
+ { "S_RXRUNT", 25, 1 },
+ { "S_RXRUNTPARSER", 24, 1 },
+ { "S_RXVALID_I2", 23, 1 },
+ { "S_RXFULL_I2", 22, 1 },
+ { "S_RXSOCP_I2", 21, 1 },
+ { "S_RXEOP_I2", 20, 1 },
+ { "S_CT_MPA_TXVALID_FIFO", 19, 1 },
+ { "S_CT_MPA_TXFULL_FIFO", 18, 1 },
+ { "S_CT_MPA_TXVALID", 17, 1 },
+ { "S_CT_MPA_TXFULL", 16, 1 },
+ { "S_RXVALID_BUF", 15, 1 },
+ { "S_RXFULL_BUF", 14, 1 },
+ { "S_PLD_TXVALID", 13, 1 },
+ { "S_PLD_TXFULL", 12, 1 },
+ { "S_ISS_FIFO_SRDY", 11, 1 },
+ { "S_ISS_FIFO_DRDY", 10, 1 },
+ { "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
+ { "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
+ { "S_P2CSUMERROR_SRDY", 7, 1 },
+ { "S_P2CSUMERROR_DRDY", 6, 1 },
+ { "S_ERROR_SRDY", 5, 1 },
+ { "S_ERROR_DRDY", 4, 1 },
+ { "S_PLD_SRDY", 3, 1 },
+ { "S_PLD_DRDY", 2, 1 },
+ { "S_RX_PKT_ATTR_SRDY", 1, 1 },
+ { "S_RX_PKT_ATTR_DRDY", 0, 1 },
+ { "TP_DBG_ESIDE_IN2", 0x14C, 0 },
+ { "S_RXVALID", 31, 1 },
+ { "S_RXFULL", 30, 1 },
+ { "S_RXSOCP", 29, 1 },
+ { "S_RXEOP", 28, 1 },
+ { "S_RXVALID_I", 27, 1 },
+ { "S_RXFULL_I", 26, 1 },
+ { "S_RXRUNT", 25, 1 },
+ { "S_RXRUNTPARSER", 24, 1 },
+ { "S_RXVALID_I2", 23, 1 },
+ { "S_RXFULL_I2", 22, 1 },
+ { "S_RXSOCP_I2", 21, 1 },
+ { "S_RXEOP_I2", 20, 1 },
+ { "S_CT_MPA_TXVALID_FIFO", 19, 1 },
+ { "S_CT_MPA_TXFULL_FIFO", 18, 1 },
+ { "S_CT_MPA_TXVALID", 17, 1 },
+ { "S_CT_MPA_TXFULL", 16, 1 },
+ { "S_RXVALID_BUF", 15, 1 },
+ { "S_RXFULL_BUF", 14, 1 },
+ { "S_PLD_TXVALID", 13, 1 },
+ { "S_PLD_TXFULL", 12, 1 },
+ { "S_ISS_FIFO_SRDY", 11, 1 },
+ { "S_ISS_FIFO_DRDY", 10, 1 },
+ { "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
+ { "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
+ { "S_P2CSUMERROR_SRDY", 7, 1 },
+ { "S_P2CSUMERROR_DRDY", 6, 1 },
+ { "S_ERROR_SRDY", 5, 1 },
+ { "S_ERROR_DRDY", 4, 1 },
+ { "S_PLD_SRDY", 3, 1 },
+ { "S_PLD_DRDY", 2, 1 },
+ { "S_RX_PKT_ATTR_SRDY", 1, 1 },
+ { "S_RX_PKT_ATTR_DRDY", 0, 1 },
+ { "TP_DBG_ESIDE_IN3", 0x14D, 0 },
+ { "S_RXVALID", 31, 1 },
+ { "S_RXFULL", 30, 1 },
+ { "S_RXSOCP", 29, 1 },
+ { "S_RXEOP", 28, 1 },
+ { "S_RXVALID_I", 27, 1 },
+ { "S_RXFULL_I", 26, 1 },
+ { "S_RXRUNT", 25, 1 },
+ { "S_RXRUNTPARSER", 24, 1 },
+ { "S_RXVALID_I2", 23, 1 },
+ { "S_RXFULL_I2", 22, 1 },
+ { "S_RXSOCP_I2", 21, 1 },
+ { "S_RXEOP_I2", 20, 1 },
+ { "S_CT_MPA_TXVALID_FIFO", 19, 1 },
+ { "S_CT_MPA_TXFULL_FIFO", 18, 1 },
+ { "S_CT_MPA_TXVALID", 17, 1 },
+ { "S_CT_MPA_TXFULL", 16, 1 },
+ { "S_RXVALID_BUF", 15, 1 },
+ { "S_RXFULL_BUF", 14, 1 },
+ { "S_PLD_TXVALID", 13, 1 },
+ { "S_PLD_TXFULL", 12, 1 },
+ { "S_ISS_FIFO_SRDY", 11, 1 },
+ { "S_ISS_FIFO_DRDY", 10, 1 },
+ { "S_CT_TCP_OP_ISS_SRDY", 9, 1 },
+ { "S_CT_TCP_OP_ISS_DRDY", 8, 1 },
+ { "S_P2CSUMERROR_SRDY", 7, 1 },
+ { "S_P2CSUMERROR_DRDY", 6, 1 },
+ { "S_ERROR_SRDY", 5, 1 },
+ { "S_ERROR_DRDY", 4, 1 },
+ { "S_PLD_SRDY", 3, 1 },
+ { "S_PLD_DRDY", 2, 1 },
+ { "S_RX_PKT_ATTR_SRDY", 1, 1 },
+ { "S_RX_PKT_ATTR_DRDY", 0, 1 },
+ { "TP_DBG_ESIDE_FRM", 0x14E, 0 },
+ { "S_ERX2XERROR", 28, 4 },
+ { "S_EPLDTX2XERROR", 24, 4 },
+ { "S_ETXERROR", 20, 4 },
+ { "S_EPLDRXERROR", 16, 4 },
+ { "S_ERXSIZEERROR3", 12, 4 },
+ { "S_ERXSIZEERROR2", 8, 4 },
+ { "S_ERXSIZEERROR1", 4, 4 },
+ { "S_ERXSIZEERROR0", 0, 4 },
+ { "TP_DBG_ESIDE_DRP", 0x14F, 0 },
+ { "S_RXDROP3", 24, 8 },
+ { "S_RXDROP2", 16, 8 },
+ { "S_RXDROP1", 8, 8 },
+ { "S_RXDROP0", 0, 8 },
+ { "TP_DBG_ESIDE_TX", 0x150, 0 },
+ { "S_ETXVALID", 4, 4 },
+ { "S_ETXFULL", 0, 4 },
+ { "TP_ESIDE_SVID_MASK", 0x151, 0 },
+ { "TP_ESIDE_DVID_MASK", 0x152, 0 },
+ { "TP_ESIDE_ALIGN_MASK", 0x153, 0 },
+ { "S_USE_LOOP_BIT", 24, 1 },
+ { "S_LOOP_OFFSET", 16, 8 },
+ { "S_DVID_ID_OFFSET", 8, 8 },
+ { "S_SVID_ID_OFFSET", 0, 8 },
+ { "TP_DBG_ESIDE_OP", 0x154, 0 },
+ { "S_RESERVED0", 30, 2 },
+ { "S_OPT_PARSER_FATAL_CHANNEL0", 29, 1 },
+ { "S_OPT_PARSER_BUSY_CHANNEL0", 28, 1 },
+ { "S_OPT_PARSER_ITCP_STATE_CHANNEL0", 26, 2 },
+ { "S_OPT_PARSER_OTK_STATE_CHANNEL0", 24, 2 },
+ { "S_RESERVED1", 22, 2 },
+ { "S_OPT_PARSER_FATAL_CHANNEL1", 21, 1 },
+ { "S_OPT_PARSER_BUSY_CHANNEL1", 20, 1 },
+ { "S_OPT_PARSER_ITCP_STATE_CHANNEL1", 18, 2 },
+ { "S_OPT_PARSER_OTK_STATE_CHANNEL1", 16, 2 },
+ { "S_RESERVED2", 14, 2 },
+ { "S_OPT_PARSER_FATAL_CHANNEL2", 13, 1 },
+ { "S_OPT_PARSER_BUSY_CHANNEL2", 12, 1 },
+ { "S_OPT_PARSER_ITCP_STATE_CHANNEL2", 10, 2 },
+ { "S_OPT_PARSER_OTK_STATE_CHANNEL2", 8, 2 },
+ { "S_RESERVED3", 6, 2 },
+ { "S_OPT_PARSER_FATAL_CHANNEL3", 5, 1 },
+ { "S_OPT_PARSER_BUSY_CHANNEL3", 4, 1 },
+ { "S_OPT_PARSER_ITCP_STATE_CHANNEL3", 2, 2 },
+ { "S_OPT_PARSER_OTK_STATE_CHANNEL3", 0, 2 },
+ { "TP_DBG_ESIDE_OP_ALT", 0x155, 0 },
+ { "S_RESERVED0", 30, 2 },
+ { "S_OPT_PARSER_PSTATE_FATAL_CHANNEL0", 29, 1 },
+ { "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0", 24, 5 },
+ { "S_RESERVED1", 22, 2 },
+ { "S_OPT_PARSER_PSTATE_FATAL_CHANNEL1", 21, 1 },
+ { "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1", 16, 5 },
+ { "S_RESERVED2", 14, 2 },
+ { "S_OPT_PARSER_PSTATE_FATAL_CHANNEL2", 13, 1 },
+ { "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2", 8, 5 },
+ { "S_RESERVED3", 6, 2 },
+ { "S_OPT_PARSER_PSTATE_FATAL_CHANNEL3", 5, 1 },
+ { "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3", 0, 5 },
+ { "TP_DBG_ESIDE_OP_BUSY", 0x156, 0 },
+ { "S_OPT_PARSER_BUSY_VEC_CHANNEL3", 24, 8 },
+ { "S_OPT_PARSER_BUSY_VEC_CHANNEL2", 16, 8 },
+ { "S_OPT_PARSER_BUSY_VEC_CHANNEL1", 8, 8 },
+ { "S_OPT_PARSER_BUSY_VEC_CHANNEL0", 0, 8 },
+ { "TP_DBG_ESIDE_OP_COOKIE", 0x157, 0 },
+ { "S_OPT_PARSER_COOKIE_CHANNEL3", 24, 8 },
+ { "S_OPT_PARSER_COOKIE_CHANNEL2", 16, 8 },
+ { "S_OPT_PARSER_COOKIE_CHANNEL1", 8, 8 },
+ { "S_OPT_PARSER_COOKIE_CHANNEL0", 0, 8 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_230_to_248[] = {
+ { "TP_DBG_CSIDE_RX0", 0x230, 0 },
+ { "S_CRXSOPCNT", 28, 4 },
+ { "S_CRXEOPCNT", 24, 4 },
+ { "S_CRXPLDSOPCNT", 20, 4 },
+ { "S_CRXPLDEOPCNT", 16, 4 },
+ { "S_CRXARBSOPCNT", 12, 4 },
+ { "S_CRXARBEOPCNT", 8, 4 },
+ { "S_CRXCPLSOPCNT", 4, 4 },
+ { "S_CRXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_RX1", 0x231, 0 },
+ { "S_CRXSOPCNT", 28, 4 },
+ { "S_CRXEOPCNT", 24, 4 },
+ { "S_CRXPLDSOPCNT", 20, 4 },
+ { "S_CRXPLDEOPCNT", 16, 4 },
+ { "S_CRXARBSOPCNT", 12, 4 },
+ { "S_CRXARBEOPCNT", 8, 4 },
+ { "S_CRXCPLSOPCNT", 4, 4 },
+ { "S_CRXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_RX2", 0x232, 0 },
+ { "S_CRXSOPCNT", 28, 4 },
+ { "S_CRXEOPCNT", 24, 4 },
+ { "S_CRXPLDSOPCNT", 20, 4 },
+ { "S_CRXPLDEOPCNT", 16, 4 },
+ { "S_CRXARBSOPCNT", 12, 4 },
+ { "S_CRXARBEOPCNT", 8, 4 },
+ { "S_CRXCPLSOPCNT", 4, 4 },
+ { "S_CRXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_RX3", 0x233, 0 },
+ { "S_CRXSOPCNT", 28, 4 },
+ { "S_CRXEOPCNT", 24, 4 },
+ { "S_CRXPLDSOPCNT", 20, 4 },
+ { "S_CRXPLDEOPCNT", 16, 4 },
+ { "S_CRXARBSOPCNT", 12, 4 },
+ { "S_CRXARBEOPCNT", 8, 4 },
+ { "S_CRXCPLSOPCNT", 4, 4 },
+ { "S_CRXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_TX0", 0x234, 0 },
+ { "S_TXSOPCNT", 28, 4 },
+ { "S_TXEOPCNT", 24, 4 },
+ { "S_TXPLDSOPCNT", 20, 4 },
+ { "S_TXPLDEOPCNT", 16, 4 },
+ { "S_TXARBSOPCNT", 12, 4 },
+ { "S_TXARBEOPCNT", 8, 4 },
+ { "S_TXCPLSOPCNT", 4, 4 },
+ { "S_TXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_TX1", 0x235, 0 },
+ { "S_TXSOPCNT", 28, 4 },
+ { "S_TXEOPCNT", 24, 4 },
+ { "S_TXPLDSOPCNT", 20, 4 },
+ { "S_TXPLDEOPCNT", 16, 4 },
+ { "S_TXARBSOPCNT", 12, 4 },
+ { "S_TXARBEOPCNT", 8, 4 },
+ { "S_TXCPLSOPCNT", 4, 4 },
+ { "S_TXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_TX2", 0x236, 0 },
+ { "S_TXSOPCNT", 28, 4 },
+ { "S_TXEOPCNT", 24, 4 },
+ { "S_TXPLDSOPCNT", 20, 4 },
+ { "S_TXPLDEOPCNT", 16, 4 },
+ { "S_TXARBSOPCNT", 12, 4 },
+ { "S_TXARBEOPCNT", 8, 4 },
+ { "S_TXCPLSOPCNT", 4, 4 },
+ { "S_TXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_TX3", 0x237, 0 },
+ { "S_TXSOPCNT", 28, 4 },
+ { "S_TXEOPCNT", 24, 4 },
+ { "S_TXPLDSOPCNT", 20, 4 },
+ { "S_TXPLDEOPCNT", 16, 4 },
+ { "S_TXARBSOPCNT", 12, 4 },
+ { "S_TXARBEOPCNT", 8, 4 },
+ { "S_TXCPLSOPCNT", 4, 4 },
+ { "S_TXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_FIFO0", 0x238, 0 },
+ { "S_PLD_RXZEROP_SRDY1", 31, 1 },
+ { "S_PLD_RXZEROP_DRDY1", 30, 1 },
+ { "S_PLD_TXZEROP_SRDY1", 29, 1 },
+ { "S_PLD_TXZEROP_DRDY1", 28, 1 },
+ { "S_PLD_TX_SRDY1", 27, 1 },
+ { "S_PLD_TX_DRDY1", 26, 1 },
+ { "S_ERROR_SRDY1", 25, 1 },
+ { "S_ERROR_DRDY1", 24, 1 },
+ { "S_DB_VLD1", 23, 1 },
+ { "S_DB_GT1", 22, 1 },
+ { "S_TXVALID1", 21, 1 },
+ { "S_TXFULL1", 20, 1 },
+ { "S_PLD_TXVALID1", 19 , 1 },
+ { "S_PLD_TXFULL1", 18, 1 },
+ { "S_CPL5_TXVALID1", 17, 1 },
+ { "S_CPL5_TXFULL1", 16, 1 },
+ { "S_PLD_RXZEROP_SRDY0", 15, 1 },
+ { "S_PLD_RXZEROP_DRDY0", 14, 1 },
+ { "S_PLD_TXZEROP_SRDY0", 13, 1 },
+ { "S_PLD_TXZEROP_DRDY0", 12, 1 },
+ { "S_PLD_TX_SRDY0", 11, 1 },
+ { "S_PLD_TX_DRDY0", 10, 1 },
+ { "S_ERROR_SRDY0", 9, 1 },
+ { "S_ERROR_DRDY0", 8, 1 },
+ { "S_DB_VLD0", 7, 1 },
+ { "S_DB_GT0", 6, 1 },
+ { "S_TXVALID0", 5, 1 },
+ { "S_TXFULL0", 4, 1 },
+ { "S_PLD_TXVALID0", 3, 1 },
+ { "S_PLD_TXFULL0", 2, 1 },
+ { "S_CPL5_TXVALID0", 1, 1 },
+ { "S_CPL5_TXFULL0", 0, 1 },
+ { "TP_DBG_CSIDE_FIFO1", 0x239, 0 },
+ { "S_PLD_RXZEROP_SRDY3", 31, 1 },
+ { "S_PLD_RXZEROP_DRDY3", 30, 1 },
+ { "S_PLD_TXZEROP_SRDY3", 29, 1 },
+ { "S_PLD_TXZEROP_DRDY3", 28, 1 },
+ { "S_PLD_TX_SRDY3", 27, 1 },
+ { "S_PLD_TX_DRDY3", 26, 1 },
+ { "S_ERROR_SRDY3", 25, 1 },
+ { "S_ERROR_DRDY3", 24, 1 },
+ { "S_DB_VLD3", 23, 1 },
+ { "S_DB_GT3", 22, 1 },
+ { "S_TXVALID3", 21, 1 },
+ { "S_TXFULL3", 20, 1 },
+ { "S_PLD_TXVALID3", 19 , 1 },
+ { "S_PLD_TXFULL3", 18, 1 },
+ { "S_CPL5_TXVALID3", 17, 1 },
+ { "S_CPL5_TXFULL3", 16, 1 },
+ { "S_PLD_RXZEROP_SRDY2", 15, 1 },
+ { "S_PLD_RXZEROP_DRDY2", 14, 1 },
+ { "S_PLD_TXZEROP_SRDY2", 13, 1 },
+ { "S_PLD_TXZEROP_DRDY2", 12, 1 },
+ { "S_PLD_TX_SRDY2", 11, 1 },
+ { "S_PLD_TX_DRDY2", 10, 1 },
+ { "S_ERROR_SRDY2", 9, 1 },
+ { "S_ERROR_DRDY2", 8, 1 },
+ { "S_DB_VLD2", 7, 1 },
+ { "S_DB_GT2", 6, 1 },
+ { "S_TXVALID2", 5, 1 },
+ { "S_TXFULL2", 4, 1 },
+ { "S_PLD_TXVALID2", 3, 1 },
+ { "S_PLD_TXFULL2", 2, 1 },
+ { "S_CPL5_TXVALID2", 1, 1 },
+ { "S_CPL5_TXFULL2", 0, 1 },
+ { "TP_DBG_CSIDE_DISP0", 0x23A, 0 },
+ { "S_TXFULL", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_CPL5RXVALID", 27, 1 },
+ { "S_CPL5RXFULL", 26, 1 },
+ { "S_PLD_RXZEROP_SRDY", 25, 1 },
+ { "S_PLD_RXZEROP", 24, 1 },
+ { "S_PLD2XRXVALID", 23, 1 },
+ { "S_DDP_SRDY", 22, 1 },
+ { "S_DDP_DRDY", 21, 1 },
+ { "S_DDPSTATE", 16, 5 },
+ { "S_DDPMSGCODE", 12, 4 },
+ { "S_CPL5SOCPCNT", 8, 4 },
+ { "S_PLDRXZEROPCNT", 4, 4 },
+ { "S_TXFRMERR2", 3, 1 },
+ { "S_TXFRMERR1", 2, 1 },
+ { "S_TXVALID2X", 1, 1 },
+ { "S_TXFULL2X", 0, 1 },
+ { "TP_DBG_CSIDE_DISP1", 0x23B, 0 },
+ { "S_TXFULL", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_CPL5RXVALID", 27, 1 },
+ { "S_CPL5RXFULL", 26, 1 },
+ { "S_PLD_RXZEROP_SRDY", 25, 1 },
+ { "S_PLD_RXZEROP", 24, 1 },
+ { "S_PLD2XRXVALID", 23, 1 },
+ { "S_DDP_SRDY", 22, 1 },
+ { "S_DDP_DRDY", 21, 1 },
+ { "S_DDPSTATE", 16, 5 },
+ { "S_DDPMSGCODE", 12, 4 },
+ { "S_CPL5SOCPCNT", 8, 4 },
+ { "S_PLDRXZEROPCNT", 4, 4 },
+ { "S_TXFRMERR2", 3, 1 },
+ { "S_TXFRMERR1", 2, 1 },
+ { "S_TXVALID2X", 1, 1 },
+ { "S_TXFULL2X", 0, 1 },
+ { "TP_DBG_CSIDE_DDP0", 0x23C, 0 },
+ { "S_DDPMSGLATEST7", 28, 4 },
+ { "S_DDPMSGLATEST6", 24, 4 },
+ { "S_DDPMSGLATEST5", 20, 4 },
+ { "S_DDPMSGLATEST4", 16, 4 },
+ { "S_DDPMSGLATEST3", 12, 4 },
+ { "S_DDPMSGLATEST2", 8, 4 },
+ { "S_DDPMSGLATEST1", 4, 4 },
+ { "S_DDPMSGLATEST0", 0, 4 },
+ { "TP_DBG_CSIDE_DDP1", 0x23D, 0 },
+ { "S_DDPMSGLATEST7", 28, 4 },
+ { "S_DDPMSGLATEST6", 24, 4 },
+ { "S_DDPMSGLATEST5", 20, 4 },
+ { "S_DDPMSGLATEST4", 16, 4 },
+ { "S_DDPMSGLATEST3", 12, 4 },
+ { "S_DDPMSGLATEST2", 8, 4 },
+ { "S_DDPMSGLATEST1", 4, 4 },
+ { "S_DDPMSGLATEST0", 0, 4 },
+ { "TP_DBG_CSIDE_FRM", 0x23E, 0 },
+ { "S_CRX2XERROR", 28, 4 },
+ { "S_CPLDTX2XERROR", 24, 4 },
+ { "S_CTXERROR", 22, 2 },
+ { "S_CPLDRXERROR", 20, 2 },
+ { "S_CPLRXERROR", 18, 2 },
+ { "S_CPLTXERROR", 16, 2 },
+ { "S_CPRSERROR", 0, 4 },
+ { "TP_DBG_CSIDE_INT", 0x23F, 0 },
+ { "S_CRXVALID2X", 28, 4 },
+ { "S_CRXAFULL2X", 24, 4 },
+ { "S_CTXVALID2X", 22, 2 },
+ { "S_CTXAFULL2X", 20, 2 },
+ { "S_PLD2X_RXVALID", 18, 2 },
+ { "S_PLD2X_RXAFULL", 16, 2 },
+ { "S_CSIDE_DDP_VALID", 14, 2 },
+ { "S_DDP_AFULL", 12, 2 },
+ { "S_TRC_RXVALID", 11, 1 },
+ { "S_TRC_RXFULL", 10, 1 },
+ { "S_CPL5_TXVALID", 9, 1 },
+ { "S_CPL5_TXFULL", 8, 1 },
+ { "S_PLD2X_TXVALID", 4, 4 },
+ { "S_PLD2X_TXAFULL", 0, 4 },
+ { "TP_CHDR_CONFIG", 0x240, 0 },
+ { "S_CH1HIGH", 24, 8 },
+ { "S_CH1LOW", 16, 8 },
+ { "S_CH0HIGH", 8, 8 },
+ { "S_CH0LOW", 0, 8 },
+ { "TP_UTRN_CONFIG", 0x241, 0 },
+ { "S_CH2FIFOLIMIT", 16, 8 },
+ { "S_CH1FIFOLIMIT", 8, 8 },
+ { "S_CH0FIFOLIMIT", 0, 8 },
+ { "TP_CDSP_CONFIG", 0x242, 0 },
+ { "S_SHAREDRQEN", 31, 1 },
+ { "S_ISCSICMDMODE", 28, 1 },
+ { "S_IMMEDIATEOP", 20, 4 },
+ { "S_IMMEDIATESE", 16, 4 },
+ { "S_ATOMICREQOP", 12, 4 },
+ { "S_ATOMICRSPOP", 8, 4 },
+ { "S_STARTSKIPPLD", 7, 1 },
+ { "S_ATOMICCMDEN", 5, 1 },
+ { "S_WRITEZEROEN", 4, 1 },
+ { "S_WRITEZEROOP", 0, 4 },
+ { "TP_CSPI_POWER", 0x243, 0 },
+ { "S_GATECHNTX3", 11, 1 },
+ { "S_GATECHNTX2", 10, 1 },
+ { "S_GATECHNTX1", 9, 1 },
+ { "S_GATECHNTX0", 8, 1 },
+ { "S_GATECHNRX1", 7, 1 },
+ { "S_GATECHNRX0", 6, 1 },
+ { "S_SLEEPRDYUTRN", 4, 1 },
+ { "S_SLEEPREQUTRN", 0, 1 },
+ { "TP_TRC_CONFIG", 0x244, 0 },
+ { "S_TRCRR", 1, 1 },
+ { "S_TRCCH", 0, 1 },
+ { "TP_TAG_CONFIG", 0x245, 0 },
+ { "S_ETAGTYPE", 16, 16 },
+ { "S_VLANTYPE", 0, 16 },
+ { "TP_DBG_CSIDE_PRS", 0x246, 0 },
+ { "S_C4TUPBUSY3", 31, 1 },
+ { "S_CDBVALID3", 30, 1 },
+ { "S_CRXVALID3", 29, 1 },
+ { "S_CRXFULL3", 28, 1 },
+ { "S_CPRSSTATE3", 24, 4 },
+ { "S_C4TUPBUSY2", 23, 1 },
+ { "S_CDBVALID2", 22, 1 },
+ { "S_CRXVALID2", 21, 1 },
+ { "S_CRXFULL2", 20, 1 },
+ { "S_CPRSSTATE2", 16, 4 },
+ { "S_C4TUPBUSY1", 15, 1 },
+ { "S_CDBVALID1", 14, 1 },
+ { "S_CRXVALID1", 13, 1 },
+ { "S_CRXFULL1", 12, 1 },
+ { "S_CPRSSTATE1", 8, 4 },
+ { "S_C4TUPBUSY0", 7, 1 },
+ { "S_CDBVALID0", 6, 1 },
+ { "S_CRXVALID0", 5, 1 },
+ { "S_CRXFULL0", 4, 1 },
+ { "S_CPRSSTATE0", 0, 4 },
+ { "TP_DBG_CSIDE_DEMUX", 0x247, 0 },
+ { "S_CARBVALID", 28, 4 },
+ { "S_CCPL5DONE", 24, 4 },
+ { "S_CTXZEROPDONE", 20, 4 },
+ { "S_CPLDDONE", 16, 4 },
+ { "S_CTCPOPDONE", 12, 4 },
+ { "S_CDBDONE", 8, 4 },
+ { "S_CISSFIFODONE", 4, 4 },
+ { "S_CTXPKTCSUMDONE", 0, 4 },
+ { "TP_DBG_CSIDE_ARBIT", 0x248, 0 },
+ { "S_CPLVALID3", 31, 1 },
+ { "S_PLDVALID3", 30, 1 },
+ { "S_CRCVALID3", 29, 1 },
+ { "S_ISSVALID3", 28, 1 },
+ { "S_DBVALID3", 27, 1 },
+ { "S_CHKVALID3", 26, 1 },
+ { "S_ZRPVALID3", 25, 1 },
+ { "S_ERRVALID3", 24, 1 },
+ { "S_CPLVALID2", 23, 1 },
+ { "S_PLDVALID2", 22, 1 },
+ { "S_CRCVALID2", 21, 1 },
+ { "S_ISSVALID2", 20, 1 },
+ { "S_DBVALID2", 19, 1 },
+ { "S_CHKVALID2", 18, 1 },
+ { "S_ZRPVALID2", 17, 1 },
+ { "S_ERRVALID2", 16, 1 },
+ { "S_CPLVALID1", 15, 1 },
+ { "S_PLDVALID1", 14, 1 },
+ { "S_CRCVALID1", 13, 1 },
+ { "S_ISSVALID1", 12, 1 },
+ { "S_DBVALID1", 11, 1 },
+ { "S_CHKVALID1", 10, 1 },
+ { "S_ZRPVALID1", 9, 1 },
+ { "S_ERRVALID1", 8, 1 },
+ { "S_CPLVALID0", 7, 1 },
+ { "S_PLDVALID0", 6, 1 },
+ { "S_CRCVALID0", 5, 1 },
+ { "S_ISSVALID0", 4, 1 },
+ { "S_DBVALID0", 3, 1 },
+ { "S_CHKVALID0", 2, 1 },
+ { "S_ZRPVALID0", 1, 1 },
+ { "S_ERRVALID0", 0, 1 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_24c[] = {
+ { "TP_DBG_CSIDE_TRACE_CNT", 0x24a, 0 },
+ { "TrcSopCnt", 24, 8 },
+ { "TrcEopCnt", 16, 8 },
+ { "TrcFltHit", 12, 4 },
+ { "TrcRntPkt", 8, 4 },
+ { "TrcPktLen", 0, 8 },
+ { "TP_DBG_CSIDE_TRACE_RSS", 0x24b, 0 },
+ { "TP_VLN_CONFIG", 0x24c, 0 },
+ { "EthTypeQinQ", 16, 16 },
+ { "EthTypeVlan", 0, 16 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_pio_regs_230_to_248[] = {
+ { "TP_DBG_CSIDE_RX0", 0x230, 0 },
+ { "S_CRXSOPCNT", 28, 4 },
+ { "S_CRXEOPCNT", 24, 4 },
+ { "S_CRXPLDSOPCNT", 20, 4 },
+ { "S_CRXPLDEOPCNT", 16, 4 },
+ { "S_CRXARBSOPCNT", 12, 4 },
+ { "S_CRXARBEOPCNT", 8, 4 },
+ { "S_CRXCPLSOPCNT", 4, 4 },
+ { "S_CRXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_RX1", 0x231, 0 },
+ { "S_CRXSOPCNT", 28, 4 },
+ { "S_CRXEOPCNT", 24, 4 },
+ { "S_CRXPLDSOPCNT", 20, 4 },
+ { "S_CRXPLDEOPCNT", 16, 4 },
+ { "S_CRXARBSOPCNT", 12, 4 },
+ { "S_CRXARBEOPCNT", 8, 4 },
+ { "S_CRXCPLSOPCNT", 4, 4 },
+ { "S_CRXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_RX2", 0x232, 0 },
+ { "S_CRXSOPCNT", 28, 4 },
+ { "S_CRXEOPCNT", 24, 4 },
+ { "S_CRXPLDSOPCNT", 20, 4 },
+ { "S_CRXPLDEOPCNT", 16, 4 },
+ { "S_CRXARBSOPCNT", 12, 4 },
+ { "S_CRXARBEOPCNT", 8, 4 },
+ { "S_CRXCPLSOPCNT", 4, 4 },
+ { "S_CRXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_RX3", 0x233, 0 },
+ { "S_CRXSOPCNT", 28, 4 },
+ { "S_CRXEOPCNT", 24, 4 },
+ { "S_CRXPLDSOPCNT", 20, 4 },
+ { "S_CRXPLDEOPCNT", 16, 4 },
+ { "S_CRXARBSOPCNT", 12, 4 },
+ { "S_CRXARBEOPCNT", 8, 4 },
+ { "S_CRXCPLSOPCNT", 4, 4 },
+ { "S_CRXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_TX0", 0x234, 0 },
+ { "S_TXSOPCNT", 28, 4 },
+ { "S_TXEOPCNT", 24, 4 },
+ { "S_TXPLDSOPCNT", 20, 4 },
+ { "S_TXPLDEOPCNT", 16, 4 },
+ { "S_TXARBSOPCNT", 12, 4 },
+ { "S_TXARBEOPCNT", 8, 4 },
+ { "S_TXCPLSOPCNT", 4, 4 },
+ { "S_TXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_TX1", 0x235, 0 },
+ { "S_TXSOPCNT", 28, 4 },
+ { "S_TXEOPCNT", 24, 4 },
+ { "S_TXPLDSOPCNT", 20, 4 },
+ { "S_TXPLDEOPCNT", 16, 4 },
+ { "S_TXARBSOPCNT", 12, 4 },
+ { "S_TXARBEOPCNT", 8, 4 },
+ { "S_TXCPLSOPCNT", 4, 4 },
+ { "S_TXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_TX2", 0x236, 0 },
+ { "S_TXSOPCNT", 28, 4 },
+ { "S_TXEOPCNT", 24, 4 },
+ { "S_TXPLDSOPCNT", 20, 4 },
+ { "S_TXPLDEOPCNT", 16, 4 },
+ { "S_TXARBSOPCNT", 12, 4 },
+ { "S_TXARBEOPCNT", 8, 4 },
+ { "S_TXCPLSOPCNT", 4, 4 },
+ { "S_TXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_TX3", 0x237, 0 },
+ { "S_TXSOPCNT", 28, 4 },
+ { "S_TXEOPCNT", 24, 4 },
+ { "S_TXPLDSOPCNT", 20, 4 },
+ { "S_TXPLDEOPCNT", 16, 4 },
+ { "S_TXARBSOPCNT", 12, 4 },
+ { "S_TXARBEOPCNT", 8, 4 },
+ { "S_TXCPLSOPCNT", 4, 4 },
+ { "S_TXCPLEOPCNT", 0, 4 },
+ { "TP_DBG_CSIDE_FIFO0", 0x238, 0 },
+ { "S_PLD_RXZEROP_SRDY1", 31, 1 },
+ { "S_PLD_RXZEROP_DRDY1", 30, 1 },
+ { "S_PLD_TXZEROP_SRDY1", 29, 1 },
+ { "S_PLD_TXZEROP_DRDY1", 28, 1 },
+ { "S_PLD_TX_SRDY1", 27, 1 },
+ { "S_PLD_TX_DRDY1", 26, 1 },
+ { "S_ERROR_SRDY1", 25, 1 },
+ { "S_ERROR_DRDY1", 24, 1 },
+ { "S_DB_VLD1", 23, 1 },
+ { "S_DB_GT1", 22, 1 },
+ { "S_TXVALID1", 21, 1 },
+ { "S_TXFULL1", 20, 1 },
+ { "S_PLD_TXVALID1", 19 , 1 },
+ { "S_PLD_TXFULL1", 18, 1 },
+ { "S_CPL5_TXVALID1", 17, 1 },
+ { "S_CPL5_TXFULL1", 16, 1 },
+ { "S_PLD_RXZEROP_SRDY0", 15, 1 },
+ { "S_PLD_RXZEROP_DRDY0", 14, 1 },
+ { "S_PLD_TXZEROP_SRDY0", 13, 1 },
+ { "S_PLD_TXZEROP_DRDY0", 12, 1 },
+ { "S_PLD_TX_SRDY0", 11, 1 },
+ { "S_PLD_TX_DRDY0", 10, 1 },
+ { "S_ERROR_SRDY0", 9, 1 },
+ { "S_ERROR_DRDY0", 8, 1 },
+ { "S_DB_VLD0", 7, 1 },
+ { "S_DB_GT0", 6, 1 },
+ { "S_TXVALID0", 5, 1 },
+ { "S_TXFULL0", 4, 1 },
+ { "S_PLD_TXVALID0", 3, 1 },
+ { "S_PLD_TXFULL0", 2, 1 },
+ { "S_CPL5_TXVALID0", 1, 1 },
+ { "S_CPL5_TXFULL0", 0, 1 },
+ { "TP_DBG_CSIDE_FIFO1", 0x239, 0 },
+ { "S_PLD_RXZEROP_SRDY3", 31, 1 },
+ { "S_PLD_RXZEROP_DRDY3", 30, 1 },
+ { "S_PLD_TXZEROP_SRDY3", 29, 1 },
+ { "S_PLD_TXZEROP_DRDY3", 28, 1 },
+ { "S_PLD_TX_SRDY3", 27, 1 },
+ { "S_PLD_TX_DRDY3", 26, 1 },
+ { "S_ERROR_SRDY3", 25, 1 },
+ { "S_ERROR_DRDY3", 24, 1 },
+ { "S_DB_VLD3", 23, 1 },
+ { "S_DB_GT3", 22, 1 },
+ { "S_TXVALID3", 21, 1 },
+ { "S_TXFULL3", 20, 1 },
+ { "S_PLD_TXVALID3", 19 , 1 },
+ { "S_PLD_TXFULL3", 18, 1 },
+ { "S_CPL5_TXVALID3", 17, 1 },
+ { "S_CPL5_TXFULL3", 16, 1 },
+ { "S_PLD_RXZEROP_SRDY2", 15, 1 },
+ { "S_PLD_RXZEROP_DRDY2", 14, 1 },
+ { "S_PLD_TXZEROP_SRDY2", 13, 1 },
+ { "S_PLD_TXZEROP_DRDY2", 12, 1 },
+ { "S_PLD_TX_SRDY2", 11, 1 },
+ { "S_PLD_TX_DRDY2", 10, 1 },
+ { "S_ERROR_SRDY2", 9, 1 },
+ { "S_ERROR_DRDY2", 8, 1 },
+ { "S_DB_VLD2", 7, 1 },
+ { "S_DB_GT2", 6, 1 },
+ { "S_TXVALID2", 5, 1 },
+ { "S_TXFULL2", 4, 1 },
+ { "S_PLD_TXVALID2", 3, 1 },
+ { "S_PLD_TXFULL2", 2, 1 },
+ { "S_CPL5_TXVALID2", 1, 1 },
+ { "S_CPL5_TXFULL2", 0, 1 },
+ { "TP_DBG_CSIDE_DISP0", 0x23A, 0 },
+ { "S_TXFULL", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_CPL5RXVALID", 27, 1 },
+ { "S_CPL5RXFULL", 26, 1 },
+ { "S_PLD_RXZEROP_SRDY", 25, 1 },
+ { "S_PLD_RXZEROP", 24, 1 },
+ { "S_PLD2XRXVALID", 23, 1 },
+ { "S_DDP_SRDY", 22, 1 },
+ { "S_DDP_DRDY", 21, 1 },
+ { "S_DDPSTATE", 16, 5 },
+ { "S_DDPMSGCODE", 12, 4 },
+ { "S_CPL5SOCPCNT", 8, 4 },
+ { "S_PLDRXZEROPCNT", 4, 4 },
+ { "S_TXFRMERR2", 3, 1 },
+ { "S_TXFRMERR1", 2, 1 },
+ { "S_TXVALID2X", 1, 1 },
+ { "S_TXFULL2X", 0, 1 },
+ { "TP_DBG_CSIDE_DISP1", 0x23B, 0 },
+ { "S_TXFULL", 31, 1 },
+ { "S_STATE", 28, 3 },
+ { "S_CPL5RXVALID", 27, 1 },
+ { "S_CPL5RXFULL", 26, 1 },
+ { "S_PLD_RXZEROP_SRDY", 25, 1 },
+ { "S_PLD_RXZEROP", 24, 1 },
+ { "S_PLD2XRXVALID", 23, 1 },
+ { "S_DDP_SRDY", 22, 1 },
+ { "S_DDP_DRDY", 21, 1 },
+ { "S_DDPSTATE", 16, 5 },
+ { "S_DDPMSGCODE", 12, 4 },
+ { "S_CPL5SOCPCNT", 8, 4 },
+ { "S_PLDRXZEROPCNT", 4, 4 },
+ { "S_TXFRMERR2", 3, 1 },
+ { "S_TXFRMERR1", 2, 1 },
+ { "S_TXVALID2X", 1, 1 },
+ { "S_TXFULL2X", 0, 1 },
+ { "TP_DBG_CSIDE_DDP0", 0x23C, 0 },
+ { "S_DDPMSGLATEST7", 28, 4 },
+ { "S_DDPMSGLATEST6", 24, 4 },
+ { "S_DDPMSGLATEST5", 20, 4 },
+ { "S_DDPMSGLATEST4", 16, 4 },
+ { "S_DDPMSGLATEST3", 12, 4 },
+ { "S_DDPMSGLATEST2", 8, 4 },
+ { "S_DDPMSGLATEST1", 4, 4 },
+ { "S_DDPMSGLATEST0", 0, 4 },
+ { "TP_DBG_CSIDE_DDP1", 0x23D, 0 },
+ { "S_DDPMSGLATEST7", 28, 4 },
+ { "S_DDPMSGLATEST6", 24, 4 },
+ { "S_DDPMSGLATEST5", 20, 4 },
+ { "S_DDPMSGLATEST4", 16, 4 },
+ { "S_DDPMSGLATEST3", 12, 4 },
+ { "S_DDPMSGLATEST2", 8, 4 },
+ { "S_DDPMSGLATEST1", 4, 4 },
+ { "S_DDPMSGLATEST0", 0, 4 },
+ { "TP_DBG_CSIDE_FRM", 0x23E, 0 },
+ { "S_CRX2XERROR", 28, 4 },
+ { "S_CPLDTX2XERROR", 24, 4 },
+ { "S_CTXERROR", 22, 2 },
+ { "S_CPLDRXERROR", 20, 2 },
+ { "S_CPLRXERROR", 18, 2 },
+ { "S_CPLTXERROR", 16, 2 },
+ { "S_CPRSERROR", 0, 4 },
+ { "TP_DBG_CSIDE_INT", 0x23F, 0 },
+ { "S_CRXVALID2X", 28, 4 },
+ { "S_CRXAFULL2X", 24, 4 },
+ { "S_CTXVALID2X", 22, 2 },
+ { "S_CTXAFULL2X", 20, 2 },
+ { "S_PLD2X_RXVALID", 18, 2 },
+ { "S_PLD2X_RXAFULL", 16, 2 },
+ { "S_CSIDE_DDP_VALID", 14, 2 },
+ { "S_DDP_AFULL", 12, 2 },
+ { "S_TRC_RXVALID", 11, 1 },
+ { "S_TRC_RXFULL", 10, 1 },
+ { "S_CPL5_TXVALID", 9, 1 },
+ { "S_CPL5_TXFULL", 8, 1 },
+ { "S_PLD2X_TXVALID", 4, 4 },
+ { "S_PLD2X_TXAFULL", 0, 4 },
+ { "TP_CHDR_CONFIG", 0x240, 0 },
+ { "S_CH1HIGH", 24, 8 },
+ { "S_CH1LOW", 16, 8 },
+ { "S_CH0HIGH", 8, 8 },
+ { "S_CH0LOW", 0, 8 },
+ { "TP_UTRN_CONFIG", 0x241, 0 },
+ { "S_CH2FIFOLIMIT", 16, 8 },
+ { "S_CH1FIFOLIMIT", 8, 8 },
+ { "S_CH0FIFOLIMIT", 0, 8 },
+ { "TP_CDSP_CONFIG", 0x242, 0 },
+ { "S_IMMEDIATEOP", 20, 4 },
+ { "S_IMMEDIATESE", 16, 4 },
+ { "S_ATOMICREQOP", 12, 4 },
+ { "S_ATOMICRSPOP", 8, 4 },
+ { "S_STARTSKIPPLD", 7, 1 },
+ { "S_ATOMICCMDEN", 5, 1 },
+ { "S_WRITEZEROEN", 4, 1 },
+ { "S_WRITEZEROOP", 0, 4 },
+ { "TP_CSPI_POWER", 0x243, 0 },
+ { "S_GATECHNTX3", 11, 1 },
+ { "S_GATECHNTX2", 10, 1 },
+ { "S_GATECHNTX1", 9, 1 },
+ { "S_GATECHNTX0", 8, 1 },
+ { "S_GATECHNRX1", 7, 1 },
+ { "S_GATECHNRX0", 6, 1 },
+ { "S_SLEEPRDYUTRN", 4, 1 },
+ { "S_SLEEPREQUTRN", 0, 1 },
+ { "TP_TRC_CONFIG", 0x244, 0 },
+ { "S_TRCRR", 1, 1 },
+ { "S_TRCCH", 0, 1 },
+ { "TP_TAG_CONFIG", 0x245, 0 },
+ { "S_ETAGTYPE", 16, 16 },
+ { "S_VLANTYPE", 0, 16 },
+ { "TP_DBG_CSIDE_PRS", 0x246, 0 },
+ { "S_C4TUPBUSY3", 31, 1 },
+ { "S_CDBVALID3", 30, 1 },
+ { "S_CRXVALID3", 29, 1 },
+ { "S_CRXFULL3", 28, 1 },
+ { "S_CPRSSTATE3", 24, 4 },
+ { "S_C4TUPBUSY2", 23, 1 },
+ { "S_CDBVALID2", 22, 1 },
+ { "S_CRXVALID2", 21, 1 },
+ { "S_CRXFULL2", 20, 1 },
+ { "S_CPRSSTATE2", 16, 4 },
+ { "S_C4TUPBUSY1", 15, 1 },
+ { "S_CDBVALID1", 14, 1 },
+ { "S_CRXVALID1", 13, 1 },
+ { "S_CRXFULL1", 12, 1 },
+ { "S_CPRSSTATE1", 8, 4 },
+ { "S_C4TUPBUSY0", 7, 1 },
+ { "S_CDBVALID0", 6, 1 },
+ { "S_CRXVALID0", 5, 1 },
+ { "S_CRXFULL0", 4, 1 },
+ { "S_CPRSSTATE0", 0, 4 },
+ { "TP_DBG_CSIDE_DEMUX", 0x247, 0 },
+ { "S_CARBVALID", 28, 4 },
+ { "S_CCPL5DONE", 24, 4 },
+ { "S_CTXZEROPDONE", 20, 4 },
+ { "S_CPLDDONE", 16, 4 },
+ { "S_CTCPOPDONE", 12, 4 },
+ { "S_CDBDONE", 8, 4 },
+ { "S_CISSFIFODONE", 4, 4 },
+ { "S_CTXPKTCSUMDONE", 0, 4 },
+ { "TP_DBG_CSIDE_ARBIT", 0x248, 0 },
+ { "S_CPLVALID3", 31, 1 },
+ { "S_PLDVALID3", 30, 1 },
+ { "S_CRCVALID3", 29, 1 },
+ { "S_ISSVALID3", 28, 1 },
+ { "S_DBVALID3", 27, 1 },
+ { "S_CHKVALID3", 26, 1 },
+ { "S_ZRPVALID3", 25, 1 },
+ { "S_ERRVALID3", 24, 1 },
+ { "S_CPLVALID2", 23, 1 },
+ { "S_PLDVALID2", 22, 1 },
+ { "S_CRCVALID2", 21, 1 },
+ { "S_ISSVALID2", 20, 1 },
+ { "S_DBVALID2", 19, 1 },
+ { "S_CHKVALID2", 18, 1 },
+ { "S_ZRPVALID2", 17, 1 },
+ { "S_ERRVALID2", 16, 1 },
+ { "S_CPLVALID1", 15, 1 },
+ { "S_PLDVALID1", 14, 1 },
+ { "S_CRCVALID1", 13, 1 },
+ { "S_ISSVALID1", 12, 1 },
+ { "S_DBVALID1", 11, 1 },
+ { "S_CHKVALID1", 10, 1 },
+ { "S_ZRPVALID1", 9, 1 },
+ { "S_ERRVALID1", 8, 1 },
+ { "S_CPLVALID0", 7, 1 },
+ { "S_PLDVALID0", 6, 1 },
+ { "S_CRCVALID0", 5, 1 },
+ { "S_ISSVALID0", 4, 1 },
+ { "S_DBVALID0", 3, 1 },
+ { "S_CHKVALID0", 2, 1 },
+ { "S_ZRPVALID0", 1, 1 },
+ { "S_ERRVALID0", 0, 1 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_tp_pio_regs_8c0[] = {
+ { "TP_FIFO_CONFIG", 0x8C0, 0 },
+ { "S_CH1_OUTPUT", 27, 5 },
+ { "S_CH2_OUTPUT", 22, 5 },
+ { "S_RESERVED", 17, 5 },
+ { "S_STROBE1", 16, 1 },
+ { "S_CH1_INPUT", 11, 5 },
+ { "S_CH2_INPUT", 6, 5 },
+ { "S_CH3_INPUT", 1, 5 },
+ { "S_STROBE0", 0, 1 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_tp_pio_regs_8c0[] = {
+ { "TP_FIFO_CONFIG", 0x8C0, 0 },
+ { "S_CH1_OUTPUT", 27, 5 },
+ { "S_CH2_OUTPUT", 22, 5 },
+ { "S_RESERVED", 17, 5 },
+ { "S_STROBE1", 16, 1 },
+ { "S_CH1_INPUT", 11, 5 },
+ { "S_CH2_INPUT", 6, 5 },
+ { "S_CH3_INPUT", 1, 5 },
+ { "S_STROBE0", 0, 1 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_pcie_pdbg_regs_00_to_20[] = {
+ { "PCIE_PDEBUG_REG_0x0", 0x00, 0 },
+ { "PCIE_PDEBUG_REG_0x1", 0x01, 0 },
+ { "PCIE_PDEBUG_REG_0x2", 0X02, 0 },
+ { "tagq_ch0_tags_used", 11, 8 },
+ { "tagq_ch0_data_empty", 10, 1 },
+ { "rdq_ch0_req_empty", 9, 1 },
+ { "req_ctl_rd_ch0_wait_for_tagtq", 8, 1 },
+ { "req_ctl_rd_ch0_wait_for_cmd", 7, 1 },
+ { "req_ctl_rd_ch0_wait_for_data_mem", 6, 1 },
+ { "req_ctl_rd_ch0_wait_for_rdq", 5, 1 },
+ { "req_ctl_rd_ch0_wait_for_txn_disable_fifo", 4, 1 },
+ { "req_ctl_rd_ch0_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_rd_ch0_exit_top_vld_started", 2, 1 },
+ { "req_ctl_rd_ch0_wait_for_pause", 1, 1 },
+ { "req_ctl_rd_ch0_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x3", 0X03, 0 },
+ { "tagq_ch1_tags_used", 11, 8 },
+ { "req_ch1_data_empty", 10, 1 },
+ { "rdq_ch1_req_empty", 9, 1 },
+ { "req_ctl_rd_ch1_wait_for_tagtq", 8, 1 },
+ { "req_ctl_rd_ch1_wait_for_cmd", 7, 1 },
+ { "req_ctl_rd_ch1_wait_for_data_mem", 6, 1 },
+ { "req_ctl_rd_ch1_wait_for_rdq", 5, 1 },
+ { "req_ctl_rd_ch1_wait_for_txn_disable_fifo", 4, 1 },
+ { "req_ctl_rd_ch1_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_rd_ch1_exit_top_vld_started", 2, 1 },
+ { "req_ctl_rd_ch1_wait_for_pause", 1, 1 },
+ { "req_ctl_rd_ch1_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x4", 0X04, 0 },
+ { "tagq_ch2_tags_used", 11, 8 },
+ { "req_ch2_data_empty", 10, 1 },
+ { "rdq_ch2_req_empty", 9, 1 },
+ { "req_ctl_rd_ch2_wait_for_tagtq", 8, 1 },
+ { "req_ctl_rd_ch2_wait_for_cmd", 7, 1 },
+ { "req_ctl_rd_ch2_wait_for_data_mem", 6, 1 },
+ { "req_ctl_rd_ch2_wait_for_rdq", 5, 1 },
+ { "req_ctl_rd_ch2_wait_for_txn_disable_fifo", 4, 1 },
+ { "req_ctl_rd_ch2_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_rd_ch2_exit_top_vld_started", 2, 1 },
+ { "req_ctl_rd_ch2_wait_for_pause", 1, 1},
+ { "req_ctl_rd_ch2_wait_for_fifo_data", 0, 1},
+ { "PCIE_PDEBUG_REG_0x5", 0x05, 0 },
+ { "tagq_ch3_tags_used", 11, 8 },
+ { "req_ch3_data_empty", 10, 1 },
+ { "rdq_ch3_req_empty", 9, 1 },
+ { "req_ctl_rd_ch3_wait_for_tagtq", 8, 1 },
+ { "req_ctl_rd_ch3_wait_for_cmd", 7, 1 },
+ { "req_ctl_rd_ch3_wait_for_data_mem", 6, 1 },
+ { "req_ctl_rd_ch3_wait_for_rdq", 5, 1 },
+ { "req_ctl_rd_ch3_wait_for_txn_disable_fifo", 4, 1 },
+ { "req_ctl_rd_ch3_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_rd_ch3_exit_top_vld_started", 2, 1 },
+ { "req_ctl_rd_ch3_wait_for_pause", 1, 1 },
+ { "req_ctl_rd_ch3_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x6", 0x06, 0 },
+ { "tagq_ch4_tags_used", 11, 8 },
+ { "req_ch4_data_empty", 10, 1 },
+ { "rdq_ch4_req_empty", 9, 1 },
+ { "req_ctl_rd_ch4_wait_for_tagtq", 8, 1 },
+ { "req_ctl_rd_ch4_wait_for_cmd", 7, 1 },
+ { "req_ctl_rd_ch4_wait_for_data_mem", 6, 1 },
+ { "req_ctl_rd_ch4_wait_for_rdq", 5, 1 },
+ { "req_ctl_rd_ch4_wait_for_txn_disable_fifo", 4, 1 },
+ { "req_ctl_rd_ch4_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_rd_ch4_exit_top_vld_started", 2, 1 },
+ { "req_ctl_rd_ch4_wait_for_pause", 1, 1 },
+ { "req_ctl_rd_ch4_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x7", 0x07, 0 },
+ { "tagq_ch5_tags_used", 11, 8 },
+ { "req_ch5_data_empty", 10, 1 },
+ { "rdq_ch5_req_empty", 9, 1 },
+ { "req_ctl_rd_ch5_wait_for_tagtq", 8, 1 },
+ { "req_ctl_rd_ch5_wait_for_cmd", 7, 1 },
+ { "req_ctl_rd_ch5_wait_for_data_mem", 6, 1 },
+ { "req_ctl_rd_ch5_wait_for_rdq", 5, 1 },
+ { "req_ctl_rd_ch5_wait_for_txn_disable_fifo", 4, 1 },
+ { "req_ctl_rd_ch5_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_rd_ch5_exit_top_vld_started", 2, 1 },
+ { "req_ctl_rd_ch5_wait_for_pause", 1, 1 },
+ { "req_ctl_rd_ch5_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x8", 0x08, 0 },
+ { "tagq_ch6_tags_used", 11, 8 },
+ { "req_ch6_data_empty", 10, 1 },
+ { "rdq_ch6_req_empty", 9, 1 },
+ { "req_ctl_rd_ch6_wait_for_tagtq", 8, 1 },
+ { "req_ctl_rd_ch6_wait_for_cmd", 7, 1 },
+ { "req_ctl_rd_ch6_wait_for_data_mem", 6, 1 },
+ { "req_ctl_rd_ch6_wait_for_rdq", 5, 1 },
+ { "req_ctl_rd_ch6_wait_for_txn_disable_fifo", 4, 1 },
+ { "req_ctl_rd_ch6_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_rd_ch6_exit_top_vld_started", 2, 1 },
+ { "req_ctl_rd_ch6_wait_for_pause", 1, 1 },
+ { "req_ctl_rd_ch6_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x9", 0x09, 0 },
+ { "tagq_ch7_tags_used", 11, 8 },
+ { "req_ch7_data_empty", 10, 1 },
+ { "rdq_ch7_req_empty", 9, 1 },
+ { "req_ctl_rd_ch7_wait_for_tagtq", 8, 1 },
+ { "req_ctl_rd_ch7_wait_for_cmd", 7, 1 },
+ { "req_ctl_rd_ch7_wait_for_data_mem", 6, 1 },
+ { "req_ctl_rd_ch7_wait_for_rdq", 5, 1 },
+ { "req_ctl_rd_ch7_wait_for_txn_disable_fifo", 4, 1 },
+ { "req_ctl_rd_ch7_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_rd_ch7_exit_top_vld_started", 2, 1 },
+ { "req_ctl_rd_ch7_wait_for_pause", 1, 1 },
+ { "req_ctl_rd_ch7_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0xa", 0x0a, 0 },
+ { "req_ctl_rd_ch0_wait_for_seqnum", 27, 1 },
+ { "req_ctl_wr_ch0_seqnum", 19, 8 },
+ { "req_ctl_rd_ch0_seqnum", 11, 8 },
+ { "req_ctl_wr_ch0_wait_for_si_fifo", 4, 1 },
+ { "req_ctl_wr_ch0_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_wr_ch0_exit_top_vld_started", 2, 1 },
+ { "req_ctl_wr_ch0_wait_for_pause", 1, 1 },
+ { "req_ctl_wr_ch0_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0xb", 0x0b, 0 },
+ { "req_ctl_rd_ch1_wait_for_seqnum", 27, 1 },
+ { "req_ctl_wr_ch1_seqnum", 19, 8 },
+ { "req_ctl_rd_ch1_seqnum", 11, 8 },
+ { "req_ctl_wr_ch1_wait_for_si_fifo", 4, 1 },
+ { "req_ctl_wr_ch1_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_wr_ch1_exit_top_vld_started", 2, 1 },
+ { "req_ctl_wr_ch1_wait_for_pause", 1, 1 },
+ { "req_ctl_wr_ch1_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0xc", 0x0c, 0 },
+ { "req_ctl_rd_ch2_wait_for_seqnum", 27, 27},
+ { "req_ctl_wr_ch2_seqnum", 19, 8 },
+ { "req_ctl_rd_ch2_seqnum", 11, 8 },
+ { "req_ctl_wr_ch2_wait_for_si_fifo", 4, 1 },
+ { "req_ctl_wr_ch2_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_wr_ch2_exit_top_vld_started", 2, 1 },
+ { "req_ctl_wr_ch2_wait_for_pause", 1, 1 },
+ { "req_ctl_wr_ch2_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0xd", 0x0d, 0 },
+ { "req_ctl_rd_ch3_wait_for_seqnum", 27, 1 },
+ { "req_ctl_wr_ch3_seqnum", 19, 8 },
+ { "req_ctl_rd_ch3_seqnum", 11, 8 },
+ { "req_ctl_wr_ch3_wait_for_si_fifo", 4, 1 },
+ { "req_ctl_wr_ch3_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_wr_ch3_exit_top_vld_started", 2, 1 },
+ { "req_ctl_wr_ch3_wait_for_pause", 1, 1 },
+ { "req_ctl_wr_ch3_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0xe", 0x0e, 0 },
+ { "req_ctl_rd_ch4_wait_for_seqnum", 27, 1 },
+ { "req_ctl_wr_ch4_seqnum", 19, 8 },
+ { "req_ctl_rd_ch4_seqnum", 11, 8 },
+ { "req_ctl_wr_ch4_wait_for_si_fifo", 4, 1 },
+ { "req_ctl_wr_ch4_exit_bot_vld_started", 3, 1 },
+ { "req_ctl_wr_ch4_exit_top_vld_started", 2, 1 },
+ { "req_ctl_wr_ch4_wait_for_pause", 1, 1 },
+ { "req_ctl_wr_ch4_wait_for_fifo_data", 0, 1 },
+ { "PCIE_PDEBUG_REG_0xf", 0xf, 0 },
+ { "PCIE_PDEBUG_REG_0x10", 0x10, 0 },
+ { "pipe0_tx3_datak_0", 31, 1 },
+ { "pipe0_tx3_data_6_0", 24, 7 },
+ { "pipe0_tx2_data_7_0", 16, 8 },
+ { "pipe0_tx1_data_7_0", 8 , 8 },
+ { "pipe0_tx0_datak_0", 7, 1 },
+ { "pipe0_tx0_data_6_0", 0 , 7 },
+ { "PCIE_PDEBUG_REG_0x11", 0x11, 0 },
+ { "pipe0_tx3_datak_1", 31, 1 },
+ { "pipe0_tx3_data_14_8", 24, 7 },
+ { "pipe0_tx2_data_15_8", 16, 8 },
+ { "pipe0_tx1_data_15_8", 8, 8 },
+ { "pipe0_tx0_datak_1", 7, 1 },
+ { "pipe0_tx0_data_14_8", 0, 7 },
+ { "PCIE_PDEBUG_REG_0x12", 0x12, 0 },
+ { "pipe0_tx7_datak_0", 31, 1 },
+ { "pipe0_tx7_data_6_0", 24, 7 },
+ { "pipe0_tx6_data_7_0", 16, 8 },
+ { "pipe0_tx5_data_7_0", 8, 8 },
+ { "pipe0_tx4_datak_0", 7, 1 },
+ { "pipe0_tx4_data_6_0", 0, 7 },
+ { "PCIE_PDEBUG_REG_0x13", 0x13, 0 },
+ { "pipe0_tx7_datak_1", 31, 1 },
+ { "pipe0_tx7_data_14_8", 24, 7 },
+ { "pipe0_tx6_data_15_8", 16, 8 },
+ { "pipe0_tx5_data_15_8", 8, 8 },
+ { "pipe0_tx4_datak_1", 7, 1 },
+ { "pipe0_tx4_data_14_8", 0, 7 },
+ { "PCIE_PDEBUG_REG_0x14", 0x14, 0 },
+ { "pipe0_rx3_valid_14", 31, 1 },
+ { "pipe0_rx3_valid2_14", 24, 7 },
+ { "pipe0_rx2_valid_14", 16, 8 },
+ { "pipe0_rx1_valid_14", 8, 8 },
+ { "pipe0_rx0_valid_14", 7, 1 },
+ { "pipe0_rx0_valid2_14", 0, 7 },
+ { "PCIE_PDEBUG_REG_0x15", 0x15, 0 },
+ { "pipe0_rx3_valid_15", 31, 1 },
+ { "pipe0_rx3_valid2_15", 24, 7 },
+ { "pipe0_rx2_valid_15", 16, 8 },
+ { "pipe0_rx1_valid_15", 8, 8 },
+ { "pipe0_rx0_valid_15", 7, 1 },
+ { "pipe0_rx0_valid2+15", 0, 7 },
+ { "PCIE_PDEBUG_REG_0x16", 0x16, 0 },
+ { "pipe0_rx7_valid_16", 31, 1 },
+ { "pipe0_rx7_valid2_16", 24, 7 },
+ { "pipe0_rx6_valid_16", 16, 8 },
+ { "pipe0_rx5_valid_16", 8, 8 },
+ { "pipe0_rx4_valid_16", 7, 1 },
+ { "pipe0_rx4_valid2_16", 0, 7 },
+ { "PCIE_PDEBUG_REG_0x17", 0x17, 0 },
+ { "pipe0_rx7_valid_17", 31, 1 },
+ { "pipe0_rx7_valid2_17", 24, 7 },
+ { "pipe0_rx6_valid_17", 16, 8 },
+ { "pipe0_rx5_valid_17", 8, 8 },
+ { "pipe0_rx4_valid_17", 7, 1 },
+ { "pipe0_rx4_valid2_17", 0, 7 },
+ { "PCIE_PDEBUG_REG_0x18", 0x18, 0 },
+ { "pipe0_rx7_polarity", 31, 1 },
+ { "pipe0_rx7_status", 28, 3 },
+ { "pipe0_rx6_polarity", 27, 1 },
+ { "pipe0_rx6_status", 24 , 3 },
+ { "pipe0_rx5_polarity", 23, 1 },
+ { "pipe0_rx5_status", 20, 3 },
+ { "pipe0_rx4_polarity", 19, 1 },
+ { "pipe0_rx4_status", 16, 3 },
+ { "pipe0_rx3_polarity", 15, 1 },
+ { "pipe0_rx3_status", 12, 3 },
+ { "pipe0_rx2_polarity", 11, 1 },
+ { "pipe0_rx2_status", 8, 3 },
+ { "pipe0_rx1_polarity", 7, 1 },
+ { "pipe0_rx1_status", 4, 3 },
+ { "pipe0_rx0_polarity", 3, 1 },
+ { "pipe0_rx0_status", 0, 3 },
+ { "PCIE_PDEBUG_REG_0x19", 0x19, 0 },
+ { "pipe0_tx7_compliance", 31, 1 },
+ { "pipe0_tx6_compliance", 30, 1 },
+ { "pipe0_tx5_compliance", 29, 1 },
+ { "pipe0_tx4_compliance", 28, 1 },
+ { "pipe0_tx3_compliance", 27, 1 },
+ { "pipe0_tx2_compliance", 26, 1 },
+ { "pipe0_tx1_compliance", 25, 1 },
+ { "pipe0_tx0_compliance", 24, 1 },
+ { "pipe0_tx7_elecidle", 23, 1 },
+ { "pipe0_tx6_elecidle", 22, 1 },
+ { "pipe0_tx5_elecidle", 21, 1 },
+ { "pipe0_tx4_elecidle", 20, 1 },
+ { "pipe0_tx3_elecidle", 19, 1 },
+ { "pipe0_tx2_elecidle", 18, 1 },
+ { "pipe0_tx1_elecidle", 17, 1 },
+ { "pipe0_tx0_elecidle", 16, 1 },
+ { "pipe0_rx7_polarity_19", 15, 1 },
+ { "pipe0_rx6_polarity_19", 14, 1 },
+ { "pipe0_rx5_polarity_19", 13, 1 },
+ { "pipe0_rx4_polarity_19", 12, 1 },
+ { "pipe0_rx3_polarity_19", 11, 1 },
+ { "pipe0_rx2_polarity_19", 10, 1 },
+ { "pipe0_rx1_polarity_19", 9, 1 },
+ { "pipe0_rx0_polarity_19", 8, 1 },
+ { "pipe0_rx7_elecidle", 7, 1 },
+ { "pipe0_rx6_elecidle", 6, 1 },
+ { "pipe0_rx5_elecidle", 5, 1 },
+ { "pipe0_rx4_elecidle", 4, 1 },
+ { "pipe0_rx3_elecidle", 3, 1 },
+ { "pipe0_rx2_elecidle", 2, 1 },
+ { "pipe0_rx1_elecidle", 1, 1 },
+ { "pipe0_rx0_elecidle", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x1a", 0x1a , 0 },
+ { "reserved", 22 , 10 },
+ { "pipe0_reset_n", 21, 1 },
+ { "pcs_common_clocks", 20, 1 },
+ { "pcs_clk_req", 19, 1 },
+ { "pipe_clkreq_n", 18, 1 },
+ { "mac_clkreq_n_to_mux", 17, 1 },
+ { "pipe0_tx2rx_loopbk", 16, 1 },
+ { "pipe0_tx_swing", 15, 1 },
+ { "pipe0_tx_margin", 12, 3 },
+ { "pipe0_tx_deemph", 11, 1 },
+ { "pipe0_tx_detectrx", 10, 1 },
+ { "pipe0_powerdown", 8, 2 },
+ { "phy_mac_phystatus", 0, 8 },
+ { "PCIE_PDEBUG_REG_0x1b", 0x1b, 0 },
+ { "pipe0_rx7_eq_in_prog", 31, 1 },
+ { "pipe0_rx7_eq_invld_req", 30, 1 },
+ { "pipe0_rx7_syncheader", 28, 2 },
+ { "pipe0_rx6_eq_in_prog", 27, 1 },
+ { "pipe0_rx6_eq_invld_req", 26, 1 },
+ { "pipe0_rx6_syncheader", 24, 2 },
+ { "pipe0_rx5_eq_in_prog", 23, 1 },
+ { "pipe0_rx5_eq_invld_req", 22, 1 },
+ { "pipe0_rx5_syncheader", 20, 2 },
+ { "pipe0_rx4_eq_in_prog", 19, 1 },
+ { "pipe0_rx4_eq_invld_req", 18, 1 },
+ { "pipe0_rx4_syncheader", 16, 2 },
+ { "pipe0_rx3_eq_in_prog", 15, 1 },
+ { "pipe0_rx3_eq_invld_req", 14, 1 },
+ { "pipe0_rx3_syncheader", 12, 2 },
+ { "pipe0_rx2_eq_in_prog", 11, 1 },
+ { "pipe0_rx2_eq_invld_req", 10, 1 },
+ { "pipe0_rx2_syncheader", 8, 2 },
+ { "pipe0_rx1_eq_in_prog", 7, 1 },
+ { "pipe0_rx1_eq_invld_req", 6, 1 },
+ { "pipe0_rx1_syncheader", 4, 2 },
+ { "pipe0_rx0_eq_in_prog", 3, 1 },
+ { "pipe0_rx0_eq_invld_req", 2, 1 },
+ { "pipe0_rx0_syncheader", 0, 2 },
+ { "PCIE_PDEBUG_REG_0x1c", 0x1c, 0 },
+ { "SI_ReqVFID", 24, 8 },
+ { "SI_ReqVec", 13, 11 },
+ { "SI_ReqTCVal", 10, 3 },
+ { "SI_ReqRdy", 9, 1 },
+ { "SI_ReqVld", 8, 1 },
+ { "AI", 0, 8 },
+ { "PCIE_PDEBUG_REG_0x1d", 0x1d, 0 },
+ { "GntSI", 31, 1 },
+ { "DropIntForFLR", 30, 1 },
+ { "SmArb", 27, 3 },
+ { "SmDefr", 24, 3 },
+ { "sys_int", 16, 8 },
+ { "CFG_INTXClr", 8, 8 },
+ { "PIO_INTXClr", 0, 8 },
+ { "PCIE_PDEBUG_REG_0x1e", 0x1e, 0 },
+ { "PLI_TABDatWrEn", 31, 1 },
+ { "TAB_RdEna", 30, 1 },
+ { "TAB_RdEna2", 19, 11 },
+ { "PLI_ReqAddr", 10, 9 },
+ { "PLI_ReqVFID", 2, 8 },
+ { "PLI_ReqTabHit", 1, 1 },
+ { "PLI_ReqRdVld", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x1f", 0x1f, 0 },
+ { "PLI_ReqVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x20", 0x20, 0 },
+ {"PLI_RspVld", 0, 32 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_pcie_pdbg_regs_21_to_40[] = {
+ { "PCIE_PDEBUG_REG_0x21", 0x21, 0 },
+ { "PLI_ReqPbaStart", 20, 12 },
+ { "PLI_ReqPbaEnd", 9, 11 },
+ { "PLI_ReqVFID", 2, 7 },
+ { "PLI_ReqPbaHit", 1, 1 },
+ { "PLI_ReqRdVld", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x22", 0x22, 0 },
+ { "GntSI1", 31, 1 },
+ { "GntSI2", 30, 1 },
+ { "GntSI3", 27, 3 },
+ { "GntSI4", 16, 11 },
+ { "GntSI5", 8, 8 },
+ { "GntSI6", 7, 1 },
+ { "GntSI7", 6, 1 },
+ { "GntSI8", 5, 1 },
+ { "GntSI9", 4, 1 },
+ { "GntSIa", 3, 1 },
+ { "GntAI", 2, 1 },
+ { "GntDB", 1, 1 },
+ { "GntDI", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x23", 0x23, 0 },
+ { "DI_ReqVld", 31, 1 },
+ { "DI_ReqRdy", 30, 1 },
+ { "DI_ReqWrEn", 19, 11 },
+ { "DI_ReqMsiEn", 18, 1 },
+ { "DI_ReqMsxEn", 17, 1 },
+ { "DI_ReqMsxVFIDMsk", 16, 1 },
+ { "DI_ReqWrEn2", 2, 14 },
+ { "DI_ReqRdEn", 1, 1 },
+ { "DI_ReqWrEn3", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x24", 0x24, 0 },
+ { "ven_msi_req_24", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x25", 0x25, 0 },
+ { "ven_msi_req", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x26", 0x26, 0 },
+ { "ven_msi_req", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x27", 0x27, 0 },
+ { "FID_STI_RspVld", 31, 1 },
+ { "TAB_StiRdEna", 30, 1 },
+ { "TAB_StiWrEna", 29, 1 },
+ { "TAB_StiRdEna2", 18, 11 },
+ { "PLI_ReqTabHit", 7, 11 },
+ { "GntSI", 0, 7 },
+ { "PCIE_PDEBUG_REG_0x28", 0x28, 0 },
+ { "PLI_ReqWrVld", 31, 1 },
+ { "PLI_ReqPbaHit", 30, 1 },
+ { "PLI_TABAddrLWrEn", 29, 1 },
+ { "PLI_TABAddrHWrEn", 28, 1 },
+ { "PLI_TABDatWrEn", 27, 1 },
+ { "PLI_TABMskWrEn", 26, 1 },
+ { "AI_ReqVld", 23, 3 },
+ { "AI_ReqVld2", 22, 1 },
+ { "AI_ReqRdy", 21, 1 },
+ { "ven_msi_req_28", 18, 3 },
+ { "ven_msi_req2", 11, 7 },
+ { "ven_msi_req3", 6, 5 },
+ { "ven_msi_req4", 3 , 3 },
+ { "ven_msi_req5", 2, 1 },
+ { "ven_msi_grant", 1, 1 },
+ { "ven_msi_req6", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x29", 0x29, 0 },
+ { "TRGT1_ReqDataVld", 16, 26 },
+ { "TRGT1_ReqDataVld2", 12, 4 },
+ { "TRGT1_ReqDataVld3", 11, 1 },
+ { "TRGT1_ReqDataVld4", 10, 1 },
+ { "TRGT1_ReqDataVld5", 9, 1 },
+ { "TRGT1_ReqDataVld6", 8, 1 },
+ { "TRGT1_ReqDataVld7", 4, 4 },
+ { "TRGT1_ReqDataVld8", 2, 2 },
+ { "TRGT1_ReqDataRdy", 1, 1 },
+ { "TRGT1_ReqDataVld0", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x2a", 0x2a, 0 },
+ { "TRGT1_ReqDataVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x2b", 0x2b, 0 },
+ { "radm_trgt1_addr", 20, 12 },
+ { "radm_trgt1_dwen", 16, 4 },
+ { "radm_trgt1_fmt", 14, 2 },
+ { "radm_trgt1_type", 9, 5 },
+ { "radm_trgt1_in_membar_range", 6, 3 },
+ { "radm_trgt1_ecrc_err", 5, 1 },
+ { "radm_trgt1_dllp_abort", 4, 1 },
+ { "radm_trgt1_tlp_abort", 3, 1 },
+ { "radm_trgt1_eot", 2, 1 },
+ { "radm_trgt1_dv_2b", 1, 1 },
+ { "radm_trgt1_hv_2b", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x2c", 0x2c, 0 },
+ { "StateMPIO", 29, 3 },
+ { "StateCPL", 25, 4 },
+ { "StateAlin", 22, 3 },
+ { "StatePL", 19, 3 },
+ { "StateMARsp", 18, 1 },
+ { "MA_TagsInUse", 11, 7 },
+ { "radm_trgt1_hsrdy", 10, 1 },
+ { "radm_trgt1_dsrdy", 9, 1 },
+ { "ALIND_ReqWrDataVld", 8, 1 },
+ { "FID_LkUpWrHdrVld", 7, 1 },
+ { "MPIO_WrVld", 6, 1 },
+ { "trgt1_radm_halt", 5, 1 },
+ { "radm_trgt1_dv_2c", 4, 1 },
+ { "radm_trgt1_dv_2c_2", 3, 1 },
+ { "radm_trgt1_tlp_abort_2c", 2, 1 },
+ { "radm_trgt1_dllp_abort_2c", 1, 1 },
+ { "radm_trgt1_ecrc_err_2c", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x2d", 0x2d, 0 },
+ { "radm_trgt1_hv_2d", 31, 1 },
+ { "radm_trgt1_dv_2d", 30, 1 },
+ { "radm_trgt1_hv2", 23, 7 },
+ { "radm_trgt1_hv3", 20, 3 },
+ { "radm_trgt1_hv4", 16, 4 },
+ { "radm_trgt1_hv5", 12, 4 },
+ { "radm_trgt1_hv6", 11, 1 },
+ { "radm_trgt1_hv7", 10, 1 },
+ { "radm_trgt1_hv8", 7, 3 },
+ { "radm_trgt1_hv9", 6, 1 },
+ { "radm_trgt1_hva", 5, 1 },
+ { "radm_trgt1_dsrdy_2d", 4, 1 },
+ { "radm_trgt1_WrCnt", 0, 4 },
+ { "PCIE_PDEBUG_REG_0x2e", 0x2e, 0 },
+ { "radm_trgt1_hv_2e", 30, 2 },
+ { "radm_trgt1_hv_2e_2", 20, 10 },
+ { "radm_trgt1_hv_we_3", 12, 8 },
+ { "ALIN_ReqDataVld4", 8, 4 },
+ { "ALIN_ReqDataVld5", 7, 1 },
+ { "ALIN_ReqDataVld6", 6, 1 },
+ { "ALIN_ReqDataVld7", 4, 2 },
+ { "ALIN_ReqDataVld8", 3, 1 },
+ { "ALIN_ReqDataVld9", 2, 1 },
+ { "ALIN_ReqDataRdy", 1, 1 },
+ { "ALIN_ReqDataVlda", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x2f", 0x2f, 0 },
+ {"ALIN_ReqDataVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x30", 0x30, 0 },
+ { "radm_trgt1_hv_30", 25, 7 },
+ { "PIO_WrCnt", 15, 10 },
+ { "ALIND_ReqWrCnt", 12, 3 },
+ { "FID_LkUpWrCnt", 9, 3 },
+ { "ALIND_ReqRdDataVld", 8, 1 },
+ { "ALIND_ReqRdDataRdy", 7, 1 },
+ { "ALIND_ReqRdDataVld2", 6, 1 },
+ { "ALIND_ReqWrDataVld3", 3, 3 },
+ { "ALIND_ReqWrDataVld4", 2, 1 },
+ { "ALIND_ReqWrDataRdyOpen", 1, 1 },
+ { "ALIND_ReqWrDataVld5", 0, 1 },
+ { "PCIE_PDEBUG_REG_0x31", 0x31, 0 },
+ { "ALIND_ReqWrDataVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x32", 0x32, 0 },
+ { "ALIND_ReqWrDataVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x33", 0x33, 0 },
+ { "ALIND_ReqWrDataVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x34", 0x34, 0 },
+ { "ALIND_ReqWrDataVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x35", 0x35, 0 },
+ { "MPIO_WrVld", 19, 13 },
+ { "FID_LkUpRdHdrVld", 18, 1 },
+ { "FID_LkUpRdHdrVld2", 17, 1 },
+ { "FID_LkUpRdHdrVld3", 16, 1 },
+ { "FID_LkUpRdHdrVld4", 15, 1 },
+ { "FID_LkUpRdHdrVld5", 14, 1 },
+ { "FID_LkUpRdHdrVld6", 13, 1 },
+ { "FID_LkUpRdHdrVld7", 12, 1 },
+ { "FID_LkUpRdHdrVld8", 11, 1 },
+ { "FID_LkUpRdHdrVld9", 10, 1 },
+ { "FID_LkUpRdHdrVlda", 9, 1 },
+ { "FID_LkUpRdHdrVldb", 8, 1 },
+ { "FID_LkUpRdHdrVldc", 7, 1 },
+ { "MPIO_WrVld1", 6, 1 },
+ { "MPIO_WrVld2", 5, 1 },
+ { "MPIO_WrVld3", 4, 1 },
+ { "MPIO_WrVld4", 0, 4 },
+ { "PCIE_PDEBUG_REG_0x36", 0x36, 0 },
+ { "MPIO_WrVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x37", 0x37, 0},
+ { "MPIO_WrVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x38", 0x38, 0 },
+ { "MPIO_WrVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x39", 0x39, 0 },
+ { "MPIO_WrVld", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x3a", 0x3a, 0 },
+ { "client0_tlp_vfunc_active", 31, 1 },
+ { "client0_tlp_vfunc_num", 24, 7 },
+ { "client0_tlp_func_num", 21, 3 },
+ { "client0_tlp_byte_en", 13, 8 },
+ { "client0_tlp_byte_len", 0, 13 },
+ { "PCIE_PDEBUG_REG_0x3b", 0x3b, 0 },
+ { "xadm_client0_halt", 31, 1 },
+ { "client0_tlp_dv", 30, 1 },
+ { "client0_addr_align_en", 29, 1 },
+ { "client0_cpl_bcm", 28, 1 },
+ { "client0_tlp_ep", 27, 1 },
+ { "client0_cpl_status", 24, 3 },
+ { "client0_tlp_td", 23, 1 },
+ { "client0_tlp_type", 18 , 5 },
+ { "client0_tlp_fmt", 16, 2 },
+ { "client0_tlp_bad_eot", 15, 1 },
+ { "client0_tlp_eot", 14, 1 },
+ { "client0_tlp_attr", 11, 3 },
+ { "client0_tlp_tc", 8, 3 },
+ { "client0_tlp_tid", 0, 8 },
+ { "PCIE_PDEBUG_REG_0x3c", 0x3c, 0 },
+ { "MEM_RspRRAVld", 31, 1 },
+ { "MEM_RspRRARdy", 30, 1 },
+ { "PIO_RspRRAVld", 29, 1 },
+ { "PIO_RspRRARdy", 28, 1 },
+ { "MEM_RspRdVld", 27, 1 },
+ { "MEM_RspRdRRARdy", 26, 1 },
+ { "PIO_RspRdVld", 25, 1 },
+ { "PIO_RspRdRRARdy", 24, 1 },
+ { "TGT_TAGQ_RdVld", 16 , 8},
+ { "CplTxnDisable", 8, 8 },
+ { "CplTxnDisable2", 7, 1 },
+ { "client0_tlp_hv", 0, 7 },
+ { "PCIE_PDEBUG_REG_0x3D", 0x3d, 0 },
+ { "pdebug_0x3D", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x3E", 0x3e, 0 },
+ { "pdebug_0x3E", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x3F", 0x3f, 0 },
+ { "pdebug_0x3F", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x40", 0x40, 0 },
+ { "pdebug_0x40", 0, 32 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_pcie_pdbg_regs_41_to_50[] = {
+ { "PCIE_PDEBUG_REG_0x41", 0x41, 0 },
+ { "pdebug_0x41", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x42", 0x42, 0 },
+ { "pdebug_0x42", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x43", 0x43, 0 },
+ { "pdebug_0x43", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x44", 0x44, 0 },
+ { "pdebug_0x44", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x45", 0x45, 0 },
+ { "pdebug_0x45", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x46", 0x46, 0 },
+ { "pdebug_0x46", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x47", 0x47, 0 },
+ { "pdebug_0x47", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x48", 0x48, 0 },
+ { "pdebug_0x48", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x49", 0x49, 0 },
+ { "pdebug_0x49", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x4a", 0x4a, 0 },
+ { "pdebug_0x4A", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x4b", 0x4b, 0 },
+ { "pdebug_0xaB", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x4c", 0x4c, 0 },
+ { "pdebug_0x4C", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x4d", 0x4d, 0 },
+ { "pdebug_0x4D", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x4e", 0x4e, 0 },
+ { "pdebug_0x4E", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x4f", 0x4f, 0 },
+ { "pdebug_0x4F", 0, 32 },
+ { "PCIE_PDEBUG_REG_0x50", 0x50, 0 },
+ { "pdebug_0x50", 0, 32 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_pcie_cdbg_regs_00_to_20[] = {
+ { "PCIE_CDEBUG_REG_0x0", 0x00, 0 },
+ { "PCIE_CDEBUG_REG_0x1", 0x01, 0 },
+ { "PCIE_CDEBUG_REG_0x2", 0x02, 0 },
+ { "FLR_ReqVld", 31, 1 },
+ { "D_RspVld", 28, 3 },
+ { "D_RspVld2", 27, 1 },
+ { "D_RspVld3", 26, 1 },
+ { "D_RspVld4", 25, 1 },
+ { "D_RspVld5", 24, 1 },
+ { "D_RspVld6", 20, 4 },
+ { "D_RspAFull", 16, 4 },
+ { "D_RdReqVld", 12, 4 },
+ { "D_RdReqAFull", 8, 4 },
+ { "D_WrReqVld", 4, 4 },
+ { "D_WrReqAFull", 0, 4 },
+ { "PCIE_CDEBUG_REG_0x3", 0x03, 0 },
+ { "C_ReqVld", 19, 13 },
+ { "C_RspVld2", 16, 3 },
+ { "C_RspVld3", 15, 1 },
+ { "C_RspVld4", 14, 1 },
+ { "C_RspVld5", 13, 1 },
+ { "C_RspVld6", 12, 1 },
+ { "C_RspVld7", 9, 3 },
+ { "C_RspAFull", 6, 3 },
+ { "C_ReqVld8", 3, 3 },
+ { "C_ReqAFull", 0, 3 },
+ { "PCIE_CDEBUG_REG_0x4", 0x04, 0 },
+ { "H_ReqVld", 7, 25 },
+ { "H_RspVld", 6, 1 },
+ { "H_RspVld2", 5, 1 },
+ { "H_RspVld3", 4, 1 },
+ { "H_RspVld4", 3, 1 },
+ { "H_RspAFull", 2, 1 },
+ { "H_ReqVld2", 1, 1 },
+ { "H_ReqAFull", 0, 1 },
+ { "PCIE_CDEBUG_REG_0x5", 0x05, 0 },
+ { "ER_RspVld", 16, 16 },
+ { "ER_ReqVld2", 5, 10 },
+ { "ER_ReqVld3", 2, 3 },
+ { "ER_RspVld4", 1, 1 },
+ { "ER_ReqVld5", 0, 1 },
+ { "PCIE_CDEBUG_REG_0x6", 0x06, 0 },
+ { "PL_BAR2_ReqVld", 4, 28 },
+ { "PL_BAR2_ReqVld2", 3, 1 },
+ { "PL_BAR2_ReqVlde", 2, 1 },
+ { "PL_BAR2_ReqFull", 1, 1 },
+ { "PL_BAR2_ReqVld4", 0, 1},
+ { "PCIE_CDEBUG_REG_0x7", 0x07, 0 },
+ {"PL_BAR2_ReqVld_7", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x8", 0x08, 0 },
+ {"PL_BAR2_ReqVld_8", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x9", 0x09, 0 },
+ {"PL_BAR2_ReqVld_9", 0, 32 },
+ { "PCIE_CDEBUG_REG_0xa", 0x0a, 0 },
+ { "VPD_RspVld", 20, 12 },
+ { "VPD_ReqVld2", 9, 11 },
+ { "VPD_ReqVld3", 6, 3 },
+ { "VPD_ReqVld4", 5, 1 },
+ { "VPD_ReqVld5", 3, 2 },
+ { "VPD_RspVld2", 2, 1 },
+ { "VPD_RspVld3", 1, 1 },
+ { "VPD_ReqVld6", 0, 1 },
+ { "PCIE_CDEBUG_REG_0xb", 0x0b, 0 },
+ { "MA_ReqDataVld", 28, 4 },
+ { "MA_ReqAddrVld", 27, 1 },
+ { "MA_ReqAddrVld2", 26, 1 },
+ { "MA_RspDataVld2", 22, 4 },
+ { "MA_ReqAddrVld3", 20, 2 },
+ { "MA_ReqAddrVld4", 4, 16 },
+ { "MA_ReqAddrVld5", 3, 1 },
+ { "MA_ReqAddrVld6", 2, 1 },
+ { "MA_ReqAddrRdy", 1, 1 },
+ { "MA_ReqAddrVld7", 0, 1 },
+ { "PCIE_CDEBUG_REG_0xc", 0x0c, 0 },
+ { "MA_ReqAddrVld_c", 0, 32 },
+ { "PCIE_CDEBUG_REG_0xd", 0x0d, 0 },
+ { "MA_ReqAddrVld_d", 0, 32 },
+ { "PCIE_CDEBUG_REG_0xe", 0x0e, 0 },
+ { "MA_ReqAddrVld_e", 0, 32 },
+ { "PCIE_CDEBUG_REG_0xf", 0x0f, 0 },
+ { "MA_ReqAddrVld_f", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x10", 0x10, 0 },
+ { "MA_ReqAddrVld_10", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x11", 0x11, 0 },
+ { "MA_ReqAddrVld_11", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x12", 0x12, 0 },
+ { "MA_ReqAddrVld_12", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x13", 0x13, 0 },
+ { "MA_ReqAddrVld_13", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x14", 0x14, 0 },
+ { "MA_ReqAddrVld_14", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x15", 0x15, 0 },
+ { "PLM_ReqVld", 19, 13 },
+ { "PLM_ReqVld2", 18, 1 },
+ { "PLM_RspVld3", 17, 1 },
+ { "PLM_ReqVld4", 16, 1 },
+ { "PLM_ReqVld5", 15, 1 },
+ { "PLM_ReqVld6", 14, 1 },
+ { "PLM_ReqVld7", 13, 1 },
+ { "PLM_ReqVld8", 12, 1 },
+ { "PLM_ReqVld9", 4, 8 },
+ { "PLM_ReqVlda", 1, 3 },
+ { "PLM_ReqVldb", 0, 1 },
+ { "PCIE_CDEBUG_REG_0x16", 0x16, 0 },
+ { "PLM_RspVld", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x17", 0x17, 0 },
+ { "cdebug_0x17", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x18", 0x18, 0 },
+ { "cdebug_0x18", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x19", 0x19, 0 },
+ { "cdebug_0x19", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x1A", 0x1a, 0 },
+ { "cdebug_0x1A", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x1B", 0x1b, 0 },
+ { "cdebug_0x1B", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x1C", 0x1c, 0 },
+ { "cdebug_0x1C", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x1D", 0x1d, 0 },
+ { "cdebug_0x1D", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x1E", 0x1e, 0 },
+ { "cdebug_0x1E", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x1F", 0x1f, 0 },
+ { "cdebug_0x1F", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x20", 0x20, 0 },
+ { "cdebug_0x20", 0, 32 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_pcie_cdbg_regs_21_to_37[] = {
+ { "PCIE_CDEBUG_REG_0x21", 0x21, 0 },
+ { "cdebug_0x21", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x22", 0x22, 0 },
+ { "cdebug_0x22", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x23", 0x23, 0 },
+ { "cdebug_0x23", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x24", 0x24, 0 },
+ { "cdebug_0x24", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x25", 0x25, 0 },
+ { "cdebug_0x25", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x26", 0x26, 0 },
+ { "cdebug_0x26", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x27", 0x27, 0 },
+ { "cdebug_0x27", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x28", 0x28, 0 },
+ { "cdebug_0x28", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x29", 0x29, 0 },
+ { "cdebug_0x29", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x2a", 0x2a, 0 },
+ { "cdebug_0x2A", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x2b", 0x2b, 0 },
+ { "cdebug_0x2B", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x2c", 0x2c, 0 },
+ { "cdebug_0x2C", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x2d", 0x2d, 0 },
+ { "cdebug_0x2D", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x2e", 0x2e, 0 },
+ { "cdebug_0x2E", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x2f", 0x2f, 0 },
+ { "cdebug_0x2F", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x30", 0x30, 0 },
+ { "cdebug_0x30", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x31", 0x31, 0 },
+ { "cdebug_0x31", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x32", 0x32, 0 },
+ { "cdebug_0x32", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x33", 0x33, 0 },
+ { "cdebug_0x33", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x34", 0x34, 0 },
+ { "cdebug_0x34", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x35", 0x35, 0 },
+ { "cdebug_0x35", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x36", 0x36, 0 },
+ { "cdebug_0x36", 0, 32 },
+ { "PCIE_CDEBUG_REG_0x37", 0x37, 0 },
+ { "cdebug_0x37", 0, 32 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_pm_rx_regs_10000_to_10020[] = {
+ { "PM_TX_ISPI_DBG_4B_DATA0", 0x10000, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_RX_ISPI_DBG_4B_DATA1", 0x10001, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_RX_ISPI_DBG_4B_DATA2", 0x10002, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_RX_ISPI_DBG_4B_DATA3", 0x10003, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_RX_ISPI_DBG_4B_DATA4", 0x10004, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_RX_ISPI_DBG_4B_DATA5", 0x10005, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_RX_ISPI_DBG_4B_DATA6", 0x10006, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_RX_ISPI_DBG_4B_DATA7", 0x10007, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_RX_ISPI_DBG_4B_DATA8", 0x10008, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_RX_OSPI_DBG_4B_DATA0", 0x10009, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_RX_OSPI_DBG_4B_DATA1", 0x1000a, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_RX_OSPI_DBG_4B_DATA2", 0x1000b, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_RX_OSPI_DBG_4B_DATA3", 0x1000c, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_RX_OSPI_DBG_4B_DATA4", 0x1000d, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_RX_OSPI_DBG_4B_DATA5", 0x1000e, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_RX_OSPI_DBG_4B_DATA6", 0x1000f, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_RX_OSPI_DBG_4B_DATA7", 0x10010, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_RX_OSPI_DBG_4B_DATA8", 0x10011, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_RX_OSPI_DBG_4B_DATA9", 0x10012, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_RX_DBG_STAT_MSB", 0x10013, 0 },
+ { "stat_msb", 0, 32 },
+ { "PM_RX_DBG_STAT_LSB", 0x10014, 0 },
+ { "stat_lsb", 0, 32 },
+ { "PM_RX_DBG_RSVD_FLIT_CNT", 0x10015, 0 },
+ { "i_to_o_path_rsvd_flit_backup", 12, 4 },
+ { "i_to_o_path_rsvd_flit", 8, 4 },
+ { "prfch_rsvd_flit", 4, 4 },
+ { "ospi_rsvd_flit", 0, 4 },
+ { "PM_RX_SDC_EN", 0x10016, 0 },
+ { "sdc_en", 0, 1 },
+ { "PM_RX_INOUT_FIFO_DBG_CHNL_SEL", 0x10017, 0 },
+ { "chnl_3_sel", 3, 1 },
+ { "chnl_2_sel", 2, 1 },
+ { "chnl_1_sel", 1, 1 },
+ { "chnl_0_sel", 0, 1 },
+ { "PM_RX_INOUT_FIFO_DBG_WR", 0x10018, 0 },
+ { "o_fifo_write", 3, 1 },
+ { "i_fifo_write", 2, 1 },
+ { "o_fifo_read", 1, 1 },
+ { "i_fifo_read", 0, 1 },
+ { "PM_RX_INPUT_FIFO_STR_FWD_EN", 0x10019, 0 },
+ { "ispi_str_fwd_en", 0, 1 },
+ { "PM_RX_PRFTCH_ACROSS_BNDLE_EN", 0x1001a, 0 },
+ { "prftch_across_bndle_en", 0, 1 },
+ { "PM_RX_PRFTCH_WRR_ENABLE", 0x1001b, 0 },
+ { "prftch_wrr_enable", 0, 1 },
+ { "PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT", 0x1001c, 0 },
+ { "chnl1_max_deficit_cnt", 16, 16 },
+ { "chnl0_max_deficit_cnt", 0, 16 },
+ { "PM_RX_FEATURE_EN", 0x1001d, 0 },
+ { "pio_ch_deficit_ctl_en", 0, 1 },
+ { "PM_RX_CH0_OSPI_DEFICIT_THRSHLD", 0x1001e, 0 },
+ { "CH0_OSPI_DEFICIT_THRSHLD", 0, 12 },
+ { "PM_RX_CH1_OSPI_DEFICIT_THRSHLD", 0x1001f, 0 },
+ { "CH1_OSPI_DEFICIT_THRSHLD", 0, 12 },
+ { "PM_RX_INT_CAUSE_MASK_HALT", 0x10020, 0 },
+ { "INT_CAUSE_MASK", 0, 32 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_pm_rx_regs_10021_to_1002c[] = {
+ { "PM_RX_DBG_STAT0", 0x10021, 0 },
+ { "rx_rd_i_busy", 29, 1 },
+ { "rx_wr_to_o_busy", 28, 1 },
+ { "rx_m_to_o_busy", 27, 1 },
+ { "rx_i_to_m_busy", 26, 1 },
+ { "rx_pcmd_fb_only", 25, 1 },
+ { "rx_pcmd_mem", 24, 1 },
+ { "rx_pcmd_bypass", 23, 1 },
+ { "rx_pcmd_eop", 22, 1 },
+ { "rx_dumplicate_pcmd_eop", 21, 1 },
+ { "rx_pcmd_eob", 20, 1 },
+ { "rx_pcmd_fb", 16, 4 },
+ { "rx_pcmd_len", 0, 16 },
+ { "PM_RX_DBG_STAT1", 0x10022, 0 },
+ { "rx_PCMD0_mem", 30, 1 },
+ { "rx_free_ospi_cnt0", 18, 12 },
+ { "rx_PCMD0_flit_len", 6, 12 },
+ { "rx_PCMD0_cmd", 2, 4 },
+ { "rx_ofifo_full0", 1, 1 },
+ { "rx_PCMD0_bypass", 0, 1 },
+ { "PM_RX_DBG_STAT2", 0x10023, 0 },
+ { "rx_PCMD1_mem", 30, 1 },
+ { "rx_free_ospi_cnt1", 18, 12 },
+ { "rx_PCMD1_flit_len", 6, 12 },
+ { "rx_PCMD1_cmd", 2, 4 },
+ { "rx_ofifo_full1", 1, 1 },
+ { "rx_PCMD1_bypass", 0, 1 },
+ { "PM_RX_DBG_STAT3", 0x10024, 0 },
+ { "rx_set_pcmd_res_rdy_rd", 10, 2 },
+ { "rx_issued_prefetch_rd_e_clr", 8, 2 },
+ { "rx_issued_prefetch_rd", 6, 2 },
+ { "rx_pcmd_res_rdy", 4, 2 },
+ { "rx_db_vld", 3, 1 },
+ { "rx_first_bundle", 1, 2 },
+ { "rx_sdc_drdy", 0, 1 },
+ { "PM_RX_DBG_STAT4", 0x10025, 0 },
+ { "rx_pcmd_vld", 26, 1 },
+ { "rx_pcmd_to_ch", 25, 1 },
+ { "rx_pcmd_from_ch", 23, 2 },
+ { "rx_line", 18, 5 },
+ { "rx_iespi_TxValid", 14, 4 },
+ { "rx_iespi_TxFull", 10, 4 },
+ { "rx_PCMD_srdy", 8, 2 },
+ { "rx_PCMD_drdy", 6, 2 },
+ { "rx_pcmd_cmd", 2 , 4},
+ { "rx_pcmd_res_rdy", 0, 2 },
+ { "PM_RX_DBG_STAT5", 0x10026, 0 },
+ { "rx_atlst_1_pcmd_ch1", 29, 1 },
+ { "rx_atlst_1_pcmd_ch0", 28, 1 },
+ { "rx_pcmd_drdy", 26, 2 },
+ { "rx_pcmd_srdy", 24, 2 },
+ { "rx_Ispi_TxValid", 20, 4 },
+ { "rx_Ispi_Full", 16, 4 },
+ { "rx_Ospi_TxValid", 14, 2 },
+ { "rx_Ospi_Full", 12, 2 },
+ { "rx_E_RxValid", 8, 4 },
+ { "rx_E_RxAFull", 4, 4 },
+ { "rx_C_TxValid", 2, 2 },
+ { "rx_C_TxAFull", 0, 2 },
+ { "PM_RX_DBG_STAT6", 0x10027, 0 },
+ { "rx_m_intrnl_fifo_cnt", 4, 2 },
+ { "rx_M_ReqAddrRdy", 3, 1 },
+ { "rx_M_ReqWrite", 2, 1 },
+ { "rx_M_ReqDataVld", 1, 1 },
+ { "rx_M_ReqDataRdy", 0, 1 },
+ { "PM_RX_DBG_STAT7", 0x10028, 0 },
+ { "rx_pcmd1_free_cnt", 7, 7 },
+ { "rx_pcmd0_free_cnt", 0, 7 },
+ { "PM_RX_DBG_STAT8", 0x10029, 0 },
+ { "rx_In_Eop_Cnt3", 28, 4 },
+ { "rx_In_Eop_Cnt2", 24, 4 },
+ { "rx_In_Eop_Cnt1", 20, 4 },
+ { "rx_In_Eop_Cnt0", 16, 4 },
+ { "rx_In_Sop_Cnt3", 12, 4 },
+ { "rx_In_Sop_Cnt2", 8, 4 },
+ { "rx_In_Sop_Cnt1", 4, 4 },
+ { "rx_In_Sop_Cnt0", 0, 4 },
+ { "PM_RX_DBG_STAT9", 0x1002a, 0 },
+ { "rx_rsvd0", 28, 4 },
+ { "rx_rsvd1", 24, 4 },
+ { "rx_Out_Eop_Cnt1", 20, 4 },
+ { "rx_Out_Eop_Cnt0", 16, 4 },
+ { "rx_rsvd2", 12, 4 },
+ { "rx_rsvd3", 8, 4 },
+ { "rx_Out_Sop_Cnt1", 4, 4 },
+ { "rx_Out_Sop_Cnt0", 0, 4 },
+ { "PM_RX_DBG_STAT10", 0x1002b, 0 },
+ { "rx_ch_deficit_blowed", 24, 1 },
+ { "rx_ch1_deficit", 12, 12 },
+ { "rx_ch0_deficit", 0, 12 },
+ { "PM_RX_DBG_STAT11", 0x1002c, 0 },
+ { "rx_bundle_len_srdy", 30, 2 },
+ { "rx_rsvd11_1", 28, 2 },
+ { "rx_bundle_len1", 16, 12 },
+ { "rx_rsvd11", 12, 4 },
+ { "rx_bundle_len0", 0, 12 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_pm_tx_regs_10000_to_10020[] = {
+ { "PM_TX_ISPI_DBG_4B_DATA0", 0x10000, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_TX_ISPI_DBG_4B_DATA1", 0x10001, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_TX_ISPI_DBG_4B_DATA2", 0x10002, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_TX_ISPI_DBG_4B_DATA3", 0x10003, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_TX_ISPI_DBG_4B_DATA4", 0x10004, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_TX_ISPI_DBG_4B_DATA5", 0x10005, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_TX_ISPI_DBG_4B_DATA6", 0x10006, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_TX_ISPI_DBG_4B_DATA7", 0x10007, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_TX_ISPI_DBG_4B_DATA8", 0x10008, 0 },
+ { "ispi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA0", 0x10009, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA1", 0x1000a, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA2", 0x1000b, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA3", 0x1000c, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA4", 0x1000d, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA5", 0x1000e, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA6", 0x1000f, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA7", 0x10010, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA8", 0x10011, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA9", 0x10012, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA10", 0x10013, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA11", 0x10014, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA12", 0x10015, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA13", 0x10016, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA14", 0x10017, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA15", 0x10018, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_OSPI_DBG_4B_DATA16", 0x10019, 0 },
+ { "ospi_dbg_data", 0, 32 },
+ { "PM_TX_DBG_STAT_MSB", 0x1001a, 0 },
+ { "stat_msb", 0, 32 },
+ { "PM_TX_DBG_STAT_LSB", 0x1001b, 0 },
+ { "stat_lsb", 0, 32 },
+ { "PM_TX_DBG_RSVD_FLIT_CNT", 0x1001c, 0 },
+ { "i_to_o_path_rsvd_flit_backup", 12, 4 },
+ { "i_to_o_path_rsvd_flit", 8, 4 },
+ { "prfch_rsvd_flit", 4, 4 },
+ { "ospi_rsvd_flit", 0, 4 },
+ { "PM_TX_SDC_EN", 0x1001d, 0 },
+ { "sdc_en", 0, 1 },
+ { "PM_TX_INOUT_FIFO_DBG_CHNL_SEL", 0x1001e, 0 },
+ { "chnl_3_sel", 3, 1 },
+ { "chnl_2_sel", 2, 1 },
+ { "chnl_1_sel", 1, 1 },
+ { "chnl_0_sel", 0, 1 },
+ { "PM_TX_INOUT_FIFO_DBG_WR", 0x1001f, 0 },
+ { "o_fifo_write", 3, 1 },
+ { "i_fifo_write", 2, 1 },
+ { "o_fifo_read", 1, 1 },
+ { "i_fifo_read", 0, 1 },
+ { "PM_TX_INPUT_FIFO_STR_FWD_EN", 0x10020, 0 },
+ { "ispi_str_fwd_en", 0, 1 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_pcie_config_regs_00_to_208[] = {
+ { "PCIE_DEVID_VENID", 0x00, 0 },
+ { "VendorID", 0, 16 },
+ { "DeviceID", 16, 16 },
+ { "PCIE_STAT_CMD", 0x04, 0 },
+ { "IOEnable", 0, 1 },
+ { "MemEnable", 1, 1 },
+ { "BusMasterEnable", 2, 1 },
+ { "Rsvdl", 3, 3 },
+ { "PERREnable", 6, 1 },
+ { "Rsvd2", 7, 1 },
+ { "SERREnable", 8, 1 },
+ { "Rsvd3", 9, 1 },
+ { "IntDisable", 10, 1 },
+ { "Rsvd4", 11, 8 },
+ { "IntStatus", 19, 1 },
+ { "CapList", 20, 1 },
+ { "Rsvd5", 21, 3 },
+ { "MstDatParErr", 24, 1 },
+ { "Rsvd6", 25, 2 },
+ { "SigTgtAbort", 27, 1 },
+ { "RcvTgtAbort", 28, 1 },
+ { "RcvMstAbort", 29, 1 },
+ { "SigSERR", 30, 1 },
+ { "DetPERR", 31, 1 },
+ { "PCIE_CCODE_REVID", 0x08, 0 },
+ { "RevisionID", 0, 8, },
+ { "ClassCode", 8, 24 },
+ { "PCIE_BIST_HDR_TMR_CLS", 0xc, 0 },
+ { "CacheLineSize", 0, 8 },
+ { "MstLatTimer", 8, 8 },
+ { "HdrType", 16, 8 },
+ { "BIST", 24, 8 },
+ { "PCIE_BAR0", 0x10, 0 },
+ { "MemSpaceInd", 0, 1 },
+ { "Type", 1, 2 },
+ { "Prefetchable", 3, 1 },
+ { "BaseAddress", 4, 28 },
+ { "PCIE_BAR1", 0x14, 0 },
+ { "PCIE_BAR2", 0x18, 0 },
+ { "MemSpaceInd", 0, 1 },
+ { "Type", 1, 2 },
+ { "Prefetchable", 3, 1 },
+ { "BaseAddress", 4, 28 },
+ { "PCIE_BAR3", 0x1c, 0 },
+ { "PCIE_BAR4", 0x20, 0 },
+ { "MemSpaceInd", 0, 1 },
+ { "Type", 1, 2 },
+ { "Prefetchable", 3, 1 },
+ { "BaseAddress", 4, 28 },
+ { "PCIE_BAR5", 0x24, 0 },
+ { "PCIE_CIS", 0x28, 0 },
+ { "PCIE_SSID_SSVENID", 0x2c, 0 },
+ { "SSVenID", 0, 16 },
+ { "SSID", 16, 16 },
+ { "PCIE_EXPROM", 0x30, 0 },
+ { "ExpROMEn", 0, 1 },
+ { "Rsvd", 1, 10 },
+ { "BaseAddr", 11, 21 },
+ { "PCIE_CAP_PTR", 0x34, 0 },
+ { "CapPtr", 0, 8 },
+ { "Rsvd", 8, 24 },
+ { "PCIE_INT_LINE_PIN", 0x3c, 0 },
+ { "IntLine", 0, 8 },
+ { "IntPin", 8, 8 },
+ { "Rsvd", 16, 16 },
+ { "PCIE_PM_CAP", 0x40, 0 },
+ { "PMCapID", 0, 8 },
+ { "NextCapPtr", 8, 8 },
+ { "PMVer", 16, 3 },
+ { "PMEClock", 19, 1 },
+ { "Rsvd", 20, 1 },
+ { "DSI", 21, 1 },
+ { "AuxCur", 22, 3 },
+ { "D1Sup", 25, 1 },
+ { "D2Sup", 26, 1 },
+ { "PMESup", 27, 5 },
+ { "PCIE_MSI_CAP", 0x50, 0 },
+ { "MSICapID", 0, 8 },
+ { "NextCapPtr", 8, 8 },
+ { "MSIEn", 16, 1 },
+ { "MultMsgCap", 17, 3 },
+ { "MultMsgEn", 20, 3 },
+ { "MSI64Cap", 23, 1 },
+ { "PerVecMaskCap", 24, 1 },
+ { "Rsvd", 25, 7 },
+ { "PCIE_MSI_ADDR", 0x54, 0 },
+ { "Rsvd", 0, 2 },
+ { "MsgAddr", 2, 30 },
+ { "PCIE_MSI_UPR_ADDR", 0x58, 0 },
+ { "MsgUprAddr", 0, 32 },
+ { "PCIE_MSI_DATA", 0x5c, 0 },
+ { "MsgData", 0, 16 },
+ { "Rsvd", 16, 16 },
+ { "PCIE_MSI_MASK", 0x60, 0 },
+ { "MSIMask", 0, 32 },
+ { "PCIE_MSI_PND", 0x64, 0 },
+ { "MSIPnd", 0, 32 },
+ { "PCIE_PCIE_CAP", 0x70, 0 },
+ { "PCIECapID", 0, 8 },
+ { "NextCapPtr", 8, 8 },
+ { "PCIECapVer", 16, 4 },
+ { "DeviceType", 20, 4 },
+ { "SlotImpl", 24, 1 },
+ { "IntMsgNum", 25, 5 },
+ { "Rsvd", 30, 2 },
+ { "PCIE_DEV_CAP", 0x74, 0 },
+ { "MaxPyldSzSup", 0, 3 },
+ { "PhantomFuncSup", 3, 2 },
+ { "ExtTagSup", 5, 1 },
+ { "L0sAccLat", 6, 3 },
+ { "L1AccLat", 9, 3 },
+ { "Rsvd1", 13, 3 },
+ { "RoleBasedErr", 15, 1 },
+ { "Rsvd2", 16, 2 },
+ { "CapSlotPwrLmtVal", 18, 8 },
+ { "CapSlotPwrLmtScl", 26, 2 },
+ { "FLRCap", 28, 1 },
+ { "Rsvd3", 29, 3 },
+ { "PCIE_DEV_STAT_CNTL", 0x78, 0 },
+ { "CorErrRptEn", 0, 1 },
+ { "NonFatErrRptEn", 1, 1 },
+ { "FatErrRptEn", 2, 1 },
+ { "UnSupReqRptEn", 3, 1 },
+ { "RlxOrdEn", 4, 1 },
+ { "MaxPyldSz", 5, 3 },
+ { "ExtTagEn", 8, 1 },
+ { "PhantomFuncEn", 9, 1 },
+ { "AuxPwrPMEn", 10, 1 },
+ { "NoSnoopEn", 11, 1 },
+ { "MaxRdReqSz", 12, 3 },
+ { "InitiateFLR", 15, 1 },
+ { "CorErrDet", 16, 1 },
+ { "NonFatErrDet", 17, 1 },
+ { "FatErrDet", 18, 1 },
+ { "UnSupReqDet", 19, 1 },
+ { "AuxPwrDet", 20, 1 },
+ { "TxnPnd", 21, 1 },
+ { "Rsvd", 22, 10 },
+ { "PCIE_LINK_CAP", 0x7c, 0 },
+ { "MaxLinkSpeed", 0, 4 },
+ { "MaxLinkWidth", 4, 6 },
+ { "ASPMSup", 10, 2 },
+ { "L0sExitLat", 12, 3 },
+ { "L1ExitLat", 15, 3 },
+ { "ClkPwrMgmt", 18, 1 },
+ { "SurpriseDnErrRptCap", 19, 1 },
+ { "DLLActvRptCap", 20, 1 },
+ { "LnkBWNotifCap", 21, 1 },
+ { "ASPMOptComp", 22, 1 },
+ { "Rsvd", 23, 1 },
+ { "PortNum", 24, 8 },
+ { "PCIE_LINK_STAT_CNTL", 0x80, 0 },
+ { "ASPMCtl", 0, 2 },
+ { "Rsvd1", 2, 1 },
+ { "RCB", 3, 1 },
+ { "LinkDisable", 4, 1 },
+ { "RetrainLink", 5, 1 },
+ { "ComClkCfg", 6, 1 },
+ { "ExtendedSync", 7, 1 },
+ { "ClkPwrMgmtEn", 8, 1 },
+ { "HWAutoWidthDis", 9, 1 },
+ { "LnkBWMgmtIntEn", 10, 1 },
+ { "LnkAutoBWIntEn", 11, 1 },
+ { "Rsvd2", 12, 4 },
+ { "CurLinkSpeed", 16, 4 },
+ { "NegLinkWidth", 20, 6 },
+ { "Rsvd3", 26, 1 },
+ { "LnkTraining", 27, 1 },
+ { "SlotClkCfg", 28, 1 },
+ { "DLLActive", 29, 1 },
+ { "LnkBWMgmtStat", 30, 1 },
+ { "LnkAutoBWStat", 31, 1 },
+ { "PCIE_DEV_CAP2", 0x94, 0 },
+ { "CplTORangesSup", 0, 4 },
+ { "CplTODisSup", 4, 1 },
+ { "ARIFwdSup", 5, 1 },
+ { "AtomicOpRouteSup", 5, 1 },
+ { "32bAtomicOpCplSup", 7, 1 },
+ { "64bAtomicOpCplSup", 8, 1 },
+ { "128bCASCplSup", 9, 1 },
+ { "NoROPRPRPass", 10, 1 },
+ { "LTRMechSupp", 11, 1 },
+ { "TPHCplSupp", 12, 2 },
+ { "Rsvd1", 14, 4 },
+ { "OBFFSupp", 18, 2 },
+ { "ExtFmtSupp", 20, 1 },
+ { "EndEndTLPPrSupp", 21, 1 },
+ { "MaxEndEndTLPPr", 22, 2 },
+ { "Rsvd2", 24, 8 },
+ { "PCIE_DEV_STAT_CNTL2", 0x98, 0 },
+ { "CplTOValue", 0, 4 },
+ { "CplTODis", 4, 1 },
+ { "ARIFwdEn", 5, 1 },
+ { "AtomicOpRqstEn", 6, 1 },
+ { "AtomicOpEgBlock", 7, 1 },
+ { "IDORqstEn", 8, 1 },
+ { "IDOCplEn", 9, 1 },
+ { "LTRMechEn", 10, 1 },
+ { "Rsvd1", 11, 2 },
+ { "OBFFEn", 13, 2 },
+ { "EndEndTLPPrBlock", 15, 1 },
+ { "Rsvd2", 16, 16 },
+ { "PCIE_LINK_CAP2", 0x9c, 0 },
+ { "Rsvd1", 0, 1 },
+ { "SupLinkSpeeds", 1, 7 },
+ { "CrossLinkSup", 8, 1 },
+ { "Rsvd2", 9, 23 },
+ { "PCIE_LINK_STAT_CNTL2", 0xa0, 0 },
+ { "TarLnkSpeed", 0, 4 },
+ { "EnterComp", 4, 1 },
+ { "HWAutoSpeedDis", 5, 1 },
+ { "SelDeEmph", 6, 1 },
+ { "TxMargin", 7, 3 },
+ { "EnterModComp", 10, 1 },
+ { "CompSOS", 11, 1 },
+ { "CompDeEmph", 12, 4 },
+ { "CurDeEmph", 16, 1 },
+ { "EqComplete", 17, 1 },
+ { "EqPh1Succ", 18, 1 },
+ { "EqPh2Succ", 19, 1 },
+ { "EqPh3Succ", 20, 1 },
+ { "LinkEqRqst", 21, 1 },
+ { "Rsvd", 22, 10 },
+ { "PCIE_MSIX_CAP", 0xb0, 0 },
+ { "MSIXCapID", 0, 8 },
+ { "NextCapPtr", 8, 8 },
+ { "TableSize", 16, 11 },
+ { "Rsvd", 27, 3 },
+ { "FuncMask", 30, 1 },
+ { "MSIXEn", 31, 1 },
+ { "PCIE_MSIX_TBL_OFST_BIR", 0xb4, 0 },
+ { "TblBIR", 0, 3 },
+ { "TblOfst", 3, 29 },
+ { "PCIE_MSIX_PBA_OFST_BIR", 0xb8, 0 },
+ { "PBABIR", 0, 3 },
+ { "PBAOfst", 3, 29 },
+ { "PCIE_VPD_CAP", 0xd0, 0 },
+ { "VPDCapID", 0, 8 },
+ { "NextCapPtr", 8, 8 },
+ { "VPDAddr", 16, 15 },
+ { "VPDFBit", 31, 1 },
+ { "PCIE_VPD_DATA", 0xd4, 0 },
+ { "Data", 0, 32 },
+ { "PCIE_AER_CAP", 0x100, 0 },
+ { "AERCapID", 0, 16 },
+ { "AERCapVer", 16, 4 },
+ { "NextCapPtr", 20, 12 },
+ { "PCIE_AER_UNCOR_ERR_STAT", 0x104, 0 },
+ { "Undefined", 0, 1 },
+ { "Rsvd1", 1, 3 },
+ { "DLLProtErr", 4, 1 },
+ { "SurpriseDnErr", 5, 1 },
+ { "Rsvd2", 6, 6 },
+ { "PsndTLP", 12, 1 },
+ { "FlowCtlProtErr", 13, 1 },
+ { "ComplTO", 14, 1 },
+ { "ComplAbort", 15, 1 },
+ { "UnExpCpl", 16, 1 },
+ { "RcvrOFlow", 17, 1 },
+ { "MalTLP", 18, 1 },
+ { "ECRCErr", 19, 1 },
+ { "UnSupReqErr", 20, 1 },
+ { "ACSViol", 21, 1 },
+ { "UnIntErr", 22, 1 },
+ { "MCBlockTLP", 23, 1 },
+ { "AtomicOPEgBlock", 24, 1 },
+ { "TLPPrBlockErr", 25, 1 },
+ { "Rsvd3", 26, 6 },
+ { "PCIE_AER_UNCOR_ERR_MASK", 0x108, 0 },
+ { "Rsvd1", 0, 4 },
+ { "DLLProtErr", 4, 1 },
+ { "SurpriseDnErr", 5, 1 },
+ { "Rsvd2", 6, 6 },
+ { "PsndTLP", 12, 1 },
+ { "FlowCtlProtErr", 13, 1 },
+ { "ComplTO", 14, 1 },
+ { "ComplAbort", 15, 1 },
+ { "UnExpCpl", 16, 1 },
+ { "RcvrOFlow", 17, 1 },
+ { "MalTLP", 18, 1 },
+ { "ECRCErr", 19, 1 },
+ { "UnSupReqErr", 20, 1 },
+ { "ACSViol", 21, 1 },
+ { "UnIntErr", 22, 1 },
+ { "MCBlockTLP", 23, 1 },
+ { "AtomicOPEgBlock", 24, 1 },
+ { "TLPPrBlockErr", 25, 1 },
+ { "Rsvd3", 26, 6 },
+ { "PCIE_AER_UNCOR_ERR_SEV", 0x10c, 0 },
+ { "Rsvd1", 0, 4 },
+ { "DLLProtErr", 4, 1 },
+ { "SurpriseDnErr", 5, 1 },
+ { "Rsvd2", 6, 6 },
+ { "PsndTLP", 12, 1 },
+ { "FlowCtlProtErr", 13, 1 },
+ { "ComplTO", 14, 1 },
+ { "ComplAbort", 15, 1 },
+ { "UnExpCpl", 16, 1 },
+ { "RcvrOFlow", 17, 1 },
+ { "MalTLP", 18, 1 },
+ { "ECRCErr", 19, 1 },
+ { "UnSupReqErr", 20, 1 },
+ { "ACSViol", 21, 1 },
+ { "UnIntErr", 22, 1 },
+ { "MCBlockTLP", 23, 1 },
+ { "AtomicOPEgBlock", 24, 1 },
+ { "TLPPrBlockErr", 25, 1 },
+ { "Rsvd3", 26, 6 },
+ { "PCIE_AER_COR_ERR_STAT", 0x110, 0 },
+ { "RcvrErr", 0, 1 },
+ { "Rsvd1", 1, 5 },
+ { "BadTLP", 6, 1 },
+ { "BadDLLP", 7, 1 },
+ { "RplNumRollOver", 8, 1 },
+ { "Rsvd2", 9, 3 },
+ { "RplTimerTO", 12, 1 },
+ { "AdvNonFatErr", 13, 1 },
+ { "CorIntErr", 14, 1 },
+ { "HdrLogOFl", 15, 1 },
+ { "Rsvd3", 16, 16 },
+ { "PCIE_AER_COR_ERR_MASK", 0x114, 0 },
+ { "RcvrErr", 0, 1 },
+ { "Rsvd1", 1, 5 },
+ { "BadTLP", 6, 1 },
+ { "BadDLLP", 7, 1 },
+ { "RplNumRollOver", 8, 1 },
+ { "RplNumRollOver", 9, 3 },
+ { "RplTimerTO", 12, 1 },
+ { "AdvNonFatErr", 13, 1 },
+ { "CorIntErr", 14, 1 },
+ { "HdrLogOFl", 15, 1 },
+ { "Rsvd3", 16, 16 },
+ { "PCIE_AER_CAP_CNTL", 0x118, 0 },
+ { "FirstErrPtr", 0, 5 },
+ { "ECRCGenCap", 5, 1 },
+ { "ECRCGenEn", 6, 1 },
+ { "ECRCChkCap", 7, 1 },
+ { "ECRCChkEn", 8, 1 },
+ { "MultHdrRecCap", 9, 1 },
+ { "MultHdrRecEn", 10, 1 },
+ { "TLPPrLog", 11, 1 },
+ { "Rsvd", 12, 20 },
+ { "CIE_AER_HDR_LOG1", 0x11c, 0 },
+ { "Hdr1DW", 0, 32 },
+ { "CIE_AER_HDR_LOG2", 0x120, 0 },
+ { "Hdr2DW", 0, 32 },
+ { "CIE_AER_HDR_LOG3", 0x124, 0 },
+ { "Hdr3DW", 0, 32 },
+ { "CIE_AER_HDR_LOG4", 0x128, 0 },
+ { "Hdr4DW", 0, 32 },
+ { "PCIE_MFVC_CAP", 0x140, 0 },
+ { "MFVCCapID", 0, 16 },
+ { "MFVCCapVer", 16, 4 },
+ { "NextCapPtr", 20, 12 },
+ { "PCIE_MFVC_PORT_VC_CAP1", 0x144, 0 },
+ { "ExtVCCount", 0, 3 },
+ { "Rsvd1", 3, 1 },
+ { "LPExtVCCount", 4, 3 },
+ { "Rsvd2", 7, 1 },
+ { "RefClk", 8, 2 },
+ { "PortArbTblSz", 10, 2 },
+ { "Rsvd3", 12, 20 },
+ { "PCIE_MFVC_PORT_VC_CAP2", 0x148, 0 },
+ { "LoadVCArbTbl", 0, 1 },
+ { "VCArbSel", 1, 3 },
+ { "Rsvd1", 4, 12 },
+ { "PortVCArbStat", 16, 1 },
+ { "Rsvd2", 17, 15 },
+ { "PCIE_MFVC_VC0_RES_CAP", 0x150, 0 },
+ { "PortArbCap", 0, 8 },
+ { "Rsvd1", 8, 7 },
+ { "RejectSnoopTxns", 15, 1 },
+ { "MaxTimeSlots", 16, 7 },
+ { "Rsvd2", 23, 1 },
+ { "PortArbTblOfst", 24, 8 },
+ { "PCIE_MFVC_VC0_RES_CNTL", 0x154, 0 },
+ { "TCVCMapBit0", 0, 1 },
+ { "TCVCMap", 1, 7 },
+ { "Rsvd1", 8, 8 },
+ { "LoadPortArbTbl", 16, 1 },
+ { "PortArbSel", 17, 3 },
+ { "Rsvd2", 20, 4 },
+ { "VCID", 24, 3 },
+ { "Rsvd3", 27, 4 },
+ { "VCEnable", 31, 1 },
+ { "PCIE_MFVC_VC0_RES_STAT", 0x158, 0 },
+ { "Rsvd1", 0, 16 },
+ { "PortArbTblStat", 16, 1 },
+ { "VC0NegPnd", 17, 1 },
+ { "Rsvd2", 18, 14 },
+ { "PCIE_MFVC_VC1_RES_CAP", 0x15c, 0 },
+ { "PortArbCap", 0, 8 },
+ { "Rsvd1", 8, 7 },
+ { "RejectSnoopTxns", 15, 1 },
+ { "MaxTimeSlots", 16, 7 },
+ { "Rsvd2", 23, 1 },
+ { "PortArbTblOfst", 24, 8 },
+ { "PCIE_MFVC_VC1_RES_CNTL", 0x160, 0 },
+ { "TCVCMap", 0, 8 },
+ { "Rsvd1", 8, 8 },
+ { "LoadPortArbTbl", 16, 1 },
+ { "PortArbSel", 17, 3 },
+ { "Rsvd2", 20, 4 },
+ { "VCID", 24, 3 },
+ { "Rsvd3", 27, 4 },
+ { "VCEnable", 31, 1 },
+ { "PCIE_MFVC_VC1_RES_STAT", 0x164, 0 },
+ { "Rsvd1", 0, 16 },
+ { "PortArbTblStat", 16, 1 },
+ { "VC1NegPnd", 17, 1 },
+ { "Rsvd2", 18, 14 },
+ { "PCIE_DSN_CAP", 0x170, 0 },
+ { "DSNCapID", 0, 16 },
+ { "DSNCapVer", 16, 4 },
+ { "NextCapPtr", 20, 12 },
+ { "PCIE_DSN_DW1", 0x174, 0 },
+ { "DSN1Dw", 0, 32 },
+ { "PCIE_DSN_DW2", 0x178, 0 },
+ { "DSN2Dw", 0, 32 },
+ { "PCIE_PB_CAP_HDR", 0x180, 0 },
+ { "PBCapID", 0, 16 },
+ { "PBCapVer", 16, 4 },
+ { "NextCapPtr", 20, 12 },
+ { "PCIE_PB_DATA_SEL", 0x184, 0 },
+ { "DataSelReg", 0, 8 },
+ { "Rsvd", 8, 24 },
+ { "PCIE_PB_DATA_REG", 0x188, 0 },
+ { "BasePower", 0, 8 },
+ { "DataScale", 8, 2 },
+ { "PMSubState", 10, 3 },
+ { "PMState", 13, 2 },
+ { "Type", 15, 3 },
+ { "PowerRail", 18, 3 },
+ { "Rsvd", 21, 11 },
+ { "PCIE_PB_CAP_REG", 0x18c, 0 },
+ { "SysAlloc", 0, 1 },
+ { "Rsvd", 1, 31 },
+ { "PCIE_ARI_CAP_HDR", 0x190, 0 },
+ { "ARICapID", 0, 16 },
+ { "ARICapVer", 16, 4 },
+ { "NextCapPtr", 20, 12 },
+ { "PCIE_ARI_CAP_CNTL", 0x194, 0 },
+ { "MFVCFnGrpCap", 0, 1 },
+ { "ACSFnGrpCap", 1, 1 },
+ { "Rsvd1", 2, 6 },
+ { "NextFnNum", 8, 8 },
+ { "MFVCFnGrpEn", 16, 1 },
+ { "ACSFnGrpEn", 17, 1 },
+ { "Rsvd2", 18, 2 },
+ { "FnGrp", 20, 3 },
+ { "Rsvd3", 23, 9 },
+ { "PCIE_SEC_PCIE_EXTENDED_CAP_HDR", 0x1a0, 0 },
+ { "PCIeExtCapID", 0, 16 },
+ { "PCIeExtCapVer", 16, 4 },
+ { "NextCapPtr", 20, 12 },
+ { "PCIE_LINK_CNTL3", 0x1a4, 0 },
+ { "PerfEql", 0, 1 },
+ { "LinkEqlReqIntEn", 1, 1 },
+ { "Rsvd", 2, 30 },
+ { "PCIE_LANE_ERR_STAT", 0x1a8, 0 },
+ { "LaneErrStat", 0, 8 },
+ { "Rsvd", 8, 24 },
+ { "PCIE_LANE_EQL_CNTL0", 0x1ac, 0 },
+ { "Ln0DnPrtXmtrPrst", 0, 4 },
+ { "Ln0DnPrtRcvrPrst", 4, 3 },
+ { "Ln0UpPrtXmtrPrst", 8, 4 },
+ { "Ln0UpPrtRcvrPrst", 12, 3 },
+ { "Ln1DnPrtXmtrPrst", 16, 4 },
+ { "Ln1DnPrtRcvrPrst", 20, 3 },
+ { "Ln1UpPrtXmtrPrst", 24, 4 },
+ { "Ln1UpPrtRcvrPrst", 28, 3 },
+ { "PCIE_LANE_EQL_CNTL1", 0x1b0, 0 },
+ { "Ln2DnPrtXmtrPrst", 0, 4 },
+ { "Ln2DnPrtRcvrPrst", 4, 3 },
+ { "Ln2UpPrtXmtrPrst", 8, 4 },
+ { "Ln2UpPrtRcvrPrst", 12, 3 },
+ { "Ln3DnPrtXmtrPrst", 16, 4 },
+ { "Ln3DnPrtRcvrPrst", 20, 3 },
+ { "Ln3UpPrtXmtrPrst", 24, 4 },
+ { "Ln3UpPrtRcvrPrst", 28, 3 },
+ { "PCIE_LANE_EQL_CNTL2", 0x1b4, 0 },
+ { "Ln4DnPrtXmtrPrst", 0, 4 },
+ { "Ln4DnPrtRcvrPrst", 4, 3 },
+ { "Ln4UpPrtXmtrPrst", 8, 4 },
+ { "Ln4UpPrtRcvrPrst", 12, 3 },
+ { "Ln5DnPrtXmtrPrst", 16, 4 },
+ { "Ln5DnPrtRcvrPrst", 20, 3 },
+ { "Ln5UpPrtXmtrPrst", 24, 4 },
+ { "Ln5UpPrtRcvrPrst", 28, 3 },
+ {"PCIE_LANE_EQL_CNTL3", 0x1b8, 0 },
+ { "Ln6DnPrtXmtrPrst", 0, 4 },
+ { "Ln6DnPrtRcvrPrst", 4, 3 },
+ { "Ln6UpPrtXmtrPrst", 8, 4 },
+ { "Ln6UpPrtRcvrPrst", 12, 3 },
+ { "Ln7DnPrtXmtrPrst", 16, 4 },
+ { "Ln7DnPrtRcvrPrst", 20, 3 },
+ { "Ln7UpPrtXmtrPrst", 24, 4 },
+ { "Ln7UpPrtRcvrPrst", 28, 3 },
+ { "PCIE_SR_CAP_HDR", 0x1c0, 0 },
+ { "SRIOVCapID", 0, 16 },
+ { "SRIOVCapVer", 16, 4 },
+ { "NextCapPtr", 20, 12 },
+ { "PCIE_SR_CAP Register", 0x1c4, 0 },
+ { "VFMigCap", 0, 1 },
+ { "ARICapHierPrsrvd", 1, 1 },
+ { "Rsvd", 2, 19 },
+ { "VFMigIntMsgNum", 21, 11 },
+ { "PCIE_SR_STAT_CNTL", 0x1c8, 0 },
+ { "VFEn", 0, 1 },
+ { "VFMigEn", 1, 1 },
+ { "VFMigIntEn", 2, 1 },
+ { "VFMSE", 3, 1 },
+ { "ARICapHier", 4, 1 },
+ { "Rsvd1", 5, 11 },
+ { "VFMigStatus", 16, 1 },
+ { "Rsvd2", 17, 15 },
+ { "PCIE_SR_INIT_TOT_VFS", 0x1cc, 0 },
+ { "InitVFs", 0, 16 },
+ { "TotVFs", 16, 16 },
+ { "PCIE_SR_NUMVFS_FUNCDEPLINK", 0x1d0, 0 },
+ { "NumVFs", 0, 16 },
+ { "FuncDepLink", 16, 8 },
+ { "PCIE_SR_VF_OFST_STRIDE", 0x1d4 },
+ { "FirstVFOfst", 0, 16 },
+ { "VFStride", 16, 16 },
+ { "PCIE_SR_VF_DEVID", 0x1d8, 0 },
+ { "Rsvd", 0, 16 },
+ { "VFDevID", 16, 16 },
+ { "PCIE_SR_SUPP_PAGE_SIZES", 0x1dc, 0 },
+ { "SuppPageSzs", 0, 32 },
+ { "PCIE_SR_SYS_PAGE_SIZE", 0x1e0 },
+ { "SysPageSz", 0, 32 },
+ { "PCIE_SR_VFBAR0", 0x1e4, 0 },
+ { "MemSpaceInd", 0, 1 },
+ { "Type", 1, 2 },
+ { "Rsvd", 3, 9 },
+ { "BaseAddress", 12, 20 },
+ { "PCIE_SR_VFBAR1", 0x1e8, 0 },
+ { "MemSpaceInd", 0, 1 },
+ { "Type", 1, 2 },
+ { "Rsvd", 3, 9 },
+ { "BaseAddress", 12, 20 },
+ { "PCIE_SR_VFBAR2", 0x1ec, 0 },
+ { "MemSpaceInd", 0, 1 },
+ { "Type", 1, 2 },
+ { "Rsvd", 3, 9 },
+ { "BaseAddress", 12, 20 },
+ { "PCIE_SR_VFBAR3", 0x1f0, 0 },
+ { "MemSpaceInd", 0, 1 },
+ { "Type", 1, 2 },
+ { "Rsvd", 3, 9 },
+ { "BaseAddress", 12, 20 },
+ { "PCIE_SR_VFBAR4", 0x1f4, 0 },
+ { "MemSpaceInd", 0, 1 },
+ { "Type", 1, 2 },
+ { "Rsvd", 3, 9 },
+ { "BaseAddress", 12, 20 },
+ { "PCIE_SR_VFBAR5", 0x1f8, 0 },
+ { "MemSpaceInd", 0, 1 },
+ { "Type", 1, 2 },
+ { "Rsvd", 3, 9 },
+ { "BaseAddress", 12, 20 },
+ { "PCIE_SR_MIG_STATE_ARRAY_OFST", 0x1fc, 0 },
+ { "Rsvd", 0, 32 },
+ { "PCIE_TPH_CAP_HDR", 0x200, 0 },
+ { "TPHCap", 0, 16 },
+ { "TPHCapVer", 16, 4 },
+ { "NextCapPtr", 20, 12 },
+ { "PCIE_TPH_REQ_CAP", 0x204, 0 },
+ { "NoSTModeSup", 0, 1 },
+ { "IntVecModeSup", 1, 1 },
+ { "DevSpModeSup", 2, 1 },
+ { "ExtTPHReqSup", 8, 1 },
+ { "STTblLoc", 9, 2 },
+ { "STTblSize", 16, 11 },
+ { "PCIE_TPH_REQ_CNTL", 0x208, 0 },
+ { "STModeSel", 0, 3 },
+ { "TPHRqstEn", 8, 1 },
+ { "ExtTPHRqstEn", 9, 1 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_pm_tx_regs_10021_to_1003c[] = {
+ { "PM_TX_FEATURE_EN", 0x10021, 0 },
+ { "pio_ch_deficit_ctl_en", 2, 1 },
+ { "pio_wrr_based_prftch_en", 1, 1 },
+ { "prftch_across_bndle_en", 0, 1 },
+ { "PM_TX_T5_PM_TX_INT_ENABLE", 0x10022, 0 },
+ { "ospi_overflow3", 7, 1 },
+ { "ospi_overflow2", 6, 1 },
+ { "ospi_overflow1", 5, 1 },
+ { "ospi_overflow0", 4, 1 },
+ { "M_IntfPerrEn", 3, 1 },
+ { "bundle_len_ParErr_en", 2, 1 },
+ { "bundle_len_ovfl_en", 1, 1 },
+ { "sdc_err_en", 0, 1 },
+ { "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0", 0x10023, 0 },
+ { "pio_wrr_wait_cnt_thrshld0", 0, 32 },
+ { "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1", 0x10024, 0 },
+ { "pio_wrr_wait_cnt_thrshld1", 0, 32 },
+ { "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2", 0x10025, 0 },
+ { "pio_wrr_wait_cnt_thrshld2", 0, 32 },
+ { "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3", 0x10026, 0 },
+ { "pio_wrr_wait_cnt_thrshld3", 0, 32 },
+ { "PM_TX_CH0_OSPI_DEFICIT_THRSHLD", 0x10027, 0 },
+ { "CH0_OSPI_DEFICIT_THRSHLD", 0, 12 },
+ { "PM_TX_CH1_OSPI_DEFICIT_THRSHLD", 0x10028, 0 },
+ { "CH1_OSPI_DEFICIT_THRSHLD", 0, 12 },
+ { "PM_TX_CH2_OSPI_DEFICIT_THRSHLD", 0x10029, 0 },
+ { "CH2_OSPI_DEFICIT_THRSHLD", 0, 12 },
+ { "PM_TX_CH3_OSPI_DEFICIT_THRSHLD", 0x1002a, 0 },
+ { "CH3_OSPI_DEFICIT_THRSHLD", 0, 12 },
+ { "PM_TX_INT_CAUSE_MASK_HALT", 0x1002b, 0 },
+ { "INT_CAUSE_MASK", 0, 32 },
+ { "PM_TX_DBG_STAT0", 0x1002c, 0 },
+ { "rd_i_busy", 29, 1 },
+ { "wr_o_busy", 28, 1 },
+ { "m_to_o_busy", 27, 1 },
+ { "i_to_m_busy", 26, 1 },
+ { "pcmd_fb_only", 25, 1 },
+ { "pcmd_mem", 24, 1 },
+ { "pcmd_bypass", 23, 1 },
+ { "pcmd_eop2", 22, 1 },
+ { "pcmd_eop", 21, 1 },
+ { "pcmd_end_bundle", 20, 1 },
+ { "pcmd_fb_cmd", 16, 4 },
+ { "cur_pcmd_len", 0, 16 },
+ { "PM_TX_DBG_STAT1", 0x1002d, 0 },
+ { "pcmd_mem0", 31, 1 },
+ { "free_oespi_cnt0", 19, 12 },
+ { "pcmd_flit_len0", 7, 12 },
+ { "pcmd_cmd0", 3, 4 },
+ { "ofifo_full0", 2, 1 },
+ { "gcsum_drdy0", 1, 1 },
+ { "Bypass0", 0, 1 },
+ { "PM_TX_DBG_STAT2", 0x1002e, 0 },
+ { "pcmd_mem1", 31, 1 },
+ { "free_oespi_cnt1", 19, 12 },
+ { "pcmd_flit_len1", 7, 12 },
+ { "pcmd_cmd1", 3, 4 },
+ { "ofifo_full1", 2, 1 },
+ { "gcsum_drdy1", 1, 1 },
+ { "Bypass1", 0, 1 },
+ { "PM_TX_DBG_STAT3", 0x1002f, 0 },
+ { "pcmd_mem2", 31, 1 },
+ { "free_oespi_cnt2", 19, 12 },
+ { "pcmd_flit_len2", 7, 12 },
+ { "pcmd_cmd2", 3, 4 },
+ { "ofifo_full2", 2, 1 },
+ { "gcsum_drdy2", 1, 1 },
+ { "Bypass2", 0, 1 },
+ { "PM_TX_DBG_STAT4", 0x10030, 0 },
+ { "pcmd_mem3", 31, 1 },
+ { "free_oespi_cnt3", 19, 12 },
+ { "pcmd_flit_len3", 7, 12 },
+ { "pcmd_cmd3", 3, 4 },
+ { "ofifo_full3", 2, 1 },
+ { "gcsum_drdy3", 1, 1 },
+ { "Bypass3", 0, 1 },
+ { "PM_TX_DBG_STAT5", 0x10031, 0 },
+ { "set_pcmd_res_rdy_rd", 24, 4 },
+ { "issued_pref_rd_er_clr", 20, 4 },
+ { "issued_pref_rd", 16, 4},
+ { "pcmd_res_rdy", 12, 4 },
+ { "db_vld", 11, 1 },
+ { "inject0_drdy", 10, 1 },
+ { "inject1_drdy", 9, 1 },
+ { "first_bundle", 5, 4 },
+ { "gcsum_more_than_2_left", 1, 5 },
+ { "sdc_drdy", 0, 1 },
+ { "PM_TX_DBG_STAT6", 0x10032, 0 },
+ { "pcmd_vld", 31, 1 },
+ { "pcmd_ch", 29, 2 },
+ { "state_machine_loc", 24, 4 },
+ { "icspi_TxValid", 20, 4 },
+ { "icspi_TxFull", 16, 4 },
+ { "PCMD_srdy", 12, 4 },
+ { "PCMD_drdy", 8, 4 },
+ { "pcmd_cmd", 4, 4 },
+ { "oefifo_full3", 3, 1 },
+ { "oefifo_full2", 2, 1 },
+ { "oefifo_full1", 1, 1 },
+ { "oefifo_full0", 0, 1 },
+ { "PM_TX_DBG_STAT7", 0x10033, 0 },
+ { "icspi_RxValid", 28, 4 },
+ { "icspi_RxFull", 24, 4 },
+ { "oespi_valid", 20, 4 },
+ { "oespi_full", 16, 4 },
+ { "C_RxValid", 12, 4 },
+ { "C_RxAFull", 8, 4 },
+ { "E_TxValid3", 7, 1 },
+ { "E_TxValid2", 6, 1 },
+ { "E_TxValid1", 5, 1 },
+ { "E_TxValid0", 4, 1 },
+ { "E_TxFull3", 3, 1 },
+ { "E_TxFull2", 2, 1 },
+ { "E_TxFull1", 1, 1 },
+ { "E_TxFull0", 0, 1 },
+ { "PM_TX_DBG_STAT8", 0x10034, 0 },
+ { "mc_rsp_fifo_cnt", 24, 2 },
+ { "pcmd_free_cnt0", 14, 10 },
+ { "pcmd_free_cnt1", 4, 10 },
+ { "M_ReqAddrRdy", 3, 1 },
+ { "M_ReqWrite", 2, 1 },
+ { "M_ReqDataVld", 1, 1 },
+ { "M_ReqDataRdy", 0, 1 },
+ { "PM_TX_DBG_STAT9", 0x10035, 0 },
+ { "pcmd_free_cnt2", 10, 10 },
+ { "pcmd_free_cnt3", 0, 10 },
+ { "PM_TX_DBG_STAT10", 0x10036, 0 },
+ { "In_Eop_Cnt3", 28, 4 },
+ { "In_Eop_Cnt2", 24, 4 },
+ { "In_Eop_Cnt1", 20, 4 },
+ { "In_Eop_Cnt0", 16, 4 },
+ { "In_Sop_Cnt3", 12, 4 },
+ { "In_Sop_Cnt2", 8, 4 },
+ { "In_Sop_Cnt1", 4, 4 },
+ { "In_Sop_Cnt0", 0, 4 },
+ { "PM_TX_DBG_STAT11", 0x10037, 0 },
+ { "Out_Eop_Cnt3", 28, 4 },
+ { "Out_Eop_Cnt2", 24, 4 },
+ { "Out_Eop_Cnt1", 20, 4 },
+ { "Out_Eop_Cnt0", 16, 4 },
+ { "Out_Sop_Cnt3", 12, 4 },
+ { "Out_Sop_Cnt2", 8, 4 },
+ { "Out_Sop_Cnt1", 4, 4 },
+ { "Out_Sop_Cnt0", 0, 4 },
+ { "PM_TX_DBG_STAT12", 0x10038, 0 },
+ { "dbg_stat12", 0, 32 },
+ { "PM_TX_DBG_STAT13", 0x10039, 0 },
+ { "ch_deficit_blowed", 31, 1 },
+ { "rsvd_13_1", 28, 3 },
+ { "ch1_deficit", 16, 12},
+ { "rsvd_13", 12, 4 },
+ { "ch0_deficit", 0, 12 },
+ { "PM_TX_DBG_STAT14", 0x1003a, 0 },
+ { "rsvd_14_1", 28, 4 },
+ { "ch3_deficit", 16, 12 },
+ { "rsvd_14", 12, 4 },
+ { "ch2_deficit", 0, 12 },
+ { "PM_TX_DBG_STAT15", 0x1003b, 0 },
+ { "bundle_len_srdy", 28, 4 },
+ { "bundle_len1", 16, 12 },
+ { "rsvd_15", 12, 4 },
+ { "bundle_len0", 0, 12 },
+ { "PM_TX_DBG_STAT16", 0x1003c, 0 },
+ { "rsvd_16_1", 28, 4 },
+ { "bundle_len3", 16, 12 },
+ { "rsvd_16", 12, 4 },
+ { "bundle_len2", 0, 12 },
+ { NULL }
+};
+
+static struct cudbg_cntxt_field t6_egress_cntxt[] = {
+ { "DCA_ST:", 181, 191, 0, 0 },
+ { "StatusPgNS:", 180, 180, 0, 0 },
+ { "StatusPgRO:", 179, 179, 0, 0 },
+ { "FetchNS:", 178, 178, 0, 0 },
+ { "FetchRO:", 177, 177, 0, 0 },
+ { "Valid:", 176, 176, 0, 0 },
+ { "ReschedulePending_1:", 175, 175, 0, 0 },
+ { "PCIeDataChannel:", 174, 174, 0, 0 },
+ { "StatusPgTPHintEn:", 173, 173, 0, 0 },
+ { "StatusPgTPHint:", 171, 172, 0, 0 },
+ { "FetchTPHintEn:", 170, 170, 0, 0 },
+ { "FetchTPHint:", 168, 169, 0, 0 },
+ { "FCThreshOverride:", 167, 167, 0, 0 },
+ { "WRLength:", 162, 166, 0, 0 },
+ { "WRLengthKnown:", 161, 161, 9, 1 },
+ { "ReschedulePending:", 160, 160, 0, 0 },
+ { "TimerIx:", 157, 159, 0, 0 },
+ { "FetchBurstMin:", 156, 157, 4, 1},
+ { "FLMPacking:", 155, 155, 0, 0 },
+ { "FetchBurstMax:", 153, 154, 0, 0 },
+ { "uPToken:", 133, 152, 0, 0 },
+ { "uPTokenEn:", 132, 132, 0, 0 },
+ { "UserModeIO:", 131, 131, 0, 0 },
+ { "uPFLCredits:", 123, 130, 0, 0 },
+ { "uPFLCreditEn:", 122, 122, 0, 0 },
+ { "FID:", 111, 121, 0, 0 },
+ { "HostFCMode:", 109, 110, 0, 0 },
+ { "HostFCOwner:", 108, 108, 0, 0 },
+ { "CIDXFlushThresh:", 105, 107, 0, 1 },
+ { "CIDX:", 89, 104, 0, 0 },
+ { "PIDX:", 73, 88, 0, 0 },
+ { "BaseAddress:", 18, 72, 9, 0 },
+ { "QueueSize:", 2, 17, 0, 0 },
+ { "QueueType:", 1, 1, 0, 0 },
+ { "CachePriority:", 0, 0, 0 },
+ { NULL }
+};
+
+static struct cudbg_cntxt_field t5_egress_cntxt[] = {
+ { "DCA_ST:", 181, 191, 0, 0 },
+ { "StatusPgNS:", 180, 180, 0, 0 },
+ { "StatusPgRO:", 179, 179, 0, 0 },
+ { "FetchNS:", 178, 178, 0, 0 },
+ { "FetchRO:", 177, 177, 0, 0 },
+ { "Valid:", 176, 176, 0, 0 },
+ { "PCIeDataChannel:", 174, 175, 0, 0 },
+ { "StatusPgTPHintEn:", 173, 173, 0, 0 },
+ { "StatusPgTPHint:", 171, 172, 0, 0 },
+ { "FetchTPHintEn:", 170, 170, 0, 0 },
+ { "FetchTPHint:", 168, 169, 0, 0 },
+ { "FCThreshOverride:", 167, 167, 0, 0 },
+ { "WRLength:", 162, 166, 0, 0 },
+ { "WRLengthKnown:", 161, 161, 9, 1 },
+ { "ReschedulePending:", 160, 160, 0, 0 },
+ { "OnChipQueue:", 159, 159, 0, 0 },
+ { "FetchSizeMode:", 158, 158, 0, 0 },
+ { "FetchBurstMin:", 156, 157, 4, 1},
+ { "FLMPacking:", 155, 155, 0, 0 },
+ { "FetchBurstMax:", 153, 154, 0, 0 },
+ { "uPToken:", 133, 152, 0, 0 },
+ { "uPTokenEn:", 132, 132, 0, 0 },
+ { "UserModeIO:", 131, 131, 0, 0 },
+ { "uPFLCredits:", 123, 130, 0, 0 },
+ { "uPFLCreditEn:", 122, 122, 0, 0 },
+ { "FID:", 111, 121, 0, 0 },
+ { "HostFCMode:", 109, 110, 0, 0 },
+ { "HostFCOwner:", 108, 108, 0, 0 },
+ { "CIDXFlushThresh:", 105, 107, 0, 1 },
+ { "CIDX:", 89, 104, 0, 0 },
+ { "PIDX:", 73, 88, 0, 0 },
+ { "BaseAddress:", 18, 72, 9, 0 },
+ { "QueueSize:", 2, 17, 0, 0 },
+ { "QueueType:", 1, 1, 0, 0 },
+ { "CachePriority:", 0, 0, 0 },
+ { NULL }
+};
+
+static struct cudbg_cntxt_field t6_ingress_cntxt[] = {
+ { "SP_NS:", 158, 158 },
+ { "SP_RO:", 157, 157 },
+ { "SP_TPHintEn:", 156, 156 },
+ { "SP_TPHint:", 154, 155 },
+ { "DCA_ST:", 143, 153 },
+ { "ISCSICoalescing:", 142, 142 },
+ { "Queue_Valid:", 141, 141 },
+ { "TimerPending:", 140, 140 },
+ { "DropRSS:", 139, 139 },
+ { "PCIeChannel:", 137, 138 },
+ { "SEInterruptArmed:", 136, 136 },
+ { "CongestionMgtEnable:", 135, 135 },
+ { "NoSnoop:", 134, 134 },
+ { "RelaxedOrdering:", 133, 133 },
+ { "GTSmode:", 132, 132 },
+ { "TPHintEn:", 131, 131 },
+ { "TPHint:", 129, 130 },
+ { "UpdateScheduling:", 128, 128 },
+ { "UpdateDelivery:", 126, 127 },
+ { "InterruptSent:", 125, 125 },
+ { "InterruptIDX:", 114, 124 },
+ { "InterruptDestination:", 113, 113 },
+ { "InterruptArmed:", 112, 112 },
+ { "RxIntCounter:", 106, 111 },
+ { "RxIntCounterThreshold:", 104, 105 },
+ { "Generation:", 103, 103 },
+ { "BaseAddress:", 48, 102, 9, 0 },
+ { "PIDX:", 32, 47 },
+ { "CIDX:", 16, 31 },
+ { "QueueSize:", 4, 15, 4, 0 },
+ { "QueueEntrySize:", 2, 3, 4, 1 },
+ { "QueueEntryOverride:", 1, 1 },
+ { "CachePriority:", 0, 0 },
+ { NULL }
+};
+
+static struct cudbg_cntxt_field t5_ingress_cntxt[] = {
+ { "DCA_ST:", 143, 153 },
+ { "ISCSICoalescing:", 142, 142 },
+ { "Queue_Valid:", 141, 141 },
+ { "TimerPending:", 140, 140 },
+ { "DropRSS:", 139, 139 },
+ { "PCIeChannel:", 137, 138 },
+ { "SEInterruptArmed:", 136, 136 },
+ { "CongestionMgtEnable:", 135, 135 },
+ { "NoSnoop:", 134, 134 },
+ { "RelaxedOrdering:", 133, 133 },
+ { "GTSmode:", 132, 132 },
+ { "TPHintEn:", 131, 131 },
+ { "TPHint:", 129, 130 },
+ { "UpdateScheduling:", 128, 128 },
+ { "UpdateDelivery:", 126, 127 },
+ { "InterruptSent:", 125, 125 },
+ { "InterruptIDX:", 114, 124 },
+ { "InterruptDestination:", 113, 113 },
+ { "InterruptArmed:", 112, 112 },
+ { "RxIntCounter:", 106, 111 },
+ { "RxIntCounterThreshold:", 104, 105 },
+ { "Generation:", 103, 103 },
+ { "BaseAddress:", 48, 102, 9, 0 },
+ { "PIDX:", 32, 47 },
+ { "CIDX:", 16, 31 },
+ { "QueueSize:", 4, 15, 4, 0 },
+ { "QueueEntrySize:", 2, 3, 4, 1 },
+ { "QueueEntryOverride:", 1, 1 },
+ { "CachePriority:", 0, 0 },
+ { NULL }
+};
+
+static struct cudbg_cntxt_field t5_cnm_cntxt[] = {
+ { "CngMPSEnable:", 21, 21 },
+ { "CngTPMode:", 19, 20 },
+ { "CngDBPHdr:", 18, 18 },
+ { "CngDBPData:", 17, 17 },
+ { "CngIMSG:", 16, 16 },
+ { "CngChMap:", 0, 15, 0, 0 },
+ { NULL }
+};
+
+static struct cudbg_cntxt_field t6_flm_cntxt[] = {
+ { "Valid:", 89, 89 },
+ { "SplitLenMode:", 87, 88 },
+ { "TPHintEn:", 86, 86 },
+ { "TPHint:", 84, 85 },
+ { "NoSnoop:", 83, 83 },
+ { "RelaxedOrdering:", 82, 82 },
+ { "DCA_ST:", 71, 81 },
+ { "EQid:", 54, 70 },
+ { "SplitEn:", 52, 53 },
+ { "PadEn:", 51, 51 },
+ { "PackEn:", 50, 50 },
+ { "Cache_Lock :", 49, 49 },
+ { "CongDrop:", 48, 48 },
+ { "Inflifght:", 47, 47 },
+ { "CongEn:", 46, 46 },
+ { "CongMode:", 45, 45 },
+ { "PackOffset:", 20, 39 },
+ { "CIDX:", 8, 15 },
+ { "PIDX:", 0, 7 },
+ { NULL }
+};
+
+static struct cudbg_cntxt_field t5_flm_cntxt[] = {
+ { "Valid:", 89, 89 },
+ { "SplitLenMode:", 87, 88 },
+ { "TPHintEn:", 86, 86 },
+ { "TPHint:", 84, 85 },
+ { "NoSnoop:", 83, 83 },
+ { "RelaxedOrdering:", 82, 82 },
+ { "DCA_ST:", 71, 81 },
+ { "EQid:", 54, 70 },
+ { "SplitEn:", 52, 53 },
+ { "PadEn:", 51, 51 },
+ { "PackEn:", 50, 50 },
+ { "Cache_Lock :", 49, 49 },
+ { "CongDrop:", 48, 48 },
+ { "PackOffset:", 16, 47 },
+ { "CIDX:", 8, 15 },
+ { "PIDX:", 0, 7 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_hma_regs_a000_to_a01f[] = {
+ { "HMAT6_DEBUG_FSM_0", 0xa000, 0 },
+ { "edc_fsm", 18, 5 },
+ { "ras_fsm_slv", 15, 3 },
+ { "fc_fsm", 10, 5 },
+ { "cookie_arb_fsm", 8, 2 },
+ { "pcie_chunk_fsm", 6, 2 },
+ { "wtransfer_fsm", 4, 2 },
+ { "wd_fsm", 2, 2 },
+ { "rd_fsm", 0, 2 },
+ { "HMAT6_DEBUG_FSM_1", 0xa001, 0 },
+ { "sync_fsm", 11, 10 },
+ { "ochk_fsm", 9, 2 },
+ { "tlb_fsm", 5, 4 },
+ { "pio_fsm", 0, 5 },
+ { "HMAT6_DEBUG_PCIE_INTF", 0xa002, 0 },
+ { "H_ReqVld", 28, 1 },
+ { "H_ReqFull", 27, 1 },
+ { "H_ReqSOP", 26, 1 },
+ { "H_ReqEOP", 25, 1 },
+ { "H_RspVld", 24, 1 },
+ { "H_RspFull", 23, 1 },
+ { "H_RspSOP", 22, 1 },
+ { "H_RspEOP", 21, 1 },
+ { "H_RspErr", 20, 1 },
+ { "pcie_cmd_avail", 19, 1 },
+ { "pcie_cmd_rdy", 18, 1 },
+ { "pcie_wnr", 17, 1 },
+ { "pcie_len", 9, 8 },
+ { "pcie_trwdat_rdy", 8, 1 },
+ { "pcie_trwdat_avail", 7, 1 },
+ { "pcie_trwsop", 6, 1 },
+ { "pcie_trweop", 5, 1 },
+ { "pcie_trrdat_rdy", 4, 1 },
+ { "pcie_trrdat_avail", 3, 1 },
+ { "pcie_trrsop", 2, 1 },
+ { "pcie_trreop", 1, 1 },
+ { "pcie_trrerr", 0, 1 },
+ { "HMAT6_DEBUG_PCIE_ADDR_INTERNAL_LO", 0xa003, 0 },
+ { "pcie_addr_lo", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_ADDR_INTERNAL_HI", 0xa004, 0 },
+ { "pcie_addr_hi", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_REQ_DATA_EXTERNAL", 0xa005, 0 },
+ { "ReqData2", 24, 8 },
+ { "ReqData1", 21, 3 },
+ { "ReqData0", 0, 21 },
+ { "HMAT6_DEBUG_PCIE_RSP_DATA_EXTERNAL", 0xa006, 0 },
+ { "RspData3", 24, 8 },
+ { "RspData2", 16, 8 },
+ { "RspData1", 8, 8 },
+ { "RspData0", 0, 8 },
+ { "HMAT6_DEBUG_MA_SLV_CTL", 0xa007, 0 },
+ { "ma_cmd_avail", 19, 1 },
+ { "ma_clnt", 15, 4 },
+ { "ma_wnr", 14, 1 },
+ { "ma_len", 6, 8 },
+ { "ma_mst_rd", 5, 1 },
+ { "ma_mst_vld", 4, 1 },
+ { "ma_mst_err", 3, 1 },
+ { "mas_tlb_req", 2, 1 },
+ { "mas_tlb_ack", 1, 1 },
+ { "mas_tlb_err", 0, 1 },
+ { "HMAT6_DEBUG_MA_SLV_ADDR_INTERNAL", 0xa008, 0 },
+ { "ma_addr", 0, 32 },
+ { "HMAT6_DEBUG_TLB_HIT_ENTRY", 0xa009, 0 },
+ { "tlb_hit_entry", 0, 32 },
+ { "HMAT6_DEBUG_TLB_HIT_CNT", 0xa00a, 0 },
+ { "tlb_hit_cnt", 0, 32 },
+ { "HMAT6_DEBUG_TLB_MISS_CNT", 0xa00b, 0 },
+ { "tlb_miss_cnt", 0, 32 },
+ { "HMAT6_DEBUG_PAGE_TBL_LKP_CTL", 0xa00c, 0 },
+ { "lkp_req_vld", 4, 1 },
+ { "lkp_desc_sel", 1, 4 },
+ { "lkp_rsp_vld", 0, 1 },
+ { "HMAT6_DEBUG_PAGE_TBL_LKP_REQ_ADDR", 0xa00d, 0 },
+ { "lkp_req_addr", 0, 32 },
+ { "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_0", 0xa00e, 0 },
+ { "lkp_rsp_0", 0, 32, },
+ { "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_1", 0xa00f, 0 },
+ { "lkp_rsp_1", 0, 32 },
+ { "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_2", 0xa010, 0 },
+ { "lkp_rsp_2", 0, 32 },
+ { "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_3", 0xa011, 0 },
+ { "lkp_rsp_3", 0, 32 },
+ { "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_4", 0xa012, 0 },
+ { "lkp_rsp_4", 0, 32 },
+ { "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_5", 0xa013, 0 },
+ { "lkp_rsp_5", 0, 32 },
+ { "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_6", 0xa014, 0 },
+ { "lkp_rsp_6", 0, 32 },
+ { "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_7", 0xa015, 0 },
+ { "lkp_rsp_7", 0, 32 },
+ { "HMAT6_DEBUG_PHYS_DESC_INTERNAL_LO", 0xa016, 0 },
+ { "paddr_lo", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_RD_REQ_CNT_LO", 0xa017, 0 },
+ { "rd_req_cnt_lo", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_RD_REQ_CNT_HI", 0xa018, 0 },
+ { "rd_req_cnt_hi", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_WR_REQ_CNT_LO", 0xa019, 0 },
+ { "wr_req_cnt_lo", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_WR_REQ_CNT_HI", 0xa01a, 0 },
+ { "wr_req_cnt_hi", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_RD_DATA_CYC_CNT_LO", 0xa01b, 0 },
+ { "rd_data_cnt_lo", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_RD_DATA_CYC_CNT_HI", 0xa01c, 0 },
+ { "rd_data_cnt_hi", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_WR_DATA_CYC_CNT_LO", 0xa01d, 0 },
+ { "wr_data_cnt_lo", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_WR_DATA_CYC_CNT_HI", 0xa01e, 0 },
+ { "wr_data_cnt_hi", 0, 32 },
+ { "HMAT6_DEBUG_PCIE_SOP_EOP_CNT", 0xa01f, 0 },
+ { "wr_eop_cnt", 16, 8 },
+ { "rd_sop_cnt", 8, 8 },
+ { "rd_eop_cnt", 0, 8 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_ma_regs_a000_to_a016[] = {
+ { "MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL", 0xa000, 0 },
+ { "CmdVld0", 31, 1 },
+ { "CmdRdy0", 30, 1 },
+ { "CmdType0", 29, 1 },
+ { "CmdLen0", 21, 8 },
+ { "CmdAddr0", 8, 13 },
+ { "WrDataVld0", 7, 1 },
+ { "WrDataRdy0", 6, 1 },
+ { "RdDataRdy0", 5, 1 },
+ { "RdDataVld0", 4, 1 },
+ { "RdData0", 0, 4 },
+ { "MA_SGE_THREAD_1_CLIENT_INTERFACE_EXTERNAL", 0xa001, 0 },
+ { "CmdVld1", 31, 1 },
+ { "CmdRdy1", 30, 1 },
+ { "CmdType1", 29, 1 },
+ { "CmdLen1", 21, 8 },
+ { "CmdAddr1", 8, 13 },
+ { "WrDataVld1", 7, 1 },
+ { "WrDataRdy1", 6, 1 },
+ { "RdDataRdy1", 5, 1 },
+ { "RdDataVld1", 4, 1 },
+ { "RdData1", 0, 4 },
+ { "MA_ULP_TX_CLIENT_INTERFACE_EXTERNAL", 0xa002, 0 },
+ { "CmdVld2", 31, 1 },
+ { "CmdRdy2", 30, 1 },
+ { "CmdType2", 29, 1 },
+ { "CmdLen2", 21, 8 },
+ { "CmdAddr2", 8, 13 },
+ { "WrDataVld2", 7, 1 },
+ { "WrDataRdy2", 6, 1 },
+ { "RdDataRdy2", 5, 1 },
+ { "RdDataVld2", 4, 1 },
+ { "RdData2", 0, 4 },
+ { "MA_ULP_RX_CLIENT_INTERFACE_EXTERNAL", 0xa003, 0 },
+ { "CmdVld3", 31, 1 },
+ { "CmdRdy3", 30, 1 },
+ { "CmdType3", 29, 1 },
+ { "CmdLen3", 21, 8 },
+ { "CmdAddr3", 8, 13 },
+ { "WrDataVld3", 7, 1 },
+ { "WrDataRdy3", 6, 1 },
+ { "RdDataRdy3", 5, 1 },
+ { "RdDataVld3", 4, 1 },
+ { "RdData3", 0, 4 },
+ { "MA_ULP_TX_RX_CLIENT_INTERFACE_EXTERNAL", 0xa004, 0 },
+ { "CmdVld4", 31, 1 },
+ { "CmdRdy4", 30, 1 },
+ { "CmdType4", 29, 1 },
+ { "CmdLen4", 21, 8 },
+ { "CmdAddr4", 8, 13 },
+ { "WrDataVld4", 7, 1 },
+ { "WrDataRdy4", 6, 1 },
+ { "RdDataRdy4", 5, 1 },
+ { "RdDataVld4", 4, 1 },
+ { "RdData4", 0, 4 },
+ { "MA_TP_THREAD_0_CLIENT_INTERFACE_EXTERNAL", 0xa005, 0 },
+ { "CmdVld5", 31, 1 },
+ { "CmdRdy5", 30, 1 },
+ { "CmdType5", 29, 1 },
+ { "CmdLen5", 21, 8 },
+ { "CmdAddr5", 8, 13 },
+ { "WrDataVld5", 7, 1 },
+ { "WrDataRdy5", 6, 1 },
+ { "RdDataRdy5", 5, 1 },
+ { "RdDataVld5", 4, 1 },
+ { "RdData5", 0, 4 },
+ { "MA_TP_THREAD_1_CLIENT_INTERFACE_EXTERNAL", 0xa006, 0 },
+ { "CmdVld6", 31, 1 },
+ { "CmdRdy6", 30, 1 },
+ { "CmdType6", 29, 1 },
+ { "CmdLen6", 21, 8 },
+ { "CmdAddr6", 8, 13 },
+ { "WrDataVld6", 7, 1 },
+ { "WrDataRdy6", 6, 1 },
+ { "RdDataRdy6", 5, 1 },
+ { "RdDataVld6", 4, 1 },
+ { "RdData6", 0, 4 },
+ { "MA_LE_CLIENT_INTERFACE_EXTERNAL", 0xa007, 0 },
+ { "CmdVld7", 31, 1 },
+ { "CmdRdy7", 30, 1 },
+ { "CmdType7", 29, 1 },
+ { "CmdLen7", 21, 8 },
+ { "CmdAddr7", 8, 13 },
+ { "WrDataVld7", 7, 1 },
+ { "WrDataRdy7", 6, 1 },
+ { "RdDataRdy7", 5, 1 },
+ { "RdDataVld7", 4, 1 },
+ { "RdData7", 0, 4 },
+ { "MA_CIM_CLIENT_INTERFACE_EXTERNAL", 0xa008, 0 },
+ { "CmdVld8", 31, 1 },
+ { "CmdRdy8", 30, 1 },
+ { "CmdType8", 29, 1 },
+ { "CmdLen8", 21, 8 },
+ { "CmdAddr8", 8, 13 },
+ { "WrDataVld8", 7, 1 },
+ { "WrDataRdy8", 6, 1 },
+ { "RdDataRdy8", 5, 1 },
+ { "RdDataVld8", 4, 1 },
+ { "RdData8", 0, 4 },
+ { "MA_PCIE_CLIENT_INTERFACE_EXTERNAL", 0xa009, 0 },
+ { "CmdVld9", 31, 1 },
+ { "CmdRdy9", 30, 1 },
+ { "CmdType9", 29, 1 },
+ { "CmdLen9", 21, 8 },
+ { "CmdAddr9", 8, 13 },
+ { "WrDataVld9", 7, 1 },
+ { "WrDataRdy9", 6, 1 },
+ { "RdDataRdy9", 5, 1 },
+ { "RdDataVld9", 4, 1 },
+ { "RdData9", 0, 4 },
+ { "MA_PM_TX_CLIENT_INTERFACE_EXTERNAL", 0xa00a, 0 },
+ { "CmdVld10", 31, 1 },
+ { "CmdRdy10", 30, 1 },
+ { "CmdType10", 29, 1 },
+ { "CmdLen10", 21, 8 },
+ { "CmdAddr10", 8, 13 },
+ { "WrDataVld10", 7, 1 },
+ { "WrDataRdy10", 6, 1 },
+ { "RdDataRdy10", 5, 1 },
+ { "RdDataVld10", 4, 1 },
+ { "RdData10", 0, 4 },
+ { "MA_PM_RX_CLIENT_INTERFACE_EXTERNAL", 0xa00b, 0 },
+ { "CmdVld11", 31, 1 },
+ { "CmdRdy11", 30, 1 },
+ { "CmdType11", 29, 1 },
+ { "CmdLen11", 21, 8 },
+ { "CmdAddr11", 8, 13 },
+ { "WrDataVld11", 7, 1 },
+ { "WrDataRdy11", 6, 1 },
+ { "RdDataRdy11", 5, 1 },
+ { "RdDataVld11", 4, 1 },
+ { "RdData11", 0, 4 },
+ { "MA_HMA_CLIENT_INTERFACE_EXTERNAL", 0xa00c, 0 },
+ { "CmdVld12", 31, 1 },
+ { "CmdRdy12", 30, 1 },
+ { "CmdType12", 29, 1 },
+ { "CmdLen12", 21, 8 },
+ { "CmdAddr12", 8, 13 },
+ { "WrDataVld12", 7, 1 },
+ { "WrDataRdy12", 6, 1 },
+ { "RdDataRdy12", 5, 1 },
+ { "RdDataVld12", 4, 1 },
+ { "RdData12", 0, 4 },
+ { "MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa00d, 0 },
+ { "ci0_arb0_Req", 31, 1 },
+ { "arb0_ci0_Gnt", 30, 1 },
+ { "ci0_dm0_wdata_vld", 29, 1 },
+ { "dm0_ci0_rdata_vld", 28, 1 },
+ { "ci1_arb0_Req", 27, 1 },
+ { "arb0_ci1_Gnt", 26, 1 },
+ { "ci1_dm0_wdata_vld", 25, 1 },
+ { "dm0_ci1_rdata_vld", 24, 1 },
+ { "ci2_arb0_Req", 23, 1 },
+ { "arb0_ci2_Gnt", 22, 1 },
+ { "ci2_dm0_wdata_vld", 21, 1 },
+ { "dm0_ci2_rdata_vld", 20, 1 },
+ { "ci3_arb0_Req", 19, 1},
+ { "arb0_ci3_Gnt", 18, 1 },
+ { "ci3_dm0_wdata_vld", 17, 1 },
+ { "dm0_ci3_rdata_vld", 16, 1 },
+ { "ci4_arb0_Req", 15, 1 },
+ { "arb0_ci4_Gnt", 14, 1 },
+ { "ci4_dm0_wdata_vld", 13, 1 },
+ { "dm0_ci4_rdata_vld", 12, 1 },
+ { "ci5_arb0_Req", 11, 1 },
+ { "arb0_ci5_Gnt", 10, 1 },
+ { "ci5_dm0_wdata_vld", 9, 1 },
+ { "dm0_ci5_rdata_vld", 8, 1 },
+ { "ci6_arb0_Req", 7, 1 },
+ { "arb0_ci6_Gnt", 6, 1 },
+ { "ci6_dm0_wdata_vld", 5, 1 },
+ { "dm0_ci6_rdata_vld", 4, 1 },
+ { "ci7_arb0_Req", 3, 1 },
+ { "arb0_ci7_Gnt", 2, 1 },
+ { "ci7_dm0_wdata_vld", 1, 1},
+ { "dm0_ci7_rdata_vld", 0, 1 },
+ { "MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa00e, 0 },
+ { "ci0_arb1_Req", 31, 1 },
+ { "arb1_ci0_Gnt", 30, 1 },
+ { "ci0_dm1_wdata_vld", 29, 1 },
+ { "dm1_ci0_rdata_vld", 28, 1 },
+ { "ci1_arb1_Req", 27, 1 },
+ { "arb1_ci1_Gnt", 26, 1 },
+ { "ci1_dm1_wdata_vld", 25, 1 },
+ { "dm1_ci1_rdata_vld", 24, 1 },
+ { "ci2_arb1_Req", 23, 1 },
+ { "arb1_ci2_Gnt", 22, 1 },
+ { "ci2_dm1_wdata_vld", 21, 1 },
+ { "dm1_ci2_rdata_vld", 20, 1 },
+ { "ci3_arb1_Req", 19, 1 },
+ { "arb1_ci3_Gnt", 18, 1 },
+ { "ci3_dm1_wdata_vld", 17, 1 },
+ { "dm1_ci3_rdata_vld", 16, 1 },
+ { "ci4_arb1_Req", 15, 1 },
+ { "arb1_ci4_Gnt", 14, 1 },
+ { "ci4_dm1_wdata_vld", 13, 1 },
+ { "dm1_ci4_rdata_vld", 12, 1 },
+ { "ci5_arb1_Req", 11, 1 },
+ { "arb1_ci5_Gnt", 10, 1 },
+ { "ci5_dm1_wdata_vld", 9, 1 },
+ { "dm1_ci5_rdata_vld", 8, 1 },
+ { "ci6_arb1_Req", 7, 1 },
+ { "arb1_ci6_Gnt", 6, 1 },
+ { "ci6_dm1_wdata_vld", 5, 1 },
+ { "dm1_ci6_rdata_vld", 4, 1 },
+ { "ci7_arb1_Req", 3, 1 },
+ { "arb1_ci7_Gnt", 2, 1 },
+ { "ci7_dm1_wdata_vld", 1, 1 },
+ { "dm1_ci7_rdata_vld", 0, 1 },
+ { "MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa00f, 0 },
+ { "ci0_arb2_Req", 31, 1 },
+ { "arb2_ci0_Gnt", 30, 1 },
+ { "ci0_dm2_wdata_vld", 29, 1 },
+ { "dm2_ci0_rdata_vld", 28, 1 },
+ { "ci1_arb2_Req", 27, 1 },
+ { "arb2_ci1_Gnt", 26, 1 },
+ { "ci1_dm2_wdata_vld", 25, 1 },
+ { "dm2_ci1_rdata_vld", 24, 1 },
+ { "ci2_arb2_Req", 23, 1 },
+ { "arb2_ci2_Gnt", 22, 1 },
+ { "ci2_dm2_wdata_vld", 21, 1 },
+ { "dm2_ci2_rdata_vld", 20, 1 },
+ { "ci3_arb2_Req", 19, 1 },
+ { "arb2_ci3_Gnt", 18, 1 },
+ { "ci3_dm2_wdata_vld", 17, 1 },
+ { "dm2_ci3_rdata_vld", 16, 1 },
+ { "ci4_arb2_Req", 15, 1 },
+ { "arb2_ci4_Gnt", 14, 1 },
+ { "ci4_dm2_wdata_vld", 13, 1 },
+ { "dm2_ci4_rdata_vld", 12, 1 },
+ { "ci5_arb2_Req", 11, 1 },
+ { "arb2_ci5_Gnt", 10, 1 },
+ { "ci5_dm2_wdata_vld", 9, 1 },
+ { "dm2_ci5_rdata_vld", 8, 1 },
+ { "ci6_arb2_Req", 7, 1 },
+ { "arb2_ci6_Gnt", 6, 1 },
+ { "ci6_dm2_wdata_vld", 5, 1 },
+ { "dm2_ci6_rdata_vld", 4, 1 },
+ { "ci7_arb2_Req", 3, 1 },
+ { "arb2_ci7_Gnt", 2, 1 },
+ { "ci7_dm2_wdata_vld", 1, 1 },
+ { "dm2_ci7_rdata_vld", 0, 1 },
+ { "MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa010, 0 },
+ { "ci0_arb3_Req", 31, 1 },
+ { "arb3_ci0_Gnt", 30, 1 },
+ { "ci0_dm3_wdata_vld", 29, 1 },
+ { "dm3_ci0_rdata_vld", 28, 1 },
+ { "ci1_arb3_Req", 27, 1 },
+ { "arb3_ci1_Gnt", 26, 1 },
+ { "ci1_dm3_wdata_vld", 25, 1 },
+ { "dm3_ci1_rdata_vld", 24, 1 },
+ { "ci2_arb3_Req", 23, 1 },
+ { "arb3_ci2_Gnt", 22, 1 },
+ { "ci2_dm3_wdata_vld", 21, 1 },
+ { "dm3_ci2_rdata_vld", 20, 1 },
+ { "ci3_arb3_Req", 19, 1 },
+ { "arb3_ci3_Gnt", 18, 1 },
+ { "ci3_dm3_wdata_vld", 17, 1 },
+ { "dm3_ci3_rdata_vld", 16, 1 },
+ { "ci4_arb3_Req", 15, 1 },
+ { "arb3_ci4_Gnt", 14, 1 },
+ { "ci4_dm3_wdata_vld", 13, 1 },
+ { "dm3_ci4_rdata_vld", 12, 1 },
+ { "ci5_arb3_Req", 11, 1 },
+ { "arb3_ci5_Gnt", 10, 1 },
+ { "ci5_dm3_wdata_vld", 9, 1 },
+ { "dm3_ci5_rdata_vld", 8, 1 },
+ { "ci6_arb3_Req", 7, 1 },
+ { "arb3_ci6_Gnt", 6, 1 },
+ { "ci6_dm3_wdata_vld", 5, 1 },
+ { "dm3_ci6_rdata_vld", 4, 1 },
+ { "ci7_arb3_Req", 3, 1 },
+ { "arb3_ci7_Gnt", 2, 1 },
+ { "ci7_dm3_wdata_vld", 1, 1 },
+ { "dm3_ci7_rdata_vld", 0, 1 },
+ { "MA_MA_DEBUG_SIGNATURE_LTL_END", 0xa011, 0 },
+ { "MA_MA_DEBUG_SIGNATURE_BIG_END_INVERSE", 0xa012, 0 },
+ { "MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa013, 0 },
+ { "ci8_arb0_Req", 31, 1 },
+ { "arb0_ci8_Gnt", 30, 1 },
+ { "ci8_dm0_wdata_vld", 29, 1 },
+ { "dm0_ci8_rdata_vld", 28, 1 },
+ { "ci9_arb0_Req", 27, 1 },
+ { "arb0_ci9_Gnt", 26, 1 },
+ { "ci9_dm0_wdata_vld", 25, 1 },
+ { "dm0_ci9_rdata_vld", 24, 1 },
+ { "ci10_arb0_Req", 23, 1 },
+ { "arb0_ci10_Gnt", 22, 1 },
+ { "ci10_dm0_wdata_vld", 21, 1 },
+ { "dm0_ci10_rdata_vld", 20, 1 },
+ { "ci11_arb0_Req", 19, 1 },
+ { "arb0_ci11_Gnt", 18, 1 },
+ { "ci11_dm0_wdata_vld", 17, 1 },
+ { "dm0_ci11_rdata_vld", 16, 1 },
+ { "ci12_arb0_Req", 15, 1 },
+ { "arb0_ci12_Gnt", 14, 1 },
+ { "ci12_dm0_wdata_vld", 13, 1 },
+ { "dm0_ci12_rdata_vld", 12, 1 },
+ { "RSVD", 0, 12 },
+ { "MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa014, 0 },
+ { "ci8_arb1_Req", 31, 1 },
+ { "arb1_ci8_Gnt", 30, 1 },
+ { "ci8_dm1_wdata_vld", 29, 1 },
+ { "dm1_ci8_rdata_vld", 28, 1 },
+ { "ci9_arb1_Req", 27, 1 },
+ { "arb1_ci9_Gnt", 26, 1 },
+ { "ci9_dm1_wdata_vld", 25, 1 },
+ { "dm1_ci9_rdata_vld", 24, 1 },
+ { "ci10_arb1_Req", 23, 1 },
+ { "arb1_ci10_Gnt", 22, 1 },
+ { "ci10_dm1_wdata_vld", 21, 1 },
+ { "dm1_ci10_rdata_vld", 20, 1 },
+ { "ci11_arb1_Req", 19, 1 },
+ { "arb1_ci11_Gnt", 18, 1 },
+ { "ci11_dm1_wdata_vld", 17, 1 },
+ { "dm1_ci11_rdata_vld", 16, 1 },
+ { "ci12_arb1_Req", 15, 1 },
+ { "arb1_ci12_Gnt", 14, 1 },
+ { "ci12_dm1_wdata_vld", 13, 1 },
+ { "dm1_ci12_rdata_vld", 12, 1 },
+ { "RSVD", 0, 12 },
+ { "MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa015, 0 },
+ { "ci8_arb2_Req", 31, 1 },
+ { "arb2_ci8_Gnt", 30, 1 },
+ { "ci8_dm2_wdata_vld", 29, 1 },
+ { "dm2_ci8_rdata_vld", 28, 1 },
+ { "ci9_arb2_Req", 27, 1 },
+ { "arb2_ci9_Gnt", 26, 1 },
+ { "ci9_dm2_wdata_vld", 25, 1 },
+ { "dm2_ci9_rdata_vld", 24, 1 },
+ { "ci10_arb2_Req", 23, 1 },
+ { "arb2_ci10_Gnt", 22, 1 },
+ { "ci10_dm2_wdata_vld", 21, 1 },
+ { "dm2_ci10_rdata_vld", 20, 1 },
+ { "ci11_arb2_Req", 19, 1 },
+ { "arb2_ci11_Gnt", 18, 1 },
+ { "ci11_dm2_wdata_vld", 17, 1 },
+ { "dm2_ci11_rdata_vld", 16, 1 },
+ { "ci12_arb2_Req", 15, 1 },
+ { "arb2_ci12_Gnt", 14, 1 },
+ { "ci12_dm2_wdata_vld", 13, 1 },
+ { "dm2_ci12_rdata_vld", 12, 1 },
+ { "RSVD", 0, 12 },
+ { "MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa016, 0 },
+ { "ci8_arb3_Req", 31, 1 },
+ { "arb3_ci8_Gnt", 30, 1 },
+ { "ci8_dm3_wdata_vld", 29, 1 },
+ { "dm3_ci8_rdata_vld", 28, 1 },
+ { "ci9_arb3_Req", 27, 1 },
+ { "arb3_ci9_Gnt", 26, 1 },
+ { "ci9_dm3_wdata_vld", 25, 1 },
+ { "dm3_ci9_rdata_vld", 24, 1 },
+ { "ci10_arb3_Req", 23, 1 },
+ { "arb3_ci10_Gnt", 22, 1 },
+ { "ci10_dm3_wdata_vld", 21, 1 },
+ { "dm3_ci10_rdata_vld", 20, 1},
+ { "ci11_arb3_Req", 19, 1 },
+ { "arb3_ci11_Gnt", 18, 1 },
+ { "ci11_dm3_wdata_vld", 17, 1 },
+ { "dm3_ci11_rdata_vld", 16, 1 },
+ { "ci12_arb3_Req", 15, 1 },
+ { "arb3_ci12_Gnt", 14, 1 },
+ { "ci12_dm3_wdata_vld", 13, 1 },
+ { "dm3_ci12_rdata_vld", 12, 1 },
+ {"RSVD", 0, 12 },
+ { NULL }
+};
+static struct cudbg_reg_info t6_ma_regs_a400_to_a41e[] = {
+ { "MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0", 0xa400, 0 },
+ { "Cmd_In_FIFO_Cnt0", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt0", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt0", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt0", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt0", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt0", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt0", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0", 0xa401, 0 },
+ { "Cmd_In_FIFO_Cnt1", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt1", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt1", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt1", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt1", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt1", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt1", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa402, 0 },
+ { "Cmd_In_FIFO_Cnt2", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt2", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt2", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt2", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt2", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt2", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt2", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa403, 0 },
+ { "Cmd_In_FIFO_Cnt3", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt3", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt3", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt3", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt3", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt3", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt3", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa404, 0 },
+ { "Cmd_In_FIFO_Cnt4", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt4", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt4", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt4", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt4", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt4", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt4", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0", 0xa405, 0 },
+ { "Cmd_In_FIFO_Cnt5", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt5", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt5", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt5", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt5", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt5", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt5", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0", 0xa406, 0 },
+ { "Cmd_In_FIFO_Cnt6", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt6", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt6", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt6", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt6", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt6", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt6", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_LE_CLIENT_INTERFACE_INTERNAL_REG0", 0xa407, 0 },
+ { "Cmd_In_FIFO_Cnt7", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt7", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt7", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt7", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt7", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt7", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt7", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_CIM_CLIENT_INTERFACE_INTERNAL_REG0", 0xa408, 0 },
+ { "Cmd_In_FIFO_Cnt8", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt8", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt8", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt8", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt8", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt8", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt8", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG0", 0xa409, 0 },
+ { "Cmd_In_FIFO_Cnt9", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt9", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt9", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt9", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt9", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt9", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt9", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa40a, 0 },
+ { "Cmd_In_FIFO_Cnt10", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt10", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt10", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt10", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt10", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt10", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt10", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa40b, 0 },
+ { "Cmd_In_FIFO_Cnt11", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt11", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt11", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt11", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt11", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt11", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt11", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_HMA_CLIENT_INTERFACE_INTERNAL_REG0", 0xa40c, 0 },
+ { "Cmd_In_FIFO_Cnt12", 30, 2 },
+ { "Cmd_Split_FIFO_Cnt12", 28, 2 },
+ { "Cmd_Throttle_FIFO_Cnt12", 22, 6 },
+ { "Rd_Chnl_FIFO_Cnt12", 15, 7 },
+ { "Rd_Data_Ext_FIFO_Cnt12", 13, 2 },
+ { "Rd_Data_512b_FIFO_Cnt12", 5, 8 },
+ { "Rd_Req_Tag_FIFO_Cnt12", 1, 4 },
+ { "RSVD", 0, 1 },
+ { "MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG0", 0xa40d, 0 },
+ { "RSVD", 24, 8 },
+ { "Wr_data_FSM0", 23, 1 },
+ { "Rd_Data_FSM0", 22, 1 },
+ { "Tgt_Cmd_FIFO_Cnt0", 19, 2 },
+ { "Clnt_Num_FIFO_Cnt0", 16, 3 },
+ { "Wr_Cmd_Tag_FIFO_Cnt_tgt0", 8, 8},
+ { "Wr_Data_512b_FIFO_Cnt_tgt0", 0, 8 },
+ { "MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG0", 0xa40e, 0 },
+ { "RSVD", 24, 8 },
+ { "Wr_data_FSM1", 23, 1 },
+ { "Rd_Data_FSM1", 22, 1 },
+ { "Tgt_Cmd_FIFO_Cnt1", 19, 2 },
+ { "Clnt_Num_FIFO_Cnt1", 16, 3 },
+ { "Wr_Cmd_Tag_FIFO_Cnt_tgt1", 8, 8},
+ { "Wr_Data_512b_FIFO_Cnt_tgt1", 0, 8 },
+ {"MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG0", 0xa40f, 0 },
+ { "RSVD", 24, 8 },
+ { "Wr_data_FSM2", 23, 1 },
+ { "Rd_Data_FSM2", 22, 1 },
+ { "Tgt_Cmd_FIFO_Cnt2", 19, 2 },
+ { "Clnt_Num_FIFO_Cnt2", 16, 3 },
+ { "Wr_Cmd_Tag_FIFO_Cnt_tgt2", 8, 8},
+ { "Wr_Data_512b_FIFO_Cnt_tgt2", 0, 8 },
+ { "MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG0", 0xa410, 0 },
+ { "RSVD", 24, 8 },
+ { "Wr_data_FSM3", 23, 1 },
+ { "Rd_Data_FSM3", 22, 1 },
+ { "Tgt_Cmd_FIFO_Cnt3", 19, 2 },
+ { "Clnt_Num_FIFO_Cnt3", 16, 3 },
+ { "Wr_Cmd_Tag_FIFO_Cnt_tgt3", 8, 8},
+ { "Wr_Data_512b_FIFO_Cnt_tgt3", 0, 8 },
+ { "MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT", 0xa412, 0 },
+ { "MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT", 0xa413, 0 },
+ { "MA_ULP_TX_CLNT_EXP_RD_CYC_CNT", 0xa414, 0 },
+ { "MA_ULP_RX_CLNT_EXP_RD_CYC_CNT", 0xa415, 0 },
+ { "MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT", 0xa416, 0 },
+ { "MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT", 0xa417, 0 },
+ { "MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT", 0xa418, 0 },
+ { "MA_LE_CLNT_EXP_RD_CYC_CNT", 0xa419, 0 },
+ { "MA_CIM_CLNT_EXP_RD_CYC_CNT", 0xa41a, 0 },
+ { "MA_PCIE_CLNT_EXP_RD_CYC_CNT", 0xa41b, 0 },
+ { "MA_PM_TX_CLNT_EXP_RD_CYC_CNT", 0xa41c, 0 },
+ { "MA_PM_RX_CLNT_EXP_RD_CYC_CNT", 0xa41d, 0 },
+ { "MA_HMA_CLNT_EXP_RD_CYC_CNT", 0xa41e, 0 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_ma_regs_a800_to_a813[] = {
+ { "MA_EDRAM0_WRDATA_CNT1", 0xa800, 0 },
+ { "MA_EDRAM0_WRDATA_CNT0", 0xa801, 0 },
+ { "MA_EDRAM1_WRDATA_CNT1", 0xa802, 0 },
+ { "MA_EDRAM1_WRDATA_CNT0", 0xa803, 0 },
+ { "MA_EXT_MEMORY0_WRDATA_CNT1", 0xa804, 0 },
+ { "MA_EXT_MEMORY0_WRDATA_CNT0", 0xa805, 0 },
+ { "MA_HOST_MEMORY_WRDATA_CNT1", 0xa806, 0 },
+ { "MA_HOST_MEMORY_WRDATA_CNT0", 0xa807, 0 },
+ { "MA_EXT_MEMORY1_WRDATA_CNT1", 0xa808, 0 },
+ { "MA_EXT_MEMORY1_WRDATA_CNT0", 0xa809, 0 },
+ { "MA_EDRAM0_RDDATA_CNT1", 0xa80a, 0 },
+ { "MA_EDRAM0_RDDATA_CNT0", 0xa80b, 0 },
+ { "MA_EDRAM1_RDDATA_CNT1", 0xa80c, 0 },
+ { "MA_EDRAM1_RDDATA_CNT0", 0xa80d, 0 },
+ { "MA_EXT_MEMORY0_RDDATA_CNT1", 0xa80e, 0 },
+ { "MA_EXT_MEMORY0_RDDATA_CNT0", 0xa80f, 0 },
+ { "MA_HOST_MEMORY_RDDATA_CNT1", 0xa810, 0 },
+ { "MA_HOST_MEMORY_RDDATA_CNT0", 0xa811, 0 },
+ { "MA_EXT_MEMORY1_RDDATA_CNT1", 0xa812, 0 },
+ { "MA_EXT_MEMORY1_RDDATA_CNT0", 0xa813, 0 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_ma_regs_e400_to_e600[] = {
+ { "MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1", 0xe400, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt0", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt0", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt0", 18, 8 },
+ { "Rd_Data_Align_FSM0", 17, 1 },
+ { "Rd_Data_Fetch_FSM0", 16, 1 },
+ { "Coherency_Tx_FSM0", 15, 1 },
+ { "Coherency_Rx_FSM0", 14, 1 },
+ { "Arb_Req_FSM0", 13, 1 },
+ { "Cmd_Split_FSM0", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1", 0xe420, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt1", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt1", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt1", 18, 8 },
+ { "Rd_Data_Align_FSM1", 17, 1 },
+ { "Rd_Data_Fetch_FSM1", 16, 1 },
+ { "Coherency_Tx_FSM1", 15, 1 },
+ { "Coherency_Rx_FSM1", 14, 1 },
+ { "Arb_Req_FSM1", 13, 1 },
+ { "Cmd_Split_FSM1", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe440, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt2", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt2", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt2", 18, 8 },
+ { "Rd_Data_Align_FSM2", 17, 1 },
+ { "Rd_Data_Fetch_FSM2", 16, 1 },
+ { "Coherency_Tx_FSM2", 15, 1 },
+ { "Coherency_Rx_FSM2", 14, 1 },
+ { "Arb_Req_FSM2", 13, 1 },
+ { "Cmd_Split_FSM2", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe460, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt3", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt3", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt3", 18, 8 },
+ { "Rd_Data_Align_FSM3", 17, 1 },
+ { "Rd_Data_Fetch_FSM3", 16, 1 },
+ { "Coherency_Tx_FSM3", 15, 1 },
+ { "Coherency_Rx_FSM3", 14, 1 },
+ { "Arb_Req_FSM3", 13, 1 },
+ { "Cmd_Split_FSM3", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe480, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt4", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt4", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt4", 18, 8 },
+ { "Rd_Data_Align_FSM4", 17, 1 },
+ { "Rd_Data_Fetch_FSM4", 16, 1 },
+ { "Coherency_Tx_FSM4", 15, 1 },
+ { "Coherency_Rx_FSM4", 14, 1 },
+ { "Arb_Req_FSM4", 13, 1 },
+ { "Cmd_Split_FSM4", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1", 0xe4a0, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt5", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt5", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt5", 18, 8 },
+ { "Rd_Data_Align_FSM5", 17, 1 },
+ { "Rd_Data_Fetch_FSM5", 16, 1 },
+ { "Coherency_Tx_FSM5", 15, 1 },
+ { "Coherency_Rx_FSM5", 14, 1 },
+ { "Arb_Req_FSM5", 13, 1 },
+ { "Cmd_Split_FSM5", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1", 0xe4c0, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt6", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt6", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt6", 18, 8 },
+ { "Rd_Data_Align_FSM6", 17, 1 },
+ { "Rd_Data_Fetch_FSM6", 16, 1 },
+ { "Coherency_Tx_FSM6", 15, 1 },
+ { "Coherency_Rx_FSM6", 14, 1 },
+ { "Arb_Req_FSM6", 13, 1 },
+ { "Cmd_Split_FSM6", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_LE_CLIENT_INTERFACE_INTERNAL_REG1", 0xe4e0, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt7", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt7", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt7", 18, 8 },
+ { "Rd_Data_Align_FSM7", 17, 1 },
+ { "Rd_Data_Fetch_FSM7", 16, 1 },
+ { "Coherency_Tx_FSM7", 15, 1 },
+ { "Coherency_Rx_FSM7", 14, 1 },
+ { "Arb_Req_FSM7", 13, 1 },
+ { "Cmd_Split_FSM7", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_CIM_CLIENT_INTERFACE_INTERNAL_REG1", 0xe500, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt8", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt8", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt8", 18, 8 },
+ { "Rd_Data_Align_FSM8", 17, 1 },
+ { "Rd_Data_Fetch_FSM8", 16, 1 },
+ { "Coherency_Tx_FSM8", 15, 1 },
+ { "Coherency_Rx_FSM8", 14, 1 },
+ { "Arb_Req_FSM8", 13, 1 },
+ { "Cmd_Split_FSM8", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG1", 0xe520, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt9", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt9", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt9", 18, 8 },
+ { "Rd_Data_Align_FSM9", 17, 1 },
+ { "Rd_Data_Fetch_FSM9", 16, 1 },
+ { "Coherency_Tx_FSM9", 15, 1 },
+ { "Coherency_Rx_FSM9", 14, 1 },
+ { "Arb_Req_FSM9", 13, 1 },
+ { "Cmd_Split_FSM9", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe540, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt10", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt10", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt10", 18, 8 },
+ { "Rd_Data_Align_FSM10", 17, 1 },
+ { "Rd_Data_Fetch_FSM10", 16, 1 },
+ { "Coherency_Tx_FSM10", 15, 1 },
+ { "Coherency_Rx_FSM10", 14, 1 },
+ { "Arb_Req_FSM10", 13, 1 },
+ { "Cmd_Split_FSM10", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe560, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt11", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt11", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt11", 18, 8 },
+ { "Rd_Data_Align_FSM11", 17, 1 },
+ { "Rd_Data_Fetch_FSM11", 16, 1 },
+ { "Coherency_Tx_FSM11", 15, 1 },
+ { "Coherency_Rx_FSM11", 14, 1 },
+ { "Arb_Req_FSM11", 13, 1 },
+ { "Cmd_Split_FSM11", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_HMA_CLIENT_INTERFACE_INTERNAL_REG1", 0xe580, 0 },
+ { "Wr_Data_Ext_FIFO_Cnt12", 30, 2 },
+ { "Wr_Cmd_Tag_FIFO_Cnt12", 26, 4 },
+ { "Wr_Data_512b_FIFO_Cnt12", 18, 8 },
+ { "Rd_Data_Align_FSM12", 17, 1 },
+ { "Rd_Data_Fetch_FSM12", 16, 1 },
+ { "Coherency_Tx_FSM12", 15, 1 },
+ { "Coherency_Rx_FSM12", 14, 1 },
+ { "Arb_Req_FSM12", 13, 1 },
+ { "Cmd_Split_FSM12", 11, 2},
+ { "RSVD", 0, 11 },
+ { "MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG1", 0xe5a0, 0 },
+ { "RSVD", 16, 16 },
+ { "Rd_Cmd_Tag_FIFO_Cnt0", 8, 8 },
+ { "Rd_Data_FIFO_Cnt0", 0, 8 },
+ { "MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG1", 0xe5c0, 0 },
+ { "RSVD", 16, 16 },
+ { "Rd_Cmd_Tag_FIFO_Cnt1", 8, 8 },
+ { "Rd_Data_FIFO_Cnt1", 0, 8 },
+ { "MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG1", 0xe5e0, 0 },
+ { "RSVD", 16, 16 },
+ { "Rd_Cmd_Tag_FIFO_Cnt2", 8, 8 },
+ { "Rd_Data_FIFO_Cnt2", 0, 8 },
+ { "MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG1", 0xe600, 0 },
+ { "RSVD", 16, 16 },
+ { "Rd_Cmd_Tag_FIFO_Cnt3", 8, 8 },
+ { "Rd_Data_FIFO_Cnt3", 0, 8 },
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_ma_regs_e640_to_e7c0[] = {
+ { "MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT", 0xe640, 0 },
+ { "MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT", 0xe660, 0 },
+ { "MA_ULP_TX_CLNT_EXP_WR_CYC_CNT", 0xe680, 0 },
+ { "MA_ULP_RX_CLNT_EXP_WR_CYC_CNT", 0xe6a0, 0 },
+ { "MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT", 0xe6c0, 0 },
+ { "MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT", 0xe6e0, 0 },
+ { "MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT", 0xe700, 0 },
+ { "MA_LE_CLNT_EXP_WR_CYC_CNT", 0xe720, 0 },
+ { "MA_CIM_CLNT_EXP_WR_CYC_CNT", 0xe740, 0 },
+ { "MA_PCIE_CLNT_EXP_WR_CYC_CNT", 0xe760, 0 },
+ { "MA_PM_TX_CLNT_EXP_WR_CYC_CNT", 0xe780, 0 },
+ { "MA_PM_RX_CLNT_EXP_WR_CYC_CNT", 0xe7a0, 0 },
+ { "MA_HMA_CLNT_EXP_WR_CYC_CNT", 0xe7c0, 0 },
+ { NULL }
+};
+
+static char *cudbg_ulptx_rdptr[] = {
+ "ULP_TX_LA_RDPTR_0" ,
+ "ULP_TX_LA_RDPTR_1" ,
+ "ULP_TX_LA_RDPTR_2" ,
+ "ULP_TX_LA_RDPTR_3" ,
+ "ULP_TX_LA_RDPTR_4" ,
+ "ULP_TX_LA_RDPTR_5" ,
+ "ULP_TX_LA_RDPTR_6" ,
+ "ULP_TX_LA_RDPTR_7" ,
+ "ULP_TX_LA_RDPTR_8" ,
+ "ULP_TX_LA_RDPTR_9" ,
+ "ULP_TX_LA_RDPTR_10"
+};
+
+static char *cudbg_ulptx_wrptr[] = {
+ "ULP_TX_LA_WRPTR_0",
+ "ULP_TX_LA_WRPTR_1",
+ "ULP_TX_LA_WRPTR_2",
+ "ULP_TX_LA_WRPTR_3",
+ "ULP_TX_LA_WRPTR_4",
+ "ULP_TX_LA_WRPTR_5",
+ "ULP_TX_LA_WRPTR_6",
+ "ULP_TX_LA_WRPTR_7",
+ "ULP_TX_LA_WRPTR_8",
+ "ULP_TX_LA_WRPTR_9",
+ "ULP_TX_LA_WRPTR_10"
+};
+
+static char *cudbg_ulptx_rddata[] = {
+ "ULP_TX_LA_RDDATA_0",
+ "ULP_TX_LA_RDDATA_1",
+ "ULP_TX_LA_RDDATA_2",
+ "ULP_TX_LA_RDDATA_3",
+ "ULP_TX_LA_RDDATA_4",
+ "ULP_TX_LA_RDDATA_5",
+ "ULP_TX_LA_RDDATA_6",
+ "ULP_TX_LA_RDDATA_7",
+ "ULP_TX_LA_RDDATA_8",
+ "ULP_TX_LA_RDDATA_9",
+ "ULP_TX_LA_RDDATA_10"
+};
+
+static struct cudbg_reg_info t6_up_cim_2000_to_207c[] = {
+ {"CIM_CTL_CONFIG", 0x2000, 0},
+ {"AutoPrefLoc", 17, 5},
+ {"AutoPrefEn", 16, 1},
+ {"DisMATimeOut", 15, 1},
+ {"DisSlowTimeOut", 14, 1},
+ {"IntlRspEn", 9, 1},
+ {"PIFMultiCmd", 8, 1},
+ {"UPSelfResetTOut", 7, 1},
+ {"PLSwapDisWr", 6, 1},
+ {"PLSwapDisRd", 5, 1},
+ {"Timer1En", 4, 1},
+ {"Timer0En", 3, 1},
+ {"TimerEn", 1, 1},
+ {"PrefEn", 0, 1},
+ {"CIM_CTL_PREFADDR", 0x2004, 0},
+ {"PrefAddr", 0, 32},
+ {"CIM_CTL_ALLOCADDR", 0x2008, 0},
+ {"IbqGen0", 0, 32},
+ {"CIM_CTL_INVLDTADDR", 0x200c, 0},
+ {"InvldtAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR0", 0x2010, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR1", 0x2014, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR2", 0x2018, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR3", 0x201c, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR4", 0x2020, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR5", 0x2024, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR6", 0x2028, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR7", 0x202c, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR8", 0x2030, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR9", 0x2034, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR10", 0x2038, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR11", 0x203c, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR12", 0x2040, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR13", 0x2044, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR14", 0x2048, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR15", 0x204c, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR0", 0x2050, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR1", 0x2054, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR2", 0x2058, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR3", 0x205c, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR4", 0x2060, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR5", 0x2064, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR6", 0x2068, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR7", 0x206c, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR8", 0x2070, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR9", 0x2074, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR10", 0x2078, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR11", 0x207c, 0},
+ {"StaticAllocAddr", 0, 32},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_2000_to_207c[] = {
+ {"CIM_CTL_CONFIG", 0x2000, 0},
+ {"AutoPrefLoc", 17, 5},
+ {"AutoPrefEn", 16, 1},
+ {"DisMATimeOut", 15, 1},
+ {"PIFMultiCmd", 8, 1},
+ {"UPSelfResetTOut", 7, 1},
+ {"PLSwapDisWr", 6, 1},
+ {"PLSwapDisRd", 5, 1},
+ {"Timer1En", 4, 1},
+ {"Timer0En", 3, 1},
+ {"TimerEn", 1, 1},
+ {"PrefEn", 0, 1},
+ {"CIM_CTL_PREFADDR", 0x2004, 0},
+ {"PrefAddr", 0, 32},
+ {"CIM_CTL_ALLOCADDR", 0x2008, 0},
+ {"IbqGen0", 0, 32},
+ {"CIM_CTL_INVLDTADDR", 0x200c, 0},
+ {"InvldtAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR0", 0x2010, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR1", 0x2014, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR2", 0x2018, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR3", 0x201c, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR4", 0x2020, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR5", 0x2024, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR6", 0x2028, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR7", 0x202c, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR8", 0x2030, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR9", 0x2034, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR10", 0x2038, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR11", 0x203c, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR12", 0x2040, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR13", 0x2044, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR14", 0x2048, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_PREFADDR15", 0x204c, 0},
+ {"StaticPrefAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR0", 0x2050, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR1", 0x2054, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR2", 0x2058, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR3", 0x205c, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR4", 0x2060, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR5", 0x2064, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR6", 0x2068, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR7", 0x206c, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR8", 0x2070, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR9", 0x2074, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR10", 0x2078, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR11", 0x207c, 0},
+ {"StaticAllocAddr", 0, 32},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_4900_to_4c60[] = {
+ {"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4900, 0},
+ {"TSCHNLEN", 31, 1},
+ {"TSCHNRESET", 30, 1},
+ {"MIN_MAX_EN", 29, 1},
+ {"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4a20, 0},
+ {"TSCHNLEN", 31, 1},
+ {"TSCHNRESET", 30, 1},
+ {"MIN_MAX_EN", 29, 1},
+ {"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4b40, 0},
+ {"TSCHNLEN", 31, 1},
+ {"TSCHNRESET", 30, 1},
+ {"MIN_MAX_EN", 29, 1},
+ {"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4c60, 0},
+ {"TSCHNLEN", 31, 1},
+ {"TSCHNRESET", 30, 1},
+ {"MIN_MAX_EN", 29, 1},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_4904_to_4c64[] = {
+ {"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4904, 0},
+ {"TSC0RATECTL", 0, 1},
+ {"TSC1RATECTL", 1, 1},
+ {"TSC2RATECTL", 2, 1},
+ {"TSC3RATECTL", 3, 1},
+ {"TSC4RATECTL", 4, 1},
+ {"TSC5RATECTL", 5, 1},
+ {"TSC6RATECTL", 6, 1},
+ {"TSC7RATECTL", 7, 1},
+ {"TSC8RATECTL", 8, 1},
+ {"TSC9RATECTL", 9, 1},
+ {"TSC10RATECTL", 10, 1},
+ {"TSC11RATECTL", 11, 1},
+ {"TSC12RATECTL", 12, 1},
+ {"TSC13RATECTL", 13, 1},
+ {"TSC14RATECTL", 14, 1},
+ {"TSC15RATECTL", 15, 1},
+ {"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4a24, 0},
+ {"TSC0RATECTL", 0, 1},
+ {"TSC1RATECTL", 1, 1},
+ {"TSC2RATECTL", 2, 1},
+ {"TSC3RATECTL", 3, 1},
+ {"TSC4RATECTL", 4, 1},
+ {"TSC5RATECTL", 5, 1},
+ {"TSC6RATECTL", 6, 1},
+ {"TSC7RATECTL", 7, 1},
+ {"TSC8RATECTL", 8, 1},
+ {"TSC9RATECTL", 9, 1},
+ {"TSC10RATECTL", 10, 1},
+ {"TSC11RATECTL", 11, 1},
+ {"TSC12RATECTL", 12, 1},
+ {"TSC13RATECTL", 13, 1},
+ {"TSC14RATECTL", 14, 1},
+ {"TSC15RATECTL", 15, 1},
+ {"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4b44, 0},
+ {"TSC0RATECTL", 0, 1},
+ {"TSC1RATECTL", 1, 1},
+ {"TSC2RATECTL", 2, 1},
+ {"TSC3RATECTL", 3, 1},
+ {"TSC4RATECTL", 4, 1},
+ {"TSC5RATECTL", 5, 1},
+ {"TSC6RATECTL", 6, 1},
+ {"TSC7RATECTL", 7, 1},
+ {"TSC8RATECTL", 8, 1},
+ {"TSC9RATECTL", 9, 1},
+ {"TSC10RATECTL", 10, 1},
+ {"TSC11RATECTL", 11, 1},
+ {"TSC12RATECTL", 12, 1},
+ {"TSC13RATECTL", 13, 1},
+ {"TSC14RATECTL", 14, 1},
+ {"TSC15RATECTL", 15, 1},
+ {"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4c64, 0},
+ {"TSC0RATECTL", 0, 1},
+ {"TSC1RATECTL", 1, 1},
+ {"TSC2RATECTL", 2, 1},
+ {"TSC3RATECTL", 3, 1},
+ {"TSC4RATECTL", 4, 1},
+ {"TSC5RATECTL", 5, 1},
+ {"TSC6RATECTL", 6, 1},
+ {"TSC7RATECTL", 7, 1},
+ {"TSC8RATECTL", 8, 1},
+ {"TSC9RATECTL", 9, 1},
+ {"TSC10RATECTL", 10, 1},
+ {"TSC11RATECTL", 11, 1},
+ {"TSC12RATECTL", 12, 1},
+ {"TSC13RATECTL", 13, 1},
+ {"TSC14RATECTL", 14, 1},
+ {"TSC15RATECTL", 15, 1},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_4908_to_4c68[] = {
+ {"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4908, 0},
+ {"TSC15WRREN", 31, 1},
+ {"TSC15RATEEN", 30, 1},
+ {"TSC14WRREN", 29, 1},
+ {"TSC14RATEEN", 28, 1},
+ {"TSC13WRREN", 27, 1},
+ {"TSC13RATEEN", 26, 1},
+ {"TSC12WRREN", 25, 1},
+ {"TSC12RATEEN", 24, 1},
+ {"TSC11WRREN", 23, 1},
+ {"TSC11RATEEN", 22, 1},
+ {"TSC10WRREN", 21, 1},
+ {"TSC10RATEEN", 20, 1},
+ {"TSC9WRREN", 19, 1},
+ {"TSC9RATEEN", 18, 1},
+ {"TSC8WRREN", 17, 1},
+ {"TSC8RATEEN", 16, 1},
+ {"TSC7WRREN", 15, 1},
+ {"TSC7RATEEN", 14, 1},
+ {"TSC6WRREN", 13, 1},
+ {"TSC6RATEEN", 12, 1},
+ {"TSC5WRREN", 11, 1},
+ {"TSC5RATEEN", 10, 1},
+ {"TSC4WRREN", 9, 1},
+ {"TSC4RATEEN", 8, 1},
+ {"TSC3WRREN", 7, 1},
+ {"TSC3RATEEN", 6, 1},
+ {"TSC2WRREN", 5, 1},
+ {"TSC2RATEEN", 4, 1},
+ {"TSC1WRREN", 3, 1},
+ {"TSC1RATEEN", 2, 1},
+ {"TSC0WRREN", 1, 1},
+ {"TSC0RATEEN", 0, 1},
+ {"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4a28, 0},
+ {"TSC15WRREN", 31, 1},
+ {"TSC15RATEEN", 30, 1},
+ {"TSC14WRREN", 29, 1},
+ {"TSC14RATEEN", 28, 1},
+ {"TSC13WRREN", 27, 1},
+ {"TSC13RATEEN", 26, 1},
+ {"TSC12WRREN", 25, 1},
+ {"TSC12RATEEN", 24, 1},
+ {"TSC11WRREN", 23, 1},
+ {"TSC11RATEEN", 22, 1},
+ {"TSC10WRREN", 21, 1},
+ {"TSC10RATEEN", 20, 1},
+ {"TSC9WRREN", 19, 1},
+ {"TSC9RATEEN", 18, 1},
+ {"TSC8WRREN", 17, 1},
+ {"TSC8RATEEN", 16, 1},
+ {"TSC7WRREN", 15, 1},
+ {"TSC7RATEEN", 14, 1},
+ {"TSC6WRREN", 13, 1},
+ {"TSC6RATEEN", 12, 1},
+ {"TSC5WRREN", 11, 1},
+ {"TSC5RATEEN", 10, 1},
+ {"TSC4WRREN", 9, 1},
+ {"TSC4RATEEN", 8, 1},
+ {"TSC3WRREN", 7, 1},
+ {"TSC3RATEEN", 6, 1},
+ {"TSC2WRREN", 5, 1},
+ {"TSC2RATEEN", 4, 1},
+ {"TSC1WRREN", 3, 1},
+ {"TSC1RATEEN", 2, 1},
+ {"TSC0WRREN", 1, 1},
+ {"TSC0RATEEN", 0, 1},
+ {"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4b48, 0},
+ {"TSC15WRREN", 31, 1},
+ {"TSC15RATEEN", 30, 1},
+ {"TSC14WRREN", 29, 1},
+ {"TSC14RATEEN", 28, 1},
+ {"TSC13WRREN", 27, 1},
+ {"TSC13RATEEN", 26, 1},
+ {"TSC12WRREN", 25, 1},
+ {"TSC12RATEEN", 24, 1},
+ {"TSC11WRREN", 23, 1},
+ {"TSC11RATEEN", 22, 1},
+ {"TSC10WRREN", 21, 1},
+ {"TSC10RATEEN", 20, 1},
+ {"TSC9WRREN", 19, 1},
+ {"TSC9RATEEN", 18, 1},
+ {"TSC8WRREN", 17, 1},
+ {"TSC8RATEEN", 16, 1},
+ {"TSC7WRREN", 15, 1},
+ {"TSC7RATEEN", 14, 1},
+ {"TSC6WRREN", 13, 1},
+ {"TSC6RATEEN", 12, 1},
+ {"TSC5WRREN", 11, 1},
+ {"TSC5RATEEN", 10, 1},
+ {"TSC4WRREN", 9, 1},
+ {"TSC4RATEEN", 8, 1},
+ {"TSC3WRREN", 7, 1},
+ {"TSC3RATEEN", 6, 1},
+ {"TSC2WRREN", 5, 1},
+ {"TSC2RATEEN", 4, 1},
+ {"TSC1WRREN", 3, 1},
+ {"TSC1RATEEN", 2, 1},
+ {"TSC0WRREN", 1, 1},
+ {"TSC0RATEEN", 0, 1},
+ {"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4c68, 0},
+ {"TSC15WRREN", 31, 1},
+ {"TSC15RATEEN", 30, 1},
+ {"TSC14WRREN", 29, 1},
+ {"TSC14RATEEN", 28, 1},
+ {"TSC13WRREN", 27, 1},
+ {"TSC13RATEEN", 26, 1},
+ {"TSC12WRREN", 25, 1},
+ {"TSC12RATEEN", 24, 1},
+ {"TSC11WRREN", 23, 1},
+ {"TSC11RATEEN", 22, 1},
+ {"TSC10WRREN", 21, 1},
+ {"TSC10RATEEN", 20, 1},
+ {"TSC9WRREN", 19, 1},
+ {"TSC9RATEEN", 18, 1},
+ {"TSC8WRREN", 17, 1},
+ {"TSC8RATEEN", 16, 1},
+ {"TSC7WRREN", 15, 1},
+ {"TSC7RATEEN", 14, 1},
+ {"TSC6WRREN", 13, 1},
+ {"TSC6RATEEN", 12, 1},
+ {"TSC5WRREN", 11, 1},
+ {"TSC5RATEEN", 10, 1},
+ {"TSC4WRREN", 9, 1},
+ {"TSC4RATEEN", 8, 1},
+ {"TSC3WRREN", 7, 1},
+ {"TSC3RATEEN", 6, 1},
+ {"TSC2WRREN", 5, 1},
+ {"TSC2RATEEN", 4, 1},
+ {"TSC1WRREN", 3, 1},
+ {"TSC1RATEEN", 2, 1},
+ {"TSC0WRREN", 1, 1},
+ {"TSC0RATEEN", 0, 1},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_4910_to_4c70[] = {
+ {"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4910, 0},
+ {"TSCHNLRATENEG", 31, 1},
+ {"TSCHNLRATEPROT", 30, 1},
+ {"TSCHNLRATEL", 0, 30},
+ {"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4a30, 0},
+ {"TSCHNLRATENEG", 31, 1},
+ {"TSCHNLRATEPROT", 30, 1},
+ {"TSCHNLRATEL", 0, 30},
+ {"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4b50, 0},
+ {"TSCHNLRATENEG", 31, 1},
+ {"TSCHNLRATEPROT", 30, 1},
+ {"TSCHNLRATEL", 0, 30},
+ {"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4c70, 0},
+ {"TSCHNLRATENEG", 31, 1},
+ {"TSCHNLRATEPROT", 30, 1},
+ {"TSCHNLRATEL", 0, 30},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_4914_to_4c74[] = {
+ {"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4914, 0},
+ {"TSCHNLRMAX", 16, 16},
+ {"TSCHNLRTSEL", 14, 2},
+ {"TSCHNLRINCR", 0, 14},
+ {"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4a34, 0},
+ {"TSCHNLRMAX", 16, 16},
+ {"TSCHNLRTSEL", 14, 2},
+ {"TSCHNLRINCR", 0, 14},
+ {"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4b54, 0},
+ {"TSCHNLRMAX", 16, 16},
+ {"TSCHNLRTSEL", 14, 2},
+ {"TSCHNLRINCR", 0, 14},
+ {"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4c74, 0},
+ {"TSCHNLRMAX", 16, 16},
+ {"TSCHNLRTSEL", 14, 2},
+ {"TSCHNLRINCR", 0, 14},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_4920_to_4a10[] = {
+ {"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4920, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4930, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4940, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4950, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4960, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4970, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4980, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4990, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49a0, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49b0, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49c0, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49d0, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49e0, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49f0, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4a00, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ {"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4a10, 0},
+ {"TSCCLRATENEG", 31, 1},
+ {"TSCCLRATEPROT", 30, 1},
+ {"TSCCLRATEL", 0, 24},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_4924_to_4a14[] = {
+ {"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4924, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4934, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4944, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4954, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4964, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4974, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4984, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4994, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49a4, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49b4, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49c4, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49d4, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49e4, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49f4, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4a04, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ {"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4a14, 0},
+ {"TSCCLRMAX", 16, 16},
+ {"TSCCLRTSEL", 14, 2},
+ {"TSCCLRINCR", 0, 14},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_4928_to_4a18[] = {
+ {"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4928, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4938, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4948, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4958, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4968, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4978, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4988, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4998, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49a8, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49b8, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49c8, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49d8, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49e8, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49f8, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4a08, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ {"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4a18, 0},
+ {"TSCCLWRRNEG", 31, 1},
+ {"TSCCLWRRPROT", 30, 1},
+ {"TSCCLWRR", 0, 26},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_492c_to_4a1c[] = {
+ {"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x492c, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x493c, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x494c, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x495c, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x496c, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x497c, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x498c, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x499c, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49ac, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49bc, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49cc, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49dc, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49ec, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49fc, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x4a0c, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ {"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x4a1c, 0},
+ {"PAUSEVECSEL", 28, 2},
+ {"MPSPAUSEMASK", 20, 8},
+ {"TSCCLWEIGHT", 0, 16},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_2080_to_20fc[] = {
+ {"CIM_CTL_STATIC_ALLOCADDR12", 0x2080, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR13", 0x2084, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR14", 0x2088, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR15", 0x208c, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_FIFO_CNT", 0x2090, 0},
+ {"CtlFifoCnt", 0, 4},
+ {"CIM_CTL_GLB_TIMER", 0x2094, 0},
+ {"GlblTimer", 0, 32},
+ {"CIM_CTL_TIMER0", 0x2098, 0},
+ {"Timer0", 0, 32},
+ {"CIM_CTL_TIMER1", 0x209c, 0},
+ {"Timer1", 0, 32},
+ {"CIM_CTL_GEN0", 0x20a0, 0},
+ {"Gen0", 0, 32},
+ {"CIM_CTL_GEN1", 0x20a4, 0},
+ {"Gen1", 0, 32},
+ {"CIM_CTL_GEN2", 0x20a8, 0},
+ {"Gen2", 0, 32},
+ {"CIM_CTL_GEN3", 0x20ac, 0},
+ {"Gen3", 0, 32},
+ {"CIM_CTL_GLB_TIMER_TICK", 0x20b0, 0},
+ {"GlblTTick", 0, 16},
+ {"CIM_CTL_GEN_TIMER0_CTL", 0x20b4, 0},
+ {"GenTimerRun", 7, 1},
+ {"GenTimerTrig", 6, 1},
+ {"GenTimerAct", 4, 2},
+ {"GenTimerCfg", 2, 2},
+ {"GenTimerStop", 1, 1},
+ {"GenTimerStrt", 0, 1},
+ {"CIM_CTL_GEN_TIMER0", 0x20b8, 0},
+ {"GenTimer0", 0, 32},
+ {"CIM_CTL_GEN_TIMER1_CTL", 0x20bc, 0},
+ {"GenTimerRun", 7, 1},
+ {"GenTimerTrig", 6, 1},
+ {"GenTimerAct", 4, 2},
+ {"GenTimerCfg", 2, 2},
+ {"GenTimerStop", 1, 1},
+ {"GenTimerStrt", 0, 1},
+ {"CIM_CTL_GEN_TIMER1", 0x20c0, 0},
+ {"GenTimer0", 0, 32},
+ {"CIM_CTL_GEN_TIMER2_CTL", 0x20c4, 0},
+ {"GenTimerRun", 7, 1},
+ {"GenTimerTrig", 6, 1},
+ {"GenTimerAct", 4, 2},
+ {"GenTimerCfg", 2, 2},
+ {"GenTimerStop", 1, 1},
+ {"GenTimerStrt", 0, 1},
+ {"CIM_CTL_GEN_TIMER2", 0x20c8, 0},
+ {"GenTimer0", 0, 32},
+ {"CIM_CTL_GEN_TIMER3_CTL", 0x20cc, 0},
+ {"GenTimerRun", 7, 1},
+ {"GenTimerTrig", 6, 1},
+ {"GenTimerAct", 4, 2},
+ {"GenTimerCfg", 2, 2},
+ {"GenTimerStop", 1, 1},
+ {"GenTimerStrt", 0, 1},
+ {"CIM_CTL_GEN_TIMER3", 0x20d0, 0},
+ {"GenTimer0", 0, 32},
+ {"CIM_CTL_0_MAILBOX_VF_STATUS", 0x20e0, 0},
+ {"MBVFStatus", 0, 32},
+ {"CIM_CTL_1_MAILBOX_VF_STATUS", 0x20e4, 0},
+ {"MBVFStatus", 0, 32},
+ {"CIM_CTL_2_MAILBOX_VF_STATUS", 0x20e8, 0},
+ {"MBVFStatus", 0, 32},
+ {"CIM_CTL_3_MAILBOX_VF_STATUS", 0x20ec, 0},
+ {"MBVFStatus", 0, 32},
+ {"CIM_CTL_4_MAILBOX_VF_STATUS", 0x20f0, 0},
+ {"MBVFStatus", 0, 32},
+ {"CIM_CTL_5_MAILBOX_VF_STATUS", 0x20f4, 0},
+ {"MBVFStatus", 0, 32},
+ {"CIM_CTL_6_MAILBOX_VF_STATUS", 0x20f8, 0},
+ {"MBVFStatus", 0, 32},
+ {"CIM_CTL_7_MAILBOX_VF_STATUS", 0x20fc, 0},
+ {"MBVFStatus", 0, 32},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_2080_to_20ec[] = {
+ {"CIM_CTL_STATIC_ALLOCADDR12", 0x2080, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR13", 0x2084, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR14", 0x2088, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_STATIC_ALLOCADDR15", 0x208c, 0},
+ {"StaticAllocAddr", 0, 32},
+ {"CIM_CTL_FIFO_CNT", 0x2090, 0},
+ {"CtlFifoCnt", 0, 4},
+ {"CIM_CTL_GLB_TIMER", 0x2094, 0},
+ {"GlblTimer", 0, 32},
+ {"CIM_CTL_TIMER0", 0x2098, 0},
+ {"Timer0", 0, 32},
+ {"CIM_CTL_TIMER1", 0x209c, 0},
+ {"Timer1", 0, 32},
+ {"CIM_CTL_GEN0", 0x20a0, 0},
+ {"Gen0", 0, 32},
+ {"CIM_CTL_GEN1", 0x20a4, 0},
+ {"Gen1", 0, 32},
+ {"CIM_CTL_GEN2", 0x20a8, 0},
+ {"Gen2", 0, 32},
+ {"CIM_CTL_GEN3", 0x20ac, 0},
+ {"Gen3", 0, 32},
+ {"CIM_CTL_GLB_TIMER_TICK", 0x20b0, 0},
+ {"GlblTTick", 0, 16},
+ {"CIM_CTL_GEN_TIMER0_CTL", 0x20b4, 0},
+ {"GenTimerRun", 7, 1},
+ {"GenTimerTrig", 6, 1},
+ {"GenTimerAct", 4, 2},
+ {"GenTimerCfg", 2, 2},
+ {"GenTimerStop", 1, 1},
+ {"GenTimerStrt", 0, 1},
+ {"CIM_CTL_GEN_TIMER0", 0x20b8, 0},
+ {"GenTimer0", 0, 32},
+ {"CIM_CTL_GEN_TIMER1_CTL", 0x20bc, 0},
+ {"GenTimerRun", 7, 1},
+ {"GenTimerTrig", 6, 1},
+ {"GenTimerAct", 4, 2},
+ {"GenTimerCfg", 2, 2},
+ {"GenTimerStop", 1, 1},
+ {"GenTimerStrt", 0, 1},
+ {"CIM_CTL_GEN_TIMER1", 0x20c0, 0},
+ {"GenTimer0", 0, 32},
+ {"CIM_CTL_GEN_TIMER2_CTL", 0x20c4, 0},
+ {"GenTimerRun", 7, 1},
+ {"GenTimerTrig", 6, 1},
+ {"GenTimerAct", 4, 2},
+ {"GenTimerCfg", 2, 2},
+ {"GenTimerStop", 1, 1},
+ {"GenTimerStrt", 0, 1},
+ {"CIM_CTL_GEN_TIMER2", 0x20c8, 0},
+ {"GenTimer0", 0, 32},
+ {"CIM_CTL_GEN_TIMER3_CTL", 0x20cc, 0},
+ {"GenTimerRun", 7, 1},
+ {"GenTimerTrig", 6, 1},
+ {"GenTimerAct", 4, 2},
+ {"GenTimerCfg", 2, 2},
+ {"GenTimerStop", 1, 1},
+ {"GenTimerStrt", 0, 1},
+ {"CIM_CTL_GEN_TIMER3", 0x20d0, 0},
+ {"GenTimer0", 0, 32},
+ {"CIM_CTL_0_MAILBOX_VF_STATUS", 0x20e0, 0},
+ {"MBVFStatus", 0, 32},
+ {"CIM_CTL_1_MAILBOX_VF_STATUS", 0x20e4, 0},
+ {"MBVFStatus", 0, 32},
+ {"CIM_CTL_2_MAILBOX_VF_STATUS", 0x20e8, 0},
+ {"MBVFStatus", 0, 32},
+ {"CIM_CTL_3_MAILBOX_VF_STATUS", 0x20ec, 0},
+ {"MBVFStatus", 0, 32},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_00_to_7c[] = {
+ {"UP_IBQ_CONFIG", 0x0, 0},
+ {"IbqGen2", 2, 30},
+ {"IbqBusy", 1, 1},
+ {"IbqEn", 0, 1},
+ {"UP_OBQ_CONFIG", 0x4, 0},
+ {"ObqGen2", 2, 30},
+ {"ObqBusy", 1, 1},
+ {"ObqEn", 0, 1},
+ {"UP_IBQ_GEN", 0x8, 0},
+ {"IbqGen0", 22, 10},
+ {"IbqTSCHChnlRdy", 18, 5},
+ {"IbqMBVFStatus", 17, 1},
+ {"IbqMBStatus", 16, 1},
+ {"IbqGen1", 6, 10},
+ {"IbqEmpty", 0, 6},
+ {"UP_OBQ_GEN", 0xc, 0},
+ {"ObqGen", 8, 25},
+ {"ObqFull", 0, 8},
+ {"UP_IBQ_0_RDADDR", 0x10, 0},
+ {"QueID", 13, 19},
+ {"QueRdAddr", 0, 13},
+ {"UP_IBQ_0_WRADDR", 0x14, 0},
+ {"QueID", 13, 19},
+ {"QueWrAddr", 0, 13},
+ {"UP_IBQ_0_STATUS", 0x18, 0},
+ {"QueErrFrame", 31, 1},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_0_PKTCNT", 0x1c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_1_RDADDR", 0x20, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_1_WRADDR", 0x24, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_1_STATUS", 0x28, 0},
+ {"QueErrFrame", 31, 1},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_1_PKTCNT", 0x2c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_2_RDADDR", 0x30, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_2_WRADDR", 0x34, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_2_STATUS", 0x38, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_2_PKTCNT", 0x3c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_3_RDADDR", 0x40, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_3_WRADDR", 0x44, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_3_STATUS", 0x48, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_3_PKTCNT", 0x4c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_4_RDADDR", 0x50, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_4_WRADDR", 0x54, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_4_STATUS", 0x58, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_4_PKTCNT", 0x5c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_5_RDADDR", 0x60, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_5_WRADDR", 0x64, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_5_STATUS", 0x68, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_5_PKTCNT", 0x6c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_0_RDADDR", 0x70, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_0_WRADDR", 0x74, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_0_STATUS", 0x78, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_0_PKTCNT", 0x7c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_80_to_fc[] = {
+ {"UP_OBQ_1_RDADDR", 0x80, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_1_WRADDR", 0x84, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_1_STATUS", 0x88, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_1_PKTCNT", 0x8c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_2_RDADDR", 0x90, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_2_WRADDR", 0x94, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_2_STATUS", 0x98, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_2_PKTCNT", 0x9c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_3_RDADDR", 0xa0, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_3_WRADDR", 0xa4, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_3_STATUS", 0xa8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_3_PKTCNT", 0xac, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_4_RDADDR", 0xb0, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_4_WRADDR", 0xb4, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_4_STATUS", 0xb8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_4_PKTCNT", 0xbc, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_5_RDADDR", 0xc0, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_5_WRADDR", 0xc4, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_5_STATUS", 0xc8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_5_PKTCNT", 0xcc, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_0_CONFIG", 0xd0, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"Que1KEn", 6, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_0_REALADDR", 0xd4, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_1_CONFIG", 0xd8, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"Que1KEn", 6, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_1_REALADDR", 0xdc, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_2_CONFIG", 0xe0, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"Que1KEn", 6, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_2_REALADDR", 0xe4, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_3_CONFIG", 0xe8, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"Que1KEn", 6, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_3_REALADDR", 0xec, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_4_CONFIG", 0xf0, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"Que1KEn", 6, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_4_REALADDR", 0xf4, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_5_CONFIG", 0xf8, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"Que1KEn", 6, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_5_REALADDR", 0xfc, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_80_to_fc[] = {
+ {"UP_OBQ_1_RDADDR", 0x80, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_1_WRADDR", 0x84, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_1_STATUS", 0x88, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_1_PKTCNT", 0x8c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_2_RDADDR", 0x90, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_2_WRADDR", 0x94, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_2_STATUS", 0x98, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_2_PKTCNT", 0x9c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_3_RDADDR", 0xa0, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_3_WRADDR", 0xa4, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_3_STATUS", 0xa8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_3_PKTCNT", 0xac, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_4_RDADDR", 0xb0, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_4_WRADDR", 0xb4, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_4_STATUS", 0xb8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_4_PKTCNT", 0xbc, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_5_RDADDR", 0xc0, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_5_WRADDR", 0xc4, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_5_STATUS", 0xc8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_5_PKTCNT", 0xcc, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_0_CONFIG", 0xd0, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_0_REALADDR", 0xd4, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_1_CONFIG", 0xd8, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_1_REALADDR", 0xdc, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_2_CONFIG", 0xe0, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_2_REALADDR", 0xe4, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_3_CONFIG", 0xe8, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_3_REALADDR", 0xec, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_4_CONFIG", 0xf0, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_4_REALADDR", 0xf4, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_5_CONFIG", 0xf8, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_5_REALADDR", 0xfc, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_100_to_14c[] = {
+ {"UP_OBQ_0_CONFIG", 0x100, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_0_REALADDR", 0x104, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_1_CONFIG", 0x108, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_1_REALADDR", 0x10c, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_2_CONFIG", 0x110, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_2_REALADDR", 0x114, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_3_CONFIG", 0x118, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_3_REALADDR", 0x11c, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_4_CONFIG", 0x120, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_4_REALADDR", 0x124, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_5_CONFIG", 0x128, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_5_REALADDR", 0x12c, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_MAILBOX_STATUS", 0x130, 0},
+ {"MBGen0", 31, 20},
+ {"GenTimerTrig", 19, 16},
+ {"MBGen1", 8, 8},
+ {"MBPFInt", 0, 8},
+ {"UP_UP_DBG_LA_CFG", 0x140, 0},
+ {"UpDbgLaCaptBub", 31, 1},
+ {"UpDbgLaCaptPCOnly", 30, 1},
+ {"UpDbgLaMaskStop", 29, 1},
+ {"UpDbgLaMaskTrig", 28, 1},
+ {"UpDbgLaWrPtr", 16, 12},
+ {"UpDbgLaBusy", 14, 1},
+ {"UpDbgLaRdPtr", 2, 12},
+ {"UpDbgLaRdEn", 1, 1},
+ {"UpDbgLaEn", 0, 1},
+ {"UP_UP_DBG_LA_DATA", 0x144, 0},
+ {"UpDbgLaWrData", 0, 32},
+ {"UP_PIO_MST_CONFIG", 0x148, 0},
+ {"ReqVFVld", 27, 1},
+ {"FLSrc", 24, 3},
+ {"SEProt", 23, 1},
+ {"SESrc", 20, 3},
+ {"UpRgn", 19, 1},
+ {"UpPF", 16, 3},
+ {"UpRID", 8, 8},
+ {"UP_UP_SELF_CONTROL", 0x14c, 0},
+ {"UpSelfReset", 0, 1},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_100_to_14c[] = {
+ {"UP_OBQ_0_CONFIG", 0x100, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_0_REALADDR", 0x104, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_1_CONFIG", 0x108, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_1_REALADDR", 0x10c, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_2_CONFIG", 0x110, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_2_REALADDR", 0x114, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_3_CONFIG", 0x118, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_3_REALADDR", 0x11c, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_4_CONFIG", 0x120, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_4_REALADDR", 0x124, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_5_CONFIG", 0x128, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_5_REALADDR", 0x12c, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_MAILBOX_STATUS", 0x130, 0},
+ {"MBGen0", 31, 20},
+ {"GenTimerTrig", 19, 16},
+ {"MBGen1", 8, 8},
+ {"MBPFInt", 0, 8},
+ {"UP_UP_DBG_LA_CFG", 0x140, 0},
+ {"UpDbgLaCaptBub", 31, 1},
+ {"UpDbgLaCaptPCOnly", 30, 1},
+ {"UpDbgLaMaskStop", 29, 1},
+ {"UpDbgLaMaskTrig", 28, 1},
+ {"UpDbgLaWrPtr", 16, 12},
+ {"UpDbgLaBusy", 14, 1},
+ {"UpDbgLaRdPtr", 2, 12},
+ {"UpDbgLaRdEn", 1, 1},
+ {"UpDbgLaEn", 0, 1},
+ {"UP_UP_DBG_LA_DATA", 0x144, 0},
+ {"UpDbgLaWrData", 0, 32},
+ {"UP_PIO_MST_CONFIG", 0x148, 0},
+ {"ReqVFVld", 27, 1},
+ {"FLSrc", 24, 3},
+ {"SEProt", 23, 1},
+ {"SESrc", 20, 3},
+ {"UpRgn", 19, 1},
+ {"UpPF", 16, 3},
+ {"RSVD", 8, 8},
+ {"UpRID", 0, 8},
+ {"UP_UP_SELF_CONTROL", 0x14c, 0},
+ {"UpSelfReset", 0, 1},
+ { NULL }
+};
+
+static struct cudbg_reg_info t6_up_cim_200_to_23c[] = {
+ {"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_RDY", 0x200, 0},
+ {"TSCHCHNLCRDY", 0, 32},
+ {"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_RDY", 0x204, 0},
+ {"TSCHWRRLIMIT", 16, 16},
+ {"TSCHCHNLCWRDY", 0, 16},
+ {"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_LIST", 0x208, 0},
+ {"TSCHWRRRELOAD", 16, 16},
+ {"TSCHCHNLCWATCH", 0, 16},
+ {"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_TAKE", 0x20c, 0},
+ {"TSCHCHNLCHDIS", 31, 1},
+ {"TSCHCHNLWDIS", 30, 1},
+ {"TSCHCHNLCLDIS", 29, 1},
+ {"TSCHCHNLCNUM", 24, 5},
+ {"TSCHCHNLCCNT", 0, 24},
+ {"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_RDY", 0x210, 0},
+ {"TSCHCHNLCRDY", 0, 32},
+ {"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_WATCH_RDY", 0x214, 0},
+ {"TSCHWRRLIMIT", 16, 16},
+ {"TSCHCHNLCWRDY", 0, 16},
+ {"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_WATCH_LIST", 0x218, 0},
+ {"TSCHWRRRELOAD", 16, 16},
+ {"TSCHCHNLCWATCH", 0, 16},
+ {"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_TAKE", 0x21c, 0},
+ {"TSCHCHNLCHDIS", 31, 1},
+ {"TSCHCHNLWDIS", 30, 1},
+ {"TSCHCHNLCLDIS", 29, 1},
+ {"TSCHCHNLCNUM", 24, 5},
+ {"TSCHCHNLCCNT", 0, 24},
+ {"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_RDY", 0x220, 0},
+ {"TSCHCHNLCRDY", 0, 32},
+ {"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_WATCH_RDY", 0x224, 0},
+ {"TSCHWRRLIMIT", 16, 16},
+ {"TSCHCHNLCWRDY", 0, 16},
+ {"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_WATCH_LIST", 0x228, 0},
+ {"TSCHWRRRELOAD", 16, 16},
+ {"TSCHCHNLCWATCH", 0, 16},
+ {"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_TAKE", 0x22c, 0},
+ {"TSCHCHNLCHDIS", 31, 1},
+ {"TSCHCHNLWDIS", 30, 1},
+ {"TSCHCHNLCLDIS", 29, 1},
+ {"TSCHCHNLCNUM", 24, 5},
+ {"TSCHCHNLCCNT", 0, 24},
+ {"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_RDY", 0x230, 0},
+ {"TSCHCHNLCRDY", 0, 32},
+ {"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_WATCH_RDY", 0x234, 0},
+ {"TSCHWRRLIMIT", 16, 16},
+ {"TSCHCHNLCWRDY", 0, 16},
+ {"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_WATCH_LIST", 0x238, 0},
+ {"TSCHWRRRELOAD", 16, 16},
+ {"TSCHCHNLCWATCH", 0, 16},
+ {"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_TAKE", 0x23c, 0},
+ {"TSCHCHNLCHDIS", 31, 1},
+ {"TSCHCHNLWDIS", 30, 1},
+ {"TSCHCHNLCLDIS", 29, 1},
+ {"TSCHCHNLCNUM", 24, 5},
+ {"TSCHCHNLCCNT", 0, 24},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_200_to_23c[] = {
+ {"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_RDY", 0x200, 0},
+ {"ECO_15444_SGE_DB_BUSY", 31, 1},
+ {"ECO_15444_PL_INTF_BUSY", 30, 1},
+ {"TSCHCHNLCRDY", 0, 30},
+ {"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_RDY", 0x204, 0},
+ {"TSCHWRRLIMIT", 16, 16},
+ {"TSCHCHNLCWRDY", 0, 16},
+ {"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_LIST", 0x208, 0},
+ {"TSCHWRRRELOAD", 16, 16},
+ {"TSCHCHNLCWATCH", 0, 16},
+ {"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_TAKE", 0x20c, 0},
+ {"TSCHCHNLCNUM", 24, 5},
+ {"TSCHCHNLCCNT", 0, 24},
+ {"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_RDY", 0x210, 0},
+ {"ECO_15444_SGE_DB_BUSY", 31, 1},
+ {"ECO_15444_PL_INTF_BUSY", 30, 1},
+ {"TSCHCHNLCRDY", 0, 30},
+ {"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_WATCH_RDY", 0x214, 0},
+ {"TSCHWRRLIMIT", 16, 16},
+ {"TSCHCHNLCWRDY", 0, 16},
+ {"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_WATCH_LIST", 0x218, 0},
+ {"TSCHWRRRELOAD", 16, 16},
+ {"TSCHCHNLCWATCH", 0, 16},
+ {"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_TAKE", 0x21c, 0},
+ {"TSCHCHNLCNUM", 24, 5},
+ {"TSCHCHNLCCNT", 0, 24},
+ {"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_RDY", 0x220, 0},
+ {"ECO_15444_SGE_DB_BUSY", 31, 1},
+ {"ECO_15444_PL_INTF_BUSY", 30, 1},
+ {"TSCHCHNLCRDY", 0, 30},
+ {"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_WATCH_RDY", 0x224, 0},
+ {"TSCHWRRLIMIT", 16, 16},
+ {"TSCHCHNLCWRDY", 0, 16},
+ {"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_WATCH_LIST", 0x228, 0},
+ {"TSCHWRRRELOAD", 16, 16},
+ {"TSCHCHNLCWATCH", 0, 16},
+ {"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_TAKE", 0x22c, 0},
+ {"TSCHCHNLCNUM", 24, 5},
+ {"TSCHCHNLCCNT", 0, 24},
+ {"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_RDY", 0x230, 0},
+ {"ECO_15444_SGE_DB_BUSY", 31, 1},
+ {"ECO_15444_PL_INTF_BUSY", 30, 1},
+ {"TSCHCHNLCRDY", 0, 30},
+ {"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_WATCH_RDY", 0x234, 0},
+ {"TSCHWRRLIMIT", 16, 16},
+ {"TSCHCHNLCWRDY", 0, 16},
+ {"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_WATCH_LIST", 0x238, 0},
+ {"TSCHWRRRELOAD", 16, 16},
+ {"TSCHCHNLCWATCH", 0, 16},
+ {"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_TAKE", 0x23c, 0},
+ {"TSCHCHNLCNUM", 24, 5},
+ {"TSCHCHNLCCNT", 0, 24},
+ { NULL }
+
+};
+
+static struct cudbg_reg_info t5_up_cim_240_to_244[] = {
+ {"UP_UpLaDbgPcChkData_0", 0x240, 0},
+ {"UpLaPcData", 0, 32},
+ {"UP_UpLaDbgPcChkMask_0", 0x244, 0},
+ {"UpLaPcMask", 0, 32},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_250_to_254[] = {
+ {"UP_UpLaDbgPcChkData_1", 0x250, 0},
+ {"UpLaPcData", 0, 32},
+ {"UP_UpLaDbgPcChkMask_1", 0x254, 0},
+ {"UpLaPcMask", 0, 32},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_260_to_264[] = {
+ {"UP_UpLaDbgPcChkData_2", 0x260, 0},
+ {"UpLaPcData", 0, 32},
+ {"UP_UpLaDbgPcChkMask_2", 0x264, 0},
+ {"UpLaPcMask", 0, 32},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_270_to_274[] = {
+ {"UP_UpLaDbgPcChkData_3", 0x270, 0},
+ {"UpLaPcData", 0, 32},
+ {"UP_UpLaDbgPcChkMask_3", 0x274, 0},
+ {"UpLaPcMask", 0, 32},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_280_to_2fc[] = {
+ {"UP_IBQ_0_SHADOW_RDADDR", 0x280, 0},
+ {"QueID", 13, 19},
+ {"QueRdAddr", 0, 13},
+ {"UP_IBQ_0_SHADOW_WRADDR", 0x284, 0},
+ {"QueID", 13, 19},
+ {"QueWrAddr", 0, 13},
+ {"UP_IBQ_0_SHADOW_STATUS", 0x288, 0},
+ {"QueErrFrame", 31, 1},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_0_SHADOW_PKTCNT", 0x28c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_1_SHADOW_RDADDR", 0x290, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_1_SHADOW_WRADDR", 0x294, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_1_SHADOW_STATUS", 0x298, 0},
+ {"QueErrFrame", 31, 1},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_1_SHADOW_PKTCNT", 0x29c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_2_SHADOW_RDADDR", 0x2a0, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_2_SHADOW_WRADDR", 0x2a4, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_2_SHADOW_STATUS", 0x2a8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_2_SHADOW_PKTCNT", 0x2ac, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_3_SHADOW_RDADDR", 0x2b0, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_3_SHADOW_WRADDR", 0x2b4, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_3_SHADOW_STATUS", 0x2b8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_3_SHADOW_PKTCNT", 0x2bc, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_4_SHADOW_RDADDR", 0x2c0, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_4_SHADOW_WRADDR", 0x2c4, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_4_SHADOW_STATUS", 0x2c8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_4_SHADOW_PKTCNT", 0x2cc, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_5_SHADOW_RDADDR", 0x2d0, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_5_SHADOW_WRADDR", 0x2d4, 0},
+ {"QueID", 13, 19},
+ {"UP_IBQ_5_SHADOW_STATUS", 0x2d8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_IBQ_5_SHADOW_PKTCNT", 0x2dc, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_0_SHADOW_RDADDR", 0x2e0, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_0_SHADOW_WRADDR", 0x2e4, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_0_SHADOW_STATUS", 0x2e8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_0_SHADOW_PKTCNT", 0x2ec, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_1_SHADOW_RDADDR", 0x2f0, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_1_SHADOW_WRADDR", 0x2f4, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_1_SHADOW_STATUS", 0x2f8, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_1_SHADOW_PKTCNT", 0x2fc, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_300_to_37c[] = {
+ {"UP_OBQ_2_SHADOW_RDADDR", 0x300, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_2_SHADOW_WRADDR", 0x304, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_2_SHADOW_STATUS", 0x308, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_2_SHADOW_PKTCNT", 0x30c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_3_SHADOW_RDADDR", 0x310, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_3_SHADOW_WRADDR", 0x314, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_3_SHADOW_STATUS", 0x318, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_3_SHADOW_PKTCNT", 0x31c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_4_SHADOW_RDADDR", 0x320, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_4_SHADOW_WRADDR", 0x324, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_4_SHADOW_STATUS", 0x328, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_4_SHADOW_PKTCNT", 0x32c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_5_SHADOW_RDADDR", 0x330, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_5_SHADOW_WRADDR", 0x334, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_5_SHADOW_STATUS", 0x338, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_5_SHADOW_PKTCNT", 0x33c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_6_SHADOW_RDADDR", 0x340, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_6_SHADOW_WRADDR", 0x344, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_6_SHADOW_STATUS", 0x348, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_6_SHADOW_PKTCNT", 0x34c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_OBQ_7_SHADOW_RDADDR", 0x350, 0},
+ {"QueID", 15, 17},
+ {"QueRdAddr", 0, 15},
+ {"UP_OBQ_7_SHADOW_WRADDR", 0x354, 0},
+ {"QueID", 15, 17},
+ {"QueWrAddr", 0, 15},
+ {"UP_OBQ_7_SHADOW_STATUS", 0x358, 0},
+ {"QueRemFlits", 0, 11},
+ {"UP_OBQ_7_SHADOW_PKTCNT", 0x35c, 0},
+ {"QueEOPCnt", 16, 12},
+ {"QueSOPCnt", 0, 12},
+ {"UP_IBQ_0_SHADOW_CONFIG", 0x360, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_0_SHADOW_REALADDR", 0x364, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_1_SHADOW_CONFIG", 0x368, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_1_SHADOW_REALADDR", 0x36c, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_2_SHADOW_CONFIG", 0x370, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_2_SHADOW_REALADDR", 0x374, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_3_SHADOW_CONFIG", 0x378, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_3_SHADOW_REALADDR", 0x37c, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ { NULL }
+};
+
+static struct cudbg_reg_info t5_up_cim_380_to_3cc[] = {
+ {"UP_IBQ_4_SHADOW_CONFIG", 0x380, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_4_SHADOW_REALADDR", 0x384, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_IBQ_5_SHADOW_CONFIG", 0x388, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_IBQ_5_SHADOW_REALADDR", 0x38c, 0},
+ {"QueRdAddrWrap", 31, 1},
+ {"QueWrAddrWrap", 30, 1},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_0_SHADOW_CONFIG", 0x390, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_0_SHADOW_REALADDR", 0x394, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_1_SHADOW_CONFIG", 0x398, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_1_SHADOW_REALADDR", 0x39c, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_2_SHADOW_CONFIG", 0x3a0, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_2_SHADOW_REALADDR", 0x3a4, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_3_SHADOW_CONFIG", 0x3a8, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_3_SHADOW_REALADDR", 0x3ac, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_4_SHADOW_CONFIG", 0x3b0, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_4_SHADOW_REALADDR", 0x3b4, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_5_SHADOW_CONFIG", 0x3b8, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_5_SHADOW_REALADDR", 0x3bc, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_6_SHADOW_CONFIG", 0x3c0, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_6_SHADOW_REALADDR", 0x3c4, 0},
+ {"QueMemAddr", 3, 11},
+ {"UP_OBQ_7_SHADOW_CONFIG", 0x3c8, 0},
+ {"QueSize", 26, 6},
+ {"QueBase", 8, 6},
+ {"QueDbg8BEn", 7, 1},
+ {"QueBareAddr", 0, 1},
+ {"UP_OBQ_7_SHADOW_REALADDR", 0x3cc, 0},
+ {"QueMemAddr", 3, 11},
+ { NULL }
+};
+
+static struct cudbg_reg_info *t6_tp_pio_ptr[] = {
+ t6_tp_pio_regs_20_to_3b,
+ t6_tp_pio_regs_40_to_49,
+ t6_tp_pio_regs_50_to_59,
+ t6_tp_pio_regs_60_to_6d,
+ t6_tp_pio_regs_6f,
+ t6_tp_pio_regs_70_to_75,
+ t6_tp_pio_regs_130_to_141,
+ t6_tp_pio_regs_145_to_157,
+ t6_tp_pio_regs_160,
+ t6_tp_pio_regs_230_to_248,
+ t6_tp_pio_regs_24c,
+ t6_tp_pio_regs_8c0
+};
+
+static struct cudbg_reg_info *t5_tp_pio_ptr[] = {
+ t5_tp_pio_regs_20_to_3b,
+ t5_tp_pio_regs_40_to_52,
+ t5_tp_pio_regs_54_to_55,
+ t5_tp_pio_regs_60_to_6c,
+ t5_tp_pio_regs_6f,
+ t5_tp_pio_regs_120_to_123,
+ t5_tp_pio_regs_12b_to_12c,
+ t5_tp_pio_regs_12f_to_143,
+ t5_tp_pio_regs_145_to_157,
+ t5_tp_pio_regs_230_to_248,
+ t5_tp_pio_regs_8c0
+};
+
+static struct cudbg_reg_info *t5_pm_tx_ptr[] = {
+ t5_pm_tx_regs_10000_to_10020,
+ t5_pm_tx_regs_10021_to_1003c,
+};
+
+static struct cudbg_reg_info *t5_pm_rx_ptr[] = {
+ t5_pm_rx_regs_10000_to_10020,
+ t5_pm_rx_regs_10021_to_1002c,
+};
+
+static struct cudbg_reg_info *t5_pcie_pdbg_ptr[] = {
+ t5_pcie_pdbg_regs_00_to_20,
+ t5_pcie_pdbg_regs_21_to_40,
+ t5_pcie_pdbg_regs_41_to_50,
+};
+
+static struct cudbg_reg_info *t5_pcie_config_ptr[] = {
+ t5_pcie_config_regs_00_to_208,
+};
+
+static struct cudbg_reg_info *t5_pcie_cdbg_ptr[] = {
+ t5_pcie_cdbg_regs_00_to_20,
+ t5_pcie_cdbg_regs_21_to_37,
+};
+
+static struct cudbg_reg_info *t6_hma_ptr[] = {
+ t6_hma_regs_a000_to_a01f,
+};
+
+static struct cudbg_reg_info *t6_ma_ptr[] = {
+ t6_ma_regs_a000_to_a016,
+ t6_ma_regs_a400_to_a41e,
+ t6_ma_regs_a800_to_a813,
+ t6_ma_regs_e400_to_e600,
+ t6_ma_regs_e640_to_e7c0,
+};
+
+static struct cudbg_reg_info *t6_up_cim_reg_ptr[] = {
+ t6_up_cim_2000_to_207c,
+ t6_up_cim_2080_to_20fc,
+ t5_up_cim_00_to_7c,
+ t6_up_cim_80_to_fc,
+ t6_up_cim_100_to_14c,
+ t6_up_cim_200_to_23c,
+ t5_up_cim_240_to_244,
+ t5_up_cim_250_to_254,
+ t5_up_cim_260_to_264,
+ t5_up_cim_270_to_274,
+ t5_up_cim_280_to_2fc,
+ t5_up_cim_300_to_37c,
+ t5_up_cim_380_to_3cc,
+ t6_up_cim_4900_to_4c60,
+ t6_up_cim_4904_to_4c64,
+ t6_up_cim_4908_to_4c68,
+ t6_up_cim_4910_to_4c70,
+ t6_up_cim_4914_to_4c74,
+ t6_up_cim_4920_to_4a10,
+ t6_up_cim_4924_to_4a14,
+ t6_up_cim_4928_to_4a18,
+ t6_up_cim_492c_to_4a1c,
+};
+
+static struct cudbg_reg_info *t5_up_cim_reg_ptr[] = {
+ t5_up_cim_2000_to_207c,
+ t5_up_cim_2080_to_20ec,
+ t5_up_cim_00_to_7c,
+ t5_up_cim_80_to_fc,
+ t5_up_cim_100_to_14c,
+ t5_up_cim_200_to_23c,
+ t5_up_cim_240_to_244,
+ t5_up_cim_250_to_254,
+ t5_up_cim_260_to_264,
+ t5_up_cim_270_to_274,
+ t5_up_cim_280_to_2fc,
+ t5_up_cim_300_to_37c,
+ t5_up_cim_380_to_3cc,
+};
+
+#define TP_TM_PIO_ADDR A_TP_TM_PIO_ADDR
+#define TP_MIB_INDEX A_TP_MIB_INDEX
+#define TP_PIO A_TP_PIO_ADDR
+#define PM_RX_INDIRECT A_PM_RX_STAT_LSB
+#define PM_TX_INDIRECT A_PM_TX_STAT_LSB
+#define PCIE_CDEBUG_INDIRECT A_PCIE_CDEBUG_INDEX
+#define PCIE_PDEBUG_INDIRECT A_PCIE_PDEBUG_INDEX
+#define SGE_DEBUG_DATA_INDIRECT A_SGE_DEBUG_INDEX
+
+#endif
diff --git a/usr/src/cmd/cxgbetool/cxgbetool.c b/usr/src/cmd/cxgbetool/cxgbetool.c
index ff5c01427a..c38b5ab5ca 100644
--- a/usr/src/cmd/cxgbetool/cxgbetool.c
+++ b/usr/src/cmd/cxgbetool/cxgbetool.c
@@ -36,6 +36,24 @@
#include "version.h"
#include "osdep.h"
#include "t4fw_interface.h"
+#include "cudbg.h"
+#include "cudbg_lib_common.h"
+
+#define CUDBG_SIZE (32 * 1024 * 1024)
+#define CUDBG_MAX_ENTITY_STR_LEN 4096
+#define MAX_PARAM_LEN 4096
+
+char *option_list[] = {
+ "--collect",
+ "--view",
+ "--version",
+};
+
+enum {
+ CUDBG_OPT_COLLECT,
+ CUDBG_OPT_VIEW,
+ CUDBG_OPT_VERSION,
+};
/*
* Firmware Device Log Dumping
@@ -79,13 +97,26 @@ static const char * const devlog_facility_strings[] = {
};
static const char *progname;
+int set_dbg_entity(u8 *dbg_bitmap, char *dbg_entity_list);
+
+static int check_option(char *opt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(option_list); i++) {
+ if (!strcmp(opt, option_list[i]))
+ return i;
+ }
+ return -1;
+}
static void usage(FILE *fp)
{
fprintf(fp, "Usage: %s <path to t4nex#> [operation]\n", progname);
fprintf(fp,
"\tdevlog show device log\n"
- "\tloadfw <FW image> Flash the FW image\n");
+ "\tloadfw <FW image> Flash the FW image\n"
+ "\tcudbg Chelsio Unified Debugger\n");
exit(fp == stderr ? 1 : 0);
}
@@ -255,6 +286,354 @@ load_fw(int argc, char *argv[], int start_arg, const char *iff_name)
free(fw);
}
+int read_input_file(char *in_file, void **buf, int *buf_size)
+{
+ FILE *fptr = NULL;
+ size_t count;
+ int rc = 0;
+
+ fptr = fopen(in_file, "rb");
+ if (!fptr) {
+ perror("error in opening file ");
+ rc = -1;
+ goto out;
+ }
+ rc = fseek(fptr, 0, SEEK_END);
+ if (rc < 0) {
+ perror("error in seeking file ");
+ rc = -1;
+ goto out;
+ }
+ *buf_size = ftell(fptr);
+ rc = fseek(fptr, 0, SEEK_SET);
+ if (rc < 0) {
+ perror("error in seeking file ");
+ rc = -1;
+ goto out;
+ }
+ *buf = (void *) malloc(*buf_size);
+ if (*buf == NULL) {
+ rc = CUDBG_STATUS_NOSPACE;
+ goto out;
+ }
+ memset(*buf, 0, *buf_size);
+
+ count = fread(*buf, 1, *buf_size, fptr);
+ if (count != *buf_size) {
+ perror("error in reading from file ");
+ goto out;
+ }
+
+out:
+ if (fptr)
+ fclose(fptr);
+
+ return rc;
+}
+
+static void
+do_collect(char *dbg_entity_list, const char *iff_name, const char *fname)
+{
+ struct t4_cudbg_dump *cudbg;
+ int fd;
+
+ cudbg = malloc(sizeof(struct t4_cudbg_dump) + CUDBG_SIZE);
+ if (!cudbg) {
+ err(1, "%s:allocate %ld bytes failed", __func__, CUDBG_SIZE);
+ }
+
+ memset(cudbg, 0, sizeof(struct t4_cudbg_dump) + CUDBG_SIZE);
+
+ cudbg->len = CUDBG_SIZE;
+
+ set_dbg_entity(cudbg->bitmap, dbg_entity_list);
+
+ if (doit(iff_name, T4_IOCTL_GET_CUDBG, cudbg)) {
+ free(cudbg);
+ err(1, "%s: IOCTL failed", __func__);
+ }
+
+ fd = open(fname, O_CREAT | O_TRUNC | O_EXCL | O_WRONLY,
+ S_IRUSR | S_IRGRP | S_IROTH);
+ if (fd < 0) {
+ err(1, "%s: file open failed", __func__);
+ }
+
+ write(fd, cudbg->data, cudbg->len);
+ close(fd);
+ free(cudbg);
+}
+
+static void
+do_view(char *dbg_entity_list, char *in_file)
+{
+ void *handle = NULL;
+ void *buf = NULL;
+ int buf_size = 32 * 1024 * 1024;
+ int next_offset = 0;
+ int data_len;
+ int rc = 0;
+
+ handle = cudbg_alloc_handle();
+ if (!handle)
+ goto out;
+ /* rcad from file */
+ rc = read_input_file(in_file, &buf, &buf_size);
+ if (rc < 0) {
+ goto out;
+ }
+
+ set_dbg_entity(((struct cudbg_private *)handle)->dbg_init.dbg_bitmap,
+ dbg_entity_list);
+ do {
+ if (buf_size - next_offset <= 0)
+ break;
+
+ data_len = cudbg_view(handle, buf+next_offset,
+ buf_size-next_offset, NULL, 0);
+ next_offset += data_len;
+ if (data_len > 0)
+ printf("\n\t\t<========================END============="\
+ "===========>\t\t\n\n\n");
+ } while (data_len > 0);
+
+out:
+ if (buf)
+ free(buf);
+ if (handle)
+ cudbg_free_handle(handle);
+ return;
+}
+
+typedef void (*cudbg_alias_get_entities_cb)(char *dst, u32 dst_size);
+
+struct entity_access_list {
+ const char *name;
+ cudbg_alias_get_entities_cb get_entities_cb;
+};
+
+void
+cudbg_append_string(char *dst, u32 dst_size, char *src)
+{
+ strlcat(dst, src, dst_size);
+ strlcat(dst, ",", dst_size);
+}
+
+static void
+cudbg_alias_get_allregs(char *dst, u32 dst_size)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(entity_list); i++)
+ if (entity_list[i].flag & (1 << ENTITY_FLAG_REGISTER))
+ cudbg_append_string(dst, dst_size, entity_list[i].name);
+}
+
+static struct entity_access_list ATTRIBUTE_UNUSED entity_alias_list[] = {
+ {"allregs", cudbg_alias_get_allregs},
+};
+
+static int
+check_dbg_entity(char *entity)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(entity_list); i++)
+ if (!strcmp(entity, entity_list[i].name))
+ return entity_list[i].bit;
+ return -1;
+}
+
+/* Get matching alias index from entity_alias_list[] */
+static
+int get_alias(const char *entity)
+{
+ u32 i;
+
+ for (i = 0; i < ARRAY_SIZE(entity_alias_list); i++)
+ if (!strcmp(entity, entity_alias_list[i].name))
+ return i;
+ return -1;
+}
+
+static int
+parse_entity_list(const char *dbg_entity_list, char *dst,
+ u32 dst_size)
+{
+ char *tmp_dbg_entity_list;
+ char *dbg_entity;
+ int rc, i;
+
+ /* Holds single entity name de-limited by comma */
+ tmp_dbg_entity_list = malloc(CUDBG_MAX_ENTITY_STR_LEN);
+ if (!tmp_dbg_entity_list)
+ return ENOMEM;
+
+ strlcpy(tmp_dbg_entity_list, dbg_entity_list, CUDBG_MAX_ENTITY_STR_LEN);
+ dbg_entity = strtok(tmp_dbg_entity_list, ",");
+ while (dbg_entity != NULL) {
+ /* See if specified entity name exists. If it doesn't
+ * exist, see if the entity name is an alias.
+ * If it's not a valid entity name, bail with error.
+ */
+ rc = check_dbg_entity(dbg_entity);
+ if (rc < 0) {
+ i = get_alias(dbg_entity);
+ if (i < 0) {
+ /* Not an alias, and not a valid entity name */
+ printf("\nUnknown entity: %s\n", dbg_entity);
+ rc = CUDBG_STATUS_ENTITY_NOT_FOUND;
+ goto out_err;
+ } else {
+ /* If alias is found, get all the corresponding
+ * debug entities related to the alias.
+ */
+ entity_alias_list[i].get_entities_cb(dst, dst_size);
+ }
+ } else {
+ /* Not an alias, but is a valid entity name.
+ * So, append the corresponding debug entity.
+ */
+ cudbg_append_string(dst, dst_size, entity_list[rc].name);
+ }
+ dbg_entity = strtok(NULL, ",");
+ }
+
+ rc = 0;
+
+out_err:
+ free(tmp_dbg_entity_list);
+ return rc;
+}
+
+static
+int get_entity_list(const char *in_buff, char **out_buff)
+{
+ char *dbg_entity_list;
+ int rc;
+
+ /* Allocate enough to hold converted alias string.
+ * Must be freed by caller
+ */
+ dbg_entity_list = malloc(CUDBG_MAX_ENTITY_STR_LEN);
+ if (!dbg_entity_list)
+ return ENOMEM;
+
+ memset(dbg_entity_list, 0, CUDBG_MAX_ENTITY_STR_LEN);
+ rc = parse_entity_list(in_buff, dbg_entity_list,
+ CUDBG_MAX_ENTITY_STR_LEN);
+ if (rc) {
+ free(dbg_entity_list);
+ return rc;
+ }
+
+ /* Remove the last comma */
+ dbg_entity_list[strlen(dbg_entity_list) - 1] = '\0';
+ *out_buff = dbg_entity_list;
+ return 0;
+}
+
+static void
+put_entity_list(char *buf)
+{
+ if (buf)
+ free(buf);
+}
+
+int
+set_dbg_entity(u8 *dbg_bitmap, char *dbg_entity_list)
+{
+ int i, dbg_entity_bit, rc = 0;
+ char *dbg_entity;
+ char *dbg_entity_list_tmp;
+
+ dbg_entity_list_tmp = malloc(MAX_PARAM_LEN);
+ if (!dbg_entity_list_tmp) {
+ rc = CUDBG_STATUS_NOSPACE;
+ return rc;
+ }
+
+ if (dbg_entity_list != NULL) {
+ strlcpy(dbg_entity_list_tmp, dbg_entity_list, MAX_PARAM_LEN);
+ dbg_entity = strtok(dbg_entity_list_tmp, ",");
+ }
+ else
+ dbg_entity = NULL;
+
+ while (dbg_entity != NULL) {
+ rc = check_dbg_entity(dbg_entity);
+ if (rc < 0) {
+ printf("\n\tInvalid debug entity: %s\n", dbg_entity);
+ //Vishal cudbg_usage();
+ goto out_free;
+ }
+
+ dbg_entity_bit = rc;
+
+ if (dbg_entity_bit == CUDBG_ALL) {
+ for (i = 1; i < CUDBG_MAX_ENTITY; i++)
+ set_dbg_bitmap(dbg_bitmap, i);
+ set_dbg_bitmap(dbg_bitmap, CUDBG_ALL);
+ break;
+ } else {
+ set_dbg_bitmap(dbg_bitmap, dbg_entity_bit);
+ }
+
+ dbg_entity = strtok(NULL, ",");
+ }
+
+ rc = 0;
+
+out_free:
+ free(dbg_entity_list_tmp);
+ return rc;
+}
+
+
+static void
+get_cudbg(int argc, char *argv[], int start_arg, const char *iff_name)
+{
+ char *dbg_entity_list = NULL;
+ int rc = 0, option;
+ rc = check_option(argv[start_arg++]);
+ if (rc < 0) {
+ err(1, "%s:Invalid option provided", __func__);
+ }
+ option = rc;
+
+ if (option == CUDBG_OPT_VERSION) {
+ printf("Library Version %d.%d.%d\n", CUDBG_MAJOR_VERSION,
+ CUDBG_MINOR_VERSION, CUDBG_BUILD_VERSION);
+ return;
+ }
+
+ if (argc < 5) {
+ err(1, "Invalid number of arguments\n");
+ }
+ rc = get_entity_list(argv[start_arg++],
+ &dbg_entity_list);
+ if (rc) {
+ err(1, "Error in parsing entity\n");
+ }
+
+ if (argc < 6) {
+ err(1, "File name is missing\n");
+ }
+
+ switch (option) {
+ case CUDBG_OPT_COLLECT:
+ do_collect(dbg_entity_list, iff_name, argv[start_arg]);
+ break;
+ case CUDBG_OPT_VIEW:
+ do_view(dbg_entity_list, argv[start_arg]);
+ break;
+ default:
+ err(1, "Wrong option provided\n");
+ }
+
+ put_entity_list(dbg_entity_list);
+}
+
static void
run_cmd(int argc, char *argv[], const char *iff_name)
{
@@ -262,6 +641,8 @@ run_cmd(int argc, char *argv[], const char *iff_name)
get_devlog(argc, argv, 3, iff_name);
else if (strcmp(argv[2], "loadfw") == 0)
load_fw(argc, argv, 3, iff_name);
+ else if (strcmp(argv[2], "cudbg") == 0)
+ get_cudbg(argc, argv, 3, iff_name);
else
usage(stderr);
}
diff --git a/usr/src/cmd/cxgbetool/reg_defs_t5.c b/usr/src/cmd/cxgbetool/reg_defs_t5.c
new file mode 100644
index 0000000000..ef8ebc20a7
--- /dev/null
+++ b/usr/src/cmd/cxgbetool/reg_defs_t5.c
@@ -0,0 +1,64811 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright (c) 2019 by Chelsio Communications, Inc.
+ */
+
+struct reg_info t5_sge_regs[] = {
+ { "SGE_PF_KDOORBELL", 0x1e000, 0 },
+ { "QID", 15, 17 },
+ { "Priority", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1e004, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1e008, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1e00c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1e400, 0 },
+ { "QID", 15, 17 },
+ { "Priority", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1e404, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1e408, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1e40c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1e800, 0 },
+ { "QID", 15, 17 },
+ { "Priority", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1e804, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1e808, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1e80c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1ec00, 0 },
+ { "QID", 15, 17 },
+ { "Priority", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1ec04, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1ec08, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1ec0c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1f000, 0 },
+ { "QID", 15, 17 },
+ { "Priority", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1f004, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1f008, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1f00c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1f400, 0 },
+ { "QID", 15, 17 },
+ { "Priority", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1f404, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1f408, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1f40c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1f800, 0 },
+ { "QID", 15, 17 },
+ { "Priority", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1f804, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1f808, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1f80c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1fc00, 0 },
+ { "QID", 15, 17 },
+ { "Priority", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1fc04, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1fc08, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1fc0c, 0 },
+ { "SGE_CONTROL", 0x1008, 0 },
+ { "IgrAllCPLtoFL", 31, 1 },
+ { "FLSplitMin", 22, 9 },
+ { "RxPktCPLMode", 18, 1 },
+ { "EgrStatusPageSize", 17, 1 },
+ { "IngHintEnable1", 15, 1 },
+ { "IngHintEnable0", 14, 1 },
+ { "IngIntCompareIDX", 13, 1 },
+ { "PktShift", 10, 3 },
+ { "IngPCIeBoundary", 7, 3 },
+ { "IngPadBoundary", 4, 3 },
+ { "GlobalEnable", 0, 1 },
+ { "SGE_HOST_PAGE_SIZE", 0x100c, 0 },
+ { "HostPageSizePF7", 28, 4 },
+ { "HostPageSizePF6", 24, 4 },
+ { "HostPageSizePF5", 20, 4 },
+ { "HostPageSizePF4", 16, 4 },
+ { "HostPageSizePF3", 12, 4 },
+ { "HostPageSizePF2", 8, 4 },
+ { "HostPageSizePF1", 4, 4 },
+ { "HostPageSizePF0", 0, 4 },
+ { "SGE_EGRESS_QUEUES_PER_PAGE_PF", 0x1010, 0 },
+ { "QueuesPerPagePF7", 28, 4 },
+ { "QueuesPerPagePF6", 24, 4 },
+ { "QueuesPerPagePF5", 20, 4 },
+ { "QueuesPerPagePF4", 16, 4 },
+ { "QueuesPerPagePF3", 12, 4 },
+ { "QueuesPerPagePF2", 8, 4 },
+ { "QueuesPerPagePF1", 4, 4 },
+ { "QueuesPerPagePF0", 0, 4 },
+ { "SGE_EGRESS_QUEUES_PER_PAGE_VF", 0x1014, 0 },
+ { "QueuesPerPageVFPF7", 28, 4 },
+ { "QueuesPerPageVFPF6", 24, 4 },
+ { "QueuesPerPageVFPF5", 20, 4 },
+ { "QueuesPerPageVFPF4", 16, 4 },
+ { "QueuesPerPageVFPF3", 12, 4 },
+ { "QueuesPerPageVFPF2", 8, 4 },
+ { "QueuesPerPageVFPF1", 4, 4 },
+ { "QueuesPerPageVFPF0", 0, 4 },
+ { "SGE_USER_MODE_LIMITS", 0x1018, 0 },
+ { "Opcode_Min", 24, 8 },
+ { "Opcode_Max", 16, 8 },
+ { "Length_Min", 8, 8 },
+ { "Length_Max", 0, 8 },
+ { "SGE_WR_ERROR", 0x101c, 0 },
+ { "SGE_PERR_INJECT", 0x1020, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "SGE_INT_CAUSE1", 0x1024, 0 },
+ { "perr_pc_chpi_rsp2", 31, 1 },
+ { "perr_flm_CreditFifo", 30, 1 },
+ { "perr_imsg_hint_fifo", 29, 1 },
+ { "perr_pc_mctag", 24, 1 },
+ { "perr_pc_chpi_rsp1", 23, 1 },
+ { "perr_pc_chpi_rsp0", 22, 1 },
+ { "perr_dbp_pc_rsp_fifo3", 21, 1 },
+ { "perr_dbp_pc_rsp_fifo2", 20, 1 },
+ { "perr_dbp_pc_rsp_fifo1", 19, 1 },
+ { "perr_dbp_pc_rsp_fifo0", 18, 1 },
+ { "perr_dmarbt", 17, 1 },
+ { "perr_flm_DbpFifo", 16, 1 },
+ { "perr_flm_MCReq_fifo", 15, 1 },
+ { "perr_flm_HintFifo", 14, 1 },
+ { "perr_align_ctl_fifo3", 13, 1 },
+ { "perr_align_ctl_fifo2", 12, 1 },
+ { "perr_align_ctl_fifo1", 11, 1 },
+ { "perr_align_ctl_fifo0", 10, 1 },
+ { "perr_edma_fifo3", 9, 1 },
+ { "perr_edma_fifo2", 8, 1 },
+ { "perr_edma_fifo1", 7, 1 },
+ { "perr_edma_fifo0", 6, 1 },
+ { "perr_pd_fifo3", 5, 1 },
+ { "perr_pd_fifo2", 4, 1 },
+ { "perr_pd_fifo1", 3, 1 },
+ { "perr_pd_fifo0", 2, 1 },
+ { "perr_ing_ctxt_mifrsp", 1, 1 },
+ { "perr_egr_ctxt_mifrsp", 0, 1 },
+ { "SGE_INT_ENABLE1", 0x1028, 0 },
+ { "perr_pc_chpi_rsp2", 31, 1 },
+ { "perr_flm_CreditFifo", 30, 1 },
+ { "perr_imsg_hint_fifo", 29, 1 },
+ { "perr_pc_mctag", 24, 1 },
+ { "perr_pc_chpi_rsp1", 23, 1 },
+ { "perr_pc_chpi_rsp0", 22, 1 },
+ { "perr_dbp_pc_rsp_fifo3", 21, 1 },
+ { "perr_dbp_pc_rsp_fifo2", 20, 1 },
+ { "perr_dbp_pc_rsp_fifo1", 19, 1 },
+ { "perr_dbp_pc_rsp_fifo0", 18, 1 },
+ { "perr_dmarbt", 17, 1 },
+ { "perr_flm_DbpFifo", 16, 1 },
+ { "perr_flm_MCReq_fifo", 15, 1 },
+ { "perr_flm_HintFifo", 14, 1 },
+ { "perr_align_ctl_fifo3", 13, 1 },
+ { "perr_align_ctl_fifo2", 12, 1 },
+ { "perr_align_ctl_fifo1", 11, 1 },
+ { "perr_align_ctl_fifo0", 10, 1 },
+ { "perr_edma_fifo3", 9, 1 },
+ { "perr_edma_fifo2", 8, 1 },
+ { "perr_edma_fifo1", 7, 1 },
+ { "perr_edma_fifo0", 6, 1 },
+ { "perr_pd_fifo3", 5, 1 },
+ { "perr_pd_fifo2", 4, 1 },
+ { "perr_pd_fifo1", 3, 1 },
+ { "perr_pd_fifo0", 2, 1 },
+ { "perr_ing_ctxt_mifrsp", 1, 1 },
+ { "perr_egr_ctxt_mifrsp", 0, 1 },
+ { "SGE_PERR_ENABLE1", 0x102c, 0 },
+ { "perr_pc_chpi_rsp2", 31, 1 },
+ { "perr_flm_CreditFifo", 30, 1 },
+ { "perr_imsg_hint_fifo", 29, 1 },
+ { "perr_pc_mctag", 24, 1 },
+ { "perr_pc_chpi_rsp1", 23, 1 },
+ { "perr_pc_chpi_rsp0", 22, 1 },
+ { "perr_dbp_pc_rsp_fifo3", 21, 1 },
+ { "perr_dbp_pc_rsp_fifo2", 20, 1 },
+ { "perr_dbp_pc_rsp_fifo1", 19, 1 },
+ { "perr_dbp_pc_rsp_fifo0", 18, 1 },
+ { "perr_dmarbt", 17, 1 },
+ { "perr_flm_DbpFifo", 16, 1 },
+ { "perr_flm_MCReq_fifo", 15, 1 },
+ { "perr_flm_HintFifo", 14, 1 },
+ { "perr_align_ctl_fifo3", 13, 1 },
+ { "perr_align_ctl_fifo2", 12, 1 },
+ { "perr_align_ctl_fifo1", 11, 1 },
+ { "perr_align_ctl_fifo0", 10, 1 },
+ { "perr_edma_fifo3", 9, 1 },
+ { "perr_edma_fifo2", 8, 1 },
+ { "perr_edma_fifo1", 7, 1 },
+ { "perr_edma_fifo0", 6, 1 },
+ { "perr_pd_fifo3", 5, 1 },
+ { "perr_pd_fifo2", 4, 1 },
+ { "perr_pd_fifo1", 3, 1 },
+ { "perr_pd_fifo0", 2, 1 },
+ { "perr_ing_ctxt_mifrsp", 1, 1 },
+ { "perr_egr_ctxt_mifrsp", 0, 1 },
+ { "SGE_INT_CAUSE2", 0x1030, 0 },
+ { "perr_dbp_hint_fl_fifo", 24, 1 },
+ { "perr_egr_dbp_tx_coal", 23, 1 },
+ { "perr_dbp_fl_fifo", 22, 1 },
+ { "perr_eswitch_fifo3", 21, 1 },
+ { "perr_eswitch_fifo2", 20, 1 },
+ { "perr_eswitch_fifo1", 19, 1 },
+ { "perr_eswitch_fifo0", 18, 1 },
+ { "perr_pc_dbp1", 17, 1 },
+ { "perr_pc_dbp0", 16, 1 },
+ { "perr_pc_dbp2", 15, 1 },
+ { "perr_conm_sram", 14, 1 },
+ { "perr_pc_mc_rsp", 13, 1 },
+ { "perr_isw_idma0_fifo", 12, 1 },
+ { "perr_isw_idma1_fifo", 11, 1 },
+ { "perr_isw_dbp_fifo", 10, 1 },
+ { "perr_isw_gts_fifo", 9, 1 },
+ { "perr_itp_evr", 8, 1 },
+ { "perr_flm_cntxmem", 7, 1 },
+ { "perr_flm_l1Cache", 6, 1 },
+ { "perr_dbp_hint_fifo", 5, 1 },
+ { "perr_dbp_hp_fifo", 4, 1 },
+ { "perr_dbp_lp_fifo", 3, 1 },
+ { "perr_ing_ctxt_cache", 2, 1 },
+ { "perr_egr_ctxt_cache", 1, 1 },
+ { "perr_base_size", 0, 1 },
+ { "SGE_INT_ENABLE2", 0x1034, 0 },
+ { "perr_dbp_hint_fl_fifo", 24, 1 },
+ { "perr_egr_dbp_tx_coal", 23, 1 },
+ { "perr_dbp_fl_fifo", 22, 1 },
+ { "perr_eswitch_fifo3", 21, 1 },
+ { "perr_eswitch_fifo2", 20, 1 },
+ { "perr_eswitch_fifo1", 19, 1 },
+ { "perr_eswitch_fifo0", 18, 1 },
+ { "perr_pc_dbp1", 17, 1 },
+ { "perr_pc_dbp0", 16, 1 },
+ { "perr_pc_dbp2", 15, 1 },
+ { "perr_conm_sram", 14, 1 },
+ { "perr_pc_mc_rsp", 13, 1 },
+ { "perr_isw_idma0_fifo", 12, 1 },
+ { "perr_isw_idma1_fifo", 11, 1 },
+ { "perr_isw_dbp_fifo", 10, 1 },
+ { "perr_isw_gts_fifo", 9, 1 },
+ { "perr_itp_evr", 8, 1 },
+ { "perr_flm_cntxmem", 7, 1 },
+ { "perr_flm_l1Cache", 6, 1 },
+ { "perr_dbp_hint_fifo", 5, 1 },
+ { "perr_dbp_hp_fifo", 4, 1 },
+ { "perr_dbp_lp_fifo", 3, 1 },
+ { "perr_ing_ctxt_cache", 2, 1 },
+ { "perr_egr_ctxt_cache", 1, 1 },
+ { "perr_base_size", 0, 1 },
+ { "SGE_PERR_ENABLE2", 0x1038, 0 },
+ { "perr_dbp_hint_fl_fifo", 24, 1 },
+ { "perr_egr_dbp_tx_coal", 23, 1 },
+ { "perr_dbp_fl_fifo", 22, 1 },
+ { "perr_eswitch_fifo3", 21, 1 },
+ { "perr_eswitch_fifo2", 20, 1 },
+ { "perr_eswitch_fifo1", 19, 1 },
+ { "perr_eswitch_fifo0", 18, 1 },
+ { "perr_pc_dbp1", 17, 1 },
+ { "perr_pc_dbp0", 16, 1 },
+ { "perr_pc_dbp2", 15, 1 },
+ { "perr_conm_sram", 14, 1 },
+ { "perr_pc_mc_rsp", 13, 1 },
+ { "perr_isw_idma0_fifo", 12, 1 },
+ { "perr_isw_idma1_fifo", 11, 1 },
+ { "perr_isw_dbp_fifo", 10, 1 },
+ { "perr_isw_gts_fifo", 9, 1 },
+ { "perr_itp_evr", 8, 1 },
+ { "perr_flm_cntxmem", 7, 1 },
+ { "perr_flm_l1Cache", 6, 1 },
+ { "perr_dbp_hint_fifo", 5, 1 },
+ { "perr_dbp_hp_fifo", 4, 1 },
+ { "perr_dbp_lp_fifo", 3, 1 },
+ { "perr_ing_ctxt_cache", 2, 1 },
+ { "perr_egr_ctxt_cache", 1, 1 },
+ { "perr_base_size", 0, 1 },
+ { "SGE_INT_CAUSE3", 0x103c, 0 },
+ { "err_flm_dbp", 31, 1 },
+ { "err_flm_idma1", 30, 1 },
+ { "err_flm_idma0", 29, 1 },
+ { "err_flm_hint", 28, 1 },
+ { "err_pcie_error3", 27, 1 },
+ { "err_pcie_error2", 26, 1 },
+ { "err_pcie_error1", 25, 1 },
+ { "err_pcie_error0", 24, 1 },
+ { "err_timer_above_max_qid", 23, 1 },
+ { "err_cpl_exceed_iqe_size", 22, 1 },
+ { "err_invalid_cidx_inc", 21, 1 },
+ { "err_itp_time_paused", 20, 1 },
+ { "err_cpl_opcode_0", 19, 1 },
+ { "err_dropped_db", 18, 1 },
+ { "err_data_cpl_on_high_qid1", 17, 1 },
+ { "err_data_cpl_on_high_qid0", 16, 1 },
+ { "err_bad_db_pidx3", 15, 1 },
+ { "err_bad_db_pidx2", 14, 1 },
+ { "err_bad_db_pidx1", 13, 1 },
+ { "err_bad_db_pidx0", 12, 1 },
+ { "err_ing_pcie_chan", 11, 1 },
+ { "err_ing_ctxt_prio", 10, 1 },
+ { "err_egr_ctxt_prio", 9, 1 },
+ { "dbfifo_hp_int", 8, 1 },
+ { "dbfifo_lp_int", 7, 1 },
+ { "reg_address_err", 6, 1 },
+ { "ingress_size_err", 5, 1 },
+ { "egress_size_err", 4, 1 },
+ { "err_inv_ctxt3", 3, 1 },
+ { "err_inv_ctxt2", 2, 1 },
+ { "err_inv_ctxt1", 1, 1 },
+ { "err_inv_ctxt0", 0, 1 },
+ { "SGE_INT_ENABLE3", 0x1040, 0 },
+ { "err_flm_dbp", 31, 1 },
+ { "err_flm_idma1", 30, 1 },
+ { "err_flm_idma0", 29, 1 },
+ { "err_flm_hint", 28, 1 },
+ { "err_pcie_error3", 27, 1 },
+ { "err_pcie_error2", 26, 1 },
+ { "err_pcie_error1", 25, 1 },
+ { "err_pcie_error0", 24, 1 },
+ { "err_timer_above_max_qid", 23, 1 },
+ { "err_cpl_exceed_iqe_size", 22, 1 },
+ { "err_invalid_cidx_inc", 21, 1 },
+ { "err_itp_time_paused", 20, 1 },
+ { "err_cpl_opcode_0", 19, 1 },
+ { "err_dropped_db", 18, 1 },
+ { "err_data_cpl_on_high_qid1", 17, 1 },
+ { "err_data_cpl_on_high_qid0", 16, 1 },
+ { "err_bad_db_pidx3", 15, 1 },
+ { "err_bad_db_pidx2", 14, 1 },
+ { "err_bad_db_pidx1", 13, 1 },
+ { "err_bad_db_pidx0", 12, 1 },
+ { "err_ing_pcie_chan", 11, 1 },
+ { "err_ing_ctxt_prio", 10, 1 },
+ { "err_egr_ctxt_prio", 9, 1 },
+ { "dbfifo_hp_int", 8, 1 },
+ { "dbfifo_lp_int", 7, 1 },
+ { "reg_address_err", 6, 1 },
+ { "ingress_size_err", 5, 1 },
+ { "egress_size_err", 4, 1 },
+ { "err_inv_ctxt3", 3, 1 },
+ { "err_inv_ctxt2", 2, 1 },
+ { "err_inv_ctxt1", 1, 1 },
+ { "err_inv_ctxt0", 0, 1 },
+ { "SGE_FL_BUFFER_SIZE0", 0x1044, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE1", 0x1048, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE2", 0x104c, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE3", 0x1050, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE4", 0x1054, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE5", 0x1058, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE6", 0x105c, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE7", 0x1060, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE8", 0x1064, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE9", 0x1068, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE10", 0x106c, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE11", 0x1070, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE12", 0x1074, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE13", 0x1078, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE14", 0x107c, 0 },
+ { "Size", 4, 28 },
+ { "SGE_FL_BUFFER_SIZE15", 0x1080, 0 },
+ { "Size", 4, 28 },
+ { "SGE_DBQ_CTXT_BADDR", 0x1084, 0 },
+ { "BaseAddr", 3, 29 },
+ { "SGE_IMSG_CTXT_BADDR", 0x1088, 0 },
+ { "BaseAddr", 3, 29 },
+ { "SGE_FLM_CACHE_BADDR", 0x108c, 0 },
+ { "BaseAddr", 3, 29 },
+ { "SGE_FLM_CFG", 0x1090, 0 },
+ { "OpMode", 26, 6 },
+ { "NoHdr", 18, 1 },
+ { "CachePtrCnt", 16, 2 },
+ { "EDRAMPtrCnt", 14, 2 },
+ { "HdrStartFLQ", 11, 3 },
+ { "FetchThresh", 6, 5 },
+ { "CreditCnt", 4, 2 },
+ { "CreditCntPacking", 2, 2 },
+ { "NoEDRAM", 0, 1 },
+ { "SGE_CONM_CTRL", 0x1094, 0 },
+ { "EgrThresholdPacking", 14, 6 },
+ { "EgrThreshold", 8, 6 },
+ { "IngThreshold", 2, 6 },
+ { "SGE_TIMESTAMP_LO", 0x1098, 0 },
+ { "SGE_TIMESTAMP_HI", 0x109c, 0 },
+ { "Opcode", 28, 2 },
+ { "Value", 0, 28 },
+ { "SGE_INGRESS_RX_THRESHOLD", 0x10a0, 0 },
+ { "Threshold_0", 24, 6 },
+ { "Threshold_1", 16, 6 },
+ { "Threshold_2", 8, 6 },
+ { "Threshold_3", 0, 6 },
+ { "SGE_DBFIFO_STATUS", 0x10a4, 0 },
+ { "Bar2Valid", 31, 1 },
+ { "Bar2Full", 30, 1 },
+ { "LP_Int_Thresh", 18, 12 },
+ { "LP_Count", 0, 18 },
+ { "SGE_DOORBELL_CONTROL", 0x10a8, 0 },
+ { "HintDepthCtl", 27, 5 },
+ { "NoCoalesce", 26, 1 },
+ { "HP_Weight", 24, 2 },
+ { "HP_Disable", 23, 1 },
+ { "ForceUserDBtoLP", 22, 1 },
+ { "ForceVFPF0DBtoLP", 21, 1 },
+ { "ForceVFPF1DBtoLP", 20, 1 },
+ { "ForceVFPF2DBtoLP", 19, 1 },
+ { "ForceVFPF3DBtoLP", 18, 1 },
+ { "ForceVFPF4DBtoLP", 17, 1 },
+ { "ForceVFPF5DBtoLP", 16, 1 },
+ { "ForceVFPF6DBtoLP", 15, 1 },
+ { "ForceVFPF7DBtoLP", 14, 1 },
+ { "Enable_Drop", 13, 1 },
+ { "Drop_Timeout", 1, 12 },
+ { "Dropped_DB", 0, 1 },
+ { "SGE_DROPPED_DOORBELL", 0x10ac, 0 },
+ { "SGE_DOORBELL_THROTTLE_CONTROL", 0x10b0, 0 },
+ { "Bar2ThrottleCount", 16, 8 },
+ { "ClrCoalesceDisable", 15, 1 },
+ { "OpenBar2GateOnce", 14, 1 },
+ { "ForceOpenBar2Gate", 13, 1 },
+ { "Throttle_Count", 1, 12 },
+ { "Throttle_Enable", 0, 1 },
+ { "SGE_ITP_CONTROL", 0x10b4, 0 },
+ { "Critical_Time", 10, 15 },
+ { "LL_Empty", 4, 6 },
+ { "LL_Read_Wait_Disable", 0, 1 },
+ { "SGE_TIMER_VALUE_0_AND_1", 0x10b8, 0 },
+ { "TimerValue0", 16, 16 },
+ { "TimerValue1", 0, 16 },
+ { "SGE_TIMER_VALUE_2_AND_3", 0x10bc, 0 },
+ { "TimerValue2", 16, 16 },
+ { "TimerValue3", 0, 16 },
+ { "SGE_TIMER_VALUE_4_AND_5", 0x10c0, 0 },
+ { "TimerValue4", 16, 16 },
+ { "TimerValue5", 0, 16 },
+ { "SGE_DEBUG_INDEX", 0x10cc, 0 },
+ { "SGE_DEBUG_DATA_HIGH", 0x10d0, 0 },
+ { "SGE_DEBUG_DATA_LOW", 0x10d4, 0 },
+ { "SGE_REVISION", 0x10d8, 0 },
+ { "SGE_INT_CAUSE4", 0x10dc, 0 },
+ { "bar2_egress_len_or_addr_err", 29, 1 },
+ { "err_cpl_exceed_max_iqe_size1", 28, 1 },
+ { "err_cpl_exceed_max_iqe_size0", 27, 1 },
+ { "err_wr_len_too_large3", 26, 1 },
+ { "err_wr_len_too_large2", 25, 1 },
+ { "err_wr_len_too_large1", 24, 1 },
+ { "err_wr_len_too_large0", 23, 1 },
+ { "err_large_minfetch_with_txcoal3", 22, 1 },
+ { "err_large_minfetch_with_txcoal2", 21, 1 },
+ { "err_large_minfetch_with_txcoal1", 20, 1 },
+ { "err_large_minfetch_with_txcoal0", 19, 1 },
+ { "coal_with_hp_disable_err", 18, 1 },
+ { "bar2_egress_coal0_err", 17, 1 },
+ { "bar2_egress_size_err", 16, 1 },
+ { "flm_pc_rsp_err", 15, 1 },
+ { "dbfifo_hp_int_low", 14, 1 },
+ { "dbfifo_lp_int_low", 13, 1 },
+ { "dbfifo_fl_int_low", 12, 1 },
+ { "dbfifo_fl_int", 11, 1 },
+ { "err_rx_cpl_packet_size1", 10, 1 },
+ { "err_rx_cpl_packet_size0", 9, 1 },
+ { "err_bad_upfl_inc_credit3", 8, 1 },
+ { "err_bad_upfl_inc_credit2", 7, 1 },
+ { "err_bad_upfl_inc_credit1", 6, 1 },
+ { "err_bad_upfl_inc_credit0", 5, 1 },
+ { "err_physaddr_len0_idma1", 4, 1 },
+ { "err_physaddr_len0_idma0", 3, 1 },
+ { "err_flm_invalid_pkt_drop1", 2, 1 },
+ { "err_flm_invalid_pkt_drop0", 1, 1 },
+ { "err_unexpected_timer", 0, 1 },
+ { "SGE_INT_ENABLE4", 0x10e0, 0 },
+ { "bar2_egress_len_or_addr_err", 29, 1 },
+ { "err_cpl_exceed_max_iqe_size1", 28, 1 },
+ { "err_cpl_exceed_max_iqe_size0", 27, 1 },
+ { "err_wr_len_too_large3", 26, 1 },
+ { "err_wr_len_too_large2", 25, 1 },
+ { "err_wr_len_too_large1", 24, 1 },
+ { "err_wr_len_too_large0", 23, 1 },
+ { "err_large_minfetch_with_txcoal3", 22, 1 },
+ { "err_large_minfetch_with_txcoal2", 21, 1 },
+ { "err_large_minfetch_with_txcoal1", 20, 1 },
+ { "err_large_minfetch_with_txcoal0", 19, 1 },
+ { "coal_with_hp_disable_err", 18, 1 },
+ { "bar2_egress_coal0_err", 17, 1 },
+ { "bar2_egress_size_err", 16, 1 },
+ { "flm_pc_rsp_err", 15, 1 },
+ { "dbfifo_hp_int_low", 14, 1 },
+ { "dbfifo_lp_int_low", 13, 1 },
+ { "dbfifo_fl_int_low", 12, 1 },
+ { "dbfifo_fl_int", 11, 1 },
+ { "err_rx_cpl_packet_size1", 10, 1 },
+ { "err_rx_cpl_packet_size0", 9, 1 },
+ { "err_bad_upfl_inc_credit3", 8, 1 },
+ { "err_bad_upfl_inc_credit2", 7, 1 },
+ { "err_bad_upfl_inc_credit1", 6, 1 },
+ { "err_bad_upfl_inc_credit0", 5, 1 },
+ { "err_physaddr_len0_idma1", 4, 1 },
+ { "err_physaddr_len0_idma0", 3, 1 },
+ { "err_flm_invalid_pkt_drop1", 2, 1 },
+ { "err_flm_invalid_pkt_drop0", 1, 1 },
+ { "err_unexpected_timer", 0, 1 },
+ { "SGE_STAT_TOTAL", 0x10e4, 0 },
+ { "SGE_STAT_MATCH", 0x10e8, 0 },
+ { "SGE_STAT_CFG", 0x10ec, 0 },
+ { "StatSource", 9, 4 },
+ { "ITPOpMode", 8, 1 },
+ { "EgrCtxtOpMode", 6, 2 },
+ { "IngCtxtOpMode", 4, 2 },
+ { "StatMode", 2, 2 },
+ { "SGE_HINT_CFG", 0x10f0, 0 },
+ { "uPCutoffThreshLp", 12, 11 },
+ { "HintsAllowedNoHdr", 6, 6 },
+ { "HintsAllowedHdr", 0, 6 },
+ { "SGE_INGRESS_QUEUES_PER_PAGE_PF", 0x10f4, 0 },
+ { "QueuesPerPagePF7", 28, 4 },
+ { "QueuesPerPagePF6", 24, 4 },
+ { "QueuesPerPagePF5", 20, 4 },
+ { "QueuesPerPagePF4", 16, 4 },
+ { "QueuesPerPagePF3", 12, 4 },
+ { "QueuesPerPagePF2", 8, 4 },
+ { "QueuesPerPagePF1", 4, 4 },
+ { "QueuesPerPagePF0", 0, 4 },
+ { "SGE_INGRESS_QUEUES_PER_PAGE_VF", 0x10f8, 0 },
+ { "QueuesPerPageVFPF7", 28, 4 },
+ { "QueuesPerPageVFPF6", 24, 4 },
+ { "QueuesPerPageVFPF5", 20, 4 },
+ { "QueuesPerPageVFPF4", 16, 4 },
+ { "QueuesPerPageVFPF3", 12, 4 },
+ { "QueuesPerPageVFPF2", 8, 4 },
+ { "QueuesPerPageVFPF1", 4, 4 },
+ { "QueuesPerPageVFPF0", 0, 4 },
+ { "SGE_ERROR_STATS", 0x1100, 0 },
+ { "Cause_Register", 24, 3 },
+ { "Cause_Bit", 19, 5 },
+ { "Uncaptured_Error", 18, 1 },
+ { "Error_QID_Valid", 17, 1 },
+ { "Error_QID", 0, 17 },
+ { "SGE_INT_CAUSE5", 0x110c, 0 },
+ { "err_T_RxCRC", 31, 1 },
+ { "perr_MC_RspData", 30, 1 },
+ { "perr_PC_RspData", 29, 1 },
+ { "perr_PD_RdRspData", 28, 1 },
+ { "perr_U_RxData", 27, 1 },
+ { "perr_UD_RxData", 26, 1 },
+ { "perr_uP_Data", 25, 1 },
+ { "perr_CIM2SGE_RxData", 24, 1 },
+ { "perr_hint_delay_fifo1", 23, 1 },
+ { "perr_hint_delay_fifo0", 22, 1 },
+ { "perr_imsg_pd_fifo", 21, 1 },
+ { "perr_ulptx_fifo1", 20, 1 },
+ { "perr_ulptx_fifo0", 19, 1 },
+ { "perr_idma2imsg_fifo1", 18, 1 },
+ { "perr_idma2imsg_fifo0", 17, 1 },
+ { "perr_pointer_data_fifo0", 16, 1 },
+ { "perr_pointer_data_fifo1", 15, 1 },
+ { "perr_pointer_hdr_fifo0", 14, 1 },
+ { "perr_pointer_hdr_fifo1", 13, 1 },
+ { "perr_payload_fifo0", 12, 1 },
+ { "perr_payload_fifo1", 11, 1 },
+ { "perr_edma_input_fifo3", 10, 1 },
+ { "perr_edma_input_fifo2", 9, 1 },
+ { "perr_edma_input_fifo1", 8, 1 },
+ { "perr_edma_input_fifo0", 7, 1 },
+ { "perr_mgt_bar2_fifo", 6, 1 },
+ { "perr_headersplit_fifo1", 5, 1 },
+ { "perr_headersplit_fifo0", 4, 1 },
+ { "perr_cim_fifo1", 3, 1 },
+ { "perr_cim_fifo0", 2, 1 },
+ { "perr_idma_switch_output_fifo1", 1, 1 },
+ { "perr_idma_switch_output_fifo0", 0, 1 },
+ { "SGE_INT_ENABLE5", 0x1110, 0 },
+ { "err_T_RxCRC", 31, 1 },
+ { "perr_MC_RspData", 30, 1 },
+ { "perr_PC_RspData", 29, 1 },
+ { "perr_PD_RdRspData", 28, 1 },
+ { "perr_U_RxData", 27, 1 },
+ { "perr_UD_RxData", 26, 1 },
+ { "perr_uP_Data", 25, 1 },
+ { "perr_CIM2SGE_RxData", 24, 1 },
+ { "perr_hint_delay_fifo1", 23, 1 },
+ { "perr_hint_delay_fifo0", 22, 1 },
+ { "perr_imsg_pd_fifo", 21, 1 },
+ { "perr_ulptx_fifo1", 20, 1 },
+ { "perr_ulptx_fifo0", 19, 1 },
+ { "perr_idma2imsg_fifo1", 18, 1 },
+ { "perr_idma2imsg_fifo0", 17, 1 },
+ { "perr_pointer_data_fifo0", 16, 1 },
+ { "perr_pointer_data_fifo1", 15, 1 },
+ { "perr_pointer_hdr_fifo0", 14, 1 },
+ { "perr_pointer_hdr_fifo1", 13, 1 },
+ { "perr_payload_fifo0", 12, 1 },
+ { "perr_payload_fifo1", 11, 1 },
+ { "perr_edma_input_fifo3", 10, 1 },
+ { "perr_edma_input_fifo2", 9, 1 },
+ { "perr_edma_input_fifo1", 8, 1 },
+ { "perr_edma_input_fifo0", 7, 1 },
+ { "perr_mgt_bar2_fifo", 6, 1 },
+ { "perr_headersplit_fifo1", 5, 1 },
+ { "perr_headersplit_fifo0", 4, 1 },
+ { "perr_cim_fifo1", 3, 1 },
+ { "perr_cim_fifo0", 2, 1 },
+ { "perr_idma_switch_output_fifo1", 1, 1 },
+ { "perr_idma_switch_output_fifo0", 0, 1 },
+ { "SGE_PERR_ENABLE5", 0x1114, 0 },
+ { "err_T_RxCRC", 31, 1 },
+ { "perr_MC_RspData", 30, 1 },
+ { "perr_PC_RspData", 29, 1 },
+ { "perr_PD_RdRspData", 28, 1 },
+ { "perr_U_RxData", 27, 1 },
+ { "perr_UD_RxData", 26, 1 },
+ { "perr_uP_Data", 25, 1 },
+ { "perr_CIM2SGE_RxData", 24, 1 },
+ { "perr_hint_delay_fifo1", 23, 1 },
+ { "perr_hint_delay_fifo0", 22, 1 },
+ { "perr_imsg_pd_fifo", 21, 1 },
+ { "perr_ulptx_fifo1", 20, 1 },
+ { "perr_ulptx_fifo0", 19, 1 },
+ { "perr_idma2imsg_fifo1", 18, 1 },
+ { "perr_idma2imsg_fifo0", 17, 1 },
+ { "perr_pointer_data_fifo0", 16, 1 },
+ { "perr_pointer_data_fifo1", 15, 1 },
+ { "perr_pointer_hdr_fifo0", 14, 1 },
+ { "perr_pointer_hdr_fifo1", 13, 1 },
+ { "perr_payload_fifo0", 12, 1 },
+ { "perr_payload_fifo1", 11, 1 },
+ { "perr_edma_input_fifo3", 10, 1 },
+ { "perr_edma_input_fifo2", 9, 1 },
+ { "perr_edma_input_fifo1", 8, 1 },
+ { "perr_edma_input_fifo0", 7, 1 },
+ { "perr_mgt_bar2_fifo", 6, 1 },
+ { "perr_headersplit_fifo1", 5, 1 },
+ { "perr_headersplit_fifo0", 4, 1 },
+ { "perr_cim_fifo1", 3, 1 },
+ { "perr_cim_fifo0", 2, 1 },
+ { "perr_idma_switch_output_fifo1", 1, 1 },
+ { "perr_idma_switch_output_fifo0", 0, 1 },
+ { "SGE_DBFIFO_STATUS2", 0x1118, 0 },
+ { "FL_Int_Thresh", 24, 4 },
+ { "FL_Count", 14, 10 },
+ { "HP_Int_Thresh", 10, 4 },
+ { "HP_Count", 0, 10 },
+ { "SGE_FETCH_BURST_MAX_0_AND_1", 0x111c, 0 },
+ { "FetchBurstMax0", 16, 10 },
+ { "FetchBurstMax1", 0, 10 },
+ { "SGE_FETCH_BURST_MAX_2_AND_3", 0x1120, 0 },
+ { "FetchBurstMax2", 16, 10 },
+ { "FetchBurstMax3", 0, 10 },
+ { "SGE_CONTROL2", 0x1124, 0 },
+ { "uPFLCutoffDis", 21, 1 },
+ { "RxCplSizeAutocorrect", 20, 1 },
+ { "IdmaArbRoundRobin", 19, 1 },
+ { "IngPackBoundary", 16, 3 },
+ { "CGEN_Egress_Context", 15, 1 },
+ { "CGEN_Ingress_Context", 14, 1 },
+ { "CGEN_IDMA", 13, 1 },
+ { "CGEN_DBP", 12, 1 },
+ { "CGEN_EDMA", 11, 1 },
+ { "VFIFO_Enable", 10, 1 },
+ { "FLM_Reschedule_Mode", 9, 1 },
+ { "HintDepthCtlFL", 4, 5 },
+ { "Force_Ordering", 3, 1 },
+ { "TX_Coalesce_Size", 2, 1 },
+ { "Coal_Strict_CIM_Pri", 1, 1 },
+ { "TX_Coalesce_Pri", 0, 1 },
+ { "SGE_DEEP_SLEEP", 0x1128, 0 },
+ { "IDMA1_Sleep_Status", 11, 1 },
+ { "IDMA0_Sleep_Status", 10, 1 },
+ { "IDMA1_Sleep_Req", 9, 1 },
+ { "IDMA0_Sleep_Req", 8, 1 },
+ { "EDMA3_Sleep_Status", 7, 1 },
+ { "EDMA2_Sleep_Status", 6, 1 },
+ { "EDMA1_Sleep_Status", 5, 1 },
+ { "EDMA0_Sleep_Status", 4, 1 },
+ { "EDMA3_Sleep_Req", 3, 1 },
+ { "EDMA2_Sleep_Req", 2, 1 },
+ { "EDMA1_Sleep_Req", 1, 1 },
+ { "EDMA0_Sleep_Req", 0, 1 },
+ { "SGE_DOORBELL_THROTTLE_THRESHOLD", 0x112c, 0 },
+ { "Throttle_Threshold_fl", 16, 4 },
+ { "Throttle_Threshold_hp", 12, 4 },
+ { "Throttle_Threshold_lp", 0, 12 },
+ { "SGE_DBP_FETCH_THRESHOLD", 0x1130, 0 },
+ { "dbp_fetch_threshold_fl", 21, 4 },
+ { "dbp_fetch_threshold_hp", 17, 4 },
+ { "dbp_fetch_threshold_lp", 5, 12 },
+ { "dbp_fetch_threshold_mode", 4, 1 },
+ { "dbp_fetch_threshold_en3", 3, 1 },
+ { "dbp_fetch_threshold_en2", 2, 1 },
+ { "dbp_fetch_threshold_en1", 1, 1 },
+ { "dbp_fetch_threshold_en0", 0, 1 },
+ { "SGE_DBP_FETCH_THRESHOLD_QUEUE", 0x1134, 0 },
+ { "dbp_fetch_threshold_iq1", 16, 16 },
+ { "dbp_fetch_threshold_iq0", 0, 16 },
+ { "SGE_DBVFIFO_BADDR", 0x1138, 0 },
+ { "BaseAddr", 3, 29 },
+ { "SGE_DBVFIFO_SIZE", 0x113c, 0 },
+ { "Size", 6, 12 },
+ { "SGE_DBFIFO_STATUS3", 0x1140, 0 },
+ { "LP_Ptrs_Equal", 21, 1 },
+ { "LP_Snaphot", 20, 1 },
+ { "FL_Int_Thresh_Low", 16, 4 },
+ { "HP_Int_Thresh_Low", 12, 4 },
+ { "LP_Int_Thresh_Low", 0, 12 },
+ { "SGE_CHANGESET", 0x1144, 0 },
+ { "SGE_PC_RSP_ERROR", 0x1148, 0 },
+ { "SGE_PC0_REQ_BIST_CMD", 0x1180, 0 },
+ { "SGE_PC0_REQ_BIST_ERROR_CNT", 0x1184, 0 },
+ { "SGE_PC1_REQ_BIST_CMD", 0x1190, 0 },
+ { "SGE_PC1_REQ_BIST_ERROR_CNT", 0x1194, 0 },
+ { "SGE_PC0_RSP_BIST_CMD", 0x11a0, 0 },
+ { "SGE_PC0_RSP_BIST_ERROR_CNT", 0x11a4, 0 },
+ { "SGE_PC1_RSP_BIST_CMD", 0x11b0, 0 },
+ { "SGE_PC1_RSP_BIST_ERROR_CNT", 0x11b4, 0 },
+ { "SGE_CTXT_CMD", 0x11fc, 0 },
+ { "Busy", 31, 1 },
+ { "Opcode", 28, 2 },
+ { "CtxtType", 24, 2 },
+ { "QID", 0, 17 },
+ { "SGE_CTXT_DATA0", 0x1200, 0 },
+ { "SGE_CTXT_DATA1", 0x1204, 0 },
+ { "SGE_CTXT_DATA2", 0x1208, 0 },
+ { "SGE_CTXT_DATA3", 0x120c, 0 },
+ { "SGE_CTXT_DATA4", 0x1210, 0 },
+ { "SGE_CTXT_DATA5", 0x1214, 0 },
+ { "SGE_CTXT_DATA6", 0x1218, 0 },
+ { "SGE_CTXT_DATA7", 0x121c, 0 },
+ { "SGE_CTXT_MASK0", 0x1220, 0 },
+ { "SGE_CTXT_MASK1", 0x1224, 0 },
+ { "SGE_CTXT_MASK2", 0x1228, 0 },
+ { "SGE_CTXT_MASK3", 0x122c, 0 },
+ { "SGE_CTXT_MASK4", 0x1230, 0 },
+ { "SGE_CTXT_MASK5", 0x1234, 0 },
+ { "SGE_CTXT_MASK6", 0x1238, 0 },
+ { "SGE_CTXT_MASK7", 0x123c, 0 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_0", 0x1280, 0 },
+ { "CIM_WM", 24, 2 },
+ { "debug_uP_SOP_cnt", 20, 4 },
+ { "debug_uP_EOP_cnt", 16, 4 },
+ { "debug_CIM_SOP1_cnt", 12, 4 },
+ { "debug_CIM_EOP1_cnt", 8, 4 },
+ { "debug_CIM_SOP0_cnt", 4, 4 },
+ { "debug_CIM_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_1", 0x1284, 0 },
+ { "debug_T_Rx_SOP1_cnt", 28, 4 },
+ { "debug_T_Rx_EOP1_cnt", 24, 4 },
+ { "debug_T_Rx_SOP0_cnt", 20, 4 },
+ { "debug_T_Rx_EOP0_cnt", 16, 4 },
+ { "debug_U_Rx_SOP1_cnt", 12, 4 },
+ { "debug_U_Rx_EOP1_cnt", 8, 4 },
+ { "debug_U_Rx_SOP0_cnt", 4, 4 },
+ { "debug_U_Rx_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_2", 0x1288, 0 },
+ { "debug_UD_Rx_SOP3_cnt", 28, 4 },
+ { "debug_UD_Rx_EOP3_cnt", 24, 4 },
+ { "debug_UD_Rx_SOP2_cnt", 20, 4 },
+ { "debug_UD_Rx_EOP2_cnt", 16, 4 },
+ { "debug_UD_Rx_SOP1_cnt", 12, 4 },
+ { "debug_UD_Rx_EOP1_cnt", 8, 4 },
+ { "debug_UD_Rx_SOP0_cnt", 4, 4 },
+ { "debug_UD_Rx_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_3", 0x128c, 0 },
+ { "debug_U_Tx_SOP3_cnt", 28, 4 },
+ { "debug_U_Tx_EOP3_cnt", 24, 4 },
+ { "debug_U_Tx_SOP2_cnt", 20, 4 },
+ { "debug_U_Tx_EOP2_cnt", 16, 4 },
+ { "debug_U_Tx_SOP1_cnt", 12, 4 },
+ { "debug_U_Tx_EOP1_cnt", 8, 4 },
+ { "debug_U_Tx_SOP0_cnt", 4, 4 },
+ { "debug_U_Tx_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_4", 0x1290, 0 },
+ { "debug_PC_Rsp_SOP1_cnt", 28, 4 },
+ { "debug_PC_Rsp_EOP1_cnt", 24, 4 },
+ { "debug_PC_Rsp_SOP0_cnt", 20, 4 },
+ { "debug_PC_Rsp_EOP0_cnt", 16, 4 },
+ { "debug_PC_Req_SOP1_cnt", 12, 4 },
+ { "debug_PC_Req_EOP1_cnt", 8, 4 },
+ { "debug_PC_Req_SOP0_cnt", 4, 4 },
+ { "debug_PC_Req_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_5", 0x1294, 0 },
+ { "debug_PD_RdReq_SOP3_cnt", 28, 4 },
+ { "debug_PD_RdReq_EOP3_cnt", 24, 4 },
+ { "debug_PD_RdReq_SOP2_cnt", 20, 4 },
+ { "debug_PD_RdReq_EOP2_cnt", 16, 4 },
+ { "debug_PD_RdReq_SOP1_cnt", 12, 4 },
+ { "debug_PD_RdReq_EOP1_cnt", 8, 4 },
+ { "debug_PD_RdReq_SOP0_cnt", 4, 4 },
+ { "debug_PD_RdReq_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_6", 0x1298, 0 },
+ { "debug_PD_RdRsp_SOP3_cnt", 28, 4 },
+ { "debug_PD_RdRsp_EOP3_cnt", 24, 4 },
+ { "debug_PD_RdRsp_SOP2_cnt", 20, 4 },
+ { "debug_PD_RdRsp_EOP2_cnt", 16, 4 },
+ { "debug_PD_RdRsp_SOP1_cnt", 12, 4 },
+ { "debug_PD_RdRsp_EOP1_cnt", 8, 4 },
+ { "debug_PD_RdRsp_SOP0_cnt", 4, 4 },
+ { "debug_PD_RdRsp_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_7", 0x129c, 0 },
+ { "debug_PD_WrReq_SOP3_cnt", 28, 4 },
+ { "debug_PD_WrReq_EOP3_cnt", 24, 4 },
+ { "debug_PD_WrReq_SOP2_cnt", 20, 4 },
+ { "debug_PD_WrReq_EOP2_cnt", 16, 4 },
+ { "debug_PD_WrReq_SOP1_cnt", 12, 4 },
+ { "debug_PD_WrReq_EOP1_cnt", 8, 4 },
+ { "debug_PD_WrReq_SOP0_cnt", 4, 4 },
+ { "debug_PD_WrReq_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_8", 0x12a0, 0 },
+ { "GlobalEnable_Off", 29, 1 },
+ { "debug_CIM2SGE_RxAFull_d", 27, 2 },
+ { "debug_CPLSW_CIM_TxAFull_d", 25, 2 },
+ { "debug_uP_Full", 24, 1 },
+ { "debug_M_rd_req_outstanding_PC", 23, 1 },
+ { "debug_M_rd_req_outstanding_VFIFO", 22, 1 },
+ { "debug_M_rd_req_outstanding_IMSG", 21, 1 },
+ { "debug_M_rd_req_outstanding_CMARB", 20, 1 },
+ { "debug_M_rd_req_outstanding_FLM", 19, 1 },
+ { "debug_M_ReqVld", 18, 1 },
+ { "debug_M_ReqRdy", 17, 1 },
+ { "debug_M_RspVld", 16, 1 },
+ { "debug_PD_WrReq_Int3_cnt", 12, 4 },
+ { "debug_PD_WrReq_Int2_cnt", 8, 4 },
+ { "debug_PD_WrReq_Int1_cnt", 4, 4 },
+ { "debug_PD_WrReq_Int0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_9", 0x12a4, 0 },
+ { "debug_CPLSW_TP_Rx_SOP1_cnt", 28, 4 },
+ { "debug_CPLSW_TP_Rx_EOP1_cnt", 24, 4 },
+ { "debug_CPLSW_TP_Rx_SOP0_cnt", 20, 4 },
+ { "debug_CPLSW_TP_Rx_EOP0_cnt", 16, 4 },
+ { "debug_CPLSW_CIM_SOP1_cnt", 12, 4 },
+ { "debug_CPLSW_CIM_EOP1_cnt", 8, 4 },
+ { "debug_CPLSW_CIM_SOP0_cnt", 4, 4 },
+ { "debug_CPLSW_CIM_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_10", 0x12a8, 0 },
+ { "debug_T_RxAFull_d", 30, 2 },
+ { "debug_PD_RdRspAFull_d", 26, 4 },
+ { "debug_PD_RdReqAFull_d", 22, 4 },
+ { "debug_PD_WrReqAFull_d", 18, 4 },
+ { "debug_PC_RspAFull_d", 15, 3 },
+ { "debug_PC_ReqAFull_d", 12, 3 },
+ { "debug_U_TxAFull_d", 8, 4 },
+ { "debug_UD_RxAFull_d", 4, 4 },
+ { "debug_U_RxAFull_d", 2, 2 },
+ { "debug_CIM_AFull_d", 0, 2 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_11", 0x12ac, 0 },
+ { "debug_flm_idma1_cache_data_active", 24, 1 },
+ { "debug_flm_idma1_cache_hdr_active", 23, 1 },
+ { "debug_flm_idma1_ctxt_data_active", 22, 1 },
+ { "debug_flm_idma1_ctxt_hdr_active", 21, 1 },
+ { "debug_st_flm_idma1_cache", 19, 2 },
+ { "debug_st_flm_idma1_ctxt", 16, 3 },
+ { "debug_flm_idma0_cache_data_active", 8, 1 },
+ { "debug_flm_idma0_cache_hdr_active", 7, 1 },
+ { "debug_flm_idma0_ctxt_data_active", 6, 1 },
+ { "debug_flm_idma0_ctxt_hdr_active", 5, 1 },
+ { "debug_st_flm_idma0_cache", 3, 2 },
+ { "debug_st_flm_idma0_ctxt", 0, 3 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_12", 0x12b0, 0 },
+ { "debug_CPLSW_SOP1_cnt", 28, 4 },
+ { "debug_CPLSW_EOP1_cnt", 24, 4 },
+ { "debug_CPLSW_SOP0_cnt", 20, 4 },
+ { "debug_CPLSW_EOP0_cnt", 16, 4 },
+ { "debug_PC_Rsp_SOP2_cnt", 12, 4 },
+ { "debug_PC_Rsp_EOP2_cnt", 8, 4 },
+ { "debug_PC_Req_SOP2_cnt", 4, 4 },
+ { "debug_PC_Req_EOP2_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_13", 0x12b4, 0 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_14", 0x12b8, 0 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_15", 0x12bc, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_0", 0x12c0, 0 },
+ { "debug_st_idma1_flm_req", 29, 3 },
+ { "debug_st_idma0_flm_req", 26, 3 },
+ { "debug_st_imsg_ctxt", 23, 3 },
+ { "debug_st_imsg", 18, 5 },
+ { "debug_st_idma1_ialn", 16, 2 },
+ { "debug_st_idma1_idma_sm", 9, 6 },
+ { "debug_st_idma0_ialn", 7, 2 },
+ { "debug_st_idma0_idma_sm", 0, 6 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_1", 0x12c4, 0 },
+ { "debug_itp_empty", 12, 6 },
+ { "debug_itp_expired", 6, 6 },
+ { "debug_itp_pause", 5, 1 },
+ { "debug_itp_del_done", 4, 1 },
+ { "debug_itp_add_done", 3, 1 },
+ { "debug_itp_evr_state", 0, 3 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_2", 0x12c8, 0 },
+ { "debug_st_dbp_thread2_cimfl", 25, 5 },
+ { "debug_st_dbp_thread2_main", 20, 5 },
+ { "debug_st_dbp_thread1_cimfl", 15, 5 },
+ { "debug_st_dbp_thread1_main", 10, 5 },
+ { "debug_st_dbp_thread0_cimfl", 5, 5 },
+ { "debug_st_dbp_thread0_main", 0, 5 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_3", 0x12cc, 0 },
+ { "debug_st_dbp_upcp_main", 14, 5 },
+ { "debug_st_dbp_dbfifo_main", 13, 1 },
+ { "debug_st_dbp_ctxt", 10, 3 },
+ { "debug_st_dbp_thread3_cimfl", 5, 5 },
+ { "debug_st_dbp_thread3_main", 0, 5 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_4", 0x12d0, 0 },
+ { "debug_st_edma3_align_sub", 29, 3 },
+ { "debug_st_edma3_align", 27, 2 },
+ { "debug_st_edma3_req", 24, 3 },
+ { "debug_st_edma2_align_sub", 21, 3 },
+ { "debug_st_edma2_align", 19, 2 },
+ { "debug_st_edma2_req", 16, 3 },
+ { "debug_st_edma1_align_sub", 13, 3 },
+ { "debug_st_edma1_align", 11, 2 },
+ { "debug_st_edma1_req", 8, 3 },
+ { "debug_st_edma0_align_sub", 5, 3 },
+ { "debug_st_edma0_align", 3, 2 },
+ { "debug_st_edma0_req", 0, 3 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_5", 0x12d4, 0 },
+ { "debug_st_flm_dbptr", 30, 2 },
+ { "debug_flm_cache_locked_count", 23, 7 },
+ { "debug_flm_cache_agent", 20, 3 },
+ { "debug_st_flm_cache", 16, 4 },
+ { "debug_flm_dbptr_cidx_stall", 12, 1 },
+ { "debug_flm_dbptr_qid", 0, 12 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_6", 0x12d8, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_7", 0x12dc, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_8", 0x12e0, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_9", 0x12e4, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_10", 0x12e8, 0 },
+ { "debug_imsg_cpl", 16, 8 },
+ { "debug_imsg_qid", 0, 16 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_11", 0x12ec, 0 },
+ { "debug_idma1_qid", 16, 16 },
+ { "debug_idma0_qid", 0, 16 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_12", 0x12f0, 0 },
+ { "debug_idma1_flm_req_qid", 16, 16 },
+ { "debug_idma0_flm_req_qid", 0, 16 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_13", 0x12f4, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_14", 0x12f8, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_15", 0x12fc, 0 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1300, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1308, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1310, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1318, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1320, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1328, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1330, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1338, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1340, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1348, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1350, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1358, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1360, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1370, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1378, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1390, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "Egress_Base", 10, 17 },
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+ { "Egress_Base", 10, 17 },
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+ { "Ingress2_Size", 5, 5 },
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+ { "Ingress2_Size", 5, 5 },
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+ { "Egress_Base", 10, 17 },
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+ { "Egress_Base", 10, 17 },
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+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "Egress_Size", 27, 5 },
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+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1470, 0 },
+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "Egress_Base", 10, 17 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1480, 0 },
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+ { "Egress_Base", 10, 17 },
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+ { "Egress_Size", 27, 5 },
+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1490, 0 },
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+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1498, 0 },
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+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1568, 0 },
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+ { "SGE_QUEUE_BASE_MAP_HIGH", 0x1570, 0 },
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+ { "Egress_Base", 10, 17 },
+ { "Ingress2_Size", 5, 5 },
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+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x14fc, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1504, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x150c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1514, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x151c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1524, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x152c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1534, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x153c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1544, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x154c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1554, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x155c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1564, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x156c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1574, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x157c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1584, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x158c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1594, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x159c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15a4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15ac, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15b4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15bc, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15c4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15cc, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15d4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15dc, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15e4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15ec, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15f4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x15fc, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1604, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x160c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1614, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x161c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1624, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x162c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1634, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x163c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1644, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x164c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1654, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x165c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1664, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x166c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1674, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x167c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1684, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x168c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1694, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x169c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16a4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16ac, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16b4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16bc, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16c4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16cc, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16d4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16dc, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16e4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16ec, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16f4, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x16fc, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1704, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x170c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1714, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x171c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1724, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x172c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x1734, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_QUEUE_BASE_MAP_LOW", 0x173c, 0 },
+ { "Ingress2_Base", 16, 16 },
+ { "Ingress1_Base", 0, 16 },
+ { "SGE_LA_RDPTR_0", 0x1800, 0 },
+ { "SGE_LA_RDDATA_0", 0x1804, 0 },
+ { "SGE_LA_WRPTR_0", 0x1808, 0 },
+ { "SGE_LA_RESERVED_0", 0x180c, 0 },
+ { "SGE_LA_RDPTR_1", 0x1810, 0 },
+ { "SGE_LA_RDDATA_1", 0x1814, 0 },
+ { "SGE_LA_WRPTR_1", 0x1818, 0 },
+ { "SGE_LA_RESERVED_1", 0x181c, 0 },
+ { "SGE_LA_RDPTR_2", 0x1820, 0 },
+ { "SGE_LA_RDDATA_2", 0x1824, 0 },
+ { "SGE_LA_WRPTR_2", 0x1828, 0 },
+ { "SGE_LA_RESERVED_2", 0x182c, 0 },
+ { "SGE_LA_RDPTR_3", 0x1830, 0 },
+ { "SGE_LA_RDDATA_3", 0x1834, 0 },
+ { "SGE_LA_WRPTR_3", 0x1838, 0 },
+ { "SGE_LA_RESERVED_3", 0x183c, 0 },
+ { "SGE_LA_RDPTR_4", 0x1840, 0 },
+ { "SGE_LA_RDDATA_4", 0x1844, 0 },
+ { "SGE_LA_WRPTR_4", 0x1848, 0 },
+ { "SGE_LA_RESERVED_4", 0x184c, 0 },
+ { "SGE_LA_RDPTR_5", 0x1850, 0 },
+ { "SGE_LA_RDDATA_5", 0x1854, 0 },
+ { "SGE_LA_WRPTR_5", 0x1858, 0 },
+ { "SGE_LA_RESERVED_5", 0x185c, 0 },
+ { "SGE_LA_RDPTR_6", 0x1860, 0 },
+ { "SGE_LA_RDDATA_6", 0x1864, 0 },
+ { "SGE_LA_WRPTR_6", 0x1868, 0 },
+ { "SGE_LA_RESERVED_6", 0x186c, 0 },
+ { "SGE_LA_RDPTR_7", 0x1870, 0 },
+ { "SGE_LA_RDDATA_7", 0x1874, 0 },
+ { "SGE_LA_WRPTR_7", 0x1878, 0 },
+ { "SGE_LA_RESERVED_7", 0x187c, 0 },
+ { "SGE_LA_RDPTR_8", 0x1880, 0 },
+ { "SGE_LA_RDDATA_8", 0x1884, 0 },
+ { "SGE_LA_WRPTR_8", 0x1888, 0 },
+ { "SGE_LA_RESERVED_8", 0x188c, 0 },
+ { "SGE_LA_RDPTR_9", 0x1890, 0 },
+ { "SGE_LA_RDDATA_9", 0x1894, 0 },
+ { "SGE_LA_WRPTR_9", 0x1898, 0 },
+ { "SGE_LA_RESERVED_9", 0x189c, 0 },
+ { "SGE_LA_RDPTR_10", 0x18a0, 0 },
+ { "SGE_LA_RDDATA_10", 0x18a4, 0 },
+ { "SGE_LA_WRPTR_10", 0x18a8, 0 },
+ { "SGE_LA_RESERVED_10", 0x18ac, 0 },
+ { "SGE_LA_RDPTR_11", 0x18b0, 0 },
+ { "SGE_LA_RDDATA_11", 0x18b4, 0 },
+ { "SGE_LA_WRPTR_11", 0x18b8, 0 },
+ { "SGE_LA_RESERVED_11", 0x18bc, 0 },
+ { "SGE_LA_RDPTR_12", 0x18c0, 0 },
+ { "SGE_LA_RDDATA_12", 0x18c4, 0 },
+ { "SGE_LA_WRPTR_12", 0x18c8, 0 },
+ { "SGE_LA_RESERVED_12", 0x18cc, 0 },
+ { "SGE_LA_RDPTR_13", 0x18d0, 0 },
+ { "SGE_LA_RDDATA_13", 0x18d4, 0 },
+ { "SGE_LA_WRPTR_13", 0x18d8, 0 },
+ { "SGE_LA_RESERVED_13", 0x18dc, 0 },
+ { "SGE_LA_RDPTR_14", 0x18e0, 0 },
+ { "SGE_LA_RDDATA_14", 0x18e4, 0 },
+ { "SGE_LA_WRPTR_14", 0x18e8, 0 },
+ { "SGE_LA_RESERVED_14", 0x18ec, 0 },
+ { "SGE_LA_RDPTR_15", 0x18f0, 0 },
+ { "SGE_LA_RDDATA_15", 0x18f4, 0 },
+ { "SGE_LA_WRPTR_15", 0x18f8, 0 },
+ { "SGE_LA_RESERVED_15", 0x18fc, 0 },
+ { NULL }
+};
+
+struct reg_info t5_pcie_regs[] = {
+ { "PCIE_INT_ENABLE", 0x3000, 0 },
+ { "IPGrpPerr", 31, 1 },
+ { "NonFatalErr", 30, 1 },
+ { "RdRspErr", 29, 1 },
+ { "TRGT1GrpPerr", 28, 1 },
+ { "IPSOTPerr", 27, 1 },
+ { "IPRetryPerr", 26, 1 },
+ { "IPRxDataGrpPerr", 25, 1 },
+ { "IPRxHdrGrpPerr", 24, 1 },
+ { "PIOTagQPerr", 23, 1 },
+ { "MAGrpPerr", 22, 1 },
+ { "VFIDPerr", 21, 1 },
+ { "FIDPerr", 20, 1 },
+ { "CfgSnpPerr", 19, 1 },
+ { "HRspPerr", 18, 1 },
+ { "HReqRdPerr", 17, 1 },
+ { "HReqWrPerr", 16, 1 },
+ { "DRspPerr", 15, 1 },
+ { "DReqRdPerr", 14, 1 },
+ { "DReqWrPerr", 13, 1 },
+ { "CRspPerr", 12, 1 },
+ { "CReqRdPerr", 11, 1 },
+ { "MstTagQPerr", 10, 1 },
+ { "TgtTagQPerr", 9, 1 },
+ { "PIOReqGrpPerr", 8, 1 },
+ { "PIOCplGrpPerr", 7, 1 },
+ { "MSIXDIPerr", 6, 1 },
+ { "MSIXDataPerr", 5, 1 },
+ { "MSIXAddrHPerr", 4, 1 },
+ { "MSIXAddrLPerr", 3, 1 },
+ { "MSIXStiPerr", 2, 1 },
+ { "MstTimeoutPerr", 1, 1 },
+ { "MstGrpPerr", 0, 1 },
+ { "PCIE_INT_CAUSE", 0x3004, 0 },
+ { "IPGrpPerr", 31, 1 },
+ { "NonFatalErr", 30, 1 },
+ { "RdRspErr", 29, 1 },
+ { "TRGT1GrpPerr", 28, 1 },
+ { "IPSOTPerr", 27, 1 },
+ { "IPRetryPerr", 26, 1 },
+ { "IPRxDataGrpPerr", 25, 1 },
+ { "IPRxHdrGrpPerr", 24, 1 },
+ { "PIOTagQPerr", 23, 1 },
+ { "MAGrpPerr", 22, 1 },
+ { "VFIDPerr", 21, 1 },
+ { "FIDPerr", 20, 1 },
+ { "CfgSnpPerr", 19, 1 },
+ { "HRspPerr", 18, 1 },
+ { "HReqRdPerr", 17, 1 },
+ { "HReqWrPerr", 16, 1 },
+ { "DRspPerr", 15, 1 },
+ { "DReqRdPerr", 14, 1 },
+ { "DReqWrPerr", 13, 1 },
+ { "CRspPerr", 12, 1 },
+ { "CReqRdPerr", 11, 1 },
+ { "MstTagQPerr", 10, 1 },
+ { "TgtTagQPerr", 9, 1 },
+ { "PIOReqGrpPerr", 8, 1 },
+ { "PIOCplGrpPerr", 7, 1 },
+ { "MSIXDIPerr", 6, 1 },
+ { "MSIXDataPerr", 5, 1 },
+ { "MSIXAddrHPerr", 4, 1 },
+ { "MSIXAddrLPerr", 3, 1 },
+ { "MSIXStiPerr", 2, 1 },
+ { "MstTimeoutPerr", 1, 1 },
+ { "MstGrpPerr", 0, 1 },
+ { "PCIE_PERR_ENABLE", 0x3008, 0 },
+ { "IPGrpPerr", 31, 1 },
+ { "TRGT1GrpPerr", 28, 1 },
+ { "IPSOTPerr", 27, 1 },
+ { "IPRetryPerr", 26, 1 },
+ { "IPRxDataGrpPerr", 25, 1 },
+ { "IPRxHdrGrpPerr", 24, 1 },
+ { "PIOTagQPerr", 23, 1 },
+ { "MAGrpPerr", 22, 1 },
+ { "VFIDPerr", 21, 1 },
+ { "FIDPerr", 20, 1 },
+ { "CfgSnpPerr", 19, 1 },
+ { "HRspPerr", 18, 1 },
+ { "HReqRdPerr", 17, 1 },
+ { "HReqWrPerr", 16, 1 },
+ { "DRspPerr", 15, 1 },
+ { "DReqRdPerr", 14, 1 },
+ { "DReqWrPerr", 13, 1 },
+ { "CRspPerr", 12, 1 },
+ { "CReqRdPerr", 11, 1 },
+ { "MstTagQPerr", 10, 1 },
+ { "TgtTagQPerr", 9, 1 },
+ { "PIOReqGrpPerr", 8, 1 },
+ { "PIOCplGrpPerr", 7, 1 },
+ { "MSIXDIPerr", 6, 1 },
+ { "MSIXDataPerr", 5, 1 },
+ { "MSIXAddrHPerr", 4, 1 },
+ { "MSIXAddrLPerr", 3, 1 },
+ { "MSIXStiPerr", 2, 1 },
+ { "MstTimeoutPerr", 1, 1 },
+ { "MstGrpPerr", 0, 1 },
+ { "PCIE_PERR_INJECT", 0x300c, 0 },
+ { "MemSel", 1, 5 },
+ { "IDE", 0, 1 },
+ { "PCIE_NONFAT_ERR", 0x3010, 0 },
+ { "MAReqTimeout", 29, 1 },
+ { "TRGT1BARTypeErr", 28, 1 },
+ { "MAExtraRspErr", 27, 1 },
+ { "MARspTimeout", 26, 1 },
+ { "INTVFAllMSIDisErr", 25, 1 },
+ { "INTVFRangeErr", 24, 1 },
+ { "INTPLIRspErr", 23, 1 },
+ { "MEMReqRdTagErr", 22, 1 },
+ { "CFGInitDoneErr", 21, 1 },
+ { "BAR2Timeout", 20, 1 },
+ { "VPDTimeout", 19, 1 },
+ { "MEMRspRdTagErr", 18, 1 },
+ { "MEMRspWrTagErr", 17, 1 },
+ { "PIORspRdTagErr", 16, 1 },
+ { "PIORspWrTagErr", 15, 1 },
+ { "DBITimeout", 14, 1 },
+ { "PIOUnAlindWr", 13, 1 },
+ { "BAR2RdErr", 12, 1 },
+ { "MAWrEOPErr", 11, 1 },
+ { "MARdEOPErr", 10, 1 },
+ { "RdRspErr", 9, 1 },
+ { "VPDRspErr", 8, 1 },
+ { "MemReq", 4, 1 },
+ { "PIOReq", 3, 1 },
+ { "BAR2Req", 2, 1 },
+ { "CfgSnp", 0, 1 },
+ { "PCIE_CFG", 0x3014, 0 },
+ { "PIOStopEn", 31, 1 },
+ { "DiagCtrlBus", 28, 3 },
+ { "IPPerrEn", 27, 1 },
+ { "CfgdExtTagEn", 26, 1 },
+ { "CfgdMaxPyldSz", 23, 3 },
+ { "CfgdMaxRdReqSz", 20, 3 },
+ { "DCAEn", 17, 1 },
+ { "CMDReqPriority", 16, 1 },
+ { "VPDReqProtect", 14, 2 },
+ { "DroppedRdRspData", 12, 1 },
+ { "AI_INTX_ReAssertEn", 11, 1 },
+ { "AutoTxnDisable", 10, 1 },
+ { "TC0_Stamp", 9, 1 },
+ { "AI_TCVal", 6, 3 },
+ { "DMAStopEn", 5, 1 },
+ { "DevStateRstMode", 4, 1 },
+ { "LinkReqRstPCIeCRstMode", 3, 1 },
+ { "LinkDnRstEn", 0, 1 },
+ { "PCIE_CFG2", 0x3018, 0 },
+ { "VPDTimer", 16, 16 },
+ { "BAR2Timer", 4, 12 },
+ { "MstReqRdRRASimple", 3, 1 },
+ { "TotMaxTag", 0, 2 },
+ { "PCIE_CFG3", 0x301c, 0 },
+ { "AutoPIOCookieMatch", 6, 1 },
+ { "FLRPndCplMode", 4, 2 },
+ { "HMADCASTFirstOnly", 2, 1 },
+ { "CMDDCASTFirstOnly", 1, 1 },
+ { "DMADCASTFirstOnly", 0, 1 },
+ { "PCIE_CFG4", 0x3020, 0 },
+ { "L1ClkRemovalEn", 17, 1 },
+ { "ReadyEnterL23", 16, 1 },
+ { "ExitL1", 12, 1 },
+ { "EnterL1", 8, 1 },
+ { "GenPME", 0, 8 },
+ { "PCIE_CFG5", 0x3024, 0 },
+ { "EnableSKPParityFix", 2, 1 },
+ { "EnableL2EntryInL1", 1, 1 },
+ { "HoldCplEnteringL1", 0, 1 },
+ { "PCIE_CFG6", 0x3028, 0 },
+ { "PERstTimerCount", 12, 14 },
+ { "PERstTimeout", 8, 1 },
+ { "PERstTimer", 0, 4 },
+ { "PCIE_CFG_SPACE_REQ", 0x3060, 0 },
+ { "Enable", 30, 1 },
+ { "AI", 29, 1 },
+ { "CS2", 28, 1 },
+ { "WrBE", 24, 4 },
+ { "VFVld", 23, 1 },
+ { "RVF", 16, 7 },
+ { "PF", 12, 3 },
+ { "ExtRegister", 8, 4 },
+ { "Register", 0, 8 },
+ { "PCIE_CFG_SPACE_DATA", 0x3064, 0 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3068, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x306c, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3070, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x3074, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3078, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x307c, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3080, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x3084, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3088, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x308c, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3090, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x3094, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3098, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x309c, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x30a0, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x30a4, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MAILBOX_BASE_WIN", 0x30a8, 0 },
+ { "PCIEOfst", 6, 26 },
+ { "BIR", 4, 2 },
+ { "Window", 0, 2 },
+ { "PCIE_MAILBOX_OFFSET", 0x30ac, 0 },
+ { "MemOfst", 7, 25 },
+ { "PCIE_MA_CTRL", 0x30b0, 0 },
+ { "TagFree", 29, 1 },
+ { "MaxRspCnt", 24, 5 },
+ { "MaxReqCnt", 16, 7 },
+ { "MaxReqSize", 8, 3 },
+ { "MaxTag", 0, 5 },
+ { "PCIE_FW", 0x30b8, 0 },
+ { "PCIE_FW_PF", 0x30bc, 0 },
+ { "PCIE_FW_PF", 0x30c0, 0 },
+ { "PCIE_FW_PF", 0x30c4, 0 },
+ { "PCIE_FW_PF", 0x30c8, 0 },
+ { "PCIE_FW_PF", 0x30cc, 0 },
+ { "PCIE_FW_PF", 0x30d0, 0 },
+ { "PCIE_FW_PF", 0x30d4, 0 },
+ { "PCIE_FW_PF", 0x30d8, 0 },
+ { "PCIE_PIO_PAUSE", 0x30dc, 0 },
+ { "PIOPauseDone", 31, 1 },
+ { "MSTPauseDone", 30, 1 },
+ { "PauseTime", 4, 24 },
+ { "MSTPause", 1, 1 },
+ { "PIOPause", 0, 1 },
+ { "PCIE_MA_STAT", 0x30e0, 0 },
+ { "PCIE_STATIC_CFG1", 0x30e4, 0 },
+ { "AUXPOWER_DETECTED", 27, 1 },
+ { "PCIE_STATIC_CFG2", 0x30e8, 0 },
+ { "PL_CONTROL", 16, 16 },
+ { "STATIC_SPARE3", 0, 14 },
+ { "PCIE_DBG_INDIR_REQ", 0x30ec, 0 },
+ { "Enable", 31, 1 },
+ { "AI", 30, 1 },
+ { "Pointer", 8, 16 },
+ { "Select", 0, 4 },
+ { "PCIE_DBG_INDIR_DATA_0", 0x30f0, 0 },
+ { "PCIE_DBG_INDIR_DATA_1", 0x30f4, 0 },
+ { "PCIE_DBG_INDIR_DATA_2", 0x30f8, 0 },
+ { "PCIE_DBG_INDIR_DATA_3", 0x30fc, 0 },
+ { "PCIE_PF_INT_CFG", 0x3140, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x3144, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3148, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x314c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3150, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x3154, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3158, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x315c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3160, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x3164, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3168, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x316c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3170, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x3174, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3178, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x317c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3180, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3184, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3188, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x318c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3190, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3194, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3198, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x319c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31a0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31a4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31a8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31ac, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31b0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31b4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31b8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31bc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31c0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31c4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31c8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31cc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31d0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31d4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31d8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31dc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31e0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31e4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31e8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31ec, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31f0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31f4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31f8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31fc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3200, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3204, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3208, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x320c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3210, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3214, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3218, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x321c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3220, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3224, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3228, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x322c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3230, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3234, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3238, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x323c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3240, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3244, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3248, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x324c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3250, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3254, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3258, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x325c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3260, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3264, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3268, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x326c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3270, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3274, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3278, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x327c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3280, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3284, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3288, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x328c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3290, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3294, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3298, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x329c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32a0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32a4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32a8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32ac, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32b0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32b4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32b8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32bc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32c0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32c4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32c8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32cc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32d0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32d4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32d8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32dc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32e0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32e4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32e8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32ec, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32f0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32f4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32f8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32fc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3300, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3304, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3308, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x330c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3310, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3314, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3318, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x331c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3320, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3324, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3328, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x332c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3330, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3334, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3338, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x333c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3340, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3344, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3348, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x334c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3350, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3354, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3358, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x335c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3360, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3364, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3368, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x336c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3370, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3374, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3378, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x337c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3380, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3384, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3388, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x338c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3390, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3394, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3398, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x339c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33a0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33a4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33a8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33ac, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33b0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33b4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33b8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33bc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33c0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33c4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33c8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33cc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33d0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33d4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33d8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33dc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33e0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33e4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33e8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33ec, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33f0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33f4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33f8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33fc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3400, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3404, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3408, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x340c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3410, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3414, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3418, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x341c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3420, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3424, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3428, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x342c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3430, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3434, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3438, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x343c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3440, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3444, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3448, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x344c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3450, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3454, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3458, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x345c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3460, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3464, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3468, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x346c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3470, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3474, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3478, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x347c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3480, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3484, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3488, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x348c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3490, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3494, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3498, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x349c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34a0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34a4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34a8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34ac, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34b0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34b4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34b8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34bc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34c0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34c4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34c8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34cc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34d0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34d4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34d8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34dc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34e0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34e4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34e8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34ec, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34f0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34f4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34f8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34fc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3500, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3504, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3508, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x350c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3510, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3514, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3518, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x351c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3520, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3524, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3528, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x352c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3530, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3534, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3538, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x353c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3540, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3544, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3548, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x354c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3550, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3554, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3558, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x355c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3560, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3564, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3568, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x356c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3570, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3574, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3578, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x357c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_MSI_EN", 0x35a8, 0 },
+ { "PCIE_VF_MSI_EN_0", 0x35ac, 0 },
+ { "PCIE_VF_MSI_EN_1", 0x35b0, 0 },
+ { "PCIE_VF_MSI_EN_2", 0x35b4, 0 },
+ { "PCIE_VF_MSI_EN_3", 0x35b8, 0 },
+ { "PCIE_PF_MSIX_EN", 0x35bc, 0 },
+ { "PCIE_VF_MSIX_EN_0", 0x35c0, 0 },
+ { "PCIE_VF_MSIX_EN_1", 0x35c4, 0 },
+ { "PCIE_VF_MSIX_EN_2", 0x35c8, 0 },
+ { "PCIE_VF_MSIX_EN_3", 0x35cc, 0 },
+ { "PCIE_FID_VFID_SEL", 0x35ec, 0 },
+ { "PCIE_FID_VFID", 0x3600, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3604, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3608, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x360c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3610, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3614, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3618, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x361c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3620, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3624, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3628, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x362c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3630, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3634, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3638, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x363c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3640, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3644, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3648, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x364c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3650, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3654, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3658, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x365c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3660, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3664, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3668, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x366c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3670, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3674, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3678, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x367c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3680, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3684, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3688, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x368c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3690, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3694, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3698, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x369c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36a0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36a4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36a8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36ac, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36b0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36b4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36b8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36bc, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36c0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36c4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36c8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36cc, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36d0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36d4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36d8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36dc, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36e0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36e4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36e8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36ec, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36f0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36f4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36f8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x36fc, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3700, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3704, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3708, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x370c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3710, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3714, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3718, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x371c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3720, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x3724, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
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+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x55e8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x55ec, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x55f0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x55f4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x55f8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_FID_VFID", 0x55fc, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 16, 8 },
+ { "TC", 11, 3 },
+ { "VFVld", 10, 1 },
+ { "PF", 7, 3 },
+ { "RVF", 0, 7 },
+ { "PCIE_COOKIE_STAT", 0x5600, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x5604, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x5608, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x560c, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x5610, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x5614, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x5618, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x561c, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_FLR_PIO", 0x5620, 0 },
+ { "RcvdBAR2Cookie", 24, 8 },
+ { "RcvdMARspCookie", 16, 8 },
+ { "RcvdPIORspCookie", 8, 8 },
+ { "ExpdCookie", 0, 8 },
+ { "PCIE_FLR_PIO2", 0x5624, 0 },
+ { "RcvdMAReqCookie", 16, 8 },
+ { "RcvdPIOReqCookie", 8, 8 },
+ { "PCIE_VC0_CDTS0", 0x56cc, 0 },
+ { "CPLD0", 20, 12 },
+ { "PH0", 12, 8 },
+ { "PD0", 0, 12 },
+ { "PCIE_VC0_CDTS1", 0x56d0, 0 },
+ { "CPLH0", 20, 8 },
+ { "NPH0", 12, 8 },
+ { "NPD0", 0, 12 },
+ { "PCIE_VC1_CDTS0", 0x56d4, 0 },
+ { "CPLD1", 20, 12 },
+ { "PH1", 12, 8 },
+ { "PD1", 0, 12 },
+ { "PCIE_VC1_CDTS1", 0x56d8, 0 },
+ { "CPLH1", 20, 8 },
+ { "NPH1", 12, 8 },
+ { "NPD1", 0, 12 },
+ { "PCIE_FLR_PF_STATUS", 0x56dc, 0 },
+ { "PCIE_FLR_VF0_STATUS", 0x56e0, 0 },
+ { "PCIE_FLR_VF1_STATUS", 0x56e4, 0 },
+ { "PCIE_FLR_VF2_STATUS", 0x56e8, 0 },
+ { "PCIE_FLR_VF3_STATUS", 0x56ec, 0 },
+ { "PCIE_STAT", 0x56f4, 0 },
+ { "PM_Status", 24, 8 },
+ { "PM_CurrentState", 20, 3 },
+ { "LTSSMEnable", 12, 1 },
+ { "StateCfgInitF", 4, 7 },
+ { "StateCfgInit", 0, 4 },
+ { "PCIE_CRS", 0x56f8, 0 },
+ { "PCIE_LTSSM", 0x56fc, 0 },
+ { "PCIE_PF_CFG", 0x1e040, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1e044, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1e04c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1e440, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1e444, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1e44c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1e840, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1e844, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1e84c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1ec40, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1ec44, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1ec4c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1f040, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1f044, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1f04c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1f440, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1f444, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1f44c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1f840, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1f844, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1f84c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1fc40, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1fc44, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1fc4c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER", 0x5700, 0 },
+ { "Replay_Time_Limit", 16, 16 },
+ { "Ack_Latency_Timer_Limit", 0, 16 },
+ { "PCIE_CORE_VENDOR_SPECIFIC_DLLP", 0x5704, 0 },
+ { "PCIE_CORE_PORT_FORCE_LINK", 0x5708, 0 },
+ { "Low_Power_Entrance_Count", 24, 8 },
+ { "Link_State", 16, 6 },
+ { "Force_Link", 15, 1 },
+ { "Link_Number", 0, 8 },
+ { "PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL", 0x570c, 0 },
+ { "Enter_ASPM_L1_wo_L0s", 30, 1 },
+ { "L1_Entrance_Latency", 27, 3 },
+ { "L0s_Entrance_Latency", 24, 3 },
+ { "Common_Clock_N_FTS", 16, 8 },
+ { "N_FTS", 8, 8 },
+ { "Ack_Frequency", 0, 8 },
+ { "PCIE_CORE_PORT_LINK_CONTROL", 0x5710, 0 },
+ { "Crosslink_Active", 23, 1 },
+ { "Crosslink_Enable", 22, 1 },
+ { "Link_Mode_Enable", 16, 6 },
+ { "Fast_Link_Mode", 7, 1 },
+ { "DLL_Link_Enable", 5, 1 },
+ { "Reset_Assert", 3, 1 },
+ { "Loopback_Enable", 2, 1 },
+ { "Scramble_Disable", 1, 1 },
+ { "Vendor_Specific_DLLP_Request", 0, 1 },
+ { "PCIE_CORE_LANE_SKEW", 0x5714, 0 },
+ { "Disable_DeSkew", 31, 1 },
+ { "Ack_Nak_Disable", 25, 1 },
+ { "Flow_Control_Disable", 24, 1 },
+ { "Insert_TxSkew", 0, 24 },
+ { "PCIE_CORE_SYMBOL_NUMBER", 0x5718, 0 },
+ { "Flow_Control_Timer_Modifier", 24, 5 },
+ { "Ack_Nak_Timer_Modifier", 19, 5 },
+ { "Replay_Timer_Modifier", 14, 5 },
+ { "MaxFunc", 0, 3 },
+ { "PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1", 0x571c, 0 },
+ { "Mask_RADM_Filter", 16, 16 },
+ { "Disable_FC_Watchdog", 15, 1 },
+ { "SKP_Interval", 0, 11 },
+ { "PCIE_CORE_FILTER_MASK2", 0x5720, 0 },
+ { "PCIE_CORE_DEBUG_0", 0x5728, 0 },
+ { "PCIE_CORE_DEBUG_1", 0x572c, 0 },
+ { "PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS", 0x5730, 0 },
+ { "TxPH_FC", 12, 8 },
+ { "TxPD_FC", 0, 12 },
+ { "PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS", 0x5734, 0 },
+ { "TxNPH_FC", 12, 8 },
+ { "TxNPD_FC", 0, 12 },
+ { "PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS", 0x5738, 0 },
+ { "TxCPLH_FC", 12, 8 },
+ { "TxCPLD_FC", 0, 12 },
+ { "PCIE_CORE_QUEUE_STATUS", 0x573c, 0 },
+ { "RxQueue_Not_Empty", 2, 1 },
+ { "TxRetryBuf_Not_Empty", 1, 1 },
+ { "RxTLP_FC_Not_Returned", 0, 1 },
+ { "PCIE_CORE_VC_TRANSMIT_ARBITRATION_1", 0x5740, 0 },
+ { "VC3_WRR", 24, 8 },
+ { "VC2_WRR", 16, 8 },
+ { "VC1_WRR", 8, 8 },
+ { "VC0_WRR", 0, 8 },
+ { "PCIE_CORE_VC_TRANSMIT_ARBITRATION_2", 0x5744, 0 },
+ { "VC7_WRR", 24, 8 },
+ { "VC6_WRR", 16, 8 },
+ { "VC5_WRR", 8, 8 },
+ { "VC4_WRR", 0, 8 },
+ { "PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL", 0x5748, 0 },
+ { "VC0_Rx_Ordering", 31, 1 },
+ { "VC0_TLP_Ordering", 30, 1 },
+ { "VC0_PTLP_Queue_Mode", 21, 3 },
+ { "VC0_PH_Credits", 12, 8 },
+ { "VC0_PD_Credits", 0, 12 },
+ { "PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x574c, 0 },
+ { "VC0_NPTLP_Queue_Mode", 21, 3 },
+ { "VC0_NPH_Credits", 12, 8 },
+ { "VC0_NPD_Credits", 0, 12 },
+ { "PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x5750, 0 },
+ { "VC0_CPLTLP_Queue_Mode", 21, 3 },
+ { "VC0_CPLH_Credits", 12, 8 },
+ { "VC0_CPLD_Credits", 0, 12 },
+ { "PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL", 0x5754, 0 },
+ { "VC1_TLP_Ordering", 30, 1 },
+ { "VC1_PTLP_Queue_Mode", 21, 3 },
+ { "VC1_PH_Credits", 12, 8 },
+ { "VC1_PD_Credits", 0, 12 },
+ { "PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x5758, 0 },
+ { "VC1_NPTLP_Queue_Mode", 21, 3 },
+ { "VC1_NPH_Credits", 12, 8 },
+ { "VC1_NPD_Credits", 0, 12 },
+ { "PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x575c, 0 },
+ { "VC1_CPLTLP_Queue_Mode", 21, 3 },
+ { "VC1_CPLH_Credits", 12, 8 },
+ { "VC1_CPLD_Credits", 0, 12 },
+ { "PCIE_CORE_LINK_WIDTH_SPEED_CHANGE", 0x580c, 0 },
+ { "Sel_DeEmphasis", 20, 1 },
+ { "TxCmplRcv", 19, 1 },
+ { "PhyTxSwing", 18, 1 },
+ { "DirSpdChange", 17, 1 },
+ { "Num_Lanes", 8, 9 },
+ { "NFTS_Gen2_3", 0, 8 },
+ { "PCIE_CORE_PHY_STATUS", 0x5810, 0 },
+ { "PCIE_CORE_PHY_CONTROL", 0x5814, 0 },
+ { "PCIE_CORE_GEN3_CONTROL", 0x5890, 0 },
+ { "DC_Balance_Disable", 18, 1 },
+ { "DLLP_Delay_Disable", 17, 1 },
+ { "Eql_Disable", 16, 1 },
+ { "Eql_Redo_Disable", 11, 1 },
+ { "Eql_EIEOS_CntRst_Disable", 10, 1 },
+ { "Eql_PH2_PH3_Disable", 9, 1 },
+ { "Disable_Scrambler", 8, 1 },
+ { "PCIE_CORE_GEN3_EQ_FS_LF", 0x5894, 0 },
+ { "Full_Swing", 6, 6 },
+ { "Low_Frequency", 0, 6 },
+ { "PCIE_CORE_GEN3_EQ_PRESET_COEFF", 0x5898, 0 },
+ { "PostCursor", 12, 6 },
+ { "Cursor", 6, 6 },
+ { "PreCursor", 0, 6 },
+ { "PCIE_CORE_GEN3_EQ_PRESET_INDEX", 0x589c, 0 },
+ { "PCIE_CORE_GEN3_EQ_STATUS", 0x58a4, 0 },
+ { "PCIE_CORE_GEN3_EQ_CONTROL", 0x58a8, 0 },
+ { "Include_Initial_FOM", 24, 1 },
+ { "Preset_Request_Vector", 8, 16 },
+ { "Phase23_2ms_Timeout_Disable", 5, 1 },
+ { "After24ms", 4, 1 },
+ { "Feedback_Mode", 0, 4 },
+ { "PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK", 0x58ac, 0 },
+ { "WinAperture_CPlus1", 14, 4 },
+ { "WinAperture_CMins1", 10, 4 },
+ { "Convergence_WinDepth", 5, 5 },
+ { "EQMasterPhase_MinTime", 0, 5 },
+ { "PCIE_CORE_PIPE_CONTROL", 0x58b8, 0 },
+ { "PCIE_CORE_DBI_RO_WE", 0x58bc, 0 },
+ { "PCIE_DMA_CFG", 0x5940, 0 },
+ { "MaxPyldSize", 28, 3 },
+ { "MaxReqCnt", 20, 8 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 8, 9 },
+ { "SeqChkDis", 7, 1 },
+ { "MinTag", 0, 7 },
+ { "PCIE_DMA_STAT", 0x5944, 0 },
+ { "RspCnt", 20, 12 },
+ { "RdReqCnt", 12, 8 },
+ { "WrReqCnt", 0, 11 },
+ { "PCIE_DMA_STAT2", 0x5948, 0 },
+ { "CookieCnt", 24, 4 },
+ { "RdSeqNumUpdCnt", 20, 4 },
+ { "SIReqCnt", 16, 4 },
+ { "WrEOPMatchSOP", 12, 1 },
+ { "WrSOPCnt", 8, 4 },
+ { "RdSOPCnt", 0, 8 },
+ { "PCIE_DMA_STAT3", 0x594c, 0 },
+ { "AtmReqSOPCnt", 24, 8 },
+ { "AtmEOPMatchSOP", 17, 1 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_DMA_CFG", 0x5950, 0 },
+ { "MaxPyldSize", 28, 3 },
+ { "MaxReqCnt", 20, 8 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 8, 9 },
+ { "SeqChkDis", 7, 1 },
+ { "MinTag", 0, 7 },
+ { "PCIE_DMA_STAT", 0x5954, 0 },
+ { "RspCnt", 20, 12 },
+ { "RdReqCnt", 12, 8 },
+ { "WrReqCnt", 0, 11 },
+ { "PCIE_DMA_STAT2", 0x5958, 0 },
+ { "CookieCnt", 24, 4 },
+ { "RdSeqNumUpdCnt", 20, 4 },
+ { "SIReqCnt", 16, 4 },
+ { "WrEOPMatchSOP", 12, 1 },
+ { "WrSOPCnt", 8, 4 },
+ { "RdSOPCnt", 0, 8 },
+ { "PCIE_DMA_STAT3", 0x595c, 0 },
+ { "AtmReqSOPCnt", 24, 8 },
+ { "AtmEOPMatchSOP", 17, 1 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_DMA_CFG", 0x5960, 0 },
+ { "MaxPyldSize", 28, 3 },
+ { "MaxReqCnt", 20, 8 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 8, 9 },
+ { "SeqChkDis", 7, 1 },
+ { "MinTag", 0, 7 },
+ { "PCIE_DMA_STAT", 0x5964, 0 },
+ { "RspCnt", 20, 12 },
+ { "RdReqCnt", 12, 8 },
+ { "WrReqCnt", 0, 11 },
+ { "PCIE_DMA_STAT2", 0x5968, 0 },
+ { "CookieCnt", 24, 4 },
+ { "RdSeqNumUpdCnt", 20, 4 },
+ { "SIReqCnt", 16, 4 },
+ { "WrEOPMatchSOP", 12, 1 },
+ { "WrSOPCnt", 8, 4 },
+ { "RdSOPCnt", 0, 8 },
+ { "PCIE_DMA_STAT3", 0x596c, 0 },
+ { "AtmReqSOPCnt", 24, 8 },
+ { "AtmEOPMatchSOP", 17, 1 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_DMA_CFG", 0x5970, 0 },
+ { "MaxPyldSize", 28, 3 },
+ { "MaxReqCnt", 20, 8 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 8, 9 },
+ { "SeqChkDis", 7, 1 },
+ { "MinTag", 0, 7 },
+ { "PCIE_DMA_STAT", 0x5974, 0 },
+ { "RspCnt", 20, 12 },
+ { "RdReqCnt", 12, 8 },
+ { "WrReqCnt", 0, 11 },
+ { "PCIE_DMA_STAT2", 0x5978, 0 },
+ { "CookieCnt", 24, 4 },
+ { "RdSeqNumUpdCnt", 20, 4 },
+ { "SIReqCnt", 16, 4 },
+ { "WrEOPMatchSOP", 12, 1 },
+ { "WrSOPCnt", 8, 4 },
+ { "RdSOPCnt", 0, 8 },
+ { "PCIE_DMA_STAT3", 0x597c, 0 },
+ { "AtmReqSOPCnt", 24, 8 },
+ { "AtmEOPMatchSOP", 17, 1 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_CMD_CFG", 0x5980, 0 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 8, 8 },
+ { "UseCmdPool", 7, 1 },
+ { "MinTag", 0, 7 },
+ { "PCIE_CMD_STAT", 0x5984, 0 },
+ { "RspCnt", 20, 11 },
+ { "RdReqCnt", 12, 5 },
+ { "PCIE_CMD_STAT2", 0x5988, 0 },
+ { "PCIE_CMD_STAT3", 0x598c, 0 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_CMD_CFG", 0x5990, 0 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 8, 8 },
+ { "UseCmdPool", 7, 1 },
+ { "MinTag", 0, 7 },
+ { "PCIE_CMD_STAT", 0x5994, 0 },
+ { "RspCnt", 20, 11 },
+ { "RdReqCnt", 12, 5 },
+ { "PCIE_CMD_STAT2", 0x5998, 0 },
+ { "PCIE_CMD_STAT3", 0x599c, 0 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_CMD_CFG", 0x59a0, 0 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 8, 8 },
+ { "UseCmdPool", 7, 1 },
+ { "MinTag", 0, 7 },
+ { "PCIE_CMD_STAT", 0x59a4, 0 },
+ { "RspCnt", 20, 11 },
+ { "RdReqCnt", 12, 5 },
+ { "PCIE_CMD_STAT2", 0x59a8, 0 },
+ { "PCIE_CMD_STAT3", 0x59ac, 0 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_HMA_CFG", 0x59b0, 0 },
+ { "MaxPyldSize", 28, 3 },
+ { "MaxReqCnt", 20, 5 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 8, 5 },
+ { "SeqChkDis", 7, 1 },
+ { "MinTag", 0, 7 },
+ { "PCIE_HMA_STAT", 0x59b4, 0 },
+ { "RspCnt", 20, 9 },
+ { "RdReqCnt", 12, 6 },
+ { "WrReqCnt", 0, 9 },
+ { "PCIE_HMA_STAT2", 0x59b8, 0 },
+ { "CookieCnt", 24, 4 },
+ { "RdSeqNumUpdCnt", 20, 4 },
+ { "WrEOPMatchSOP", 12, 1 },
+ { "WrSOPCnt", 8, 4 },
+ { "RdSOPCnt", 0, 8 },
+ { "PCIE_HMA_STAT3", 0x59bc, 0 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_CGEN", 0x59c0, 0 },
+ { "VPD_Dynamic_CGEN", 26, 1 },
+ { "MA_Dynamic_CGEN", 25, 1 },
+ { "Tagq_Dynamic_CGEN", 24, 1 },
+ { "ReqCtl_Dynamic_CGEN", 23, 1 },
+ { "RspDataProc_Dynamic_CGEN", 22, 1 },
+ { "RspRdq_Dynamic_CGEN", 21, 1 },
+ { "RspIPif_Dynamic_CGEN", 20, 1 },
+ { "HMA_Static_CGEN", 19, 1 },
+ { "HMA_Dynamic_CGEN", 18, 1 },
+ { "CMD_Static_CGEN", 16, 1 },
+ { "CMD_Dynamic_CGEN", 15, 1 },
+ { "DMA_Static_CGEN", 13, 1 },
+ { "DMA_Dynamic_CGEN", 12, 1 },
+ { "VFID_SleepStatus", 10, 1 },
+ { "VC1_SleepStatus", 9, 1 },
+ { "STI_SleepStatus", 8, 1 },
+ { "VFID_SleepReq", 2, 1 },
+ { "VC1_SleepReq", 1, 1 },
+ { "STI_SleepReq", 0, 1 },
+ { "PCIE_MA_RSP", 0x59c4, 0 },
+ { "TimerValue", 8, 24 },
+ { "MAReqTimerEn", 1, 1 },
+ { "TimerEn", 0, 1 },
+ { "PCIE_HPRD", 0x59c8, 0 },
+ { "NPH_CreditsAvailVC0", 19, 2 },
+ { "NPD_CreditsAvailVC0", 17, 2 },
+ { "NPH_CreditsAvailVC1", 15, 2 },
+ { "NPD_CreditsAvailVC1", 13, 2 },
+ { "NPH_CreditsRequired", 11, 2 },
+ { "NPD_CreditsRequired", 9, 2 },
+ { "ReqBurstCount", 5, 4 },
+ { "ReqBurstFrequency", 1, 4 },
+ { "EnableVC1", 0, 1 },
+ { "PCIE_PERR_GROUP", 0x59d0, 0 },
+ { "MST_DataPathPerr", 25, 1 },
+ { "MST_RspRdQPerr", 24, 1 },
+ { "IP_RxPerr", 23, 1 },
+ { "IP_BackTxPerr", 22, 1 },
+ { "IP_FrontTxPerr", 21, 1 },
+ { "TRGT1_FIDLkUpHdrPerr", 20, 1 },
+ { "TRGT1_AlindDataPerr", 19, 1 },
+ { "TRGT1_UnAlinDataPerr", 18, 1 },
+ { "TRGT1_ReqDataPerr", 17, 1 },
+ { "TRGT1_ReqHdrPerr", 16, 1 },
+ { "IPRxData_VC1Perr", 15, 1 },
+ { "IPRxData_VC0Perr", 14, 1 },
+ { "IPRxHdr_VC1Perr", 13, 1 },
+ { "IPRxHdr_VC0Perr", 12, 1 },
+ { "MA_RspDataPerr", 11, 1 },
+ { "MA_CplTagQPerr", 10, 1 },
+ { "MA_ReqTagQPerr", 9, 1 },
+ { "PIOReq_BAR2CtlPerr", 8, 1 },
+ { "PIOReq_MEMCtlPerr", 7, 1 },
+ { "PIOReq_PLMCtlPerr", 6, 1 },
+ { "PIOReq_BAR2DataPerr", 5, 1 },
+ { "PIOReq_MEMDataPerr", 4, 1 },
+ { "PIOReq_PLMDataPerr", 3, 1 },
+ { "PIOCpl_CtlPerr", 2, 1 },
+ { "PIOCpl_DataPerr", 1, 1 },
+ { "PIOCpl_PLMRspPerr", 0, 1 },
+ { "PCIE_RSP_ERR_INT_LOG_EN", 0x59d4, 0 },
+ { "CplStatusIntEn", 12, 1 },
+ { "TimeoutIntEn", 11, 1 },
+ { "DisabledIntEn", 10, 1 },
+ { "RspDropFLRIntEn", 9, 1 },
+ { "ReqUnderFLRIntEn", 8, 1 },
+ { "CplStatusLogEn", 4, 1 },
+ { "TimeoutLogEn", 3, 1 },
+ { "DisabledLogEn", 2, 1 },
+ { "RspDropFLRLogEn", 1, 1 },
+ { "ReqUnderFLRLogEn", 0, 1 },
+ { "PCIE_RSP_ERR_LOG1", 0x59d8, 0 },
+ { "Tag", 25, 7 },
+ { "CID", 22, 3 },
+ { "ChNum", 19, 3 },
+ { "ByteLen", 6, 13 },
+ { "Reason", 3, 3 },
+ { "CplStatus", 0, 3 },
+ { "PCIE_RSP_ERR_LOG2", 0x59dc, 0 },
+ { "Valid", 31, 1 },
+ { "Addr10b", 8, 10 },
+ { "VFID", 0, 8 },
+ { "PCIE_REVISION", 0x5a00, 0 },
+ { "PCIE_PDEBUG_INDEX", 0x5a04, 0 },
+ { "PDEBUGSelH", 16, 6 },
+ { "PDEBUGSelL", 0, 6 },
+ { "PCIE_PDEBUG_DATA_HIGH", 0x5a08, 0 },
+ { "PCIE_PDEBUG_DATA_LOW", 0x5a0c, 0 },
+ { "PCIE_CDEBUG_INDEX", 0x5a10, 0 },
+ { "CDEBUGSelH", 16, 8 },
+ { "CDEBUGSelL", 0, 8 },
+ { "PCIE_CDEBUG_DATA_HIGH", 0x5a14, 0 },
+ { "PCIE_CDEBUG_DATA_LOW", 0x5a18, 0 },
+ { "PCIE_BUS_MST_STAT_0", 0x5a60, 0 },
+ { "PCIE_BUS_MST_STAT_1", 0x5a64, 0 },
+ { "PCIE_BUS_MST_STAT_2", 0x5a68, 0 },
+ { "PCIE_BUS_MST_STAT_3", 0x5a6c, 0 },
+ { "PCIE_BUS_MST_STAT_4", 0x5a70, 0 },
+ { "PCIE_RSP_ERR_STAT_0", 0x5a80, 0 },
+ { "PCIE_RSP_ERR_STAT_1", 0x5a84, 0 },
+ { "PCIE_RSP_ERR_STAT_2", 0x5a88, 0 },
+ { "PCIE_RSP_ERR_STAT_3", 0x5a8c, 0 },
+ { "PCIE_RSP_ERR_STAT_4", 0x5a90, 0 },
+ { "PCIE_DBI_TIMEOUT_CTL", 0x5a94, 0 },
+ { "PCIE_DBI_TIMEOUT_STATUS0", 0x5a98, 0 },
+ { "PCIE_DBI_TIMEOUT_STATUS1", 0x5a9c, 0 },
+ { "Valid", 31, 1 },
+ { "Source", 16, 2 },
+ { "Write", 12, 4 },
+ { "CS2", 11, 1 },
+ { "PF", 8, 3 },
+ { "VFVld", 7, 1 },
+ { "VF", 0, 7 },
+ { "PCIE_PB_CTL", 0x5b94, 0 },
+ { "PB_Sel", 16, 8 },
+ { "PB_SelReg", 8, 8 },
+ { "PB_Func", 0, 3 },
+ { "PCIE_PB_DATA", 0x5b98, 0 },
+ { "PCIE_CHANGESET", 0x59fc, 0 },
+ { "PCIE_CUR_LINK", 0x5b9c, 0 },
+ { "CfgInitCoeffDoneSeen", 22, 1 },
+ { "CfgInitCoeffDone", 21, 1 },
+ { "xmlh_link_up", 20, 1 },
+ { "pm_linkst_in_l0s", 19, 1 },
+ { "pm_linkst_in_l1", 18, 1 },
+ { "pm_linkst_in_l2", 17, 1 },
+ { "pm_linkst_l2_exit", 16, 1 },
+ { "xmlh_in_rl0s", 15, 1 },
+ { "xmlh_ltssm_state_rcvry_eq", 14, 1 },
+ { "NegotiatedWidth", 8, 6 },
+ { "ActiveLanes", 0, 8 },
+ { "PCIE_PHY_REQRXPWR", 0x5ba0, 0 },
+ { "LnH_RxStateDone", 31, 1 },
+ { "LnH_RxStateReq", 30, 1 },
+ { "LnH_RxPwrState", 28, 2 },
+ { "LnG_RxStateDone", 27, 1 },
+ { "LnG_RxStateReq", 26, 1 },
+ { "LnG_RxPwrState", 24, 2 },
+ { "LnF_RxStateDone", 23, 1 },
+ { "LnF_RxStateReq", 22, 1 },
+ { "LnF_RxPwrState", 20, 2 },
+ { "LnE_RxStateDone", 19, 1 },
+ { "LnE_RxStateReq", 18, 1 },
+ { "LnE_RxPwrState", 16, 2 },
+ { "LnD_RxStateDone", 15, 1 },
+ { "LnD_RxStateReq", 14, 1 },
+ { "LnD_RxPwrState", 12, 2 },
+ { "LnC_RxStateDone", 11, 1 },
+ { "LnC_RxStateReq", 10, 1 },
+ { "LnC_RxPwrState", 8, 2 },
+ { "LnB_RxStateDone", 7, 1 },
+ { "LnB_RxStateReq", 6, 1 },
+ { "LnB_RxPwrState", 4, 2 },
+ { "LnA_RxStateDone", 3, 1 },
+ { "LnA_RxStateReq", 2, 1 },
+ { "LnA_RxPwrState", 0, 2 },
+ { "PCIE_PHY_CURRXPWR", 0x5ba4, 0 },
+ { "LnH_RxPwrState", 28, 3 },
+ { "LnG_RxPwrState", 24, 3 },
+ { "LnF_RxPwrState", 20, 3 },
+ { "LnE_RxPwrState", 16, 3 },
+ { "LnD_RxPwrState", 12, 3 },
+ { "LnC_RxPwrState", 8, 3 },
+ { "LnB_RxPwrState", 4, 3 },
+ { "LnA_RxPwrState", 0, 3 },
+ { "PCIE_PHY_GEN3_AE0", 0x5ba8, 0 },
+ { "LnD_STAT", 28, 3 },
+ { "LnD_CMD", 24, 3 },
+ { "LnC_STAT", 20, 3 },
+ { "LnC_CMD", 16, 3 },
+ { "LnB_STAT", 12, 3 },
+ { "LnB_CMD", 8, 3 },
+ { "LnA_STAT", 4, 3 },
+ { "LnA_CMD", 0, 3 },
+ { "PCIE_PHY_GEN3_AE1", 0x5bac, 0 },
+ { "LnH_STAT", 28, 3 },
+ { "LnH_CMD", 24, 3 },
+ { "LnG_STAT", 20, 3 },
+ { "LnG_CMD", 16, 3 },
+ { "LnF_STAT", 12, 3 },
+ { "LnF_CMD", 8, 3 },
+ { "LnE_STAT", 4, 3 },
+ { "LnE_CMD", 0, 3 },
+ { "PCIE_PHY_FS_LF0", 0x5bb0, 0 },
+ { "Lane1LF", 24, 6 },
+ { "Lane1FS", 16, 6 },
+ { "Lane0LF", 8, 6 },
+ { "Lane0FS", 0, 6 },
+ { "PCIE_PHY_FS_LF1", 0x5bb4, 0 },
+ { "Lane3LF", 24, 6 },
+ { "Lane3FS", 16, 6 },
+ { "Lane2LF", 8, 6 },
+ { "Lane2FS", 0, 6 },
+ { "PCIE_PHY_FS_LF2", 0x5bb8, 0 },
+ { "Lane5LF", 24, 6 },
+ { "Lane5FS", 16, 6 },
+ { "Lane4LF", 8, 6 },
+ { "Lane4FS", 0, 6 },
+ { "PCIE_PHY_FS_LF3", 0x5bbc, 0 },
+ { "Lane7LF", 24, 6 },
+ { "Lane7FS", 16, 6 },
+ { "Lane6LF", 8, 6 },
+ { "Lane6FS", 0, 6 },
+ { "PCIE_PHY_PRESET_REQ", 0x5bc0, 0 },
+ { "CoeffDone", 16, 1 },
+ { "CoeffLane", 8, 3 },
+ { "CoeffStart", 0, 1 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bc4, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bc8, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bcc, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bd0, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bd4, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bd8, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bdc, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5be0, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5be4, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5be8, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bec, 0 },
+ { "PCIE_PHY_INDIR_REQ", 0x5bf0, 0 },
+ { "Enable", 31, 1 },
+ { "RegAddr", 0, 16 },
+ { "PCIE_PHY_INDIR_DATA", 0x5bf4, 0 },
+ { "PCIE_STATIC_SPARE1", 0x5bf8, 0 },
+ { "PCIE_STATIC_SPARE2", 0x5bfc, 0 },
+ { NULL }
+};
+
+struct reg_info t5_dbg_regs[] = {
+ { "DBG_DBG0_CFG", 0x6000, 0 },
+ { "ModuleSelect", 12, 8 },
+ { "RegSelect", 4, 8 },
+ { "ClkSelect", 0, 4 },
+ { "DBG_DBG0_EN", 0x6004, 0 },
+ { "SDRHalfWord0", 8, 1 },
+ { "DDREn", 4, 1 },
+ { "PortEn", 0, 1 },
+ { "DBG_DBG1_CFG", 0x6008, 0 },
+ { "ModuleSelect", 12, 8 },
+ { "RegSelect", 4, 8 },
+ { "ClkSelect", 0, 4 },
+ { "DBG_DBG1_EN", 0x600c, 0 },
+ { "Clk_en_on_dbg1", 20, 1 },
+ { "SDRHalfWord0", 8, 1 },
+ { "DDREn", 4, 1 },
+ { "PortEn", 0, 1 },
+ { "DBG_GPIO_EN", 0x6010, 0 },
+ { "GPIO15_OEn", 31, 1 },
+ { "GPIO14_OEn", 30, 1 },
+ { "GPIO13_OEn", 29, 1 },
+ { "GPIO12_OEn", 28, 1 },
+ { "GPIO11_OEn", 27, 1 },
+ { "GPIO10_OEn", 26, 1 },
+ { "GPIO9_OEn", 25, 1 },
+ { "GPIO8_OEn", 24, 1 },
+ { "GPIO7_OEn", 23, 1 },
+ { "GPIO6_OEn", 22, 1 },
+ { "GPIO5_OEn", 21, 1 },
+ { "GPIO4_OEn", 20, 1 },
+ { "GPIO3_OEn", 19, 1 },
+ { "GPIO2_OEn", 18, 1 },
+ { "GPIO1_OEn", 17, 1 },
+ { "GPIO0_OEn", 16, 1 },
+ { "GPIO15_Out_Val", 15, 1 },
+ { "GPIO14_Out_Val", 14, 1 },
+ { "GPIO13_Out_Val", 13, 1 },
+ { "GPIO12_Out_Val", 12, 1 },
+ { "GPIO11_Out_Val", 11, 1 },
+ { "GPIO10_Out_Val", 10, 1 },
+ { "GPIO9_Out_Val", 9, 1 },
+ { "GPIO8_Out_Val", 8, 1 },
+ { "GPIO7_Out_Val", 7, 1 },
+ { "GPIO6_Out_Val", 6, 1 },
+ { "GPIO5_Out_Val", 5, 1 },
+ { "GPIO4_Out_Val", 4, 1 },
+ { "GPIO3_Out_Val", 3, 1 },
+ { "GPIO2_Out_Val", 2, 1 },
+ { "GPIO1_Out_Val", 1, 1 },
+ { "GPIO0_Out_Val", 0, 1 },
+ { "DBG_GPIO_IN", 0x6014, 0 },
+ { "GPIO15_CHG_DET", 31, 1 },
+ { "GPIO14_CHG_DET", 30, 1 },
+ { "GPIO13_CHG_DET", 29, 1 },
+ { "GPIO12_CHG_DET", 28, 1 },
+ { "GPIO11_CHG_DET", 27, 1 },
+ { "GPIO10_CHG_DET", 26, 1 },
+ { "GPIO9_CHG_DET", 25, 1 },
+ { "GPIO8_CHG_DET", 24, 1 },
+ { "GPIO7_CHG_DET", 23, 1 },
+ { "GPIO6_CHG_DET", 22, 1 },
+ { "GPIO5_CHG_DET", 21, 1 },
+ { "GPIO4_CHG_DET", 20, 1 },
+ { "GPIO3_CHG_DET", 19, 1 },
+ { "GPIO2_CHG_DET", 18, 1 },
+ { "GPIO1_CHG_DET", 17, 1 },
+ { "GPIO0_CHG_DET", 16, 1 },
+ { "GPIO15_IN", 15, 1 },
+ { "GPIO14_IN", 14, 1 },
+ { "GPIO13_IN", 13, 1 },
+ { "GPIO12_IN", 12, 1 },
+ { "GPIO11_IN", 11, 1 },
+ { "GPIO10_IN", 10, 1 },
+ { "GPIO9_IN", 9, 1 },
+ { "GPIO8_IN", 8, 1 },
+ { "GPIO7_IN", 7, 1 },
+ { "GPIO6_IN", 6, 1 },
+ { "GPIO5_IN", 5, 1 },
+ { "GPIO4_IN", 4, 1 },
+ { "GPIO3_IN", 3, 1 },
+ { "GPIO2_IN", 2, 1 },
+ { "GPIO1_IN", 1, 1 },
+ { "GPIO0_IN", 0, 1 },
+ { "DBG_GPIO_EN_NEW", 0x6100, 0 },
+ { "GPIO16_OEn", 7, 1 },
+ { "GPIO17_OEn", 6, 1 },
+ { "GPIO18_OEn", 5, 1 },
+ { "GPIO19_OEn", 4, 1 },
+ { "GPIO16_Out_Val", 3, 1 },
+ { "GPIO17_Out_Val", 2, 1 },
+ { "GPIO18_Out_Val", 1, 1 },
+ { "GPIO19_Out_Val", 0, 1 },
+ { "DBG_GPIO_IN_NEW", 0x6104, 0 },
+ { "GPIO16_CHG_DET", 7, 1 },
+ { "GPIO17_CHG_DET", 6, 1 },
+ { "GPIO18_CHG_DET", 5, 1 },
+ { "GPIO19_CHG_DET", 4, 1 },
+ { "GPIO19_IN", 3, 1 },
+ { "GPIO18_IN", 2, 1 },
+ { "GPIO17_IN", 1, 1 },
+ { "GPIO16_IN", 0, 1 },
+ { "DBG_INT_ENABLE", 0x6018, 0 },
+ { "GPIO19", 29, 1 },
+ { "GPIO18", 28, 1 },
+ { "GPIO17", 27, 1 },
+ { "GPIO16", 26, 1 },
+ { "IBM_FDL_FAIL_int_enbl", 25, 1 },
+ { "pll_lock_lost_int_enbl", 22, 1 },
+ { "C_LOCK", 21, 1 },
+ { "M_LOCK", 20, 1 },
+ { "U_LOCK", 19, 1 },
+ { "PCIe_LOCK", 18, 1 },
+ { "KX_LOCK", 17, 1 },
+ { "KR_LOCK", 16, 1 },
+ { "GPIO15", 15, 1 },
+ { "GPIO14", 14, 1 },
+ { "GPIO13", 13, 1 },
+ { "GPIO12", 12, 1 },
+ { "GPIO11", 11, 1 },
+ { "GPIO10", 10, 1 },
+ { "GPIO9", 9, 1 },
+ { "GPIO8", 8, 1 },
+ { "GPIO7", 7, 1 },
+ { "GPIO6", 6, 1 },
+ { "GPIO5", 5, 1 },
+ { "GPIO4", 4, 1 },
+ { "GPIO3", 3, 1 },
+ { "GPIO2", 2, 1 },
+ { "GPIO1", 1, 1 },
+ { "GPIO0", 0, 1 },
+ { "DBG_INT_CAUSE", 0x601c, 0 },
+ { "GPIO19", 29, 1 },
+ { "GPIO18", 28, 1 },
+ { "GPIO17", 27, 1 },
+ { "GPIO16", 26, 1 },
+ { "IBM_FDL_FAIL_int_cause", 25, 1 },
+ { "pll_lock_lost_int_cause", 22, 1 },
+ { "C_LOCK", 21, 1 },
+ { "M_LOCK", 20, 1 },
+ { "U_LOCK", 19, 1 },
+ { "PCIe_LOCK", 18, 1 },
+ { "KX_LOCK", 17, 1 },
+ { "KR_LOCK", 16, 1 },
+ { "GPIO15", 15, 1 },
+ { "GPIO14", 14, 1 },
+ { "GPIO13", 13, 1 },
+ { "GPIO12", 12, 1 },
+ { "GPIO11", 11, 1 },
+ { "GPIO10", 10, 1 },
+ { "GPIO9", 9, 1 },
+ { "GPIO8", 8, 1 },
+ { "GPIO7", 7, 1 },
+ { "GPIO6", 6, 1 },
+ { "GPIO5", 5, 1 },
+ { "GPIO4", 4, 1 },
+ { "GPIO3", 3, 1 },
+ { "GPIO2", 2, 1 },
+ { "GPIO1", 1, 1 },
+ { "GPIO0", 0, 1 },
+ { "DBG_DBG0_RST_VALUE", 0x6020, 0 },
+ { "DBG_PLL_OCLK_PAD_EN", 0x6028, 0 },
+ { "PCIE_OCLK_En", 20, 1 },
+ { "KX_OCLK_En", 16, 1 },
+ { "U_OCLK_En", 12, 1 },
+ { "KR_OCLK_En", 8, 1 },
+ { "M_OCLK_En", 4, 1 },
+ { "C_OCLK_En", 0, 1 },
+ { "DBG_PLL_LOCK", 0x602c, 0 },
+ { "P_LOCK", 20, 1 },
+ { "KX_LOCK", 16, 1 },
+ { "U_LOCK", 12, 1 },
+ { "KR_LOCK", 8, 1 },
+ { "M_LOCK", 4, 1 },
+ { "C_LOCK", 0, 1 },
+ { "DBG_GPIO_ACT_LOW", 0x6030, 0 },
+ { "GPIO19_ACT_LOW", 25, 1 },
+ { "GPIO18_ACT_LOW", 24, 1 },
+ { "GPIO17_ACT_LOW", 23, 1 },
+ { "GPIO16_ACT_LOW", 22, 1 },
+ { "P_LOCK_ACT_LOW", 21, 1 },
+ { "C_LOCK_ACT_LOW", 20, 1 },
+ { "M_LOCK_ACT_LOW", 19, 1 },
+ { "U_LOCK_ACT_LOW", 18, 1 },
+ { "KR_LOCK_ACT_LOW", 17, 1 },
+ { "KX_LOCK_ACT_LOW", 16, 1 },
+ { "GPIO15_ACT_LOW", 15, 1 },
+ { "GPIO14_ACT_LOW", 14, 1 },
+ { "GPIO13_ACT_LOW", 13, 1 },
+ { "GPIO12_ACT_LOW", 12, 1 },
+ { "GPIO11_ACT_LOW", 11, 1 },
+ { "GPIO10_ACT_LOW", 10, 1 },
+ { "GPIO9_ACT_LOW", 9, 1 },
+ { "GPIO8_ACT_LOW", 8, 1 },
+ { "GPIO7_ACT_LOW", 7, 1 },
+ { "GPIO6_ACT_LOW", 6, 1 },
+ { "GPIO5_ACT_LOW", 5, 1 },
+ { "GPIO4_ACT_LOW", 4, 1 },
+ { "GPIO3_ACT_LOW", 3, 1 },
+ { "GPIO2_ACT_LOW", 2, 1 },
+ { "GPIO1_ACT_LOW", 1, 1 },
+ { "GPIO0_ACT_LOW", 0, 1 },
+ { "DBG_EFUSE_BYTE0_3", 0x6034, 0 },
+ { "DBG_EFUSE_BYTE4_7", 0x6038, 0 },
+ { "DBG_EFUSE_BYTE8_11", 0x603c, 0 },
+ { "DBG_EFUSE_BYTE12_15", 0x6040, 0 },
+ { "DBG_EXTRA_STATIC_BITS_CONF", 0x6058, 0 },
+ { "STATIC_M_PLL_RESET", 30, 1 },
+ { "STATIC_M_PLL_SLEEP", 29, 1 },
+ { "STATIC_M_PLL_BYPASS", 28, 1 },
+ { "STATIC_MPLL_CLK_SEL", 27, 1 },
+ { "STATIC_U_PLL_SLEEP", 26, 1 },
+ { "STATIC_C_PLL_SLEEP", 25, 1 },
+ { "STATIC_LVDS_CLKOUT_SEL", 23, 2 },
+ { "STATIC_LVDS_CLKOUT_EN", 22, 1 },
+ { "STATIC_CCLK_FREQ_SEL", 20, 2 },
+ { "STATIC_UCLK_FREQ_SEL", 18, 2 },
+ { "ExPHYClk_sel_en", 17, 1 },
+ { "ExPHYClk_sel", 15, 2 },
+ { "STATIC_U_PLL_BYPASS", 14, 1 },
+ { "STATIC_C_PLL_BYPASS", 13, 1 },
+ { "STATIC_KR_PLL_BYPASS", 12, 1 },
+ { "STATIC_KX_PLL_BYPASS", 11, 1 },
+ { "STATIC_KX_PLL_V", 7, 4 },
+ { "STATIC_KR_PLL_V", 3, 4 },
+ { "DBG_STATIC_OCLK_MUXSEL_CONF", 0x605c, 0 },
+ { "T5_P_OCLK_MUXSEL", 13, 4 },
+ { "M_OCLK_MUXSEL", 12, 1 },
+ { "C_OCLK_MUXSEL", 10, 2 },
+ { "U_OCLK_MUXSEL", 8, 2 },
+ { "P_OCLK_MUXSEL", 6, 2 },
+ { "KX_OCLK_MUXSEL", 3, 3 },
+ { "KR_OCLK_MUXSEL", 0, 3 },
+ { "DBG_TRACE0_CONF_COMPREG0", 0x6060, 0 },
+ { "DBG_TRACE0_CONF_COMPREG1", 0x6064, 0 },
+ { "DBG_TRACE1_CONF_COMPREG0", 0x6068, 0 },
+ { "DBG_TRACE1_CONF_COMPREG1", 0x606c, 0 },
+ { "DBG_TRACE0_CONF_MASKREG0", 0x6070, 0 },
+ { "DBG_TRACE0_CONF_MASKREG1", 0x6074, 0 },
+ { "DBG_TRACE1_CONF_MASKREG0", 0x6078, 0 },
+ { "DBG_TRACE1_CONF_MASKREG1", 0x607c, 0 },
+ { "DBG_TRACE_COUNTER", 0x6080, 0 },
+ { "Counter1", 16, 16 },
+ { "Counter0", 0, 16 },
+ { "DBG_STATIC_REFCLK_PERIOD", 0x6084, 0 },
+ { "DBG_TRACE_CONF", 0x6088, 0 },
+ { "dbg_trace_operate_with_trg", 5, 1 },
+ { "dbg_trace_operate_en", 4, 1 },
+ { "dbg_operate_indv_combined", 3, 1 },
+ { "dbg_operate_order_of_trigger", 2, 1 },
+ { "dbg_operate_sgl_dbl_trigger", 1, 1 },
+ { "dbg_operate0_or_1", 0, 1 },
+ { "DBG_TRACE_RDEN", 0x608c, 0 },
+ { "RD_ADDR1", 11, 9 },
+ { "RD_ADDR0", 2, 9 },
+ { "Rd_en1", 1, 1 },
+ { "Rd_en0", 0, 1 },
+ { "DBG_TRACE_WRADDR", 0x6090, 0 },
+ { "Wr_pointer_addr1", 16, 9 },
+ { "Wr_pointer_addr0", 0, 9 },
+ { "DBG_TRACE0_DATA_OUT", 0x6094, 0 },
+ { "DBG_TRACE1_DATA_OUT", 0x6098, 0 },
+ { "DBG_FUSE_SENSE_DONE", 0x609c, 0 },
+ { "STATIC_JTAG_VersionNr", 5, 4 },
+ { "PSRO_sel", 1, 4 },
+ { "FUSE_DONE_SENSE", 0, 1 },
+ { "DBG_TVSENSE_EN", 0x60a8, 0 },
+ { "MCIMPED1_out", 29, 1 },
+ { "MCIMPED2_out", 28, 1 },
+ { "TVSENSE_SNSOUT", 17, 9 },
+ { "TVSENSE_OUTPUTVALID", 16, 1 },
+ { "TVSENSE_SLEEP", 10, 1 },
+ { "TVSENSE_SENSV", 9, 1 },
+ { "TVSENSE_RST", 8, 1 },
+ { "TVSENSE_RATIO", 0, 8 },
+ { "DBG_CUST_EFUSE_OUT_EN", 0x60ac, 0 },
+ { "DBG_CUST_EFUSE_SEL1_EN", 0x60b0, 0 },
+ { "DBG_CUST_EFUSE_SEL2_EN", 0x60b4, 0 },
+ { "DBG_FEENABLE", 29, 1 },
+ { "DBG_FEF", 23, 6 },
+ { "DBG_FEMIMICN", 22, 1 },
+ { "DBG_FEGATEC", 21, 1 },
+ { "DBG_FEPROGP", 20, 1 },
+ { "DBG_FEREADCLK", 19, 1 },
+ { "DBG_FERSEL", 3, 16 },
+ { "DBG_FETIME", 0, 3 },
+ { "DBG_T5_STATIC_M_PLL_CONF1", 0x60b8, 0 },
+ { "T5_STATIC_M_PLL_MULTFRAC", 8, 24 },
+ { "T5_STATIC_M_PLL_FFSLEWRATE", 0, 8 },
+ { "DBG_T5_STATIC_M_PLL_CONF2", 0x60bc, 0 },
+ { "T5_STATIC_M_PLL_DCO_BYPASS", 23, 1 },
+ { "T5_STATIC_M_PLL_SDORDER", 21, 2 },
+ { "T5_STATIC_M_PLL_FFENABLE", 20, 1 },
+ { "T5_STATIC_M_PLL_STOPCLKB", 19, 1 },
+ { "T5_STATIC_M_PLL_STOPCLKA", 18, 1 },
+ { "T5_STATIC_M_PLL_SLEEP", 17, 1 },
+ { "T5_STATIC_M_PLL_BYPASS", 16, 1 },
+ { "T5_STATIC_M_PLL_LOCKTUNE", 0, 16 },
+ { "DBG_T5_STATIC_M_PLL_CONF3", 0x60c0, 0 },
+ { "T5_STATIC_M_PLL_MULTPRE", 30, 2 },
+ { "T5_STATIC_M_PLL_LOCKSEL", 28, 2 },
+ { "T5_STATIC_M_PLL_FFTUNE", 12, 16 },
+ { "T5_STATIC_M_PLL_RANGEPRE", 10, 2 },
+ { "T5_STATIC_M_PLL_RANGEB", 5, 5 },
+ { "T5_STATIC_M_PLL_RANGEA", 0, 5 },
+ { "DBG_T5_STATIC_M_PLL_CONF4", 0x60c4, 0 },
+ { "DBG_T5_STATIC_M_PLL_CONF5", 0x60c8, 0 },
+ { "T5_STATIC_M_PLL_VCVTUNE", 24, 3 },
+ { "T5_STATIC_M_PLL_RESET", 23, 1 },
+ { "T5_STATIC_MPLL_REFCLK_SEL", 22, 1 },
+ { "T5_STATIC_M_PLL_LFTUNE_32_40", 13, 9 },
+ { "T5_STATIC_M_PLL_PREDIV", 8, 5 },
+ { "T5_STATIC_M_PLL_MULT", 0, 8 },
+ { "DBG_T5_STATIC_M_PLL_CONF6", 0x60cc, 0 },
+ { "T5_STATIC_PHY0RecRst_", 5, 1 },
+ { "T5_STATIC_PHY1RecRst_", 4, 1 },
+ { "T5_STATIC_SWMC0Rst_", 3, 1 },
+ { "T5_STATIC_SWMC0CfgRst_", 2, 1 },
+ { "T5_STATIC_SWMC1Rst_", 1, 1 },
+ { "T5_STATIC_SWMC1CfgRst_", 0, 1 },
+ { "DBG_T5_STATIC_C_PLL_CONF1", 0x60d0, 0 },
+ { "T5_STATIC_C_PLL_MULTFRAC", 8, 24 },
+ { "T5_STATIC_C_PLL_FFSLEWRATE", 0, 8 },
+ { "DBG_T5_STATIC_C_PLL_CONF2", 0x60d4, 0 },
+ { "T5_STATIC_C_PLL_DCO_BYPASS", 23, 1 },
+ { "T5_STATIC_C_PLL_SDORDER", 21, 2 },
+ { "T5_STATIC_C_PLL_FFENABLE", 20, 1 },
+ { "T5_STATIC_C_PLL_STOPCLKB", 19, 1 },
+ { "T5_STATIC_C_PLL_STOPCLKA", 18, 1 },
+ { "T5_STATIC_C_PLL_SLEEP", 17, 1 },
+ { "T5_STATIC_C_PLL_BYPASS", 16, 1 },
+ { "T5_STATIC_C_PLL_LOCKTUNE", 0, 16 },
+ { "DBG_T5_STATIC_C_PLL_CONF3", 0x60d8, 0 },
+ { "T5_STATIC_C_PLL_MULTPRE", 30, 2 },
+ { "T5_STATIC_C_PLL_LOCKSEL", 28, 2 },
+ { "T5_STATIC_C_PLL_FFTUNE", 12, 16 },
+ { "T5_STATIC_C_PLL_RANGEPRE", 10, 2 },
+ { "T5_STATIC_C_PLL_RANGEB", 5, 5 },
+ { "T5_STATIC_C_PLL_RANGEA", 0, 5 },
+ { "DBG_T5_STATIC_C_PLL_CONF4", 0x60dc, 0 },
+ { "DBG_T5_STATIC_C_PLL_CONF5", 0x60e0, 0 },
+ { "T5_STATIC_C_PLL_VCVTUNE", 22, 3 },
+ { "T5_STATIC_C_PLL_LFTUNE_32_40", 13, 9 },
+ { "T5_STATIC_C_PLL_PREDIV", 8, 5 },
+ { "T5_STATIC_C_PLL_MULT", 0, 8 },
+ { "DBG_T5_STATIC_U_PLL_CONF1", 0x60e4, 0 },
+ { "T5_STATIC_U_PLL_MULTFRAC", 8, 24 },
+ { "T5_STATIC_U_PLL_FFSLEWRATE", 0, 8 },
+ { "DBG_T5_STATIC_U_PLL_CONF2", 0x60e8, 0 },
+ { "T5_STATIC_U_PLL_DCO_BYPASS", 23, 1 },
+ { "T5_STATIC_U_PLL_SDORDER", 21, 2 },
+ { "T5_STATIC_U_PLL_FFENABLE", 20, 1 },
+ { "T5_STATIC_U_PLL_STOPCLKB", 19, 1 },
+ { "T5_STATIC_U_PLL_STOPCLKA", 18, 1 },
+ { "T5_STATIC_U_PLL_SLEEP", 17, 1 },
+ { "T5_STATIC_U_PLL_BYPASS", 16, 1 },
+ { "T5_STATIC_U_PLL_LOCKTUNE", 0, 16 },
+ { "DBG_T5_STATIC_U_PLL_CONF3", 0x60ec, 0 },
+ { "T5_STATIC_U_PLL_MULTPRE", 30, 2 },
+ { "T5_STATIC_U_PLL_LOCKSEL", 28, 2 },
+ { "T5_STATIC_U_PLL_FFTUNE", 12, 16 },
+ { "T5_STATIC_U_PLL_RANGEPRE", 10, 2 },
+ { "T5_STATIC_U_PLL_RANGEB", 5, 5 },
+ { "T5_STATIC_U_PLL_RANGEA", 0, 5 },
+ { "DBG_T5_STATIC_U_PLL_CONF4", 0x60f0, 0 },
+ { "DBG_T5_STATIC_U_PLL_CONF5", 0x60f4, 0 },
+ { "T5_STATIC_U_PLL_VCVTUNE", 22, 3 },
+ { "T5_STATIC_U_PLL_LFTUNE_32_40", 13, 9 },
+ { "T5_STATIC_U_PLL_PREDIV", 8, 5 },
+ { "T5_STATIC_U_PLL_MULT", 0, 8 },
+ { "DBG_T5_STATIC_KR_PLL_CONF1", 0x60f8, 0 },
+ { "T5_STATIC_KR_PLL_BYPASS", 30, 1 },
+ { "T5_STATIC_KR_PLL_VBOOSTDIV", 27, 3 },
+ { "T5_STATIC_KR_PLL_CPISEL", 24, 3 },
+ { "T5_STATIC_KR_PLL_CCALMETHOD", 23, 1 },
+ { "T5_STATIC_KR_PLL_CCALLOAD", 22, 1 },
+ { "T5_STATIC_KR_PLL_CCALFMIN", 21, 1 },
+ { "T5_STATIC_KR_PLL_CCALFMAX", 20, 1 },
+ { "T5_STATIC_KR_PLL_CCALCVHOLD", 19, 1 },
+ { "T5_STATIC_KR_PLL_CCALBANDSEL", 15, 4 },
+ { "T5_STATIC_KR_PLL_BGOFFSET", 11, 4 },
+ { "T5_STATIC_KR_PLL_P", 8, 3 },
+ { "T5_STATIC_KR_PLL_N2", 4, 4 },
+ { "T5_STATIC_KR_PLL_N1", 0, 4 },
+ { "DBG_T5_STATIC_KR_PLL_CONF2", 0x60fc, 0 },
+ { "T5_STATIC_KR_PLL_M", 11, 9 },
+ { "T5_STATIC_KR_PLL_ANALOGTUNE", 0, 11 },
+ { "DBG_T5_STATIC_KX_PLL_CONF1", 0x6108, 0 },
+ { "T5_STATIC_KX_PLL_BYPASS", 30, 1 },
+ { "T5_STATIC_KX_PLL_VBOOSTDIV", 27, 3 },
+ { "T5_STATIC_KX_PLL_CPISEL", 24, 3 },
+ { "T5_STATIC_KX_PLL_CCALMETHOD", 23, 1 },
+ { "T5_STATIC_KX_PLL_CCALLOAD", 22, 1 },
+ { "T5_STATIC_KX_PLL_CCALFMIN", 21, 1 },
+ { "T5_STATIC_KX_PLL_CCALFMAX", 20, 1 },
+ { "T5_STATIC_KX_PLL_CCALCVHOLD", 19, 1 },
+ { "T5_STATIC_KX_PLL_CCALBANDSEL", 15, 4 },
+ { "T5_STATIC_KX_PLL_BGOFFSET", 11, 4 },
+ { "T5_STATIC_KX_PLL_P", 8, 3 },
+ { "T5_STATIC_KX_PLL_N2", 4, 4 },
+ { "T5_STATIC_KX_PLL_N1", 0, 4 },
+ { "DBG_T5_STATIC_KX_PLL_CONF2", 0x610c, 0 },
+ { "T5_STATIC_KX_PLL_M", 11, 9 },
+ { "T5_STATIC_KX_PLL_ANALOGTUNE", 0, 11 },
+ { "DBG_T5_STATIC_C_DFS_CONF", 0x6110, 0 },
+ { "STATIC_C_DFS_RANGEA", 8, 5 },
+ { "STATIC_C_DFS_RANGEB", 3, 5 },
+ { "STATIC_C_DFS_FFTUNE4", 2, 1 },
+ { "STATIC_C_DFS_FFTUNE5", 1, 1 },
+ { "STATIC_C_DFS_ENABLE", 0, 1 },
+ { "DBG_T5_STATIC_U_DFS_CONF", 0x6114, 0 },
+ { "STATIC_U_DFS_RANGEA", 8, 5 },
+ { "STATIC_U_DFS_RANGEB", 3, 5 },
+ { "STATIC_U_DFS_FFTUNE4", 2, 1 },
+ { "STATIC_U_DFS_FFTUNE5", 1, 1 },
+ { "STATIC_U_DFS_ENABLE", 0, 1 },
+ { "DBG_GPIO_PE_EN", 0x6118, 0 },
+ { "GPIO19_PE_En", 19, 1 },
+ { "GPIO18_PE_En", 18, 1 },
+ { "GPIO17_PE_En", 17, 1 },
+ { "GPIO16_PE_En", 16, 1 },
+ { "GPIO15_PE_En", 15, 1 },
+ { "GPIO14_PE_En", 14, 1 },
+ { "GPIO13_PE_En", 13, 1 },
+ { "GPIO12_PE_En", 12, 1 },
+ { "GPIO11_PE_En", 11, 1 },
+ { "GPIO10_PE_En", 10, 1 },
+ { "GPIO9_PE_En", 9, 1 },
+ { "GPIO8_PE_En", 8, 1 },
+ { "GPIO7_PE_En", 7, 1 },
+ { "GPIO6_PE_En", 6, 1 },
+ { "GPIO5_PE_En", 5, 1 },
+ { "GPIO4_PE_En", 4, 1 },
+ { "GPIO3_PE_En", 3, 1 },
+ { "GPIO2_PE_En", 2, 1 },
+ { "GPIO1_PE_En", 1, 1 },
+ { "GPIO0_PE_En", 0, 1 },
+ { "DBG_GPIO_PS_EN", 0x611c, 0 },
+ { "GPIO19_PS_En", 19, 1 },
+ { "GPIO18_PS_En", 18, 1 },
+ { "GPIO17_PS_En", 17, 1 },
+ { "GPIO16_PS_En", 16, 1 },
+ { "GPIO15_PS_En", 15, 1 },
+ { "GPIO14_PS_En", 14, 1 },
+ { "GPIO13_PS_En", 13, 1 },
+ { "GPIO12_PS_En", 12, 1 },
+ { "GPIO11_PS_En", 11, 1 },
+ { "GPIO10_PS_En", 10, 1 },
+ { "GPIO9_PS_En", 9, 1 },
+ { "GPIO8_PS_En", 8, 1 },
+ { "GPIO7_PS_En", 7, 1 },
+ { "GPIO6_PS_En", 6, 1 },
+ { "GPIO5_PS_En", 5, 1 },
+ { "GPIO4_PS_En", 4, 1 },
+ { "GPIO3_PS_En", 3, 1 },
+ { "GPIO2_PS_En", 2, 1 },
+ { "GPIO1_PS_En", 1, 1 },
+ { "GPIO0_PS_En", 0, 1 },
+ { "DBG_EFUSE_BYTE16_19", 0x6120, 0 },
+ { "DBG_EFUSE_BYTE20_23", 0x6124, 0 },
+ { "DBG_EFUSE_BYTE24_27", 0x6128, 0 },
+ { "DBG_EFUSE_BYTE28_31", 0x612c, 0 },
+ { "DBG_EFUSE_BYTE32_35", 0x6130, 0 },
+ { "DBG_EFUSE_BYTE36_39", 0x6134, 0 },
+ { "DBG_EFUSE_BYTE40_43", 0x6138, 0 },
+ { "DBG_EFUSE_BYTE44_47", 0x613c, 0 },
+ { "DBG_EFUSE_BYTE48_51", 0x6140, 0 },
+ { "DBG_EFUSE_BYTE52_55", 0x6144, 0 },
+ { "DBG_EFUSE_BYTE56_59", 0x6148, 0 },
+ { "DBG_EFUSE_BYTE60_63", 0x614c, 0 },
+ { NULL }
+};
+
+struct reg_info t5_ma_regs[] = {
+ { "MA_CLIENT0_RD_LATENCY_THRESHOLD", 0x7700, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT0_WR_LATENCY_THRESHOLD", 0x7704, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT1_RD_LATENCY_THRESHOLD", 0x7708, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT1_WR_LATENCY_THRESHOLD", 0x770c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT2_RD_LATENCY_THRESHOLD", 0x7710, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT2_WR_LATENCY_THRESHOLD", 0x7714, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT3_RD_LATENCY_THRESHOLD", 0x7718, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT3_WR_LATENCY_THRESHOLD", 0x771c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT4_RD_LATENCY_THRESHOLD", 0x7720, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT4_WR_LATENCY_THRESHOLD", 0x7724, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT5_RD_LATENCY_THRESHOLD", 0x7728, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT5_WR_LATENCY_THRESHOLD", 0x772c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT6_RD_LATENCY_THRESHOLD", 0x7730, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT6_WR_LATENCY_THRESHOLD", 0x7734, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT7_RD_LATENCY_THRESHOLD", 0x7738, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT7_WR_LATENCY_THRESHOLD", 0x773c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT8_RD_LATENCY_THRESHOLD", 0x7740, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT8_WR_LATENCY_THRESHOLD", 0x7744, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT9_RD_LATENCY_THRESHOLD", 0x7748, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT9_WR_LATENCY_THRESHOLD", 0x774c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT10_RD_LATENCY_THRESHOLD", 0x7750, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT10_WR_LATENCY_THRESHOLD", 0x7754, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT11_RD_LATENCY_THRESHOLD", 0x7758, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT11_WR_LATENCY_THRESHOLD", 0x775c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT12_RD_LATENCY_THRESHOLD", 0x7760, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT12_WR_LATENCY_THRESHOLD", 0x7764, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_SGE_TH0_DEBUG_CNT", 0x7768, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_SGE_TH1_DEBUG_CNT", 0x776c, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_ULPTX_DEBUG_CNT", 0x7770, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_ULPRX_DEBUG_CNT", 0x7774, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_ULPTXRX_DEBUG_CNT", 0x7778, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_TP_TH0_DEBUG_CNT", 0x777c, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_TP_TH1_DEBUG_CNT", 0x7780, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_LE_DEBUG_CNT", 0x7784, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_CIM_DEBUG_CNT", 0x7788, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_PCIE_DEBUG_CNT", 0x778c, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_PMTX_DEBUG_CNT", 0x7790, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_PMRX_DEBUG_CNT", 0x7794, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_HMA_DEBUG_CNT", 0x7798, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_EDRAM0_BAR", 0x77c0, 0 },
+ { "EDRAM0_BASE", 16, 12 },
+ { "EDRAM0_SIZE", 0, 12 },
+ { "MA_EDRAM1_BAR", 0x77c4, 0 },
+ { "EDRAM1_BASE", 16, 12 },
+ { "EDRAM1_SIZE", 0, 12 },
+ { "MA_EXT_MEMORY0_BAR", 0x77c8, 0 },
+ { "EXT_MEM0_BASE", 16, 12 },
+ { "EXT_MEM0_SIZE", 0, 12 },
+ { "MA_HOST_MEMORY_BAR", 0x77cc, 0 },
+ { "HMA_BASE", 16, 12 },
+ { "HMA_SIZE", 0, 12 },
+ { "MA_EXT_MEM_PAGE_SIZE", 0x77d0, 0 },
+ { "BRC_MODE1", 6, 1 },
+ { "EXT_MEM_PAGE_SIZE1", 4, 2 },
+ { "BRC_MODE", 2, 1 },
+ { "EXT_MEM_PAGE_SIZE", 0, 2 },
+ { "MA_ARB_CTRL", 0x77d4, 0 },
+ { "DIS_BANK_FAIR", 2, 1 },
+ { "DIS_PAGE_HINT", 1, 1 },
+ { "DIS_ADV_ARB", 0, 1 },
+ { "MA_TARGET_MEM_ENABLE", 0x77d8, 0 },
+ { "HMA_MUX", 5, 1 },
+ { "EXT_MEM1_ENABLE", 4, 1 },
+ { "HMA_ENABLE", 3, 1 },
+ { "EXT_MEM0_ENABLE", 2, 1 },
+ { "EDRAM1_ENABLE", 1, 1 },
+ { "EDRAM0_ENABLE", 0, 1 },
+ { "MA_INT_ENABLE", 0x77dc, 0 },
+ { "MEM_TO_INT_ENABLE", 2, 1 },
+ { "MEM_PERR_INT_ENABLE", 1, 1 },
+ { "MEM_WRAP_INT_ENABLE", 0, 1 },
+ { "MA_INT_CAUSE", 0x77e0, 0 },
+ { "MEM_TO_INT_CAUSE", 2, 1 },
+ { "MEM_PERR_INT_CAUSE", 1, 1 },
+ { "MEM_WRAP_INT_CAUSE", 0, 1 },
+ { "MA_INT_WRAP_STATUS", 0x77e4, 0 },
+ { "MEM_WRAP_ADDRESS", 4, 28 },
+ { "MEM_WRAP_CLIENT_NUM", 0, 4 },
+ { "MA_TP_THREAD1_MAPPER", 0x77e8, 0 },
+ { "MA_SGE_THREAD1_MAPPER", 0x77ec, 0 },
+ { "MA_PARITY_ERROR_ENABLE1", 0x77f0, 0 },
+ { "TP_DMARBT_PAR_ERROR_EN", 31, 1 },
+ { "LOGIC_FIFO_PAR_ERROR_EN", 30, 1 },
+ { "ARB3_PAR_WRQUEUE_ERROR_EN", 29, 1 },
+ { "ARB2_PAR_WRQUEUE_ERROR_EN", 28, 1 },
+ { "ARB1_PAR_WRQUEUE_ERROR_EN", 27, 1 },
+ { "ARB0_PAR_WRQUEUE_ERROR_EN", 26, 1 },
+ { "ARB3_PAR_RDQUEUE_ERROR_EN", 25, 1 },
+ { "ARB2_PAR_RDQUEUE_ERROR_EN", 24, 1 },
+ { "ARB1_PAR_RDQUEUE_ERROR_EN", 23, 1 },
+ { "ARB0_PAR_RDQUEUE_ERROR_EN", 22, 1 },
+ { "CL10_PAR_WRQUEUE_ERROR_EN", 21, 1 },
+ { "CL9_PAR_WRQUEUE_ERROR_EN", 20, 1 },
+ { "CL8_PAR_WRQUEUE_ERROR_EN", 19, 1 },
+ { "CL7_PAR_WRQUEUE_ERROR_EN", 18, 1 },
+ { "CL6_PAR_WRQUEUE_ERROR_EN", 17, 1 },
+ { "CL5_PAR_WRQUEUE_ERROR_EN", 16, 1 },
+ { "CL4_PAR_WRQUEUE_ERROR_EN", 15, 1 },
+ { "CL3_PAR_WRQUEUE_ERROR_EN", 14, 1 },
+ { "CL2_PAR_WRQUEUE_ERROR_EN", 13, 1 },
+ { "CL1_PAR_WRQUEUE_ERROR_EN", 12, 1 },
+ { "CL0_PAR_WRQUEUE_ERROR_EN", 11, 1 },
+ { "CL10_PAR_RDQUEUE_ERROR_EN", 10, 1 },
+ { "CL9_PAR_RDQUEUE_ERROR_EN", 9, 1 },
+ { "CL8_PAR_RDQUEUE_ERROR_EN", 8, 1 },
+ { "CL7_PAR_RDQUEUE_ERROR_EN", 7, 1 },
+ { "CL6_PAR_RDQUEUE_ERROR_EN", 6, 1 },
+ { "CL5_PAR_RDQUEUE_ERROR_EN", 5, 1 },
+ { "CL4_PAR_RDQUEUE_ERROR_EN", 4, 1 },
+ { "CL3_PAR_RDQUEUE_ERROR_EN", 3, 1 },
+ { "CL2_PAR_RDQUEUE_ERROR_EN", 2, 1 },
+ { "CL1_PAR_RDQUEUE_ERROR_EN", 1, 1 },
+ { "CL0_PAR_RDQUEUE_ERROR_EN", 0, 1 },
+ { "MA_PARITY_ERROR_STATUS1", 0x77f4, 0 },
+ { "TP_DMARBT_PAR_ERROR", 31, 1 },
+ { "LOGIC_FIFO_PAR_ERROR", 30, 1 },
+ { "ARB3_PAR_WRQUEUE_ERROR", 29, 1 },
+ { "ARB2_PAR_WRQUEUE_ERROR", 28, 1 },
+ { "ARB1_PAR_WRQUEUE_ERROR", 27, 1 },
+ { "ARB0_PAR_WRQUEUE_ERROR", 26, 1 },
+ { "ARB3_PAR_RDQUEUE_ERROR", 25, 1 },
+ { "ARB2_PAR_RDQUEUE_ERROR", 24, 1 },
+ { "ARB1_PAR_RDQUEUE_ERROR", 23, 1 },
+ { "ARB0_PAR_RDQUEUE_ERROR", 22, 1 },
+ { "CL10_PAR_WRQUEUE_ERROR", 21, 1 },
+ { "CL9_PAR_WRQUEUE_ERROR", 20, 1 },
+ { "CL8_PAR_WRQUEUE_ERROR", 19, 1 },
+ { "CL7_PAR_WRQUEUE_ERROR", 18, 1 },
+ { "CL6_PAR_WRQUEUE_ERROR", 17, 1 },
+ { "CL5_PAR_WRQUEUE_ERROR", 16, 1 },
+ { "CL4_PAR_WRQUEUE_ERROR", 15, 1 },
+ { "CL3_PAR_WRQUEUE_ERROR", 14, 1 },
+ { "CL2_PAR_WRQUEUE_ERROR", 13, 1 },
+ { "CL1_PAR_WRQUEUE_ERROR", 12, 1 },
+ { "CL0_PAR_WRQUEUE_ERROR", 11, 1 },
+ { "CL10_PAR_RDQUEUE_ERROR", 10, 1 },
+ { "CL9_PAR_RDQUEUE_ERROR", 9, 1 },
+ { "CL8_PAR_RDQUEUE_ERROR", 8, 1 },
+ { "CL7_PAR_RDQUEUE_ERROR", 7, 1 },
+ { "CL6_PAR_RDQUEUE_ERROR", 6, 1 },
+ { "CL5_PAR_RDQUEUE_ERROR", 5, 1 },
+ { "CL4_PAR_RDQUEUE_ERROR", 4, 1 },
+ { "CL3_PAR_RDQUEUE_ERROR", 3, 1 },
+ { "CL2_PAR_RDQUEUE_ERROR", 2, 1 },
+ { "CL1_PAR_RDQUEUE_ERROR", 1, 1 },
+ { "CL0_PAR_RDQUEUE_ERROR", 0, 1 },
+ { "MA_SGE_PCIE_COHERANCY_CTRL", 0x77f8, 0 },
+ { "BONUS_REG", 6, 26 },
+ { "COHERANCY_CMD_TYPE", 4, 2 },
+ { "COHERANCY_THREAD_NUM", 1, 3 },
+ { "COHERANCY_ENABLE", 0, 1 },
+ { "MA_ERROR_ENABLE", 0x77fc, 0 },
+ { "FUTURE_EXPANSION", 1, 31 },
+ { "UE_ENABLE", 0, 1 },
+ { "MA_PARITY_ERROR_ENABLE2", 0x7800, 0 },
+ { "ARB4_PAR_WRQUEUE_ERROR_EN", 1, 1 },
+ { "ARB4_PAR_RDQUEUE_ERROR_EN", 0, 1 },
+ { "MA_PARITY_ERROR_STATUS2", 0x7804, 0 },
+ { "ARB4_PAR_WRQUEUE_ERROR", 1, 1 },
+ { "ARB4_PAR_RDQUEUE_ERROR", 0, 1 },
+ { "MA_EXT_MEMORY1_BAR", 0x7808, 0 },
+ { "EXT_MEM1_BASE", 16, 12 },
+ { "EXT_MEM1_SIZE", 0, 12 },
+ { "MA_PMTX_THROTTLE", 0x780c, 0 },
+ { "FL_ENABLE", 31, 1 },
+ { "FL_LIMIT", 0, 8 },
+ { "MA_PMRX_THROTTLE", 0x7810, 0 },
+ { "FL_ENABLE", 31, 1 },
+ { "FL_LIMIT", 0, 8 },
+ { "MA_SGE_TH0_WRDATA_CNT", 0x7814, 0 },
+ { "MA_SGE_TH1_WRDATA_CNT", 0x7818, 0 },
+ { "MA_ULPTX_WRDATA_CNT", 0x781c, 0 },
+ { "MA_ULPRX_WRDATA_CNT", 0x7820, 0 },
+ { "MA_ULPTXRX_WRDATA_CNT", 0x7824, 0 },
+ { "MA_TP_TH0_WRDATA_CNT", 0x7828, 0 },
+ { "MA_TP_TH1_WRDATA_CNT", 0x782c, 0 },
+ { "MA_LE_WRDATA_CNT", 0x7830, 0 },
+ { "MA_CIM_WRDATA_CNT", 0x7834, 0 },
+ { "MA_PCIE_WRDATA_CNT", 0x7838, 0 },
+ { "MA_PMTX_WRDATA_CNT", 0x783c, 0 },
+ { "MA_PMRX_WRDATA_CNT", 0x7840, 0 },
+ { "MA_HMA_WRDATA_CNT", 0x7844, 0 },
+ { "MA_SGE_TH0_RDDATA_CNT", 0x7848, 0 },
+ { "MA_SGE_TH1_RDDATA_CNT", 0x784c, 0 },
+ { "MA_ULPTX_RDDATA_CNT", 0x7850, 0 },
+ { "MA_ULPRX_RDDATA_CNT", 0x7854, 0 },
+ { "MA_ULPTXRX_RDDATA_CNT", 0x7858, 0 },
+ { "MA_TP_TH0_RDDATA_CNT", 0x785c, 0 },
+ { "MA_TP_TH1_RDDATA_CNT", 0x7860, 0 },
+ { "MA_LE_RDDATA_CNT", 0x7864, 0 },
+ { "MA_CIM_RDDATA_CNT", 0x7868, 0 },
+ { "MA_PCIE_RDDATA_CNT", 0x786c, 0 },
+ { "MA_PMTX_RDDATA_CNT", 0x7870, 0 },
+ { "MA_PMRX_RDDATA_CNT", 0x7874, 0 },
+ { "MA_HMA_RDDATA_CNT", 0x7878, 0 },
+ { "MA_EDRAM0_WRDATA_CNT1", 0x787c, 0 },
+ { "MA_EDRAM0_WRDATA_CNT0", 0x7880, 0 },
+ { "MA_EDRAM1_WRDATA_CNT1", 0x7884, 0 },
+ { "MA_EDRAM1_WRDATA_CNT0", 0x7888, 0 },
+ { "MA_EXT_MEMORY0_WRDATA_CNT1", 0x788c, 0 },
+ { "MA_EXT_MEMORY0_WRDATA_CNT0", 0x7890, 0 },
+ { "MA_HOST_MEMORY_WRDATA_CNT1", 0x7894, 0 },
+ { "MA_HOST_MEMORY_WRDATA_CNT0", 0x7898, 0 },
+ { "MA_EXT_MEMORY1_WRDATA_CNT1", 0x789c, 0 },
+ { "MA_EXT_MEMORY1_WRDATA_CNT0", 0x78a0, 0 },
+ { "MA_EDRAM0_RDDATA_CNT1", 0x78a4, 0 },
+ { "MA_EDRAM0_RDDATA_CNT0", 0x78a8, 0 },
+ { "MA_EDRAM1_RDDATA_CNT1", 0x78ac, 0 },
+ { "MA_EDRAM1_RDDATA_CNT0", 0x78b0, 0 },
+ { "MA_EXT_MEMORY0_RDDATA_CNT1", 0x78b4, 0 },
+ { "MA_EXT_MEMORY0_RDDATA_CNT0", 0x78b8, 0 },
+ { "MA_HOST_MEMORY_RDDATA_CNT1", 0x78bc, 0 },
+ { "MA_HOST_MEMORY_RDDATA_CNT0", 0x78c0, 0 },
+ { "MA_EXT_MEMORY1_RDDATA_CNT1", 0x78c4, 0 },
+ { "MA_EXT_MEMORY1_RDDATA_CNT0", 0x78c8, 0 },
+ { "MA_TIMEOUT_CFG", 0x78cc, 0 },
+ { "CLR", 31, 1 },
+ { "CNT_LOCK", 30, 1 },
+ { "WRN", 24, 1 },
+ { "DIR", 23, 1 },
+ { "TYPE", 22, 1 },
+ { "CLIENT", 16, 4 },
+ { "DELAY", 0, 16 },
+ { "MA_TIMEOUT_CNT", 0x78d0, 0 },
+ { "DIR", 23, 1 },
+ { "TYPE", 22, 1 },
+ { "CLIENT", 16, 4 },
+ { "CNT_VAL", 0, 16 },
+ { "MA_WRITE_TIMEOUT_ERROR_ENABLE", 0x78d4, 0 },
+ { "FUTURE_CEXPANSION", 29, 3 },
+ { "CL12_WR_CMD_TO_EN", 28, 1 },
+ { "CL11_WR_CMD_TO_EN", 27, 1 },
+ { "CL10_WR_CMD_TO_EN", 26, 1 },
+ { "CL9_WR_CMD_TO_EN", 25, 1 },
+ { "CL8_WR_CMD_TO_EN", 24, 1 },
+ { "CL7_WR_CMD_TO_EN", 23, 1 },
+ { "CL6_WR_CMD_TO_EN", 22, 1 },
+ { "CL5_WR_CMD_TO_EN", 21, 1 },
+ { "CL4_WR_CMD_TO_EN", 20, 1 },
+ { "CL3_WR_CMD_TO_EN", 19, 1 },
+ { "CL2_WR_CMD_TO_EN", 18, 1 },
+ { "CL1_WR_CMD_TO_EN", 17, 1 },
+ { "CL0_WR_CMD_TO_EN", 16, 1 },
+ { "FUTURE_DEXPANSION", 13, 3 },
+ { "CL12_WR_DATA_TO_EN", 12, 1 },
+ { "CL11_WR_DATA_TO_EN", 11, 1 },
+ { "CL10_WR_DATA_TO_EN", 10, 1 },
+ { "CL9_WR_DATA_TO_EN", 9, 1 },
+ { "CL8_WR_DATA_TO_EN", 8, 1 },
+ { "CL7_WR_DATA_TO_EN", 7, 1 },
+ { "CL6_WR_DATA_TO_EN", 6, 1 },
+ { "CL5_WR_DATA_TO_EN", 5, 1 },
+ { "CL4_WR_DATA_TO_EN", 4, 1 },
+ { "CL3_WR_DATA_TO_EN", 3, 1 },
+ { "CL2_WR_DATA_TO_EN", 2, 1 },
+ { "CL1_WR_DATA_TO_EN", 1, 1 },
+ { "CL0_WR_DATA_TO_EN", 0, 1 },
+ { "MA_WRITE_TIMEOUT_ERROR_STATUS", 0x78d8, 0 },
+ { "FUTURE_CEXPANSION", 29, 3 },
+ { "CL12_WR_CMD_TO_ERROR", 28, 1 },
+ { "CL11_WR_CMD_TO_ERROR", 27, 1 },
+ { "CL10_WR_CMD_TO_ERROR", 26, 1 },
+ { "CL9_WR_CMD_TO_ERROR", 25, 1 },
+ { "CL8_WR_CMD_TO_ERROR", 24, 1 },
+ { "CL7_WR_CMD_TO_ERROR", 23, 1 },
+ { "CL6_WR_CMD_TO_ERROR", 22, 1 },
+ { "CL5_WR_CMD_TO_ERROR", 21, 1 },
+ { "CL4_WR_CMD_TO_ERROR", 20, 1 },
+ { "CL3_WR_CMD_TO_ERROR", 19, 1 },
+ { "CL2_WR_CMD_TO_ERROR", 18, 1 },
+ { "CL1_WR_CMD_TO_ERROR", 17, 1 },
+ { "CL0_WR_CMD_TO_ERROR", 16, 1 },
+ { "FUTURE_DEXPANSION", 13, 3 },
+ { "CL12_WR_DATA_TO_ERROR", 12, 1 },
+ { "CL11_WR_DATA_TO_ERROR", 11, 1 },
+ { "CL10_WR_DATA_TO_ERROR", 10, 1 },
+ { "CL9_WR_DATA_TO_ERROR", 9, 1 },
+ { "CL8_WR_DATA_TO_ERROR", 8, 1 },
+ { "CL7_WR_DATA_TO_ERROR", 7, 1 },
+ { "CL6_WR_DATA_TO_ERROR", 6, 1 },
+ { "CL5_WR_DATA_TO_ERROR", 5, 1 },
+ { "CL4_WR_DATA_TO_ERROR", 4, 1 },
+ { "CL3_WR_DATA_TO_ERROR", 3, 1 },
+ { "CL2_WR_DATA_TO_ERROR", 2, 1 },
+ { "CL1_WR_DATA_TO_ERROR", 1, 1 },
+ { "CL0_WR_DATA_TO_ERROR", 0, 1 },
+ { "MA_READ_TIMEOUT_ERROR_ENABLE", 0x78dc, 0 },
+ { "FUTURE_CEXPANSION", 29, 3 },
+ { "CL12_RD_CMD_TO_EN", 28, 1 },
+ { "CL11_RD_CMD_TO_EN", 27, 1 },
+ { "CL10_RD_CMD_TO_EN", 26, 1 },
+ { "CL9_RD_CMD_TO_EN", 25, 1 },
+ { "CL8_RD_CMD_TO_EN", 24, 1 },
+ { "CL7_RD_CMD_TO_EN", 23, 1 },
+ { "CL6_RD_CMD_TO_EN", 22, 1 },
+ { "CL5_RD_CMD_TO_EN", 21, 1 },
+ { "CL4_RD_CMD_TO_EN", 20, 1 },
+ { "CL3_RD_CMD_TO_EN", 19, 1 },
+ { "CL2_RD_CMD_TO_EN", 18, 1 },
+ { "CL1_RD_CMD_TO_EN", 17, 1 },
+ { "CL0_RD_CMD_TO_EN", 16, 1 },
+ { "FUTURE_DEXPANSION", 13, 3 },
+ { "CL12_RD_DATA_TO_EN", 12, 1 },
+ { "CL11_RD_DATA_TO_EN", 11, 1 },
+ { "CL10_RD_DATA_TO_EN", 10, 1 },
+ { "CL9_RD_DATA_TO_EN", 9, 1 },
+ { "CL8_RD_DATA_TO_EN", 8, 1 },
+ { "CL7_RD_DATA_TO_EN", 7, 1 },
+ { "CL6_RD_DATA_TO_EN", 6, 1 },
+ { "CL5_RD_DATA_TO_EN", 5, 1 },
+ { "CL4_RD_DATA_TO_EN", 4, 1 },
+ { "CL3_RD_DATA_TO_EN", 3, 1 },
+ { "CL2_RD_DATA_TO_EN", 2, 1 },
+ { "CL1_RD_DATA_TO_EN", 1, 1 },
+ { "CL0_RD_DATA_TO_EN", 0, 1 },
+ { "MA_READ_TIMEOUT_ERROR_STATUS", 0x78e0, 0 },
+ { "FUTURE_CEXPANSION", 29, 3 },
+ { "CL12_RD_CMD_TO_ERROR", 28, 1 },
+ { "CL11_RD_CMD_TO_ERROR", 27, 1 },
+ { "CL10_RD_CMD_TO_ERROR", 26, 1 },
+ { "CL9_RD_CMD_TO_ERROR", 25, 1 },
+ { "CL8_RD_CMD_TO_ERROR", 24, 1 },
+ { "CL7_RD_CMD_TO_ERROR", 23, 1 },
+ { "CL6_RD_CMD_TO_ERROR", 22, 1 },
+ { "CL5_RD_CMD_TO_ERROR", 21, 1 },
+ { "CL4_RD_CMD_TO_ERROR", 20, 1 },
+ { "CL3_RD_CMD_TO_ERROR", 19, 1 },
+ { "CL2_RD_CMD_TO_ERROR", 18, 1 },
+ { "CL1_RD_CMD_TO_ERROR", 17, 1 },
+ { "CL0_RD_CMD_TO_ERROR", 16, 1 },
+ { "FUTURE_DEXPANSION", 13, 3 },
+ { "CL12_RD_DATA_TO_ERROR", 12, 1 },
+ { "CL11_RD_DATA_TO_ERROR", 11, 1 },
+ { "CL10_RD_DATA_TO_ERROR", 10, 1 },
+ { "CL9_RD_DATA_TO_ERROR", 9, 1 },
+ { "CL8_RD_DATA_TO_ERROR", 8, 1 },
+ { "CL7_RD_DATA_TO_ERROR", 7, 1 },
+ { "CL6_RD_DATA_TO_ERROR", 6, 1 },
+ { "CL5_RD_DATA_TO_ERROR", 5, 1 },
+ { "CL4_RD_DATA_TO_ERROR", 4, 1 },
+ { "CL3_RD_DATA_TO_ERROR", 3, 1 },
+ { "CL2_RD_DATA_TO_ERROR", 2, 1 },
+ { "CL1_RD_DATA_TO_ERROR", 1, 1 },
+ { "CL0_RD_DATA_TO_ERROR", 0, 1 },
+ { "MA_BKP_CNT_SEL", 0x78e4, 0 },
+ { "TYPE", 30, 2 },
+ { "CLIENT", 24, 4 },
+ { "MA_BKP_CNT", 0x78e8, 0 },
+ { "MA_WRT_ARB", 0x78ec, 0 },
+ { "WRT_EN", 31, 1 },
+ { "WR_TIM", 16, 8 },
+ { "RD_WIN", 8, 8 },
+ { "WR_WIN", 0, 8 },
+ { "MA_IF_PARITY_ERROR_ENABLE", 0x78f0, 0 },
+ { "FUTURE_DEXPANSION", 13, 19 },
+ { "CL12_IF_PAR_EN", 12, 1 },
+ { "CL11_IF_PAR_EN", 11, 1 },
+ { "CL10_IF_PAR_EN", 10, 1 },
+ { "CL9_IF_PAR_EN", 9, 1 },
+ { "CL8_IF_PAR_EN", 8, 1 },
+ { "CL7_IF_PAR_EN", 7, 1 },
+ { "CL6_IF_PAR_EN", 6, 1 },
+ { "CL5_IF_PAR_EN", 5, 1 },
+ { "CL4_IF_PAR_EN", 4, 1 },
+ { "CL3_IF_PAR_EN", 3, 1 },
+ { "CL2_IF_PAR_EN", 2, 1 },
+ { "CL1_IF_PAR_EN", 1, 1 },
+ { "CL0_IF_PAR_EN", 0, 1 },
+ { "MA_IF_PARITY_ERROR_STATUS", 0x78f4, 0 },
+ { "FUTURE_DEXPANSION", 13, 19 },
+ { "CL12_IF_PAR_ERROR", 12, 1 },
+ { "CL11_IF_PAR_ERROR", 11, 1 },
+ { "CL10_IF_PAR_ERROR", 10, 1 },
+ { "CL9_IF_PAR_ERROR", 9, 1 },
+ { "CL8_IF_PAR_ERROR", 8, 1 },
+ { "CL7_IF_PAR_ERROR", 7, 1 },
+ { "CL6_IF_PAR_ERROR", 6, 1 },
+ { "CL5_IF_PAR_ERROR", 5, 1 },
+ { "CL4_IF_PAR_ERROR", 4, 1 },
+ { "CL3_IF_PAR_ERROR", 3, 1 },
+ { "CL2_IF_PAR_ERROR", 2, 1 },
+ { "CL1_IF_PAR_ERROR", 1, 1 },
+ { "CL0_IF_PAR_ERROR", 0, 1 },
+ { "MA_LOCAL_DEBUG_CFG", 0x78f8, 0 },
+ { "DEBUG_OR", 15, 1 },
+ { "DEBUG_HI", 14, 1 },
+ { "DEBUG_RPT", 13, 1 },
+ { "DEBUGPAGE", 10, 3 },
+ { "DEBUGSELH", 5, 5 },
+ { "DEBUGSELL", 0, 5 },
+ { "MA_LOCAL_DEBUG_RPT", 0x78fc, 0 },
+ { NULL }
+};
+
+struct reg_info t5_cim_regs[] = {
+ { "CIM_BOOT_CFG", 0x7b00, 0 },
+ { "BootAddr", 8, 24 },
+ { "uPGen", 2, 6 },
+ { "BootSdram", 1, 1 },
+ { "uPCRst", 0, 1 },
+ { "CIM_BOOT_LEN", 0x7bf0, 0 },
+ { "BootLen", 4, 28 },
+ { "CIM_FLASH_BASE_ADDR", 0x7b04, 0 },
+ { "FlashBaseAddr", 6, 18 },
+ { "CIM_FLASH_ADDR_SIZE", 0x7b08, 0 },
+ { "FlashAddrSize", 4, 20 },
+ { "CIM_EEPROM_BASE_ADDR", 0x7b0c, 0 },
+ { "EEPROMBaseAddr", 6, 18 },
+ { "CIM_EEPROM_ADDR_SIZE", 0x7b10, 0 },
+ { "EEPROMAddrSize", 4, 20 },
+ { "CIM_SDRAM_BASE_ADDR", 0x7b14, 0 },
+ { "SdramBaseAddr", 6, 26 },
+ { "CIM_SDRAM_ADDR_SIZE", 0x7b18, 0 },
+ { "SdramAddrSize", 4, 28 },
+ { "CIM_EXTMEM2_BASE_ADDR", 0x7b1c, 0 },
+ { "ExtMem2BaseAddr", 6, 26 },
+ { "CIM_EXTMEM2_ADDR_SIZE", 0x7b20, 0 },
+ { "ExtMem2AddrSize", 4, 28 },
+ { "CIM_UP_SPARE_INT", 0x7b24, 0 },
+ { "TDebugInt", 4, 1 },
+ { "BootVecSel", 3, 1 },
+ { "uPSpareInt", 0, 3 },
+ { "CIM_HOST_INT_ENABLE", 0x7b28, 0 },
+ { "ma_cim_IntfPerr", 28, 1 },
+ { "PLCIM_MstRspDataParErr", 27, 1 },
+ { "NCSI2CIMIntfParErr", 26, 1 },
+ { "SGE2CIMIntfParErr", 25, 1 },
+ { "ULP2CIMIntfParErr", 24, 1 },
+ { "TP2CIMIntfParErr", 23, 1 },
+ { "OBQSGERx1ParErr", 22, 1 },
+ { "OBQSGERx0ParErr", 21, 1 },
+ { "TieQOutParErrIntEn", 20, 1 },
+ { "TieQInParErrIntEn", 19, 1 },
+ { "MBHostParErr", 18, 1 },
+ { "MBuPParErr", 17, 1 },
+ { "IBQTP0ParErr", 16, 1 },
+ { "IBQTP1ParErr", 15, 1 },
+ { "IBQULPParErr", 14, 1 },
+ { "IBQSGELOParErr", 13, 1 },
+ { "IBQSGEHIParErr", 12, 1 },
+ { "IBQNCSIParErr", 11, 1 },
+ { "OBQULP0ParErr", 10, 1 },
+ { "OBQULP1ParErr", 9, 1 },
+ { "OBQULP2ParErr", 8, 1 },
+ { "OBQULP3ParErr", 7, 1 },
+ { "OBQSGEParErr", 6, 1 },
+ { "OBQNCSIParErr", 5, 1 },
+ { "Timer1IntEn", 3, 1 },
+ { "Timer0IntEn", 2, 1 },
+ { "PrefDropIntEn", 1, 1 },
+ { "CIM_HOST_INT_CAUSE", 0x7b2c, 0 },
+ { "ma_cim_IntfPerr", 28, 1 },
+ { "PLCIM_MstRspDataParErr", 27, 1 },
+ { "NCSI2CIMIntfParErr", 26, 1 },
+ { "SGE2CIMIntfParErr", 25, 1 },
+ { "ULP2CIMIntfParErr", 24, 1 },
+ { "TP2CIMIntfParErr", 23, 1 },
+ { "OBQSGERx1ParErr", 22, 1 },
+ { "OBQSGERx0ParErr", 21, 1 },
+ { "TieQOutParErrInt", 20, 1 },
+ { "TieQInParErrInt", 19, 1 },
+ { "MBHostParErr", 18, 1 },
+ { "IBQTP0ParErr", 16, 1 },
+ { "IBQTP1ParErr", 15, 1 },
+ { "IBQULPParErr", 14, 1 },
+ { "IBQSGELOParErr", 13, 1 },
+ { "IBQSGEHIParErr", 12, 1 },
+ { "IBQNCSIParErr", 11, 1 },
+ { "OBQULP0ParErr", 10, 1 },
+ { "OBQULP1ParErr", 9, 1 },
+ { "OBQULP2ParErr", 8, 1 },
+ { "OBQULP3ParErr", 7, 1 },
+ { "OBQSGEParErr", 6, 1 },
+ { "OBQNCSIParErr", 5, 1 },
+ { "Timer1Int", 3, 1 },
+ { "Timer0Int", 2, 1 },
+ { "PrefDropInt", 1, 1 },
+ { "uPAccNonZero", 0, 1 },
+ { "CIM_HOST_UPACC_INT_ENABLE", 0x7b30, 0 },
+ { "EEPROMWRIntEn", 30, 1 },
+ { "TimeOutMAIntEn", 29, 1 },
+ { "TimeOutIntEn", 28, 1 },
+ { "RspOvrLookupIntEn", 27, 1 },
+ { "ReqOvrLookupIntEn", 26, 1 },
+ { "BlkWrPlIntEn", 25, 1 },
+ { "BlkRdPlIntEn", 24, 1 },
+ { "SglWrPlIntEn", 23, 1 },
+ { "SglRdPlIntEn", 22, 1 },
+ { "BlkWrCtlIntEn", 21, 1 },
+ { "BlkRdCtlIntEn", 20, 1 },
+ { "SglWrCtlIntEn", 19, 1 },
+ { "SglRdCtlIntEn", 18, 1 },
+ { "BlkWrEEPROMIntEn", 17, 1 },
+ { "BlkRdEEPROMIntEn", 16, 1 },
+ { "SglWrEEPROMIntEn", 15, 1 },
+ { "SglRdEEPROMIntEn", 14, 1 },
+ { "BlkWrFlashIntEn", 13, 1 },
+ { "BlkRdFlashIntEn", 12, 1 },
+ { "SglWrFlashIntEn", 11, 1 },
+ { "SglRdFlashIntEn", 10, 1 },
+ { "BlkWrBootIntEn", 9, 1 },
+ { "BlkRdBootIntEn", 8, 1 },
+ { "SglWrBootIntEn", 7, 1 },
+ { "SglRdBootIntEn", 6, 1 },
+ { "IllWrBEIntEn", 5, 1 },
+ { "IllRdBEIntEn", 4, 1 },
+ { "IllRdIntEn", 3, 1 },
+ { "IllWrIntEn", 2, 1 },
+ { "IllTransIntEn", 1, 1 },
+ { "RsvdSpaceIntEn", 0, 1 },
+ { "CIM_HOST_UPACC_INT_CAUSE", 0x7b34, 0 },
+ { "EEPROMWRInt", 30, 1 },
+ { "TimeOutMAInt", 29, 1 },
+ { "TimeOutInt", 28, 1 },
+ { "RspOvrLookupInt", 27, 1 },
+ { "ReqOvrLookupInt", 26, 1 },
+ { "BlkWrPlInt", 25, 1 },
+ { "BlkRdPlInt", 24, 1 },
+ { "SglWrPlInt", 23, 1 },
+ { "SglRdPlInt", 22, 1 },
+ { "BlkWrCtlInt", 21, 1 },
+ { "BlkRdCtlInt", 20, 1 },
+ { "SglWrCtlInt", 19, 1 },
+ { "SglRdCtlInt", 18, 1 },
+ { "BlkWrEEPROMInt", 17, 1 },
+ { "BlkRdEEPROMInt", 16, 1 },
+ { "SglWrEEPROMInt", 15, 1 },
+ { "SglRdEEPROMInt", 14, 1 },
+ { "BlkWrFlashInt", 13, 1 },
+ { "BlkRdFlashInt", 12, 1 },
+ { "SglWrFlashInt", 11, 1 },
+ { "SglRdFlashInt", 10, 1 },
+ { "BlkWrBootInt", 9, 1 },
+ { "BlkRdBootInt", 8, 1 },
+ { "SglWrBootInt", 7, 1 },
+ { "SglRdBootInt", 6, 1 },
+ { "IllWrBEInt", 5, 1 },
+ { "IllRdBEInt", 4, 1 },
+ { "IllRdInt", 3, 1 },
+ { "IllWrInt", 2, 1 },
+ { "IllTransInt", 1, 1 },
+ { "RsvdSpaceInt", 0, 1 },
+ { "CIM_UP_INT_ENABLE", 0x7b38, 0 },
+ { "ma_cim_IntfPerr", 28, 1 },
+ { "PLCIM_MstRspDataParErr", 27, 1 },
+ { "NCSI2CIMIntfParErr", 26, 1 },
+ { "SGE2CIMIntfParErr", 25, 1 },
+ { "ULP2CIMIntfParErr", 24, 1 },
+ { "TP2CIMIntfParErr", 23, 1 },
+ { "OBQSGERx1ParErr", 22, 1 },
+ { "OBQSGERx0ParErr", 21, 1 },
+ { "TieQOutParErrIntEn", 20, 1 },
+ { "TieQInParErrIntEn", 19, 1 },
+ { "MBHostParErr", 18, 1 },
+ { "MBuPParErr", 17, 1 },
+ { "IBQTP0ParErr", 16, 1 },
+ { "IBQTP1ParErr", 15, 1 },
+ { "IBQULPParErr", 14, 1 },
+ { "IBQSGELOParErr", 13, 1 },
+ { "IBQSGEHIParErr", 12, 1 },
+ { "IBQNCSIParErr", 11, 1 },
+ { "OBQULP0ParErr", 10, 1 },
+ { "OBQULP1ParErr", 9, 1 },
+ { "OBQULP2ParErr", 8, 1 },
+ { "OBQULP3ParErr", 7, 1 },
+ { "OBQSGEParErr", 6, 1 },
+ { "OBQNCSIParErr", 5, 1 },
+ { "MstPlIntEn", 4, 1 },
+ { "Timer1IntEn", 3, 1 },
+ { "Timer0IntEn", 2, 1 },
+ { "PrefDropIntEn", 1, 1 },
+ { "CIM_UP_INT_CAUSE", 0x7b3c, 0 },
+ { "ma_cim_IntfPerr", 28, 1 },
+ { "PLCIM_MstRspDataParErr", 27, 1 },
+ { "NCSI2CIMIntfParErr", 26, 1 },
+ { "SGE2CIMIntfParErr", 25, 1 },
+ { "ULP2CIMIntfParErr", 24, 1 },
+ { "TP2CIMIntfParErr", 23, 1 },
+ { "OBQSGERx1ParErr", 22, 1 },
+ { "OBQSGERx0ParErr", 21, 1 },
+ { "TieQOutParErrInt", 20, 1 },
+ { "TieQInParErrInt", 19, 1 },
+ { "MBHostParErr", 18, 1 },
+ { "IBQTP0ParErr", 16, 1 },
+ { "IBQTP1ParErr", 15, 1 },
+ { "IBQULPParErr", 14, 1 },
+ { "IBQSGELOParErr", 13, 1 },
+ { "IBQSGEHIParErr", 12, 1 },
+ { "IBQNCSIParErr", 11, 1 },
+ { "OBQULP0ParErr", 10, 1 },
+ { "OBQULP1ParErr", 9, 1 },
+ { "OBQULP2ParErr", 8, 1 },
+ { "OBQULP3ParErr", 7, 1 },
+ { "OBQSGEParErr", 6, 1 },
+ { "OBQNCSIParErr", 5, 1 },
+ { "MstPlInt", 4, 1 },
+ { "Timer1Int", 3, 1 },
+ { "Timer0Int", 2, 1 },
+ { "PrefDropInt", 1, 1 },
+ { "uPAccNonZero", 0, 1 },
+ { "CIM_UP_ACC_INT_ENABLE", 0x7b40, 0 },
+ { "EEPROMWRIntEn", 30, 1 },
+ { "TimeOutMAIntEn", 29, 1 },
+ { "TimeOutIntEn", 28, 1 },
+ { "RspOvrLookupIntEn", 27, 1 },
+ { "ReqOvrLookupIntEn", 26, 1 },
+ { "BlkWrPlIntEn", 25, 1 },
+ { "BlkRdPlIntEn", 24, 1 },
+ { "SglWrPlIntEn", 23, 1 },
+ { "SglRdPlIntEn", 22, 1 },
+ { "BlkWrCtlIntEn", 21, 1 },
+ { "BlkRdCtlIntEn", 20, 1 },
+ { "SglWrCtlIntEn", 19, 1 },
+ { "SglRdCtlIntEn", 18, 1 },
+ { "BlkWrEEPROMIntEn", 17, 1 },
+ { "BlkRdEEPROMIntEn", 16, 1 },
+ { "SglWrEEPROMIntEn", 15, 1 },
+ { "SglRdEEPROMIntEn", 14, 1 },
+ { "BlkWrFlashIntEn", 13, 1 },
+ { "BlkRdFlashIntEn", 12, 1 },
+ { "SglWrFlashIntEn", 11, 1 },
+ { "SglRdFlashIntEn", 10, 1 },
+ { "BlkWrBootIntEn", 9, 1 },
+ { "BlkRdBootIntEn", 8, 1 },
+ { "SglWrBootIntEn", 7, 1 },
+ { "SglRdBootIntEn", 6, 1 },
+ { "IllWrBEIntEn", 5, 1 },
+ { "IllRdBEIntEn", 4, 1 },
+ { "IllRdIntEn", 3, 1 },
+ { "IllWrIntEn", 2, 1 },
+ { "IllTransIntEn", 1, 1 },
+ { "RsvdSpaceIntEn", 0, 1 },
+ { "CIM_UP_ACC_INT_CAUSE", 0x7b44, 0 },
+ { "EEPROMWRInt", 30, 1 },
+ { "TimeOutMAInt", 29, 1 },
+ { "TimeOutInt", 28, 1 },
+ { "RspOvrLookupInt", 27, 1 },
+ { "ReqOvrLookupInt", 26, 1 },
+ { "BlkWrPlInt", 25, 1 },
+ { "BlkRdPlInt", 24, 1 },
+ { "SglWrPlInt", 23, 1 },
+ { "SglRdPlInt", 22, 1 },
+ { "BlkWrCtlInt", 21, 1 },
+ { "BlkRdCtlInt", 20, 1 },
+ { "SglWrCtlInt", 19, 1 },
+ { "SglRdCtlInt", 18, 1 },
+ { "BlkWrEEPROMInt", 17, 1 },
+ { "BlkRdEEPROMInt", 16, 1 },
+ { "SglWrEEPROMInt", 15, 1 },
+ { "SglRdEEPROMInt", 14, 1 },
+ { "BlkWrFlashInt", 13, 1 },
+ { "BlkRdFlashInt", 12, 1 },
+ { "SglWrFlashInt", 11, 1 },
+ { "SglRdFlashInt", 10, 1 },
+ { "BlkWrBootInt", 9, 1 },
+ { "BlkRdBootInt", 8, 1 },
+ { "SglWrBootInt", 7, 1 },
+ { "SglRdBootInt", 6, 1 },
+ { "IllWrBEInt", 5, 1 },
+ { "IllRdBEInt", 4, 1 },
+ { "IllRdInt", 3, 1 },
+ { "IllWrInt", 2, 1 },
+ { "IllTransInt", 1, 1 },
+ { "RsvdSpaceInt", 0, 1 },
+ { "CIM_QUEUE_CONFIG_REF", 0x7b48, 0 },
+ { "OBQSelect", 4, 1 },
+ { "IBQSelect", 3, 1 },
+ { "QueNumSelect", 0, 3 },
+ { "CIM_QUEUE_CONFIG_CTRL", 0x7b4c, 0 },
+ { "QueSize", 24, 6 },
+ { "QueBase", 16, 6 },
+ { "QueDbg8BEn", 9, 1 },
+ { "QueFullThrsh", 0, 9 },
+ { "CIM_HOST_ACC_CTRL", 0x7b50, 0 },
+ { "HostBusy", 17, 1 },
+ { "HostWrite", 16, 1 },
+ { "HostAddr", 0, 16 },
+ { "CIM_HOST_ACC_DATA", 0x7b54, 0 },
+ { "CIM_CDEBUGDATA", 0x7b58, 0 },
+ { "CDebugDataH", 16, 16 },
+ { "CDebugDataL", 0, 16 },
+ { "CIM_IBQ_DBG_CFG", 0x7b60, 0 },
+ { "IbqDbgAddr", 16, 12 },
+ { "IbqDbgWr", 2, 1 },
+ { "IbqDbgBusy", 1, 1 },
+ { "IbqDbgEn", 0, 1 },
+ { "CIM_OBQ_DBG_CFG", 0x7b64, 0 },
+ { "ObqDbgAddr", 16, 12 },
+ { "ObqDbgWr", 2, 1 },
+ { "ObqDbgBusy", 1, 1 },
+ { "ObqDbgEn", 0, 1 },
+ { "CIM_IBQ_DBG_DATA", 0x7b68, 0 },
+ { "CIM_OBQ_DBG_DATA", 0x7b6c, 0 },
+ { "CIM_DEBUGCFG", 0x7b70, 0 },
+ { "POLADbgRdPtr", 23, 9 },
+ { "PILADbgRdPtr", 14, 9 },
+ { "LAMaskTrig", 13, 1 },
+ { "LADbgEn", 12, 1 },
+ { "LAFillOnce", 11, 1 },
+ { "LAMaskStop", 10, 1 },
+ { "DebugSelH", 5, 5 },
+ { "DebugSelL", 0, 5 },
+ { "CIM_DEBUGSTS", 0x7b74, 0 },
+ { "LAReset", 31, 1 },
+ { "POLADbgWrPtr", 16, 9 },
+ { "PILADbgWrPtr", 0, 9 },
+ { "CIM_PO_LA_DEBUGDATA", 0x7b78, 0 },
+ { "CIM_PI_LA_DEBUGDATA", 0x7b7c, 0 },
+ { "CIM_PO_LA_MADEBUGDATA", 0x7b80, 0 },
+ { "CIM_PI_LA_MADEBUGDATA", 0x7b84, 0 },
+ { "CIM_PO_LA_PIFSMDEBUGDATA", 0x7b8c, 0 },
+ { "CIM_MEM_ZONE0_VA", 0x7b90, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE0_BA", 0x7b94, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE0_LEN", 0x7b98, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE1_VA", 0x7b9c, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE1_BA", 0x7ba0, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE1_LEN", 0x7ba4, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE2_VA", 0x7ba8, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE2_BA", 0x7bac, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE2_LEN", 0x7bb0, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE3_VA", 0x7bb4, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE3_BA", 0x7bb8, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE3_LEN", 0x7bbc, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE4_VA", 0x7bc0, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE4_BA", 0x7bc4, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE4_LEN", 0x7bc8, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE5_VA", 0x7bcc, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE5_BA", 0x7bd0, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE5_LEN", 0x7bd4, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE6_VA", 0x7bd8, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE6_BA", 0x7bdc, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE6_LEN", 0x7be0, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE7_VA", 0x7be4, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE7_BA", 0x7be8, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE7_LEN", 0x7bec, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_GLB_TIMER_CTL", 0x7bf4, 0 },
+ { "Timer1En", 4, 1 },
+ { "Timer0En", 3, 1 },
+ { "TimerEn", 1, 1 },
+ { "CIM_GLB_TIMER", 0x7bf8, 0 },
+ { "CIM_GLB_TIMER_TICK", 0x7bfc, 0 },
+ { "CIM_TIMER0", 0x7c00, 0 },
+ { "CIM_TIMER1", 0x7c04, 0 },
+ { "CIM_DEBUG_ADDR_TIMEOUT", 0x7c08, 0 },
+ { "DAddrTimeOut", 2, 30 },
+ { "CIM_DEBUG_ADDR_ILLEGAL", 0x7c0c, 0 },
+ { "DAddrIllegal", 2, 30 },
+ { "CIM_DEBUG_PIF_CAUSE_MASK", 0x7c10, 0 },
+ { "CIM_DEBUG_PIF_UPACC_CAUSE_MASK", 0x7c14, 0 },
+ { "CIM_DEBUG_UP_CAUSE_MASK", 0x7c18, 0 },
+ { "CIM_DEBUG_UP_UPACC_CAUSE_MASK", 0x7c1c, 0 },
+ { "CIM_PERR_INJECT", 0x7c20, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "CIM_PERR_ENABLE", 0x7c24, 0 },
+ { "CIM_EEPROM_BUSY_BIT", 0x7c28, 0 },
+ { "CIM_MA_TIMER_EN", 0x7c2c, 0 },
+ { "CIM_UP_PO_SINGLE_OUTSTANDING", 0x7c30, 0 },
+ { "CIM_CIM_DEBUG_SPARE", 0x7c34, 0 },
+ { "CIM_UP_OPERATION_FREQ", 0x7c38, 0 },
+ { "CIM_CIM_IBQ_ERR_CODE", 0x7c3c, 0 },
+ { "CIM_ULP_TX_PKT_ERR_CODE", 16, 8 },
+ { "CIM_SGE1_PKT_ERR_CODE", 8, 8 },
+ { "CIM_SGE0_PKT_ERR_CODE", 0, 8 },
+ { "CIM_IBQ_DBG_WAIT_COUNTER", 0x7c40, 0 },
+ { "CIM_PIO_UP_MST_CFG_SEL", 0x7c44, 0 },
+ { "CIM_CGEN", 0x7c48, 0 },
+ { "CIM_QUEUE_FEATURE_DISABLE", 0x7c4c, 0 },
+ { "obq_throuttle_on_eop", 4, 1 },
+ { "obq_read_ctl_perf_mode_disable", 3, 1 },
+ { "obq_wait_for_eop_flush_disable", 2, 1 },
+ { "ibq_rra_dsbl", 1, 1 },
+ { "ibq_skid_fifo_eop_flsh_dsbl", 0, 1 },
+ { "CIM_CGEN_GLOBAL", 0x7c50, 0 },
+ { "CIM_DPSLP_EN", 0x7c54, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e240, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e244, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e248, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e24c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e250, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e254, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e258, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e25c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e260, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e264, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e268, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e26c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e270, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e274, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e278, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e27c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1e280, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1e284, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1e288, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1e28c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e290, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e640, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e644, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e648, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e64c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e650, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e654, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e658, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e65c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e660, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e664, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e668, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e66c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e670, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e674, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e678, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e67c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1e680, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1e684, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1e688, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1e68c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e690, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea40, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea44, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea48, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea4c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea50, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea54, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea58, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea5c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea60, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea64, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea68, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea6c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea70, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea74, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea78, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea7c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1ea80, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1ea84, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1ea88, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1ea8c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ea90, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee40, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee44, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee48, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee4c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee50, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee54, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee58, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee5c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee60, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee64, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee68, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee6c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee70, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee74, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee78, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee7c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1ee80, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1ee84, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1ee88, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1ee8c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ee90, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f240, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f244, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f248, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f24c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f250, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f254, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f258, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f25c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f260, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f264, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f268, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f26c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f270, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f274, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f278, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f27c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1f280, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1f284, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1f288, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1f28c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f290, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f640, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f644, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f648, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f64c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f650, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f654, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f658, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f65c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f660, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f664, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f668, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f66c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f670, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f674, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f678, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f67c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1f680, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1f684, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1f688, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1f68c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f690, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa40, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa44, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa48, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa4c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa50, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa54, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa58, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa5c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa60, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa64, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa68, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa6c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa70, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa74, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa78, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa7c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1fa80, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1fa84, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1fa88, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1fa8c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fa90, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe40, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe44, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe48, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe4c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe50, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe54, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe58, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe5c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe60, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe64, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe68, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe6c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe70, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe74, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe78, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe7c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1fe80, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1fe84, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1fe88, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1fe8c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fe90, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { NULL }
+};
+
+struct reg_info t5_tp_regs[] = {
+ { "TP_IN_CONFIG", 0x7d00, 0 },
+ { "VLANExtEnPort3", 31, 1 },
+ { "VLANExtEnPort2", 30, 1 },
+ { "VLANExtEnPort1", 29, 1 },
+ { "VLANExtEnPort0", 28, 1 },
+ { "TcpOptParserDisCh3", 27, 1 },
+ { "TcpOptParserDisCh2", 26, 1 },
+ { "TcpOptParserDisCh1", 25, 1 },
+ { "TcpOptParserDisCh0", 24, 1 },
+ { "CrcPassPrt3", 23, 1 },
+ { "CrcPassPrt2", 22, 1 },
+ { "CrcPassPrt1", 21, 1 },
+ { "CrcPassPrt0", 20, 1 },
+ { "VepaMode", 19, 1 },
+ { "FipUpEn", 18, 1 },
+ { "FcoeUpEn", 17, 1 },
+ { "FcoeEnable", 16, 1 },
+ { "IPv6Enable", 15, 1 },
+ { "NICMode", 14, 1 },
+ { "VnTagDefaultVal", 13, 1 },
+ { "ECheckUDPLen", 12, 1 },
+ { "EReportUdpHdrLen", 11, 1 },
+ { "FcoeFPMA", 10, 1 },
+ { "VnTagEnable", 9, 1 },
+ { "VnTagEthEnable", 8, 1 },
+ { "CChecksumCheckIP", 7, 1 },
+ { "CChecksumCheckUDP", 6, 1 },
+ { "CChecksumCheckTCP", 5, 1 },
+ { "CTag", 4, 1 },
+ { "CDemux", 3, 1 },
+ { "EthUpEn", 2, 1 },
+ { "CEthernet", 1, 1 },
+ { "CTunnel", 0, 1 },
+ { "TP_OUT_CONFIG", 0x7d04, 0 },
+ { "PortQfcEn", 28, 4 },
+ { "EPktDistChn3", 23, 1 },
+ { "EPktDistChn2", 22, 1 },
+ { "EPktDistChn1", 21, 1 },
+ { "EPktDistChn0", 20, 1 },
+ { "TtlMode", 19, 1 },
+ { "EQfcDmac", 18, 1 },
+ { "ELpbkIncMpsStat", 17, 1 },
+ { "IPIDSplitMode", 16, 1 },
+ { "EChecksumInsertTCP", 11, 1 },
+ { "EChecksumInsertIP", 10, 1 },
+ { "EVnTagEn", 9, 1 },
+ { "ECPL", 8, 1 },
+ { "EPriority", 7, 1 },
+ { "EEthernet", 6, 1 },
+ { "CChecksumInsertTCP", 5, 1 },
+ { "CChecksumInsertIP", 4, 1 },
+ { "CCPL", 2, 1 },
+ { "CEthernet", 0, 1 },
+ { "TP_GLOBAL_CONFIG", 0x7d08, 0 },
+ { "SYNCookieParams", 26, 6 },
+ { "RXFlowControlDisable", 25, 1 },
+ { "TXPacingEnable", 24, 1 },
+ { "AttackFilterEnable", 23, 1 },
+ { "SYNCookieNoOptions", 22, 1 },
+ { "ProtectedMode", 21, 1 },
+ { "PingDrop", 20, 1 },
+ { "FragmentDrop", 19, 1 },
+ { "FiveTupleLookup", 17, 2 },
+ { "OfdMpsStats", 16, 1 },
+ { "DontFragment", 15, 1 },
+ { "IPIdentSplit", 14, 1 },
+ { "RssSynSteerEnable", 12, 1 },
+ { "IssFromCplEnable", 11, 1 },
+ { "RssLoopbackEnable", 10, 1 },
+ { "TCAMServerUse", 8, 2 },
+ { "IPTTL", 0, 8 },
+ { "TP_DB_CONFIG", 0x7d0c, 0 },
+ { "DBMaxOpCnt", 24, 8 },
+ { "CxMaxOpCntDisable", 23, 1 },
+ { "CxMaxOpCnt", 16, 7 },
+ { "TxMaxOpCntDisable", 15, 1 },
+ { "TxMaxOpCnt", 8, 7 },
+ { "RxMaxOpCntDisable", 7, 1 },
+ { "RxMaxOpCnt", 0, 7 },
+ { "TP_CMM_TCB_BASE", 0x7d10, 0 },
+ { "TP_CMM_MM_BASE", 0x7d14, 0 },
+ { "TP_CMM_TIMER_BASE", 0x7d18, 0 },
+ { "TP_CMM_MM_FLST_SIZE", 0x7d1c, 0 },
+ { "RxPoolSize", 16, 16 },
+ { "TxPoolSize", 0, 16 },
+ { "TP_PMM_TX_BASE", 0x7d20, 0 },
+ { "TP_PMM_DEFRAG_BASE", 0x7d24, 0 },
+ { "TP_PMM_RX_BASE", 0x7d28, 0 },
+ { "TP_PMM_RX_PAGE_SIZE", 0x7d2c, 0 },
+ { "TP_PMM_RX_MAX_PAGE", 0x7d30, 0 },
+ { "PMRxNumChn", 31, 1 },
+ { "PMRxMaxPage", 0, 21 },
+ { "TP_PMM_TX_PAGE_SIZE", 0x7d34, 0 },
+ { "TP_PMM_TX_MAX_PAGE", 0x7d38, 0 },
+ { "PMTxNumChn", 30, 2 },
+ { "PMTxMaxPage", 0, 21 },
+ { "TP_TCP_OPTIONS", 0x7d40, 0 },
+ { "MTUDefault", 16, 16 },
+ { "MTUEnable", 10, 1 },
+ { "SACKTx", 9, 1 },
+ { "SACKRx", 8, 1 },
+ { "SACKMode", 4, 2 },
+ { "WindowScaleMode", 2, 2 },
+ { "TimestampsMode", 0, 2 },
+ { "TP_DACK_CONFIG", 0x7d44, 0 },
+ { "AutoState3", 30, 2 },
+ { "AutoState2", 28, 2 },
+ { "AutoState1", 26, 2 },
+ { "ByteThreshold", 8, 18 },
+ { "MSSThreshold", 4, 3 },
+ { "AutoCareful", 2, 1 },
+ { "AutoEnable", 1, 1 },
+ { "Mode", 0, 1 },
+ { "TP_PC_CONFIG", 0x7d48, 0 },
+ { "CMCacheDisable", 31, 1 },
+ { "EnableOcspiFull", 30, 1 },
+ { "EnableFLMErrorDDP", 29, 1 },
+ { "LockTid", 28, 1 },
+ { "DisableInvPend", 27, 1 },
+ { "EnableFilterCount", 26, 1 },
+ { "RddpCongEn", 25, 1 },
+ { "EnableOnFlyPDU", 24, 1 },
+ { "EnableMinRcvWnd", 23, 1 },
+ { "EnableMaxRcvWnd", 22, 1 },
+ { "TxDataAckRateEnable", 21, 1 },
+ { "TxDeferEnable", 20, 1 },
+ { "RxCongestionMode", 19, 1 },
+ { "HearbeatOnceDACK", 18, 1 },
+ { "HearbeatOnceHeap", 17, 1 },
+ { "HearbeatDACK", 16, 1 },
+ { "TxCongestionMode", 15, 1 },
+ { "AcceptLatestRcvAdv", 14, 1 },
+ { "DisableSYNData", 13, 1 },
+ { "DisableWindowPSH", 12, 1 },
+ { "DisableFINOldData", 11, 1 },
+ { "EnableFLMError", 10, 1 },
+ { "EnableOptMtu", 9, 1 },
+ { "FilterPeerFIN", 8, 1 },
+ { "EnableFeedbackSend", 7, 1 },
+ { "EnableRDMAError", 6, 1 },
+ { "EnableFilterNat", 5, 1 },
+ { "DisableHeldFIN", 4, 1 },
+ { "EnableOfdoVLAN", 3, 1 },
+ { "DisableTimeWait", 2, 1 },
+ { "EnableVlanCheck", 1, 1 },
+ { "TxDataAckPageEnable", 0, 1 },
+ { "TP_PC_CONFIG2", 0x7d4c, 0 },
+ { "EnableMtuVfMode", 31, 1 },
+ { "EnableMibVfMode", 30, 1 },
+ { "DisableLbkCheck", 29, 1 },
+ { "EnableUrgDdpOff", 28, 1 },
+ { "EnableFilterLpbk", 27, 1 },
+ { "DisableTblMmgr", 26, 1 },
+ { "CngRecSndNxt", 25, 1 },
+ { "EnableLbkChn", 24, 1 },
+ { "EnableLroEcn", 23, 1 },
+ { "EnablePcmdCheck", 22, 1 },
+ { "EnableELbkAFull", 21, 1 },
+ { "EnableCLbkAFull", 20, 1 },
+ { "EnableOespiFull", 19, 1 },
+ { "DisableHitCheck", 18, 1 },
+ { "EnableRssErrCheck", 17, 1 },
+ { "DisableNewPshFlag", 16, 1 },
+ { "EnableRddpRcvAdvClr", 15, 1 },
+ { "EnableFinDdpOff", 14, 1 },
+ { "EnableArpMiss", 13, 1 },
+ { "EnableRstPaws", 12, 1 },
+ { "EnableIPv6RSS", 11, 1 },
+ { "EnableNonOfdHybRss", 10, 1 },
+ { "EnableUDP4TupRss", 9, 1 },
+ { "EnableRxPktTmstpRss", 8, 1 },
+ { "EnableEPCMDAFull", 7, 1 },
+ { "EnableCPCMDAFull", 6, 1 },
+ { "EnableEHdrAFull", 5, 1 },
+ { "EnableCHdrAFull", 4, 1 },
+ { "EnableEMacAFull", 3, 1 },
+ { "EnableNonOfdTidRss", 2, 1 },
+ { "EnableNonOfdTcbRss", 1, 1 },
+ { "EnableTnlOfdClosed", 0, 1 },
+ { "TP_TCP_BACKOFF_REG0", 0x7d50, 0 },
+ { "TimerBackoffIndex3", 24, 8 },
+ { "TimerBackoffIndex2", 16, 8 },
+ { "TimerBackoffIndex1", 8, 8 },
+ { "TimerBackoffIndex0", 0, 8 },
+ { "TP_TCP_BACKOFF_REG1", 0x7d54, 0 },
+ { "TimerBackoffIndex7", 24, 8 },
+ { "TimerBackoffIndex6", 16, 8 },
+ { "TimerBackoffIndex5", 8, 8 },
+ { "TimerBackoffIndex4", 0, 8 },
+ { "TP_TCP_BACKOFF_REG2", 0x7d58, 0 },
+ { "TimerBackoffIndex11", 24, 8 },
+ { "TimerBackoffIndex10", 16, 8 },
+ { "TimerBackoffIndex9", 8, 8 },
+ { "TimerBackoffIndex8", 0, 8 },
+ { "TP_TCP_BACKOFF_REG3", 0x7d5c, 0 },
+ { "TimerBackoffIndex15", 24, 8 },
+ { "TimerBackoffIndex14", 16, 8 },
+ { "TimerBackoffIndex13", 8, 8 },
+ { "TimerBackoffIndex12", 0, 8 },
+ { "TP_PARA_REG0", 0x7d60, 0 },
+ { "LimTxThresh", 28, 4 },
+ { "InitCwndIdle", 27, 1 },
+ { "InitCwnd", 24, 3 },
+ { "DupAckThresh", 20, 4 },
+ { "ChnErrEnable", 14, 1 },
+ { "SetTimeEnable", 13, 1 },
+ { "CplErrEnable", 12, 1 },
+ { "FastTnlCnt", 11, 1 },
+ { "FastTblCnt", 10, 1 },
+ { "TpTcamKey", 9, 1 },
+ { "SwsMode", 8, 1 },
+ { "TsmpMode", 6, 2 },
+ { "ByteCountLimit", 4, 2 },
+ { "SwsShove", 3, 1 },
+ { "TblTimer", 2, 1 },
+ { "RxtPace", 1, 1 },
+ { "SwsTimer", 0, 1 },
+ { "TP_PARA_REG1", 0x7d64, 0 },
+ { "InitRwnd", 16, 16 },
+ { "InitialSSThresh", 0, 16 },
+ { "TP_PARA_REG2", 0x7d68, 0 },
+ { "MaxRxData", 16, 16 },
+ { "RxCoalesceSize", 0, 16 },
+ { "TP_PARA_REG3", 0x7d6c, 0 },
+ { "EnableTnlCngLpbk", 31, 1 },
+ { "EnableTnlCngFifo", 30, 1 },
+ { "EnableTnlCngHdr", 29, 1 },
+ { "EnableTnlCngSge", 28, 1 },
+ { "RxMacCheck", 27, 1 },
+ { "RxSynFilter", 26, 1 },
+ { "CngCtrlECN", 25, 1 },
+ { "RxDdpOffInit", 24, 1 },
+ { "TunnelCngDrop3", 23, 1 },
+ { "TunnelCngDrop2", 22, 1 },
+ { "TunnelCngDrop1", 21, 1 },
+ { "TunnelCngDrop0", 20, 1 },
+ { "TxDataAckIdx", 16, 4 },
+ { "RxFragEnable", 12, 3 },
+ { "TxPaceFixedStrict", 11, 1 },
+ { "TxPaceAutoStrict", 10, 1 },
+ { "TxPaceFixed", 9, 1 },
+ { "TxPaceAuto", 8, 1 },
+ { "RxChnTunnel", 7, 1 },
+ { "RxUrgTunnel", 6, 1 },
+ { "RxUrgMode", 5, 1 },
+ { "TxUrgMode", 4, 1 },
+ { "CngCtrlMode", 2, 2 },
+ { "RxCoalesceEnable", 1, 1 },
+ { "RxCoalescePshEn", 0, 1 },
+ { "TP_PARA_REG4", 0x7d70, 0 },
+ { "IdleCwndHighSpeed", 28, 1 },
+ { "RxmtCwndHighSpeed", 27, 1 },
+ { "OverdriveHighSpeed", 25, 2 },
+ { "ByteCountHighSpeed", 24, 1 },
+ { "IdleCwndNewReno", 20, 1 },
+ { "RxmtCwndNewReno", 19, 1 },
+ { "OverdriveNewReno", 17, 2 },
+ { "ByteCountNewReno", 16, 1 },
+ { "IdleCwndTahoe", 12, 1 },
+ { "RxmtCwndTahoe", 11, 1 },
+ { "OverdriveTahoe", 9, 2 },
+ { "ByteCountTahoe", 8, 1 },
+ { "IdleCwndReno", 4, 1 },
+ { "RxmtCwndReno", 3, 1 },
+ { "OverdriveReno", 1, 2 },
+ { "ByteCountReno", 0, 1 },
+ { "TP_PARA_REG5", 0x7d74, 0 },
+ { "IndicateSize", 16, 16 },
+ { "MaxProxySize", 12, 4 },
+ { "EnableReadPdu", 11, 1 },
+ { "EnableReadAhead", 10, 1 },
+ { "EmptyRqEnable", 9, 1 },
+ { "SchdEnable", 8, 1 },
+ { "EnableXoffPdu", 7, 1 },
+ { "EnableNewFar", 6, 1 },
+ { "EnableFragCheck", 5, 1 },
+ { "RearmDdpOffset", 4, 1 },
+ { "ResetDdpOffset", 3, 1 },
+ { "OnFlyDDPEnable", 2, 1 },
+ { "DackTimerSpin", 1, 1 },
+ { "PushTimerEnable", 0, 1 },
+ { "TP_PARA_REG6", 0x7d78, 0 },
+ { "TxPDUSizeAdj", 24, 8 },
+ { "DisablePDUAck", 20, 1 },
+ { "EnableCSav", 19, 1 },
+ { "EnableDeferPDU", 18, 1 },
+ { "EnableFlush", 17, 1 },
+ { "EnableBytePersist", 16, 1 },
+ { "DisableTmoCng", 15, 1 },
+ { "EnableReadAhead", 14, 1 },
+ { "AllowExeption", 13, 1 },
+ { "EnableDeferACK", 12, 1 },
+ { "EnableESnd", 11, 1 },
+ { "EnableCSnd", 10, 1 },
+ { "EnablePDUE", 9, 1 },
+ { "EnablePDUC", 8, 1 },
+ { "EnableBUFI", 7, 1 },
+ { "EnableBUFE", 6, 1 },
+ { "EnableDefer", 5, 1 },
+ { "EnableClearRxmtOos", 4, 1 },
+ { "DisablePDUCng", 3, 1 },
+ { "DisablePDUTimeout", 2, 1 },
+ { "DisablePDURxmt", 1, 1 },
+ { "DisablePDUxmt", 0, 1 },
+ { "TP_PARA_REG7", 0x7d7c, 0 },
+ { "PMMaxXferLen1", 16, 16 },
+ { "PMMaxXferLen0", 0, 16 },
+ { "TP_ENG_CONFIG", 0x7d80, 0 },
+ { "TableLatencyDone", 28, 4 },
+ { "TableLatencyStart", 24, 4 },
+ { "EngineLatencyDelta", 16, 4 },
+ { "EngineLatencyMmgr", 12, 4 },
+ { "EngineLatencyWireIp6", 8, 4 },
+ { "EngineLatencyWire", 4, 4 },
+ { "EngineLatencyBase", 0, 4 },
+ { "TP_ERR_CONFIG", 0x7d8c, 0 },
+ { "TnlErrorFPMA", 31, 1 },
+ { "TnlErrorPing", 30, 1 },
+ { "TnlErrorCsum", 29, 1 },
+ { "TnlErrorCsumIP", 28, 1 },
+ { "TnlErrorTcpOpt", 25, 1 },
+ { "TnlErrorPktLen", 24, 1 },
+ { "TnlErrorTcpHdrLen", 23, 1 },
+ { "TnlErrorIpHdrLen", 22, 1 },
+ { "TnlErrorEthHdrLen", 21, 1 },
+ { "TnlErrorAttack", 20, 1 },
+ { "TnlErrorFrag", 19, 1 },
+ { "TnlErrorIpVer", 18, 1 },
+ { "TnlErrorMac", 17, 1 },
+ { "TnlErrorAny", 16, 1 },
+ { "DropErrorFPMA", 15, 1 },
+ { "DropErrorPing", 14, 1 },
+ { "DropErrorCsum", 13, 1 },
+ { "DropErrorCsumIP", 12, 1 },
+ { "DropErrorTcpOpt", 9, 1 },
+ { "DropErrorPktLen", 8, 1 },
+ { "DropErrorTcpHdrLen", 7, 1 },
+ { "DropErrorIpHdrLen", 6, 1 },
+ { "DropErrorEthHdrLen", 5, 1 },
+ { "DropErrorAttack", 4, 1 },
+ { "DropErrorFrag", 3, 1 },
+ { "DropErrorIpVer", 2, 1 },
+ { "DropErrorMac", 1, 1 },
+ { "DropErrorAny", 0, 1 },
+ { "TP_TIMER_RESOLUTION", 0x7d90, 0 },
+ { "TimerResolution", 16, 8 },
+ { "TimestampResolution", 8, 8 },
+ { "DelayedACKResolution", 0, 8 },
+ { "TP_MSL", 0x7d94, 0 },
+ { "TP_RXT_MIN", 0x7d98, 0 },
+ { "TP_RXT_MAX", 0x7d9c, 0 },
+ { "TP_PERS_MIN", 0x7da0, 0 },
+ { "TP_PERS_MAX", 0x7da4, 0 },
+ { "TP_KEEP_IDLE", 0x7da8, 0 },
+ { "TP_KEEP_INTVL", 0x7dac, 0 },
+ { "TP_INIT_SRTT", 0x7db0, 0 },
+ { "MaxRtt", 16, 16 },
+ { "InitSrtt", 0, 16 },
+ { "TP_DACK_TIMER", 0x7db4, 0 },
+ { "TP_FINWAIT2_TIMER", 0x7db8, 0 },
+ { "TP_FAST_FINWAIT2_TIMER", 0x7dbc, 0 },
+ { "TP_SHIFT_CNT", 0x7dc0, 0 },
+ { "SynShiftMax", 24, 8 },
+ { "RxtShiftMaxR1", 20, 4 },
+ { "RxtShiftMaxR2", 16, 4 },
+ { "PerShiftBackoffMax", 12, 4 },
+ { "PerShiftMax", 8, 4 },
+ { "KeepaliveMaxR1", 4, 4 },
+ { "KeepaliveMaxR2", 0, 4 },
+ { "TP_TM_CONFIG", 0x7dc4, 0 },
+ { "TP_TIME_LO", 0x7dc8, 0 },
+ { "TP_TIME_HI", 0x7dcc, 0 },
+ { "TP_PORT_MTU_0", 0x7dd0, 0 },
+ { "Port1MTUValue", 16, 16 },
+ { "Port0MTUValue", 0, 16 },
+ { "TP_PORT_MTU_1", 0x7dd4, 0 },
+ { "Port3MTUValue", 16, 16 },
+ { "Port2MTUValue", 0, 16 },
+ { "TP_PACE_TABLE", 0x7dd8, 0 },
+ { "TP_CCTRL_TABLE", 0x7ddc, 0 },
+ { "RowIndex", 16, 16 },
+ { "RowValue", 0, 16 },
+ { "TP_MTU_TABLE", 0x7de4, 0 },
+ { "MTUIndex", 24, 8 },
+ { "MTUWidth", 16, 4 },
+ { "MTUValue", 0, 14 },
+ { "TP_ULP_TABLE", 0x7de8, 0 },
+ { "ULPType7Field", 28, 4 },
+ { "ULPType6Field", 24, 4 },
+ { "ULPType5Field", 20, 4 },
+ { "ULPType4Field", 16, 4 },
+ { "ULPType3Field", 12, 4 },
+ { "ULPType2Field", 8, 4 },
+ { "ULPType1Field", 4, 4 },
+ { "ULPType0Field", 0, 4 },
+ { "TP_RSS_LKP_TABLE", 0x7dec, 0 },
+ { "LkpTblRowVld", 31, 1 },
+ { "LkpTblRowIdx", 20, 10 },
+ { "LkpTblQueue1", 10, 10 },
+ { "LkpTblQueue0", 0, 10 },
+ { "TP_RSS_CONFIG", 0x7df0, 0 },
+ { "TNL4tupEnIpv6", 31, 1 },
+ { "TNL2tupEnIpv6", 30, 1 },
+ { "TNL4tupEnIpv4", 29, 1 },
+ { "TNL2tupEnIpv4", 28, 1 },
+ { "TNLTcpSel", 27, 1 },
+ { "TNLIp6Sel", 26, 1 },
+ { "TNLVrtSel", 25, 1 },
+ { "TNLMapEn", 24, 1 },
+ { "TNLFcoeMode", 23, 1 },
+ { "TNLFcoeEn", 21, 1 },
+ { "HashXor", 20, 1 },
+ { "OFDHashSave", 19, 1 },
+ { "OFDVrtSel", 18, 1 },
+ { "OFDMapEn", 17, 1 },
+ { "OFDLkpEn", 16, 1 },
+ { "SYN4tupEnIpv6", 15, 1 },
+ { "SYN2tupEnIpv6", 14, 1 },
+ { "SYN4tupEnIpv4", 13, 1 },
+ { "SYN2tupEnIpv4", 12, 1 },
+ { "SYNIp6Sel", 11, 1 },
+ { "SYNVrtSel", 10, 1 },
+ { "SYNMapEn", 9, 1 },
+ { "SYNLkpEn", 8, 1 },
+ { "ChannelEnable", 7, 1 },
+ { "PortEnable", 6, 1 },
+ { "TNLAllLookup", 5, 1 },
+ { "VirtEnable", 4, 1 },
+ { "CongestionEnable", 3, 1 },
+ { "HashToeplitz", 2, 1 },
+ { "UdpEnable", 1, 1 },
+ { "Disable", 0, 1 },
+ { "TP_RSS_CONFIG_TNL", 0x7df4, 0 },
+ { "MaskSize", 28, 4 },
+ { "MaskFilter", 16, 11 },
+ { "UseWireCh", 0, 1 },
+ { "TP_RSS_CONFIG_OFD", 0x7df8, 0 },
+ { "MaskSize", 28, 4 },
+ { "RRCPLMapEn", 20, 1 },
+ { "RRCPLQueWidth", 16, 4 },
+ { "FrmwrQueMask", 12, 4 },
+ { "TP_RSS_CONFIG_SYN", 0x7dfc, 0 },
+ { "MaskSize", 28, 4 },
+ { "UseWireCh", 0, 1 },
+ { "TP_RSS_CONFIG_VRT", 0x7e00, 0 },
+ { "VfRdRg", 25, 1 },
+ { "VfRdEn", 24, 1 },
+ { "VfPerrEn", 23, 1 },
+ { "KeyPerrEn", 22, 1 },
+ { "VfVlanEn", 21, 1 },
+ { "VfFwEn", 20, 1 },
+ { "HashDelay", 16, 4 },
+ { "VfWrAddr", 8, 7 },
+ { "KeyMode", 6, 2 },
+ { "VfWrEn", 5, 1 },
+ { "KeyWrEn", 4, 1 },
+ { "KeyWrAddr", 0, 4 },
+ { "TP_RSS_CONFIG_CNG", 0x7e04, 0 },
+ { "ChnCount3", 31, 1 },
+ { "ChnCount2", 30, 1 },
+ { "ChnCount1", 29, 1 },
+ { "ChnCount0", 28, 1 },
+ { "ChnUndFlow3", 27, 1 },
+ { "ChnUndFlow2", 26, 1 },
+ { "ChnUndFlow1", 25, 1 },
+ { "ChnUndFlow0", 24, 1 },
+ { "ChnOvrFlow3", 23, 1 },
+ { "ChnOvrFlow2", 22, 1 },
+ { "ChnOvrFlow1", 21, 1 },
+ { "ChnOvrFlow0", 20, 1 },
+ { "RstChn3", 19, 1 },
+ { "RstChn2", 18, 1 },
+ { "RstChn1", 17, 1 },
+ { "RstChn0", 16, 1 },
+ { "UpdVld", 15, 1 },
+ { "Xoff", 14, 1 },
+ { "UpdChn3", 13, 1 },
+ { "UpdChn2", 12, 1 },
+ { "UpdChn1", 11, 1 },
+ { "UpdChn0", 10, 1 },
+ { "Queue", 0, 10 },
+ { "TP_LA_TABLE_0", 0x7e10, 0 },
+ { "VirtPort1Table", 16, 16 },
+ { "VirtPort0Table", 0, 16 },
+ { "TP_LA_TABLE_1", 0x7e14, 0 },
+ { "VirtPort3Table", 16, 16 },
+ { "VirtPort2Table", 0, 16 },
+ { "TP_TM_PIO_ADDR", 0x7e18, 0 },
+ { "TP_TM_PIO_DATA", 0x7e1c, 0 },
+ { "TP_MOD_CONFIG", 0x7e24, 0 },
+ { "RxChannelWeight1", 24, 8 },
+ { "RXChannelWeight0", 16, 8 },
+ { "TimerMode", 8, 8 },
+ { "TxChannelXoffEn", 0, 4 },
+ { "TP_TX_MOD_QUEUE_REQ_MAP", 0x7e28, 0 },
+ { "RX_MOD_WEIGHT", 24, 8 },
+ { "TX_MOD_WEIGHT", 16, 8 },
+ { "TX_MOD_QUEUE_REQ_MAP", 0, 16 },
+ { "TP_TX_MOD_QUEUE_WEIGHT1", 0x7e2c, 0 },
+ { "TP_TX_MOD_QUEUE_WEIGHT7", 24, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT6", 16, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT5", 8, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT4", 0, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT0", 0x7e30, 0 },
+ { "TP_TX_MOD_QUEUE_WEIGHT3", 24, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT2", 16, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT1", 8, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT0", 0, 8 },
+ { "TP_TX_MOD_CHANNEL_WEIGHT", 0x7e34, 0 },
+ { "CH3", 24, 8 },
+ { "CH2", 16, 8 },
+ { "CH1", 8, 8 },
+ { "CH0", 0, 8 },
+ { "TP_MOD_RATE_LIMIT", 0x7e38, 0 },
+ { "RX_MOD_RATE_LIMIT_INC", 24, 8 },
+ { "RX_MOD_RATE_LIMIT_TICK", 16, 8 },
+ { "TX_MOD_RATE_LIMIT_INC", 8, 8 },
+ { "TX_MOD_RATE_LIMIT_TICK", 0, 8 },
+ { "TP_PIO_ADDR", 0x7e40, 0 },
+ { "TP_PIO_DATA", 0x7e44, 0 },
+ { "TP_RESET", 0x7e4c, 0 },
+ { "FlstInitEnable", 1, 1 },
+ { "TPReset", 0, 1 },
+ { "TP_MIB_INDEX", 0x7e50, 0 },
+ { "TP_MIB_DATA", 0x7e54, 0 },
+ { "TP_SYNC_TIME_HI", 0x7e58, 0 },
+ { "TP_SYNC_TIME_LO", 0x7e5c, 0 },
+ { "TP_CMM_MM_RX_FLST_BASE", 0x7e60, 0 },
+ { "TP_CMM_MM_TX_FLST_BASE", 0x7e64, 0 },
+ { "TP_CMM_MM_PS_FLST_BASE", 0x7e68, 0 },
+ { "TP_CMM_MM_MAX_PSTRUCT", 0x7e6c, 0 },
+ { "TP_INT_ENABLE", 0x7e70, 0 },
+ { "FlmTxFlstEmpty", 30, 1 },
+ { "RssLkpPerr", 29, 1 },
+ { "FlmPerrSet", 28, 1 },
+ { "ProtocolSramPerr", 27, 1 },
+ { "ArpLutPerr", 26, 1 },
+ { "CmRcfOpPerr", 25, 1 },
+ { "CmCachePerr", 24, 1 },
+ { "CmRcfDataPerr", 23, 1 },
+ { "DbL2tLutPerr", 22, 1 },
+ { "DbTxTidPerr", 21, 1 },
+ { "DbExtPerr", 20, 1 },
+ { "DbOpPerr", 19, 1 },
+ { "TmCachePerr", 18, 1 },
+ { "ETpOutCplFifoPerr", 17, 1 },
+ { "ETpOutTcpFifoPerr", 16, 1 },
+ { "ETpOutIpFifoPerr", 15, 1 },
+ { "ETpOutEthFifoPerr", 14, 1 },
+ { "ETpInCplFifoPerr", 13, 1 },
+ { "ETpInTcpOptFifoPerr", 12, 1 },
+ { "ETpInTcpFifoPerr", 11, 1 },
+ { "ETpInIpFifoPerr", 10, 1 },
+ { "ETpInEthFifoPerr", 9, 1 },
+ { "CTpOutCplFifoPerr", 8, 1 },
+ { "CTpOutPldFifoPerr", 7, 1 },
+ { "CTpOutIpFifoPerr", 6, 1 },
+ { "CTpOutEthFifoPerr", 5, 1 },
+ { "CTpInCplFifoPerr", 4, 1 },
+ { "CTpInTcpOpFifoPerr", 3, 1 },
+ { "PduFbkFifoPerr", 2, 1 },
+ { "CmOpExtFifoPerr", 1, 1 },
+ { "DelInvFifoPerr", 0, 1 },
+ { "TP_INT_CAUSE", 0x7e74, 0 },
+ { "FlmTxFlstEmpty", 30, 1 },
+ { "RssLkpPerr", 29, 1 },
+ { "FlmPerrSet", 28, 1 },
+ { "ProtocolSramPerr", 27, 1 },
+ { "ArpLutPerr", 26, 1 },
+ { "CmRcfOpPerr", 25, 1 },
+ { "CmCachePerr", 24, 1 },
+ { "CmRcfDataPerr", 23, 1 },
+ { "DbL2tLutPerr", 22, 1 },
+ { "DbTxTidPerr", 21, 1 },
+ { "DbExtPerr", 20, 1 },
+ { "DbOpPerr", 19, 1 },
+ { "TmCachePerr", 18, 1 },
+ { "ETpOutCplFifoPerr", 17, 1 },
+ { "ETpOutTcpFifoPerr", 16, 1 },
+ { "ETpOutIpFifoPerr", 15, 1 },
+ { "ETpOutEthFifoPerr", 14, 1 },
+ { "ETpInCplFifoPerr", 13, 1 },
+ { "ETpInTcpOptFifoPerr", 12, 1 },
+ { "ETpInTcpFifoPerr", 11, 1 },
+ { "ETpInIpFifoPerr", 10, 1 },
+ { "ETpInEthFifoPerr", 9, 1 },
+ { "CTpOutCplFifoPerr", 8, 1 },
+ { "CTpOutPldFifoPerr", 7, 1 },
+ { "CTpOutIpFifoPerr", 6, 1 },
+ { "CTpOutEthFifoPerr", 5, 1 },
+ { "CTpInCplFifoPerr", 4, 1 },
+ { "CTpInTcpOpFifoPerr", 3, 1 },
+ { "PduFbkFifoPerr", 2, 1 },
+ { "CmOpExtFifoPerr", 1, 1 },
+ { "DelInvFifoPerr", 0, 1 },
+ { "TP_PER_ENABLE", 0x7e78, 0 },
+ { "FlmTxFlstEmpty", 30, 1 },
+ { "RssLkpPerr", 29, 1 },
+ { "FlmPerrSet", 28, 1 },
+ { "ProtocolSramPerr", 27, 1 },
+ { "ArpLutPerr", 26, 1 },
+ { "CmRcfOpPerr", 25, 1 },
+ { "CmCachePerr", 24, 1 },
+ { "CmRcfDataPerr", 23, 1 },
+ { "DbL2tLutPerr", 22, 1 },
+ { "DbTxTidPerr", 21, 1 },
+ { "DbExtPerr", 20, 1 },
+ { "DbOpPerr", 19, 1 },
+ { "TmCachePerr", 18, 1 },
+ { "ETpOutCplFifoPerr", 17, 1 },
+ { "ETpOutTcpFifoPerr", 16, 1 },
+ { "ETpOutIpFifoPerr", 15, 1 },
+ { "ETpOutEthFifoPerr", 14, 1 },
+ { "ETpInCplFifoPerr", 13, 1 },
+ { "ETpInTcpOptFifoPerr", 12, 1 },
+ { "ETpInTcpFifoPerr", 11, 1 },
+ { "ETpInIpFifoPerr", 10, 1 },
+ { "ETpInEthFifoPerr", 9, 1 },
+ { "CTpOutCplFifoPerr", 8, 1 },
+ { "CTpOutPldFifoPerr", 7, 1 },
+ { "CTpOutIpFifoPerr", 6, 1 },
+ { "CTpOutEthFifoPerr", 5, 1 },
+ { "CTpInCplFifoPerr", 4, 1 },
+ { "CTpInTcpOpFifoPerr", 3, 1 },
+ { "PduFbkFifoPerr", 2, 1 },
+ { "CmOpExtFifoPerr", 1, 1 },
+ { "DelInvFifoPerr", 0, 1 },
+ { "TP_FLM_FREE_PS_CNT", 0x7e80, 0 },
+ { "TP_FLM_FREE_RX_CNT", 0x7e84, 0 },
+ { "FreeRxPageChn", 28, 1 },
+ { "FreeRxPageCount", 0, 21 },
+ { "TP_FLM_FREE_TX_CNT", 0x7e88, 0 },
+ { "FreeTxPageChn", 28, 2 },
+ { "FreeTxPageCount", 0, 21 },
+ { "TP_TM_HEAP_PUSH_CNT", 0x7e8c, 0 },
+ { "TP_TM_HEAP_POP_CNT", 0x7e90, 0 },
+ { "TP_TM_DACK_PUSH_CNT", 0x7e94, 0 },
+ { "TP_TM_DACK_POP_CNT", 0x7e98, 0 },
+ { "TP_TM_MOD_PUSH_CNT", 0x7e9c, 0 },
+ { "TP_MOD_POP_CNT", 0x7ea0, 0 },
+ { "TP_TIMER_SEPARATOR", 0x7ea4, 0 },
+ { "TimerSeparator", 16, 16 },
+ { "DisableTimeFreeze", 0, 1 },
+ { "TP_STAMP_TIME", 0x7ea8, 0 },
+ { "TP_DEBUG_FLAGS", 0x7eac, 0 },
+ { "RxTimerCompBuffer", 27, 1 },
+ { "RxTimerDackFirst", 26, 1 },
+ { "RxTimerDack", 25, 1 },
+ { "RxTimerHeartbeat", 24, 1 },
+ { "RxPawsDrop", 23, 1 },
+ { "RxUrgDataDrop", 22, 1 },
+ { "RxFutureData", 21, 1 },
+ { "RxRcvRxmData", 20, 1 },
+ { "RxRcvOooDataFin", 19, 1 },
+ { "RxRcvOooData", 18, 1 },
+ { "RxRcvWndZero", 17, 1 },
+ { "RxRcvWndLtMss", 16, 1 },
+ { "TxDfrFast", 13, 1 },
+ { "TxRxmMisc", 12, 1 },
+ { "TxDupAckInc", 11, 1 },
+ { "TxRxmUrg", 10, 1 },
+ { "TxRxmFin", 9, 1 },
+ { "TxRxmSyn", 8, 1 },
+ { "TxRxmNewReno", 7, 1 },
+ { "TxRxmFast", 6, 1 },
+ { "TxRxmTimer", 5, 1 },
+ { "TxRxmTimerKeepalive", 4, 1 },
+ { "TxRxmTimerPersist", 3, 1 },
+ { "TxRcvAdvShrunk", 2, 1 },
+ { "TxRcvAdvZero", 1, 1 },
+ { "TxRcvAdvLtMss", 0, 1 },
+ { "TP_RX_SCHED", 0x7eb0, 0 },
+ { "CommitReset1", 31, 1 },
+ { "CommitReset0", 30, 1 },
+ { "ForceCong1", 29, 1 },
+ { "ForceCong0", 28, 1 },
+ { "EnableLpbkFull1", 26, 2 },
+ { "EnableLpbkFull0", 24, 2 },
+ { "EnableFifoFull1", 22, 2 },
+ { "EnablePcmdFull1", 20, 2 },
+ { "EnableHdrFull1", 18, 2 },
+ { "EnableFifoFull0", 16, 2 },
+ { "EnablePcmdFull0", 14, 2 },
+ { "EnableHdrFull0", 12, 2 },
+ { "TP_TX_SCHED", 0x7eb4, 0 },
+ { "CommitReset3", 31, 1 },
+ { "CommitReset2", 30, 1 },
+ { "CommitReset1", 29, 1 },
+ { "CommitReset0", 28, 1 },
+ { "ForceCong3", 27, 1 },
+ { "ForceCong2", 26, 1 },
+ { "ForceCong1", 25, 1 },
+ { "ForceCong0", 24, 1 },
+ { "CommitLimit3", 18, 6 },
+ { "CommitLimit2", 12, 6 },
+ { "CommitLimit1", 6, 6 },
+ { "CommitLimit0", 0, 6 },
+ { "TP_FX_SCHED", 0x7eb8, 0 },
+ { "TxChnXoff3", 19, 1 },
+ { "TxChnXoff2", 18, 1 },
+ { "TxChnXoff1", 17, 1 },
+ { "TxChnXoff0", 16, 1 },
+ { "TxModXoff7", 15, 1 },
+ { "TxModXoff6", 14, 1 },
+ { "TxModXoff5", 13, 1 },
+ { "TxModXoff4", 12, 1 },
+ { "TxModXoff3", 11, 1 },
+ { "TxModXoff2", 10, 1 },
+ { "TxModXoff1", 9, 1 },
+ { "TxModXoff0", 8, 1 },
+ { "RxChnXoff3", 7, 1 },
+ { "RxChnXoff2", 6, 1 },
+ { "RxChnXoff1", 5, 1 },
+ { "RxChnXoff0", 4, 1 },
+ { "RxModXoff1", 1, 1 },
+ { "RxModXoff0", 0, 1 },
+ { "TP_TX_ORATE", 0x7ebc, 0 },
+ { "OfdRate3", 24, 8 },
+ { "OfdRate2", 16, 8 },
+ { "OfdRate1", 8, 8 },
+ { "OfdRate0", 0, 8 },
+ { "TP_IX_SCHED0", 0x7ec0, 0 },
+ { "TP_IX_SCHED1", 0x7ec4, 0 },
+ { "TP_IX_SCHED2", 0x7ec8, 0 },
+ { "TP_IX_SCHED3", 0x7ecc, 0 },
+ { "TP_TX_TRATE", 0x7ed0, 0 },
+ { "TnlRate3", 24, 8 },
+ { "TnlRate2", 16, 8 },
+ { "TnlRate1", 8, 8 },
+ { "TnlRate0", 0, 8 },
+ { "TP_DBG_LA_CONFIG", 0x7ed4, 0 },
+ { "DbgLaOpcEnable", 24, 8 },
+ { "DbgLaWhlf", 23, 1 },
+ { "DbgLaWptr", 16, 7 },
+ { "DbgLaMode", 14, 2 },
+ { "DbgLaFatalFreeze", 13, 1 },
+ { "DbgLaEnable", 12, 1 },
+ { "DbgLaRptr", 0, 7 },
+ { "TP_DBG_LA_DATAL", 0x7ed8, 0 },
+ { "TP_DBG_LA_DATAH", 0x7edc, 0 },
+ { "TP_PROTOCOL_CNTRL", 0x7ee8, 0 },
+ { "WriteEnable", 31, 1 },
+ { "TcamEnable", 10, 1 },
+ { "BlockSelect", 8, 2 },
+ { "LineAddress", 1, 7 },
+ { "RequestDone", 0, 1 },
+ { "TP_PROTOCOL_DATA0", 0x7eec, 0 },
+ { "TP_PROTOCOL_DATA1", 0x7ef0, 0 },
+ { "TP_PROTOCOL_DATA2", 0x7ef4, 0 },
+ { "TP_PROTOCOL_DATA3", 0x7ef8, 0 },
+ { "TP_PROTOCOL_DATA4", 0x7efc, 0 },
+ { NULL }
+};
+
+struct reg_info t5_ulp_tx_regs[] = {
+ { "ULP_TX_CONFIG", 0x8dc0, 0 },
+ { "PHYS_ADDR_RESP_EN", 6, 1 },
+ { "ENDIANESS_CHANGE", 5, 1 },
+ { "ERR_RTAG_EN", 4, 1 },
+ { "TSO_ETHLEN_EN", 3, 1 },
+ { "emsg_more_info", 2, 1 },
+ { "LOSDR", 1, 1 },
+ { "extra_tag_insertion_enable", 0, 1 },
+ { "ULP_TX_PERR_INJECT", 0x8dc4, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "ULP_TX_INT_ENABLE", 0x8dc8, 0 },
+ { "Pbl_bound_err_ch3", 31, 1 },
+ { "Pbl_bound_err_ch2", 30, 1 },
+ { "Pbl_bound_err_ch1", 29, 1 },
+ { "Pbl_bound_err_ch0", 28, 1 },
+ { "sge2ulp_fifo_perr_set3", 27, 1 },
+ { "sge2ulp_fifo_perr_set2", 26, 1 },
+ { "sge2ulp_fifo_perr_set1", 25, 1 },
+ { "sge2ulp_fifo_perr_set0", 24, 1 },
+ { "cim2ulp_fifo_perr_set3", 23, 1 },
+ { "cim2ulp_fifo_perr_set2", 22, 1 },
+ { "cim2ulp_fifo_perr_set1", 21, 1 },
+ { "cim2ulp_fifo_perr_set0", 20, 1 },
+ { "CQE_fifo_perr_set3", 19, 1 },
+ { "CQE_fifo_perr_set2", 18, 1 },
+ { "CQE_fifo_perr_set1", 17, 1 },
+ { "CQE_fifo_perr_set0", 16, 1 },
+ { "pbl_fifo_perr_set3", 15, 1 },
+ { "pbl_fifo_perr_set2", 14, 1 },
+ { "pbl_fifo_perr_set1", 13, 1 },
+ { "pbl_fifo_perr_set0", 12, 1 },
+ { "cmd_fifo_perr_set3", 11, 1 },
+ { "cmd_fifo_perr_set2", 10, 1 },
+ { "cmd_fifo_perr_set1", 9, 1 },
+ { "cmd_fifo_perr_set0", 8, 1 },
+ { "lso_hdr_sram_perr_set3", 7, 1 },
+ { "lso_hdr_sram_perr_set2", 6, 1 },
+ { "lso_hdr_sram_perr_set1", 5, 1 },
+ { "lso_hdr_sram_perr_set0", 4, 1 },
+ { "ULP_TX_INT_CAUSE", 0x8dcc, 0 },
+ { "Pbl_bound_err_ch3", 31, 1 },
+ { "Pbl_bound_err_ch2", 30, 1 },
+ { "Pbl_bound_err_ch1", 29, 1 },
+ { "Pbl_bound_err_ch0", 28, 1 },
+ { "sge2ulp_fifo_perr_set3", 27, 1 },
+ { "sge2ulp_fifo_perr_set2", 26, 1 },
+ { "sge2ulp_fifo_perr_set1", 25, 1 },
+ { "sge2ulp_fifo_perr_set0", 24, 1 },
+ { "cim2ulp_fifo_perr_set3", 23, 1 },
+ { "cim2ulp_fifo_perr_set2", 22, 1 },
+ { "cim2ulp_fifo_perr_set1", 21, 1 },
+ { "cim2ulp_fifo_perr_set0", 20, 1 },
+ { "CQE_fifo_perr_set3", 19, 1 },
+ { "CQE_fifo_perr_set2", 18, 1 },
+ { "CQE_fifo_perr_set1", 17, 1 },
+ { "CQE_fifo_perr_set0", 16, 1 },
+ { "pbl_fifo_perr_set3", 15, 1 },
+ { "pbl_fifo_perr_set2", 14, 1 },
+ { "pbl_fifo_perr_set1", 13, 1 },
+ { "pbl_fifo_perr_set0", 12, 1 },
+ { "cmd_fifo_perr_set3", 11, 1 },
+ { "cmd_fifo_perr_set2", 10, 1 },
+ { "cmd_fifo_perr_set1", 9, 1 },
+ { "cmd_fifo_perr_set0", 8, 1 },
+ { "lso_hdr_sram_perr_set3", 7, 1 },
+ { "lso_hdr_sram_perr_set2", 6, 1 },
+ { "lso_hdr_sram_perr_set1", 5, 1 },
+ { "lso_hdr_sram_perr_set0", 4, 1 },
+ { "ULP_TX_PERR_ENABLE", 0x8dd0, 0 },
+ { "sge2ulp_fifo_perr_set3", 27, 1 },
+ { "sge2ulp_fifo_perr_set2", 26, 1 },
+ { "sge2ulp_fifo_perr_set1", 25, 1 },
+ { "sge2ulp_fifo_perr_set0", 24, 1 },
+ { "cim2ulp_fifo_perr_set3", 23, 1 },
+ { "cim2ulp_fifo_perr_set2", 22, 1 },
+ { "cim2ulp_fifo_perr_set1", 21, 1 },
+ { "cim2ulp_fifo_perr_set0", 20, 1 },
+ { "CQE_fifo_perr_set3", 19, 1 },
+ { "CQE_fifo_perr_set2", 18, 1 },
+ { "CQE_fifo_perr_set1", 17, 1 },
+ { "CQE_fifo_perr_set0", 16, 1 },
+ { "pbl_fifo_perr_set3", 15, 1 },
+ { "pbl_fifo_perr_set2", 14, 1 },
+ { "pbl_fifo_perr_set1", 13, 1 },
+ { "pbl_fifo_perr_set0", 12, 1 },
+ { "cmd_fifo_perr_set3", 11, 1 },
+ { "cmd_fifo_perr_set2", 10, 1 },
+ { "cmd_fifo_perr_set1", 9, 1 },
+ { "cmd_fifo_perr_set0", 8, 1 },
+ { "lso_hdr_sram_perr_set3", 7, 1 },
+ { "lso_hdr_sram_perr_set2", 6, 1 },
+ { "lso_hdr_sram_perr_set1", 5, 1 },
+ { "lso_hdr_sram_perr_set0", 4, 1 },
+ { "ULP_TX_TPT_LLIMIT", 0x8dd4, 0 },
+ { "ULP_TX_TPT_ULIMIT", 0x8dd8, 0 },
+ { "ULP_TX_PBL_LLIMIT", 0x8ddc, 0 },
+ { "ULP_TX_PBL_ULIMIT", 0x8de0, 0 },
+ { "ULP_TX_CPL_PACK_SIZE1", 0x8df8, 0 },
+ { "Ch3Size1", 24, 8 },
+ { "Ch2Size1", 16, 8 },
+ { "Ch1Size1", 8, 8 },
+ { "Ch0Size1", 0, 8 },
+ { "ULP_TX_CPL_PACK_SIZE2", 0x8dfc, 0 },
+ { "Ch3Size2", 24, 8 },
+ { "Ch2Size2", 16, 8 },
+ { "Ch1Size2", 8, 8 },
+ { "Ch0Size2", 0, 8 },
+ { "ULP_TX_ERR_MSG2CIM", 0x8e00, 0 },
+ { "ULP_TX_ERR_TABLE_BASE", 0x8e04, 0 },
+ { "ULP_TX_ERR_CNT_CH0", 0x8e10, 0 },
+ { "ULP_TX_ERR_CNT_CH1", 0x8e14, 0 },
+ { "ULP_TX_ERR_CNT_CH2", 0x8e18, 0 },
+ { "ULP_TX_ERR_CNT_CH3", 0x8e1c, 0 },
+ { "ULP_TX_FC_SOF", 0x8e20, 0 },
+ { "SOF_FS3", 24, 8 },
+ { "SOF_FS2", 16, 8 },
+ { "SOF_3", 8, 8 },
+ { "SOF_2", 0, 8 },
+ { "ULP_TX_FC_EOF", 0x8e24, 0 },
+ { "EOF_LS3", 24, 8 },
+ { "EOF_LS2", 16, 8 },
+ { "EOF_3", 8, 8 },
+ { "EOF_2", 0, 8 },
+ { "ULP_TX_CGEN_GLOBAL", 0x8e28, 0 },
+ { "ULP_TX_CGEN", 0x8e2c, 0 },
+ { "ULP_TX_CGEN_Storage", 8, 4 },
+ { "ULP_TX_CGEN_RDMA", 4, 4 },
+ { "ULP_TX_CGEN_Channel", 0, 4 },
+ { "ULP_TX_MEM_CFG", 0x8e30, 0 },
+ { "ULP_TX_PERR_INJECT_2", 0x8e34, 0 },
+ { "MemSel", 1, 3 },
+ { "InjectDataErr", 0, 1 },
+ { "ULP_TX_INT_ENABLE_2", 0x8e7c, 0 },
+ { "smarbt2ulp_data_perr_set", 12, 1 },
+ { "ulp2tp_data_perr_set", 11, 1 },
+ { "ma2ulp_data_perr_set", 10, 1 },
+ { "sge2ulp_data_perr_set", 9, 1 },
+ { "cim2ulp_data_perr_set", 8, 1 },
+ { "fso_hdr_sram_perr_set3", 7, 1 },
+ { "fso_hdr_sram_perr_set2", 6, 1 },
+ { "fso_hdr_sram_perr_set1", 5, 1 },
+ { "fso_hdr_sram_perr_set0", 4, 1 },
+ { "t10_pi_sram_perr_set3", 3, 1 },
+ { "t10_pi_sram_perr_set2", 2, 1 },
+ { "t10_pi_sram_perr_set1", 1, 1 },
+ { "t10_pi_sram_perr_set0", 0, 1 },
+ { "ULP_TX_INT_CAUSE_2", 0x8e80, 0 },
+ { "smarbt2ulp_data_perr_set", 12, 1 },
+ { "ulp2tp_data_perr_set", 11, 1 },
+ { "ma2ulp_data_perr_set", 10, 1 },
+ { "sge2ulp_data_perr_set", 9, 1 },
+ { "cim2ulp_data_perr_set", 8, 1 },
+ { "fso_hdr_sram_perr_set3", 7, 1 },
+ { "fso_hdr_sram_perr_set2", 6, 1 },
+ { "fso_hdr_sram_perr_set1", 5, 1 },
+ { "fso_hdr_sram_perr_set0", 4, 1 },
+ { "t10_pi_sram_perr_set3", 3, 1 },
+ { "t10_pi_sram_perr_set2", 2, 1 },
+ { "t10_pi_sram_perr_set1", 1, 1 },
+ { "t10_pi_sram_perr_set0", 0, 1 },
+ { "ULP_TX_PERR_ENABLE_2", 0x8e84, 0 },
+ { "smarbt2ulp_data_perr_set", 12, 1 },
+ { "ulp2tp_data_perr_set", 11, 1 },
+ { "ma2ulp_data_perr_set", 10, 1 },
+ { "sge2ulp_data_perr_set", 9, 1 },
+ { "cim2ulp_data_perr_set", 8, 1 },
+ { "fso_hdr_sram_perr_set3", 7, 1 },
+ { "fso_hdr_sram_perr_set2", 6, 1 },
+ { "fso_hdr_sram_perr_set1", 5, 1 },
+ { "fso_hdr_sram_perr_set0", 4, 1 },
+ { "t10_pi_sram_perr_set3", 3, 1 },
+ { "t10_pi_sram_perr_set2", 2, 1 },
+ { "t10_pi_sram_perr_set1", 1, 1 },
+ { "t10_pi_sram_perr_set0", 0, 1 },
+ { "ULP_TX_SE_CNT_ERR", 0x8ea0, 0 },
+ { "ERR_CH3", 12, 4 },
+ { "ERR_CH2", 8, 4 },
+ { "ERR_CH1", 4, 4 },
+ { "ERR_CH0", 0, 4 },
+ { "ULP_TX_SE_CNT_CLR", 0x8ea4, 0 },
+ { "CLR_DROP", 16, 4 },
+ { "CLR_CH3", 12, 4 },
+ { "CLR_CH2", 8, 4 },
+ { "CLR_CH1", 4, 4 },
+ { "CLR_CH0", 0, 4 },
+ { "ULP_TX_SE_CNT_CH0", 0x8ea8, 0 },
+ { "SOP_CNT_ULP2TP", 28, 4 },
+ { "EOP_CNT_ULP2TP", 24, 4 },
+ { "SOP_CNT_LSO_IN", 20, 4 },
+ { "EOP_CNT_LSO_IN", 16, 4 },
+ { "SOP_CNT_ALG_IN", 12, 4 },
+ { "EOP_CNT_ALG_IN", 8, 4 },
+ { "SOP_CNT_CIM2ULP", 4, 4 },
+ { "EOP_CNT_CIM2ULP", 0, 4 },
+ { "ULP_TX_SE_CNT_CH1", 0x8eac, 0 },
+ { "SOP_CNT_ULP2TP", 28, 4 },
+ { "EOP_CNT_ULP2TP", 24, 4 },
+ { "SOP_CNT_LSO_IN", 20, 4 },
+ { "EOP_CNT_LSO_IN", 16, 4 },
+ { "SOP_CNT_ALG_IN", 12, 4 },
+ { "EOP_CNT_ALG_IN", 8, 4 },
+ { "SOP_CNT_CIM2ULP", 4, 4 },
+ { "EOP_CNT_CIM2ULP", 0, 4 },
+ { "ULP_TX_SE_CNT_CH2", 0x8eb0, 0 },
+ { "SOP_CNT_ULP2TP", 28, 4 },
+ { "EOP_CNT_ULP2TP", 24, 4 },
+ { "SOP_CNT_LSO_IN", 20, 4 },
+ { "EOP_CNT_LSO_IN", 16, 4 },
+ { "SOP_CNT_ALG_IN", 12, 4 },
+ { "EOP_CNT_ALG_IN", 8, 4 },
+ { "SOP_CNT_CIM2ULP", 4, 4 },
+ { "EOP_CNT_CIM2ULP", 0, 4 },
+ { "ULP_TX_SE_CNT_CH3", 0x8eb4, 0 },
+ { "SOP_CNT_ULP2TP", 28, 4 },
+ { "EOP_CNT_ULP2TP", 24, 4 },
+ { "SOP_CNT_LSO_IN", 20, 4 },
+ { "EOP_CNT_LSO_IN", 16, 4 },
+ { "SOP_CNT_ALG_IN", 12, 4 },
+ { "EOP_CNT_ALG_IN", 8, 4 },
+ { "SOP_CNT_CIM2ULP", 4, 4 },
+ { "EOP_CNT_CIM2ULP", 0, 4 },
+ { "ULP_TX_DROP_CNT", 0x8eb8, 0 },
+ { "DROP_CH3", 12, 4 },
+ { "DROP_CH2", 8, 4 },
+ { "DROP_CH1", 4, 4 },
+ { "DROP_CH0", 0, 4 },
+ { "ULP_TX_FPGA_CMD_CTRL", 0x8e38, 0 },
+ { "channel_sel", 12, 2 },
+ { "intf_sel", 4, 4 },
+ { "num_flits", 1, 3 },
+ { "cmd_gen_en", 0, 1 },
+ { "ULP_TX_FPGA_CMD_0", 0x8e3c, 0 },
+ { "ULP_TX_FPGA_CMD_1", 0x8e40, 0 },
+ { "ULP_TX_FPGA_CMD_2", 0x8e44, 0 },
+ { "ULP_TX_FPGA_CMD_3", 0x8e48, 0 },
+ { "ULP_TX_FPGA_CMD_4", 0x8e4c, 0 },
+ { "ULP_TX_FPGA_CMD_5", 0x8e50, 0 },
+ { "ULP_TX_FPGA_CMD_6", 0x8e54, 0 },
+ { "ULP_TX_FPGA_CMD_7", 0x8e58, 0 },
+ { "ULP_TX_FPGA_CMD_8", 0x8e5c, 0 },
+ { "ULP_TX_FPGA_CMD_9", 0x8e60, 0 },
+ { "ULP_TX_FPGA_CMD_10", 0x8e64, 0 },
+ { "ULP_TX_FPGA_CMD_11", 0x8e68, 0 },
+ { "ULP_TX_FPGA_CMD_12", 0x8e6c, 0 },
+ { "ULP_TX_FPGA_CMD_13", 0x8e70, 0 },
+ { "ULP_TX_FPGA_CMD_14", 0x8e74, 0 },
+ { "ULP_TX_FPGA_CMD_15", 0x8e78, 0 },
+ { "ULP_TX_ASIC_DEBUG_CTRL", 0x8f70, 0 },
+ { "ULP_TX_ASIC_DEBUG_0", 0x8f74, 0 },
+ { "ULP_TX_ASIC_DEBUG_1", 0x8f78, 0 },
+ { "ULP_TX_ASIC_DEBUG_2", 0x8f7c, 0 },
+ { "ULP_TX_ASIC_DEBUG_3", 0x8f80, 0 },
+ { "ULP_TX_ASIC_DEBUG_4", 0x8f84, 0 },
+ { "ULP_TX_CSU_REVISION", 0x8ebc, 0 },
+ { "ULP_TX_LA_RDPTR_0", 0x8ec0, 0 },
+ { "ULP_TX_LA_RDDATA_0", 0x8ec4, 0 },
+ { "ULP_TX_LA_WRPTR_0", 0x8ec8, 0 },
+ { "ULP_TX_LA_RESERVED_0", 0x8ecc, 0 },
+ { "ULP_TX_LA_RDPTR_1", 0x8ed0, 0 },
+ { "ULP_TX_LA_RDDATA_1", 0x8ed4, 0 },
+ { "ULP_TX_LA_WRPTR_1", 0x8ed8, 0 },
+ { "ULP_TX_LA_RESERVED_1", 0x8edc, 0 },
+ { "ULP_TX_LA_RDPTR_2", 0x8ee0, 0 },
+ { "ULP_TX_LA_RDDATA_2", 0x8ee4, 0 },
+ { "ULP_TX_LA_WRPTR_2", 0x8ee8, 0 },
+ { "ULP_TX_LA_RESERVED_2", 0x8eec, 0 },
+ { "ULP_TX_LA_RDPTR_3", 0x8ef0, 0 },
+ { "ULP_TX_LA_RDDATA_3", 0x8ef4, 0 },
+ { "ULP_TX_LA_WRPTR_3", 0x8ef8, 0 },
+ { "ULP_TX_LA_RESERVED_3", 0x8efc, 0 },
+ { "ULP_TX_LA_RDPTR_4", 0x8f00, 0 },
+ { "ULP_TX_LA_RDDATA_4", 0x8f04, 0 },
+ { "ULP_TX_LA_WRPTR_4", 0x8f08, 0 },
+ { "ULP_TX_LA_RESERVED_4", 0x8f0c, 0 },
+ { "ULP_TX_LA_RDPTR_5", 0x8f10, 0 },
+ { "ULP_TX_LA_RDDATA_5", 0x8f14, 0 },
+ { "ULP_TX_LA_WRPTR_5", 0x8f18, 0 },
+ { "ULP_TX_LA_RESERVED_5", 0x8f1c, 0 },
+ { "ULP_TX_LA_RDPTR_6", 0x8f20, 0 },
+ { "ULP_TX_LA_RDDATA_6", 0x8f24, 0 },
+ { "ULP_TX_LA_WRPTR_6", 0x8f28, 0 },
+ { "ULP_TX_LA_RESERVED_6", 0x8f2c, 0 },
+ { "ULP_TX_LA_RDPTR_7", 0x8f30, 0 },
+ { "ULP_TX_LA_RDDATA_7", 0x8f34, 0 },
+ { "ULP_TX_LA_WRPTR_7", 0x8f38, 0 },
+ { "ULP_TX_LA_RESERVED_7", 0x8f3c, 0 },
+ { "ULP_TX_LA_RDPTR_8", 0x8f40, 0 },
+ { "ULP_TX_LA_RDDATA_8", 0x8f44, 0 },
+ { "ULP_TX_LA_WRPTR_8", 0x8f48, 0 },
+ { "ULP_TX_LA_RESERVED_8", 0x8f4c, 0 },
+ { "ULP_TX_LA_RDPTR_9", 0x8f50, 0 },
+ { "ULP_TX_LA_RDDATA_9", 0x8f54, 0 },
+ { "ULP_TX_LA_WRPTR_9", 0x8f58, 0 },
+ { "ULP_TX_LA_RESERVED_9", 0x8f5c, 0 },
+ { "ULP_TX_LA_RDPTR_10", 0x8f60, 0 },
+ { "ULP_TX_LA_RDDATA_10", 0x8f64, 0 },
+ { "ULP_TX_LA_WRPTR_10", 0x8f68, 0 },
+ { "ULP_TX_LA_RESERVED_10", 0x8f6c, 0 },
+ { NULL }
+};
+
+struct reg_info t5_pm_rx_regs[] = {
+ { "PM_RX_CFG", 0x8fc0, 0 },
+ { "ch1_output", 27, 5 },
+ { "strobe1", 16, 1 },
+ { "ch1_input", 11, 5 },
+ { "ch2_input", 6, 5 },
+ { "ch3_input", 1, 5 },
+ { "strobe0", 0, 1 },
+ { "PM_RX_MODE", 0x8fc4, 0 },
+ { "use_bundle_len", 4, 1 },
+ { "stat_to_ch", 3, 1 },
+ { "stat_from_ch", 1, 2 },
+ { "prefetch_enable", 0, 1 },
+ { "PM_RX_STAT_CONFIG", 0x8fc8, 0 },
+ { "PM_RX_STAT_COUNT", 0x8fcc, 0 },
+ { "PM_RX_DBG_CTRL", 0x8fd0, 0 },
+ { "OspiWrBusy", 21, 2 },
+ { "IspiWrBusy", 17, 4 },
+ { "PMDbgAddr", 0, 17 },
+ { "PM_RX_DBG_DATA", 0x8fd4, 0 },
+ { "PM_RX_INT_ENABLE", 0x8fd8, 0 },
+ { "ospi_overflow1", 28, 1 },
+ { "ospi_overflow0", 27, 1 },
+ { "ma_intf_sdc_err", 26, 1 },
+ { "bundle_len_ParErr", 25, 1 },
+ { "bundle_len_ovfl", 24, 1 },
+ { "sdc_err", 23, 1 },
+ { "zero_e_cmd_error", 22, 1 },
+ { "iespi0_fifo2x_Rx_framing_error", 21, 1 },
+ { "iespi1_fifo2x_Rx_framing_error", 20, 1 },
+ { "iespi2_fifo2x_Rx_framing_error", 19, 1 },
+ { "iespi3_fifo2x_Rx_framing_error", 18, 1 },
+ { "iespi0_Rx_framing_error", 17, 1 },
+ { "iespi1_Rx_framing_error", 16, 1 },
+ { "iespi2_Rx_framing_error", 15, 1 },
+ { "iespi3_Rx_framing_error", 14, 1 },
+ { "iespi0_Tx_framing_error", 13, 1 },
+ { "iespi1_Tx_framing_error", 12, 1 },
+ { "iespi2_Tx_framing_error", 11, 1 },
+ { "iespi3_Tx_framing_error", 10, 1 },
+ { "ocspi0_Rx_framing_error", 9, 1 },
+ { "ocspi1_Rx_framing_error", 8, 1 },
+ { "ocspi0_Tx_framing_error", 7, 1 },
+ { "ocspi1_Tx_framing_error", 6, 1 },
+ { "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
+ { "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
+ { "ocspi_par_error", 3, 1 },
+ { "db_options_par_error", 2, 1 },
+ { "iespi_par_error", 1, 1 },
+ { "e_pcmd_par_error", 0, 1 },
+ { "PM_RX_INT_CAUSE", 0x8fdc, 0 },
+ { "ospi_overflow1", 28, 1 },
+ { "ospi_overflow0", 27, 1 },
+ { "ma_intf_sdc_err", 26, 1 },
+ { "bundle_len_ParErr", 25, 1 },
+ { "bundle_len_ovfl", 24, 1 },
+ { "sdc_err", 23, 1 },
+ { "zero_e_cmd_error", 22, 1 },
+ { "iespi0_fifo2x_Rx_framing_error", 21, 1 },
+ { "iespi1_fifo2x_Rx_framing_error", 20, 1 },
+ { "iespi2_fifo2x_Rx_framing_error", 19, 1 },
+ { "iespi3_fifo2x_Rx_framing_error", 18, 1 },
+ { "iespi0_Rx_framing_error", 17, 1 },
+ { "iespi1_Rx_framing_error", 16, 1 },
+ { "iespi2_Rx_framing_error", 15, 1 },
+ { "iespi3_Rx_framing_error", 14, 1 },
+ { "iespi0_Tx_framing_error", 13, 1 },
+ { "iespi1_Tx_framing_error", 12, 1 },
+ { "iespi2_Tx_framing_error", 11, 1 },
+ { "iespi3_Tx_framing_error", 10, 1 },
+ { "ocspi0_Rx_framing_error", 9, 1 },
+ { "ocspi1_Rx_framing_error", 8, 1 },
+ { "ocspi0_Tx_framing_error", 7, 1 },
+ { "ocspi1_Tx_framing_error", 6, 1 },
+ { "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
+ { "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
+ { "ocspi_par_error", 3, 1 },
+ { "db_options_par_error", 2, 1 },
+ { "iespi_par_error", 1, 1 },
+ { "e_pcmd_par_error", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t5_pm_tx_regs[] = {
+ { "PM_TX_CFG", 0x8fe0, 0 },
+ { "ch1_output", 27, 5 },
+ { "ch2_output", 22, 5 },
+ { "ch3_output", 17, 5 },
+ { "strobe1", 16, 1 },
+ { "ch1_input", 11, 5 },
+ { "ch2_input", 6, 5 },
+ { "ch3_input", 1, 5 },
+ { "strobe0", 0, 1 },
+ { "PM_TX_MODE", 0x8fe4, 0 },
+ { "cong_thresh3", 25, 7 },
+ { "cong_thresh2", 18, 7 },
+ { "cong_thresh1", 11, 7 },
+ { "cong_thresh0", 4, 7 },
+ { "use_bundle_len", 3, 1 },
+ { "stat_channel", 1, 2 },
+ { "prefetch_enable", 0, 1 },
+ { "PM_TX_STAT_CONFIG", 0x8fe8, 0 },
+ { "PM_TX_STAT_COUNT", 0x8fec, 0 },
+ { "PM_TX_DBG_CTRL", 0x8ff0, 0 },
+ { "OspiWrBusy", 21, 4 },
+ { "IspiWrBusy", 17, 4 },
+ { "PMDbgAddr", 0, 17 },
+ { "PM_TX_DBG_DATA", 0x8ff4, 0 },
+ { "PM_TX_INT_ENABLE", 0x8ff8, 0 },
+ { "pcmd_len_ovfl0", 31, 1 },
+ { "pcmd_len_ovfl1", 30, 1 },
+ { "pcmd_len_ovfl2", 29, 1 },
+ { "zero_c_cmd_error", 28, 1 },
+ { "icspi0_fifo2x_Rx_framing_error", 27, 1 },
+ { "icspi1_fifo2x_Rx_framing_error", 26, 1 },
+ { "icspi2_fifo2x_Rx_framing_error", 25, 1 },
+ { "icspi3_fifo2x_Rx_framing_error", 24, 1 },
+ { "icspi0_Rx_framing_error", 23, 1 },
+ { "icspi1_Rx_framing_error", 22, 1 },
+ { "icspi2_Rx_framing_error", 21, 1 },
+ { "icspi3_Rx_framing_error", 20, 1 },
+ { "icspi0_Tx_framing_error", 19, 1 },
+ { "icspi1_Tx_framing_error", 18, 1 },
+ { "icspi2_Tx_framing_error", 17, 1 },
+ { "icspi3_Tx_framing_error", 16, 1 },
+ { "oespi0_Rx_framing_error", 15, 1 },
+ { "oespi1_Rx_framing_error", 14, 1 },
+ { "oespi2_Rx_framing_error", 13, 1 },
+ { "oespi3_Rx_framing_error", 12, 1 },
+ { "oespi0_Tx_framing_error", 11, 1 },
+ { "oespi1_Tx_framing_error", 10, 1 },
+ { "oespi2_Tx_framing_error", 9, 1 },
+ { "oespi3_Tx_framing_error", 8, 1 },
+ { "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
+ { "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
+ { "oespi2_ofifo2x_Tx_framing_error", 5, 1 },
+ { "oespi3_ofifo2x_Tx_framing_error", 4, 1 },
+ { "oespi_par_error", 3, 1 },
+ { "db_options_par_error", 2, 1 },
+ { "icspi_par_error", 1, 1 },
+ { "c_pcmd_par_error", 0, 1 },
+ { "PM_TX_INT_CAUSE", 0x8ffc, 0 },
+ { "pcmd_len_ovfl0", 31, 1 },
+ { "pcmd_len_ovfl1", 30, 1 },
+ { "pcmd_len_ovfl2", 29, 1 },
+ { "zero_c_cmd_error", 28, 1 },
+ { "icspi0_fifo2x_Rx_framing_error", 27, 1 },
+ { "icspi1_fifo2x_Rx_framing_error", 26, 1 },
+ { "icspi2_fifo2x_Rx_framing_error", 25, 1 },
+ { "icspi3_fifo2x_Rx_framing_error", 24, 1 },
+ { "icspi0_Rx_framing_error", 23, 1 },
+ { "icspi1_Rx_framing_error", 22, 1 },
+ { "icspi2_Rx_framing_error", 21, 1 },
+ { "icspi3_Rx_framing_error", 20, 1 },
+ { "icspi0_Tx_framing_error", 19, 1 },
+ { "icspi1_Tx_framing_error", 18, 1 },
+ { "icspi2_Tx_framing_error", 17, 1 },
+ { "icspi3_Tx_framing_error", 16, 1 },
+ { "oespi0_Rx_framing_error", 15, 1 },
+ { "oespi1_Rx_framing_error", 14, 1 },
+ { "oespi2_Rx_framing_error", 13, 1 },
+ { "oespi3_Rx_framing_error", 12, 1 },
+ { "oespi0_Tx_framing_error", 11, 1 },
+ { "oespi1_Tx_framing_error", 10, 1 },
+ { "oespi2_Tx_framing_error", 9, 1 },
+ { "oespi3_Tx_framing_error", 8, 1 },
+ { "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
+ { "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
+ { "oespi2_ofifo2x_Tx_framing_error", 5, 1 },
+ { "oespi3_ofifo2x_Tx_framing_error", 4, 1 },
+ { "ospi_or_bundle_len_par_err", 3, 1 },
+ { "db_options_par_error", 2, 1 },
+ { "icspi_par_error", 1, 1 },
+ { "c_pcmd_par_error", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t5_mps_regs[] = {
+ { "MPS_CMN_CTL", 0x9000, 0 },
+ { "LpbkCrdtCtrl", 4, 1 },
+ { "Detect8023", 3, 1 },
+ { "VFDirectAccess", 2, 1 },
+ { "NumPorts", 0, 2 },
+ { "MPS_INT_ENABLE", 0x9004, 0 },
+ { "StatIntEnb", 5, 1 },
+ { "TxIntEnb", 4, 1 },
+ { "RxIntEnb", 3, 1 },
+ { "TrcIntEnb", 2, 1 },
+ { "ClsIntEnb", 1, 1 },
+ { "PLIntEnb", 0, 1 },
+ { "MPS_INT_CAUSE", 0x9008, 0 },
+ { "StatInt", 5, 1 },
+ { "TxInt", 4, 1 },
+ { "RxInt", 3, 1 },
+ { "TrcInt", 2, 1 },
+ { "ClsInt", 1, 1 },
+ { "PLInt", 0, 1 },
+ { "MPS_CGEN_GLOBAL", 0x900c, 0 },
+ { "MPS_VF_TX_CTL_31_0", 0x9010, 0 },
+ { "MPS_VF_TX_CTL_63_32", 0x9014, 0 },
+ { "MPS_VF_TX_CTL_95_64", 0x9018, 0 },
+ { "MPS_VF_TX_CTL_127_96", 0x901c, 0 },
+ { "MPS_VF_RX_CTL_31_0", 0x9020, 0 },
+ { "MPS_VF_RX_CTL_63_32", 0x9024, 0 },
+ { "MPS_VF_RX_CTL_95_64", 0x9028, 0 },
+ { "MPS_VF_RX_CTL_127_96", 0x902c, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP0", 0x9030, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP1", 0x9034, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP2", 0x9038, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP3", 0x903c, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP0", 0x9040, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP1", 0x9044, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP2", 0x9048, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP3", 0x904c, 0 },
+ { "MPS_TP_CSIDE_MUX_CTL_P0", 0x9050, 0 },
+ { "MPS_TP_CSIDE_MUX_CTL_P1", 0x9054, 0 },
+ { "MPS_WOL_CTL_MODE", 0x9058, 0 },
+ { "MPS_FPGA_DEBUG", 0x9060, 0 },
+ { "FPGA_PTP_PORT", 9, 2 },
+ { "LPBK_EN", 8, 1 },
+ { "CH_MAP3", 6, 2 },
+ { "CH_MAP2", 4, 2 },
+ { "CH_MAP1", 2, 2 },
+ { "CH_MAP0", 0, 2 },
+ { "MPS_DEBUG_CTL", 0x9068, 0 },
+ { "DbgModeCtl_H", 11, 1 },
+ { "DbgSel_H", 6, 5 },
+ { "DbgModeCtl_L", 5, 1 },
+ { "DbgSel_L", 0, 5 },
+ { "MPS_DEBUG_DATA_REG_L", 0x906c, 0 },
+ { "MPS_DEBUG_DATA_REG_H", 0x9070, 0 },
+ { "MPS_TOP_SPARE", 0x9074, 0 },
+ { "TopSpare", 8, 24 },
+ { "oVlanSelLpbk3", 7, 1 },
+ { "oVlanSelLpbk2", 6, 1 },
+ { "oVlanSelLpbk1", 5, 1 },
+ { "oVlanSelLpbk0", 4, 1 },
+ { "oVlanSelMac3", 3, 1 },
+ { "oVlanSelMac2", 2, 1 },
+ { "oVlanSelMac1", 1, 1 },
+ { "oVlanSelMac0", 0, 1 },
+ { "MPS_BUILD_REVISION", 0x9078, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH0", 0x907c, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH1", 0x9080, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH2", 0x9084, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH3", 0x9088, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH4", 0x908c, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH5", 0x9090, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH6", 0x9094, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH7", 0x9098, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH8", 0x909c, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH9", 0x90a0, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH10", 0x90a4, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH11", 0x90a8, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH12", 0x90ac, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH13", 0x90b0, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH14", 0x90b4, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH15", 0x90b8, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0", 0x90bc, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1", 0x90c0, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2", 0x90c4, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3", 0x90c8, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4", 0x90cc, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5", 0x90d0, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6", 0x90d4, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7", 0x90d8, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8", 0x90dc, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9", 0x90e0, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10", 0x90e4, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11", 0x90e8, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12", 0x90ec, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13", 0x90f0, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14", 0x90f4, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15", 0x90f8, 0 },
+ { "MPS_PORT_CTL", 0x30000, 0 },
+ { "LpbkEn", 31, 1 },
+ { "TxEn", 30, 1 },
+ { "RxEn", 29, 1 },
+ { "PPPEn", 28, 1 },
+ { "FCSStripEn", 27, 1 },
+ { "PPPAndPause", 26, 1 },
+ { "PrioPPPEnMap", 16, 8 },
+ { "MPS_PORT_PAUSE_CTL", 0x30004, 0 },
+ { "MPS_PORT_TX_PAUSE_CTL", 0x30008, 0 },
+ { "RegSendOff", 24, 8 },
+ { "RegSendOn", 16, 8 },
+ { "SgeSendEn", 8, 8 },
+ { "RxSendEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_CTL2", 0x3000c, 0 },
+ { "MPS_PORT_RX_PAUSE_CTL", 0x30010, 0 },
+ { "RegHaltOn", 8, 8 },
+ { "RxHaltEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_STATUS", 0x30014, 0 },
+ { "RegSending", 16, 8 },
+ { "SgeSending", 8, 8 },
+ { "RxSending", 0, 8 },
+ { "MPS_PORT_RX_PAUSE_STATUS", 0x30018, 0 },
+ { "RegHalted", 8, 8 },
+ { "RxHalted", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_DEST_L", 0x3001c, 0 },
+ { "MPS_PORT_TX_PAUSE_DEST_H", 0x30020, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_L", 0x30024, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_H", 0x30028, 0 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3002c, 0 },
+ { "Prty7", 14, 2 },
+ { "Prty6", 12, 2 },
+ { "Prty5", 10, 2 },
+ { "Prty4", 8, 2 },
+ { "Prty3", 6, 2 },
+ { "Prty2", 4, 2 },
+ { "Prty1", 2, 2 },
+ { "Prty0", 0, 2 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x30030, 0 },
+ { "Prty7", 28, 4 },
+ { "Prty6", 24, 4 },
+ { "Prty5", 20, 4 },
+ { "Prty4", 16, 4 },
+ { "Prty3", 12, 4 },
+ { "Prty2", 8, 4 },
+ { "Prty1", 4, 4 },
+ { "Prty0", 0, 4 },
+ { "MPS_PORT_CTL", 0x34000, 0 },
+ { "LpbkEn", 31, 1 },
+ { "TxEn", 30, 1 },
+ { "RxEn", 29, 1 },
+ { "PPPEn", 28, 1 },
+ { "FCSStripEn", 27, 1 },
+ { "PPPAndPause", 26, 1 },
+ { "PrioPPPEnMap", 16, 8 },
+ { "MPS_PORT_PAUSE_CTL", 0x34004, 0 },
+ { "MPS_PORT_TX_PAUSE_CTL", 0x34008, 0 },
+ { "RegSendOff", 24, 8 },
+ { "RegSendOn", 16, 8 },
+ { "SgeSendEn", 8, 8 },
+ { "RxSendEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_CTL2", 0x3400c, 0 },
+ { "MPS_PORT_RX_PAUSE_CTL", 0x34010, 0 },
+ { "RegHaltOn", 8, 8 },
+ { "RxHaltEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_STATUS", 0x34014, 0 },
+ { "RegSending", 16, 8 },
+ { "SgeSending", 8, 8 },
+ { "RxSending", 0, 8 },
+ { "MPS_PORT_RX_PAUSE_STATUS", 0x34018, 0 },
+ { "RegHalted", 8, 8 },
+ { "RxHalted", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_DEST_L", 0x3401c, 0 },
+ { "MPS_PORT_TX_PAUSE_DEST_H", 0x34020, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_L", 0x34024, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_H", 0x34028, 0 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3402c, 0 },
+ { "Prty7", 14, 2 },
+ { "Prty6", 12, 2 },
+ { "Prty5", 10, 2 },
+ { "Prty4", 8, 2 },
+ { "Prty3", 6, 2 },
+ { "Prty2", 4, 2 },
+ { "Prty1", 2, 2 },
+ { "Prty0", 0, 2 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x34030, 0 },
+ { "Prty7", 28, 4 },
+ { "Prty6", 24, 4 },
+ { "Prty5", 20, 4 },
+ { "Prty4", 16, 4 },
+ { "Prty3", 12, 4 },
+ { "Prty2", 8, 4 },
+ { "Prty1", 4, 4 },
+ { "Prty0", 0, 4 },
+ { "MPS_PORT_CTL", 0x38000, 0 },
+ { "LpbkEn", 31, 1 },
+ { "TxEn", 30, 1 },
+ { "RxEn", 29, 1 },
+ { "PPPEn", 28, 1 },
+ { "FCSStripEn", 27, 1 },
+ { "PPPAndPause", 26, 1 },
+ { "PrioPPPEnMap", 16, 8 },
+ { "MPS_PORT_PAUSE_CTL", 0x38004, 0 },
+ { "MPS_PORT_TX_PAUSE_CTL", 0x38008, 0 },
+ { "RegSendOff", 24, 8 },
+ { "RegSendOn", 16, 8 },
+ { "SgeSendEn", 8, 8 },
+ { "RxSendEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_CTL2", 0x3800c, 0 },
+ { "MPS_PORT_RX_PAUSE_CTL", 0x38010, 0 },
+ { "RegHaltOn", 8, 8 },
+ { "RxHaltEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_STATUS", 0x38014, 0 },
+ { "RegSending", 16, 8 },
+ { "SgeSending", 8, 8 },
+ { "RxSending", 0, 8 },
+ { "MPS_PORT_RX_PAUSE_STATUS", 0x38018, 0 },
+ { "RegHalted", 8, 8 },
+ { "RxHalted", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_DEST_L", 0x3801c, 0 },
+ { "MPS_PORT_TX_PAUSE_DEST_H", 0x38020, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_L", 0x38024, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_H", 0x38028, 0 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3802c, 0 },
+ { "Prty7", 14, 2 },
+ { "Prty6", 12, 2 },
+ { "Prty5", 10, 2 },
+ { "Prty4", 8, 2 },
+ { "Prty3", 6, 2 },
+ { "Prty2", 4, 2 },
+ { "Prty1", 2, 2 },
+ { "Prty0", 0, 2 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x38030, 0 },
+ { "Prty7", 28, 4 },
+ { "Prty6", 24, 4 },
+ { "Prty5", 20, 4 },
+ { "Prty4", 16, 4 },
+ { "Prty3", 12, 4 },
+ { "Prty2", 8, 4 },
+ { "Prty1", 4, 4 },
+ { "Prty0", 0, 4 },
+ { "MPS_PORT_CTL", 0x3c000, 0 },
+ { "LpbkEn", 31, 1 },
+ { "TxEn", 30, 1 },
+ { "RxEn", 29, 1 },
+ { "PPPEn", 28, 1 },
+ { "FCSStripEn", 27, 1 },
+ { "PPPAndPause", 26, 1 },
+ { "PrioPPPEnMap", 16, 8 },
+ { "MPS_PORT_PAUSE_CTL", 0x3c004, 0 },
+ { "MPS_PORT_TX_PAUSE_CTL", 0x3c008, 0 },
+ { "RegSendOff", 24, 8 },
+ { "RegSendOn", 16, 8 },
+ { "SgeSendEn", 8, 8 },
+ { "RxSendEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_CTL2", 0x3c00c, 0 },
+ { "MPS_PORT_RX_PAUSE_CTL", 0x3c010, 0 },
+ { "RegHaltOn", 8, 8 },
+ { "RxHaltEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_STATUS", 0x3c014, 0 },
+ { "RegSending", 16, 8 },
+ { "SgeSending", 8, 8 },
+ { "RxSending", 0, 8 },
+ { "MPS_PORT_RX_PAUSE_STATUS", 0x3c018, 0 },
+ { "RegHalted", 8, 8 },
+ { "RxHalted", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_DEST_L", 0x3c01c, 0 },
+ { "MPS_PORT_TX_PAUSE_DEST_H", 0x3c020, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_L", 0x3c024, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_H", 0x3c028, 0 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3c02c, 0 },
+ { "Prty7", 14, 2 },
+ { "Prty6", 12, 2 },
+ { "Prty5", 10, 2 },
+ { "Prty4", 8, 2 },
+ { "Prty3", 6, 2 },
+ { "Prty2", 4, 2 },
+ { "Prty1", 2, 2 },
+ { "Prty0", 0, 2 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x3c030, 0 },
+ { "Prty7", 28, 4 },
+ { "Prty6", 24, 4 },
+ { "Prty5", 20, 4 },
+ { "Prty4", 16, 4 },
+ { "Prty3", 12, 4 },
+ { "Prty2", 8, 4 },
+ { "Prty1", 4, 4 },
+ { "Prty0", 0, 4 },
+ { "MPS_PF_CTL", 0x1e2c0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1e6c0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1eac0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1eec0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1f2c0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1f6c0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1fac0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1fec0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_RX_CTL", 0x11000, 0 },
+ { "FILT_VLAN_SEL", 17, 1 },
+ { "CBA_EN", 16, 1 },
+ { "BLK_SNDR", 12, 4 },
+ { "CMPRS", 8, 4 },
+ { "SNF", 0, 8 },
+ { "MPS_RX_PORT_MUX_CTL", 0x11004, 0 },
+ { "CTL_P3", 12, 4 },
+ { "CTL_P2", 8, 4 },
+ { "CTL_P1", 4, 4 },
+ { "CTL_P0", 0, 4 },
+ { "MPS_RX_PG_FL", 0x11008, 0 },
+ { "RST", 16, 1 },
+ { "CNT", 0, 16 },
+ { "MPS_RX_PKT_FL", 0x1100c, 0 },
+ { "RST", 16, 1 },
+ { "CNT", 0, 16 },
+ { "MPS_RX_PG_RSV0", 0x11010, 0 },
+ { "CLR_INTR", 31, 1 },
+ { "SET_INTR", 30, 1 },
+ { "USED", 16, 12 },
+ { "ALLOC", 0, 12 },
+ { "MPS_RX_PG_RSV1", 0x11014, 0 },
+ { "CLR_INTR", 31, 1 },
+ { "SET_INTR", 30, 1 },
+ { "USED", 16, 12 },
+ { "ALLOC", 0, 12 },
+ { "MPS_RX_PG_RSV2", 0x11018, 0 },
+ { "CLR_INTR", 31, 1 },
+ { "SET_INTR", 30, 1 },
+ { "USED", 16, 12 },
+ { "ALLOC", 0, 12 },
+ { "MPS_RX_PG_RSV3", 0x1101c, 0 },
+ { "CLR_INTR", 31, 1 },
+ { "SET_INTR", 30, 1 },
+ { "USED", 16, 12 },
+ { "ALLOC", 0, 12 },
+ { "MPS_RX_PG_RSV4", 0x11020, 0 },
+ { "CLR_INTR", 31, 1 },
+ { "SET_INTR", 30, 1 },
+ { "USED", 16, 12 },
+ { "ALLOC", 0, 12 },
+ { "MPS_RX_PG_RSV5", 0x11024, 0 },
+ { "CLR_INTR", 31, 1 },
+ { "SET_INTR", 30, 1 },
+ { "USED", 16, 12 },
+ { "ALLOC", 0, 12 },
+ { "MPS_RX_PG_RSV6", 0x11028, 0 },
+ { "CLR_INTR", 31, 1 },
+ { "SET_INTR", 30, 1 },
+ { "USED", 16, 12 },
+ { "ALLOC", 0, 12 },
+ { "MPS_RX_PG_RSV7", 0x1102c, 0 },
+ { "CLR_INTR", 31, 1 },
+ { "SET_INTR", 30, 1 },
+ { "USED", 16, 12 },
+ { "ALLOC", 0, 12 },
+ { "MPS_RX_PG_SHR_BG0", 0x11030, 0 },
+ { "EN", 31, 1 },
+ { "SEL", 30, 1 },
+ { "MAX", 16, 12 },
+ { "BORW", 0, 12 },
+ { "MPS_RX_PG_SHR_BG1", 0x11034, 0 },
+ { "EN", 31, 1 },
+ { "SEL", 30, 1 },
+ { "MAX", 16, 12 },
+ { "BORW", 0, 12 },
+ { "MPS_RX_PG_SHR_BG2", 0x11038, 0 },
+ { "EN", 31, 1 },
+ { "SEL", 30, 1 },
+ { "MAX", 16, 12 },
+ { "BORW", 0, 12 },
+ { "MPS_RX_PG_SHR_BG3", 0x1103c, 0 },
+ { "EN", 31, 1 },
+ { "SEL", 30, 1 },
+ { "MAX", 16, 12 },
+ { "BORW", 0, 12 },
+ { "MPS_RX_PG_SHR0", 0x11040, 0 },
+ { "QUOTA", 16, 12 },
+ { "USED", 0, 12 },
+ { "MPS_RX_PG_SHR1", 0x11044, 0 },
+ { "QUOTA", 16, 12 },
+ { "USED", 0, 12 },
+ { "MPS_RX_PG_HYST_BG0", 0x11048, 0 },
+ { "EN", 31, 1 },
+ { "TH", 0, 12 },
+ { "MPS_RX_PG_HYST_BG1", 0x1104c, 0 },
+ { "EN", 31, 1 },
+ { "TH", 0, 12 },
+ { "MPS_RX_PG_HYST_BG2", 0x11050, 0 },
+ { "EN", 31, 1 },
+ { "TH", 0, 12 },
+ { "MPS_RX_PG_HYST_BG3", 0x11054, 0 },
+ { "EN", 31, 1 },
+ { "TH", 0, 12 },
+ { "MPS_RX_OCH_CTL", 0x11058, 0 },
+ { "DROP_WT", 27, 5 },
+ { "TRUNC_WT", 22, 5 },
+ { "DRAIN", 13, 5 },
+ { "DROP", 8, 5 },
+ { "STOP", 0, 5 },
+ { "MPS_RX_LPBK_BP0", 0x1105c, 0 },
+ { "MPS_RX_LPBK_BP1", 0x11060, 0 },
+ { "MPS_RX_LPBK_BP2", 0x11064, 0 },
+ { "MPS_RX_LPBK_BP3", 0x11068, 0 },
+ { "MPS_RX_PORT_GAP", 0x1106c, 0 },
+ { "MPS_RX_PERR_INT_CAUSE", 0x11074, 0 },
+ { "FF", 23, 1 },
+ { "PGMO", 22, 1 },
+ { "PGME", 21, 1 },
+ { "CHMN", 20, 1 },
+ { "RPLC", 19, 1 },
+ { "ATRB", 18, 1 },
+ { "PSMX", 17, 1 },
+ { "PGLL", 16, 1 },
+ { "PGFL", 15, 1 },
+ { "PKTQ", 14, 1 },
+ { "PKFL", 13, 1 },
+ { "PPM3", 12, 1 },
+ { "PPM2", 11, 1 },
+ { "PPM1", 10, 1 },
+ { "PPM0", 9, 1 },
+ { "SPMX", 8, 1 },
+ { "CDL3", 7, 1 },
+ { "CDL2", 6, 1 },
+ { "CDL1", 5, 1 },
+ { "CDL0", 4, 1 },
+ { "CDM3", 3, 1 },
+ { "CDM2", 2, 1 },
+ { "CDM1", 1, 1 },
+ { "CDM0", 0, 1 },
+ { "MPS_RX_PERR_INT_ENABLE", 0x11078, 0 },
+ { "FF", 23, 1 },
+ { "PGMO", 22, 1 },
+ { "PGME", 21, 1 },
+ { "CHMN", 20, 1 },
+ { "RPLC", 19, 1 },
+ { "ATRB", 18, 1 },
+ { "PSMX", 17, 1 },
+ { "PGLL", 16, 1 },
+ { "PGFL", 15, 1 },
+ { "PKTQ", 14, 1 },
+ { "PKFL", 13, 1 },
+ { "PPM3", 12, 1 },
+ { "PPM2", 11, 1 },
+ { "PPM1", 10, 1 },
+ { "PPM0", 9, 1 },
+ { "SPMX", 8, 1 },
+ { "CDL3", 7, 1 },
+ { "CDL2", 6, 1 },
+ { "CDL1", 5, 1 },
+ { "CDL0", 4, 1 },
+ { "CDM3", 3, 1 },
+ { "CDM2", 2, 1 },
+ { "CDM1", 1, 1 },
+ { "CDM0", 0, 1 },
+ { "MPS_RX_PERR_ENABLE", 0x1107c, 0 },
+ { "FF", 23, 1 },
+ { "PGMO", 22, 1 },
+ { "PGME", 21, 1 },
+ { "CHMN", 20, 1 },
+ { "RPLC", 19, 1 },
+ { "ATRB", 18, 1 },
+ { "PSMX", 17, 1 },
+ { "PGLL", 16, 1 },
+ { "PGFL", 15, 1 },
+ { "PKTQ", 14, 1 },
+ { "PKFL", 13, 1 },
+ { "PPM3", 12, 1 },
+ { "PPM2", 11, 1 },
+ { "PPM1", 10, 1 },
+ { "PPM0", 9, 1 },
+ { "SPMX", 8, 1 },
+ { "CDL3", 7, 1 },
+ { "CDL2", 6, 1 },
+ { "CDL1", 5, 1 },
+ { "CDL0", 4, 1 },
+ { "CDM3", 3, 1 },
+ { "CDM2", 2, 1 },
+ { "CDM1", 1, 1 },
+ { "CDM0", 0, 1 },
+ { "MPS_RX_PERR_INJECT", 0x11080, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "MPS_RX_FUNC_INT_CAUSE", 0x11084, 0 },
+ { "MTU_ERR_INT3", 19, 1 },
+ { "MTU_ERR_INT2", 18, 1 },
+ { "MTU_ERR_INT1", 17, 1 },
+ { "MTU_ERR_INT0", 16, 1 },
+ { "SE_CNT_ERR_INT", 15, 1 },
+ { "FRM_ERR_INT", 14, 1 },
+ { "LEN_ERR_INT", 13, 1 },
+ { "INT_ERR_INT", 8, 5 },
+ { "PG_TH_INT7", 7, 1 },
+ { "PG_TH_INT6", 6, 1 },
+ { "PG_TH_INT5", 5, 1 },
+ { "PG_TH_INT4", 4, 1 },
+ { "PG_TH_INT3", 3, 1 },
+ { "PG_TH_INT2", 2, 1 },
+ { "PG_TH_INT1", 1, 1 },
+ { "PG_TH_INT0", 0, 1 },
+ { "MPS_RX_FUNC_INT_ENABLE", 0x11088, 0 },
+ { "MTU_ERR_INT3", 19, 1 },
+ { "MTU_ERR_INT2", 18, 1 },
+ { "MTU_ERR_INT1", 17, 1 },
+ { "MTU_ERR_INT0", 16, 1 },
+ { "SE_CNT_ERR_INT", 15, 1 },
+ { "FRM_ERR_INT", 14, 1 },
+ { "LEN_ERR_INT", 13, 1 },
+ { "INT_ERR_INT", 8, 5 },
+ { "PG_TH_INT7", 7, 1 },
+ { "PG_TH_INT6", 6, 1 },
+ { "PG_TH_INT5", 5, 1 },
+ { "PG_TH_INT4", 4, 1 },
+ { "PG_TH_INT3", 3, 1 },
+ { "PG_TH_INT2", 2, 1 },
+ { "PG_TH_INT1", 1, 1 },
+ { "PG_TH_INT0", 0, 1 },
+ { "MPS_RX_PPP_ATRB", 0x1109c, 0 },
+ { "ETYPE", 16, 16 },
+ { "OPCODE", 0, 16 },
+ { "MPS_RX_QFC0_ATRB", 0x110a0, 0 },
+ { "ETYPE", 16, 16 },
+ { "DA", 0, 16 },
+ { "MPS_RX_QFC1_ATRB", 0x110a4, 0 },
+ { "MPS_RX_PT_ARB0", 0x110a8, 0 },
+ { "LPBK_WT", 16, 14 },
+ { "MAC_WT", 0, 14 },
+ { "MPS_RX_PT_ARB1", 0x110ac, 0 },
+ { "LPBK_WT", 16, 14 },
+ { "MAC_WT", 0, 14 },
+ { "MPS_RX_PT_ARB2", 0x110b0, 0 },
+ { "LPBK_WT", 16, 14 },
+ { "MAC_WT", 0, 14 },
+ { "MPS_RX_PT_ARB3", 0x110b4, 0 },
+ { "LPBK_WT", 16, 14 },
+ { "MAC_WT", 0, 14 },
+ { "MPS_RX_PT_ARB4", 0x110b8, 0 },
+ { "LPBK_WT", 16, 14 },
+ { "MAC_WT", 0, 14 },
+ { "MPS_PF_OUT_EN", 0x110bc, 0 },
+ { "MPS_BMC_MTU", 0x110c0, 0 },
+ { "MPS_BMC_PKT_CNT", 0x110c4, 0 },
+ { "MPS_BMC_BYTE_CNT", 0x110c8, 0 },
+ { "MPS_PFVF_ATRB_CTL", 0x110cc, 0 },
+ { "RD_WRN", 31, 1 },
+ { "PFVF", 0, 8 },
+ { "MPS_PFVF_ATRB", 0x110d0, 0 },
+ { "PF", 28, 3 },
+ { "OFF", 18, 1 },
+ { "NV_DROP", 17, 1 },
+ { "MODE", 16, 1 },
+ { "MTU", 0, 14 },
+ { "MPS_PFVF_ATRB_FLTR0", 0x110d4, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR1", 0x110d8, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR2", 0x110dc, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR3", 0x110e0, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR4", 0x110e4, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR5", 0x110e8, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR6", 0x110ec, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR7", 0x110f0, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR8", 0x110f4, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR9", 0x110f8, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR10", 0x110fc, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR11", 0x11100, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR12", 0x11104, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR13", 0x11108, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR14", 0x1110c, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR15", 0x11110, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_RPLC_MAP_CTL", 0x11114, 0 },
+ { "RD_WRN", 31, 1 },
+ { "ADDR", 0, 10 },
+ { "MPS_PF_RPLCT_MAP", 0x11118, 0 },
+ { "MPS_VF_RPLCT_MAP0", 0x1111c, 0 },
+ { "MPS_VF_RPLCT_MAP1", 0x11120, 0 },
+ { "MPS_VF_RPLCT_MAP2", 0x11124, 0 },
+ { "MPS_VF_RPLCT_MAP3", 0x11128, 0 },
+ { "MPS_MEM_DBG_CTL", 0x1112c, 0 },
+ { "PKD", 17, 1 },
+ { "PGD", 16, 1 },
+ { "ADDR", 0, 16 },
+ { "MPS_PKD_MEM_DATA0", 0x11130, 0 },
+ { "MPS_PKD_MEM_DATA1", 0x11134, 0 },
+ { "MPS_PKD_MEM_DATA2", 0x11138, 0 },
+ { "MPS_PGD_MEM_DATA", 0x1113c, 0 },
+ { "MPS_RX_SE_CNT_ERR", 0x11140, 0 },
+ { "MPS_RX_SE_CNT_CLR", 0x11144, 0 },
+ { "MPS_RX_SE_CNT_IN0", 0x11148, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN1", 0x1114c, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN2", 0x11150, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN3", 0x11154, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN4", 0x11158, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN5", 0x1115c, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN6", 0x11160, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN7", 0x11164, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_OUT01", 0x11168, 0 },
+ { "SOP_CNT_1", 24, 8 },
+ { "EOP_CNT_1", 16, 8 },
+ { "SOP_CNT_0", 8, 8 },
+ { "EOP_CNT_0", 0, 8 },
+ { "MPS_RX_SE_CNT_OUT23", 0x1116c, 0 },
+ { "SOP_CNT_3", 24, 8 },
+ { "EOP_CNT_3", 16, 8 },
+ { "SOP_CNT_2", 8, 8 },
+ { "EOP_CNT_2", 0, 8 },
+ { "MPS_RX_SPI_ERR", 0x11170, 0 },
+ { "LEN_ERR", 21, 4 },
+ { "ERR", 0, 21 },
+ { "MPS_RX_IN_BUS_STATE", 0x11174, 0 },
+ { "ST3", 24, 8 },
+ { "ST2", 16, 8 },
+ { "ST1", 8, 8 },
+ { "ST0", 0, 8 },
+ { "MPS_RX_OUT_BUS_STATE", 0x11178, 0 },
+ { "ST_NCSI", 23, 9 },
+ { "ST_TP", 0, 23 },
+ { "MPS_RX_DBG_CTL", 0x1117c, 0 },
+ { "OUT_DBG_CHNL", 8, 3 },
+ { "DBG_PKD_QSEL", 7, 1 },
+ { "DBG_CDS_INV", 6, 1 },
+ { "IN_DBG_PORT", 3, 3 },
+ { "IN_DBG_CHNL", 0, 3 },
+ { "MPS_RX_SPARE", 0x11190, 0 },
+ { "MPS_RX_PTP_ETYPE", 0x11194, 0 },
+ { "PETYPE2", 16, 16 },
+ { "PETYPE1", 0, 16 },
+ { "MPS_RX_PTP_TCP", 0x11198, 0 },
+ { "PTCPORT2", 16, 16 },
+ { "PTCPORT1", 0, 16 },
+ { "MPS_RX_PTP_UDP", 0x1119c, 0 },
+ { "PUDPORT2", 16, 16 },
+ { "PUDPORT1", 0, 16 },
+ { "MPS_RX_PTP_CTL", 0x111a0, 0 },
+ { "MIN_PTP_SPACE", 24, 7 },
+ { "PUDP2EN", 20, 4 },
+ { "PUDP1EN", 16, 4 },
+ { "PTCP2EN", 12, 4 },
+ { "PTCP1EN", 8, 4 },
+ { "PETYPE2EN", 4, 4 },
+ { "PETYPE1EN", 0, 4 },
+ { "MPS_RX_PAUSE_GEN_TH_0_0", 0x111a4, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_0_1", 0x111a8, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_0_2", 0x111ac, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_0_3", 0x111b0, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_1_0", 0x111b4, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_1_1", 0x111b8, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_1_2", 0x111bc, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_1_3", 0x111c0, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_2_0", 0x111c4, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_2_1", 0x111c8, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_2_2", 0x111cc, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_2_3", 0x111d0, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_3_0", 0x111d4, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_3_1", 0x111d8, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_3_2", 0x111dc, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_3_3", 0x111e0, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_MAC_CLS_DROP_CNT0", 0x111e4, 0 },
+ { "MPS_RX_MAC_CLS_DROP_CNT1", 0x111e8, 0 },
+ { "MPS_RX_MAC_CLS_DROP_CNT2", 0x111ec, 0 },
+ { "MPS_RX_MAC_CLS_DROP_CNT3", 0x111f0, 0 },
+ { "MPS_RX_LPBK_CLS_DROP_CNT0", 0x111f4, 0 },
+ { "MPS_RX_LPBK_CLS_DROP_CNT1", 0x111f8, 0 },
+ { "MPS_RX_LPBK_CLS_DROP_CNT2", 0x111fc, 0 },
+ { "MPS_RX_LPBK_CLS_DROP_CNT3", 0x11200, 0 },
+ { "MPS_RX_CGEN", 0x11204, 0 },
+ { "MPS_RX_CGEN_NCSI", 12, 1 },
+ { "MPS_RX_CGEN_OUT", 8, 4 },
+ { "MPS_RX_CGEN_LPBK_IN", 4, 4 },
+ { "MPS_RX_CGEN_MAC_IN", 0, 4 },
+ { "MPS_PORT_RX_CTL", 0x30100, 0 },
+ { "PTP_FWD_UP", 21, 1 },
+ { "NO_RPLCT_M", 20, 1 },
+ { "RPLCT_SEL_L", 18, 2 },
+ { "FLTR_VLAN_SEL", 17, 1 },
+ { "PRIO_VLAN_SEL", 16, 1 },
+ { "CHK_8023_LEN_M", 15, 1 },
+ { "CHK_8023_LEN_L", 14, 1 },
+ { "NIV_DROP", 13, 1 },
+ { "NOV_DROP", 12, 1 },
+ { "CLS_PRT", 11, 1 },
+ { "RX_QFC_EN", 10, 1 },
+ { "QFC_FWD_UP", 9, 1 },
+ { "PPP_FWD_UP", 8, 1 },
+ { "PAUSE_FWD_UP", 7, 1 },
+ { "LPBK_BP", 6, 1 },
+ { "PASS_NO_MATCH", 5, 1 },
+ { "IVLAN_EN", 4, 1 },
+ { "OVLAN_EN3", 3, 1 },
+ { "OVLAN_EN2", 2, 1 },
+ { "OVLAN_EN1", 1, 1 },
+ { "OVLAN_EN0", 0, 1 },
+ { "MPS_PORT_RX_MTU", 0x30104, 0 },
+ { "MPS_PORT_RX_PF_MAP", 0x30108, 0 },
+ { "MPS_PORT_RX_VF_MAP0", 0x3010c, 0 },
+ { "MPS_PORT_RX_VF_MAP1", 0x30110, 0 },
+ { "MPS_PORT_RX_VF_MAP2", 0x30114, 0 },
+ { "MPS_PORT_RX_VF_MAP3", 0x30118, 0 },
+ { "MPS_PORT_RX_IVLAN", 0x3011c, 0 },
+ { "MPS_PORT_RX_OVLAN0", 0x30120, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN1", 0x30124, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN2", 0x30128, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN3", 0x3012c, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_RSS_HASH", 0x30130, 0 },
+ { "MPS_PORT_RX_RSS_CONTROL", 0x30134, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_CTL1", 0x30138, 0 },
+ { "FIXED_PFVF_MAC", 13, 1 },
+ { "FIXED_PFVF_LPBK", 12, 1 },
+ { "FIXED_PFVF_LPBK_OV", 11, 1 },
+ { "FIXED_PF", 8, 3 },
+ { "FIXED_VF_VLD", 7, 1 },
+ { "FIXED_VF", 0, 7 },
+ { "MPS_PORT_RX_SPARE", 0x3013c, 0 },
+ { "MPS_PORT_RX_PTP_RSS_HASH", 0x30140, 0 },
+ { "MPS_PORT_RX_PTP_RSS_CONTROL", 0x30144, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_CTL", 0x34100, 0 },
+ { "PTP_FWD_UP", 21, 1 },
+ { "NO_RPLCT_M", 20, 1 },
+ { "RPLCT_SEL_L", 18, 2 },
+ { "FLTR_VLAN_SEL", 17, 1 },
+ { "PRIO_VLAN_SEL", 16, 1 },
+ { "CHK_8023_LEN_M", 15, 1 },
+ { "CHK_8023_LEN_L", 14, 1 },
+ { "NIV_DROP", 13, 1 },
+ { "NOV_DROP", 12, 1 },
+ { "CLS_PRT", 11, 1 },
+ { "RX_QFC_EN", 10, 1 },
+ { "QFC_FWD_UP", 9, 1 },
+ { "PPP_FWD_UP", 8, 1 },
+ { "PAUSE_FWD_UP", 7, 1 },
+ { "LPBK_BP", 6, 1 },
+ { "PASS_NO_MATCH", 5, 1 },
+ { "IVLAN_EN", 4, 1 },
+ { "OVLAN_EN3", 3, 1 },
+ { "OVLAN_EN2", 2, 1 },
+ { "OVLAN_EN1", 1, 1 },
+ { "OVLAN_EN0", 0, 1 },
+ { "MPS_PORT_RX_MTU", 0x34104, 0 },
+ { "MPS_PORT_RX_PF_MAP", 0x34108, 0 },
+ { "MPS_PORT_RX_VF_MAP0", 0x3410c, 0 },
+ { "MPS_PORT_RX_VF_MAP1", 0x34110, 0 },
+ { "MPS_PORT_RX_VF_MAP2", 0x34114, 0 },
+ { "MPS_PORT_RX_VF_MAP3", 0x34118, 0 },
+ { "MPS_PORT_RX_IVLAN", 0x3411c, 0 },
+ { "MPS_PORT_RX_OVLAN0", 0x34120, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN1", 0x34124, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN2", 0x34128, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN3", 0x3412c, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_RSS_HASH", 0x34130, 0 },
+ { "MPS_PORT_RX_RSS_CONTROL", 0x34134, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_CTL1", 0x34138, 0 },
+ { "FIXED_PFVF_MAC", 13, 1 },
+ { "FIXED_PFVF_LPBK", 12, 1 },
+ { "FIXED_PFVF_LPBK_OV", 11, 1 },
+ { "FIXED_PF", 8, 3 },
+ { "FIXED_VF_VLD", 7, 1 },
+ { "FIXED_VF", 0, 7 },
+ { "MPS_PORT_RX_SPARE", 0x3413c, 0 },
+ { "MPS_PORT_RX_PTP_RSS_HASH", 0x34140, 0 },
+ { "MPS_PORT_RX_PTP_RSS_CONTROL", 0x34144, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_CTL", 0x38100, 0 },
+ { "PTP_FWD_UP", 21, 1 },
+ { "NO_RPLCT_M", 20, 1 },
+ { "RPLCT_SEL_L", 18, 2 },
+ { "FLTR_VLAN_SEL", 17, 1 },
+ { "PRIO_VLAN_SEL", 16, 1 },
+ { "CHK_8023_LEN_M", 15, 1 },
+ { "CHK_8023_LEN_L", 14, 1 },
+ { "NIV_DROP", 13, 1 },
+ { "NOV_DROP", 12, 1 },
+ { "CLS_PRT", 11, 1 },
+ { "RX_QFC_EN", 10, 1 },
+ { "QFC_FWD_UP", 9, 1 },
+ { "PPP_FWD_UP", 8, 1 },
+ { "PAUSE_FWD_UP", 7, 1 },
+ { "LPBK_BP", 6, 1 },
+ { "PASS_NO_MATCH", 5, 1 },
+ { "IVLAN_EN", 4, 1 },
+ { "OVLAN_EN3", 3, 1 },
+ { "OVLAN_EN2", 2, 1 },
+ { "OVLAN_EN1", 1, 1 },
+ { "OVLAN_EN0", 0, 1 },
+ { "MPS_PORT_RX_MTU", 0x38104, 0 },
+ { "MPS_PORT_RX_PF_MAP", 0x38108, 0 },
+ { "MPS_PORT_RX_VF_MAP0", 0x3810c, 0 },
+ { "MPS_PORT_RX_VF_MAP1", 0x38110, 0 },
+ { "MPS_PORT_RX_VF_MAP2", 0x38114, 0 },
+ { "MPS_PORT_RX_VF_MAP3", 0x38118, 0 },
+ { "MPS_PORT_RX_IVLAN", 0x3811c, 0 },
+ { "MPS_PORT_RX_OVLAN0", 0x38120, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN1", 0x38124, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN2", 0x38128, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN3", 0x3812c, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_RSS_HASH", 0x38130, 0 },
+ { "MPS_PORT_RX_RSS_CONTROL", 0x38134, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_CTL1", 0x38138, 0 },
+ { "FIXED_PFVF_MAC", 13, 1 },
+ { "FIXED_PFVF_LPBK", 12, 1 },
+ { "FIXED_PFVF_LPBK_OV", 11, 1 },
+ { "FIXED_PF", 8, 3 },
+ { "FIXED_VF_VLD", 7, 1 },
+ { "FIXED_VF", 0, 7 },
+ { "MPS_PORT_RX_SPARE", 0x3813c, 0 },
+ { "MPS_PORT_RX_PTP_RSS_HASH", 0x38140, 0 },
+ { "MPS_PORT_RX_PTP_RSS_CONTROL", 0x38144, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_CTL", 0x3c100, 0 },
+ { "PTP_FWD_UP", 21, 1 },
+ { "NO_RPLCT_M", 20, 1 },
+ { "RPLCT_SEL_L", 18, 2 },
+ { "FLTR_VLAN_SEL", 17, 1 },
+ { "PRIO_VLAN_SEL", 16, 1 },
+ { "CHK_8023_LEN_M", 15, 1 },
+ { "CHK_8023_LEN_L", 14, 1 },
+ { "NIV_DROP", 13, 1 },
+ { "NOV_DROP", 12, 1 },
+ { "CLS_PRT", 11, 1 },
+ { "RX_QFC_EN", 10, 1 },
+ { "QFC_FWD_UP", 9, 1 },
+ { "PPP_FWD_UP", 8, 1 },
+ { "PAUSE_FWD_UP", 7, 1 },
+ { "LPBK_BP", 6, 1 },
+ { "PASS_NO_MATCH", 5, 1 },
+ { "IVLAN_EN", 4, 1 },
+ { "OVLAN_EN3", 3, 1 },
+ { "OVLAN_EN2", 2, 1 },
+ { "OVLAN_EN1", 1, 1 },
+ { "OVLAN_EN0", 0, 1 },
+ { "MPS_PORT_RX_MTU", 0x3c104, 0 },
+ { "MPS_PORT_RX_PF_MAP", 0x3c108, 0 },
+ { "MPS_PORT_RX_VF_MAP0", 0x3c10c, 0 },
+ { "MPS_PORT_RX_VF_MAP1", 0x3c110, 0 },
+ { "MPS_PORT_RX_VF_MAP2", 0x3c114, 0 },
+ { "MPS_PORT_RX_VF_MAP3", 0x3c118, 0 },
+ { "MPS_PORT_RX_IVLAN", 0x3c11c, 0 },
+ { "MPS_PORT_RX_OVLAN0", 0x3c120, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN1", 0x3c124, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN2", 0x3c128, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN3", 0x3c12c, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_RSS_HASH", 0x3c130, 0 },
+ { "MPS_PORT_RX_RSS_CONTROL", 0x3c134, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_CTL1", 0x3c138, 0 },
+ { "FIXED_PFVF_MAC", 13, 1 },
+ { "FIXED_PFVF_LPBK", 12, 1 },
+ { "FIXED_PFVF_LPBK_OV", 11, 1 },
+ { "FIXED_PF", 8, 3 },
+ { "FIXED_VF_VLD", 7, 1 },
+ { "FIXED_VF", 0, 7 },
+ { "MPS_PORT_RX_SPARE", 0x3c13c, 0 },
+ { "MPS_PORT_RX_PTP_RSS_HASH", 0x3c140, 0 },
+ { "MPS_PORT_RX_PTP_RSS_CONTROL", 0x3c144, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_TX_PRTY_SEL", 0x9400, 0 },
+ { "Ch4_Prty", 20, 3 },
+ { "Ch3_Prty", 16, 3 },
+ { "Ch2_Prty", 12, 3 },
+ { "Ch1_Prty", 8, 3 },
+ { "Ch0_Prty", 4, 3 },
+ { "TP_Source", 2, 2 },
+ { "NCSI_Source", 0, 2 },
+ { "MPS_TX_INT_ENABLE", 0x9404, 0 },
+ { "PortErr", 16, 1 },
+ { "FRMERR", 15, 1 },
+ { "SECNTERR", 14, 1 },
+ { "BUBBLE", 13, 1 },
+ { "TxDescFifo", 9, 4 },
+ { "TxDataFifo", 5, 4 },
+ { "Ncsi", 4, 1 },
+ { "TP", 0, 4 },
+ { "MPS_TX_INT_CAUSE", 0x9408, 0 },
+ { "PortErr", 16, 1 },
+ { "FRMERR", 15, 1 },
+ { "SECNTERR", 14, 1 },
+ { "BUBBLE", 13, 1 },
+ { "TxDescFifo", 9, 4 },
+ { "TxDataFifo", 5, 4 },
+ { "Ncsi", 4, 1 },
+ { "TP", 0, 4 },
+ { "MPS_TX_PERR_ENABLE", 0x9410, 0 },
+ { "TxDescFifo", 9, 4 },
+ { "TxDataFifo", 5, 4 },
+ { "Ncsi", 4, 1 },
+ { "TP", 0, 4 },
+ { "MPS_TX_PERR_INJECT", 0x9414, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "MPS_TX_SE_CNT_TP01", 0x9418, 0 },
+ { "SOP_CNT_1", 24, 8 },
+ { "EOP_CNT_1", 16, 8 },
+ { "SOP_CNT_0", 8, 8 },
+ { "EOP_CNT_0", 0, 8 },
+ { "MPS_TX_SE_CNT_TP23", 0x941c, 0 },
+ { "SOP_CNT_3", 24, 8 },
+ { "EOP_CNT_3", 16, 8 },
+ { "SOP_CNT_2", 8, 8 },
+ { "EOP_CNT_2", 0, 8 },
+ { "MPS_TX_SE_CNT_MAC01", 0x9420, 0 },
+ { "SOP_CNT_1", 24, 8 },
+ { "EOP_CNT_1", 16, 8 },
+ { "SOP_CNT_0", 8, 8 },
+ { "EOP_CNT_0", 0, 8 },
+ { "MPS_TX_SE_CNT_MAC23", 0x9424, 0 },
+ { "SOP_CNT_3", 24, 8 },
+ { "EOP_CNT_3", 16, 8 },
+ { "SOP_CNT_2", 8, 8 },
+ { "EOP_CNT_2", 0, 8 },
+ { "MPS_TX_SECNT_SPI_BUBBLE_ERR", 0x9428, 0 },
+ { "Bubble", 16, 8 },
+ { "Spi", 8, 8 },
+ { "SeCnt", 0, 8 },
+ { "MPS_TX_SECNT_BUBBLE_CLR", 0x942c, 0 },
+ { "NcsiSeCnt", 20, 1 },
+ { "LpbkSeCnt", 16, 4 },
+ { "Bubble", 8, 8 },
+ { "SeCnt", 0, 8 },
+ { "MPS_TX_PORT_ERR", 0x9430, 0 },
+ { "Lpbkpt3", 7, 1 },
+ { "Lpbkpt2", 6, 1 },
+ { "Lpbkpt1", 5, 1 },
+ { "Lpbkpt0", 4, 1 },
+ { "pt3", 3, 1 },
+ { "pt2", 2, 1 },
+ { "pt1", 1, 1 },
+ { "pt0", 0, 1 },
+ { "MPS_TX_LPBK_DROP_BP_CTL_CH0", 0x9434, 0 },
+ { "BpEn", 1, 1 },
+ { "DropEn", 0, 1 },
+ { "MPS_TX_LPBK_DROP_BP_CTL_CH1", 0x9438, 0 },
+ { "BpEn", 1, 1 },
+ { "DropEn", 0, 1 },
+ { "MPS_TX_LPBK_DROP_BP_CTL_CH2", 0x943c, 0 },
+ { "BpEn", 1, 1 },
+ { "DropEn", 0, 1 },
+ { "MPS_TX_LPBK_DROP_BP_CTL_CH3", 0x9440, 0 },
+ { "BpEn", 1, 1 },
+ { "DropEn", 0, 1 },
+ { "MPS_TX_DEBUG_REG_TP2TX_10", 0x9444, 0 },
+ { "SOPCh1", 31, 1 },
+ { "EOPCh1", 30, 1 },
+ { "SizeCh1", 26, 4 },
+ { "ErrCh1", 25, 1 },
+ { "FullCh1", 24, 1 },
+ { "ValidCh1", 23, 1 },
+ { "DataCh1", 16, 7 },
+ { "SOPCh0", 15, 1 },
+ { "EOPCh0", 14, 1 },
+ { "SizeCh0", 10, 4 },
+ { "ErrCh0", 9, 1 },
+ { "FullCh0", 8, 1 },
+ { "ValidCh0", 7, 1 },
+ { "DataCh0", 0, 7 },
+ { "MPS_TX_DEBUG_REG_TP2TX_32", 0x9448, 0 },
+ { "SOPCh3", 31, 1 },
+ { "EOPCh3", 30, 1 },
+ { "SizeCh3", 26, 4 },
+ { "ErrCh3", 25, 1 },
+ { "FullCh3", 24, 1 },
+ { "ValidCh3", 23, 1 },
+ { "DataCh3", 16, 7 },
+ { "SOPCh2", 15, 1 },
+ { "EOPCh2", 14, 1 },
+ { "SizeCh2", 10, 4 },
+ { "ErrCh2", 9, 1 },
+ { "FullCh2", 8, 1 },
+ { "ValidCh2", 7, 1 },
+ { "DataCh2", 0, 7 },
+ { "MPS_TX_DEBUG_REG_TX2MAC_10", 0x944c, 0 },
+ { "SOPPt1", 31, 1 },
+ { "EOPPt1", 30, 1 },
+ { "SizePt1", 26, 4 },
+ { "ErrPt1", 25, 1 },
+ { "FullPt1", 24, 1 },
+ { "ValidPt1", 23, 1 },
+ { "DataPt1", 16, 7 },
+ { "SOPPt0", 15, 1 },
+ { "EOPPt0", 14, 1 },
+ { "SizePt0", 10, 4 },
+ { "ErrPt0", 9, 1 },
+ { "FullPt0", 8, 1 },
+ { "ValidPt0", 7, 1 },
+ { "DataPt0", 0, 7 },
+ { "MPS_TX_DEBUG_REG_TX2MAC_32", 0x9450, 0 },
+ { "SOPPt3", 31, 1 },
+ { "EOPPt3", 30, 1 },
+ { "SizePt3", 26, 4 },
+ { "ErrPt3", 25, 1 },
+ { "FullPt3", 24, 1 },
+ { "ValidPt3", 23, 1 },
+ { "DataPt3", 16, 7 },
+ { "SOPPt2", 15, 1 },
+ { "EOPPt2", 14, 1 },
+ { "SizePt2", 10, 4 },
+ { "ErrPt2", 9, 1 },
+ { "FullPt2", 8, 1 },
+ { "ValidPt2", 7, 1 },
+ { "DataPt2", 0, 7 },
+ { "MPS_TX_SGE_CH_PAUSE_IGNR", 0x9454, 0 },
+ { "MPS_TX_DEBUG_SUBPART_SEL", 0x9458, 0 },
+ { "SubPrtH", 11, 5 },
+ { "PortH", 8, 3 },
+ { "SubPrtL", 3, 5 },
+ { "PortL", 0, 3 },
+ { "MPS_TX_PAD_CTL", 0x945c, 0 },
+ { "LpbkPadEnPt3", 7, 1 },
+ { "LpbkPadEnPt2", 6, 1 },
+ { "LpbkPadEnPt1", 5, 1 },
+ { "LpbkPadEnPt0", 4, 1 },
+ { "MacPadEnPt3", 3, 1 },
+ { "MacPadEnPt2", 2, 1 },
+ { "MacPadEnPt1", 1, 1 },
+ { "MacPadEnPt0", 0, 1 },
+ { "MPS_TX_PFVF_PORT_DROP_TP", 0x9460, 0 },
+ { "TP2MPS_Ch3", 24, 8 },
+ { "TP2MPS_Ch2", 16, 8 },
+ { "TP2MPS_Ch1", 8, 8 },
+ { "TP2MPS_Ch0", 0, 8 },
+ { "MPS_TX_PFVF_PORT_DROP_NCSI", 0x9464, 0 },
+ { "MPS_TX_PFVF_PORT_DROP_CTL", 0x9468, 0 },
+ { "PFNOVFDROP", 5, 1 },
+ { "NCSI_Ch4_CLR", 4, 1 },
+ { "TP2MPS_Ch3_CLR", 3, 1 },
+ { "TP2MPS_Ch2_CLR", 2, 1 },
+ { "TP2MPS_Ch1_CLR", 1, 1 },
+ { "TP2MPS_Ch0_CLR", 0, 1 },
+ { "MPS_TX_CGEN", 0x946c, 0 },
+ { "TxOutLpbk3_CGEN", 31, 1 },
+ { "TxOutLpbk2_CGEN", 30, 1 },
+ { "TxOutLpbk1_CGEN", 29, 1 },
+ { "TxOutLpbk0_CGEN", 28, 1 },
+ { "TxOutMAC3_CGEN", 27, 1 },
+ { "TxOutMAC2_CGEN", 26, 1 },
+ { "TxOutMAC1_CGEN", 25, 1 },
+ { "TxOutMAC0_CGEN", 24, 1 },
+ { "TxSchLpbk3_CGEN", 23, 1 },
+ { "TxSchLpbk2_CGEN", 22, 1 },
+ { "TxSchLpbk1_CGEN", 21, 1 },
+ { "TxSchLpbk0_CGEN", 20, 1 },
+ { "TxSchMAC3_CGEN", 19, 1 },
+ { "TxSchMAC2_CGEN", 18, 1 },
+ { "TxSchMAC1_CGEN", 17, 1 },
+ { "TxSchMAC0_CGEN", 16, 1 },
+ { "TxInCh4_CGEN", 15, 1 },
+ { "TxInCh3_CGEN", 14, 1 },
+ { "TxInCh2_CGEN", 13, 1 },
+ { "TxInCh1_CGEN", 12, 1 },
+ { "TxInCh0_CGEN", 11, 1 },
+ { "MPS_TX_CGEN_DYNAMIC", 0x9470, 0 },
+ { "TxOutLpbk3_CGEN", 31, 1 },
+ { "TxOutLpbk2_CGEN", 30, 1 },
+ { "TxOutLpbk1_CGEN", 29, 1 },
+ { "TxOutLpbk0_CGEN", 28, 1 },
+ { "TxOutMAC3_CGEN", 27, 1 },
+ { "TxOutMAC2_CGEN", 26, 1 },
+ { "TxOutMAC1_CGEN", 25, 1 },
+ { "TxOutMAC0_CGEN", 24, 1 },
+ { "TxSchLpbk3_CGEN", 23, 1 },
+ { "TxSchLpbk2_CGEN", 22, 1 },
+ { "TxSchLpbk1_CGEN", 21, 1 },
+ { "TxSchLpbk0_CGEN", 20, 1 },
+ { "TxSchMAC3_CGEN", 19, 1 },
+ { "TxSchMAC2_CGEN", 18, 1 },
+ { "TxSchMAC1_CGEN", 17, 1 },
+ { "TxSchMAC0_CGEN", 16, 1 },
+ { "TxInCh4_CGEN", 15, 1 },
+ { "TxInCh3_CGEN", 14, 1 },
+ { "TxInCh2_CGEN", 13, 1 },
+ { "TxInCh1_CGEN", 12, 1 },
+ { "TxInCh0_CGEN", 11, 1 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1e2e0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1e6e0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1eae0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1eee0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1f2e0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1f6e0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1fae0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1fee0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH0", 0x30190, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH1", 0x30194, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH2", 0x30198, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3019c, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH4", 0x301a0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x301a8, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x301ac, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x301b0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x301b4, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x301b8, 0 },
+ { "MPS_PORT_TX_FIFO_CTL", 0x301c4, 0 },
+ { "FifoTh", 5, 9 },
+ { "FifoEn", 4, 1 },
+ { "MaxPktCnt", 0, 4 },
+ { "MPS_PORT_FPGA_PAUSE_CTL", 0x301c8, 0 },
+ { "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x301d0, 0 },
+ { "off_pending", 8, 8 },
+ { "on_pending", 0, 8 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH0", 0x34190, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH1", 0x34194, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH2", 0x34198, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3419c, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH4", 0x341a0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x341a8, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x341ac, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x341b0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x341b4, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x341b8, 0 },
+ { "MPS_PORT_TX_FIFO_CTL", 0x341c4, 0 },
+ { "FifoTh", 5, 9 },
+ { "FifoEn", 4, 1 },
+ { "MaxPktCnt", 0, 4 },
+ { "MPS_PORT_FPGA_PAUSE_CTL", 0x341c8, 0 },
+ { "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x341d0, 0 },
+ { "off_pending", 8, 8 },
+ { "on_pending", 0, 8 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH0", 0x38190, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH1", 0x38194, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH2", 0x38198, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3819c, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH4", 0x381a0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x381a8, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x381ac, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x381b0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x381b4, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x381b8, 0 },
+ { "MPS_PORT_TX_FIFO_CTL", 0x381c4, 0 },
+ { "FifoTh", 5, 9 },
+ { "FifoEn", 4, 1 },
+ { "MaxPktCnt", 0, 4 },
+ { "MPS_PORT_FPGA_PAUSE_CTL", 0x381c8, 0 },
+ { "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x381d0, 0 },
+ { "off_pending", 8, 8 },
+ { "on_pending", 0, 8 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH0", 0x3c190, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH1", 0x3c194, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH2", 0x3c198, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3c19c, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH4", 0x3c1a0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x3c1a8, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x3c1ac, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x3c1b0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x3c1b4, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x3c1b8, 0 },
+ { "MPS_PORT_TX_FIFO_CTL", 0x3c1c4, 0 },
+ { "FifoTh", 5, 9 },
+ { "FifoEn", 4, 1 },
+ { "MaxPktCnt", 0, 4 },
+ { "MPS_PORT_FPGA_PAUSE_CTL", 0x3c1c8, 0 },
+ { "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x3c1d0, 0 },
+ { "off_pending", 8, 8 },
+ { "on_pending", 0, 8 },
+ { "MPS_TRC_CFG", 0x9800, 0 },
+ { "TrcMultiRSSFilter", 5, 1 },
+ { "TrcFifoEmpty", 4, 1 },
+ { "TrcIgnoreDropInput", 3, 1 },
+ { "TrcKeepDuplicates", 2, 1 },
+ { "TrcEn", 1, 1 },
+ { "TrcMultiFilter", 0, 1 },
+ { "MPS_TRC_FILTER0_RSS_HASH", 0x9804, 0 },
+ { "MPS_TRC_FILTER0_RSS_CONTROL", 0x9808, 0 },
+ { "RssControl", 16, 8 },
+ { "QueueNumber", 0, 16 },
+ { "MPS_TRC_FILTER1_RSS_HASH", 0x9ff0, 0 },
+ { "MPS_TRC_FILTER1_RSS_CONTROL", 0x9ff4, 0 },
+ { "RssControl", 16, 8 },
+ { "QueueNumber", 0, 16 },
+ { "MPS_TRC_FILTER2_RSS_HASH", 0x9ff8, 0 },
+ { "MPS_TRC_FILTER2_RSS_CONTROL", 0x9ffc, 0 },
+ { "RssControl", 16, 8 },
+ { "QueueNumber", 0, 16 },
+ { "MPS_TRC_FILTER3_RSS_HASH", 0xa000, 0 },
+ { "MPS_TRC_FILTER3_RSS_CONTROL", 0xa004, 0 },
+ { "RssControl", 16, 8 },
+ { "QueueNumber", 0, 16 },
+ { "MPS_TRC_RSS_HASH", 0xa008, 0 },
+ { "MPS_TRC_RSS_CONTROL", 0xa00c, 0 },
+ { "RssControl", 16, 8 },
+ { "QueueNumber", 0, 16 },
+ { "MPS_TRC_VF_OFF_FILTER_0", 0xa010, 0 },
+ { "TrcMPS2TP_MacOnly", 20, 1 },
+ { "TrcAllMPS2TP", 19, 1 },
+ { "TrcAllTP2MPS", 18, 1 },
+ { "TrcAllVf", 17, 1 },
+ { "OffEn", 16, 1 },
+ { "VfFiltEn", 15, 1 },
+ { "VfFiltMask", 8, 7 },
+ { "VfFiltValid", 7, 1 },
+ { "VfFiltData", 0, 7 },
+ { "MPS_TRC_VF_OFF_FILTER_1", 0xa014, 0 },
+ { "TrcMPS2TP_MacOnly", 20, 1 },
+ { "TrcAllMPS2TP", 19, 1 },
+ { "TrcAllTP2MPS", 18, 1 },
+ { "TrcAllVf", 17, 1 },
+ { "OffEn", 16, 1 },
+ { "VfFiltEn", 15, 1 },
+ { "VfFiltMask", 8, 7 },
+ { "VfFiltValid", 7, 1 },
+ { "VfFiltData", 0, 7 },
+ { "MPS_TRC_VF_OFF_FILTER_2", 0xa018, 0 },
+ { "TrcMPS2TP_MacOnly", 20, 1 },
+ { "TrcAllMPS2TP", 19, 1 },
+ { "TrcAllTP2MPS", 18, 1 },
+ { "TrcAllVf", 17, 1 },
+ { "OffEn", 16, 1 },
+ { "VfFiltEn", 15, 1 },
+ { "VfFiltMask", 8, 7 },
+ { "VfFiltValid", 7, 1 },
+ { "VfFiltData", 0, 7 },
+ { "MPS_TRC_VF_OFF_FILTER_3", 0xa01c, 0 },
+ { "TrcMPS2TP_MacOnly", 20, 1 },
+ { "TrcAllMPS2TP", 19, 1 },
+ { "TrcAllTP2MPS", 18, 1 },
+ { "TrcAllVf", 17, 1 },
+ { "OffEn", 16, 1 },
+ { "VfFiltEn", 15, 1 },
+ { "VfFiltMask", 8, 7 },
+ { "VfFiltValid", 7, 1 },
+ { "VfFiltData", 0, 7 },
+ { "MPS_TRC_CGEN", 0xa020, 0 },
+ { "MPS_TRC_FILTER_MATCH_CTL_A", 0x9810, 0 },
+ { "TfInsertActLen", 27, 1 },
+ { "TfInsertTimer", 26, 1 },
+ { "TfInvertMatch", 25, 1 },
+ { "TfPktTooLarge", 24, 1 },
+ { "TfEn", 23, 1 },
+ { "TfPort", 18, 5 },
+ { "TfDrop", 17, 1 },
+ { "TfSopEopErr", 16, 1 },
+ { "TfLength", 8, 5 },
+ { "TfOffset", 0, 5 },
+ { "MPS_TRC_FILTER_MATCH_CTL_A", 0x9814, 0 },
+ { "TfInsertActLen", 27, 1 },
+ { "TfInsertTimer", 26, 1 },
+ { "TfInvertMatch", 25, 1 },
+ { "TfPktTooLarge", 24, 1 },
+ { "TfEn", 23, 1 },
+ { "TfPort", 18, 5 },
+ { "TfDrop", 17, 1 },
+ { "TfSopEopErr", 16, 1 },
+ { "TfLength", 8, 5 },
+ { "TfOffset", 0, 5 },
+ { "MPS_TRC_FILTER_MATCH_CTL_A", 0x9818, 0 },
+ { "TfInsertActLen", 27, 1 },
+ { "TfInsertTimer", 26, 1 },
+ { "TfInvertMatch", 25, 1 },
+ { "TfPktTooLarge", 24, 1 },
+ { "TfEn", 23, 1 },
+ { "TfPort", 18, 5 },
+ { "TfDrop", 17, 1 },
+ { "TfSopEopErr", 16, 1 },
+ { "TfLength", 8, 5 },
+ { "TfOffset", 0, 5 },
+ { "MPS_TRC_FILTER_MATCH_CTL_A", 0x981c, 0 },
+ { "TfInsertActLen", 27, 1 },
+ { "TfInsertTimer", 26, 1 },
+ { "TfInvertMatch", 25, 1 },
+ { "TfPktTooLarge", 24, 1 },
+ { "TfEn", 23, 1 },
+ { "TfPort", 18, 5 },
+ { "TfDrop", 17, 1 },
+ { "TfSopEopErr", 16, 1 },
+ { "TfLength", 8, 5 },
+ { "TfOffset", 0, 5 },
+ { "MPS_TRC_FILTER_MATCH_CTL_B", 0x9820, 0 },
+ { "TfMinPktSize", 16, 9 },
+ { "TfCaptureMax", 0, 14 },
+ { "MPS_TRC_FILTER_MATCH_CTL_B", 0x9824, 0 },
+ { "TfMinPktSize", 16, 9 },
+ { "TfCaptureMax", 0, 14 },
+ { "MPS_TRC_FILTER_MATCH_CTL_B", 0x9828, 0 },
+ { "TfMinPktSize", 16, 9 },
+ { "TfCaptureMax", 0, 14 },
+ { "MPS_TRC_FILTER_MATCH_CTL_B", 0x982c, 0 },
+ { "TfMinPktSize", 16, 9 },
+ { "TfCaptureMax", 0, 14 },
+ { "MPS_TRC_FILTER_RUNT_CTL", 0x9830, 0 },
+ { "MPS_TRC_FILTER_RUNT_CTL", 0x9834, 0 },
+ { "MPS_TRC_FILTER_RUNT_CTL", 0x9838, 0 },
+ { "MPS_TRC_FILTER_RUNT_CTL", 0x983c, 0 },
+ { "MPS_TRC_FILTER_DROP", 0x9840, 0 },
+ { "TfDropInpCount", 16, 16 },
+ { "TfDropBufferCount", 0, 16 },
+ { "MPS_TRC_FILTER_DROP", 0x9844, 0 },
+ { "TfDropInpCount", 16, 16 },
+ { "TfDropBufferCount", 0, 16 },
+ { "MPS_TRC_FILTER_DROP", 0x9848, 0 },
+ { "TfDropInpCount", 16, 16 },
+ { "TfDropBufferCount", 0, 16 },
+ { "MPS_TRC_FILTER_DROP", 0x984c, 0 },
+ { "TfDropInpCount", 16, 16 },
+ { "TfDropBufferCount", 0, 16 },
+ { "MPS_TRC_PERR_INJECT", 0x9850, 0 },
+ { "MemSel", 1, 4 },
+ { "InjectDataErr", 0, 1 },
+ { "MPS_TRC_PERR_ENABLE", 0x9854, 0 },
+ { "MiscPerr", 8, 1 },
+ { "PktFifo", 4, 4 },
+ { "FiltMem", 0, 4 },
+ { "MPS_TRC_INT_ENABLE", 0x9858, 0 },
+ { "PLErrEnb", 9, 1 },
+ { "MiscPerr", 8, 1 },
+ { "PktFifo", 4, 4 },
+ { "FiltMem", 0, 4 },
+ { "MPS_TRC_INT_CAUSE", 0x985c, 0 },
+ { "PLErrEnb", 9, 1 },
+ { "MiscPerr", 8, 1 },
+ { "PktFifo", 4, 4 },
+ { "FiltMem", 0, 4 },
+ { "MPS_TRC_TIMESTAMP_L", 0x9860, 0 },
+ { "MPS_TRC_TIMESTAMP_H", 0x9864, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c00, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c04, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c08, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c0c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c10, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c14, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c18, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c1c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c20, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c24, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c28, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c2c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c30, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c34, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c38, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c3c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c40, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c44, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c48, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c4c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c50, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c54, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c58, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c5c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c60, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c64, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c68, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c6c, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c80, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c84, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c88, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c8c, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c90, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c94, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c98, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c9c, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ca0, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ca4, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ca8, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cac, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cb0, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cb4, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cb8, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cbc, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cc0, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cc4, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cc8, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ccc, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cd0, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cd4, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cd8, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cdc, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ce0, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ce4, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ce8, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cec, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d00, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d04, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d08, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d0c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d10, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d14, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d18, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d1c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d20, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d24, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d28, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d2c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d30, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d34, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d38, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d3c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d40, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d44, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d48, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d4c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d50, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d54, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d58, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d5c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d60, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d64, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d68, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d6c, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d80, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d84, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d88, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d8c, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d90, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d94, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d98, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d9c, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9da0, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9da4, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9da8, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dac, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9db0, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9db4, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9db8, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dbc, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dc0, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dc4, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dc8, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dcc, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dd0, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dd4, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dd8, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9ddc, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9de0, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9de4, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9de8, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dec, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e00, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e04, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e08, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e0c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e10, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e14, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e18, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e1c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e20, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e24, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e28, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e2c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e30, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e34, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e38, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e3c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e40, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e44, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e48, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e4c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e50, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e54, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e58, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e5c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e60, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e64, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e68, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e6c, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e80, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e84, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e88, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e8c, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e90, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e94, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e98, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e9c, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ea0, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ea4, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ea8, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9eac, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9eb0, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9eb4, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9eb8, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ebc, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ec0, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ec4, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ec8, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ecc, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ed0, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ed4, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ed8, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9edc, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ee0, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ee4, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ee8, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9eec, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f00, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f04, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f08, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f0c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f10, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f14, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f18, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f1c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f20, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f24, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f28, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f2c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f30, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f34, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f38, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f3c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f40, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f44, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f48, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f4c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f50, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f54, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f58, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f5c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f60, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f64, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f68, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f6c, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f80, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f84, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f88, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f8c, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f90, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f94, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f98, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f9c, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fa0, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fa4, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fa8, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fac, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fb0, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fb4, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fb8, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fbc, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fc0, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fc4, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fc8, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fcc, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fd0, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fd4, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fd8, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fdc, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fe0, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fe4, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fe8, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fec, 0 },
+ { "MPS_STAT_CTL", 0x9600, 0 },
+ { "StatStopCtrl", 10, 1 },
+ { "StopStat", 9, 1 },
+ { "StatWriteCtrl", 8, 1 },
+ { "CountLbPF", 7, 1 },
+ { "CountLbVF", 6, 1 },
+ { "CountPauseMCRx", 5, 1 },
+ { "CountPauseStatRx", 4, 1 },
+ { "CountPauseMCTx", 3, 1 },
+ { "CountPauseStatTx", 2, 1 },
+ { "CountVFinPF", 1, 1 },
+ { "LpbkErrStat", 0, 1 },
+ { "MPS_STAT_INT_ENABLE", 0x9608, 0 },
+ { "MPS_STAT_INT_CAUSE", 0x960c, 0 },
+ { "MPS_STAT_PERR_INT_ENABLE_SRAM", 0x9610, 0 },
+ { "Rxbg", 27, 2 },
+ { "Rxpf", 22, 5 },
+ { "Txpf", 18, 4 },
+ { "Rxport", 11, 7 },
+ { "Lbport", 6, 5 },
+ { "Txport", 0, 6 },
+ { "MPS_STAT_PERR_INT_CAUSE_SRAM", 0x9614, 0 },
+ { "Rxbg", 27, 2 },
+ { "Rxpf", 22, 5 },
+ { "Txpf", 18, 4 },
+ { "Rxport", 11, 7 },
+ { "Lbport", 6, 5 },
+ { "Txport", 0, 6 },
+ { "MPS_STAT_PERR_ENABLE_SRAM", 0x9618, 0 },
+ { "Rxbg", 27, 2 },
+ { "Rxpf", 22, 5 },
+ { "Txpf", 18, 4 },
+ { "Rxport", 11, 7 },
+ { "Lbport", 6, 5 },
+ { "Txport", 0, 6 },
+ { "MPS_STAT_PERR_INT_ENABLE_TX_FIFO", 0x961c, 0 },
+ { "TxCh", 20, 4 },
+ { "Tx", 12, 8 },
+ { "Pause", 8, 4 },
+ { "Drop", 0, 8 },
+ { "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 0x9620, 0 },
+ { "TxCh", 20, 4 },
+ { "Tx", 12, 8 },
+ { "Pause", 8, 4 },
+ { "Drop", 0, 8 },
+ { "MPS_STAT_PERR_ENABLE_TX_FIFO", 0x9624, 0 },
+ { "TxCh", 20, 4 },
+ { "Tx", 12, 8 },
+ { "Pause", 8, 4 },
+ { "Drop", 0, 8 },
+ { "MPS_STAT_PERR_INT_ENABLE_RX_FIFO", 0x9628, 0 },
+ { "Pause", 20, 4 },
+ { "Lpbk", 16, 4 },
+ { "Nq", 8, 8 },
+ { "PV", 4, 4 },
+ { "Mac", 0, 4 },
+ { "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 0x962c, 0 },
+ { "Pause", 20, 4 },
+ { "Lpbk", 16, 4 },
+ { "Nq", 8, 8 },
+ { "PV", 4, 4 },
+ { "Mac", 0, 4 },
+ { "MPS_STAT_PERR_ENABLE_RX_FIFO", 0x9630, 0 },
+ { "Pause", 20, 4 },
+ { "Lpbk", 16, 4 },
+ { "Nq", 8, 8 },
+ { "PV", 4, 4 },
+ { "Mac", 0, 4 },
+ { "MPS_STAT_PERR_INJECT", 0x9634, 0 },
+ { "MemSel", 1, 7 },
+ { "InjectDataErr", 0, 1 },
+ { "MPS_STAT_DEBUG_SUB_SEL", 0x9638, 0 },
+ { "SubPrtH", 5, 5 },
+ { "SubPrtL", 0, 5 },
+ { "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L", 0x9640, 0 },
+ { "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H", 0x9644, 0 },
+ { "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L", 0x9648, 0 },
+ { "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H", 0x964c, 0 },
+ { "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L", 0x9650, 0 },
+ { "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H", 0x9654, 0 },
+ { "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L", 0x9658, 0 },
+ { "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H", 0x965c, 0 },
+ { "MPS_STAT_RX_BG_0_LB_DROP_FRAME_L", 0x9660, 0 },
+ { "MPS_STAT_RX_BG_0_LB_DROP_FRAME_H", 0x9664, 0 },
+ { "MPS_STAT_RX_BG_1_LB_DROP_FRAME_L", 0x9668, 0 },
+ { "MPS_STAT_RX_BG_1_LB_DROP_FRAME_H", 0x966c, 0 },
+ { "MPS_STAT_RX_BG_2_LB_DROP_FRAME_L", 0x9670, 0 },
+ { "MPS_STAT_RX_BG_2_LB_DROP_FRAME_H", 0x9674, 0 },
+ { "MPS_STAT_RX_BG_3_LB_DROP_FRAME_L", 0x9678, 0 },
+ { "MPS_STAT_RX_BG_3_LB_DROP_FRAME_H", 0x967c, 0 },
+ { "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L", 0x9680, 0 },
+ { "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H", 0x9684, 0 },
+ { "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L", 0x9688, 0 },
+ { "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H", 0x968c, 0 },
+ { "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L", 0x9690, 0 },
+ { "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H", 0x9694, 0 },
+ { "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L", 0x9698, 0 },
+ { "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H", 0x969c, 0 },
+ { "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L", 0x96a0, 0 },
+ { "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H", 0x96a4, 0 },
+ { "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L", 0x96a8, 0 },
+ { "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H", 0x96ac, 0 },
+ { "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L", 0x96b0, 0 },
+ { "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H", 0x96b4, 0 },
+ { "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L", 0x96b8, 0 },
+ { "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H", 0x96bc, 0 },
+ { "MPS_STAT_PERR_INT_ENABLE_SRAM1", 0x96c0, 0 },
+ { "Rxvf", 5, 3 },
+ { "Txvf", 0, 5 },
+ { "MPS_STAT_PERR_INT_CAUSE_SRAM1", 0x96c4, 0 },
+ { "Rxvf", 5, 3 },
+ { "Txvf", 0, 5 },
+ { "MPS_STAT_PERR_ENABLE_SRAM1", 0x96c8, 0 },
+ { "Rxvf", 5, 3 },
+ { "Txvf", 0, 5 },
+ { "MPS_STAT_STOP_UPD_BG", 0x96cc, 0 },
+ { "MPS_STAT_STOP_UPD_PORT", 0x96d0, 0 },
+ { "PtLpbk", 8, 4 },
+ { "PtTx", 4, 4 },
+ { "PtRx", 0, 4 },
+ { "MPS_STAT_STOP_UPD_PF", 0x96d4, 0 },
+ { "PFTx", 8, 8 },
+ { "PFRx", 0, 8 },
+ { "MPS_STAT_STOP_UPD_TX_VF_0_31", 0x96d8, 0 },
+ { "MPS_STAT_STOP_UPD_TX_VF_32_63", 0x96dc, 0 },
+ { "MPS_STAT_STOP_UPD_TX_VF_64_95", 0x96e0, 0 },
+ { "MPS_STAT_STOP_UPD_TX_VF_96_127", 0x96e4, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_0_31", 0x96e8, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_32_63", 0x96ec, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_64_95", 0x96f0, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_96_127", 0x96f4, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x30400, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x30404, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x30408, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3040c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x30410, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x30414, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x30418, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3041c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x30420, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x30424, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x30428, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3042c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_L", 0x30430, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_H", 0x30434, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x30438, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3043c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x30440, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x30444, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x30448, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3044c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x30450, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x30454, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x30458, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3045c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x30460, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x30464, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_L", 0x30468, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3046c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x30470, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x30474, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x30478, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3047c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x30480, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x30484, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x30488, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3048c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x30490, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x30494, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x30498, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3049c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x304a0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x304a4, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x304a8, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x304ac, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x304b0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x304b4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x304c0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x304c4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x304c8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x304cc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x304d0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x304d4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x304d8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x304dc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x304e0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x304e4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x304e8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x304ec, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_L", 0x304f0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_H", 0x304f4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x304f8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x304fc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x30500, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x30504, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x30508, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3050c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x30510, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x30514, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x30518, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3051c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x30520, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x30524, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x30528, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3052c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x30540, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x30544, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x30548, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3054c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x30550, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x30554, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x30558, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3055c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x30560, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x30564, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x30568, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3056c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x30570, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x30574, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x30578, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3057c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x30580, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x30584, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x30588, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3058c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_L", 0x30590, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_H", 0x30594, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x30598, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3059c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x305a0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x305a4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x305a8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x305ac, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x305b0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x305b4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x305b8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x305bc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x305c0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x305c4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x305c8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x305cc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x305d0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x305d4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x305d8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x305dc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x305e0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x305e4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x305e8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x305ec, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x305f0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x305f4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x305f8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x305fc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x30600, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x30604, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x30608, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3060c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x30610, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x30614, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x30618, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3061c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x34400, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x34404, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x34408, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3440c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x34410, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x34414, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x34418, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3441c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x34420, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x34424, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x34428, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3442c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_L", 0x34430, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_H", 0x34434, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x34438, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3443c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x34440, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x34444, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x34448, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3444c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x34450, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x34454, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x34458, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3445c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x34460, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x34464, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_L", 0x34468, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3446c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x34470, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x34474, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x34478, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3447c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x34480, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x34484, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x34488, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3448c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x34490, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x34494, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x34498, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3449c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x344a0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x344a4, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x344a8, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x344ac, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x344b0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x344b4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x344c0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x344c4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x344c8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x344cc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x344d0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x344d4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x344d8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x344dc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x344e0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x344e4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x344e8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x344ec, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_L", 0x344f0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_H", 0x344f4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x344f8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x344fc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x34500, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x34504, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x34508, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3450c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x34510, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x34514, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x34518, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3451c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x34520, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x34524, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x34528, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3452c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x34540, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x34544, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x34548, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3454c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x34550, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x34554, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x34558, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3455c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x34560, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x34564, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x34568, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3456c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x34570, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x34574, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x34578, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3457c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x34580, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x34584, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x34588, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3458c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_L", 0x34590, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_H", 0x34594, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x34598, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3459c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x345a0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x345a4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x345a8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x345ac, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x345b0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x345b4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x345b8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x345bc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x345c0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x345c4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x345c8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x345cc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x345d0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x345d4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x345d8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x345dc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x345e0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x345e4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x345e8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x345ec, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x345f0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x345f4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x345f8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x345fc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x34600, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x34604, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x34608, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3460c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x34610, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x34614, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x34618, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3461c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x38400, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x38404, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x38408, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3840c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x38410, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x38414, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x38418, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3841c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x38420, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x38424, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x38428, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3842c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_L", 0x38430, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_H", 0x38434, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x38438, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3843c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x38440, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x38444, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x38448, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3844c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x38450, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x38454, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x38458, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3845c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x38460, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x38464, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_L", 0x38468, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3846c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x38470, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x38474, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x38478, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3847c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x38480, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x38484, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x38488, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3848c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x38490, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x38494, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x38498, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3849c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x384a0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x384a4, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x384a8, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x384ac, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x384b0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x384b4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x384c0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x384c4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x384c8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x384cc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x384d0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x384d4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x384d8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x384dc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x384e0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x384e4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x384e8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x384ec, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_L", 0x384f0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_H", 0x384f4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x384f8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x384fc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x38500, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x38504, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x38508, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3850c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x38510, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x38514, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x38518, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3851c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x38520, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x38524, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x38528, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3852c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x38540, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x38544, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x38548, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3854c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x38550, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x38554, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x38558, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3855c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x38560, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x38564, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x38568, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3856c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x38570, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x38574, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x38578, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3857c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x38580, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x38584, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x38588, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3858c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_L", 0x38590, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_H", 0x38594, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x38598, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3859c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x385a0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x385a4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x385a8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x385ac, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x385b0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x385b4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x385b8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x385bc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x385c0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x385c4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x385c8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x385cc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x385d0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x385d4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x385d8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x385dc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x385e0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x385e4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x385e8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x385ec, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x385f0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x385f4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x385f8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x385fc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x38600, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x38604, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x38608, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3860c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x38610, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x38614, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x38618, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3861c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x3c400, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x3c404, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x3c408, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3c40c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x3c410, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x3c414, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x3c418, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3c41c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x3c420, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x3c424, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x3c428, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3c42c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_L", 0x3c430, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_H", 0x3c434, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x3c438, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3c43c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x3c440, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x3c444, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x3c448, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3c44c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x3c450, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x3c454, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x3c458, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3c45c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x3c460, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x3c464, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_L", 0x3c468, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3c46c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x3c470, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x3c474, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x3c478, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3c47c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x3c480, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x3c484, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x3c488, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3c48c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x3c490, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x3c494, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x3c498, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3c49c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x3c4a0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x3c4a4, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x3c4a8, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x3c4ac, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x3c4b0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x3c4b4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x3c4c0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x3c4c4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x3c4c8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x3c4cc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x3c4d0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x3c4d4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x3c4d8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x3c4dc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x3c4e0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x3c4e4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x3c4e8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x3c4ec, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_L", 0x3c4f0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_H", 0x3c4f4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x3c4f8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x3c4fc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x3c500, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x3c504, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x3c508, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3c50c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x3c510, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x3c514, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x3c518, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3c51c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x3c520, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x3c524, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x3c528, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3c52c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x3c540, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x3c544, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x3c548, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3c54c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x3c550, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x3c554, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x3c558, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3c55c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x3c560, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x3c564, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x3c568, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3c56c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x3c570, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x3c574, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x3c578, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3c57c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x3c580, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x3c584, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x3c588, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3c58c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_L", 0x3c590, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_H", 0x3c594, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x3c598, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3c59c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x3c5a0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x3c5a4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x3c5a8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x3c5ac, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x3c5b0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x3c5b4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x3c5b8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x3c5bc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x3c5c0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x3c5c4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x3c5c8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x3c5cc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x3c5d0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x3c5d4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x3c5d8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x3c5dc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x3c5e0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x3c5e4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x3c5e8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x3c5ec, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x3c5f0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x3c5f4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x3c5f8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x3c5fc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x3c600, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x3c604, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x3c608, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3c60c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x3c610, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x3c614, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x3c618, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3c61c, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e300, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e304, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e308, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e30c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e310, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e314, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e318, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e31c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e320, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e324, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e328, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e32c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e330, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e334, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e338, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e33c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e340, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e344, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e348, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e34c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e350, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e354, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e358, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e35c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e360, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e364, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e368, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e36c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e370, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e374, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e378, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e37c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e380, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e384, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e700, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e704, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e708, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e70c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e710, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e714, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e718, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e71c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e720, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e724, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e728, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e72c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e730, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e734, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e738, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e73c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e740, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e744, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e748, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e74c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e750, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e754, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e758, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e75c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e760, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e764, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e768, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e76c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e770, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e774, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e778, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e77c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e780, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e784, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1eb00, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1eb04, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1eb08, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1eb0c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1eb10, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1eb14, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1eb18, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1eb1c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1eb20, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1eb24, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1eb28, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1eb2c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1eb30, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1eb34, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1eb38, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1eb3c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1eb40, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1eb44, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1eb48, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1eb4c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1eb50, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1eb54, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1eb58, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1eb5c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1eb60, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1eb64, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1eb68, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1eb6c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1eb70, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1eb74, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1eb78, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1eb7c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1eb80, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1eb84, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ef00, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ef04, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ef08, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ef0c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ef10, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ef14, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ef18, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ef1c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ef20, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ef24, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ef28, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ef2c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ef30, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ef34, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ef38, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ef3c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ef40, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ef44, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ef48, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ef4c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ef50, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ef54, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ef58, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ef5c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ef60, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ef64, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ef68, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ef6c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ef70, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ef74, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ef78, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ef7c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ef80, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ef84, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f300, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f304, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f308, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f30c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f310, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f314, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f318, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f31c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f320, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f324, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f328, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f32c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f330, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f334, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f338, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f33c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f340, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f344, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f348, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f34c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f350, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f354, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f358, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f35c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f360, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f364, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f368, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f36c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f370, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f374, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f378, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f37c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f380, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f384, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f700, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f704, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f708, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f70c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f710, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f714, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f718, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f71c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f720, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f724, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f728, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f72c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f730, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f734, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f738, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f73c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f740, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f744, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f748, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f74c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f750, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f754, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f758, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f75c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f760, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f764, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f768, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f76c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f770, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f774, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f778, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f77c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f780, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f784, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1fb00, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1fb04, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1fb08, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1fb0c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1fb10, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1fb14, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1fb18, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1fb1c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1fb20, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1fb24, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1fb28, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1fb2c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1fb30, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1fb34, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1fb38, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1fb3c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1fb40, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1fb44, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1fb48, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1fb4c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1fb50, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1fb54, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1fb58, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1fb5c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1fb60, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1fb64, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1fb68, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1fb6c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1fb70, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1fb74, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1fb78, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1fb7c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1fb80, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1fb84, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ff00, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ff04, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ff08, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ff0c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ff10, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ff14, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ff18, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ff1c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ff20, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ff24, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ff28, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ff2c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ff30, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ff34, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ff38, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ff3c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ff40, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ff44, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ff48, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ff4c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ff50, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ff54, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ff58, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ff5c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ff60, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ff64, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ff68, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ff6c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ff70, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ff74, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ff78, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ff7c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ff80, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ff84, 0 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30200, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30204, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30208, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3020c, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30210, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30214, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30218, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3021c, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30220, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30224, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30228, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3022c, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30230, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30234, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30238, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3023c, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30240, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30244, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30248, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3024c, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30250, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30254, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30258, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3025c, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30260, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30264, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30268, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3026c, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30270, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30274, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30278, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3027c, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30280, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30284, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30288, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3028c, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30290, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30294, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30298, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3029c, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x302a0, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x302a4, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x302a8, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x302ac, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x302b0, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x302b4, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
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+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3c2dc, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3c2e0, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3c2e4, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3c2e8, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3c2ec, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3c2f0, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3c2f4, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3c2f8, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3c2fc, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3c300, 0 },
+ { "Valid", 20, 1 },
+ { "PortMap", 16, 4 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_HASH_CTL", 0x30304, 0 },
+ { "UnicastEnable", 31, 1 },
+ { "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x30308, 0 },
+ { "Enable", 31, 1 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3030c, 0 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x30310, 0 },
+ { "MatchBoth", 17, 1 },
+ { "Valid", 16, 1 },
+ { "DA", 0, 16 },
+ { "MPS_PORT_CLS_BMC_VLAN", 0x30314, 0 },
+ { "BMC_VLAN_SEL", 13, 1 },
+ { "Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PORT_CLS_CTL", 0x30318, 0 },
+ { "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
+ { "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
+ { "LPBK_TCAM_PRIORITY", 12, 1 },
+ { "LPBK_SMAC_TCAM_SEL", 10, 2 },
+ { "LPBK_DMAC_TCAM_SEL", 8, 2 },
+ { "TCAM1_HIT_PRIORITY", 7, 1 },
+ { "TCAM0_HIT_PRIORITY", 6, 1 },
+ { "TCAM_PRIORITY", 5, 1 },
+ { "SMAC_TCAM_SEL", 3, 2 },
+ { "DMAC_TCAM_SEL", 1, 2 },
+ { "PF_VLAN_SEL", 0, 1 },
+ { "MPS_PORT_CLS_HASH_CTL", 0x34304, 0 },
+ { "UnicastEnable", 31, 1 },
+ { "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x34308, 0 },
+ { "Enable", 31, 1 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3430c, 0 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x34310, 0 },
+ { "MatchBoth", 17, 1 },
+ { "Valid", 16, 1 },
+ { "DA", 0, 16 },
+ { "MPS_PORT_CLS_BMC_VLAN", 0x34314, 0 },
+ { "BMC_VLAN_SEL", 13, 1 },
+ { "Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PORT_CLS_CTL", 0x34318, 0 },
+ { "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
+ { "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
+ { "LPBK_TCAM_PRIORITY", 12, 1 },
+ { "LPBK_SMAC_TCAM_SEL", 10, 2 },
+ { "LPBK_DMAC_TCAM_SEL", 8, 2 },
+ { "TCAM1_HIT_PRIORITY", 7, 1 },
+ { "TCAM0_HIT_PRIORITY", 6, 1 },
+ { "TCAM_PRIORITY", 5, 1 },
+ { "SMAC_TCAM_SEL", 3, 2 },
+ { "DMAC_TCAM_SEL", 1, 2 },
+ { "PF_VLAN_SEL", 0, 1 },
+ { "MPS_PORT_CLS_HASH_CTL", 0x38304, 0 },
+ { "UnicastEnable", 31, 1 },
+ { "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x38308, 0 },
+ { "Enable", 31, 1 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3830c, 0 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x38310, 0 },
+ { "MatchBoth", 17, 1 },
+ { "Valid", 16, 1 },
+ { "DA", 0, 16 },
+ { "MPS_PORT_CLS_BMC_VLAN", 0x38314, 0 },
+ { "BMC_VLAN_SEL", 13, 1 },
+ { "Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PORT_CLS_CTL", 0x38318, 0 },
+ { "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
+ { "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
+ { "LPBK_TCAM_PRIORITY", 12, 1 },
+ { "LPBK_SMAC_TCAM_SEL", 10, 2 },
+ { "LPBK_DMAC_TCAM_SEL", 8, 2 },
+ { "TCAM1_HIT_PRIORITY", 7, 1 },
+ { "TCAM0_HIT_PRIORITY", 6, 1 },
+ { "TCAM_PRIORITY", 5, 1 },
+ { "SMAC_TCAM_SEL", 3, 2 },
+ { "DMAC_TCAM_SEL", 1, 2 },
+ { "PF_VLAN_SEL", 0, 1 },
+ { "MPS_PORT_CLS_HASH_CTL", 0x3c304, 0 },
+ { "UnicastEnable", 31, 1 },
+ { "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x3c308, 0 },
+ { "Enable", 31, 1 },
+ { "MultiListen", 15, 1 },
+ { "Priority", 12, 3 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3c30c, 0 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x3c310, 0 },
+ { "MatchBoth", 17, 1 },
+ { "Valid", 16, 1 },
+ { "DA", 0, 16 },
+ { "MPS_PORT_CLS_BMC_VLAN", 0x3c314, 0 },
+ { "BMC_VLAN_SEL", 13, 1 },
+ { "Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PORT_CLS_CTL", 0x3c318, 0 },
+ { "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
+ { "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
+ { "LPBK_TCAM_PRIORITY", 12, 1 },
+ { "LPBK_SMAC_TCAM_SEL", 10, 2 },
+ { "LPBK_DMAC_TCAM_SEL", 8, 2 },
+ { "TCAM1_HIT_PRIORITY", 7, 1 },
+ { "TCAM0_HIT_PRIORITY", 6, 1 },
+ { "TCAM_PRIORITY", 5, 1 },
+ { "SMAC_TCAM_SEL", 3, 2 },
+ { "DMAC_TCAM_SEL", 1, 2 },
+ { "PF_VLAN_SEL", 0, 1 },
+ { "MPS_CLS_CTL", 0xd000, 0 },
+ { "MemWriteFault", 4, 1 },
+ { "MemWriteWaiting", 3, 1 },
+ { "CimNoPromiscuous", 2, 1 },
+ { "HypervisorOnly", 1, 1 },
+ { "VlanClsEn", 0, 1 },
+ { "MPS_CLS_ARB_WEIGHT", 0xd004, 0 },
+ { "PlWeight", 16, 5 },
+ { "CimWeight", 8, 5 },
+ { "LpbkWeight", 0, 5 },
+ { "MPS_CLS_BMC_MAC_ADDR_L", 0xd010, 0 },
+ { "MPS_CLS_BMC_MAC_ADDR_H", 0xd014, 0 },
+ { "MatchBoth", 17, 1 },
+ { "Valid", 16, 1 },
+ { "DA", 0, 16 },
+ { "MPS_CLS_BMC_VLAN", 0xd018, 0 },
+ { "Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_PERR_INJECT", 0xd01c, 0 },
+ { "MemSel", 1, 2 },
+ { "InjectDataErr", 0, 1 },
+ { "MPS_CLS_PERR_ENABLE", 0xd020, 0 },
+ { "HashSRAM", 2, 1 },
+ { "MatchTCAM", 1, 1 },
+ { "MatchSRAM", 0, 1 },
+ { "MPS_CLS_INT_ENABLE", 0xd024, 0 },
+ { "PLErrEnb", 3, 1 },
+ { "HashSRAM", 2, 1 },
+ { "MatchTCAM", 1, 1 },
+ { "MatchSRAM", 0, 1 },
+ { "MPS_CLS_INT_CAUSE", 0xd028, 0 },
+ { "PLErrEnb", 3, 1 },
+ { "HashSRAM", 2, 1 },
+ { "MatchTCAM", 1, 1 },
+ { "MatchSRAM", 0, 1 },
+ { "MPS_CLS_PL_TEST_DATA_L", 0xd02c, 0 },
+ { "MPS_CLS_PL_TEST_DATA_H", 0xd030, 0 },
+ { "MPS_CLS_PL_TEST_RES_DATA", 0xd034, 0 },
+ { "Cls_Priority", 24, 3 },
+ { "Cls_Replicate", 23, 1 },
+ { "Cls_Index", 14, 9 },
+ { "Cls_VF", 7, 7 },
+ { "Cls_VF_Vld", 6, 1 },
+ { "Cls_PF", 3, 3 },
+ { "Cls_Match", 0, 3 },
+ { "MPS_CLS_PL_TEST_CTL", 0xd038, 0 },
+ { "MPS_CLS_PORT_BMC_CTL", 0xd03c, 0 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfc0, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfc4, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfc8, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfcc, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfd0, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfd4, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfd8, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfdc, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfe0, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_SRAM_L", 0xe000, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe008, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe010, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe018, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe020, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe028, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe030, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe038, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe040, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe048, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe050, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe058, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe060, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe068, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe070, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe078, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe080, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe088, 0 },
+ { "MultiListen3", 28, 1 },
+ { "MultiListen2", 27, 1 },
+ { "MultiListen1", 26, 1 },
+ { "MultiListen0", 25, 1 },
+ { "Priority3", 22, 3 },
+ { "Priority2", 19, 3 },
+ { "Priority1", 16, 3 },
+ { "Priority0", 13, 3 },
+ { "Valid", 12, 1 },
+ { "Replicate", 11, 1 },
+ { "PF", 8, 3 },
+ { "VF_Valid", 7, 1 },
+ { "VF", 0, 7 },
+ { "MPS_CLS_SRAM_L", 0xe090, 0 },
+ { "MultiListen3", 28, 1 },
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+ { "MPS_CLS_SRAM_H", 0xed34, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed3c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed44, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed4c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed54, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed5c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed64, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed6c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed74, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed7c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed84, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed8c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed94, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xed9c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeda4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xedac, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xedb4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xedbc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xedc4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xedcc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xedd4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeddc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xede4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xedec, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xedf4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xedfc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee04, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee0c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee14, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee1c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee24, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee2c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee34, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee3c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee44, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee4c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee54, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee5c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee64, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee6c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee74, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee7c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee84, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee8c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee94, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee9c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeea4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeeac, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeeb4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeebc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeec4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeecc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeed4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeedc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeee4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeeec, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeef4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeefc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef04, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef0c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef14, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef1c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef24, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef2c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef34, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef3c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef44, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef4c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef54, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef5c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef64, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef6c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef74, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef7c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef84, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef8c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef94, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef9c, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefa4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefac, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefb4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefbc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefc4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefcc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefd4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefdc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefe4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefec, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeff4, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeffc, 0 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_TCAM_Y_L", 0xf000, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf010, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf020, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf030, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf040, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf050, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf060, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf070, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf080, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf090, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf0a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf0b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf0c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf0d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf0e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf0f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf100, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf110, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf120, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf130, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf140, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf150, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf160, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf170, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf180, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf190, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf1a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf1b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf1c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf1d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf1e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf1f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf200, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf210, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf220, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf230, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf240, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf250, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf260, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf270, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf280, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf290, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf2a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf2b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf2c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf2d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf2e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf2f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf300, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf310, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf320, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf330, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf340, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf350, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf360, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf370, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf380, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf390, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf3a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf3b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf3c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf3d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf3e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf3f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf400, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf410, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf420, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf430, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf440, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf450, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf460, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf470, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf480, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf490, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf4a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf4b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf4c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf4d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf4e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf4f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf500, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf510, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf520, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf530, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf540, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf550, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf560, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf570, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf580, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf590, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf5a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf5b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf5c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf5d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf5e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf5f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf600, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf610, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf620, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf630, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf640, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf650, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf660, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf670, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf680, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf690, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf6a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf6b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf6c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf6d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf6e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf6f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf700, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf710, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf720, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf730, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf740, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf750, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf760, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf770, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf780, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf790, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf7a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf7b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf7c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf7d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf7e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf7f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf800, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf810, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf820, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf830, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf840, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf850, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf860, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf870, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf880, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf890, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf8a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf8b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf8c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf8d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf8e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf8f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf900, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf910, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf920, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf930, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf940, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf950, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf960, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf970, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf980, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf990, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf9a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf9b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf9c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf9d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf9e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xf9f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfa00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfa10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfa20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfa30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfa40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfa50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfa60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfa70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfa80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfa90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfaa0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfab0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfac0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfad0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfae0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfaf0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfb00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfb10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfb20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfb30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfb40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfb50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfb60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfb70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfb80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfb90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfba0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfbb0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfbc0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfbd0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfbe0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfbf0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfc00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfc10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfc20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfc30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfc40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfc50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfc60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfc70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfc80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfc90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfca0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfcb0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfcc0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfcd0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfce0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfcf0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfd00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfd10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfd20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfd30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfd40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfd50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfd60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfd70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfd80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfd90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfda0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfdb0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfdc0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfdd0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfde0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfdf0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfe00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfe10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfe20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfe30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfe40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfe50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfe60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfe70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfe80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfe90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfea0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfeb0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfec0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfed0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfee0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfef0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xff00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xff10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xff20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xff30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xff40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xff50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xff60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xff70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xff80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xff90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xffa0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xffb0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xffc0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xffd0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xffe0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0xfff0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10000, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10010, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10020, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10030, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10040, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10050, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10060, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10070, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10080, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10090, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x100a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x100b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x100c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x100d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x100e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x100f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10100, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10110, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10120, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10130, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10140, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10150, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10160, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10170, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10180, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10190, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x101a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x101b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x101c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x101d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x101e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x101f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10200, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10210, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10220, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10230, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10240, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10250, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10260, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10270, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10280, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10290, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x102a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x102b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x102c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x102d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x102e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x102f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10300, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10310, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10320, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10330, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10340, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10350, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10360, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10370, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10380, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10390, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x103a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x103b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x103c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x103d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x103e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x103f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10400, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10410, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10420, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10430, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10440, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10450, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10460, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10470, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10480, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10490, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x104a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x104b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x104c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x104d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x104e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x104f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10500, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10510, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10520, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10530, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10540, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10550, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10560, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10570, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10580, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10590, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x105a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x105b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x105c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x105d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x105e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x105f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10600, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10610, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10620, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10630, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10640, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10650, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10660, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10670, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10680, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10690, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x106a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x106b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x106c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x106d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x106e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x106f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10700, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10710, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10720, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10730, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10740, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10750, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10760, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10770, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10780, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10790, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x107a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x107b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x107c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x107d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x107e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x107f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10800, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10810, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10820, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10830, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10840, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10850, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10860, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10870, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10880, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10890, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x108a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x108b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x108c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x108d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x108e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x108f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10900, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10910, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10920, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10930, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10940, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10950, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10960, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10970, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10980, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10990, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x109a0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x109b0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x109c0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x109d0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x109e0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x109f0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10a00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10a10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10a20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10a30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10a40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10a50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10a60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10a70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10a80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10a90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10aa0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ab0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ac0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ad0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ae0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10af0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10b00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10b10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10b20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10b30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10b40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10b50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10b60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10b70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10b80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10b90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ba0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10bb0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10bc0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10bd0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10be0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10bf0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10c00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10c10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10c20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10c30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10c40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10c50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10c60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10c70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10c80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10c90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ca0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10cb0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10cc0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10cd0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ce0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10cf0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10d00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10d10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10d20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10d30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10d40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10d50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10d60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10d70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10d80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10d90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10da0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10db0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10dc0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10dd0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10de0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10df0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10e00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10e10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10e20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10e30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10e40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10e50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10e60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10e70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10e80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10e90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ea0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10eb0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ec0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ed0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ee0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ef0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10f00, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10f10, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10f20, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10f30, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10f40, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10f50, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10f60, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10f70, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10f80, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10f90, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10fa0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10fb0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10fc0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10fd0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10fe0, 0 },
+ { "MPS_CLS_TCAM_Y_L", 0x10ff0, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf004, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf014, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf024, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf034, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf044, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf054, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf064, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf074, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf084, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf094, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf0a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf0b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf0c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf0d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf0e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf0f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf104, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf114, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf124, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf134, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf144, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf154, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf164, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf174, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf184, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf194, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf1a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf1b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf1c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf1d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf1e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf1f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf204, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf214, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf224, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf234, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf244, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf254, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf264, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf274, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf284, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf294, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf2a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf2b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf2c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf2d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf2e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf2f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf304, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf314, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf324, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf334, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf344, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf354, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf364, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf374, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf384, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf394, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf3a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf3b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf3c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf3d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf3e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf3f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf404, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf414, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf424, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf434, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf444, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf454, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf464, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf474, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf484, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf494, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf4a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf4b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf4c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf4d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf4e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf4f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf504, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf514, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf524, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf534, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf544, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf554, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf564, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf574, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf584, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf594, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf5a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf5b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf5c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf5d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf5e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf5f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf604, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf614, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf624, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf634, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf644, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf654, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf664, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf674, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf684, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf694, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf6a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf6b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf6c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf6d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf6e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf6f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf704, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf714, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf724, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf734, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf744, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf754, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf764, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf774, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf784, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf794, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf7a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf7b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf7c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf7d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf7e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf7f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf804, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf814, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf824, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf834, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf844, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf854, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf864, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf874, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf884, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf894, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf8a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf8b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf8c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf8d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf8e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf8f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf904, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf914, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf924, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf934, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf944, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf954, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf964, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf974, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf984, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf994, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf9a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf9b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf9c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf9d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf9e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xf9f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfa04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfa14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfa24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfa34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfa44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfa54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfa64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfa74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfa84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfa94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfaa4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfab4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfac4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfad4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfae4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfaf4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfb04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfb14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfb24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfb34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfb44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfb54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfb64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfb74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfb84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfb94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfba4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfbb4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfbc4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfbd4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfbe4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfbf4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfc04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfc14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfc24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfc34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfc44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfc54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfc64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfc74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfc84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfc94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfca4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfcb4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfcc4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfcd4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfce4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfcf4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfd04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfd14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfd24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfd34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfd44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfd54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfd64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfd74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfd84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfd94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfda4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfdb4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfdc4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfdd4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfde4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfdf4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfe04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfe14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfe24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfe34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfe44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfe54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfe64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfe74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfe84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfe94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfea4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfeb4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfec4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfed4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfee4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfef4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xff04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xff14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xff24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xff34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xff44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xff54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xff64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xff74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xff84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xff94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xffa4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xffb4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xffc4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xffd4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xffe4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0xfff4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10004, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10014, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10024, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10034, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10044, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10054, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10064, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10074, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10084, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10094, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x100a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x100b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x100c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x100d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x100e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x100f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10104, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10114, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10124, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10134, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10144, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10154, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10164, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10174, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10184, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10194, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x101a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x101b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x101c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x101d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x101e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x101f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10204, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10214, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10224, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10234, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10244, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10254, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10264, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10274, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10284, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10294, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x102a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x102b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x102c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x102d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x102e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x102f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10304, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10314, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10324, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10334, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10344, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10354, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10364, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10374, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10384, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10394, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x103a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x103b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x103c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x103d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x103e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x103f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10404, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10414, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10424, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10434, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10444, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10454, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10464, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10474, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10484, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10494, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x104a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x104b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x104c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x104d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x104e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x104f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10504, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10514, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10524, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10534, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10544, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10554, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10564, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10574, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10584, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10594, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x105a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x105b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x105c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x105d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x105e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x105f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10604, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10614, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10624, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10634, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10644, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10654, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10664, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10674, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10684, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10694, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x106a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x106b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x106c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x106d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x106e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x106f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10704, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10714, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10724, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10734, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10744, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10754, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10764, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10774, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10784, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10794, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x107a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x107b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x107c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x107d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x107e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x107f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10804, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10814, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10824, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10834, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10844, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10854, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10864, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10874, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10884, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10894, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x108a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x108b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x108c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x108d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x108e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x108f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10904, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10914, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10924, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10934, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10944, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10954, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10964, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10974, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10984, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10994, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x109a4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x109b4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x109c4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x109d4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x109e4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x109f4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10a04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10a14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10a24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10a34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10a44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10a54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10a64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10a74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10a84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10a94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10aa4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ab4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ac4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ad4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ae4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10af4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10b04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10b14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10b24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10b34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10b44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10b54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10b64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10b74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10b84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10b94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ba4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10bb4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10bc4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10bd4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10be4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10bf4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10c04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10c14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10c24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10c34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10c44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10c54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10c64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10c74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10c84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10c94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ca4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10cb4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10cc4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10cd4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ce4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10cf4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10d04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10d14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10d24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10d34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10d44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10d54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10d64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10d74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10d84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10d94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10da4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10db4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10dc4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10dd4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10de4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10df4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10e04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10e14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10e24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10e34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10e44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10e54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10e64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10e74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10e84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10e94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ea4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10eb4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ec4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ed4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ee4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ef4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10f04, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10f14, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10f24, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10f34, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10f44, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10f54, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10f64, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10f74, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10f84, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10f94, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10fa4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10fb4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10fc4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10fd4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10fe4, 0 },
+ { "MPS_CLS_TCAM_Y_H", 0x10ff4, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf008, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf018, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf028, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf038, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf048, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf058, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf068, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf078, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf088, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf098, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf0a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf0b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf0c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf0d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf0e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf0f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf108, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf118, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf128, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf138, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf148, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf158, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf168, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf178, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf188, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf198, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf1a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf1b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf1c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf1d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf1e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf1f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf208, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf218, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf228, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf238, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf248, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf258, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf268, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf278, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf288, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf298, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf2a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf2b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf2c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf2d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf2e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf2f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf308, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf318, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf328, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf338, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf348, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf358, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf368, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf378, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf388, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf398, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf3a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf3b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf3c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf3d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf3e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf3f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf408, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf418, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf428, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf438, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf448, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf458, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf468, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf478, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf488, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf498, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf4a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf4b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf4c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf4d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf4e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf4f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf508, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf518, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf528, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf538, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf548, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf558, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf568, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf578, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf588, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf598, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf5a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf5b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf5c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf5d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf5e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf5f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf608, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf618, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf628, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf638, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf648, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf658, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf668, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf678, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf688, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf698, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf6a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf6b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf6c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf6d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf6e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf6f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf708, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf718, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf728, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf738, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf748, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf758, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf768, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf778, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf788, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf798, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf7a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf7b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf7c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf7d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf7e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf7f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf808, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf818, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf828, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf838, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf848, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf858, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf868, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf878, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf888, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf898, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf8a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf8b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf8c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf8d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf8e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf8f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf908, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf918, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf928, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf938, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf948, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf958, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf968, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf978, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf988, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf998, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf9a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf9b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf9c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf9d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf9e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xf9f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfa08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfa18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfa28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfa38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfa48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfa58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfa68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfa78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfa88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfa98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfaa8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfab8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfac8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfad8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfae8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfaf8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfb08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfb18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfb28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfb38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfb48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfb58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfb68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfb78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfb88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfb98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfba8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfbb8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfbc8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfbd8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfbe8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfbf8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfc08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfc18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfc28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfc38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfc48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfc58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfc68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfc78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfc88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfc98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfca8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfcb8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfcc8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfcd8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfce8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfcf8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfd08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfd18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfd28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfd38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfd48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfd58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfd68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfd78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfd88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfd98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfda8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfdb8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfdc8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfdd8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfde8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfdf8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfe08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfe18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfe28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfe38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfe48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfe58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfe68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfe78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfe88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfe98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfea8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfeb8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfec8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfed8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfee8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfef8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xff08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xff18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xff28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xff38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xff48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xff58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xff68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xff78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xff88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xff98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xffa8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xffb8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xffc8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xffd8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xffe8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0xfff8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10008, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10018, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10028, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10038, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10048, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10058, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10068, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10078, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10088, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10098, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x100a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x100b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x100c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x100d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x100e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x100f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10108, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10118, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10128, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10138, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10148, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10158, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10168, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10178, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10188, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10198, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x101a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x101b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x101c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x101d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x101e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x101f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10208, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10218, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10228, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10238, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10248, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10258, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10268, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10278, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10288, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10298, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x102a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x102b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x102c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x102d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x102e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x102f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10308, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10318, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10328, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10338, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10348, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10358, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10368, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10378, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10388, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10398, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x103a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x103b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x103c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x103d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x103e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x103f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10408, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10418, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10428, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10438, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10448, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10458, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10468, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10478, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10488, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10498, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x104a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x104b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x104c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x104d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x104e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x104f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10508, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10518, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10528, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10538, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10548, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10558, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10568, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10578, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10588, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10598, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x105a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x105b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x105c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x105d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x105e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x105f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10608, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10618, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10628, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10638, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10648, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10658, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10668, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10678, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10688, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10698, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x106a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x106b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x106c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x106d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x106e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x106f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10708, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10718, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10728, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10738, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10748, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10758, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10768, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10778, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10788, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10798, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x107a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x107b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x107c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x107d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x107e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x107f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10808, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10818, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10828, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10838, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10848, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10858, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10868, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10878, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10888, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10898, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x108a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x108b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x108c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x108d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x108e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x108f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10908, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10918, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10928, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10938, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10948, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10958, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10968, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10978, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10988, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10998, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x109a8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x109b8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x109c8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x109d8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x109e8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x109f8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10a08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10a18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10a28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10a38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10a48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10a58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10a68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10a78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10a88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10a98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10aa8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ab8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ac8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ad8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ae8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10af8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10b08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10b18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10b28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10b38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10b48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10b58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10b68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10b78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10b88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10b98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ba8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10bb8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10bc8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10bd8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10be8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10bf8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10c08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10c18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10c28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10c38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10c48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10c58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10c68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10c78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10c88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10c98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ca8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10cb8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10cc8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10cd8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ce8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10cf8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10d08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10d18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10d28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10d38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10d48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10d58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10d68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10d78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10d88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10d98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10da8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10db8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10dc8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10dd8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10de8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10df8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10e08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10e18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10e28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10e38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10e48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10e58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10e68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10e78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10e88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10e98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ea8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10eb8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ec8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ed8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ee8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ef8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10f08, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10f18, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10f28, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10f38, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10f48, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10f58, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10f68, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10f78, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10f88, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10f98, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10fa8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10fb8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10fc8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10fd8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10fe8, 0 },
+ { "MPS_CLS_TCAM_X_L", 0x10ff8, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf00c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf01c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf02c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf03c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf04c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf05c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf06c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf07c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf08c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf09c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf0ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf0bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf0cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf0dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf0ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf0fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf10c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf11c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf12c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf13c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf14c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf15c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf16c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf17c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf18c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf19c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf1ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf1bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf1cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf1dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf1ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf1fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf20c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf21c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf22c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf23c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf24c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf25c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf26c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf27c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf28c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf29c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf2ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf2bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf2cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf2dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf2ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf2fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf30c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf31c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf32c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf33c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf34c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf35c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf36c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf37c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf38c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf39c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf3ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf3bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf3cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf3dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf3ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf3fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf40c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf41c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf42c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf43c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf44c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf45c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf46c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf47c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf48c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf49c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf4ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf4bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf4cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf4dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf4ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf4fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf50c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf51c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf52c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf53c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf54c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf55c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf56c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf57c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf58c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf59c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf5ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf5bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf5cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf5dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf5ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf5fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf60c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf61c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf62c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf63c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf64c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf65c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf66c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf67c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf68c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf69c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf6ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf6bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf6cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf6dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf6ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf6fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf70c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf71c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf72c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf73c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf74c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf75c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf76c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf77c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf78c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf79c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf7ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf7bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf7cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf7dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf7ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf7fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf80c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf81c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf82c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf83c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf84c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf85c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf86c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf87c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf88c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf89c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf8ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf8bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf8cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf8dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf8ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf8fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf90c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf91c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf92c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf93c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf94c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf95c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf96c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf97c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf98c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf99c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf9ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf9bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf9cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf9dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf9ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xf9fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfa0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfa1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfa2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfa3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfa4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfa5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfa6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfa7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfa8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfa9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfaac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfabc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfacc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfadc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfaec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfafc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfb0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfb1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfb2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfb3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfb4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfb5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfb6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfb7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfb8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfb9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfbac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfbbc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfbcc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfbdc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfbec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfbfc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfc0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfc1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfc2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfc3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfc4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfc5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfc6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfc7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfc8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfc9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfcac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfcbc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfccc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfcdc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfcec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfcfc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfd0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfd1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfd2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfd3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfd4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfd5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfd6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfd7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfd8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfd9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfdac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfdbc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfdcc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfddc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfdec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfdfc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfe0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfe1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfe2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfe3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfe4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfe5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfe6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfe7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfe8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfe9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfeac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfebc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfecc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfedc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfeec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfefc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xff0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xff1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xff2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xff3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xff4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xff5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xff6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xff7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xff8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xff9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xffac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xffbc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xffcc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xffdc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xffec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0xfffc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1000c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1001c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1002c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1003c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1004c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1005c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1006c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1007c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1008c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1009c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x100ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x100bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x100cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x100dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x100ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x100fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1010c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1011c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1012c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1013c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1014c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1015c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1016c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1017c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1018c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1019c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x101ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x101bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x101cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x101dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x101ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x101fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1020c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1021c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1022c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1023c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1024c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1025c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1026c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1027c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1028c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1029c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x102ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x102bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x102cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x102dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x102ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x102fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1030c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1031c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1032c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1033c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1034c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1035c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1036c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1037c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1038c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1039c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x103ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x103bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x103cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x103dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x103ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x103fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1040c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1041c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1042c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1043c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1044c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1045c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1046c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1047c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1048c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1049c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x104ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x104bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x104cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x104dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x104ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x104fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1050c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1051c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1052c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1053c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1054c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1055c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1056c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1057c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1058c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1059c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x105ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x105bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x105cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x105dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x105ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x105fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1060c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1061c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1062c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1063c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1064c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1065c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1066c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1067c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1068c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1069c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x106ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x106bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x106cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x106dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x106ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x106fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1070c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1071c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1072c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1073c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1074c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1075c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1076c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1077c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1078c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1079c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x107ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x107bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x107cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x107dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x107ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x107fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1080c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1081c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1082c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1083c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1084c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1085c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1086c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1087c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1088c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1089c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x108ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x108bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x108cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x108dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x108ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x108fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1090c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1091c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1092c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1093c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1094c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1095c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1096c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1097c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1098c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x1099c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x109ac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x109bc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x109cc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x109dc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x109ec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x109fc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10a0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10a1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10a2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10a3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10a4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10a5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10a6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10a7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10a8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10a9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10aac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10abc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10acc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10adc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10aec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10afc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10b0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10b1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10b2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10b3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10b4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10b5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10b6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10b7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10b8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10b9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10bac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10bbc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10bcc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10bdc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10bec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10bfc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10c0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10c1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10c2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10c3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10c4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10c5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10c6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10c7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10c8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10c9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10cac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10cbc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10ccc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10cdc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10cec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10cfc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10d0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10d1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10d2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10d3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10d4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10d5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10d6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10d7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10d8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10d9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10dac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10dbc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10dcc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10ddc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10dec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10dfc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10e0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10e1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10e2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10e3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10e4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10e5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10e6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10e7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10e8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10e9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10eac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10ebc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10ecc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10edc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10eec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10efc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10f0c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10f1c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10f2c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10f3c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10f4c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10f5c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10f6c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10f7c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10f8c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10f9c, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10fac, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10fbc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10fcc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10fdc, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10fec, 0 },
+ { "MPS_CLS_TCAM_X_H", 0x10ffc, 0 },
+ { NULL }
+};
+
+struct reg_info t5_cpl_switch_regs[] = {
+ { "CPL_SWITCH_CNTRL", 0x19040, 0 },
+ { "cpl_pkt_tid", 8, 24 },
+ { "cim_split_enable", 6, 1 },
+ { "cim_truncate_enable", 5, 1 },
+ { "cim_to_up_full_size", 4, 1 },
+ { "cpu_no_enable", 3, 1 },
+ { "switch_table_enable", 2, 1 },
+ { "sge_enable", 1, 1 },
+ { "cim_enable", 0, 1 },
+ { "CPL_SWITCH_TBL_IDX", 0x19044, 0 },
+ { "CPL_SWITCH_TBL_DATA", 0x19048, 0 },
+ { "CPL_SWITCH_ZERO_ERROR", 0x1904c, 0 },
+ { "zero_cmd_ch1", 8, 8 },
+ { "zero_cmd_ch0", 0, 8 },
+ { "CPL_INTR_ENABLE", 0x19050, 0 },
+ { "perr_cpl_128to128_1", 7, 1 },
+ { "perr_cpl_128to128_0", 6, 1 },
+ { "cim_op_map_perr", 5, 1 },
+ { "cim_ovfl_error", 4, 1 },
+ { "tp_framing_error", 3, 1 },
+ { "sge_framing_error", 2, 1 },
+ { "cim_framing_error", 1, 1 },
+ { "zero_switch_error", 0, 1 },
+ { "CPL_INTR_CAUSE", 0x19054, 0 },
+ { "perr_cpl_128to128_1", 7, 1 },
+ { "perr_cpl_128to128_0", 6, 1 },
+ { "cim_op_map_perr", 5, 1 },
+ { "cim_ovfl_error", 4, 1 },
+ { "tp_framing_error", 3, 1 },
+ { "sge_framing_error", 2, 1 },
+ { "cim_framing_error", 1, 1 },
+ { "zero_switch_error", 0, 1 },
+ { "CPL_MAP_TBL_IDX", 0x19058, 0 },
+ { "cim_split_opcode_program", 8, 1 },
+ { "cpl_map_tbl_idx", 0, 8 },
+ { "CPL_MAP_TBL_DATA", 0x1905c, 0 },
+ { NULL }
+};
+
+struct reg_info t5_smb_regs[] = {
+ { "SMB_GLOBAL_TIME_CFG", 0x19060, 0 },
+ { "MacroCntCfg", 8, 5 },
+ { "MicroCntCfg", 0, 8 },
+ { "SMB_MST_TIMEOUT_CFG", 0x19064, 0 },
+ { "SMB_MST_CTL_CFG", 0x19068, 0 },
+ { "MstFifoDbg", 31, 1 },
+ { "MstFifoDbgClr", 30, 1 },
+ { "MstRxByteCfg", 12, 6 },
+ { "MstTxByteCfg", 6, 6 },
+ { "MstReset", 1, 1 },
+ { "MstCtlEn", 0, 1 },
+ { "SMB_MST_CTL_STS", 0x1906c, 0 },
+ { "MstRxByteCnt", 12, 6 },
+ { "MstTxByteCnt", 6, 6 },
+ { "MstBusySts", 0, 1 },
+ { "SMB_MST_TX_FIFO_RDWR", 0x19070, 0 },
+ { "SMB_MST_RX_FIFO_RDWR", 0x19074, 0 },
+ { "SMB_SLV_TIMEOUT_CFG", 0x19078, 0 },
+ { "SMB_SLV_CTL_CFG", 0x1907c, 0 },
+ { "SlvFifoDbg", 31, 1 },
+ { "SlvFifoDbgClr", 30, 1 },
+ { "SlvCrcOutBitInv", 21, 1 },
+ { "SlvCrcOutBitRev", 20, 1 },
+ { "SlvCrcInBitRev", 19, 1 },
+ { "SlvCrcPreset", 11, 8 },
+ { "SlvAddrCfg", 4, 7 },
+ { "SlvAlrtSet", 2, 1 },
+ { "SlvReset", 1, 1 },
+ { "SlvCtlEn", 0, 1 },
+ { "SMB_SLV_CTL_STS", 0x19080, 0 },
+ { "SlvFifoTxCnt", 12, 6 },
+ { "SlvFifoCnt", 6, 6 },
+ { "SlvAlrtSts", 2, 1 },
+ { "SlvBusySts", 0, 1 },
+ { "SMB_SLV_FIFO_RDWR", 0x19084, 0 },
+ { "SMB_INT_ENABLE", 0x1908c, 0 },
+ { "MstTxFifoParEn", 21, 1 },
+ { "MstRxFifoParEn", 20, 1 },
+ { "SlvFifoParEn", 19, 1 },
+ { "SlvUnExpBusStopEn", 18, 1 },
+ { "SlvUnExpBusStartEn", 17, 1 },
+ { "SlvCommandCodeInvEn", 16, 1 },
+ { "SlvByteCntErrEn", 15, 1 },
+ { "SlvUnExpAckMstEn", 14, 1 },
+ { "SlvUnExpNackMstEn", 13, 1 },
+ { "SlvNoBusStopEn", 12, 1 },
+ { "SlvNoRepStartEn", 11, 1 },
+ { "SlvRxAddrIntEn", 10, 1 },
+ { "SlvRxPecErrIntEn", 9, 1 },
+ { "SlvPrepToArpIntEn", 8, 1 },
+ { "SlvTimeOutIntEn", 7, 1 },
+ { "SlvErrIntEn", 6, 1 },
+ { "SlvDoneIntEn", 5, 1 },
+ { "SlvRxRdyIntEn", 4, 1 },
+ { "MstTimeOutIntEn", 3, 1 },
+ { "MstNAckIntEn", 2, 1 },
+ { "MstLostArbIntEn", 1, 1 },
+ { "MstDoneIntEn", 0, 1 },
+ { "SMB_INT_CAUSE", 0x19090, 0 },
+ { "MstTxFifoParInt", 21, 1 },
+ { "MstRxFifoParInt", 20, 1 },
+ { "SlvFifoParInt", 19, 1 },
+ { "SlvUnExpBusStopInt", 18, 1 },
+ { "SlvUnExpBusStartInt", 17, 1 },
+ { "SlvCommandCodeInvInt", 16, 1 },
+ { "SlvByteCntErrInt", 15, 1 },
+ { "SlvUnExpAckMstInt", 14, 1 },
+ { "SlvUnExpNackMstInt", 13, 1 },
+ { "SlvNoBusStopInt", 12, 1 },
+ { "SlvNoRepStartInt", 11, 1 },
+ { "SlvRxAddrInt", 10, 1 },
+ { "SlvRxPecErrInt", 9, 1 },
+ { "SlvPrepToArpInt", 8, 1 },
+ { "SlvTimeOutInt", 7, 1 },
+ { "SlvErrInt", 6, 1 },
+ { "SlvDoneInt", 5, 1 },
+ { "SlvRxRdyInt", 4, 1 },
+ { "MstTimeOutInt", 3, 1 },
+ { "MstNAckInt", 2, 1 },
+ { "MstLostArbInt", 1, 1 },
+ { "MstDoneInt", 0, 1 },
+ { "SMB_DEBUG_DATA", 0x19094, 0 },
+ { "DebugDataH", 16, 16 },
+ { "DebugDataL", 0, 16 },
+ { "SMB_PERR_EN", 0x19098, 0 },
+ { "MstTxFifo", 21, 1 },
+ { "MstRxFifo", 19, 1 },
+ { "SlvFifo", 18, 1 },
+ { "MstTxFifoPerrEn", 2, 1 },
+ { "MstRxFifoPerrEn", 1, 1 },
+ { "SlvFifoPerrEn", 0, 1 },
+ { "SMB_PERR_INJ", 0x1909c, 0 },
+ { "MstTxInjDataErr", 3, 1 },
+ { "MstRxInjDataErr", 2, 1 },
+ { "SlvInjDataErr", 1, 1 },
+ { "FifoInjDataErrEn", 0, 1 },
+ { "SMB_SLV_ARP_CTL", 0x190a0, 0 },
+ { "ArpCommandCode", 2, 8 },
+ { "ArpAddrRes", 1, 1 },
+ { "ArpAddrVal", 0, 1 },
+ { "SMB_ARP_UDID0", 0x190a4, 0 },
+ { "SMB_ARP_UDID1", 0x190a8, 0 },
+ { "SubsystemVendorID", 16, 16 },
+ { "SubsystemDeviceID", 0, 16 },
+ { "SMB_ARP_UDID2", 0x190ac, 0 },
+ { "DeviceID", 16, 16 },
+ { "Interface", 0, 16 },
+ { "SMB_ARP_UDID3", 0x190b0, 0 },
+ { "DeviceCap", 24, 8 },
+ { "VersionID", 16, 8 },
+ { "VendorID", 0, 16 },
+ { "SMB_SLV_AUX_ADDR0", 0x190b4, 0 },
+ { "AuxAddr0Val", 6, 1 },
+ { "AuxAddr0", 0, 6 },
+ { "SMB_SLV_AUX_ADDR1", 0x190b8, 0 },
+ { "AuxAddr1Val", 6, 1 },
+ { "AuxAddr1", 0, 6 },
+ { "SMB_SLV_AUX_ADDR2", 0x190bc, 0 },
+ { "AuxAddr2Val", 6, 1 },
+ { "AuxAddr2", 0, 6 },
+ { "SMB_SLV_AUX_ADDR3", 0x190c0, 0 },
+ { "AuxAddr3Val", 6, 1 },
+ { "AuxAddr3", 0, 6 },
+ { "SMB_COMMAND_CODE0", 0x190c4, 0 },
+ { "SMB_COMMAND_CODE1", 0x190c8, 0 },
+ { "SMB_COMMAND_CODE2", 0x190cc, 0 },
+ { "SMB_COMMAND_CODE3", 0x190d0, 0 },
+ { "SMB_COMMAND_CODE4", 0x190d4, 0 },
+ { "SMB_COMMAND_CODE5", 0x190d8, 0 },
+ { "SMB_COMMAND_CODE6", 0x190dc, 0 },
+ { "SMB_COMMAND_CODE7", 0x190e0, 0 },
+ { "SMB_MICRO_CNT_CLK_CFG", 0x190e4, 0 },
+ { "MacroCntClkCfg", 8, 5 },
+ { "MicroCntClkCfg", 0, 8 },
+ { "SMB_CTL_STATUS", 0x190e8, 0 },
+ { "MstBusBusy", 2, 1 },
+ { "SlvBusBusy", 1, 1 },
+ { "BusBusy", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t5_i2cm_regs[] = {
+ { "I2CM_CFG", 0x190f0, 0 },
+ { "I2CM_DATA", 0x190f4, 0 },
+ { "I2CM_OP", 0x190f8, 0 },
+ { "Busy", 31, 1 },
+ { "Ack", 30, 1 },
+ { "Cont", 1, 1 },
+ { "Op", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t5_mi_regs[] = {
+ { "MI_CFG", 0x19100, 0 },
+ { "T4_St", 14, 1 },
+ { "ClkDiv", 5, 8 },
+ { "St", 3, 2 },
+ { "PreEn", 2, 1 },
+ { "MDIInv", 1, 1 },
+ { "MDIO_1P2V_Sel", 0, 1 },
+ { "MI_ADDR", 0x19104, 0 },
+ { "PhyAddr", 5, 5 },
+ { "RegAddr", 0, 5 },
+ { "MI_DATA", 0x19108, 0 },
+ { "MI_OP", 0x1910c, 0 },
+ { "Busy", 31, 1 },
+ { "St", 3, 2 },
+ { "Inc", 2, 1 },
+ { "Op", 0, 2 },
+ { NULL }
+};
+
+struct reg_info t5_uart_regs[] = {
+ { "UART_CONFIG", 0x19110, 0 },
+ { "StopBits", 22, 2 },
+ { "Parity", 20, 2 },
+ { "DataBits", 16, 4 },
+ { "ClkDiv", 0, 12 },
+ { NULL }
+};
+
+struct reg_info t5_pmu_regs[] = {
+ { "PMU_PART_CG_PWRMODE", 0x19120, 0 },
+ { "SGE_Part_CGEn", 19, 1 },
+ { "PDP_Part_CGEn", 18, 1 },
+ { "TP_Part_CGEn", 17, 1 },
+ { "EDC0_Part_CGEn", 16, 1 },
+ { "EDC1_Part_CGEn", 15, 1 },
+ { "LE_Part_CGEn", 14, 1 },
+ { "MA_Part_CGEn", 13, 1 },
+ { "MC0_Part_CGEn", 12, 1 },
+ { "MC1_Part_CGEn", 11, 1 },
+ { "PCIE_Part_CGEn", 10, 1 },
+ { "InitPowerMode", 0, 2 },
+ { "PMU_SLEEPMODE_WAKEUP", 0x19124, 0 },
+ { "GlobalDeepSleepEn", 6, 1 },
+ { "HWWakeUpEn", 5, 1 },
+ { "Port3SleepMode", 4, 1 },
+ { "Port2SleepMode", 3, 1 },
+ { "Port1SleepMode", 2, 1 },
+ { "Port0SleepMode", 1, 1 },
+ { "WakeUp", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t5_ulp_rx_regs[] = {
+ { "ULP_RX_CTL", 0x19150, 0 },
+ { "PCMD1Threshold", 24, 8 },
+ { "PCMD0Threshold", 16, 8 },
+ { "disable_0B_STAG_ERR", 14, 1 },
+ { "RDMA_0b_wr_opcode", 10, 4 },
+ { "RDMA_0b_wr_pass", 9, 1 },
+ { "STAG_RQE", 8, 1 },
+ { "RDMA_State_En", 7, 1 },
+ { "Crc1_En", 6, 1 },
+ { "RDMA_0b_wr_cqe", 5, 1 },
+ { "PCIE_Atrb_En", 4, 1 },
+ { "RDMA_permissive_mode", 3, 1 },
+ { "PagePodME", 2, 1 },
+ { "IscsiTagTcb", 1, 1 },
+ { "TddpTagTcb", 0, 1 },
+ { "ULP_RX_INT_ENABLE", 0x19154, 0 },
+ { "SE_CNT_MISMATCH_1", 26, 1 },
+ { "SE_CNT_MISMATCH_0", 25, 1 },
+ { "ENABLE_CTX_1", 24, 1 },
+ { "ENABLE_CTX_0", 23, 1 },
+ { "ENABLE_FF", 22, 1 },
+ { "ENABLE_APF_1", 21, 1 },
+ { "ENABLE_APF_0", 20, 1 },
+ { "ENABLE_AF_1", 19, 1 },
+ { "ENABLE_AF_0", 18, 1 },
+ { "ENABLE_DDPDF_1", 17, 1 },
+ { "ENABLE_DDPMF_1", 16, 1 },
+ { "ENABLE_MEMRF_1", 15, 1 },
+ { "ENABLE_PRSDF_1", 14, 1 },
+ { "ENABLE_DDPDF_0", 13, 1 },
+ { "ENABLE_DDPMF_0", 12, 1 },
+ { "ENABLE_MEMRF_0", 11, 1 },
+ { "ENABLE_PRSDF_0", 10, 1 },
+ { "ENABLE_PCMDF_1", 9, 1 },
+ { "ENABLE_TPTCF_1", 8, 1 },
+ { "ENABLE_DDPCF_1", 7, 1 },
+ { "ENABLE_MPARF_1", 6, 1 },
+ { "ENABLE_MPARC_1", 5, 1 },
+ { "ENABLE_PCMDF_0", 4, 1 },
+ { "ENABLE_TPTCF_0", 3, 1 },
+ { "ENABLE_DDPCF_0", 2, 1 },
+ { "ENABLE_MPARF_0", 1, 1 },
+ { "ENABLE_MPARC_0", 0, 1 },
+ { "ULP_RX_INT_CAUSE", 0x19158, 0 },
+ { "SE_CNT_MISMATCH_1", 26, 1 },
+ { "SE_CNT_MISMATCH_0", 25, 1 },
+ { "CAUSE_CTX_1", 24, 1 },
+ { "CAUSE_CTX_0", 23, 1 },
+ { "CAUSE_FF", 22, 1 },
+ { "CAUSE_APF_1", 21, 1 },
+ { "CAUSE_APF_0", 20, 1 },
+ { "CAUSE_AF_1", 19, 1 },
+ { "CAUSE_AF_0", 18, 1 },
+ { "CAUSE_DDPDF_1", 17, 1 },
+ { "CAUSE_DDPMF_1", 16, 1 },
+ { "CAUSE_MEMRF_1", 15, 1 },
+ { "CAUSE_PRSDF_1", 14, 1 },
+ { "CAUSE_DDPDF_0", 13, 1 },
+ { "CAUSE_DDPMF_0", 12, 1 },
+ { "CAUSE_MEMRF_0", 11, 1 },
+ { "CAUSE_PRSDF_0", 10, 1 },
+ { "CAUSE_PCMDF_1", 9, 1 },
+ { "CAUSE_TPTCF_1", 8, 1 },
+ { "CAUSE_DDPCF_1", 7, 1 },
+ { "CAUSE_MPARF_1", 6, 1 },
+ { "CAUSE_MPARC_1", 5, 1 },
+ { "CAUSE_PCMDF_0", 4, 1 },
+ { "CAUSE_TPTCF_0", 3, 1 },
+ { "CAUSE_DDPCF_0", 2, 1 },
+ { "CAUSE_MPARF_0", 1, 1 },
+ { "CAUSE_MPARC_0", 0, 1 },
+ { "ULP_RX_ISCSI_LLIMIT", 0x1915c, 0 },
+ { "IscsiLlimit", 6, 26 },
+ { "ULP_RX_ISCSI_ULIMIT", 0x19160, 0 },
+ { "IscsiUlimit", 6, 26 },
+ { "ULP_RX_ISCSI_TAGMASK", 0x19164, 0 },
+ { "IscsiTagMask", 6, 26 },
+ { "ULP_RX_ISCSI_PSZ", 0x19168, 0 },
+ { "Hpz3", 24, 4 },
+ { "Hpz2", 16, 4 },
+ { "Hpz1", 8, 4 },
+ { "Hpz0", 0, 4 },
+ { "ULP_RX_TDDP_LLIMIT", 0x1916c, 0 },
+ { "TddpLlimit", 6, 26 },
+ { "ULP_RX_TDDP_ULIMIT", 0x19170, 0 },
+ { "TddpUlimit", 6, 26 },
+ { "ULP_RX_TDDP_TAGMASK", 0x19174, 0 },
+ { "TddpTagMask", 6, 26 },
+ { "ULP_RX_TDDP_PSZ", 0x19178, 0 },
+ { "Hpz3", 24, 4 },
+ { "Hpz2", 16, 4 },
+ { "Hpz1", 8, 4 },
+ { "Hpz0", 0, 4 },
+ { "ULP_RX_STAG_LLIMIT", 0x1917c, 0 },
+ { "ULP_RX_STAG_ULIMIT", 0x19180, 0 },
+ { "ULP_RX_RQ_LLIMIT", 0x19184, 0 },
+ { "ULP_RX_RQ_ULIMIT", 0x19188, 0 },
+ { "ULP_RX_PBL_LLIMIT", 0x1918c, 0 },
+ { "ULP_RX_PBL_ULIMIT", 0x19190, 0 },
+ { "ULP_RX_CTX_BASE", 0x19194, 0 },
+ { "ULP_RX_PERR_ENABLE", 0x1919c, 0 },
+ { "PERR_SE_CNT_MISMATCH_1", 26, 1 },
+ { "PERR_SE_CNT_MISMATCH_0", 25, 1 },
+ { "PERR_RSVD0", 24, 1 },
+ { "PERR_RSVD1", 23, 1 },
+ { "PERR_ENABLE_FF", 22, 1 },
+ { "PERR_ENABLE_APF_1", 21, 1 },
+ { "PERR_ENABLE_APF_0", 20, 1 },
+ { "PERR_ENABLE_AF_1", 19, 1 },
+ { "PERR_ENABLE_AF_0", 18, 1 },
+ { "PERR_ENABLE_DDPDF_1", 17, 1 },
+ { "PERR_ENABLE_DDPMF_1", 16, 1 },
+ { "PERR_ENABLE_MEMRF_1", 15, 1 },
+ { "PERR_ENABLE_PRSDF_1", 14, 1 },
+ { "PERR_ENABLE_DDPDF_0", 13, 1 },
+ { "PERR_ENABLE_DDPMF_0", 12, 1 },
+ { "PERR_ENABLE_MEMRF_0", 11, 1 },
+ { "PERR_ENABLE_PRSDF_0", 10, 1 },
+ { "PERR_ENABLE_PCMDF_1", 9, 1 },
+ { "PERR_ENABLE_TPTCF_1", 8, 1 },
+ { "PERR_ENABLE_DDPCF_1", 7, 1 },
+ { "PERR_ENABLE_MPARF_1", 6, 1 },
+ { "PERR_ENABLE_MPARC_1", 5, 1 },
+ { "PERR_ENABLE_PCMDF_0", 4, 1 },
+ { "PERR_ENABLE_TPTCF_0", 3, 1 },
+ { "PERR_ENABLE_DDPCF_0", 2, 1 },
+ { "PERR_ENABLE_MPARF_0", 1, 1 },
+ { "PERR_ENABLE_MPARC_0", 0, 1 },
+ { "ULP_RX_PERR_INJECT", 0x191a0, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "ULP_RX_RQUDP_LLIMIT", 0x191a4, 0 },
+ { "ULP_RX_RQUDP_ULIMIT", 0x191a8, 0 },
+ { "ULP_RX_CTX_ACC_CH0", 0x191ac, 0 },
+ { "REQ", 21, 1 },
+ { "WB", 20, 1 },
+ { "TID", 0, 20 },
+ { "ULP_RX_CTX_ACC_CH1", 0x191b0, 0 },
+ { "REQ", 21, 1 },
+ { "WB", 20, 1 },
+ { "TID", 0, 20 },
+ { "ULP_RX_SE_CNT_ERR", 0x191d0, 0 },
+ { "ERR_CH1", 4, 4 },
+ { "ERR_CH0", 0, 4 },
+ { "ULP_RX_SE_CNT_CLR", 0x191d4, 0 },
+ { "CLR_CH0", 4, 4 },
+ { "CLR_CH1", 0, 4 },
+ { "ULP_RX_SE_CNT_CH0", 0x191d8, 0 },
+ { "SOP_CNT_OUT0", 28, 4 },
+ { "EOP_CNT_OUT0", 24, 4 },
+ { "SOP_CNT_AL0", 20, 4 },
+ { "EOP_CNT_AL0", 16, 4 },
+ { "SOP_CNT_MR0", 12, 4 },
+ { "EOP_CNT_MR0", 8, 4 },
+ { "SOP_CNT_IN0", 4, 4 },
+ { "EOP_CNT_IN0", 0, 4 },
+ { "ULP_RX_SE_CNT_CH1", 0x191dc, 0 },
+ { "SOP_CNT_OUT1", 28, 4 },
+ { "EOP_CNT_OUT1", 24, 4 },
+ { "SOP_CNT_AL1", 20, 4 },
+ { "EOP_CNT_AL1", 16, 4 },
+ { "SOP_CNT_MR1", 12, 4 },
+ { "EOP_CNT_MR1", 8, 4 },
+ { "SOP_CNT_IN1", 4, 4 },
+ { "EOP_CNT_IN1", 0, 4 },
+ { "ULP_RX_DBG_CTL", 0x191e0, 0 },
+ { "EN_DBG_H", 17, 1 },
+ { "EN_DBG_L", 16, 1 },
+ { "SEL_H", 8, 8 },
+ { "SEL_L", 0, 8 },
+ { "ULP_RX_DBG_DATAH", 0x191e4, 0 },
+ { "ULP_RX_DBG_DATAL", 0x191e8, 0 },
+ { "ULP_RX_LA_CHNL", 0x19238, 0 },
+ { "ULP_RX_LA_CTL", 0x1923c, 0 },
+ { "ULP_RX_LA_RDPTR", 0x19240, 0 },
+ { "ULP_RX_LA_RDDATA", 0x19244, 0 },
+ { "ULP_RX_LA_WRPTR", 0x19248, 0 },
+ { "ULP_RX_LA_RESERVED", 0x1924c, 0 },
+ { "ULP_RX_CQE_GEN_EN", 0x19250, 0 },
+ { "Termimate_msg", 1, 1 },
+ { "Terminate_with_err", 0, 1 },
+ { "ULP_RX_ATOMIC_OPCODES", 0x19254, 0 },
+ { "atomic_req_qno", 22, 2 },
+ { "atomic_rsp_qno", 20, 2 },
+ { "immediate_qno", 18, 2 },
+ { "immediate_with_se_qno", 16, 2 },
+ { "atomic_wr_opcode", 12, 4 },
+ { "atomic_rd_opcode", 8, 4 },
+ { "immediate_opcode", 4, 4 },
+ { "immediate_with_se_opcode", 0, 4 },
+ { "ULP_RX_T10_CRC_ENDIAN_SWITCHING", 0x19258, 0 },
+ { "ULP_RX_MISC_FEATURE_ENABLE", 0x1925c, 0 },
+ { "terminate_status_en", 4, 1 },
+ { "multiple_pref_enable", 3, 1 },
+ { "umudp_pbl_pref_enable", 2, 1 },
+ { "rdma_pbl_pref_en", 1, 1 },
+ { "sdc_crc_prot_en", 0, 1 },
+ { "ULP_RX_CH0_CGEN", 0x19260, 0 },
+ { "BYPASS_CGEN", 7, 1 },
+ { "TDDP_CGEN", 6, 1 },
+ { "ISCSI_CGEN", 5, 1 },
+ { "RDMA_CGEN", 4, 1 },
+ { "CHANNEL_CGEN", 3, 1 },
+ { "All_DataPath_CGEN", 2, 1 },
+ { "T10Diff_DataPath_CGEN", 1, 1 },
+ { "Rdma_DataPath_CGEN", 0, 1 },
+ { "ULP_RX_CH1_CGEN", 0x19264, 0 },
+ { "BYPASS_CGEN", 7, 1 },
+ { "TDDP_CGEN", 6, 1 },
+ { "ISCSI_CGEN", 5, 1 },
+ { "RDMA_CGEN", 4, 1 },
+ { "CHANNEL_CGEN", 3, 1 },
+ { "All_DataPath_CGEN", 2, 1 },
+ { "T10Diff_DataPath_CGEN", 1, 1 },
+ { "Rdma_DataPath_CGEN", 0, 1 },
+ { "ULP_RX_RFE_DISABLE", 0x19268, 0 },
+ { "ULP_RX_INT_ENABLE_2", 0x1926c, 0 },
+ { "ULPRX2MA_IntfPerr", 8, 1 },
+ { "ALN_SDC_ERR_1", 7, 1 },
+ { "ALN_SDC_ERR_0", 6, 1 },
+ { "PF_UNTAGGED_TPT_1", 5, 1 },
+ { "PF_UNTAGGED_TPT_0", 4, 1 },
+ { "PF_PBL_1", 3, 1 },
+ { "PF_PBL_0", 2, 1 },
+ { "DDP_HINT_1", 1, 1 },
+ { "DDP_HINT_0", 0, 1 },
+ { "ULP_RX_INT_CAUSE_2", 0x19270, 0 },
+ { "ULPRX2MA_IntfPerr", 8, 1 },
+ { "ALN_SDC_ERR_1", 7, 1 },
+ { "ALN_SDC_ERR_0", 6, 1 },
+ { "PF_UNTAGGED_TPT_1", 5, 1 },
+ { "PF_UNTAGGED_TPT_0", 4, 1 },
+ { "PF_PBL_1", 3, 1 },
+ { "PF_PBL_0", 2, 1 },
+ { "DDP_HINT_1", 1, 1 },
+ { "DDP_HINT_0", 0, 1 },
+ { "ULP_RX_PERR_ENABLE_2", 0x19274, 0 },
+ { "ENABLE_ULPRX2MA_IntfPerr", 8, 1 },
+ { "ENABLE_ALN_SDC_ERR_1", 7, 1 },
+ { "ENABLE_ALN_SDC_ERR_0", 6, 1 },
+ { "ENABLE_PF_UNTAGGED_TPT_1", 5, 1 },
+ { "ENABLE_PF_UNTAGGED_TPT_0", 4, 1 },
+ { "ENABLE_PF_PBL_1", 3, 1 },
+ { "ENABLE_PF_PBL_0", 2, 1 },
+ { "ENABLE_DDP_HINT_1", 1, 1 },
+ { "ENABLE_DDP_HINT_0", 0, 1 },
+ { "ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT", 0x19278, 0 },
+ { "ULP_RX_ATOMIC_LEN", 0x1927c, 0 },
+ { "atomic_rpl_len", 16, 8 },
+ { "atomic_req_len", 8, 8 },
+ { "atomic_immediate_len", 0, 8 },
+ { "ULP_RX_CGEN_GLOBAL", 0x19280, 0 },
+ { "ULP_RX_CTX_SKIP_MA_REQ", 0x19284, 0 },
+ { "clear_ctx_err_cnt1", 3, 1 },
+ { "clear_ctx_err_cnt0", 2, 1 },
+ { "skip_ma_req_en1", 1, 1 },
+ { "skip_ma_req_en0", 0, 1 },
+ { "ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID", 0x19288, 0 },
+ { "ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID", 0x1928c, 0 },
+ { "ULP_RX_MSN_CHECK_ENABLE", 0x19290, 0 },
+ { "Rd_or_Term_msn_check_enable", 2, 1 },
+ { "atomic_op_msn_check_enable", 1, 1 },
+ { "send_msn_check_enable", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t5_sf_regs[] = {
+ { "SF_DATA", 0x193f8, 0 },
+ { "SF_OP", 0x193fc, 0 },
+ { "Busy", 31, 1 },
+ { "Lock", 4, 1 },
+ { "Cont", 3, 1 },
+ { "ByteCnt", 1, 2 },
+ { "Op", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t5_pl_regs[] = {
+ { "PL_PF_INT_CAUSE", 0x1e3c0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1e3c4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1e3c8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1e7c0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1e7c4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1e7c8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1ebc0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1ebc4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1ebc8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1efc0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1efc4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1efc8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1f3c0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1f3c4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1f3c8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1f7c0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1f7c4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1f7c8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1fbc0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1fbc4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1fbc8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1ffc0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1ffc4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1ffc8, 0 },
+ { "PL_WHOAMI", 0x19400, 0 },
+ { "PortxMap", 24, 3 },
+ { "SourceBus", 16, 2 },
+ { "SourcePF", 8, 3 },
+ { "IsVF", 7, 1 },
+ { "VFID", 0, 7 },
+ { "PL_PERR_CAUSE", 0x19404, 0 },
+ { "MC1", 31, 1 },
+ { "UART", 28, 1 },
+ { "ULP_TX", 27, 1 },
+ { "SGE", 26, 1 },
+ { "HMA", 25, 1 },
+ { "CPL_SWITCH", 24, 1 },
+ { "ULP_RX", 23, 1 },
+ { "PM_RX", 22, 1 },
+ { "PM_TX", 21, 1 },
+ { "MA", 20, 1 },
+ { "TP", 19, 1 },
+ { "LE", 18, 1 },
+ { "EDC1", 17, 1 },
+ { "EDC0", 16, 1 },
+ { "MC0", 15, 1 },
+ { "PCIE", 14, 1 },
+ { "PMU", 13, 1 },
+ { "MAC", 9, 1 },
+ { "SMB", 8, 1 },
+ { "SF", 7, 1 },
+ { "PL", 6, 1 },
+ { "NCSI", 5, 1 },
+ { "MPS", 4, 1 },
+ { "MI", 3, 1 },
+ { "DBG", 2, 1 },
+ { "I2CM", 1, 1 },
+ { "CIM", 0, 1 },
+ { "PL_PERR_ENABLE", 0x19408, 0 },
+ { "MC1", 31, 1 },
+ { "UART", 28, 1 },
+ { "ULP_TX", 27, 1 },
+ { "SGE", 26, 1 },
+ { "HMA", 25, 1 },
+ { "CPL_SWITCH", 24, 1 },
+ { "ULP_RX", 23, 1 },
+ { "PM_RX", 22, 1 },
+ { "PM_TX", 21, 1 },
+ { "MA", 20, 1 },
+ { "TP", 19, 1 },
+ { "LE", 18, 1 },
+ { "EDC1", 17, 1 },
+ { "EDC0", 16, 1 },
+ { "MC0", 15, 1 },
+ { "PCIE", 14, 1 },
+ { "PMU", 13, 1 },
+ { "MAC", 9, 1 },
+ { "SMB", 8, 1 },
+ { "SF", 7, 1 },
+ { "PL", 6, 1 },
+ { "NCSI", 5, 1 },
+ { "MPS", 4, 1 },
+ { "MI", 3, 1 },
+ { "DBG", 2, 1 },
+ { "I2CM", 1, 1 },
+ { "CIM", 0, 1 },
+ { "PL_INT_CAUSE", 0x1940c, 0 },
+ { "MC1", 31, 1 },
+ { "FLR", 30, 1 },
+ { "SW_CIM", 29, 1 },
+ { "UART", 28, 1 },
+ { "ULP_TX", 27, 1 },
+ { "SGE", 26, 1 },
+ { "HMA", 25, 1 },
+ { "CPL_SWITCH", 24, 1 },
+ { "ULP_RX", 23, 1 },
+ { "PM_RX", 22, 1 },
+ { "PM_TX", 21, 1 },
+ { "MA", 20, 1 },
+ { "TP", 19, 1 },
+ { "LE", 18, 1 },
+ { "EDC1", 17, 1 },
+ { "EDC0", 16, 1 },
+ { "MC0", 15, 1 },
+ { "PCIE", 14, 1 },
+ { "PMU", 13, 1 },
+ { "MAC3", 12, 1 },
+ { "MAC2", 11, 1 },
+ { "MAC1", 10, 1 },
+ { "MAC0", 9, 1 },
+ { "SMB", 8, 1 },
+ { "SF", 7, 1 },
+ { "PL", 6, 1 },
+ { "NCSI", 5, 1 },
+ { "MPS", 4, 1 },
+ { "MI", 3, 1 },
+ { "DBG", 2, 1 },
+ { "I2CM", 1, 1 },
+ { "CIM", 0, 1 },
+ { "PL_INT_ENABLE", 0x19410, 0 },
+ { "MC1", 31, 1 },
+ { "FLR", 30, 1 },
+ { "SW_CIM", 29, 1 },
+ { "UART", 28, 1 },
+ { "ULP_TX", 27, 1 },
+ { "SGE", 26, 1 },
+ { "HMA", 25, 1 },
+ { "CPL_SWITCH", 24, 1 },
+ { "ULP_RX", 23, 1 },
+ { "PM_RX", 22, 1 },
+ { "PM_TX", 21, 1 },
+ { "MA", 20, 1 },
+ { "TP", 19, 1 },
+ { "LE", 18, 1 },
+ { "EDC1", 17, 1 },
+ { "EDC0", 16, 1 },
+ { "MC0", 15, 1 },
+ { "PCIE", 14, 1 },
+ { "PMU", 13, 1 },
+ { "MAC3", 12, 1 },
+ { "MAC2", 11, 1 },
+ { "MAC1", 10, 1 },
+ { "MAC0", 9, 1 },
+ { "SMB", 8, 1 },
+ { "SF", 7, 1 },
+ { "PL", 6, 1 },
+ { "NCSI", 5, 1 },
+ { "MPS", 4, 1 },
+ { "MI", 3, 1 },
+ { "DBG", 2, 1 },
+ { "I2CM", 1, 1 },
+ { "CIM", 0, 1 },
+ { "PL_INT_MAP0", 0x19414, 0 },
+ { "MapNCSI", 16, 9 },
+ { "MapDefault", 0, 9 },
+ { "PL_INT_MAP1", 0x19418, 0 },
+ { "MapMAC1", 16, 9 },
+ { "MapMAC0", 0, 9 },
+ { "PL_INT_MAP2", 0x1941c, 0 },
+ { "MapMAC3", 16, 9 },
+ { "MapMAC2", 0, 9 },
+ { "PL_INT_MAP3", 0x19420, 0 },
+ { "MapMI", 16, 9 },
+ { "MapSMB", 0, 9 },
+ { "PL_INT_MAP4", 0x19424, 0 },
+ { "MapDBG", 16, 9 },
+ { "MapI2CM", 0, 9 },
+ { "PL_RST", 0x19428, 0 },
+ { "AutoPciePause", 4, 1 },
+ { "FatalPerrEn", 3, 1 },
+ { "SWIntCIM", 2, 1 },
+ { "PIORst", 1, 1 },
+ { "PIORstMode", 0, 1 },
+ { "PL_PL_INT_CAUSE", 0x19430, 0 },
+ { "PL_BusPerr", 6, 1 },
+ { "FatalPerr", 4, 1 },
+ { "InvalidAccess", 3, 1 },
+ { "Timeout", 2, 1 },
+ { "PLErr", 1, 1 },
+ { "PL_PL_INT_ENABLE", 0x19434, 0 },
+ { "PL_BusPerr", 6, 1 },
+ { "FatalPerr", 4, 1 },
+ { "InvalidAccess", 3, 1 },
+ { "Timeout", 2, 1 },
+ { "PLErr", 1, 1 },
+ { "PL_PL_PERR_ENABLE", 0x19438, 0 },
+ { "PL_BusPerr", 6, 1 },
+ { "PL_REV", 0x1943c, 0 },
+ { "ChipID", 4, 4 },
+ { "Rev", 0, 4 },
+ { "PL_PCIE_LINK", 0x19440, 0 },
+ { "LN0_AESTAT", 26, 3 },
+ { "LN0_AECMD", 23, 3 },
+ { "StateCfgInitF", 16, 7 },
+ { "StateCfgInit", 12, 4 },
+ { "SPEED", 8, 2 },
+ { "PERstTimeout", 7, 1 },
+ { "LTSSMEnable", 6, 1 },
+ { "LTSSM", 0, 6 },
+ { "PL_PCIE_CTL_STAT", 0x19444, 0 },
+ { "Status", 16, 16 },
+ { "Control", 0, 16 },
+ { "PL_SEMAPHORE_CTL", 0x1944c, 0 },
+ { "LockStatus", 16, 8 },
+ { "OwnerOverride", 8, 1 },
+ { "EnablePF", 0, 8 },
+ { "PL_SEMAPHORE_LOCK", 0x19450, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x19454, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x19458, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x1945c, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x19460, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x19464, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x19468, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x1946c, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_PORTX_MAP", 0x19474, 0 },
+ { "MAP7", 28, 3 },
+ { "MAP6", 24, 3 },
+ { "MAP5", 20, 3 },
+ { "MAP4", 16, 3 },
+ { "MAP3", 12, 3 },
+ { "MAP2", 8, 3 },
+ { "MAP1", 4, 3 },
+ { "MAP0", 0, 3 },
+ { "PL_VF_SLICE_L", 0x19490, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x19498, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194a0, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194a8, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194b0, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194b8, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194c0, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194c8, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_H", 0x19494, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x1949c, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194a4, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194ac, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194b4, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194bc, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194c4, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194cc, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_TIMEOUT_CTL", 0x194f0, 0 },
+ { "PerrCapture", 16, 1 },
+ { "Timeout", 0, 16 },
+ { "PL_TIMEOUT_STATUS0", 0x194f4, 0 },
+ { "Addr", 2, 28 },
+ { "PL_TIMEOUT_STATUS1", 0x194f8, 0 },
+ { "Valid", 31, 1 },
+ { "ValidPerr", 30, 1 },
+ { "Write", 22, 1 },
+ { "Bus", 20, 2 },
+ { "PF", 16, 3 },
+ { "VFID", 0, 8 },
+ { NULL }
+};
+
+struct reg_info t5_le_regs[] = {
+ { "LE_BUF_CONFIG", 0x19c00, 0 },
+ { "LE_DB_CONFIG", 0x19c04, 0 },
+ { "MASKCMDOLAPDIS", 26, 1 },
+ { "IPv4HASHSIZEEN", 25, 1 },
+ { "PROTOCOLMASKEN", 24, 1 },
+ { "TUPLESIZEEN", 23, 1 },
+ { "SRVRSRAMEN", 22, 1 },
+ { "TCAMCMDOVLAPEN", 21, 1 },
+ { "HASHEN", 20, 1 },
+ { "ASBOTHSRCHENPR", 19, 1 },
+ { "ASBOTHSRCHEN", 18, 1 },
+ { "ASLIPCOMPEN", 17, 1 },
+ { "BUILD", 16, 1 },
+ { "POCLIPTID0", 15, 1 },
+ { "TCAMARBOFF", 14, 1 },
+ { "ACCNTFULLEN", 13, 1 },
+ { "FilterRWnoCLIP", 12, 1 },
+ { "FilterEn", 11, 1 },
+ { "CRCHASH", 10, 1 },
+ { "COMPTID", 9, 1 },
+ { "SYNMode", 7, 2 },
+ { "SINGLETHREAD", 6, 1 },
+ { "LEBUSEN", 5, 1 },
+ { "ELOOKDUMEN", 4, 1 },
+ { "IPv4ONLYEN", 3, 1 },
+ { "MOSTCMDOEN", 2, 1 },
+ { "DELACTSYNOEN", 1, 1 },
+ { "CMDOVERLAPDIS", 0, 1 },
+ { "LE_MISC", 0x19c08, 0 },
+ { "SRAMDEEPSLEEP_STAT", 11, 1 },
+ { "TCAMDEEPSLEEP1_STAT", 10, 1 },
+ { "TCAMDEEPSLEEP0_STAT", 9, 1 },
+ { "SRAMDEEPSLEEP", 8, 1 },
+ { "TCAMDEEPSLEEP1", 7, 1 },
+ { "TCAMDEEPSLEEP0", 6, 1 },
+ { "SRVRAMCLKOFF", 5, 1 },
+ { "HASHCLKOFF", 4, 1 },
+ { "CMPUNVAIL", 0, 4 },
+ { "LE_DB_ROUTING_TABLE_INDEX", 0x19c10, 0 },
+ { "RTINDX", 7, 6 },
+ { "LE_DB_FILTER_TABLE_INDEX", 0x19c14, 0 },
+ { "FTINDX", 7, 6 },
+ { "LE_DB_SERVER_INDEX", 0x19c18, 0 },
+ { "SRINDX", 7, 6 },
+ { "LE_DB_CLIP_TABLE_INDEX", 0x19c1c, 0 },
+ { "CLIPTINDX", 7, 6 },
+ { "LE_DB_ACT_CNT_IPV4", 0x19c20, 0 },
+ { "LE_DB_ACT_CNT_IPV6", 0x19c24, 0 },
+ { "LE_DB_ACT_CNT_IPV4_TCAM", 0x19c94, 0 },
+ { "LE_DB_ACT_CNT_IPV6_TCAM", 0x19c98, 0 },
+ { "LE_ACT_CNT_THRSH", 0x19c9c, 0 },
+ { "LE_DB_HASH_CONFIG", 0x19c28, 0 },
+ { "HASHTIDSIZE", 16, 6 },
+ { "HASHSIZE", 0, 6 },
+ { "LE_DB_HASH_TABLE_BASE", 0x19c2c, 0 },
+ { "LE_DB_HASH_TID_BASE", 0x19c30, 0 },
+ { "LE_DB_SIZE", 0x19c34, 0 },
+ { "LE_DB_INT_ENABLE", 0x19c38, 0 },
+ { "MsgSel", 27, 5 },
+ { "ActCntIPv6Tzero", 21, 1 },
+ { "ActCntIPv4Tzero", 20, 1 },
+ { "ActCntIPv6zero", 19, 1 },
+ { "ActCntIPv4zero", 18, 1 },
+ { "MARspParErr", 17, 1 },
+ { "ReqQParErr", 16, 1 },
+ { "UnknownCmd", 15, 1 },
+ { "VfParErr", 14, 1 },
+ { "DropFilterHit", 13, 1 },
+ { "FilterHit", 12, 1 },
+ { "SYNCookieOff", 11, 1 },
+ { "SYNCookieBad", 10, 1 },
+ { "SYNCookie", 9, 1 },
+ { "NFASrchFail", 8, 1 },
+ { "ActRgnFull", 7, 1 },
+ { "ParityErr", 6, 1 },
+ { "LIPMiss", 5, 1 },
+ { "LIP0", 4, 1 },
+ { "Miss", 3, 1 },
+ { "RoutingHit", 2, 1 },
+ { "ActiveHit", 1, 1 },
+ { "ServerHit", 0, 1 },
+ { "LE_DB_INT_CAUSE", 0x19c3c, 0 },
+ { "ActCntIPv6Tzero", 21, 1 },
+ { "ActCntIPv4Tzero", 20, 1 },
+ { "ActCntIPv6zero", 19, 1 },
+ { "ActCntIPv4zero", 18, 1 },
+ { "MARspParErr", 17, 1 },
+ { "ReqQParErr", 16, 1 },
+ { "UnknownCmd", 15, 1 },
+ { "VfParErr", 14, 1 },
+ { "DropFilterHit", 13, 1 },
+ { "FilterHit", 12, 1 },
+ { "SYNCookieOff", 11, 1 },
+ { "SYNCookieBad", 10, 1 },
+ { "SYNCookie", 9, 1 },
+ { "NFASrchFail", 8, 1 },
+ { "ActRgnFull", 7, 1 },
+ { "ParityErr", 6, 1 },
+ { "LIPMiss", 5, 1 },
+ { "LIP0", 4, 1 },
+ { "Miss", 3, 1 },
+ { "RoutingHit", 2, 1 },
+ { "ActiveHit", 1, 1 },
+ { "ServerHit", 0, 1 },
+ { "LE_DB_INT_TID", 0x19c40, 0 },
+ { "LE_DB_INT_PTID", 0x19c44, 0 },
+ { "LE_DB_INT_INDEX", 0x19c48, 0 },
+ { "LE_DB_INT_CMD", 0x19c4c, 0 },
+ { "LE_DB_MASK_IPV4", 0x19c50, 0 },
+ { "LE_DB_MASK_IPV4", 0x19c54, 0 },
+ { "LE_DB_MASK_IPV4", 0x19c58, 0 },
+ { "LE_DB_MASK_IPV4", 0x19c5c, 0 },
+ { "LE_DB_MASK_IPV4", 0x19c60, 0 },
+ { "LE_DB_MASK_IPV6", 0x19ca0, 0 },
+ { "LE_DB_MASK_IPV6", 0x19ca4, 0 },
+ { "LE_DB_MASK_IPV6", 0x19ca8, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cac, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cb0, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cb4, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cb8, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cbc, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cc0, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cc4, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cc8, 0 },
+ { "LE_DB_MASK_IPV6", 0x19ccc, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cd0, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cd4, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cd8, 0 },
+ { "LE_DB_MASK_IPV6", 0x19cdc, 0 },
+ { "LE_DB_MASK_IPV6", 0x19ce0, 0 },
+ { "LE_DB_REQ_RSP_CNT", 0x19ce4, 0 },
+ { "RspCnt", 16, 16 },
+ { "ReqCnt", 0, 16 },
+ { "LE_DB_DBGI_CONFIG", 0x19cf0, 0 },
+ { "DBGICMDPERR", 31, 1 },
+ { "DBGICMDRANGE", 22, 3 },
+ { "DBGICMDMSKTYPE", 21, 1 },
+ { "DBGICMDSEARCH", 20, 1 },
+ { "DBGICMDREAD", 19, 1 },
+ { "DBGICMDLEARN", 18, 1 },
+ { "DBGICMDERASE", 17, 1 },
+ { "DBGICMDIPv6", 16, 1 },
+ { "DBGICMDTYPE", 13, 3 },
+ { "DBGICMDACKERR", 12, 1 },
+ { "DBGICMDBUSY", 3, 1 },
+ { "DBGICMDSTRT", 2, 1 },
+ { "DBGICMDMODE", 0, 2 },
+ { "LE_DB_DBGI_REQ_TCAM_CMD", 0x19cf4, 0 },
+ { "DBGICMD", 20, 4 },
+ { "DBGITINDEX", 0, 20 },
+ { "LE_PERR_ENABLE", 0x19cf8, 0 },
+ { "MARspParErr", 17, 1 },
+ { "ReqQueue", 16, 1 },
+ { "VfParErr", 14, 1 },
+ { "TCAM", 6, 1 },
+ { "LE_SPARE", 0x19cfc, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d00, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d04, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d08, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d0c, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d10, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d14, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d18, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d1c, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d20, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d24, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d28, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d2c, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d30, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d34, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d38, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d3c, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d40, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d50, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d54, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d58, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d5c, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d60, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d64, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d68, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d6c, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d70, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d74, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d78, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d7c, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d80, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d84, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d88, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d8c, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d90, 0 },
+ { "LE_DB_DBGI_RSP_STATUS", 0x19d94, 0 },
+ { "DBGIRspIndex", 12, 20 },
+ { "DBGIRspMsg", 8, 4 },
+ { "DBGIRspMsgVld", 7, 1 },
+ { "DBGIRspMHit", 2, 1 },
+ { "DBGIRspHit", 1, 1 },
+ { "DBGIRspValid", 0, 1 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19da0, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19da4, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19da8, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dac, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19db0, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19db4, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19db8, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dbc, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dc0, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dc4, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dc8, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dcc, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dd0, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dd4, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dd8, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19ddc, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19de0, 0 },
+ { "LE_DB_DBGI_RSP_LAST_CMD", 0x19de4, 0 },
+ { "LastCmdB", 16, 11 },
+ { "LastCmdA", 0, 11 },
+ { "LE_DB_DROP_FILTER_ENTRY", 0x19de8, 0 },
+ { "DropFilterEn", 31, 1 },
+ { "DropFilterClear", 17, 1 },
+ { "DropFilterSet", 16, 1 },
+ { "DropFilterFIDX", 0, 13 },
+ { "LE_DB_PTID_SVRBASE", 0x19df0, 0 },
+ { "SVRBASE_ADDR", 2, 18 },
+ { "LE_DB_FTID_FLTRBASE", 0x19df4, 0 },
+ { "FLTRBASE_ADDR", 2, 18 },
+ { "LE_DB_TID_HASHBASE", 0x19df8, 0 },
+ { "HASHBASE_ADDR", 2, 20 },
+ { "LE_PERR_INJECT", 0x19dfc, 0 },
+ { "MemSel", 1, 3 },
+ { "InjectDataErr", 0, 1 },
+ { "LE_DB_ACTIVE_MASK_IPV4", 0x19e00, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV4", 0x19e04, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV4", 0x19e08, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV4", 0x19e0c, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV4", 0x19e10, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e50, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e54, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e58, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e5c, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e60, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e64, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e68, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e6c, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e70, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e74, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e78, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e7c, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e80, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e84, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e88, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e8c, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e90, 0 },
+ { "LE_HASH_MASK_GEN_IPV4", 0x19ea0, 0 },
+ { "LE_HASH_MASK_GEN_IPV4", 0x19ea4, 0 },
+ { "LE_HASH_MASK_GEN_IPV4", 0x19ea8, 0 },
+ { "LE_HASH_MASK_GEN_IPV4", 0x19eac, 0 },
+ { "LE_HASH_MASK_GEN_IPV4", 0x19eb0, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19eb4, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19eb8, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19ebc, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19ec0, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19ec4, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19ec8, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19ecc, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19ed0, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19ed4, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19ed8, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19edc, 0 },
+ { "LE_HASH_MASK_GEN_IPV6", 0x19ee0, 0 },
+ { "LE_HASH_MASK_CMP_IPV4", 0x19ee4, 0 },
+ { "LE_HASH_MASK_CMP_IPV4", 0x19ee8, 0 },
+ { "LE_HASH_MASK_CMP_IPV4", 0x19eec, 0 },
+ { "LE_HASH_MASK_CMP_IPV4", 0x19ef0, 0 },
+ { "LE_HASH_MASK_CMP_IPV4", 0x19ef4, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19ef8, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19efc, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19f00, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19f04, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19f08, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19f0c, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19f10, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19f14, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19f18, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19f1c, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19f20, 0 },
+ { "LE_HASH_MASK_CMP_IPV6", 0x19f24, 0 },
+ { "LE_SRVR_SRAM_INIT", 0x19f34, 0 },
+ { "SRVRSRAMBASE", 2, 20 },
+ { "SRVRINITBUSY", 1, 1 },
+ { "SRVRINIT", 0, 1 },
+ { "LE_SRVR_VF_SRCH_TABLE", 0x19f38, 0 },
+ { "RDWR", 21, 1 },
+ { "VFINDEX", 14, 7 },
+ { "SRCHHADDR", 7, 7 },
+ { "SRCHLADDR", 0, 7 },
+ { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f40, 0 },
+ { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f44, 0 },
+ { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f48, 0 },
+ { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f4c, 0 },
+ { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f50, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f90, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f94, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f98, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f9c, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa0, 0 },
+ { "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fa4, 0 },
+ { "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fa8, 0 },
+ { "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fac, 0 },
+ { "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fb0, 0 },
+ { "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fb4, 0 },
+ { "LE_HASH_COLLISION", 0x19fc4, 0 },
+ { "LE_GLOBAL_COLLISION", 0x19fc8, 0 },
+ { "LE_FULL_CNT_COLLISION", 0x19fcc, 0 },
+ { "LE_DEBUG_LA_CONFIG", 0x19fd0, 0 },
+ { "LE_REQ_DEBUG_LA_DATA", 0x19fd4, 0 },
+ { "LE_REQ_DEBUG_LA_WRPTR", 0x19fd8, 0 },
+ { "LE_RSP_DEBUG_LA_DATA", 0x19fdc, 0 },
+ { "LE_RSP_DEBUG_LA_WRPTR", 0x19fe0, 0 },
+ { "LE_DEBUG_LA_SEL_DATA", 0x19fe4, 0 },
+ { NULL }
+};
+
+struct reg_info t5_ncsi_regs[] = {
+ { "NCSI_PORT_CFGREG", 0x1a000, 0 },
+ { "WireEn", 28, 4 },
+ { "strp_crc", 24, 4 },
+ { "rx_halt", 22, 1 },
+ { "flush_rx_fifo", 21, 1 },
+ { "hw_arb_en", 20, 1 },
+ { "soft_pkg_sel", 19, 1 },
+ { "err_discard_en", 18, 1 },
+ { "max_pkt_size", 4, 14 },
+ { "rx_byte_swap", 3, 1 },
+ { "tx_byte_swap", 2, 1 },
+ { "NCSI_RST_CTRL", 0x1a004, 0 },
+ { "mac_ref_rst", 2, 1 },
+ { "mac_rx_rst", 1, 1 },
+ { "mac_tx_rst", 0, 1 },
+ { "NCSI_CH0_SADDR_LOW", 0x1a010, 0 },
+ { "NCSI_CH0_SADDR_HIGH", 0x1a014, 0 },
+ { "CHO_SADDR_EN", 31, 1 },
+ { "CH0_SADDR_HIGH", 0, 16 },
+ { "NCSI_CH1_SADDR_LOW", 0x1a018, 0 },
+ { "NCSI_CH1_SADDR_HIGH", 0x1a01c, 0 },
+ { "CH1_SADDR_EN", 31, 1 },
+ { "CH1_SADDR_HIGH", 0, 16 },
+ { "NCSI_CH2_SADDR_LOW", 0x1a020, 0 },
+ { "NCSI_CH2_SADDR_HIGH", 0x1a024, 0 },
+ { "CH2_SADDR_EN", 31, 1 },
+ { "CH2_SADDR_HIGH", 0, 16 },
+ { "NCSI_CH3_SADDR_LOW", 0x1a028, 0 },
+ { "NCSI_CH3_SADDR_HIGH", 0x1a02c, 0 },
+ { "CH3_SADDR_EN", 31, 1 },
+ { "CH3_SADDR_HIGH", 0, 16 },
+ { "NCSI_WORK_REQHDR_0", 0x1a030, 0 },
+ { "NCSI_WORK_REQHDR_1", 0x1a034, 0 },
+ { "NCSI_WORK_REQHDR_2", 0x1a038, 0 },
+ { "NCSI_WORK_REQHDR_3", 0x1a03c, 0 },
+ { "NCSI_MPS_HDR_LO", 0x1a040, 0 },
+ { "NCSI_MPS_HDR_HI", 0x1a044, 0 },
+ { "NCSI_CTL", 0x1a048, 0 },
+ { "STRIP_OVLAN", 3, 1 },
+ { "bmc_drop_non_bc", 2, 1 },
+ { "bmc_rx_fwd_all", 1, 1 },
+ { "FWD_BMC", 0, 1 },
+ { "NCSI_NCSI_ETYPE", 0x1a04c, 0 },
+ { "NCSI_RX_FIFO_CNT", 0x1a050, 0 },
+ { "NCSI_RX_ERR_CNT", 0x1a054, 0 },
+ { "NCSI_RX_OF_CNT", 0x1a058, 0 },
+ { "NCSI_RX_MS_CNT", 0x1a05c, 0 },
+ { "NCSI_RX_IE_CNT", 0x1a060, 0 },
+ { "NCSI_MPS_DEMUX_CNT", 0x1a064, 0 },
+ { "MPS2CIM_CNT", 16, 9 },
+ { "MPS2BMC_CNT", 0, 9 },
+ { "NCSI_CIM_DEMUX_CNT", 0x1a068, 0 },
+ { "CIM2MPS_CNT", 16, 9 },
+ { "CIM2BMC_CNT", 0, 9 },
+ { "NCSI_TX_FIFO_CNT", 0x1a06c, 0 },
+ { "NCSI_SE_CNT_CTL", 0x1a0b0, 0 },
+ { "NCSI_SE_CNT_MPS", 0x1a0b4, 0 },
+ { "NCSI_SE_CNT_CIM", 0x1a0b8, 0 },
+ { "NCSI_BUS_DEBUG", 0x1a0bc, 0 },
+ { "NCSI_LA_RDPTR", 0x1a0c0, 0 },
+ { "NCSI_LA_RDDATA", 0x1a0c4, 0 },
+ { "NCSI_LA_WRPTR", 0x1a0c8, 0 },
+ { "NCSI_LA_RESERVED", 0x1a0cc, 0 },
+ { "NCSI_LA_CTL", 0x1a0d0, 0 },
+ { "NCSI_INT_ENABLE", 0x1a0d4, 0 },
+ { "CIM_DM_prty_err", 8, 1 },
+ { "MPS_DM_prty_err", 7, 1 },
+ { "token", 6, 1 },
+ { "arb_done", 5, 1 },
+ { "arb_started", 4, 1 },
+ { "WOL", 3, 1 },
+ { "MACInt", 2, 1 },
+ { "TXFIFO_prty_err", 1, 1 },
+ { "RXFIFO_prty_err", 0, 1 },
+ { "NCSI_INT_CAUSE", 0x1a0d8, 0 },
+ { "CIM_DM_prty_err", 8, 1 },
+ { "MPS_DM_prty_err", 7, 1 },
+ { "token", 6, 1 },
+ { "arb_done", 5, 1 },
+ { "arb_started", 4, 1 },
+ { "WOL", 3, 1 },
+ { "MACInt", 2, 1 },
+ { "TXFIFO_prty_err", 1, 1 },
+ { "RXFIFO_prty_err", 0, 1 },
+ { "NCSI_STATUS", 0x1a0dc, 0 },
+ { "Master", 1, 1 },
+ { "arb_status", 0, 1 },
+ { "NCSI_PAUSE_CTRL", 0x1a0e0, 0 },
+ { "NCSI_PAUSE_TIMEOUT", 0x1a0e4, 0 },
+ { "NCSI_PAUSE_WM", 0x1a0ec, 0 },
+ { "PauseHWM", 16, 11 },
+ { "PauseLWM", 0, 11 },
+ { "NCSI_DEBUG", 0x1a0f0, 0 },
+ { "TxFIFO_empty", 4, 1 },
+ { "TxFIFO_full", 3, 1 },
+ { "PKG_ID", 0, 3 },
+ { "NCSI_PERR_INJECT", 0x1a0f4, 0 },
+ { "MemSel", 1, 1 },
+ { "InjectDataErr", 0, 1 },
+ { "NCSI_PERR_ENABLE", 0x1a0f8, 0 },
+ { "CIM_DM_prty_err", 8, 1 },
+ { "MPS_DM_prty_err", 7, 1 },
+ { "TXFIFO_prty_err", 1, 1 },
+ { "RXFIFO_prty_err", 0, 1 },
+ { "NCSI_MACB_NETWORK_CTRL", 0x1a100, 0 },
+ { "TxSndZeroPause", 12, 1 },
+ { "TxSndPause", 11, 1 },
+ { "TxStop", 10, 1 },
+ { "TxStart", 9, 1 },
+ { "BackPress", 8, 1 },
+ { "StatWrEn", 7, 1 },
+ { "IncrStat", 6, 1 },
+ { "ClearStat", 5, 1 },
+ { "EnMgmtPort", 4, 1 },
+ { "TxEn", 3, 1 },
+ { "RxEn", 2, 1 },
+ { "LoopLocal", 1, 1 },
+ { "LoopPHY", 0, 1 },
+ { "NCSI_MACB_NETWORK_CFG", 0x1a104, 0 },
+ { "PClkDiv128", 22, 1 },
+ { "CopyPause", 21, 1 },
+ { "NonStdPreOK", 20, 1 },
+ { "NoFCS", 19, 1 },
+ { "RxEnHalfDup", 18, 1 },
+ { "NoCopyFCS", 17, 1 },
+ { "LenChkEn", 16, 1 },
+ { "RxBufOffset", 14, 2 },
+ { "PauseEn", 13, 1 },
+ { "RetryTest", 12, 1 },
+ { "PClkDiv", 10, 2 },
+ { "ExtClass", 9, 1 },
+ { "En1536Frame", 8, 1 },
+ { "UCastHashEn", 7, 1 },
+ { "MCastHashEn", 6, 1 },
+ { "RxBCastDis", 5, 1 },
+ { "CopyAllFrames", 4, 1 },
+ { "JumboEn", 3, 1 },
+ { "SerEn", 2, 1 },
+ { "FullDuplex", 1, 1 },
+ { "Speed", 0, 1 },
+ { "NCSI_MACB_NETWORK_STATUS", 0x1a108, 0 },
+ { "PHYMgmtStatus", 2, 1 },
+ { "MDIStatus", 1, 1 },
+ { "LinkStatus", 0, 1 },
+ { "NCSI_MACB_TX_STATUS", 0x1a114, 0 },
+ { "UnderrunErr", 6, 1 },
+ { "TxComplete", 5, 1 },
+ { "BufferExhausted", 4, 1 },
+ { "TxProgress", 3, 1 },
+ { "RetryLimit", 2, 1 },
+ { "ColEvent", 1, 1 },
+ { "UsedBitRead", 0, 1 },
+ { "NCSI_MACB_RX_BUF_QPTR", 0x1a118, 0 },
+ { "RxBufQPtr", 2, 30 },
+ { "NCSI_MACB_TX_BUF_QPTR", 0x1a11c, 0 },
+ { "TxBufQPtr", 2, 30 },
+ { "NCSI_MACB_RX_STATUS", 0x1a120, 0 },
+ { "RxOverrunErr", 2, 1 },
+ { "FrameRcvd", 1, 1 },
+ { "NoRxBuf", 0, 1 },
+ { "NCSI_MACB_INT_STATUS", 0x1a124, 0 },
+ { "PauseTimeZero", 13, 1 },
+ { "PauseRcvd", 12, 1 },
+ { "HRespNotOK", 11, 1 },
+ { "RxOverrun", 10, 1 },
+ { "LinkChange", 9, 1 },
+ { "TxComplete", 7, 1 },
+ { "TxBufErr", 6, 1 },
+ { "RetryLimitErr", 5, 1 },
+ { "TxBufUnderrun", 4, 1 },
+ { "TxUsedBitRead", 3, 1 },
+ { "RxUsedBitRead", 2, 1 },
+ { "RxComplete", 1, 1 },
+ { "MgmtFrameSent", 0, 1 },
+ { "NCSI_MACB_INT_EN", 0x1a128, 0 },
+ { "PauseTimeZero", 13, 1 },
+ { "PauseRcvd", 12, 1 },
+ { "HRespNotOK", 11, 1 },
+ { "RxOverrun", 10, 1 },
+ { "LinkChange", 9, 1 },
+ { "TxComplete", 7, 1 },
+ { "TxBufErr", 6, 1 },
+ { "RetryLimitErr", 5, 1 },
+ { "TxBufUnderrun", 4, 1 },
+ { "TxUsedBitRead", 3, 1 },
+ { "RxUsedBitRead", 2, 1 },
+ { "RxComplete", 1, 1 },
+ { "MgmtFrameSent", 0, 1 },
+ { "NCSI_MACB_INT_DIS", 0x1a12c, 0 },
+ { "PauseTimeZero", 13, 1 },
+ { "PauseRcvd", 12, 1 },
+ { "HRespNotOK", 11, 1 },
+ { "RxOverrun", 10, 1 },
+ { "LinkChange", 9, 1 },
+ { "TxComplete", 7, 1 },
+ { "TxBufErr", 6, 1 },
+ { "RetryLimitErr", 5, 1 },
+ { "TxBufUnderrun", 4, 1 },
+ { "TxUsedBitRead", 3, 1 },
+ { "RxUsedBitRead", 2, 1 },
+ { "RxComplete", 1, 1 },
+ { "MgmtFrameSent", 0, 1 },
+ { "NCSI_MACB_INT_MASK", 0x1a130, 0 },
+ { "PauseTimeZero", 13, 1 },
+ { "PauseRcvd", 12, 1 },
+ { "HRespNotOK", 11, 1 },
+ { "RxOverrun", 10, 1 },
+ { "LinkChange", 9, 1 },
+ { "TxComplete", 7, 1 },
+ { "TxBufErr", 6, 1 },
+ { "RetryLimitErr", 5, 1 },
+ { "TxBufUnderrun", 4, 1 },
+ { "TxUsedBitRead", 3, 1 },
+ { "RxUsedBitRead", 2, 1 },
+ { "RxComplete", 1, 1 },
+ { "MgmtFrameSent", 0, 1 },
+ { "NCSI_MACB_PAUSE_TIME", 0x1a138, 0 },
+ { "NCSI_MACB_PAUSE_FRAMES_RCVD", 0x1a13c, 0 },
+ { "NCSI_MACB_TX_FRAMES_OK", 0x1a140, 0 },
+ { "NCSI_MACB_SINGLE_COL_FRAMES", 0x1a144, 0 },
+ { "NCSI_MACB_MUL_COL_FRAMES", 0x1a148, 0 },
+ { "NCSI_MACB_RX_FRAMES_OK", 0x1a14c, 0 },
+ { "NCSI_MACB_FCS_ERR", 0x1a150, 0 },
+ { "NCSI_MACB_ALIGN_ERR", 0x1a154, 0 },
+ { "NCSI_MACB_DEF_TX_FRAMES", 0x1a158, 0 },
+ { "NCSI_MACB_LATE_COL", 0x1a15c, 0 },
+ { "NCSI_MACB_EXCESSIVE_COL", 0x1a160, 0 },
+ { "NCSI_MACB_TX_UNDERRUN_ERR", 0x1a164, 0 },
+ { "NCSI_MACB_CARRIER_SENSE_ERR", 0x1a168, 0 },
+ { "NCSI_MACB_RX_RESOURCE_ERR", 0x1a16c, 0 },
+ { "NCSI_MACB_RX_OVERRUN_ERR", 0x1a170, 0 },
+ { "NCSI_MACB_RX_SYMBOL_ERR", 0x1a174, 0 },
+ { "NCSI_MACB_RX_OVERSIZE_FRAME", 0x1a178, 0 },
+ { "NCSI_MACB_RX_JABBER_ERR", 0x1a17c, 0 },
+ { "NCSI_MACB_RX_UNDERSIZE_FRAME", 0x1a180, 0 },
+ { "NCSI_MACB_SQE_TEST_ERR", 0x1a184, 0 },
+ { "NCSI_MACB_LENGTH_ERR", 0x1a188, 0 },
+ { "NCSI_MACB_TX_PAUSE_FRAMES", 0x1a18c, 0 },
+ { "NCSI_MACB_HASH_LOW", 0x1a190, 0 },
+ { "NCSI_MACB_HASH_HIGH", 0x1a194, 0 },
+ { "NCSI_MACB_SPECIFIC_1_LOW", 0x1a198, 0 },
+ { "NCSI_MACB_SPECIFIC_1_HIGH", 0x1a19c, 0 },
+ { "NCSI_MACB_SPECIFIC_2_LOW", 0x1a1a0, 0 },
+ { "NCSI_MACB_SPECIFIC_2_HIGH", 0x1a1a4, 0 },
+ { "NCSI_MACB_SPECIFIC_3_LOW", 0x1a1a8, 0 },
+ { "NCSI_MACB_SPECIFIC_3_HIGH", 0x1a1ac, 0 },
+ { "NCSI_MACB_SPECIFIC_4_LOW", 0x1a1b0, 0 },
+ { "NCSI_MACB_SPECIFIC_4_HIGH", 0x1a1b4, 0 },
+ { "NCSI_MACB_TYPE_ID", 0x1a1b8, 0 },
+ { "NCSI_MACB_TX_PAUSE_QUANTUM", 0x1a1bc, 0 },
+ { "NCSI_MACB_USER_IO", 0x1a1c0, 0 },
+ { "UserProgInput", 16, 16 },
+ { "UserProgOutput", 0, 16 },
+ { "NCSI_MACB_WOL_CFG", 0x1a1c4, 0 },
+ { "MCHashEn", 19, 1 },
+ { "Specific1En", 18, 1 },
+ { "ARPEn", 17, 1 },
+ { "MagicPktEn", 16, 1 },
+ { "ARPIPAddr", 0, 16 },
+ { "NCSI_MACB_REV_STATUS", 0x1a1fc, 0 },
+ { "PartRef", 16, 16 },
+ { "DesRev", 0, 16 },
+ { NULL }
+};
+
+struct reg_info t5_mac_regs[] = {
+ { "MAC_PORT_CFG", 0x30800, 0 },
+ { "MAC_Clk_Sel", 29, 3 },
+ { "SinkTx", 27, 1 },
+ { "SinkTxOnLinkDown", 26, 1 },
+ { "LoopNoFwd", 24, 1 },
+ { "Smux_Rx_Loop", 19, 1 },
+ { "Rx_Lane_Swap", 18, 1 },
+ { "Tx_Lane_Swap", 17, 1 },
+ { "Signal_Det", 14, 1 },
+ { "SmuxTxSel", 9, 1 },
+ { "SmuxRxSel", 8, 1 },
+ { "PortSpeed", 4, 2 },
+ { "Rx_Byte_Swap", 3, 1 },
+ { "Tx_Byte_Swap", 2, 1 },
+ { "Port_Sel", 0, 1 },
+ { "MAC_PORT_RESET_CTRL", 0x30804, 0 },
+ { "TWGDSK_HSSC16B", 31, 1 },
+ { "EEE_RESET", 30, 1 },
+ { "PTP_TIMER", 29, 1 },
+ { "MtipRefReset", 28, 1 },
+ { "MtipTxffReset", 27, 1 },
+ { "MtipRxffReset", 26, 1 },
+ { "MtipRegReset", 25, 1 },
+ { "AEC3Reset", 23, 1 },
+ { "AEC2Reset", 22, 1 },
+ { "AEC1Reset", 21, 1 },
+ { "AEC0Reset", 20, 1 },
+ { "AET3Reset", 19, 1 },
+ { "AET2Reset", 18, 1 },
+ { "AET1Reset", 17, 1 },
+ { "AET0Reset", 16, 1 },
+ { "TXIF_Reset", 12, 1 },
+ { "RXIF_Reset", 11, 1 },
+ { "AuxExt_Reset", 10, 1 },
+ { "MtipSd3TxRst", 9, 1 },
+ { "MtipSd2TxRst", 8, 1 },
+ { "MtipSd1TxRst", 7, 1 },
+ { "MtipSd0TxRst", 6, 1 },
+ { "MtipSd3RxRst", 5, 1 },
+ { "MtipSd2RxRst", 4, 1 },
+ { "MtipSd1RxRst", 3, 1 },
+ { "WOL_Reset", 2, 1 },
+ { "MtipSd0RxRst", 1, 1 },
+ { "HSS_Reset", 0, 1 },
+ { "MAC_PORT_LED_CFG", 0x30808, 0 },
+ { "Led1_Cfg", 5, 3 },
+ { "Led1_Polarity_Inv", 4, 1 },
+ { "Led0_Cfg", 1, 3 },
+ { "Led0_Polarity_Inv", 0, 1 },
+ { "MAC_PORT_LED_COUNTHI", 0x3080c, 0 },
+ { "MAC_PORT_LED_COUNTLO", 0x30810, 0 },
+ { "MAC_PORT_CFG3", 0x30814, 0 },
+ { "FPGA_PTP_PORT", 26, 2 },
+ { "FCSDisCtrl", 25, 1 },
+ { "SigDetCtrl", 24, 1 },
+ { "tx_lane", 23, 1 },
+ { "rx_lane", 22, 1 },
+ { "se_clr", 21, 1 },
+ { "an_ena", 17, 4 },
+ { "sd_rx_clk_ena", 13, 4 },
+ { "sd_tx_clk_ena", 9, 4 },
+ { "SGMIISEL", 8, 1 },
+ { "HSSPLLSEL", 4, 4 },
+ { "HSSC16C20SEL", 0, 4 },
+ { "MAC_PORT_CFG2", 0x30818, 0 },
+ { "Rx_Polarity_Inv", 28, 4 },
+ { "Tx_Polarity_Inv", 24, 4 },
+ { "InstanceNum", 22, 2 },
+ { "StopOnPerr", 21, 1 },
+ { "PatEn", 18, 1 },
+ { "MagicEn", 17, 1 },
+ { "T5_AEC_PMA_TX_READY", 4, 4 },
+ { "T5_AEC_PMA_RX_READY", 0, 4 },
+ { "MAC_PORT_PKT_COUNT", 0x3081c, 0 },
+ { "tx_sop_count", 24, 8 },
+ { "tx_eop_count", 16, 8 },
+ { "rx_sop_count", 8, 8 },
+ { "rx_eop_count", 0, 8 },
+ { "MAC_PORT_CFG4", 0x30820, 0 },
+ { "AEC3_RX_WIDTH", 14, 2 },
+ { "AEC2_RX_WIDTH", 12, 2 },
+ { "AEC1_RX_WIDTH", 10, 2 },
+ { "AEC0_RX_WIDTH", 8, 2 },
+ { "AEC3_TX_WIDTH", 6, 2 },
+ { "AEC2_TX_WIDTH", 4, 2 },
+ { "AEC1_TX_WIDTH", 2, 2 },
+ { "AEC0_TX_WIDTH", 0, 2 },
+ { "MAC_PORT_MAGIC_MACID_LO", 0x30824, 0 },
+ { "MAC_PORT_MAGIC_MACID_HI", 0x30828, 0 },
+ { "MAC_PORT_LINK_STATUS", 0x30834, 0 },
+ { "an_done", 6, 1 },
+ { "align_done", 5, 1 },
+ { "block_lock", 4, 1 },
+ { "remflt", 3, 1 },
+ { "locflt", 2, 1 },
+ { "linkup", 1, 1 },
+ { "linkdn", 0, 1 },
+ { "MAC_PORT_EPIO_DATA0", 0x308c0, 0 },
+ { "MAC_PORT_EPIO_DATA1", 0x308c4, 0 },
+ { "MAC_PORT_EPIO_DATA2", 0x308c8, 0 },
+ { "MAC_PORT_EPIO_DATA3", 0x308cc, 0 },
+ { "MAC_PORT_EPIO_OP", 0x308d0, 0 },
+ { "Busy", 31, 1 },
+ { "Write", 8, 1 },
+ { "Address", 0, 8 },
+ { "MAC_PORT_WOL_STATUS", 0x308d4, 0 },
+ { "MagicDetected", 31, 1 },
+ { "PatDetected", 30, 1 },
+ { "ClearMagic", 4, 1 },
+ { "ClearMatch", 3, 1 },
+ { "MatchedFilter", 0, 3 },
+ { "MAC_PORT_INT_EN", 0x308d8, 0 },
+ { "tx_ts_avail", 29, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_INT_CAUSE", 0x308dc, 0 },
+ { "tx_ts_avail", 29, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_PERR_INT_EN", 0x308e0, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_INT_CAUSE", 0x308e4, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_ENABLE", 0x308e8, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_INJECT", 0x308ec, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "MAC_PORT_HSS_CFG0", 0x308f0, 0 },
+ { "TXDTS", 31, 1 },
+ { "TXCTS", 30, 1 },
+ { "TXBTS", 29, 1 },
+ { "TXATS", 28, 1 },
+ { "TXDOBS", 27, 1 },
+ { "TXCOBS", 26, 1 },
+ { "TXBOBS", 25, 1 },
+ { "TXAOBS", 24, 1 },
+ { "HSSREFCLKVALIDA", 20, 1 },
+ { "HSSREFCLKVALIDB", 19, 1 },
+ { "HSSRESYNCA", 18, 1 },
+ { "HSSAVDHI", 17, 1 },
+ { "HSSRESYNCB", 16, 1 },
+ { "HSSRECCALA", 15, 1 },
+ { "HSSRXACMODE", 14, 1 },
+ { "HSSRECCALB", 13, 1 },
+ { "HSSPLLBYPA", 12, 1 },
+ { "HSSPLLBYPB", 11, 1 },
+ { "HSSPDWNPLLA", 10, 1 },
+ { "HSSPDWNPLLB", 9, 1 },
+ { "HSSVCOSELA", 8, 1 },
+ { "HSSVCOSELB", 7, 1 },
+ { "HSSCALCOMP", 6, 1 },
+ { "HSSCALENAB", 5, 1 },
+ { "HSSEXTC16SEL", 4, 1 },
+ { "MAC_PORT_HSS_CFG1", 0x308f4, 0 },
+ { "RXACONFIGSEL", 30, 2 },
+ { "RXAQUIET", 29, 1 },
+ { "RXAREFRESH", 28, 1 },
+ { "RXBCONFIGSEL", 26, 2 },
+ { "RXBQUIET", 25, 1 },
+ { "RXBREFRESH", 24, 1 },
+ { "RXCCONFIGSEL", 22, 2 },
+ { "RXCQUIET", 21, 1 },
+ { "RXCREFRESH", 20, 1 },
+ { "RXDCONFIGSEL", 18, 2 },
+ { "RXDQUIET", 17, 1 },
+ { "RXDREFRESH", 16, 1 },
+ { "TXACONFIGSEL", 14, 2 },
+ { "TXAQUIET", 13, 1 },
+ { "TXAREFRESH", 12, 1 },
+ { "TXBCONFIGSEL", 10, 2 },
+ { "TXBQUIET", 9, 1 },
+ { "TXBREFRESH", 8, 1 },
+ { "TXCCONFIGSEL", 6, 2 },
+ { "TXCQUIET", 5, 1 },
+ { "TXCREFRESH", 4, 1 },
+ { "TXDCONFIGSEL", 2, 2 },
+ { "TXDQUIET", 1, 1 },
+ { "TXDREFRESH", 0, 1 },
+ { "MAC_PORT_HSS_CFG2", 0x308f8, 0 },
+ { "RXAASSTCLK", 31, 1 },
+ { "T5RXAPRBSRST", 30, 1 },
+ { "RXBASSTCLK", 29, 1 },
+ { "T5RXBPRBSRST", 28, 1 },
+ { "RXCASSTCLK", 27, 1 },
+ { "T5RXCPRBSRST", 26, 1 },
+ { "RXDASSTCLK", 25, 1 },
+ { "T5RXDPRBSRST", 24, 1 },
+ { "RXDDATASYNC", 23, 1 },
+ { "RXCDATASYNC", 22, 1 },
+ { "RXBDATASYNC", 21, 1 },
+ { "RXADATASYNC", 20, 1 },
+ { "RXDEARLYIN", 19, 1 },
+ { "RXDLATEIN", 18, 1 },
+ { "RXDPHSLOCK", 17, 1 },
+ { "RXDPHSDNIN", 16, 1 },
+ { "RXDPHSUPIN", 15, 1 },
+ { "RXCEARLYIN", 14, 1 },
+ { "RXCLATEIN", 13, 1 },
+ { "RXCPHSLOCK", 12, 1 },
+ { "RXCPHSDNIN", 11, 1 },
+ { "RXCPHSUPIN", 10, 1 },
+ { "RXBEARLYIN", 9, 1 },
+ { "RXBLATEIN", 8, 1 },
+ { "RXBPHSLOCK", 7, 1 },
+ { "RXBPHSDNIN", 6, 1 },
+ { "RXBPHSUPIN", 5, 1 },
+ { "RXAEARLYIN", 4, 1 },
+ { "RXALATEIN", 3, 1 },
+ { "RXAPHSLOCK", 2, 1 },
+ { "RXAPHSDNIN", 1, 1 },
+ { "RXAPHSUPIN", 0, 1 },
+ { "MAC_PORT_HSS_CFG3", 0x308fc, 0 },
+ { "HSSCALSSTN", 25, 3 },
+ { "HSSCALSSTP", 22, 3 },
+ { "HSSVBOOSTDIVB", 19, 3 },
+ { "HSSVBOOSTDIVA", 16, 3 },
+ { "HSSPLLCONFIGB", 8, 8 },
+ { "HSSPLLCONFIGA", 0, 8 },
+ { "MAC_PORT_HSS_CFG4", 0x30900, 0 },
+ { "HSSDIVSELA", 9, 9 },
+ { "HSSDIVSELB", 0, 9 },
+ { "MAC_PORT_HSS_STATUS", 0x30904, 0 },
+ { "RXDPRBSSYNC", 15, 1 },
+ { "RXCPRBSSYNC", 14, 1 },
+ { "RXBPRBSSYNC", 13, 1 },
+ { "RXAPRBSSYNC", 12, 1 },
+ { "RXDPRBSERR", 11, 1 },
+ { "RXCPRBSERR", 10, 1 },
+ { "RXBPRBSERR", 9, 1 },
+ { "RXAPRBSERR", 8, 1 },
+ { "RXDSIGDET", 7, 1 },
+ { "RXCSIGDET", 6, 1 },
+ { "RXBSIGDET", 5, 1 },
+ { "RXASIGDET", 4, 1 },
+ { "HSSPLLLOCKB", 3, 1 },
+ { "HSSPLLLOCKA", 2, 1 },
+ { "HSSPRTREADYB", 1, 1 },
+ { "HSSPRTREADYA", 0, 1 },
+ { "MAC_PORT_HSS_EEE_STATUS", 0x30908, 0 },
+ { "RXAQUIET_STATUS", 15, 1 },
+ { "RXAREFRESH_STATUS", 14, 1 },
+ { "RXBQUIET_STATUS", 13, 1 },
+ { "RXBREFRESH_STATUS", 12, 1 },
+ { "RXCQUIET_STATUS", 11, 1 },
+ { "RXCREFRESH_STATUS", 10, 1 },
+ { "RXDQUIET_STATUS", 9, 1 },
+ { "RXDREFRESH_STATUS", 8, 1 },
+ { "TXAQUIET_STATUS", 7, 1 },
+ { "TXAREFRESH_STATUS", 6, 1 },
+ { "TXBQUIET_STATUS", 5, 1 },
+ { "TXBREFRESH_STATUS", 4, 1 },
+ { "TXCQUIET_STATUS", 3, 1 },
+ { "TXCREFRESH_STATUS", 2, 1 },
+ { "TXDQUIET_STATUS", 1, 1 },
+ { "TXDREFRESH_STATUS", 0, 1 },
+ { "MAC_PORT_HSS_SIGDET_STATUS", 0x3090c, 0 },
+ { "MAC_PORT_HSS_PL_CTL", 0x30910, 0 },
+ { "TOV", 16, 8 },
+ { "TSU", 8, 8 },
+ { "IPW", 0, 8 },
+ { "MAC_PORT_RUNT_FRAME", 0x30914, 0 },
+ { "runtclear", 16, 1 },
+ { "runt", 0, 16 },
+ { "MAC_PORT_EEE_STATUS", 0x30918, 0 },
+ { "eee_tx_10g_state", 10, 2 },
+ { "eee_rx_10g_state", 8, 2 },
+ { "eee_tx_1g_state", 6, 2 },
+ { "eee_rx_1g_state", 4, 2 },
+ { "pma_rx_refresh", 3, 1 },
+ { "pma_rx_quiet", 2, 1 },
+ { "pma_tx_refresh", 1, 1 },
+ { "pma_tx_quiet", 0, 1 },
+ { "MAC_PORT_CGEN", 0x3091c, 0 },
+ { "CGEN", 8, 1 },
+ { "sd7_CGEN", 7, 1 },
+ { "sd6_CGEN", 6, 1 },
+ { "sd5_CGEN", 5, 1 },
+ { "sd4_CGEN", 4, 1 },
+ { "sd3_CGEN", 3, 1 },
+ { "sd2_CGEN", 2, 1 },
+ { "sd1_CGEN", 1, 1 },
+ { "sd0_CGEN", 0, 1 },
+ { "MAC_PORT_CGEN_MTIP", 0x30920, 0 },
+ { "MACSEG5_CGEN", 11, 1 },
+ { "PCSSEG5_CGEN", 10, 1 },
+ { "MACSEG4_CGEN", 9, 1 },
+ { "PCSSEG4_CGEN", 8, 1 },
+ { "MACSEG3_CGEN", 7, 1 },
+ { "PCSSEG3_CGEN", 6, 1 },
+ { "MACSEG2_CGEN", 5, 1 },
+ { "PCSSEG2_CGEN", 4, 1 },
+ { "MACSEG1_CGEN", 3, 1 },
+ { "PCSSEG1_CGEN", 2, 1 },
+ { "MACSEG0_CGEN", 1, 1 },
+ { "PCSSEG0_CGEN", 0, 1 },
+ { "MAC_PORT_TX_TS_ID", 0x30924, 0 },
+ { "MAC_PORT_TX_TS_VAL_LO", 0x30928, 0 },
+ { "MAC_PORT_TX_TS_VAL_HI", 0x3092c, 0 },
+ { "MAC_PORT_EEE_CTL", 0x30930, 0 },
+ { "EEE_CTRL", 2, 30 },
+ { "TICK_START", 1, 1 },
+ { "En", 0, 1 },
+ { "MAC_PORT_EEE_TX_CTL", 0x30934, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_ACTIVE", 3, 1 },
+ { "LPI_TXHOLD", 2, 1 },
+ { "LPI_REQ", 1, 1 },
+ { "EEE_TX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_RX_CTL", 0x30938, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_IND", 1, 1 },
+ { "EEE_RX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3093c, 0 },
+ { "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x30940, 0 },
+ { "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x30944, 0 },
+ { "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x30948, 0 },
+ { "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3094c, 0 },
+ { "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x30950, 0 },
+ { "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x30954, 0 },
+ { "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x30958, 0 },
+ { "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3095c, 0 },
+ { "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x30960, 0 },
+ { "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x30964, 0 },
+ { "MAC_PORT_EEE_WF_COUNT", 0x30968, 0 },
+ { "wake_cnt_clr", 16, 1 },
+ { "wake_cnt", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_RD0_LO", 0x3096c, 0 },
+ { "MAC_PORT_PTP_TIMER_RD0_HI", 0x30970, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_LO", 0x30974, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_HI", 0x30978, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_LO", 0x3097c, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_HI", 0x30980, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_0", 0x30984, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_1", 0x30988, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3098c, 0 },
+ { "MAC_PORT_PTP_SUM_LO", 0x30990, 0 },
+ { "MAC_PORT_PTP_SUM_HI", 0x30994, 0 },
+ { "MAC_PORT_PTP_TIMER_INCR0", 0x30998, 0 },
+ { "Y", 16, 16 },
+ { "X", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_INCR1", 0x3099c, 0 },
+ { "Y_TICK", 16, 16 },
+ { "X_TICK", 0, 16 },
+ { "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x309a0, 0 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x309a4, 0 },
+ { "B", 16, 16 },
+ { "A", 0, 16 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x309a8, 0 },
+ { "MAC_PORT_PTP_CFG", 0x309ac, 0 },
+ { "FRZ", 18, 1 },
+ { "OFFSER_ADJUST_SIGN", 17, 1 },
+ { "ADD_OFFSET", 16, 1 },
+ { "CYCLE1", 8, 8 },
+ { "Q", 0, 8 },
+ { "MAC_PORT_MTIP_REVISION", 0x30a00, 0 },
+ { "CUSTREV", 16, 16 },
+ { "VER", 8, 8 },
+ { "REV", 0, 8 },
+ { "MAC_PORT_MTIP_SCRATCH", 0x30a04, 0 },
+ { "MAC_PORT_MTIP_COMMAND_CONFIG", 0x30a08, 0 },
+ { "TX_FLUSH", 22, 1 },
+ { "RX_SFD_ANY", 21, 1 },
+ { "PAUSE_PFC_COMP", 20, 1 },
+ { "PFC_MODE", 19, 1 },
+ { "RS_COL_CNT_EXT", 18, 1 },
+ { "NO_LGTH_CHECK", 17, 1 },
+ { "SEND_IDLE", 16, 1 },
+ { "PHY_TXENA", 15, 1 },
+ { "RX_ERR_DISC", 14, 1 },
+ { "CMD_FRAME_ENA", 13, 1 },
+ { "SW_RESET", 12, 1 },
+ { "TX_PAD_EN", 11, 1 },
+ { "LOOPBACK_EN", 10, 1 },
+ { "TX_ADDR_INS", 9, 1 },
+ { "PAUSE_IGNORE", 8, 1 },
+ { "PAUSE_FWD", 7, 1 },
+ { "CRC_FWD", 6, 1 },
+ { "PAD_EN", 5, 1 },
+ { "PROMIS_EN", 4, 1 },
+ { "WAN_MODE", 3, 1 },
+ { "RX_ENA", 1, 1 },
+ { "TX_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_MAC_ADDR_0", 0x30a0c, 0 },
+ { "MAC_PORT_MTIP_MAC_ADDR_1", 0x30a10, 0 },
+ { "MAC_PORT_MTIP_FRM_LENGTH", 0x30a14, 0 },
+ { "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x30a1c, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x30a20, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x30a24, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x30a28, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x30a2c, 0 },
+ { "ENABLE", 8, 1 },
+ { "ADDR", 0, 6 },
+ { "MAC_PORT_MTIP_MAC_STATUS", 0x30a40, 0 },
+ { "TS_AVAIL", 3, 1 },
+ { "PHY_LOS", 2, 1 },
+ { "RX_REM_FAULT", 1, 1 },
+ { "RX_LOC_FAULT", 0, 1 },
+ { "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x30a44, 0 },
+ { "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x30a48, 0 },
+ { "MAC_PORT_MTIP_INIT_CREDIT", 0x30a4c, 0 },
+ { "MAC_PORT_MTIP_CURRENT_CREDIT", 0x30a50, 0 },
+ { "MAC_PORT_RX_PAUSE_STATUS", 0x30a74, 0 },
+ { "MAC_PORT_MTIP_TS_TIMESTAMP", 0x30a7c, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x30a80, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x30a84, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOK", 0x30a88, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x30a8c, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x30a90, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x30a94, 0 },
+ { "MAC_PORT_AALIGNMENTERRORS", 0x30a98, 0 },
+ { "MAC_PORT_AALIGNMENTERRORSHI", 0x30a9c, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x30aa0, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x30aa4, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x30aa8, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x30aac, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORS", 0x30ab0, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x30ab4, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORS", 0x30ab8, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORSHI", 0x30abc, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOK", 0x30ac0, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOKHI", 0x30ac4, 0 },
+ { "MAC_PORT_VLANRECEIVEDOK", 0x30ac8, 0 },
+ { "MAC_PORT_VLANRECEIVEDOKHI", 0x30acc, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x30ad0, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x30ad4, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOK", 0x30ad8, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x30adc, 0 },
+ { "MAC_PORT_IFINUCASTPKTS", 0x30ae0, 0 },
+ { "MAC_PORT_IFINUCASTPKTSHI", 0x30ae4, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTS", 0x30ae8, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTSHI", 0x30aec, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTS", 0x30af0, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTSHI", 0x30af4, 0 },
+ { "MAC_PORT_IFOUTERRORS", 0x30af8, 0 },
+ { "MAC_PORT_IFOUTERRORSHI", 0x30afc, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTS", 0x30b08, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTSHI", 0x30b0c, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTS", 0x30b10, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x30b14, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTS", 0x30b18, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x30b1c, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTS", 0x30b20, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x30b24, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETS", 0x30b28, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETSHI", 0x30b2c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS", 0x30b30, 0 },
+ { "MAC_PORT_ETHERSTATSPKTSHI", 0x30b34, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x30b38, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x30b3c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x30b40, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x30b44, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x30b48, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x30b4c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x30b50, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x30b54, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x30b58, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x30b5c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x30b60, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30b64, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x30b68, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30b6c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x30b70, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x30b74, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x30b78, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x30b7c, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERS", 0x30b80, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERSHI", 0x30b84, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTS", 0x30b88, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x30b8c, 0 },
+ { "MAC_PORT_IFINERRORS", 0x30b90, 0 },
+ { "MAC_PORT_IFINERRORSHI", 0x30b94, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x30b98, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x30b9c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x30ba0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x30ba4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x30ba8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x30bac, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x30bb0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x30bb4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x30bb8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x30bbc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x30bc0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x30bc4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x30bc8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x30bcc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x30bd0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x30bd4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x30bd8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x30bdc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x30be0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x30be4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x30be8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x30bec, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x30bf0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x30bf4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x30bf8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x30bfc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x30c00, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x30c04, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x30c08, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x30c0c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x30c10, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x30c14, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x30c18, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x30c1c, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x30c20, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x30c24, 0 },
+ { "MAC_PORT_MTIP_SGMII_CONTROL", 0x30d00, 0 },
+ { "Reset", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "sppedsel1", 13, 1 },
+ { "AN_EN", 12, 1 },
+ { "PWRDWN", 11, 1 },
+ { "Isolate", 10, 1 },
+ { "AN_RESTART", 9, 1 },
+ { "DPLX", 8, 1 },
+ { "CollisionTest", 7, 1 },
+ { "SpeedSel0", 6, 1 },
+ { "MAC_PORT_MTIP_SGMII_STATUS", 0x30d04, 0 },
+ { "100BaseT4", 15, 1 },
+ { "100BaseXFullDplx", 14, 1 },
+ { "100BaseXHalfDplx", 13, 1 },
+ { "10MbpsFullDplx", 12, 1 },
+ { "10MbpsHalfDplx", 11, 1 },
+ { "100BaseT2FullDplx", 10, 1 },
+ { "100BaseT2HalfDplx", 9, 1 },
+ { "ExtdStatus", 8, 1 },
+ { "AN_Complete", 5, 1 },
+ { "SGMII_REM_FAULT", 4, 1 },
+ { "AN_Ability", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "JabberDetect", 1, 1 },
+ { "ExtdCapability", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x30d08, 0 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x30d0c, 0 },
+ { "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x30d10, 0 },
+ { "NP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "RF2", 13, 1 },
+ { "RF1", 12, 1 },
+ { "PS2", 8, 1 },
+ { "PS1", 7, 1 },
+ { "HD", 6, 1 },
+ { "FD", 5, 1 },
+ { "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x30d14, 0 },
+ { "CuLinkStatus", 15, 1 },
+ { "ACK", 14, 1 },
+ { "CuDplxStatus", 12, 1 },
+ { "CuSpeed", 10, 2 },
+ { "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x30d18, 0 },
+ { "PgRcvd", 1, 1 },
+ { "RealTimePgRcvd", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x30d1c, 0 },
+ { "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x30d20, 0 },
+ { "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x30d3c, 0 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x30d48, 0 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x30d4c, 0 },
+ { "MAC_PORT_MTIP_SGMII_IF_MODE", 0x30d50, 0 },
+ { "SGMII_PCS_ENABLE", 5, 1 },
+ { "SGMII_HDUPLEX", 4, 1 },
+ { "SGMII_SPEED", 2, 2 },
+ { "USE_SGMII_AN", 1, 1 },
+ { "SGMII_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_ACT_CTL_SEG", 0x31200, 0 },
+ { "MAC_PORT_MTIP_MODE_CTL_SEG", 0x31204, 0 },
+ { "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x31208, 0 },
+ { "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3120c, 0 },
+ { "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x31220, 0 },
+ { "MAC_PORT_MTIP_VL_INTVL", 0x31240, 0 },
+ { "VL_INTVL", 1, 1 },
+ { "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x31600, 0 },
+ { "CLK_DIV", 7, 9 },
+ { "CL45_EN", 6, 1 },
+ { "disable_preamble", 5, 1 },
+ { "mdio_hold_time", 2, 3 },
+ { "mdio_read_err", 1, 1 },
+ { "mdio_busy", 0, 1 },
+ { "MAC_PORT_MTIP_MDIO_COMMAND", 0x31604, 0 },
+ { "read", 15, 1 },
+ { "read_incr", 14, 1 },
+ { "port_addr", 5, 5 },
+ { "dev_addr", 0, 5 },
+ { "MAC_PORT_MTIP_MDIO_DATA", 0x31608, 0 },
+ { "readbusy", 31, 1 },
+ { "data_word", 0, 16 },
+ { "MAC_PORT_MTIP_MDIO_REGADDR", 0x3160c, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_0", 0x31a00, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_1", 0x31a04, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_2", 0x31a08, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_3", 0x31a0c, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_4", 0x31a10, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_5", 0x31a14, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_6", 0x31a18, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_7", 0x31a1c, 0 },
+ { "MAC_PORT_MTIP_PCS_CTL", 0x31e00, 0 },
+ { "RESET", 15, 1 },
+ { "LPBK", 14, 1 },
+ { "SPEED_SEL1", 13, 1 },
+ { "LP_MODE", 11, 1 },
+ { "SPEED_SEL0", 6, 1 },
+ { "SPEED", 2, 4 },
+ { "MAC_PORT_MTIP_PCS_STATUS1", 0x31e04, 0 },
+ { "FaultDet", 7, 1 },
+ { "rx_link_status", 2, 1 },
+ { "LoPwrAbl", 1, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x31e08, 0 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x31e0c, 0 },
+ { "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x31e10, 0 },
+ { "100G", 8, 1 },
+ { "40G", 7, 1 },
+ { "10BASE_TL", 1, 1 },
+ { "10G", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x31e14, 0 },
+ { "TC", 6, 1 },
+ { "DTEXS", 5, 1 },
+ { "PHYXS", 4, 1 },
+ { "PCS", 3, 1 },
+ { "WIS", 2, 1 },
+ { "PMD_PMA", 1, 1 },
+ { "CL22", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x31e18, 0 },
+ { "VendDev2", 15, 1 },
+ { "VendDev1", 14, 1 },
+ { "CL22EXT", 13, 1 },
+ { "MAC_PORT_MTIP_PCS_CTL2", 0x31e1c, 0 },
+ { "MAC_PORT_MTIP_PCS_STATUS2", 0x31e20, 0 },
+ { "Device", 15, 1 },
+ { "TxFault", 7, 1 },
+ { "RxFault", 6, 1 },
+ { "100BASE_R", 5, 1 },
+ { "40GBASE_R", 4, 1 },
+ { "10GBASE_T", 3, 1 },
+ { "10GBASE_W", 2, 1 },
+ { "10GBASE_X", 1, 1 },
+ { "10GBASE_R", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_PKG_ID0", 0x31e38, 0 },
+ { "MAC_PORT_MTIP_PCS_PKG_ID1", 0x31e3c, 0 },
+ { "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x31e80, 0 },
+ { "RxLinkStatus", 12, 1 },
+ { "RESEREVED", 4, 8 },
+ { "10GPRBS9", 3, 1 },
+ { "10GPRBS31", 2, 1 },
+ { "HiBER", 1, 1 },
+ { "blocklock", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x31e84, 0 },
+ { "blocklockLL", 15, 1 },
+ { "HiBERLH", 14, 1 },
+ { "HiBERCount", 8, 6 },
+ { "ErrBlkCnt", 0, 8 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A", 0x31e88, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x31e8c, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x31e90, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x31e94, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B", 0x31e98, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x31e9c, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x31ea0, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x31ea4, 0 },
+ { "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x31ea8, 0 },
+ { "TXPRBS9", 6, 1 },
+ { "RXPRBS31", 5, 1 },
+ { "TXPRBS31", 4, 1 },
+ { "TxTestPatEn", 3, 1 },
+ { "RxTestPatEn", 2, 1 },
+ { "TestPatSel", 1, 1 },
+ { "DataPatSel", 0, 1 },
+ { "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x31eac, 0 },
+ { "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x31eb0, 0 },
+ { "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x31eb4, 0 },
+ { "HiCountPrsnt", 15, 1 },
+ { "BLOCK_CNT_HI", 0, 14 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x31ec8, 0 },
+ { "alignstatus", 12, 1 },
+ { "Lane7", 7, 1 },
+ { "Lane6", 6, 1 },
+ { "Lane5", 5, 1 },
+ { "Lane4", 4, 1 },
+ { "Lane3", 3, 1 },
+ { "Lane2", 2, 1 },
+ { "Lane1", 1, 1 },
+ { "Lane0", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x31ecc, 0 },
+ { "Lane19", 11, 1 },
+ { "Lane18", 10, 1 },
+ { "Lane17", 9, 1 },
+ { "Lane16", 8, 1 },
+ { "Lane15", 7, 1 },
+ { "Lane14", 6, 1 },
+ { "Lane13", 5, 1 },
+ { "Lane12", 4, 1 },
+ { "Lane11", 3, 1 },
+ { "Lane10", 2, 1 },
+ { "Lane9", 1, 1 },
+ { "Lane8", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x31ed0, 0 },
+ { "AMLOCK7", 7, 1 },
+ { "AMLOCK6", 6, 1 },
+ { "AMLOCK5", 5, 1 },
+ { "AMLOCK4", 4, 1 },
+ { "AMLOCK3", 3, 1 },
+ { "AMLOCK2", 2, 1 },
+ { "AMLOCK1", 1, 1 },
+ { "AMLOCK0", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x31ed4, 0 },
+ { "AMLOCK19", 11, 1 },
+ { "AMLOCK18", 10, 1 },
+ { "AMLOCK17", 9, 1 },
+ { "AMLOCK16", 8, 1 },
+ { "AMLOCK15", 7, 1 },
+ { "AMLOCK14", 6, 1 },
+ { "AMLOCK13", 5, 1 },
+ { "AMLOCK12", 4, 1 },
+ { "AMLOCK11", 3, 1 },
+ { "AMLOCK10", 2, 1 },
+ { "AMLOCK9", 1, 1 },
+ { "AMLOCK8", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x31f68, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x31f6c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x31f70, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x31f74, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x31f78, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x31f7c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x31f80, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x31f84, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x31f88, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x31f8c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x31f90, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x31f94, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x31f98, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x31f9c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x31fa0, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x31fa4, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x31fa8, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x31fac, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x31fb0, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x31fb4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x31fb8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x31fbc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x31fc0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x31fc4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x31fc8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x31fcc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x31fd0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x31fd4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x31fd8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x31fdc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x31fe0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x31fe4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x31fe8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x31fec, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x31ff0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x31ff4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x31ff8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x31ffc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x32000, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x32004, 0 },
+ { "MAC_PORT_BEAN_CTL", 0x32200, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS", 0x32204, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0", 0x32208, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1", 0x3220c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2", 0x32210, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0", 0x32214, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1", 0x32218, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2", 0x3221c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT", 0x32220, 0 },
+ { "MAC_PORT_BEAN_XNP_0", 0x32224, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1", 0x32228, 0 },
+ { "MAC_PORT_BEAN_XNP_2", 0x3222c, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0", 0x32230, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1", 0x32234, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2", 0x32238, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS", 0x3223c, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE1", 0x32240, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE1", 0x32244, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x32248, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3224c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x32250, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x32254, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x32258, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3225c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x32260, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE1", 0x32264, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE1", 0x32268, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE1", 0x3226c, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x32270, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x32274, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x32278, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3227c, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE2", 0x32280, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE2", 0x32284, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x32288, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3228c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x32290, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x32294, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x32298, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3229c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x322a0, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE2", 0x322a4, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE2", 0x322a8, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE2", 0x322ac, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x322b0, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x322b4, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x322b8, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x322bc, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE3", 0x322c0, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE3", 0x322c4, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x322c8, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x322cc, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x322d0, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x322d4, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x322d8, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x322dc, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x322e0, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE3", 0x322e4, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE3", 0x322e8, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE3", 0x322ec, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x322f0, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x322f4, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x322f8, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x322fc, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_FEC_KR_CONTROL", 0x32600, 0 },
+ { "enable_tr", 1, 1 },
+ { "restart_tr", 0, 1 },
+ { "MAC_PORT_FEC_KR_STATUS", 0x32604, 0 },
+ { "fecKRsigdet", 15, 1 },
+ { "train_fail", 3, 1 },
+ { "startup_status", 2, 1 },
+ { "frame_lock", 1, 1 },
+ { "rx_status", 0, 1 },
+ { "MAC_PORT_FEC_KR_LP_COEFF", 0x32608, 0 },
+ { "Preset", 13, 1 },
+ { "Initialize", 12, 1 },
+ { "CP1_UPD", 4, 2 },
+ { "C0_UPD", 2, 2 },
+ { "CN1_UPD", 0, 2 },
+ { "MAC_PORT_FEC_KR_LP_STAT", 0x3260c, 0 },
+ { "rx_ready", 15, 1 },
+ { "CP1_STAT", 4, 2 },
+ { "C0_STAT", 2, 2 },
+ { "CN1_STAT", 0, 2 },
+ { "MAC_PORT_FEC_KR_LD_COEFF", 0x32610, 0 },
+ { "Preset", 13, 1 },
+ { "Initialize", 12, 1 },
+ { "CP1_UPD", 4, 2 },
+ { "C0_UPD", 2, 2 },
+ { "CN1_UPD", 0, 2 },
+ { "MAC_PORT_FEC_KR_LD_STAT", 0x32614, 0 },
+ { "rx_ready", 15, 1 },
+ { "CP1_STAT", 4, 2 },
+ { "C0_STAT", 2, 2 },
+ { "CN1_STAT", 0, 2 },
+ { "MAC_PORT_FEC_ABILITY", 0x32618, 0 },
+ { "fec_ind_ability", 1, 1 },
+ { "ability", 0, 1 },
+ { "MAC_PORT_FEC_CONTROL", 0x3261c, 0 },
+ { "fec_en_err_ind", 1, 1 },
+ { "fec_en", 0, 1 },
+ { "MAC_PORT_FEC_STATUS", 0x32620, 0 },
+ { "FEC_LOCKED_100", 1, 1 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_FEC_CERR_CNT_0", 0x32624, 0 },
+ { "MAC_PORT_FEC_CERR_CNT_1", 0x32628, 0 },
+ { "MAC_PORT_FEC_NCERR_CNT_0", 0x3262c, 0 },
+ { "MAC_PORT_FEC_NCERR_CNT_1", 0x32630, 0 },
+ { "MAC_PORT_AE_RX_COEF_REQ", 0x32a00, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT", 0x32a04, 0 },
+ { "T5_AE0_RXSTAT_RDY", 15, 1 },
+ { "T5_AE0_RXSTAT_C2", 4, 2 },
+ { "T5_AE0_RXSTAT_C1", 2, 2 },
+ { "T5_AE0_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ", 0x32a08, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT", 0x32a0c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE", 0x32a10, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL", 0x32a14, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL", 0x32a18, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE", 0x32a1c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_1", 0x32a20, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_1", 0x32a24, 0 },
+ { "T5_AE1_RXSTAT_RDY", 15, 1 },
+ { "T5_AE1_RXSTAT_C2", 4, 2 },
+ { "T5_AE1_RXSTAT_C1", 2, 2 },
+ { "T5_AE1_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_1", 0x32a28, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_1", 0x32a2c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_1", 0x32a30, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_1", 0x32a34, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_1", 0x32a38, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_1", 0x32a3c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_2", 0x32a40, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_2", 0x32a44, 0 },
+ { "T5_AE2_RXSTAT_RDY", 15, 1 },
+ { "T5_AE2_RXSTAT_C2", 4, 2 },
+ { "T5_AE2_RXSTAT_C1", 2, 2 },
+ { "T5_AE2_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_2", 0x32a48, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_2", 0x32a4c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_2", 0x32a50, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_2", 0x32a54, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_2", 0x32a58, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_2", 0x32a5c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_3", 0x32a60, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_3", 0x32a64, 0 },
+ { "T5_AE3_RXSTAT_RDY", 15, 1 },
+ { "T5_AE3_RXSTAT_C2", 4, 2 },
+ { "T5_AE3_RXSTAT_C1", 2, 2 },
+ { "T5_AE3_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_3", 0x32a68, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_3", 0x32a6c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_3", 0x32a70, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_3", 0x32a74, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_3", 0x32a78, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_3", 0x32a7c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_TX_DIS", 0x32a80, 0 },
+ { "MAC_PORT_AE_KR_CTRL", 0x32a84, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET", 0x32a88, 0 },
+ { "MAC_PORT_AE_KR_STATUS", 0x32a8c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_1", 0x32a90, 0 },
+ { "MAC_PORT_AE_KR_CTRL_1", 0x32a94, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_1", 0x32a98, 0 },
+ { "MAC_PORT_AE_KR_STATUS_1", 0x32a9c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_2", 0x32aa0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_2", 0x32aa4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_2", 0x32aa8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_2", 0x32aac, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_3", 0x32ab0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_3", 0x32ab4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_3", 0x32ab8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_3", 0x32abc, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x32b00, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x32b04, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_0", 0x32b08, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x32b0c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_0", 0x32b10, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x32b20, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x32b24, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_1", 0x32b28, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x32b2c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_1", 0x32b30, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x32b40, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x32b44, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_2", 0x32b48, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x32b4c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_2", 0x32b50, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x32b60, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x32b64, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_3", 0x32b68, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x32b6c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_3", 0x32b70, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_ANALOG_TEST_MUX", 0x33814, 0 },
+ { "MAC_PORT_BANDGAP_CONTROL", 0x3382c, 0 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x33880, 0 },
+ { "RCCTL1", 5, 1 },
+ { "RCCTL0", 4, 1 },
+ { "RCAMP1", 3, 1 },
+ { "RCAMP0", 2, 1 },
+ { "RCAMPEN", 1, 1 },
+ { "RCRST", 0, 1 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x33884, 0 },
+ { "RCERR", 1, 1 },
+ { "RCCOMP", 0, 1 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x33888, 0 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3388c, 0 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_6", 0x338e8, 0 },
+ { "LBIST", 7, 1 },
+ { "LOGICTEST", 6, 1 },
+ { "MAVDHI", 5, 1 },
+ { "AUXEN", 4, 1 },
+ { "JTAGMD", 3, 1 },
+ { "RXACMODE", 2, 1 },
+ { "HSSACJPC", 1, 1 },
+ { "HSSACJAC", 0, 1 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_5", 0x338ec, 0 },
+ { "REFVALIDD", 6, 1 },
+ { "REFVALIDC", 5, 1 },
+ { "REFVALIDB", 4, 1 },
+ { "REFVALIDA", 3, 1 },
+ { "REFSELRESET", 2, 1 },
+ { "SOFTRESET", 1, 1 },
+ { "MACROTEST", 0, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x33b00, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x33b04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x33b08, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x33b0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x33b10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x33b28, 0 },
+ { "MAC_PORT_PLLA_PCLK_CONTROL", 0x33b3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x33b40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x33b44, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x33b48, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x33b4c, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x33b50, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x33bf0, 0 },
+ { "VBST", 1, 3 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x33bf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "PDWNP", 2, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x33bf8, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x33bfc, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x33c00, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x33c04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x33c08, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x33c0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x33c10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x33c28, 0 },
+ { "MAC_PORT_PLLB_PCLK_CONTROL", 0x33c3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x33c40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x33c44, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x33c48, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x33c4c, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x33c50, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x33cf0, 0 },
+ { "VBST", 1, 3 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x33cf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "PDWNP", 2, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x33cf8, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x33cfc, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x33000, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x33004, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x33008, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3300c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33010, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33014, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33018, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3301c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x33020, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x33024, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x33028, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x33030, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x33034, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33038, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3303c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33040, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33044, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33048, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33060, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33064, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33068, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33070, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33074, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33078, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3307c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33080, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33084, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33088, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3308c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x33090, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x33094, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x33098, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3309c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x330f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x330f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x330f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x330fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x33100, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x33104, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x33108, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3310c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33110, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33114, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33118, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3311c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x33120, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x33124, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x33128, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x33130, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x33134, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33138, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3313c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33140, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33144, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33148, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33160, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33164, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33168, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33170, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33174, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33178, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3317c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33180, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33184, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33188, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3318c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x33190, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x33194, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x33198, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3319c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x331f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x331f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x331f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x331fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x33400, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x33404, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x33408, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3340c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33410, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33414, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33418, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3341c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x33420, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x33424, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x33428, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x33430, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x33434, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33438, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3343c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33440, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33444, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33448, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33460, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33464, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33468, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33470, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33474, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33478, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3347c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33480, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33484, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33488, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3348c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x33490, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x33494, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x33498, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3349c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x334f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x334f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x334f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x334fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x33500, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x33504, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x33508, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3350c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33510, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33514, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33518, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3351c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x33520, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x33524, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x33528, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x33530, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x33534, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33538, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3353c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33540, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33544, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33548, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33560, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33564, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33568, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33570, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33574, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33578, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3357c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33580, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33584, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33588, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3358c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x33590, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x33594, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x33598, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3359c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x335f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x335f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x335f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x335fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x33900, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x33904, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x33908, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3390c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33910, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33914, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33918, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3391c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x33920, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x33924, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x33928, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x33930, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x33934, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33938, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3393c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33940, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33944, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33948, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33960, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33964, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33968, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33970, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33974, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33978, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3397c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33980, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33984, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33988, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3398c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x33990, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x33994, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x33998, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3399c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x339f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x339f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x339f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x339fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x33200, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x33204, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x33208, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3320c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x33210, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x33214, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33218, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3321c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x33220, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x33224, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x33228, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3322c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x33230, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x33234, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x33238, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x33240, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x33248, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3324c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x33250, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3325c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33260, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33264, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33270, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x33274, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x33278, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3327c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x33280, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x33284, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x33288, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3328c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x33290, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x33294, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x33298, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3329c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x332a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x332a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x332a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x332ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x332b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x332b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x332b8, 0 },
+ { "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x332c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKA_DFE_H1", 0x332c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H2", 0x332c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_H3", 0x332cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H4", 0x332d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H5", 0x332d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x332d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x332dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x332e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H12", 0x332e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x332f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x332fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x33300, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x33304, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x33308, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3330c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x33310, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x33314, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33318, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3331c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x33320, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x33324, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x33328, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3332c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x33330, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x33334, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x33338, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x33340, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x33348, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3334c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x33350, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3335c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33360, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33364, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33370, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x33374, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x33378, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3337c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x33380, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x33384, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x33388, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3338c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x33390, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x33394, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x33398, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3339c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x333a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x333a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x333a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x333ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x333b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x333b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x333b8, 0 },
+ { "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x333c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKB_DFE_H1", 0x333c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H2", 0x333c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_H3", 0x333cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H4", 0x333d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H5", 0x333d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x333d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x333dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x333e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H12", 0x333e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x333f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x333fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x33600, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x33604, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x33608, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3360c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x33610, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x33614, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33618, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3361c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x33620, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x33624, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x33628, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3362c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x33630, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x33634, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x33638, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x33640, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x33648, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3364c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x33650, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3365c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33660, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33664, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33670, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x33674, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x33678, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3367c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x33680, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x33684, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x33688, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3368c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x33690, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x33694, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x33698, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3369c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x336a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x336a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x336a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x336ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x336b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x336b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x336b8, 0 },
+ { "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x336c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKC_DFE_H1", 0x336c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H2", 0x336c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_H3", 0x336cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H4", 0x336d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H5", 0x336d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x336d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x336dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x336e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H12", 0x336e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x336f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x336fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x33700, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x33704, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x33708, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3370c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x33710, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x33714, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33718, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3371c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x33720, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x33724, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x33728, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3372c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x33730, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x33734, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x33738, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x33740, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x33748, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3374c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x33750, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3375c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33760, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33764, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33770, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x33774, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x33778, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3377c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x33780, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x33784, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x33788, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3378c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x33790, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x33794, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x33798, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3379c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x337a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x337a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x337a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x337ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x337b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x337b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x337b8, 0 },
+ { "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x337c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKD_DFE_H1", 0x337c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H2", 0x337c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_H3", 0x337cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H4", 0x337d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H5", 0x337d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x337d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x337dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x337e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H12", 0x337e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x337f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x337fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x33a00, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x33a04, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x33a08, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x33a0c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x33a10, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x33a14, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33a18, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x33a1c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x33a20, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x33a24, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x33a28, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x33a2c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x33a30, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x33a34, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x33a38, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x33a40, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x33a48, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x33a4c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x33a50, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x33a5c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33a60, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33a64, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33a70, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x33a74, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x33a78, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x33a7c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x33a80, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x33a84, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x33a88, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x33a8c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x33a90, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x33a94, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x33a98, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x33a9c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x33aa0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x33aa4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x33aa8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x33aac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x33ab0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x33ab4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x33ab8, 0 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x33ac0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x33ac4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x33ac8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x33acc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x33ad0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x33ad4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x33ad8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x33adc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x33ae0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x33ae4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x33af8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x33afc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_CFG", 0x34800, 0 },
+ { "MAC_Clk_Sel", 29, 3 },
+ { "SinkTx", 27, 1 },
+ { "SinkTxOnLinkDown", 26, 1 },
+ { "LoopNoFwd", 24, 1 },
+ { "Smux_Rx_Loop", 19, 1 },
+ { "Rx_Lane_Swap", 18, 1 },
+ { "Tx_Lane_Swap", 17, 1 },
+ { "Signal_Det", 14, 1 },
+ { "SmuxTxSel", 9, 1 },
+ { "SmuxRxSel", 8, 1 },
+ { "PortSpeed", 4, 2 },
+ { "Rx_Byte_Swap", 3, 1 },
+ { "Tx_Byte_Swap", 2, 1 },
+ { "Port_Sel", 0, 1 },
+ { "MAC_PORT_RESET_CTRL", 0x34804, 0 },
+ { "TWGDSK_HSSC16B", 31, 1 },
+ { "EEE_RESET", 30, 1 },
+ { "PTP_TIMER", 29, 1 },
+ { "MtipRefReset", 28, 1 },
+ { "MtipTxffReset", 27, 1 },
+ { "MtipRxffReset", 26, 1 },
+ { "MtipRegReset", 25, 1 },
+ { "AEC3Reset", 23, 1 },
+ { "AEC2Reset", 22, 1 },
+ { "AEC1Reset", 21, 1 },
+ { "AEC0Reset", 20, 1 },
+ { "AET3Reset", 19, 1 },
+ { "AET2Reset", 18, 1 },
+ { "AET1Reset", 17, 1 },
+ { "AET0Reset", 16, 1 },
+ { "TXIF_Reset", 12, 1 },
+ { "RXIF_Reset", 11, 1 },
+ { "AuxExt_Reset", 10, 1 },
+ { "MtipSd3TxRst", 9, 1 },
+ { "MtipSd2TxRst", 8, 1 },
+ { "MtipSd1TxRst", 7, 1 },
+ { "MtipSd0TxRst", 6, 1 },
+ { "MtipSd3RxRst", 5, 1 },
+ { "MtipSd2RxRst", 4, 1 },
+ { "MtipSd1RxRst", 3, 1 },
+ { "WOL_Reset", 2, 1 },
+ { "MtipSd0RxRst", 1, 1 },
+ { "HSS_Reset", 0, 1 },
+ { "MAC_PORT_LED_CFG", 0x34808, 0 },
+ { "Led1_Cfg", 5, 3 },
+ { "Led1_Polarity_Inv", 4, 1 },
+ { "Led0_Cfg", 1, 3 },
+ { "Led0_Polarity_Inv", 0, 1 },
+ { "MAC_PORT_LED_COUNTHI", 0x3480c, 0 },
+ { "MAC_PORT_LED_COUNTLO", 0x34810, 0 },
+ { "MAC_PORT_CFG3", 0x34814, 0 },
+ { "FPGA_PTP_PORT", 26, 2 },
+ { "FCSDisCtrl", 25, 1 },
+ { "SigDetCtrl", 24, 1 },
+ { "tx_lane", 23, 1 },
+ { "rx_lane", 22, 1 },
+ { "se_clr", 21, 1 },
+ { "an_ena", 17, 4 },
+ { "sd_rx_clk_ena", 13, 4 },
+ { "sd_tx_clk_ena", 9, 4 },
+ { "SGMIISEL", 8, 1 },
+ { "HSSPLLSEL", 4, 4 },
+ { "HSSC16C20SEL", 0, 4 },
+ { "MAC_PORT_CFG2", 0x34818, 0 },
+ { "Rx_Polarity_Inv", 28, 4 },
+ { "Tx_Polarity_Inv", 24, 4 },
+ { "InstanceNum", 22, 2 },
+ { "StopOnPerr", 21, 1 },
+ { "PatEn", 18, 1 },
+ { "MagicEn", 17, 1 },
+ { "T5_AEC_PMA_TX_READY", 4, 4 },
+ { "T5_AEC_PMA_RX_READY", 0, 4 },
+ { "MAC_PORT_PKT_COUNT", 0x3481c, 0 },
+ { "tx_sop_count", 24, 8 },
+ { "tx_eop_count", 16, 8 },
+ { "rx_sop_count", 8, 8 },
+ { "rx_eop_count", 0, 8 },
+ { "MAC_PORT_CFG4", 0x34820, 0 },
+ { "AEC3_RX_WIDTH", 14, 2 },
+ { "AEC2_RX_WIDTH", 12, 2 },
+ { "AEC1_RX_WIDTH", 10, 2 },
+ { "AEC0_RX_WIDTH", 8, 2 },
+ { "AEC3_TX_WIDTH", 6, 2 },
+ { "AEC2_TX_WIDTH", 4, 2 },
+ { "AEC1_TX_WIDTH", 2, 2 },
+ { "AEC0_TX_WIDTH", 0, 2 },
+ { "MAC_PORT_MAGIC_MACID_LO", 0x34824, 0 },
+ { "MAC_PORT_MAGIC_MACID_HI", 0x34828, 0 },
+ { "MAC_PORT_LINK_STATUS", 0x34834, 0 },
+ { "an_done", 6, 1 },
+ { "align_done", 5, 1 },
+ { "block_lock", 4, 1 },
+ { "remflt", 3, 1 },
+ { "locflt", 2, 1 },
+ { "linkup", 1, 1 },
+ { "linkdn", 0, 1 },
+ { "MAC_PORT_EPIO_DATA0", 0x348c0, 0 },
+ { "MAC_PORT_EPIO_DATA1", 0x348c4, 0 },
+ { "MAC_PORT_EPIO_DATA2", 0x348c8, 0 },
+ { "MAC_PORT_EPIO_DATA3", 0x348cc, 0 },
+ { "MAC_PORT_EPIO_OP", 0x348d0, 0 },
+ { "Busy", 31, 1 },
+ { "Write", 8, 1 },
+ { "Address", 0, 8 },
+ { "MAC_PORT_WOL_STATUS", 0x348d4, 0 },
+ { "MagicDetected", 31, 1 },
+ { "PatDetected", 30, 1 },
+ { "ClearMagic", 4, 1 },
+ { "ClearMatch", 3, 1 },
+ { "MatchedFilter", 0, 3 },
+ { "MAC_PORT_INT_EN", 0x348d8, 0 },
+ { "tx_ts_avail", 29, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_INT_CAUSE", 0x348dc, 0 },
+ { "tx_ts_avail", 29, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_PERR_INT_EN", 0x348e0, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_INT_CAUSE", 0x348e4, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_ENABLE", 0x348e8, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_INJECT", 0x348ec, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "MAC_PORT_HSS_CFG0", 0x348f0, 0 },
+ { "TXDTS", 31, 1 },
+ { "TXCTS", 30, 1 },
+ { "TXBTS", 29, 1 },
+ { "TXATS", 28, 1 },
+ { "TXDOBS", 27, 1 },
+ { "TXCOBS", 26, 1 },
+ { "TXBOBS", 25, 1 },
+ { "TXAOBS", 24, 1 },
+ { "HSSREFCLKVALIDA", 20, 1 },
+ { "HSSREFCLKVALIDB", 19, 1 },
+ { "HSSRESYNCA", 18, 1 },
+ { "HSSAVDHI", 17, 1 },
+ { "HSSRESYNCB", 16, 1 },
+ { "HSSRECCALA", 15, 1 },
+ { "HSSRXACMODE", 14, 1 },
+ { "HSSRECCALB", 13, 1 },
+ { "HSSPLLBYPA", 12, 1 },
+ { "HSSPLLBYPB", 11, 1 },
+ { "HSSPDWNPLLA", 10, 1 },
+ { "HSSPDWNPLLB", 9, 1 },
+ { "HSSVCOSELA", 8, 1 },
+ { "HSSVCOSELB", 7, 1 },
+ { "HSSCALCOMP", 6, 1 },
+ { "HSSCALENAB", 5, 1 },
+ { "HSSEXTC16SEL", 4, 1 },
+ { "MAC_PORT_HSS_CFG1", 0x348f4, 0 },
+ { "RXACONFIGSEL", 30, 2 },
+ { "RXAQUIET", 29, 1 },
+ { "RXAREFRESH", 28, 1 },
+ { "RXBCONFIGSEL", 26, 2 },
+ { "RXBQUIET", 25, 1 },
+ { "RXBREFRESH", 24, 1 },
+ { "RXCCONFIGSEL", 22, 2 },
+ { "RXCQUIET", 21, 1 },
+ { "RXCREFRESH", 20, 1 },
+ { "RXDCONFIGSEL", 18, 2 },
+ { "RXDQUIET", 17, 1 },
+ { "RXDREFRESH", 16, 1 },
+ { "TXACONFIGSEL", 14, 2 },
+ { "TXAQUIET", 13, 1 },
+ { "TXAREFRESH", 12, 1 },
+ { "TXBCONFIGSEL", 10, 2 },
+ { "TXBQUIET", 9, 1 },
+ { "TXBREFRESH", 8, 1 },
+ { "TXCCONFIGSEL", 6, 2 },
+ { "TXCQUIET", 5, 1 },
+ { "TXCREFRESH", 4, 1 },
+ { "TXDCONFIGSEL", 2, 2 },
+ { "TXDQUIET", 1, 1 },
+ { "TXDREFRESH", 0, 1 },
+ { "MAC_PORT_HSS_CFG2", 0x348f8, 0 },
+ { "RXAASSTCLK", 31, 1 },
+ { "T5RXAPRBSRST", 30, 1 },
+ { "RXBASSTCLK", 29, 1 },
+ { "T5RXBPRBSRST", 28, 1 },
+ { "RXCASSTCLK", 27, 1 },
+ { "T5RXCPRBSRST", 26, 1 },
+ { "RXDASSTCLK", 25, 1 },
+ { "T5RXDPRBSRST", 24, 1 },
+ { "RXDDATASYNC", 23, 1 },
+ { "RXCDATASYNC", 22, 1 },
+ { "RXBDATASYNC", 21, 1 },
+ { "RXADATASYNC", 20, 1 },
+ { "RXDEARLYIN", 19, 1 },
+ { "RXDLATEIN", 18, 1 },
+ { "RXDPHSLOCK", 17, 1 },
+ { "RXDPHSDNIN", 16, 1 },
+ { "RXDPHSUPIN", 15, 1 },
+ { "RXCEARLYIN", 14, 1 },
+ { "RXCLATEIN", 13, 1 },
+ { "RXCPHSLOCK", 12, 1 },
+ { "RXCPHSDNIN", 11, 1 },
+ { "RXCPHSUPIN", 10, 1 },
+ { "RXBEARLYIN", 9, 1 },
+ { "RXBLATEIN", 8, 1 },
+ { "RXBPHSLOCK", 7, 1 },
+ { "RXBPHSDNIN", 6, 1 },
+ { "RXBPHSUPIN", 5, 1 },
+ { "RXAEARLYIN", 4, 1 },
+ { "RXALATEIN", 3, 1 },
+ { "RXAPHSLOCK", 2, 1 },
+ { "RXAPHSDNIN", 1, 1 },
+ { "RXAPHSUPIN", 0, 1 },
+ { "MAC_PORT_HSS_CFG3", 0x348fc, 0 },
+ { "HSSCALSSTN", 25, 3 },
+ { "HSSCALSSTP", 22, 3 },
+ { "HSSVBOOSTDIVB", 19, 3 },
+ { "HSSVBOOSTDIVA", 16, 3 },
+ { "HSSPLLCONFIGB", 8, 8 },
+ { "HSSPLLCONFIGA", 0, 8 },
+ { "MAC_PORT_HSS_CFG4", 0x34900, 0 },
+ { "HSSDIVSELA", 9, 9 },
+ { "HSSDIVSELB", 0, 9 },
+ { "MAC_PORT_HSS_STATUS", 0x34904, 0 },
+ { "RXDPRBSSYNC", 15, 1 },
+ { "RXCPRBSSYNC", 14, 1 },
+ { "RXBPRBSSYNC", 13, 1 },
+ { "RXAPRBSSYNC", 12, 1 },
+ { "RXDPRBSERR", 11, 1 },
+ { "RXCPRBSERR", 10, 1 },
+ { "RXBPRBSERR", 9, 1 },
+ { "RXAPRBSERR", 8, 1 },
+ { "RXDSIGDET", 7, 1 },
+ { "RXCSIGDET", 6, 1 },
+ { "RXBSIGDET", 5, 1 },
+ { "RXASIGDET", 4, 1 },
+ { "HSSPLLLOCKB", 3, 1 },
+ { "HSSPLLLOCKA", 2, 1 },
+ { "HSSPRTREADYB", 1, 1 },
+ { "HSSPRTREADYA", 0, 1 },
+ { "MAC_PORT_HSS_EEE_STATUS", 0x34908, 0 },
+ { "RXAQUIET_STATUS", 15, 1 },
+ { "RXAREFRESH_STATUS", 14, 1 },
+ { "RXBQUIET_STATUS", 13, 1 },
+ { "RXBREFRESH_STATUS", 12, 1 },
+ { "RXCQUIET_STATUS", 11, 1 },
+ { "RXCREFRESH_STATUS", 10, 1 },
+ { "RXDQUIET_STATUS", 9, 1 },
+ { "RXDREFRESH_STATUS", 8, 1 },
+ { "TXAQUIET_STATUS", 7, 1 },
+ { "TXAREFRESH_STATUS", 6, 1 },
+ { "TXBQUIET_STATUS", 5, 1 },
+ { "TXBREFRESH_STATUS", 4, 1 },
+ { "TXCQUIET_STATUS", 3, 1 },
+ { "TXCREFRESH_STATUS", 2, 1 },
+ { "TXDQUIET_STATUS", 1, 1 },
+ { "TXDREFRESH_STATUS", 0, 1 },
+ { "MAC_PORT_HSS_SIGDET_STATUS", 0x3490c, 0 },
+ { "MAC_PORT_HSS_PL_CTL", 0x34910, 0 },
+ { "TOV", 16, 8 },
+ { "TSU", 8, 8 },
+ { "IPW", 0, 8 },
+ { "MAC_PORT_RUNT_FRAME", 0x34914, 0 },
+ { "runtclear", 16, 1 },
+ { "runt", 0, 16 },
+ { "MAC_PORT_EEE_STATUS", 0x34918, 0 },
+ { "eee_tx_10g_state", 10, 2 },
+ { "eee_rx_10g_state", 8, 2 },
+ { "eee_tx_1g_state", 6, 2 },
+ { "eee_rx_1g_state", 4, 2 },
+ { "pma_rx_refresh", 3, 1 },
+ { "pma_rx_quiet", 2, 1 },
+ { "pma_tx_refresh", 1, 1 },
+ { "pma_tx_quiet", 0, 1 },
+ { "MAC_PORT_CGEN", 0x3491c, 0 },
+ { "CGEN", 8, 1 },
+ { "sd7_CGEN", 7, 1 },
+ { "sd6_CGEN", 6, 1 },
+ { "sd5_CGEN", 5, 1 },
+ { "sd4_CGEN", 4, 1 },
+ { "sd3_CGEN", 3, 1 },
+ { "sd2_CGEN", 2, 1 },
+ { "sd1_CGEN", 1, 1 },
+ { "sd0_CGEN", 0, 1 },
+ { "MAC_PORT_CGEN_MTIP", 0x34920, 0 },
+ { "MACSEG5_CGEN", 11, 1 },
+ { "PCSSEG5_CGEN", 10, 1 },
+ { "MACSEG4_CGEN", 9, 1 },
+ { "PCSSEG4_CGEN", 8, 1 },
+ { "MACSEG3_CGEN", 7, 1 },
+ { "PCSSEG3_CGEN", 6, 1 },
+ { "MACSEG2_CGEN", 5, 1 },
+ { "PCSSEG2_CGEN", 4, 1 },
+ { "MACSEG1_CGEN", 3, 1 },
+ { "PCSSEG1_CGEN", 2, 1 },
+ { "MACSEG0_CGEN", 1, 1 },
+ { "PCSSEG0_CGEN", 0, 1 },
+ { "MAC_PORT_TX_TS_ID", 0x34924, 0 },
+ { "MAC_PORT_TX_TS_VAL_LO", 0x34928, 0 },
+ { "MAC_PORT_TX_TS_VAL_HI", 0x3492c, 0 },
+ { "MAC_PORT_EEE_CTL", 0x34930, 0 },
+ { "EEE_CTRL", 2, 30 },
+ { "TICK_START", 1, 1 },
+ { "En", 0, 1 },
+ { "MAC_PORT_EEE_TX_CTL", 0x34934, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_ACTIVE", 3, 1 },
+ { "LPI_TXHOLD", 2, 1 },
+ { "LPI_REQ", 1, 1 },
+ { "EEE_TX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_RX_CTL", 0x34938, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_IND", 1, 1 },
+ { "EEE_RX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3493c, 0 },
+ { "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x34940, 0 },
+ { "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x34944, 0 },
+ { "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x34948, 0 },
+ { "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3494c, 0 },
+ { "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x34950, 0 },
+ { "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x34954, 0 },
+ { "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x34958, 0 },
+ { "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3495c, 0 },
+ { "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x34960, 0 },
+ { "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x34964, 0 },
+ { "MAC_PORT_EEE_WF_COUNT", 0x34968, 0 },
+ { "wake_cnt_clr", 16, 1 },
+ { "wake_cnt", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_RD0_LO", 0x3496c, 0 },
+ { "MAC_PORT_PTP_TIMER_RD0_HI", 0x34970, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_LO", 0x34974, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_HI", 0x34978, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_LO", 0x3497c, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_HI", 0x34980, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_0", 0x34984, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_1", 0x34988, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3498c, 0 },
+ { "MAC_PORT_PTP_SUM_LO", 0x34990, 0 },
+ { "MAC_PORT_PTP_SUM_HI", 0x34994, 0 },
+ { "MAC_PORT_PTP_TIMER_INCR0", 0x34998, 0 },
+ { "Y", 16, 16 },
+ { "X", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_INCR1", 0x3499c, 0 },
+ { "Y_TICK", 16, 16 },
+ { "X_TICK", 0, 16 },
+ { "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x349a0, 0 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x349a4, 0 },
+ { "B", 16, 16 },
+ { "A", 0, 16 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x349a8, 0 },
+ { "MAC_PORT_PTP_CFG", 0x349ac, 0 },
+ { "FRZ", 18, 1 },
+ { "OFFSER_ADJUST_SIGN", 17, 1 },
+ { "ADD_OFFSET", 16, 1 },
+ { "CYCLE1", 8, 8 },
+ { "Q", 0, 8 },
+ { "MAC_PORT_MTIP_REVISION", 0x34a00, 0 },
+ { "CUSTREV", 16, 16 },
+ { "VER", 8, 8 },
+ { "REV", 0, 8 },
+ { "MAC_PORT_MTIP_SCRATCH", 0x34a04, 0 },
+ { "MAC_PORT_MTIP_COMMAND_CONFIG", 0x34a08, 0 },
+ { "TX_FLUSH", 22, 1 },
+ { "RX_SFD_ANY", 21, 1 },
+ { "PAUSE_PFC_COMP", 20, 1 },
+ { "PFC_MODE", 19, 1 },
+ { "RS_COL_CNT_EXT", 18, 1 },
+ { "NO_LGTH_CHECK", 17, 1 },
+ { "SEND_IDLE", 16, 1 },
+ { "PHY_TXENA", 15, 1 },
+ { "RX_ERR_DISC", 14, 1 },
+ { "CMD_FRAME_ENA", 13, 1 },
+ { "SW_RESET", 12, 1 },
+ { "TX_PAD_EN", 11, 1 },
+ { "LOOPBACK_EN", 10, 1 },
+ { "TX_ADDR_INS", 9, 1 },
+ { "PAUSE_IGNORE", 8, 1 },
+ { "PAUSE_FWD", 7, 1 },
+ { "CRC_FWD", 6, 1 },
+ { "PAD_EN", 5, 1 },
+ { "PROMIS_EN", 4, 1 },
+ { "WAN_MODE", 3, 1 },
+ { "RX_ENA", 1, 1 },
+ { "TX_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_MAC_ADDR_0", 0x34a0c, 0 },
+ { "MAC_PORT_MTIP_MAC_ADDR_1", 0x34a10, 0 },
+ { "MAC_PORT_MTIP_FRM_LENGTH", 0x34a14, 0 },
+ { "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x34a1c, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x34a20, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x34a24, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x34a28, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x34a2c, 0 },
+ { "ENABLE", 8, 1 },
+ { "ADDR", 0, 6 },
+ { "MAC_PORT_MTIP_MAC_STATUS", 0x34a40, 0 },
+ { "TS_AVAIL", 3, 1 },
+ { "PHY_LOS", 2, 1 },
+ { "RX_REM_FAULT", 1, 1 },
+ { "RX_LOC_FAULT", 0, 1 },
+ { "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x34a44, 0 },
+ { "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x34a48, 0 },
+ { "MAC_PORT_MTIP_INIT_CREDIT", 0x34a4c, 0 },
+ { "MAC_PORT_MTIP_CURRENT_CREDIT", 0x34a50, 0 },
+ { "MAC_PORT_RX_PAUSE_STATUS", 0x34a74, 0 },
+ { "MAC_PORT_MTIP_TS_TIMESTAMP", 0x34a7c, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x34a80, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x34a84, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOK", 0x34a88, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x34a8c, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x34a90, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x34a94, 0 },
+ { "MAC_PORT_AALIGNMENTERRORS", 0x34a98, 0 },
+ { "MAC_PORT_AALIGNMENTERRORSHI", 0x34a9c, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x34aa0, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x34aa4, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x34aa8, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x34aac, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORS", 0x34ab0, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x34ab4, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORS", 0x34ab8, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORSHI", 0x34abc, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOK", 0x34ac0, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOKHI", 0x34ac4, 0 },
+ { "MAC_PORT_VLANRECEIVEDOK", 0x34ac8, 0 },
+ { "MAC_PORT_VLANRECEIVEDOKHI", 0x34acc, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x34ad0, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x34ad4, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOK", 0x34ad8, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x34adc, 0 },
+ { "MAC_PORT_IFINUCASTPKTS", 0x34ae0, 0 },
+ { "MAC_PORT_IFINUCASTPKTSHI", 0x34ae4, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTS", 0x34ae8, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTSHI", 0x34aec, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTS", 0x34af0, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTSHI", 0x34af4, 0 },
+ { "MAC_PORT_IFOUTERRORS", 0x34af8, 0 },
+ { "MAC_PORT_IFOUTERRORSHI", 0x34afc, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTS", 0x34b08, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTSHI", 0x34b0c, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTS", 0x34b10, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x34b14, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTS", 0x34b18, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x34b1c, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTS", 0x34b20, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x34b24, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETS", 0x34b28, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETSHI", 0x34b2c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS", 0x34b30, 0 },
+ { "MAC_PORT_ETHERSTATSPKTSHI", 0x34b34, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x34b38, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x34b3c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x34b40, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x34b44, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x34b48, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x34b4c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x34b50, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x34b54, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x34b58, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x34b5c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x34b60, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34b64, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x34b68, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34b6c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x34b70, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x34b74, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x34b78, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x34b7c, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERS", 0x34b80, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERSHI", 0x34b84, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTS", 0x34b88, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x34b8c, 0 },
+ { "MAC_PORT_IFINERRORS", 0x34b90, 0 },
+ { "MAC_PORT_IFINERRORSHI", 0x34b94, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x34b98, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x34b9c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x34ba0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x34ba4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x34ba8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x34bac, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x34bb0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x34bb4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x34bb8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x34bbc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x34bc0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x34bc4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x34bc8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x34bcc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x34bd0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x34bd4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x34bd8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x34bdc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x34be0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x34be4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x34be8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x34bec, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x34bf0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x34bf4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x34bf8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x34bfc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x34c00, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x34c04, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x34c08, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x34c0c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x34c10, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x34c14, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x34c18, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x34c1c, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x34c20, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x34c24, 0 },
+ { "MAC_PORT_MTIP_SGMII_CONTROL", 0x34d00, 0 },
+ { "Reset", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "sppedsel1", 13, 1 },
+ { "AN_EN", 12, 1 },
+ { "PWRDWN", 11, 1 },
+ { "Isolate", 10, 1 },
+ { "AN_RESTART", 9, 1 },
+ { "DPLX", 8, 1 },
+ { "CollisionTest", 7, 1 },
+ { "SpeedSel0", 6, 1 },
+ { "MAC_PORT_MTIP_SGMII_STATUS", 0x34d04, 0 },
+ { "100BaseT4", 15, 1 },
+ { "100BaseXFullDplx", 14, 1 },
+ { "100BaseXHalfDplx", 13, 1 },
+ { "10MbpsFullDplx", 12, 1 },
+ { "10MbpsHalfDplx", 11, 1 },
+ { "100BaseT2FullDplx", 10, 1 },
+ { "100BaseT2HalfDplx", 9, 1 },
+ { "ExtdStatus", 8, 1 },
+ { "AN_Complete", 5, 1 },
+ { "SGMII_REM_FAULT", 4, 1 },
+ { "AN_Ability", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "JabberDetect", 1, 1 },
+ { "ExtdCapability", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x34d08, 0 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x34d0c, 0 },
+ { "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x34d10, 0 },
+ { "NP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "RF2", 13, 1 },
+ { "RF1", 12, 1 },
+ { "PS2", 8, 1 },
+ { "PS1", 7, 1 },
+ { "HD", 6, 1 },
+ { "FD", 5, 1 },
+ { "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x34d14, 0 },
+ { "CuLinkStatus", 15, 1 },
+ { "ACK", 14, 1 },
+ { "CuDplxStatus", 12, 1 },
+ { "CuSpeed", 10, 2 },
+ { "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x34d18, 0 },
+ { "PgRcvd", 1, 1 },
+ { "RealTimePgRcvd", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x34d1c, 0 },
+ { "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x34d20, 0 },
+ { "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x34d3c, 0 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x34d48, 0 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x34d4c, 0 },
+ { "MAC_PORT_MTIP_SGMII_IF_MODE", 0x34d50, 0 },
+ { "SGMII_PCS_ENABLE", 5, 1 },
+ { "SGMII_HDUPLEX", 4, 1 },
+ { "SGMII_SPEED", 2, 2 },
+ { "USE_SGMII_AN", 1, 1 },
+ { "SGMII_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_ACT_CTL_SEG", 0x35200, 0 },
+ { "MAC_PORT_MTIP_MODE_CTL_SEG", 0x35204, 0 },
+ { "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x35208, 0 },
+ { "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3520c, 0 },
+ { "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x35220, 0 },
+ { "MAC_PORT_MTIP_VL_INTVL", 0x35240, 0 },
+ { "VL_INTVL", 1, 1 },
+ { "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x35600, 0 },
+ { "CLK_DIV", 7, 9 },
+ { "CL45_EN", 6, 1 },
+ { "disable_preamble", 5, 1 },
+ { "mdio_hold_time", 2, 3 },
+ { "mdio_read_err", 1, 1 },
+ { "mdio_busy", 0, 1 },
+ { "MAC_PORT_MTIP_MDIO_COMMAND", 0x35604, 0 },
+ { "read", 15, 1 },
+ { "read_incr", 14, 1 },
+ { "port_addr", 5, 5 },
+ { "dev_addr", 0, 5 },
+ { "MAC_PORT_MTIP_MDIO_DATA", 0x35608, 0 },
+ { "readbusy", 31, 1 },
+ { "data_word", 0, 16 },
+ { "MAC_PORT_MTIP_MDIO_REGADDR", 0x3560c, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_0", 0x35a00, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_1", 0x35a04, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_2", 0x35a08, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_3", 0x35a0c, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_4", 0x35a10, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_5", 0x35a14, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_6", 0x35a18, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_7", 0x35a1c, 0 },
+ { "MAC_PORT_MTIP_PCS_CTL", 0x35e00, 0 },
+ { "RESET", 15, 1 },
+ { "LPBK", 14, 1 },
+ { "SPEED_SEL1", 13, 1 },
+ { "LP_MODE", 11, 1 },
+ { "SPEED_SEL0", 6, 1 },
+ { "SPEED", 2, 4 },
+ { "MAC_PORT_MTIP_PCS_STATUS1", 0x35e04, 0 },
+ { "FaultDet", 7, 1 },
+ { "rx_link_status", 2, 1 },
+ { "LoPwrAbl", 1, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x35e08, 0 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x35e0c, 0 },
+ { "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x35e10, 0 },
+ { "100G", 8, 1 },
+ { "40G", 7, 1 },
+ { "10BASE_TL", 1, 1 },
+ { "10G", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x35e14, 0 },
+ { "TC", 6, 1 },
+ { "DTEXS", 5, 1 },
+ { "PHYXS", 4, 1 },
+ { "PCS", 3, 1 },
+ { "WIS", 2, 1 },
+ { "PMD_PMA", 1, 1 },
+ { "CL22", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x35e18, 0 },
+ { "VendDev2", 15, 1 },
+ { "VendDev1", 14, 1 },
+ { "CL22EXT", 13, 1 },
+ { "MAC_PORT_MTIP_PCS_CTL2", 0x35e1c, 0 },
+ { "MAC_PORT_MTIP_PCS_STATUS2", 0x35e20, 0 },
+ { "Device", 15, 1 },
+ { "TxFault", 7, 1 },
+ { "RxFault", 6, 1 },
+ { "100BASE_R", 5, 1 },
+ { "40GBASE_R", 4, 1 },
+ { "10GBASE_T", 3, 1 },
+ { "10GBASE_W", 2, 1 },
+ { "10GBASE_X", 1, 1 },
+ { "10GBASE_R", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_PKG_ID0", 0x35e38, 0 },
+ { "MAC_PORT_MTIP_PCS_PKG_ID1", 0x35e3c, 0 },
+ { "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x35e80, 0 },
+ { "RxLinkStatus", 12, 1 },
+ { "RESEREVED", 4, 8 },
+ { "10GPRBS9", 3, 1 },
+ { "10GPRBS31", 2, 1 },
+ { "HiBER", 1, 1 },
+ { "blocklock", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x35e84, 0 },
+ { "blocklockLL", 15, 1 },
+ { "HiBERLH", 14, 1 },
+ { "HiBERCount", 8, 6 },
+ { "ErrBlkCnt", 0, 8 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A", 0x35e88, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x35e8c, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x35e90, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x35e94, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B", 0x35e98, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x35e9c, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x35ea0, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x35ea4, 0 },
+ { "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x35ea8, 0 },
+ { "TXPRBS9", 6, 1 },
+ { "RXPRBS31", 5, 1 },
+ { "TXPRBS31", 4, 1 },
+ { "TxTestPatEn", 3, 1 },
+ { "RxTestPatEn", 2, 1 },
+ { "TestPatSel", 1, 1 },
+ { "DataPatSel", 0, 1 },
+ { "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x35eac, 0 },
+ { "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x35eb0, 0 },
+ { "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x35eb4, 0 },
+ { "HiCountPrsnt", 15, 1 },
+ { "BLOCK_CNT_HI", 0, 14 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x35ec8, 0 },
+ { "alignstatus", 12, 1 },
+ { "Lane7", 7, 1 },
+ { "Lane6", 6, 1 },
+ { "Lane5", 5, 1 },
+ { "Lane4", 4, 1 },
+ { "Lane3", 3, 1 },
+ { "Lane2", 2, 1 },
+ { "Lane1", 1, 1 },
+ { "Lane0", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x35ecc, 0 },
+ { "Lane19", 11, 1 },
+ { "Lane18", 10, 1 },
+ { "Lane17", 9, 1 },
+ { "Lane16", 8, 1 },
+ { "Lane15", 7, 1 },
+ { "Lane14", 6, 1 },
+ { "Lane13", 5, 1 },
+ { "Lane12", 4, 1 },
+ { "Lane11", 3, 1 },
+ { "Lane10", 2, 1 },
+ { "Lane9", 1, 1 },
+ { "Lane8", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x35ed0, 0 },
+ { "AMLOCK7", 7, 1 },
+ { "AMLOCK6", 6, 1 },
+ { "AMLOCK5", 5, 1 },
+ { "AMLOCK4", 4, 1 },
+ { "AMLOCK3", 3, 1 },
+ { "AMLOCK2", 2, 1 },
+ { "AMLOCK1", 1, 1 },
+ { "AMLOCK0", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x35ed4, 0 },
+ { "AMLOCK19", 11, 1 },
+ { "AMLOCK18", 10, 1 },
+ { "AMLOCK17", 9, 1 },
+ { "AMLOCK16", 8, 1 },
+ { "AMLOCK15", 7, 1 },
+ { "AMLOCK14", 6, 1 },
+ { "AMLOCK13", 5, 1 },
+ { "AMLOCK12", 4, 1 },
+ { "AMLOCK11", 3, 1 },
+ { "AMLOCK10", 2, 1 },
+ { "AMLOCK9", 1, 1 },
+ { "AMLOCK8", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x35f68, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x35f6c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x35f70, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x35f74, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x35f78, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x35f7c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x35f80, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x35f84, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x35f88, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x35f8c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x35f90, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x35f94, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x35f98, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x35f9c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x35fa0, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x35fa4, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x35fa8, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x35fac, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x35fb0, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x35fb4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x35fb8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x35fbc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x35fc0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x35fc4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x35fc8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x35fcc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x35fd0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x35fd4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x35fd8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x35fdc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x35fe0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x35fe4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x35fe8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x35fec, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x35ff0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x35ff4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x35ff8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x35ffc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x36000, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x36004, 0 },
+ { "MAC_PORT_BEAN_CTL", 0x36200, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS", 0x36204, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0", 0x36208, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1", 0x3620c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2", 0x36210, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0", 0x36214, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1", 0x36218, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2", 0x3621c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT", 0x36220, 0 },
+ { "MAC_PORT_BEAN_XNP_0", 0x36224, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1", 0x36228, 0 },
+ { "MAC_PORT_BEAN_XNP_2", 0x3622c, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0", 0x36230, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1", 0x36234, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2", 0x36238, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS", 0x3623c, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE1", 0x36240, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE1", 0x36244, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x36248, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3624c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x36250, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x36254, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x36258, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3625c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x36260, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE1", 0x36264, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE1", 0x36268, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE1", 0x3626c, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x36270, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x36274, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x36278, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3627c, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE2", 0x36280, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE2", 0x36284, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x36288, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3628c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x36290, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x36294, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x36298, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3629c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x362a0, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE2", 0x362a4, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE2", 0x362a8, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE2", 0x362ac, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x362b0, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x362b4, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x362b8, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x362bc, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE3", 0x362c0, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE3", 0x362c4, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x362c8, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x362cc, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x362d0, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x362d4, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x362d8, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x362dc, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x362e0, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE3", 0x362e4, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE3", 0x362e8, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE3", 0x362ec, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x362f0, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x362f4, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x362f8, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x362fc, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_FEC_KR_CONTROL", 0x36600, 0 },
+ { "enable_tr", 1, 1 },
+ { "restart_tr", 0, 1 },
+ { "MAC_PORT_FEC_KR_STATUS", 0x36604, 0 },
+ { "fecKRsigdet", 15, 1 },
+ { "train_fail", 3, 1 },
+ { "startup_status", 2, 1 },
+ { "frame_lock", 1, 1 },
+ { "rx_status", 0, 1 },
+ { "MAC_PORT_FEC_KR_LP_COEFF", 0x36608, 0 },
+ { "Preset", 13, 1 },
+ { "Initialize", 12, 1 },
+ { "CP1_UPD", 4, 2 },
+ { "C0_UPD", 2, 2 },
+ { "CN1_UPD", 0, 2 },
+ { "MAC_PORT_FEC_KR_LP_STAT", 0x3660c, 0 },
+ { "rx_ready", 15, 1 },
+ { "CP1_STAT", 4, 2 },
+ { "C0_STAT", 2, 2 },
+ { "CN1_STAT", 0, 2 },
+ { "MAC_PORT_FEC_KR_LD_COEFF", 0x36610, 0 },
+ { "Preset", 13, 1 },
+ { "Initialize", 12, 1 },
+ { "CP1_UPD", 4, 2 },
+ { "C0_UPD", 2, 2 },
+ { "CN1_UPD", 0, 2 },
+ { "MAC_PORT_FEC_KR_LD_STAT", 0x36614, 0 },
+ { "rx_ready", 15, 1 },
+ { "CP1_STAT", 4, 2 },
+ { "C0_STAT", 2, 2 },
+ { "CN1_STAT", 0, 2 },
+ { "MAC_PORT_FEC_ABILITY", 0x36618, 0 },
+ { "fec_ind_ability", 1, 1 },
+ { "ability", 0, 1 },
+ { "MAC_PORT_FEC_CONTROL", 0x3661c, 0 },
+ { "fec_en_err_ind", 1, 1 },
+ { "fec_en", 0, 1 },
+ { "MAC_PORT_FEC_STATUS", 0x36620, 0 },
+ { "FEC_LOCKED_100", 1, 1 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_FEC_CERR_CNT_0", 0x36624, 0 },
+ { "MAC_PORT_FEC_CERR_CNT_1", 0x36628, 0 },
+ { "MAC_PORT_FEC_NCERR_CNT_0", 0x3662c, 0 },
+ { "MAC_PORT_FEC_NCERR_CNT_1", 0x36630, 0 },
+ { "MAC_PORT_AE_RX_COEF_REQ", 0x36a00, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT", 0x36a04, 0 },
+ { "T5_AE0_RXSTAT_RDY", 15, 1 },
+ { "T5_AE0_RXSTAT_C2", 4, 2 },
+ { "T5_AE0_RXSTAT_C1", 2, 2 },
+ { "T5_AE0_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ", 0x36a08, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT", 0x36a0c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE", 0x36a10, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL", 0x36a14, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL", 0x36a18, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE", 0x36a1c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_1", 0x36a20, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_1", 0x36a24, 0 },
+ { "T5_AE1_RXSTAT_RDY", 15, 1 },
+ { "T5_AE1_RXSTAT_C2", 4, 2 },
+ { "T5_AE1_RXSTAT_C1", 2, 2 },
+ { "T5_AE1_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_1", 0x36a28, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_1", 0x36a2c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_1", 0x36a30, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_1", 0x36a34, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_1", 0x36a38, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_1", 0x36a3c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_2", 0x36a40, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_2", 0x36a44, 0 },
+ { "T5_AE2_RXSTAT_RDY", 15, 1 },
+ { "T5_AE2_RXSTAT_C2", 4, 2 },
+ { "T5_AE2_RXSTAT_C1", 2, 2 },
+ { "T5_AE2_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_2", 0x36a48, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_2", 0x36a4c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_2", 0x36a50, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_2", 0x36a54, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_2", 0x36a58, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_2", 0x36a5c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_3", 0x36a60, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_3", 0x36a64, 0 },
+ { "T5_AE3_RXSTAT_RDY", 15, 1 },
+ { "T5_AE3_RXSTAT_C2", 4, 2 },
+ { "T5_AE3_RXSTAT_C1", 2, 2 },
+ { "T5_AE3_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_3", 0x36a68, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_3", 0x36a6c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_3", 0x36a70, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_3", 0x36a74, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_3", 0x36a78, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_3", 0x36a7c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_TX_DIS", 0x36a80, 0 },
+ { "MAC_PORT_AE_KR_CTRL", 0x36a84, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET", 0x36a88, 0 },
+ { "MAC_PORT_AE_KR_STATUS", 0x36a8c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_1", 0x36a90, 0 },
+ { "MAC_PORT_AE_KR_CTRL_1", 0x36a94, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_1", 0x36a98, 0 },
+ { "MAC_PORT_AE_KR_STATUS_1", 0x36a9c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_2", 0x36aa0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_2", 0x36aa4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_2", 0x36aa8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_2", 0x36aac, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_3", 0x36ab0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_3", 0x36ab4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_3", 0x36ab8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_3", 0x36abc, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x36b00, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x36b04, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_0", 0x36b08, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x36b0c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_0", 0x36b10, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x36b20, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x36b24, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_1", 0x36b28, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x36b2c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_1", 0x36b30, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x36b40, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x36b44, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_2", 0x36b48, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x36b4c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_2", 0x36b50, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x36b60, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x36b64, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_3", 0x36b68, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x36b6c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_3", 0x36b70, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_ANALOG_TEST_MUX", 0x37814, 0 },
+ { "MAC_PORT_BANDGAP_CONTROL", 0x3782c, 0 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x37880, 0 },
+ { "RCCTL1", 5, 1 },
+ { "RCCTL0", 4, 1 },
+ { "RCAMP1", 3, 1 },
+ { "RCAMP0", 2, 1 },
+ { "RCAMPEN", 1, 1 },
+ { "RCRST", 0, 1 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x37884, 0 },
+ { "RCERR", 1, 1 },
+ { "RCCOMP", 0, 1 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x37888, 0 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3788c, 0 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_6", 0x378e8, 0 },
+ { "LBIST", 7, 1 },
+ { "LOGICTEST", 6, 1 },
+ { "MAVDHI", 5, 1 },
+ { "AUXEN", 4, 1 },
+ { "JTAGMD", 3, 1 },
+ { "RXACMODE", 2, 1 },
+ { "HSSACJPC", 1, 1 },
+ { "HSSACJAC", 0, 1 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_5", 0x378ec, 0 },
+ { "REFVALIDD", 6, 1 },
+ { "REFVALIDC", 5, 1 },
+ { "REFVALIDB", 4, 1 },
+ { "REFVALIDA", 3, 1 },
+ { "REFSELRESET", 2, 1 },
+ { "SOFTRESET", 1, 1 },
+ { "MACROTEST", 0, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x37b00, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x37b04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x37b08, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x37b0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x37b10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x37b28, 0 },
+ { "MAC_PORT_PLLA_PCLK_CONTROL", 0x37b3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x37b40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x37b44, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x37b48, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x37b4c, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x37b50, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x37bf0, 0 },
+ { "VBST", 1, 3 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x37bf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "PDWNP", 2, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x37bf8, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x37bfc, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x37c00, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x37c04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x37c08, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x37c0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x37c10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x37c28, 0 },
+ { "MAC_PORT_PLLB_PCLK_CONTROL", 0x37c3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x37c40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x37c44, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x37c48, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x37c4c, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x37c50, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x37cf0, 0 },
+ { "VBST", 1, 3 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x37cf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "PDWNP", 2, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x37cf8, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x37cfc, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x37000, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x37004, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x37008, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3700c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37010, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37014, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37018, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3701c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x37020, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x37024, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x37028, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x37030, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x37034, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37038, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3703c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37040, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37044, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37048, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37060, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37064, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37068, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37070, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37074, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37078, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3707c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37080, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37084, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37088, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3708c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x37090, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x37094, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x37098, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3709c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x370f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x370f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x370f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x370fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x37100, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x37104, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x37108, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3710c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37110, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37114, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37118, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3711c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x37120, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x37124, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x37128, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x37130, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x37134, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37138, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3713c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37140, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37144, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37148, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37160, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37164, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37168, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37170, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37174, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37178, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3717c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37180, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37184, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37188, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3718c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x37190, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x37194, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x37198, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3719c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x371f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x371f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x371f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x371fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x37400, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x37404, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x37408, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3740c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37410, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37414, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37418, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3741c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x37420, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x37424, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x37428, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x37430, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x37434, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37438, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3743c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37440, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37444, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37448, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37460, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37464, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37468, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37470, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37474, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37478, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3747c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37480, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37484, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37488, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3748c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x37490, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x37494, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x37498, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3749c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x374f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x374f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x374f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x374fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x37500, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x37504, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x37508, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3750c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37510, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37514, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37518, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3751c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x37520, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x37524, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x37528, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x37530, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x37534, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37538, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3753c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37540, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37544, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37548, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37560, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37564, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37568, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37570, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37574, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37578, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3757c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37580, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37584, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37588, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3758c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x37590, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x37594, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x37598, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3759c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x375f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x375f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x375f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x375fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x37900, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x37904, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x37908, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3790c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37910, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37914, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37918, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3791c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x37920, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x37924, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x37928, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x37930, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x37934, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37938, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3793c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37940, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37944, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37948, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37960, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37964, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37968, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37970, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37974, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37978, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3797c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37980, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37984, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37988, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3798c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x37990, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x37994, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x37998, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3799c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x379f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x379f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x379f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x379fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x37200, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x37204, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x37208, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3720c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x37210, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x37214, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37218, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3721c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x37220, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x37224, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x37228, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3722c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x37230, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x37234, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x37238, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x37240, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x37248, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3724c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x37250, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3725c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37260, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37264, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37270, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x37274, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x37278, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3727c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x37280, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x37284, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x37288, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3728c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x37290, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x37294, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x37298, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3729c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x372a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x372a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x372a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x372ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x372b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x372b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x372b8, 0 },
+ { "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x372c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKA_DFE_H1", 0x372c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H2", 0x372c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_H3", 0x372cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H4", 0x372d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H5", 0x372d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x372d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x372dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x372e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H12", 0x372e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x372f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x372fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x37300, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x37304, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x37308, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3730c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x37310, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x37314, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37318, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3731c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x37320, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x37324, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x37328, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3732c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x37330, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x37334, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x37338, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x37340, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x37348, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3734c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x37350, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3735c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37360, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37364, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37370, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x37374, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x37378, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3737c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x37380, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x37384, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x37388, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3738c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x37390, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x37394, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x37398, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3739c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x373a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x373a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x373a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x373ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x373b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x373b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x373b8, 0 },
+ { "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x373c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKB_DFE_H1", 0x373c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H2", 0x373c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_H3", 0x373cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H4", 0x373d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H5", 0x373d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x373d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x373dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x373e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H12", 0x373e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x373f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x373fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x37600, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x37604, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x37608, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3760c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x37610, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x37614, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37618, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3761c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x37620, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x37624, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x37628, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3762c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x37630, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x37634, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x37638, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x37640, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x37648, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3764c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x37650, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3765c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37660, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37664, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37670, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x37674, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x37678, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3767c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x37680, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x37684, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x37688, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3768c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x37690, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x37694, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x37698, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3769c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x376a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x376a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x376a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x376ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x376b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x376b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x376b8, 0 },
+ { "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x376c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKC_DFE_H1", 0x376c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H2", 0x376c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_H3", 0x376cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H4", 0x376d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H5", 0x376d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x376d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x376dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x376e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H12", 0x376e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x376f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x376fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x37700, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x37704, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x37708, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3770c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x37710, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x37714, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37718, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3771c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x37720, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x37724, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x37728, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3772c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x37730, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x37734, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x37738, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x37740, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x37748, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3774c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x37750, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3775c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37760, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37764, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37770, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x37774, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x37778, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3777c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x37780, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x37784, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x37788, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3778c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x37790, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x37794, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x37798, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3779c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x377a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x377a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x377a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x377ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x377b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x377b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x377b8, 0 },
+ { "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x377c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKD_DFE_H1", 0x377c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H2", 0x377c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_H3", 0x377cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H4", 0x377d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H5", 0x377d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x377d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x377dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x377e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H12", 0x377e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x377f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x377fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x37a00, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x37a04, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x37a08, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x37a0c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x37a10, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x37a14, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37a18, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x37a1c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x37a20, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x37a24, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x37a28, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x37a2c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x37a30, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x37a34, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x37a38, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x37a40, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x37a48, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x37a4c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x37a50, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x37a5c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37a60, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37a64, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37a70, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x37a74, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x37a78, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x37a7c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x37a80, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x37a84, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x37a88, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x37a8c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x37a90, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x37a94, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x37a98, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x37a9c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x37aa0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x37aa4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x37aa8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x37aac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x37ab0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x37ab4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x37ab8, 0 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x37ac0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x37ac4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x37ac8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x37acc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x37ad0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x37ad4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x37ad8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x37adc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x37ae0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x37ae4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x37af8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x37afc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_CFG", 0x38800, 0 },
+ { "MAC_Clk_Sel", 29, 3 },
+ { "SinkTx", 27, 1 },
+ { "SinkTxOnLinkDown", 26, 1 },
+ { "LoopNoFwd", 24, 1 },
+ { "Smux_Rx_Loop", 19, 1 },
+ { "Rx_Lane_Swap", 18, 1 },
+ { "Tx_Lane_Swap", 17, 1 },
+ { "Signal_Det", 14, 1 },
+ { "SmuxTxSel", 9, 1 },
+ { "SmuxRxSel", 8, 1 },
+ { "PortSpeed", 4, 2 },
+ { "Rx_Byte_Swap", 3, 1 },
+ { "Tx_Byte_Swap", 2, 1 },
+ { "Port_Sel", 0, 1 },
+ { "MAC_PORT_RESET_CTRL", 0x38804, 0 },
+ { "TWGDSK_HSSC16B", 31, 1 },
+ { "EEE_RESET", 30, 1 },
+ { "PTP_TIMER", 29, 1 },
+ { "MtipRefReset", 28, 1 },
+ { "MtipTxffReset", 27, 1 },
+ { "MtipRxffReset", 26, 1 },
+ { "MtipRegReset", 25, 1 },
+ { "AEC3Reset", 23, 1 },
+ { "AEC2Reset", 22, 1 },
+ { "AEC1Reset", 21, 1 },
+ { "AEC0Reset", 20, 1 },
+ { "AET3Reset", 19, 1 },
+ { "AET2Reset", 18, 1 },
+ { "AET1Reset", 17, 1 },
+ { "AET0Reset", 16, 1 },
+ { "TXIF_Reset", 12, 1 },
+ { "RXIF_Reset", 11, 1 },
+ { "AuxExt_Reset", 10, 1 },
+ { "MtipSd3TxRst", 9, 1 },
+ { "MtipSd2TxRst", 8, 1 },
+ { "MtipSd1TxRst", 7, 1 },
+ { "MtipSd0TxRst", 6, 1 },
+ { "MtipSd3RxRst", 5, 1 },
+ { "MtipSd2RxRst", 4, 1 },
+ { "MtipSd1RxRst", 3, 1 },
+ { "WOL_Reset", 2, 1 },
+ { "MtipSd0RxRst", 1, 1 },
+ { "HSS_Reset", 0, 1 },
+ { "MAC_PORT_LED_CFG", 0x38808, 0 },
+ { "Led1_Cfg", 5, 3 },
+ { "Led1_Polarity_Inv", 4, 1 },
+ { "Led0_Cfg", 1, 3 },
+ { "Led0_Polarity_Inv", 0, 1 },
+ { "MAC_PORT_LED_COUNTHI", 0x3880c, 0 },
+ { "MAC_PORT_LED_COUNTLO", 0x38810, 0 },
+ { "MAC_PORT_CFG3", 0x38814, 0 },
+ { "FPGA_PTP_PORT", 26, 2 },
+ { "FCSDisCtrl", 25, 1 },
+ { "SigDetCtrl", 24, 1 },
+ { "tx_lane", 23, 1 },
+ { "rx_lane", 22, 1 },
+ { "se_clr", 21, 1 },
+ { "an_ena", 17, 4 },
+ { "sd_rx_clk_ena", 13, 4 },
+ { "sd_tx_clk_ena", 9, 4 },
+ { "SGMIISEL", 8, 1 },
+ { "HSSPLLSEL", 4, 4 },
+ { "HSSC16C20SEL", 0, 4 },
+ { "MAC_PORT_CFG2", 0x38818, 0 },
+ { "Rx_Polarity_Inv", 28, 4 },
+ { "Tx_Polarity_Inv", 24, 4 },
+ { "InstanceNum", 22, 2 },
+ { "StopOnPerr", 21, 1 },
+ { "PatEn", 18, 1 },
+ { "MagicEn", 17, 1 },
+ { "T5_AEC_PMA_TX_READY", 4, 4 },
+ { "T5_AEC_PMA_RX_READY", 0, 4 },
+ { "MAC_PORT_PKT_COUNT", 0x3881c, 0 },
+ { "tx_sop_count", 24, 8 },
+ { "tx_eop_count", 16, 8 },
+ { "rx_sop_count", 8, 8 },
+ { "rx_eop_count", 0, 8 },
+ { "MAC_PORT_CFG4", 0x38820, 0 },
+ { "AEC3_RX_WIDTH", 14, 2 },
+ { "AEC2_RX_WIDTH", 12, 2 },
+ { "AEC1_RX_WIDTH", 10, 2 },
+ { "AEC0_RX_WIDTH", 8, 2 },
+ { "AEC3_TX_WIDTH", 6, 2 },
+ { "AEC2_TX_WIDTH", 4, 2 },
+ { "AEC1_TX_WIDTH", 2, 2 },
+ { "AEC0_TX_WIDTH", 0, 2 },
+ { "MAC_PORT_MAGIC_MACID_LO", 0x38824, 0 },
+ { "MAC_PORT_MAGIC_MACID_HI", 0x38828, 0 },
+ { "MAC_PORT_LINK_STATUS", 0x38834, 0 },
+ { "an_done", 6, 1 },
+ { "align_done", 5, 1 },
+ { "block_lock", 4, 1 },
+ { "remflt", 3, 1 },
+ { "locflt", 2, 1 },
+ { "linkup", 1, 1 },
+ { "linkdn", 0, 1 },
+ { "MAC_PORT_EPIO_DATA0", 0x388c0, 0 },
+ { "MAC_PORT_EPIO_DATA1", 0x388c4, 0 },
+ { "MAC_PORT_EPIO_DATA2", 0x388c8, 0 },
+ { "MAC_PORT_EPIO_DATA3", 0x388cc, 0 },
+ { "MAC_PORT_EPIO_OP", 0x388d0, 0 },
+ { "Busy", 31, 1 },
+ { "Write", 8, 1 },
+ { "Address", 0, 8 },
+ { "MAC_PORT_WOL_STATUS", 0x388d4, 0 },
+ { "MagicDetected", 31, 1 },
+ { "PatDetected", 30, 1 },
+ { "ClearMagic", 4, 1 },
+ { "ClearMatch", 3, 1 },
+ { "MatchedFilter", 0, 3 },
+ { "MAC_PORT_INT_EN", 0x388d8, 0 },
+ { "tx_ts_avail", 29, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_INT_CAUSE", 0x388dc, 0 },
+ { "tx_ts_avail", 29, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_PERR_INT_EN", 0x388e0, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_INT_CAUSE", 0x388e4, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_ENABLE", 0x388e8, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_INJECT", 0x388ec, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "MAC_PORT_HSS_CFG0", 0x388f0, 0 },
+ { "TXDTS", 31, 1 },
+ { "TXCTS", 30, 1 },
+ { "TXBTS", 29, 1 },
+ { "TXATS", 28, 1 },
+ { "TXDOBS", 27, 1 },
+ { "TXCOBS", 26, 1 },
+ { "TXBOBS", 25, 1 },
+ { "TXAOBS", 24, 1 },
+ { "HSSREFCLKVALIDA", 20, 1 },
+ { "HSSREFCLKVALIDB", 19, 1 },
+ { "HSSRESYNCA", 18, 1 },
+ { "HSSAVDHI", 17, 1 },
+ { "HSSRESYNCB", 16, 1 },
+ { "HSSRECCALA", 15, 1 },
+ { "HSSRXACMODE", 14, 1 },
+ { "HSSRECCALB", 13, 1 },
+ { "HSSPLLBYPA", 12, 1 },
+ { "HSSPLLBYPB", 11, 1 },
+ { "HSSPDWNPLLA", 10, 1 },
+ { "HSSPDWNPLLB", 9, 1 },
+ { "HSSVCOSELA", 8, 1 },
+ { "HSSVCOSELB", 7, 1 },
+ { "HSSCALCOMP", 6, 1 },
+ { "HSSCALENAB", 5, 1 },
+ { "HSSEXTC16SEL", 4, 1 },
+ { "MAC_PORT_HSS_CFG1", 0x388f4, 0 },
+ { "RXACONFIGSEL", 30, 2 },
+ { "RXAQUIET", 29, 1 },
+ { "RXAREFRESH", 28, 1 },
+ { "RXBCONFIGSEL", 26, 2 },
+ { "RXBQUIET", 25, 1 },
+ { "RXBREFRESH", 24, 1 },
+ { "RXCCONFIGSEL", 22, 2 },
+ { "RXCQUIET", 21, 1 },
+ { "RXCREFRESH", 20, 1 },
+ { "RXDCONFIGSEL", 18, 2 },
+ { "RXDQUIET", 17, 1 },
+ { "RXDREFRESH", 16, 1 },
+ { "TXACONFIGSEL", 14, 2 },
+ { "TXAQUIET", 13, 1 },
+ { "TXAREFRESH", 12, 1 },
+ { "TXBCONFIGSEL", 10, 2 },
+ { "TXBQUIET", 9, 1 },
+ { "TXBREFRESH", 8, 1 },
+ { "TXCCONFIGSEL", 6, 2 },
+ { "TXCQUIET", 5, 1 },
+ { "TXCREFRESH", 4, 1 },
+ { "TXDCONFIGSEL", 2, 2 },
+ { "TXDQUIET", 1, 1 },
+ { "TXDREFRESH", 0, 1 },
+ { "MAC_PORT_HSS_CFG2", 0x388f8, 0 },
+ { "RXAASSTCLK", 31, 1 },
+ { "T5RXAPRBSRST", 30, 1 },
+ { "RXBASSTCLK", 29, 1 },
+ { "T5RXBPRBSRST", 28, 1 },
+ { "RXCASSTCLK", 27, 1 },
+ { "T5RXCPRBSRST", 26, 1 },
+ { "RXDASSTCLK", 25, 1 },
+ { "T5RXDPRBSRST", 24, 1 },
+ { "RXDDATASYNC", 23, 1 },
+ { "RXCDATASYNC", 22, 1 },
+ { "RXBDATASYNC", 21, 1 },
+ { "RXADATASYNC", 20, 1 },
+ { "RXDEARLYIN", 19, 1 },
+ { "RXDLATEIN", 18, 1 },
+ { "RXDPHSLOCK", 17, 1 },
+ { "RXDPHSDNIN", 16, 1 },
+ { "RXDPHSUPIN", 15, 1 },
+ { "RXCEARLYIN", 14, 1 },
+ { "RXCLATEIN", 13, 1 },
+ { "RXCPHSLOCK", 12, 1 },
+ { "RXCPHSDNIN", 11, 1 },
+ { "RXCPHSUPIN", 10, 1 },
+ { "RXBEARLYIN", 9, 1 },
+ { "RXBLATEIN", 8, 1 },
+ { "RXBPHSLOCK", 7, 1 },
+ { "RXBPHSDNIN", 6, 1 },
+ { "RXBPHSUPIN", 5, 1 },
+ { "RXAEARLYIN", 4, 1 },
+ { "RXALATEIN", 3, 1 },
+ { "RXAPHSLOCK", 2, 1 },
+ { "RXAPHSDNIN", 1, 1 },
+ { "RXAPHSUPIN", 0, 1 },
+ { "MAC_PORT_HSS_CFG3", 0x388fc, 0 },
+ { "HSSCALSSTN", 25, 3 },
+ { "HSSCALSSTP", 22, 3 },
+ { "HSSVBOOSTDIVB", 19, 3 },
+ { "HSSVBOOSTDIVA", 16, 3 },
+ { "HSSPLLCONFIGB", 8, 8 },
+ { "HSSPLLCONFIGA", 0, 8 },
+ { "MAC_PORT_HSS_CFG4", 0x38900, 0 },
+ { "HSSDIVSELA", 9, 9 },
+ { "HSSDIVSELB", 0, 9 },
+ { "MAC_PORT_HSS_STATUS", 0x38904, 0 },
+ { "RXDPRBSSYNC", 15, 1 },
+ { "RXCPRBSSYNC", 14, 1 },
+ { "RXBPRBSSYNC", 13, 1 },
+ { "RXAPRBSSYNC", 12, 1 },
+ { "RXDPRBSERR", 11, 1 },
+ { "RXCPRBSERR", 10, 1 },
+ { "RXBPRBSERR", 9, 1 },
+ { "RXAPRBSERR", 8, 1 },
+ { "RXDSIGDET", 7, 1 },
+ { "RXCSIGDET", 6, 1 },
+ { "RXBSIGDET", 5, 1 },
+ { "RXASIGDET", 4, 1 },
+ { "HSSPLLLOCKB", 3, 1 },
+ { "HSSPLLLOCKA", 2, 1 },
+ { "HSSPRTREADYB", 1, 1 },
+ { "HSSPRTREADYA", 0, 1 },
+ { "MAC_PORT_HSS_EEE_STATUS", 0x38908, 0 },
+ { "RXAQUIET_STATUS", 15, 1 },
+ { "RXAREFRESH_STATUS", 14, 1 },
+ { "RXBQUIET_STATUS", 13, 1 },
+ { "RXBREFRESH_STATUS", 12, 1 },
+ { "RXCQUIET_STATUS", 11, 1 },
+ { "RXCREFRESH_STATUS", 10, 1 },
+ { "RXDQUIET_STATUS", 9, 1 },
+ { "RXDREFRESH_STATUS", 8, 1 },
+ { "TXAQUIET_STATUS", 7, 1 },
+ { "TXAREFRESH_STATUS", 6, 1 },
+ { "TXBQUIET_STATUS", 5, 1 },
+ { "TXBREFRESH_STATUS", 4, 1 },
+ { "TXCQUIET_STATUS", 3, 1 },
+ { "TXCREFRESH_STATUS", 2, 1 },
+ { "TXDQUIET_STATUS", 1, 1 },
+ { "TXDREFRESH_STATUS", 0, 1 },
+ { "MAC_PORT_HSS_SIGDET_STATUS", 0x3890c, 0 },
+ { "MAC_PORT_HSS_PL_CTL", 0x38910, 0 },
+ { "TOV", 16, 8 },
+ { "TSU", 8, 8 },
+ { "IPW", 0, 8 },
+ { "MAC_PORT_RUNT_FRAME", 0x38914, 0 },
+ { "runtclear", 16, 1 },
+ { "runt", 0, 16 },
+ { "MAC_PORT_EEE_STATUS", 0x38918, 0 },
+ { "eee_tx_10g_state", 10, 2 },
+ { "eee_rx_10g_state", 8, 2 },
+ { "eee_tx_1g_state", 6, 2 },
+ { "eee_rx_1g_state", 4, 2 },
+ { "pma_rx_refresh", 3, 1 },
+ { "pma_rx_quiet", 2, 1 },
+ { "pma_tx_refresh", 1, 1 },
+ { "pma_tx_quiet", 0, 1 },
+ { "MAC_PORT_CGEN", 0x3891c, 0 },
+ { "CGEN", 8, 1 },
+ { "sd7_CGEN", 7, 1 },
+ { "sd6_CGEN", 6, 1 },
+ { "sd5_CGEN", 5, 1 },
+ { "sd4_CGEN", 4, 1 },
+ { "sd3_CGEN", 3, 1 },
+ { "sd2_CGEN", 2, 1 },
+ { "sd1_CGEN", 1, 1 },
+ { "sd0_CGEN", 0, 1 },
+ { "MAC_PORT_CGEN_MTIP", 0x38920, 0 },
+ { "MACSEG5_CGEN", 11, 1 },
+ { "PCSSEG5_CGEN", 10, 1 },
+ { "MACSEG4_CGEN", 9, 1 },
+ { "PCSSEG4_CGEN", 8, 1 },
+ { "MACSEG3_CGEN", 7, 1 },
+ { "PCSSEG3_CGEN", 6, 1 },
+ { "MACSEG2_CGEN", 5, 1 },
+ { "PCSSEG2_CGEN", 4, 1 },
+ { "MACSEG1_CGEN", 3, 1 },
+ { "PCSSEG1_CGEN", 2, 1 },
+ { "MACSEG0_CGEN", 1, 1 },
+ { "PCSSEG0_CGEN", 0, 1 },
+ { "MAC_PORT_TX_TS_ID", 0x38924, 0 },
+ { "MAC_PORT_TX_TS_VAL_LO", 0x38928, 0 },
+ { "MAC_PORT_TX_TS_VAL_HI", 0x3892c, 0 },
+ { "MAC_PORT_EEE_CTL", 0x38930, 0 },
+ { "EEE_CTRL", 2, 30 },
+ { "TICK_START", 1, 1 },
+ { "En", 0, 1 },
+ { "MAC_PORT_EEE_TX_CTL", 0x38934, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_ACTIVE", 3, 1 },
+ { "LPI_TXHOLD", 2, 1 },
+ { "LPI_REQ", 1, 1 },
+ { "EEE_TX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_RX_CTL", 0x38938, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_IND", 1, 1 },
+ { "EEE_RX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3893c, 0 },
+ { "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x38940, 0 },
+ { "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x38944, 0 },
+ { "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x38948, 0 },
+ { "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3894c, 0 },
+ { "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x38950, 0 },
+ { "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x38954, 0 },
+ { "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x38958, 0 },
+ { "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3895c, 0 },
+ { "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x38960, 0 },
+ { "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x38964, 0 },
+ { "MAC_PORT_EEE_WF_COUNT", 0x38968, 0 },
+ { "wake_cnt_clr", 16, 1 },
+ { "wake_cnt", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_RD0_LO", 0x3896c, 0 },
+ { "MAC_PORT_PTP_TIMER_RD0_HI", 0x38970, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_LO", 0x38974, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_HI", 0x38978, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_LO", 0x3897c, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_HI", 0x38980, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_0", 0x38984, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_1", 0x38988, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3898c, 0 },
+ { "MAC_PORT_PTP_SUM_LO", 0x38990, 0 },
+ { "MAC_PORT_PTP_SUM_HI", 0x38994, 0 },
+ { "MAC_PORT_PTP_TIMER_INCR0", 0x38998, 0 },
+ { "Y", 16, 16 },
+ { "X", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_INCR1", 0x3899c, 0 },
+ { "Y_TICK", 16, 16 },
+ { "X_TICK", 0, 16 },
+ { "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x389a0, 0 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x389a4, 0 },
+ { "B", 16, 16 },
+ { "A", 0, 16 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x389a8, 0 },
+ { "MAC_PORT_PTP_CFG", 0x389ac, 0 },
+ { "FRZ", 18, 1 },
+ { "OFFSER_ADJUST_SIGN", 17, 1 },
+ { "ADD_OFFSET", 16, 1 },
+ { "CYCLE1", 8, 8 },
+ { "Q", 0, 8 },
+ { "MAC_PORT_MTIP_REVISION", 0x38a00, 0 },
+ { "CUSTREV", 16, 16 },
+ { "VER", 8, 8 },
+ { "REV", 0, 8 },
+ { "MAC_PORT_MTIP_SCRATCH", 0x38a04, 0 },
+ { "MAC_PORT_MTIP_COMMAND_CONFIG", 0x38a08, 0 },
+ { "TX_FLUSH", 22, 1 },
+ { "RX_SFD_ANY", 21, 1 },
+ { "PAUSE_PFC_COMP", 20, 1 },
+ { "PFC_MODE", 19, 1 },
+ { "RS_COL_CNT_EXT", 18, 1 },
+ { "NO_LGTH_CHECK", 17, 1 },
+ { "SEND_IDLE", 16, 1 },
+ { "PHY_TXENA", 15, 1 },
+ { "RX_ERR_DISC", 14, 1 },
+ { "CMD_FRAME_ENA", 13, 1 },
+ { "SW_RESET", 12, 1 },
+ { "TX_PAD_EN", 11, 1 },
+ { "LOOPBACK_EN", 10, 1 },
+ { "TX_ADDR_INS", 9, 1 },
+ { "PAUSE_IGNORE", 8, 1 },
+ { "PAUSE_FWD", 7, 1 },
+ { "CRC_FWD", 6, 1 },
+ { "PAD_EN", 5, 1 },
+ { "PROMIS_EN", 4, 1 },
+ { "WAN_MODE", 3, 1 },
+ { "RX_ENA", 1, 1 },
+ { "TX_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_MAC_ADDR_0", 0x38a0c, 0 },
+ { "MAC_PORT_MTIP_MAC_ADDR_1", 0x38a10, 0 },
+ { "MAC_PORT_MTIP_FRM_LENGTH", 0x38a14, 0 },
+ { "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x38a1c, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x38a20, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x38a24, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x38a28, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x38a2c, 0 },
+ { "ENABLE", 8, 1 },
+ { "ADDR", 0, 6 },
+ { "MAC_PORT_MTIP_MAC_STATUS", 0x38a40, 0 },
+ { "TS_AVAIL", 3, 1 },
+ { "PHY_LOS", 2, 1 },
+ { "RX_REM_FAULT", 1, 1 },
+ { "RX_LOC_FAULT", 0, 1 },
+ { "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x38a44, 0 },
+ { "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x38a48, 0 },
+ { "MAC_PORT_MTIP_INIT_CREDIT", 0x38a4c, 0 },
+ { "MAC_PORT_MTIP_CURRENT_CREDIT", 0x38a50, 0 },
+ { "MAC_PORT_RX_PAUSE_STATUS", 0x38a74, 0 },
+ { "MAC_PORT_MTIP_TS_TIMESTAMP", 0x38a7c, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x38a80, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x38a84, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOK", 0x38a88, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x38a8c, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x38a90, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x38a94, 0 },
+ { "MAC_PORT_AALIGNMENTERRORS", 0x38a98, 0 },
+ { "MAC_PORT_AALIGNMENTERRORSHI", 0x38a9c, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x38aa0, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x38aa4, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x38aa8, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x38aac, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORS", 0x38ab0, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x38ab4, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORS", 0x38ab8, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORSHI", 0x38abc, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOK", 0x38ac0, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOKHI", 0x38ac4, 0 },
+ { "MAC_PORT_VLANRECEIVEDOK", 0x38ac8, 0 },
+ { "MAC_PORT_VLANRECEIVEDOKHI", 0x38acc, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x38ad0, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x38ad4, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOK", 0x38ad8, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x38adc, 0 },
+ { "MAC_PORT_IFINUCASTPKTS", 0x38ae0, 0 },
+ { "MAC_PORT_IFINUCASTPKTSHI", 0x38ae4, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTS", 0x38ae8, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTSHI", 0x38aec, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTS", 0x38af0, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTSHI", 0x38af4, 0 },
+ { "MAC_PORT_IFOUTERRORS", 0x38af8, 0 },
+ { "MAC_PORT_IFOUTERRORSHI", 0x38afc, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTS", 0x38b08, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTSHI", 0x38b0c, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTS", 0x38b10, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x38b14, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTS", 0x38b18, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x38b1c, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTS", 0x38b20, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x38b24, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETS", 0x38b28, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETSHI", 0x38b2c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS", 0x38b30, 0 },
+ { "MAC_PORT_ETHERSTATSPKTSHI", 0x38b34, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x38b38, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x38b3c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x38b40, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x38b44, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x38b48, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x38b4c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x38b50, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x38b54, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x38b58, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x38b5c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x38b60, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x38b64, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x38b68, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x38b6c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x38b70, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x38b74, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x38b78, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x38b7c, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERS", 0x38b80, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERSHI", 0x38b84, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTS", 0x38b88, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x38b8c, 0 },
+ { "MAC_PORT_IFINERRORS", 0x38b90, 0 },
+ { "MAC_PORT_IFINERRORSHI", 0x38b94, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x38b98, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x38b9c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x38ba0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x38ba4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x38ba8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x38bac, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x38bb0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x38bb4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x38bb8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x38bbc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x38bc0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x38bc4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x38bc8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x38bcc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x38bd0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x38bd4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x38bd8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x38bdc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x38be0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x38be4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x38be8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x38bec, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x38bf0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x38bf4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x38bf8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x38bfc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x38c00, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x38c04, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x38c08, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x38c0c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x38c10, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x38c14, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x38c18, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x38c1c, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x38c20, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x38c24, 0 },
+ { "MAC_PORT_MTIP_SGMII_CONTROL", 0x38d00, 0 },
+ { "Reset", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "sppedsel1", 13, 1 },
+ { "AN_EN", 12, 1 },
+ { "PWRDWN", 11, 1 },
+ { "Isolate", 10, 1 },
+ { "AN_RESTART", 9, 1 },
+ { "DPLX", 8, 1 },
+ { "CollisionTest", 7, 1 },
+ { "SpeedSel0", 6, 1 },
+ { "MAC_PORT_MTIP_SGMII_STATUS", 0x38d04, 0 },
+ { "100BaseT4", 15, 1 },
+ { "100BaseXFullDplx", 14, 1 },
+ { "100BaseXHalfDplx", 13, 1 },
+ { "10MbpsFullDplx", 12, 1 },
+ { "10MbpsHalfDplx", 11, 1 },
+ { "100BaseT2FullDplx", 10, 1 },
+ { "100BaseT2HalfDplx", 9, 1 },
+ { "ExtdStatus", 8, 1 },
+ { "AN_Complete", 5, 1 },
+ { "SGMII_REM_FAULT", 4, 1 },
+ { "AN_Ability", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "JabberDetect", 1, 1 },
+ { "ExtdCapability", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x38d08, 0 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x38d0c, 0 },
+ { "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x38d10, 0 },
+ { "NP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "RF2", 13, 1 },
+ { "RF1", 12, 1 },
+ { "PS2", 8, 1 },
+ { "PS1", 7, 1 },
+ { "HD", 6, 1 },
+ { "FD", 5, 1 },
+ { "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x38d14, 0 },
+ { "CuLinkStatus", 15, 1 },
+ { "ACK", 14, 1 },
+ { "CuDplxStatus", 12, 1 },
+ { "CuSpeed", 10, 2 },
+ { "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x38d18, 0 },
+ { "PgRcvd", 1, 1 },
+ { "RealTimePgRcvd", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x38d1c, 0 },
+ { "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x38d20, 0 },
+ { "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x38d3c, 0 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x38d48, 0 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x38d4c, 0 },
+ { "MAC_PORT_MTIP_SGMII_IF_MODE", 0x38d50, 0 },
+ { "SGMII_PCS_ENABLE", 5, 1 },
+ { "SGMII_HDUPLEX", 4, 1 },
+ { "SGMII_SPEED", 2, 2 },
+ { "USE_SGMII_AN", 1, 1 },
+ { "SGMII_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_ACT_CTL_SEG", 0x39200, 0 },
+ { "MAC_PORT_MTIP_MODE_CTL_SEG", 0x39204, 0 },
+ { "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x39208, 0 },
+ { "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3920c, 0 },
+ { "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x39220, 0 },
+ { "MAC_PORT_MTIP_VL_INTVL", 0x39240, 0 },
+ { "VL_INTVL", 1, 1 },
+ { "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x39600, 0 },
+ { "CLK_DIV", 7, 9 },
+ { "CL45_EN", 6, 1 },
+ { "disable_preamble", 5, 1 },
+ { "mdio_hold_time", 2, 3 },
+ { "mdio_read_err", 1, 1 },
+ { "mdio_busy", 0, 1 },
+ { "MAC_PORT_MTIP_MDIO_COMMAND", 0x39604, 0 },
+ { "read", 15, 1 },
+ { "read_incr", 14, 1 },
+ { "port_addr", 5, 5 },
+ { "dev_addr", 0, 5 },
+ { "MAC_PORT_MTIP_MDIO_DATA", 0x39608, 0 },
+ { "readbusy", 31, 1 },
+ { "data_word", 0, 16 },
+ { "MAC_PORT_MTIP_MDIO_REGADDR", 0x3960c, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_0", 0x39a00, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_1", 0x39a04, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_2", 0x39a08, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_3", 0x39a0c, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_4", 0x39a10, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_5", 0x39a14, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_6", 0x39a18, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_7", 0x39a1c, 0 },
+ { "MAC_PORT_MTIP_PCS_CTL", 0x39e00, 0 },
+ { "RESET", 15, 1 },
+ { "LPBK", 14, 1 },
+ { "SPEED_SEL1", 13, 1 },
+ { "LP_MODE", 11, 1 },
+ { "SPEED_SEL0", 6, 1 },
+ { "SPEED", 2, 4 },
+ { "MAC_PORT_MTIP_PCS_STATUS1", 0x39e04, 0 },
+ { "FaultDet", 7, 1 },
+ { "rx_link_status", 2, 1 },
+ { "LoPwrAbl", 1, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x39e08, 0 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x39e0c, 0 },
+ { "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x39e10, 0 },
+ { "100G", 8, 1 },
+ { "40G", 7, 1 },
+ { "10BASE_TL", 1, 1 },
+ { "10G", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x39e14, 0 },
+ { "TC", 6, 1 },
+ { "DTEXS", 5, 1 },
+ { "PHYXS", 4, 1 },
+ { "PCS", 3, 1 },
+ { "WIS", 2, 1 },
+ { "PMD_PMA", 1, 1 },
+ { "CL22", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x39e18, 0 },
+ { "VendDev2", 15, 1 },
+ { "VendDev1", 14, 1 },
+ { "CL22EXT", 13, 1 },
+ { "MAC_PORT_MTIP_PCS_CTL2", 0x39e1c, 0 },
+ { "MAC_PORT_MTIP_PCS_STATUS2", 0x39e20, 0 },
+ { "Device", 15, 1 },
+ { "TxFault", 7, 1 },
+ { "RxFault", 6, 1 },
+ { "100BASE_R", 5, 1 },
+ { "40GBASE_R", 4, 1 },
+ { "10GBASE_T", 3, 1 },
+ { "10GBASE_W", 2, 1 },
+ { "10GBASE_X", 1, 1 },
+ { "10GBASE_R", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_PKG_ID0", 0x39e38, 0 },
+ { "MAC_PORT_MTIP_PCS_PKG_ID1", 0x39e3c, 0 },
+ { "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x39e80, 0 },
+ { "RxLinkStatus", 12, 1 },
+ { "RESEREVED", 4, 8 },
+ { "10GPRBS9", 3, 1 },
+ { "10GPRBS31", 2, 1 },
+ { "HiBER", 1, 1 },
+ { "blocklock", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x39e84, 0 },
+ { "blocklockLL", 15, 1 },
+ { "HiBERLH", 14, 1 },
+ { "HiBERCount", 8, 6 },
+ { "ErrBlkCnt", 0, 8 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A", 0x39e88, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x39e8c, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x39e90, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x39e94, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B", 0x39e98, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x39e9c, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x39ea0, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x39ea4, 0 },
+ { "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x39ea8, 0 },
+ { "TXPRBS9", 6, 1 },
+ { "RXPRBS31", 5, 1 },
+ { "TXPRBS31", 4, 1 },
+ { "TxTestPatEn", 3, 1 },
+ { "RxTestPatEn", 2, 1 },
+ { "TestPatSel", 1, 1 },
+ { "DataPatSel", 0, 1 },
+ { "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x39eac, 0 },
+ { "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x39eb0, 0 },
+ { "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x39eb4, 0 },
+ { "HiCountPrsnt", 15, 1 },
+ { "BLOCK_CNT_HI", 0, 14 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x39ec8, 0 },
+ { "alignstatus", 12, 1 },
+ { "Lane7", 7, 1 },
+ { "Lane6", 6, 1 },
+ { "Lane5", 5, 1 },
+ { "Lane4", 4, 1 },
+ { "Lane3", 3, 1 },
+ { "Lane2", 2, 1 },
+ { "Lane1", 1, 1 },
+ { "Lane0", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x39ecc, 0 },
+ { "Lane19", 11, 1 },
+ { "Lane18", 10, 1 },
+ { "Lane17", 9, 1 },
+ { "Lane16", 8, 1 },
+ { "Lane15", 7, 1 },
+ { "Lane14", 6, 1 },
+ { "Lane13", 5, 1 },
+ { "Lane12", 4, 1 },
+ { "Lane11", 3, 1 },
+ { "Lane10", 2, 1 },
+ { "Lane9", 1, 1 },
+ { "Lane8", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x39ed0, 0 },
+ { "AMLOCK7", 7, 1 },
+ { "AMLOCK6", 6, 1 },
+ { "AMLOCK5", 5, 1 },
+ { "AMLOCK4", 4, 1 },
+ { "AMLOCK3", 3, 1 },
+ { "AMLOCK2", 2, 1 },
+ { "AMLOCK1", 1, 1 },
+ { "AMLOCK0", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x39ed4, 0 },
+ { "AMLOCK19", 11, 1 },
+ { "AMLOCK18", 10, 1 },
+ { "AMLOCK17", 9, 1 },
+ { "AMLOCK16", 8, 1 },
+ { "AMLOCK15", 7, 1 },
+ { "AMLOCK14", 6, 1 },
+ { "AMLOCK13", 5, 1 },
+ { "AMLOCK12", 4, 1 },
+ { "AMLOCK11", 3, 1 },
+ { "AMLOCK10", 2, 1 },
+ { "AMLOCK9", 1, 1 },
+ { "AMLOCK8", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x39f68, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x39f6c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x39f70, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x39f74, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x39f78, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x39f7c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x39f80, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x39f84, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x39f88, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x39f8c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x39f90, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x39f94, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x39f98, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x39f9c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x39fa0, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x39fa4, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x39fa8, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x39fac, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x39fb0, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x39fb4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x39fb8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x39fbc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x39fc0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x39fc4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x39fc8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x39fcc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x39fd0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x39fd4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x39fd8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x39fdc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x39fe0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x39fe4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x39fe8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x39fec, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x39ff0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x39ff4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x39ff8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x39ffc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x3a000, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x3a004, 0 },
+ { "MAC_PORT_BEAN_CTL", 0x3a200, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS", 0x3a204, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0", 0x3a208, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1", 0x3a20c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2", 0x3a210, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0", 0x3a214, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1", 0x3a218, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2", 0x3a21c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT", 0x3a220, 0 },
+ { "MAC_PORT_BEAN_XNP_0", 0x3a224, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1", 0x3a228, 0 },
+ { "MAC_PORT_BEAN_XNP_2", 0x3a22c, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0", 0x3a230, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1", 0x3a234, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2", 0x3a238, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS", 0x3a23c, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE1", 0x3a240, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE1", 0x3a244, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x3a248, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3a24c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x3a250, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x3a254, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x3a258, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3a25c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x3a260, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE1", 0x3a264, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE1", 0x3a268, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE1", 0x3a26c, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x3a270, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x3a274, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x3a278, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3a27c, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE2", 0x3a280, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE2", 0x3a284, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x3a288, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3a28c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x3a290, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x3a294, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x3a298, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3a29c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x3a2a0, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE2", 0x3a2a4, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE2", 0x3a2a8, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE2", 0x3a2ac, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x3a2b0, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x3a2b4, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x3a2b8, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x3a2bc, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE3", 0x3a2c0, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE3", 0x3a2c4, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x3a2c8, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x3a2cc, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x3a2d0, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x3a2d4, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x3a2d8, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x3a2dc, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x3a2e0, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE3", 0x3a2e4, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE3", 0x3a2e8, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE3", 0x3a2ec, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x3a2f0, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x3a2f4, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x3a2f8, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x3a2fc, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_FEC_KR_CONTROL", 0x3a600, 0 },
+ { "enable_tr", 1, 1 },
+ { "restart_tr", 0, 1 },
+ { "MAC_PORT_FEC_KR_STATUS", 0x3a604, 0 },
+ { "fecKRsigdet", 15, 1 },
+ { "train_fail", 3, 1 },
+ { "startup_status", 2, 1 },
+ { "frame_lock", 1, 1 },
+ { "rx_status", 0, 1 },
+ { "MAC_PORT_FEC_KR_LP_COEFF", 0x3a608, 0 },
+ { "Preset", 13, 1 },
+ { "Initialize", 12, 1 },
+ { "CP1_UPD", 4, 2 },
+ { "C0_UPD", 2, 2 },
+ { "CN1_UPD", 0, 2 },
+ { "MAC_PORT_FEC_KR_LP_STAT", 0x3a60c, 0 },
+ { "rx_ready", 15, 1 },
+ { "CP1_STAT", 4, 2 },
+ { "C0_STAT", 2, 2 },
+ { "CN1_STAT", 0, 2 },
+ { "MAC_PORT_FEC_KR_LD_COEFF", 0x3a610, 0 },
+ { "Preset", 13, 1 },
+ { "Initialize", 12, 1 },
+ { "CP1_UPD", 4, 2 },
+ { "C0_UPD", 2, 2 },
+ { "CN1_UPD", 0, 2 },
+ { "MAC_PORT_FEC_KR_LD_STAT", 0x3a614, 0 },
+ { "rx_ready", 15, 1 },
+ { "CP1_STAT", 4, 2 },
+ { "C0_STAT", 2, 2 },
+ { "CN1_STAT", 0, 2 },
+ { "MAC_PORT_FEC_ABILITY", 0x3a618, 0 },
+ { "fec_ind_ability", 1, 1 },
+ { "ability", 0, 1 },
+ { "MAC_PORT_FEC_CONTROL", 0x3a61c, 0 },
+ { "fec_en_err_ind", 1, 1 },
+ { "fec_en", 0, 1 },
+ { "MAC_PORT_FEC_STATUS", 0x3a620, 0 },
+ { "FEC_LOCKED_100", 1, 1 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_FEC_CERR_CNT_0", 0x3a624, 0 },
+ { "MAC_PORT_FEC_CERR_CNT_1", 0x3a628, 0 },
+ { "MAC_PORT_FEC_NCERR_CNT_0", 0x3a62c, 0 },
+ { "MAC_PORT_FEC_NCERR_CNT_1", 0x3a630, 0 },
+ { "MAC_PORT_AE_RX_COEF_REQ", 0x3aa00, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT", 0x3aa04, 0 },
+ { "T5_AE0_RXSTAT_RDY", 15, 1 },
+ { "T5_AE0_RXSTAT_C2", 4, 2 },
+ { "T5_AE0_RXSTAT_C1", 2, 2 },
+ { "T5_AE0_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ", 0x3aa08, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT", 0x3aa0c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE", 0x3aa10, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL", 0x3aa14, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL", 0x3aa18, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE", 0x3aa1c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_1", 0x3aa20, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_1", 0x3aa24, 0 },
+ { "T5_AE1_RXSTAT_RDY", 15, 1 },
+ { "T5_AE1_RXSTAT_C2", 4, 2 },
+ { "T5_AE1_RXSTAT_C1", 2, 2 },
+ { "T5_AE1_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_1", 0x3aa28, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_1", 0x3aa2c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_1", 0x3aa30, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_1", 0x3aa34, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_1", 0x3aa38, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_1", 0x3aa3c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_2", 0x3aa40, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_2", 0x3aa44, 0 },
+ { "T5_AE2_RXSTAT_RDY", 15, 1 },
+ { "T5_AE2_RXSTAT_C2", 4, 2 },
+ { "T5_AE2_RXSTAT_C1", 2, 2 },
+ { "T5_AE2_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_2", 0x3aa48, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_2", 0x3aa4c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_2", 0x3aa50, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_2", 0x3aa54, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_2", 0x3aa58, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_2", 0x3aa5c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_3", 0x3aa60, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_3", 0x3aa64, 0 },
+ { "T5_AE3_RXSTAT_RDY", 15, 1 },
+ { "T5_AE3_RXSTAT_C2", 4, 2 },
+ { "T5_AE3_RXSTAT_C1", 2, 2 },
+ { "T5_AE3_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_3", 0x3aa68, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_3", 0x3aa6c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_3", 0x3aa70, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_3", 0x3aa74, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_3", 0x3aa78, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_3", 0x3aa7c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_TX_DIS", 0x3aa80, 0 },
+ { "MAC_PORT_AE_KR_CTRL", 0x3aa84, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET", 0x3aa88, 0 },
+ { "MAC_PORT_AE_KR_STATUS", 0x3aa8c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_1", 0x3aa90, 0 },
+ { "MAC_PORT_AE_KR_CTRL_1", 0x3aa94, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_1", 0x3aa98, 0 },
+ { "MAC_PORT_AE_KR_STATUS_1", 0x3aa9c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_2", 0x3aaa0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_2", 0x3aaa4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_2", 0x3aaa8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_2", 0x3aaac, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_3", 0x3aab0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_3", 0x3aab4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_3", 0x3aab8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_3", 0x3aabc, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x3ab00, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x3ab04, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_0", 0x3ab08, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x3ab0c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_0", 0x3ab10, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x3ab20, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x3ab24, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_1", 0x3ab28, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x3ab2c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_1", 0x3ab30, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x3ab40, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x3ab44, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_2", 0x3ab48, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x3ab4c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_2", 0x3ab50, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x3ab60, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x3ab64, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_3", 0x3ab68, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x3ab6c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_3", 0x3ab70, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_ANALOG_TEST_MUX", 0x3b814, 0 },
+ { "MAC_PORT_BANDGAP_CONTROL", 0x3b82c, 0 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x3b880, 0 },
+ { "RCCTL1", 5, 1 },
+ { "RCCTL0", 4, 1 },
+ { "RCAMP1", 3, 1 },
+ { "RCAMP0", 2, 1 },
+ { "RCAMPEN", 1, 1 },
+ { "RCRST", 0, 1 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x3b884, 0 },
+ { "RCERR", 1, 1 },
+ { "RCCOMP", 0, 1 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x3b888, 0 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3b88c, 0 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_6", 0x3b8e8, 0 },
+ { "LBIST", 7, 1 },
+ { "LOGICTEST", 6, 1 },
+ { "MAVDHI", 5, 1 },
+ { "AUXEN", 4, 1 },
+ { "JTAGMD", 3, 1 },
+ { "RXACMODE", 2, 1 },
+ { "HSSACJPC", 1, 1 },
+ { "HSSACJAC", 0, 1 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_5", 0x3b8ec, 0 },
+ { "REFVALIDD", 6, 1 },
+ { "REFVALIDC", 5, 1 },
+ { "REFVALIDB", 4, 1 },
+ { "REFVALIDA", 3, 1 },
+ { "REFSELRESET", 2, 1 },
+ { "SOFTRESET", 1, 1 },
+ { "MACROTEST", 0, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x3bb00, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x3bb04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x3bb08, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x3bb0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x3bb10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x3bb28, 0 },
+ { "MAC_PORT_PLLA_PCLK_CONTROL", 0x3bb3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x3bb40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x3bb44, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x3bb48, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x3bb4c, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x3bb50, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x3bbf0, 0 },
+ { "VBST", 1, 3 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x3bbf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "PDWNP", 2, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x3bbf8, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x3bbfc, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x3bc00, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x3bc04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x3bc08, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x3bc0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x3bc10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x3bc28, 0 },
+ { "MAC_PORT_PLLB_PCLK_CONTROL", 0x3bc3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x3bc40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x3bc44, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x3bc48, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x3bc4c, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x3bc50, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x3bcf0, 0 },
+ { "VBST", 1, 3 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x3bcf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "PDWNP", 2, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x3bcf8, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x3bcfc, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x3b000, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x3b004, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x3b008, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b00c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b010, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b014, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b018, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b01c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x3b020, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x3b024, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x3b028, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x3b030, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x3b034, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b038, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b03c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b040, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b044, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b048, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b060, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b064, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b068, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b070, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b074, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b078, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b07c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b080, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b084, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b088, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3b08c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x3b090, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x3b094, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x3b098, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3b09c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b0f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b0f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b0f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b0fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x3b100, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x3b104, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x3b108, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b10c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b110, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b114, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b118, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b11c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x3b120, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x3b124, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x3b128, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x3b130, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x3b134, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b138, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b13c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b140, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b144, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b148, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b160, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b164, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b168, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b170, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b174, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b178, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b17c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b180, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b184, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b188, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3b18c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x3b190, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x3b194, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x3b198, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3b19c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b1f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b1f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b1f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b1fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x3b400, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x3b404, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x3b408, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b40c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b410, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b414, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b418, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b41c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x3b420, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x3b424, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x3b428, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x3b430, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x3b434, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b438, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b43c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b440, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b444, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b448, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b460, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b464, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b468, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b470, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b474, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b478, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b47c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b480, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b484, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b488, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3b48c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x3b490, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x3b494, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x3b498, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3b49c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b4f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b4f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b4f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b4fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x3b500, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x3b504, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x3b508, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b50c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b510, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b514, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b518, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b51c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x3b520, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x3b524, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x3b528, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x3b530, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x3b534, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b538, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b53c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b540, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b544, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b548, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b560, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b564, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b568, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b570, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b574, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b578, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b57c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b580, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b584, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b588, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3b58c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x3b590, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x3b594, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x3b598, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3b59c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b5f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b5f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b5f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b5fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x3b900, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x3b904, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x3b908, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b90c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b910, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b914, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b918, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b91c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x3b920, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x3b924, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x3b928, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x3b930, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x3b934, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b938, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b93c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b940, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b944, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b948, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b960, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b964, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b968, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b970, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b974, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b978, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b97c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b980, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b984, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b988, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3b98c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x3b990, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x3b994, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x3b998, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3b99c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b9f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b9f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b9f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b9fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x3b200, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x3b204, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x3b208, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b20c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x3b210, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x3b214, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b218, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b21c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x3b220, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x3b224, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x3b228, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3b22c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x3b230, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x3b234, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x3b238, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x3b240, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x3b248, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b24c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x3b250, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b25c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b260, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b264, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b270, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x3b274, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x3b278, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3b27c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x3b280, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x3b284, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x3b288, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3b28c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x3b290, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x3b294, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x3b298, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3b29c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b2a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x3b2a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x3b2a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x3b2ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b2b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b2b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b2b8, 0 },
+ { "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x3b2c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKA_DFE_H1", 0x3b2c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H2", 0x3b2c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_H3", 0x3b2cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H4", 0x3b2d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H5", 0x3b2d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x3b2d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x3b2dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x3b2e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H12", 0x3b2e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b2f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b2fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x3b300, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x3b304, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x3b308, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b30c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x3b310, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x3b314, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b318, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b31c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x3b320, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x3b324, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x3b328, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3b32c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x3b330, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x3b334, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x3b338, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x3b340, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x3b348, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b34c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x3b350, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b35c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b360, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b364, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b370, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x3b374, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x3b378, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3b37c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x3b380, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x3b384, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x3b388, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3b38c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x3b390, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x3b394, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x3b398, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3b39c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b3a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x3b3a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x3b3a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x3b3ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b3b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b3b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b3b8, 0 },
+ { "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x3b3c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKB_DFE_H1", 0x3b3c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H2", 0x3b3c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_H3", 0x3b3cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H4", 0x3b3d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H5", 0x3b3d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x3b3d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x3b3dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x3b3e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H12", 0x3b3e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b3f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b3fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x3b600, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x3b604, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x3b608, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b60c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x3b610, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x3b614, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b618, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b61c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x3b620, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x3b624, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x3b628, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3b62c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x3b630, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x3b634, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x3b638, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x3b640, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x3b648, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b64c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x3b650, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b65c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b660, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b664, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b670, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x3b674, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x3b678, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3b67c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x3b680, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x3b684, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x3b688, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3b68c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x3b690, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x3b694, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x3b698, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3b69c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b6a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x3b6a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x3b6a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x3b6ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b6b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b6b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b6b8, 0 },
+ { "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x3b6c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKC_DFE_H1", 0x3b6c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H2", 0x3b6c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_H3", 0x3b6cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H4", 0x3b6d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H5", 0x3b6d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x3b6d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x3b6dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x3b6e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H12", 0x3b6e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b6f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b6fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x3b700, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x3b704, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x3b708, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b70c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x3b710, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x3b714, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b718, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b71c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x3b720, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x3b724, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x3b728, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3b72c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x3b730, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x3b734, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x3b738, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x3b740, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x3b748, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b74c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x3b750, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b75c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b760, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b764, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b770, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x3b774, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x3b778, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3b77c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x3b780, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x3b784, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x3b788, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3b78c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x3b790, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x3b794, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x3b798, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3b79c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b7a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x3b7a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x3b7a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x3b7ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b7b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b7b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b7b8, 0 },
+ { "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x3b7c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKD_DFE_H1", 0x3b7c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H2", 0x3b7c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_H3", 0x3b7cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H4", 0x3b7d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H5", 0x3b7d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x3b7d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x3b7dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x3b7e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H12", 0x3b7e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b7f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b7fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x3ba00, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x3ba04, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x3ba08, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x3ba0c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x3ba10, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x3ba14, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3ba18, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3ba1c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x3ba20, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x3ba24, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x3ba28, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x3ba2c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x3ba30, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x3ba34, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x3ba38, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x3ba40, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x3ba48, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x3ba4c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x3ba50, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3ba5c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3ba60, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3ba64, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3ba70, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x3ba74, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x3ba78, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x3ba7c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x3ba80, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x3ba84, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x3ba88, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x3ba8c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x3ba90, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x3ba94, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x3ba98, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x3ba9c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3baa0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x3baa4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x3baa8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x3baac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3bab0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3bab4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3bab8, 0 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x3bac0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x3bac4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x3bac8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x3bacc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x3bad0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x3bad4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x3bad8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x3badc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x3bae0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x3bae4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x3baf8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x3bafc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_CFG", 0x3c800, 0 },
+ { "MAC_Clk_Sel", 29, 3 },
+ { "SinkTx", 27, 1 },
+ { "SinkTxOnLinkDown", 26, 1 },
+ { "LoopNoFwd", 24, 1 },
+ { "Smux_Rx_Loop", 19, 1 },
+ { "Rx_Lane_Swap", 18, 1 },
+ { "Tx_Lane_Swap", 17, 1 },
+ { "Signal_Det", 14, 1 },
+ { "SmuxTxSel", 9, 1 },
+ { "SmuxRxSel", 8, 1 },
+ { "PortSpeed", 4, 2 },
+ { "Rx_Byte_Swap", 3, 1 },
+ { "Tx_Byte_Swap", 2, 1 },
+ { "Port_Sel", 0, 1 },
+ { "MAC_PORT_RESET_CTRL", 0x3c804, 0 },
+ { "TWGDSK_HSSC16B", 31, 1 },
+ { "EEE_RESET", 30, 1 },
+ { "PTP_TIMER", 29, 1 },
+ { "MtipRefReset", 28, 1 },
+ { "MtipTxffReset", 27, 1 },
+ { "MtipRxffReset", 26, 1 },
+ { "MtipRegReset", 25, 1 },
+ { "AEC3Reset", 23, 1 },
+ { "AEC2Reset", 22, 1 },
+ { "AEC1Reset", 21, 1 },
+ { "AEC0Reset", 20, 1 },
+ { "AET3Reset", 19, 1 },
+ { "AET2Reset", 18, 1 },
+ { "AET1Reset", 17, 1 },
+ { "AET0Reset", 16, 1 },
+ { "TXIF_Reset", 12, 1 },
+ { "RXIF_Reset", 11, 1 },
+ { "AuxExt_Reset", 10, 1 },
+ { "MtipSd3TxRst", 9, 1 },
+ { "MtipSd2TxRst", 8, 1 },
+ { "MtipSd1TxRst", 7, 1 },
+ { "MtipSd0TxRst", 6, 1 },
+ { "MtipSd3RxRst", 5, 1 },
+ { "MtipSd2RxRst", 4, 1 },
+ { "MtipSd1RxRst", 3, 1 },
+ { "WOL_Reset", 2, 1 },
+ { "MtipSd0RxRst", 1, 1 },
+ { "HSS_Reset", 0, 1 },
+ { "MAC_PORT_LED_CFG", 0x3c808, 0 },
+ { "Led1_Cfg", 5, 3 },
+ { "Led1_Polarity_Inv", 4, 1 },
+ { "Led0_Cfg", 1, 3 },
+ { "Led0_Polarity_Inv", 0, 1 },
+ { "MAC_PORT_LED_COUNTHI", 0x3c80c, 0 },
+ { "MAC_PORT_LED_COUNTLO", 0x3c810, 0 },
+ { "MAC_PORT_CFG3", 0x3c814, 0 },
+ { "FPGA_PTP_PORT", 26, 2 },
+ { "FCSDisCtrl", 25, 1 },
+ { "SigDetCtrl", 24, 1 },
+ { "tx_lane", 23, 1 },
+ { "rx_lane", 22, 1 },
+ { "se_clr", 21, 1 },
+ { "an_ena", 17, 4 },
+ { "sd_rx_clk_ena", 13, 4 },
+ { "sd_tx_clk_ena", 9, 4 },
+ { "SGMIISEL", 8, 1 },
+ { "HSSPLLSEL", 4, 4 },
+ { "HSSC16C20SEL", 0, 4 },
+ { "MAC_PORT_CFG2", 0x3c818, 0 },
+ { "Rx_Polarity_Inv", 28, 4 },
+ { "Tx_Polarity_Inv", 24, 4 },
+ { "InstanceNum", 22, 2 },
+ { "StopOnPerr", 21, 1 },
+ { "PatEn", 18, 1 },
+ { "MagicEn", 17, 1 },
+ { "T5_AEC_PMA_TX_READY", 4, 4 },
+ { "T5_AEC_PMA_RX_READY", 0, 4 },
+ { "MAC_PORT_PKT_COUNT", 0x3c81c, 0 },
+ { "tx_sop_count", 24, 8 },
+ { "tx_eop_count", 16, 8 },
+ { "rx_sop_count", 8, 8 },
+ { "rx_eop_count", 0, 8 },
+ { "MAC_PORT_CFG4", 0x3c820, 0 },
+ { "AEC3_RX_WIDTH", 14, 2 },
+ { "AEC2_RX_WIDTH", 12, 2 },
+ { "AEC1_RX_WIDTH", 10, 2 },
+ { "AEC0_RX_WIDTH", 8, 2 },
+ { "AEC3_TX_WIDTH", 6, 2 },
+ { "AEC2_TX_WIDTH", 4, 2 },
+ { "AEC1_TX_WIDTH", 2, 2 },
+ { "AEC0_TX_WIDTH", 0, 2 },
+ { "MAC_PORT_MAGIC_MACID_LO", 0x3c824, 0 },
+ { "MAC_PORT_MAGIC_MACID_HI", 0x3c828, 0 },
+ { "MAC_PORT_LINK_STATUS", 0x3c834, 0 },
+ { "an_done", 6, 1 },
+ { "align_done", 5, 1 },
+ { "block_lock", 4, 1 },
+ { "remflt", 3, 1 },
+ { "locflt", 2, 1 },
+ { "linkup", 1, 1 },
+ { "linkdn", 0, 1 },
+ { "MAC_PORT_EPIO_DATA0", 0x3c8c0, 0 },
+ { "MAC_PORT_EPIO_DATA1", 0x3c8c4, 0 },
+ { "MAC_PORT_EPIO_DATA2", 0x3c8c8, 0 },
+ { "MAC_PORT_EPIO_DATA3", 0x3c8cc, 0 },
+ { "MAC_PORT_EPIO_OP", 0x3c8d0, 0 },
+ { "Busy", 31, 1 },
+ { "Write", 8, 1 },
+ { "Address", 0, 8 },
+ { "MAC_PORT_WOL_STATUS", 0x3c8d4, 0 },
+ { "MagicDetected", 31, 1 },
+ { "PatDetected", 30, 1 },
+ { "ClearMagic", 4, 1 },
+ { "ClearMatch", 3, 1 },
+ { "MatchedFilter", 0, 3 },
+ { "MAC_PORT_INT_EN", 0x3c8d8, 0 },
+ { "tx_ts_avail", 29, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_INT_CAUSE", 0x3c8dc, 0 },
+ { "tx_ts_avail", 29, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_PERR_INT_EN", 0x3c8e0, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_INT_CAUSE", 0x3c8e4, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_ENABLE", 0x3c8e8, 0 },
+ { "Perr_pkt_ram", 24, 1 },
+ { "Perr_mask_ram", 23, 1 },
+ { "Perr_crc_ram", 22, 1 },
+ { "rx_dff_seg0", 21, 1 },
+ { "rx_sff_seg0", 20, 1 },
+ { "rx_dff_mac10", 19, 1 },
+ { "rx_sff_mac10", 18, 1 },
+ { "tx_dff_seg0", 17, 1 },
+ { "tx_sff_seg0", 16, 1 },
+ { "tx_dff_mac10", 15, 1 },
+ { "tx_sff_mac10", 14, 1 },
+ { "rx_stats", 13, 1 },
+ { "tx_stats", 12, 1 },
+ { "Perr3_rx_mix", 11, 1 },
+ { "Perr3_rx_sd", 10, 1 },
+ { "Perr3_tx", 9, 1 },
+ { "Perr2_rx_mix", 8, 1 },
+ { "Perr2_rx_sd", 7, 1 },
+ { "Perr2_tx", 6, 1 },
+ { "Perr1_rx_mix", 5, 1 },
+ { "Perr1_rx_sd", 4, 1 },
+ { "Perr1_tx", 3, 1 },
+ { "Perr0_rx_mix", 2, 1 },
+ { "Perr0_rx_sd", 1, 1 },
+ { "Perr0_tx", 0, 1 },
+ { "MAC_PORT_PERR_INJECT", 0x3c8ec, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "MAC_PORT_HSS_CFG0", 0x3c8f0, 0 },
+ { "TXDTS", 31, 1 },
+ { "TXCTS", 30, 1 },
+ { "TXBTS", 29, 1 },
+ { "TXATS", 28, 1 },
+ { "TXDOBS", 27, 1 },
+ { "TXCOBS", 26, 1 },
+ { "TXBOBS", 25, 1 },
+ { "TXAOBS", 24, 1 },
+ { "HSSREFCLKVALIDA", 20, 1 },
+ { "HSSREFCLKVALIDB", 19, 1 },
+ { "HSSRESYNCA", 18, 1 },
+ { "HSSAVDHI", 17, 1 },
+ { "HSSRESYNCB", 16, 1 },
+ { "HSSRECCALA", 15, 1 },
+ { "HSSRXACMODE", 14, 1 },
+ { "HSSRECCALB", 13, 1 },
+ { "HSSPLLBYPA", 12, 1 },
+ { "HSSPLLBYPB", 11, 1 },
+ { "HSSPDWNPLLA", 10, 1 },
+ { "HSSPDWNPLLB", 9, 1 },
+ { "HSSVCOSELA", 8, 1 },
+ { "HSSVCOSELB", 7, 1 },
+ { "HSSCALCOMP", 6, 1 },
+ { "HSSCALENAB", 5, 1 },
+ { "HSSEXTC16SEL", 4, 1 },
+ { "MAC_PORT_HSS_CFG1", 0x3c8f4, 0 },
+ { "RXACONFIGSEL", 30, 2 },
+ { "RXAQUIET", 29, 1 },
+ { "RXAREFRESH", 28, 1 },
+ { "RXBCONFIGSEL", 26, 2 },
+ { "RXBQUIET", 25, 1 },
+ { "RXBREFRESH", 24, 1 },
+ { "RXCCONFIGSEL", 22, 2 },
+ { "RXCQUIET", 21, 1 },
+ { "RXCREFRESH", 20, 1 },
+ { "RXDCONFIGSEL", 18, 2 },
+ { "RXDQUIET", 17, 1 },
+ { "RXDREFRESH", 16, 1 },
+ { "TXACONFIGSEL", 14, 2 },
+ { "TXAQUIET", 13, 1 },
+ { "TXAREFRESH", 12, 1 },
+ { "TXBCONFIGSEL", 10, 2 },
+ { "TXBQUIET", 9, 1 },
+ { "TXBREFRESH", 8, 1 },
+ { "TXCCONFIGSEL", 6, 2 },
+ { "TXCQUIET", 5, 1 },
+ { "TXCREFRESH", 4, 1 },
+ { "TXDCONFIGSEL", 2, 2 },
+ { "TXDQUIET", 1, 1 },
+ { "TXDREFRESH", 0, 1 },
+ { "MAC_PORT_HSS_CFG2", 0x3c8f8, 0 },
+ { "RXAASSTCLK", 31, 1 },
+ { "T5RXAPRBSRST", 30, 1 },
+ { "RXBASSTCLK", 29, 1 },
+ { "T5RXBPRBSRST", 28, 1 },
+ { "RXCASSTCLK", 27, 1 },
+ { "T5RXCPRBSRST", 26, 1 },
+ { "RXDASSTCLK", 25, 1 },
+ { "T5RXDPRBSRST", 24, 1 },
+ { "RXDDATASYNC", 23, 1 },
+ { "RXCDATASYNC", 22, 1 },
+ { "RXBDATASYNC", 21, 1 },
+ { "RXADATASYNC", 20, 1 },
+ { "RXDEARLYIN", 19, 1 },
+ { "RXDLATEIN", 18, 1 },
+ { "RXDPHSLOCK", 17, 1 },
+ { "RXDPHSDNIN", 16, 1 },
+ { "RXDPHSUPIN", 15, 1 },
+ { "RXCEARLYIN", 14, 1 },
+ { "RXCLATEIN", 13, 1 },
+ { "RXCPHSLOCK", 12, 1 },
+ { "RXCPHSDNIN", 11, 1 },
+ { "RXCPHSUPIN", 10, 1 },
+ { "RXBEARLYIN", 9, 1 },
+ { "RXBLATEIN", 8, 1 },
+ { "RXBPHSLOCK", 7, 1 },
+ { "RXBPHSDNIN", 6, 1 },
+ { "RXBPHSUPIN", 5, 1 },
+ { "RXAEARLYIN", 4, 1 },
+ { "RXALATEIN", 3, 1 },
+ { "RXAPHSLOCK", 2, 1 },
+ { "RXAPHSDNIN", 1, 1 },
+ { "RXAPHSUPIN", 0, 1 },
+ { "MAC_PORT_HSS_CFG3", 0x3c8fc, 0 },
+ { "HSSCALSSTN", 25, 3 },
+ { "HSSCALSSTP", 22, 3 },
+ { "HSSVBOOSTDIVB", 19, 3 },
+ { "HSSVBOOSTDIVA", 16, 3 },
+ { "HSSPLLCONFIGB", 8, 8 },
+ { "HSSPLLCONFIGA", 0, 8 },
+ { "MAC_PORT_HSS_CFG4", 0x3c900, 0 },
+ { "HSSDIVSELA", 9, 9 },
+ { "HSSDIVSELB", 0, 9 },
+ { "MAC_PORT_HSS_STATUS", 0x3c904, 0 },
+ { "RXDPRBSSYNC", 15, 1 },
+ { "RXCPRBSSYNC", 14, 1 },
+ { "RXBPRBSSYNC", 13, 1 },
+ { "RXAPRBSSYNC", 12, 1 },
+ { "RXDPRBSERR", 11, 1 },
+ { "RXCPRBSERR", 10, 1 },
+ { "RXBPRBSERR", 9, 1 },
+ { "RXAPRBSERR", 8, 1 },
+ { "RXDSIGDET", 7, 1 },
+ { "RXCSIGDET", 6, 1 },
+ { "RXBSIGDET", 5, 1 },
+ { "RXASIGDET", 4, 1 },
+ { "HSSPLLLOCKB", 3, 1 },
+ { "HSSPLLLOCKA", 2, 1 },
+ { "HSSPRTREADYB", 1, 1 },
+ { "HSSPRTREADYA", 0, 1 },
+ { "MAC_PORT_HSS_EEE_STATUS", 0x3c908, 0 },
+ { "RXAQUIET_STATUS", 15, 1 },
+ { "RXAREFRESH_STATUS", 14, 1 },
+ { "RXBQUIET_STATUS", 13, 1 },
+ { "RXBREFRESH_STATUS", 12, 1 },
+ { "RXCQUIET_STATUS", 11, 1 },
+ { "RXCREFRESH_STATUS", 10, 1 },
+ { "RXDQUIET_STATUS", 9, 1 },
+ { "RXDREFRESH_STATUS", 8, 1 },
+ { "TXAQUIET_STATUS", 7, 1 },
+ { "TXAREFRESH_STATUS", 6, 1 },
+ { "TXBQUIET_STATUS", 5, 1 },
+ { "TXBREFRESH_STATUS", 4, 1 },
+ { "TXCQUIET_STATUS", 3, 1 },
+ { "TXCREFRESH_STATUS", 2, 1 },
+ { "TXDQUIET_STATUS", 1, 1 },
+ { "TXDREFRESH_STATUS", 0, 1 },
+ { "MAC_PORT_HSS_SIGDET_STATUS", 0x3c90c, 0 },
+ { "MAC_PORT_HSS_PL_CTL", 0x3c910, 0 },
+ { "TOV", 16, 8 },
+ { "TSU", 8, 8 },
+ { "IPW", 0, 8 },
+ { "MAC_PORT_RUNT_FRAME", 0x3c914, 0 },
+ { "runtclear", 16, 1 },
+ { "runt", 0, 16 },
+ { "MAC_PORT_EEE_STATUS", 0x3c918, 0 },
+ { "eee_tx_10g_state", 10, 2 },
+ { "eee_rx_10g_state", 8, 2 },
+ { "eee_tx_1g_state", 6, 2 },
+ { "eee_rx_1g_state", 4, 2 },
+ { "pma_rx_refresh", 3, 1 },
+ { "pma_rx_quiet", 2, 1 },
+ { "pma_tx_refresh", 1, 1 },
+ { "pma_tx_quiet", 0, 1 },
+ { "MAC_PORT_CGEN", 0x3c91c, 0 },
+ { "CGEN", 8, 1 },
+ { "sd7_CGEN", 7, 1 },
+ { "sd6_CGEN", 6, 1 },
+ { "sd5_CGEN", 5, 1 },
+ { "sd4_CGEN", 4, 1 },
+ { "sd3_CGEN", 3, 1 },
+ { "sd2_CGEN", 2, 1 },
+ { "sd1_CGEN", 1, 1 },
+ { "sd0_CGEN", 0, 1 },
+ { "MAC_PORT_CGEN_MTIP", 0x3c920, 0 },
+ { "MACSEG5_CGEN", 11, 1 },
+ { "PCSSEG5_CGEN", 10, 1 },
+ { "MACSEG4_CGEN", 9, 1 },
+ { "PCSSEG4_CGEN", 8, 1 },
+ { "MACSEG3_CGEN", 7, 1 },
+ { "PCSSEG3_CGEN", 6, 1 },
+ { "MACSEG2_CGEN", 5, 1 },
+ { "PCSSEG2_CGEN", 4, 1 },
+ { "MACSEG1_CGEN", 3, 1 },
+ { "PCSSEG1_CGEN", 2, 1 },
+ { "MACSEG0_CGEN", 1, 1 },
+ { "PCSSEG0_CGEN", 0, 1 },
+ { "MAC_PORT_TX_TS_ID", 0x3c924, 0 },
+ { "MAC_PORT_TX_TS_VAL_LO", 0x3c928, 0 },
+ { "MAC_PORT_TX_TS_VAL_HI", 0x3c92c, 0 },
+ { "MAC_PORT_EEE_CTL", 0x3c930, 0 },
+ { "EEE_CTRL", 2, 30 },
+ { "TICK_START", 1, 1 },
+ { "En", 0, 1 },
+ { "MAC_PORT_EEE_TX_CTL", 0x3c934, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_ACTIVE", 3, 1 },
+ { "LPI_TXHOLD", 2, 1 },
+ { "LPI_REQ", 1, 1 },
+ { "EEE_TX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_RX_CTL", 0x3c938, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_IND", 1, 1 },
+ { "EEE_RX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3c93c, 0 },
+ { "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x3c940, 0 },
+ { "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x3c944, 0 },
+ { "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x3c948, 0 },
+ { "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3c94c, 0 },
+ { "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x3c950, 0 },
+ { "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x3c954, 0 },
+ { "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x3c958, 0 },
+ { "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3c95c, 0 },
+ { "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x3c960, 0 },
+ { "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x3c964, 0 },
+ { "MAC_PORT_EEE_WF_COUNT", 0x3c968, 0 },
+ { "wake_cnt_clr", 16, 1 },
+ { "wake_cnt", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_RD0_LO", 0x3c96c, 0 },
+ { "MAC_PORT_PTP_TIMER_RD0_HI", 0x3c970, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_LO", 0x3c974, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_HI", 0x3c978, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_LO", 0x3c97c, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_HI", 0x3c980, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_0", 0x3c984, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_1", 0x3c988, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3c98c, 0 },
+ { "MAC_PORT_PTP_SUM_LO", 0x3c990, 0 },
+ { "MAC_PORT_PTP_SUM_HI", 0x3c994, 0 },
+ { "MAC_PORT_PTP_TIMER_INCR0", 0x3c998, 0 },
+ { "Y", 16, 16 },
+ { "X", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_INCR1", 0x3c99c, 0 },
+ { "Y_TICK", 16, 16 },
+ { "X_TICK", 0, 16 },
+ { "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x3c9a0, 0 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x3c9a4, 0 },
+ { "B", 16, 16 },
+ { "A", 0, 16 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x3c9a8, 0 },
+ { "MAC_PORT_PTP_CFG", 0x3c9ac, 0 },
+ { "FRZ", 18, 1 },
+ { "OFFSER_ADJUST_SIGN", 17, 1 },
+ { "ADD_OFFSET", 16, 1 },
+ { "CYCLE1", 8, 8 },
+ { "Q", 0, 8 },
+ { "MAC_PORT_MTIP_REVISION", 0x3ca00, 0 },
+ { "CUSTREV", 16, 16 },
+ { "VER", 8, 8 },
+ { "REV", 0, 8 },
+ { "MAC_PORT_MTIP_SCRATCH", 0x3ca04, 0 },
+ { "MAC_PORT_MTIP_COMMAND_CONFIG", 0x3ca08, 0 },
+ { "TX_FLUSH", 22, 1 },
+ { "RX_SFD_ANY", 21, 1 },
+ { "PAUSE_PFC_COMP", 20, 1 },
+ { "PFC_MODE", 19, 1 },
+ { "RS_COL_CNT_EXT", 18, 1 },
+ { "NO_LGTH_CHECK", 17, 1 },
+ { "SEND_IDLE", 16, 1 },
+ { "PHY_TXENA", 15, 1 },
+ { "RX_ERR_DISC", 14, 1 },
+ { "CMD_FRAME_ENA", 13, 1 },
+ { "SW_RESET", 12, 1 },
+ { "TX_PAD_EN", 11, 1 },
+ { "LOOPBACK_EN", 10, 1 },
+ { "TX_ADDR_INS", 9, 1 },
+ { "PAUSE_IGNORE", 8, 1 },
+ { "PAUSE_FWD", 7, 1 },
+ { "CRC_FWD", 6, 1 },
+ { "PAD_EN", 5, 1 },
+ { "PROMIS_EN", 4, 1 },
+ { "WAN_MODE", 3, 1 },
+ { "RX_ENA", 1, 1 },
+ { "TX_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_MAC_ADDR_0", 0x3ca0c, 0 },
+ { "MAC_PORT_MTIP_MAC_ADDR_1", 0x3ca10, 0 },
+ { "MAC_PORT_MTIP_FRM_LENGTH", 0x3ca14, 0 },
+ { "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x3ca1c, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x3ca20, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x3ca24, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x3ca28, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x3ca2c, 0 },
+ { "ENABLE", 8, 1 },
+ { "ADDR", 0, 6 },
+ { "MAC_PORT_MTIP_MAC_STATUS", 0x3ca40, 0 },
+ { "TS_AVAIL", 3, 1 },
+ { "PHY_LOS", 2, 1 },
+ { "RX_REM_FAULT", 1, 1 },
+ { "RX_LOC_FAULT", 0, 1 },
+ { "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x3ca44, 0 },
+ { "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x3ca48, 0 },
+ { "MAC_PORT_MTIP_INIT_CREDIT", 0x3ca4c, 0 },
+ { "MAC_PORT_MTIP_CURRENT_CREDIT", 0x3ca50, 0 },
+ { "MAC_PORT_RX_PAUSE_STATUS", 0x3ca74, 0 },
+ { "MAC_PORT_MTIP_TS_TIMESTAMP", 0x3ca7c, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x3ca80, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x3ca84, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOK", 0x3ca88, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x3ca8c, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x3ca90, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x3ca94, 0 },
+ { "MAC_PORT_AALIGNMENTERRORS", 0x3ca98, 0 },
+ { "MAC_PORT_AALIGNMENTERRORSHI", 0x3ca9c, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x3caa0, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x3caa4, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x3caa8, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x3caac, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORS", 0x3cab0, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x3cab4, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORS", 0x3cab8, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORSHI", 0x3cabc, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOK", 0x3cac0, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOKHI", 0x3cac4, 0 },
+ { "MAC_PORT_VLANRECEIVEDOK", 0x3cac8, 0 },
+ { "MAC_PORT_VLANRECEIVEDOKHI", 0x3cacc, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x3cad0, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x3cad4, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOK", 0x3cad8, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x3cadc, 0 },
+ { "MAC_PORT_IFINUCASTPKTS", 0x3cae0, 0 },
+ { "MAC_PORT_IFINUCASTPKTSHI", 0x3cae4, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTS", 0x3cae8, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTSHI", 0x3caec, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTS", 0x3caf0, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTSHI", 0x3caf4, 0 },
+ { "MAC_PORT_IFOUTERRORS", 0x3caf8, 0 },
+ { "MAC_PORT_IFOUTERRORSHI", 0x3cafc, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTS", 0x3cb08, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTSHI", 0x3cb0c, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTS", 0x3cb10, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x3cb14, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTS", 0x3cb18, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x3cb1c, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTS", 0x3cb20, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x3cb24, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETS", 0x3cb28, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETSHI", 0x3cb2c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS", 0x3cb30, 0 },
+ { "MAC_PORT_ETHERSTATSPKTSHI", 0x3cb34, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x3cb38, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x3cb3c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x3cb40, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x3cb44, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x3cb48, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x3cb4c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x3cb50, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x3cb54, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x3cb58, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x3cb5c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x3cb60, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x3cb64, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x3cb68, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x3cb6c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x3cb70, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x3cb74, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x3cb78, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x3cb7c, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERS", 0x3cb80, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERSHI", 0x3cb84, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTS", 0x3cb88, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x3cb8c, 0 },
+ { "MAC_PORT_IFINERRORS", 0x3cb90, 0 },
+ { "MAC_PORT_IFINERRORSHI", 0x3cb94, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x3cb98, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x3cb9c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x3cba0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x3cba4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x3cba8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x3cbac, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x3cbb0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x3cbb4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x3cbb8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x3cbbc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x3cbc0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x3cbc4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x3cbc8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x3cbcc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x3cbd0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x3cbd4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x3cbd8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x3cbdc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x3cbe0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x3cbe4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x3cbe8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x3cbec, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x3cbf0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x3cbf4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x3cbf8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x3cbfc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x3cc00, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x3cc04, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x3cc08, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x3cc0c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x3cc10, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x3cc14, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x3cc18, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x3cc1c, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x3cc20, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x3cc24, 0 },
+ { "MAC_PORT_MTIP_SGMII_CONTROL", 0x3cd00, 0 },
+ { "Reset", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "sppedsel1", 13, 1 },
+ { "AN_EN", 12, 1 },
+ { "PWRDWN", 11, 1 },
+ { "Isolate", 10, 1 },
+ { "AN_RESTART", 9, 1 },
+ { "DPLX", 8, 1 },
+ { "CollisionTest", 7, 1 },
+ { "SpeedSel0", 6, 1 },
+ { "MAC_PORT_MTIP_SGMII_STATUS", 0x3cd04, 0 },
+ { "100BaseT4", 15, 1 },
+ { "100BaseXFullDplx", 14, 1 },
+ { "100BaseXHalfDplx", 13, 1 },
+ { "10MbpsFullDplx", 12, 1 },
+ { "10MbpsHalfDplx", 11, 1 },
+ { "100BaseT2FullDplx", 10, 1 },
+ { "100BaseT2HalfDplx", 9, 1 },
+ { "ExtdStatus", 8, 1 },
+ { "AN_Complete", 5, 1 },
+ { "SGMII_REM_FAULT", 4, 1 },
+ { "AN_Ability", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "JabberDetect", 1, 1 },
+ { "ExtdCapability", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x3cd08, 0 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x3cd0c, 0 },
+ { "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x3cd10, 0 },
+ { "NP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "RF2", 13, 1 },
+ { "RF1", 12, 1 },
+ { "PS2", 8, 1 },
+ { "PS1", 7, 1 },
+ { "HD", 6, 1 },
+ { "FD", 5, 1 },
+ { "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x3cd14, 0 },
+ { "CuLinkStatus", 15, 1 },
+ { "ACK", 14, 1 },
+ { "CuDplxStatus", 12, 1 },
+ { "CuSpeed", 10, 2 },
+ { "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x3cd18, 0 },
+ { "PgRcvd", 1, 1 },
+ { "RealTimePgRcvd", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x3cd1c, 0 },
+ { "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x3cd20, 0 },
+ { "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x3cd3c, 0 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x3cd48, 0 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x3cd4c, 0 },
+ { "MAC_PORT_MTIP_SGMII_IF_MODE", 0x3cd50, 0 },
+ { "SGMII_PCS_ENABLE", 5, 1 },
+ { "SGMII_HDUPLEX", 4, 1 },
+ { "SGMII_SPEED", 2, 2 },
+ { "USE_SGMII_AN", 1, 1 },
+ { "SGMII_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_ACT_CTL_SEG", 0x3d200, 0 },
+ { "MAC_PORT_MTIP_MODE_CTL_SEG", 0x3d204, 0 },
+ { "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x3d208, 0 },
+ { "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3d20c, 0 },
+ { "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x3d220, 0 },
+ { "MAC_PORT_MTIP_VL_INTVL", 0x3d240, 0 },
+ { "VL_INTVL", 1, 1 },
+ { "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x3d600, 0 },
+ { "CLK_DIV", 7, 9 },
+ { "CL45_EN", 6, 1 },
+ { "disable_preamble", 5, 1 },
+ { "mdio_hold_time", 2, 3 },
+ { "mdio_read_err", 1, 1 },
+ { "mdio_busy", 0, 1 },
+ { "MAC_PORT_MTIP_MDIO_COMMAND", 0x3d604, 0 },
+ { "read", 15, 1 },
+ { "read_incr", 14, 1 },
+ { "port_addr", 5, 5 },
+ { "dev_addr", 0, 5 },
+ { "MAC_PORT_MTIP_MDIO_DATA", 0x3d608, 0 },
+ { "readbusy", 31, 1 },
+ { "data_word", 0, 16 },
+ { "MAC_PORT_MTIP_MDIO_REGADDR", 0x3d60c, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_0", 0x3da00, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_1", 0x3da04, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_2", 0x3da08, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_3", 0x3da0c, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_4", 0x3da10, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_5", 0x3da14, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_6", 0x3da18, 0 },
+ { "MAC_PORT_MTIP_VLAN_TPID_7", 0x3da1c, 0 },
+ { "MAC_PORT_MTIP_PCS_CTL", 0x3de00, 0 },
+ { "RESET", 15, 1 },
+ { "LPBK", 14, 1 },
+ { "SPEED_SEL1", 13, 1 },
+ { "LP_MODE", 11, 1 },
+ { "SPEED_SEL0", 6, 1 },
+ { "SPEED", 2, 4 },
+ { "MAC_PORT_MTIP_PCS_STATUS1", 0x3de04, 0 },
+ { "FaultDet", 7, 1 },
+ { "rx_link_status", 2, 1 },
+ { "LoPwrAbl", 1, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x3de08, 0 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x3de0c, 0 },
+ { "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x3de10, 0 },
+ { "100G", 8, 1 },
+ { "40G", 7, 1 },
+ { "10BASE_TL", 1, 1 },
+ { "10G", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x3de14, 0 },
+ { "TC", 6, 1 },
+ { "DTEXS", 5, 1 },
+ { "PHYXS", 4, 1 },
+ { "PCS", 3, 1 },
+ { "WIS", 2, 1 },
+ { "PMD_PMA", 1, 1 },
+ { "CL22", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x3de18, 0 },
+ { "VendDev2", 15, 1 },
+ { "VendDev1", 14, 1 },
+ { "CL22EXT", 13, 1 },
+ { "MAC_PORT_MTIP_PCS_CTL2", 0x3de1c, 0 },
+ { "MAC_PORT_MTIP_PCS_STATUS2", 0x3de20, 0 },
+ { "Device", 15, 1 },
+ { "TxFault", 7, 1 },
+ { "RxFault", 6, 1 },
+ { "100BASE_R", 5, 1 },
+ { "40GBASE_R", 4, 1 },
+ { "10GBASE_T", 3, 1 },
+ { "10GBASE_W", 2, 1 },
+ { "10GBASE_X", 1, 1 },
+ { "10GBASE_R", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_PKG_ID0", 0x3de38, 0 },
+ { "MAC_PORT_MTIP_PCS_PKG_ID1", 0x3de3c, 0 },
+ { "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x3de80, 0 },
+ { "RxLinkStatus", 12, 1 },
+ { "RESEREVED", 4, 8 },
+ { "10GPRBS9", 3, 1 },
+ { "10GPRBS31", 2, 1 },
+ { "HiBER", 1, 1 },
+ { "blocklock", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x3de84, 0 },
+ { "blocklockLL", 15, 1 },
+ { "HiBERLH", 14, 1 },
+ { "HiBERCount", 8, 6 },
+ { "ErrBlkCnt", 0, 8 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A", 0x3de88, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x3de8c, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x3de90, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x3de94, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B", 0x3de98, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x3de9c, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x3dea0, 0 },
+ { "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x3dea4, 0 },
+ { "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x3dea8, 0 },
+ { "TXPRBS9", 6, 1 },
+ { "RXPRBS31", 5, 1 },
+ { "TXPRBS31", 4, 1 },
+ { "TxTestPatEn", 3, 1 },
+ { "RxTestPatEn", 2, 1 },
+ { "TestPatSel", 1, 1 },
+ { "DataPatSel", 0, 1 },
+ { "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x3deac, 0 },
+ { "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x3deb0, 0 },
+ { "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x3deb4, 0 },
+ { "HiCountPrsnt", 15, 1 },
+ { "BLOCK_CNT_HI", 0, 14 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x3dec8, 0 },
+ { "alignstatus", 12, 1 },
+ { "Lane7", 7, 1 },
+ { "Lane6", 6, 1 },
+ { "Lane5", 5, 1 },
+ { "Lane4", 4, 1 },
+ { "Lane3", 3, 1 },
+ { "Lane2", 2, 1 },
+ { "Lane1", 1, 1 },
+ { "Lane0", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x3decc, 0 },
+ { "Lane19", 11, 1 },
+ { "Lane18", 10, 1 },
+ { "Lane17", 9, 1 },
+ { "Lane16", 8, 1 },
+ { "Lane15", 7, 1 },
+ { "Lane14", 6, 1 },
+ { "Lane13", 5, 1 },
+ { "Lane12", 4, 1 },
+ { "Lane11", 3, 1 },
+ { "Lane10", 2, 1 },
+ { "Lane9", 1, 1 },
+ { "Lane8", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x3ded0, 0 },
+ { "AMLOCK7", 7, 1 },
+ { "AMLOCK6", 6, 1 },
+ { "AMLOCK5", 5, 1 },
+ { "AMLOCK4", 4, 1 },
+ { "AMLOCK3", 3, 1 },
+ { "AMLOCK2", 2, 1 },
+ { "AMLOCK1", 1, 1 },
+ { "AMLOCK0", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x3ded4, 0 },
+ { "AMLOCK19", 11, 1 },
+ { "AMLOCK18", 10, 1 },
+ { "AMLOCK17", 9, 1 },
+ { "AMLOCK16", 8, 1 },
+ { "AMLOCK15", 7, 1 },
+ { "AMLOCK14", 6, 1 },
+ { "AMLOCK13", 5, 1 },
+ { "AMLOCK12", 4, 1 },
+ { "AMLOCK11", 3, 1 },
+ { "AMLOCK10", 2, 1 },
+ { "AMLOCK9", 1, 1 },
+ { "AMLOCK8", 0, 1 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x3df68, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x3df6c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x3df70, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x3df74, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x3df78, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x3df7c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x3df80, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x3df84, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x3df88, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x3df8c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x3df90, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x3df94, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x3df98, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x3df9c, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x3dfa0, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x3dfa4, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x3dfa8, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x3dfac, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x3dfb0, 0 },
+ { "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x3dfb4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x3dfb8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x3dfbc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x3dfc0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x3dfc4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x3dfc8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x3dfcc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x3dfd0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x3dfd4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x3dfd8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x3dfdc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x3dfe0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x3dfe4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x3dfe8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x3dfec, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x3dff0, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x3dff4, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x3dff8, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x3dffc, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x3e000, 0 },
+ { "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x3e004, 0 },
+ { "MAC_PORT_BEAN_CTL", 0x3e200, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS", 0x3e204, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0", 0x3e208, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1", 0x3e20c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2", 0x3e210, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0", 0x3e214, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1", 0x3e218, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2", 0x3e21c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT", 0x3e220, 0 },
+ { "MAC_PORT_BEAN_XNP_0", 0x3e224, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1", 0x3e228, 0 },
+ { "MAC_PORT_BEAN_XNP_2", 0x3e22c, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0", 0x3e230, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1", 0x3e234, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2", 0x3e238, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS", 0x3e23c, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE1", 0x3e240, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE1", 0x3e244, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x3e248, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3e24c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x3e250, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x3e254, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x3e258, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3e25c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x3e260, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE1", 0x3e264, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE1", 0x3e268, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE1", 0x3e26c, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x3e270, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x3e274, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x3e278, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3e27c, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE2", 0x3e280, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE2", 0x3e284, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x3e288, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3e28c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x3e290, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x3e294, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x3e298, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3e29c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x3e2a0, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE2", 0x3e2a4, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE2", 0x3e2a8, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE2", 0x3e2ac, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x3e2b0, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x3e2b4, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x3e2b8, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x3e2bc, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_BEAN_CTL_LANE3", 0x3e2c0, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS_LANE3", 0x3e2c4, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x3e2c8, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x3e2cc, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x3e2d0, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x3e2d4, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x3e2d8, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x3e2dc, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x3e2e0, 0 },
+ { "MAC_PORT_BEAN_XNP_0_LANE3", 0x3e2e4, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1_LANE3", 0x3e2e8, 0 },
+ { "MAC_PORT_BEAN_XNP_2_LANE3", 0x3e2ec, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x3e2f0, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x3e2f4, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x3e2f8, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x3e2fc, 0 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_FEC_KR_CONTROL", 0x3e600, 0 },
+ { "enable_tr", 1, 1 },
+ { "restart_tr", 0, 1 },
+ { "MAC_PORT_FEC_KR_STATUS", 0x3e604, 0 },
+ { "fecKRsigdet", 15, 1 },
+ { "train_fail", 3, 1 },
+ { "startup_status", 2, 1 },
+ { "frame_lock", 1, 1 },
+ { "rx_status", 0, 1 },
+ { "MAC_PORT_FEC_KR_LP_COEFF", 0x3e608, 0 },
+ { "Preset", 13, 1 },
+ { "Initialize", 12, 1 },
+ { "CP1_UPD", 4, 2 },
+ { "C0_UPD", 2, 2 },
+ { "CN1_UPD", 0, 2 },
+ { "MAC_PORT_FEC_KR_LP_STAT", 0x3e60c, 0 },
+ { "rx_ready", 15, 1 },
+ { "CP1_STAT", 4, 2 },
+ { "C0_STAT", 2, 2 },
+ { "CN1_STAT", 0, 2 },
+ { "MAC_PORT_FEC_KR_LD_COEFF", 0x3e610, 0 },
+ { "Preset", 13, 1 },
+ { "Initialize", 12, 1 },
+ { "CP1_UPD", 4, 2 },
+ { "C0_UPD", 2, 2 },
+ { "CN1_UPD", 0, 2 },
+ { "MAC_PORT_FEC_KR_LD_STAT", 0x3e614, 0 },
+ { "rx_ready", 15, 1 },
+ { "CP1_STAT", 4, 2 },
+ { "C0_STAT", 2, 2 },
+ { "CN1_STAT", 0, 2 },
+ { "MAC_PORT_FEC_ABILITY", 0x3e618, 0 },
+ { "fec_ind_ability", 1, 1 },
+ { "ability", 0, 1 },
+ { "MAC_PORT_FEC_CONTROL", 0x3e61c, 0 },
+ { "fec_en_err_ind", 1, 1 },
+ { "fec_en", 0, 1 },
+ { "MAC_PORT_FEC_STATUS", 0x3e620, 0 },
+ { "FEC_LOCKED_100", 1, 1 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_FEC_CERR_CNT_0", 0x3e624, 0 },
+ { "MAC_PORT_FEC_CERR_CNT_1", 0x3e628, 0 },
+ { "MAC_PORT_FEC_NCERR_CNT_0", 0x3e62c, 0 },
+ { "MAC_PORT_FEC_NCERR_CNT_1", 0x3e630, 0 },
+ { "MAC_PORT_AE_RX_COEF_REQ", 0x3ea00, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT", 0x3ea04, 0 },
+ { "T5_AE0_RXSTAT_RDY", 15, 1 },
+ { "T5_AE0_RXSTAT_C2", 4, 2 },
+ { "T5_AE0_RXSTAT_C1", 2, 2 },
+ { "T5_AE0_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ", 0x3ea08, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT", 0x3ea0c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE", 0x3ea10, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL", 0x3ea14, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL", 0x3ea18, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE", 0x3ea1c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_1", 0x3ea20, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_1", 0x3ea24, 0 },
+ { "T5_AE1_RXSTAT_RDY", 15, 1 },
+ { "T5_AE1_RXSTAT_C2", 4, 2 },
+ { "T5_AE1_RXSTAT_C1", 2, 2 },
+ { "T5_AE1_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_1", 0x3ea28, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_1", 0x3ea2c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_1", 0x3ea30, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_1", 0x3ea34, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_1", 0x3ea38, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_1", 0x3ea3c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_2", 0x3ea40, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_2", 0x3ea44, 0 },
+ { "T5_AE2_RXSTAT_RDY", 15, 1 },
+ { "T5_AE2_RXSTAT_C2", 4, 2 },
+ { "T5_AE2_RXSTAT_C1", 2, 2 },
+ { "T5_AE2_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_2", 0x3ea48, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_2", 0x3ea4c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_2", 0x3ea50, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_2", 0x3ea54, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_2", 0x3ea58, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_2", 0x3ea5c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_3", 0x3ea60, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_3", 0x3ea64, 0 },
+ { "T5_AE3_RXSTAT_RDY", 15, 1 },
+ { "T5_AE3_RXSTAT_C2", 4, 2 },
+ { "T5_AE3_RXSTAT_C1", 2, 2 },
+ { "T5_AE3_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_3", 0x3ea68, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_3", 0x3ea6c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_3", 0x3ea70, 0 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_3", 0x3ea74, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_3", 0x3ea78, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_3", 0x3ea7c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_TX_DIS", 0x3ea80, 0 },
+ { "MAC_PORT_AE_KR_CTRL", 0x3ea84, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET", 0x3ea88, 0 },
+ { "MAC_PORT_AE_KR_STATUS", 0x3ea8c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_1", 0x3ea90, 0 },
+ { "MAC_PORT_AE_KR_CTRL_1", 0x3ea94, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_1", 0x3ea98, 0 },
+ { "MAC_PORT_AE_KR_STATUS_1", 0x3ea9c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_2", 0x3eaa0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_2", 0x3eaa4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_2", 0x3eaa8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_2", 0x3eaac, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_3", 0x3eab0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_3", 0x3eab4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_3", 0x3eab8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_3", 0x3eabc, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x3eb00, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x3eb04, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_0", 0x3eb08, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x3eb0c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_0", 0x3eb10, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x3eb20, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x3eb24, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_1", 0x3eb28, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x3eb2c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_1", 0x3eb30, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x3eb40, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x3eb44, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_2", 0x3eb48, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x3eb4c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_2", 0x3eb50, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x3eb60, 0 },
+ { "EN_HOLD_FAIL", 14, 1 },
+ { "INIT_METH", 12, 2 },
+ { "CE_DECS", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_C1", 5, 1 },
+ { "EN_MAX_ST", 4, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x3eb64, 0 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_3", 0x3eb68, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x3eb6c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT6", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_3", 0x3eb70, 0 },
+ { "AET_STAT", 9, 4 },
+ { "NEU_STATE", 5, 4 },
+ { "CTRL_STATE", 0, 5 },
+ { "MAC_PORT_ANALOG_TEST_MUX", 0x3f814, 0 },
+ { "MAC_PORT_BANDGAP_CONTROL", 0x3f82c, 0 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x3f880, 0 },
+ { "RCCTL1", 5, 1 },
+ { "RCCTL0", 4, 1 },
+ { "RCAMP1", 3, 1 },
+ { "RCAMP0", 2, 1 },
+ { "RCAMPEN", 1, 1 },
+ { "RCRST", 0, 1 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x3f884, 0 },
+ { "RCERR", 1, 1 },
+ { "RCCOMP", 0, 1 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x3f888, 0 },
+ { "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3f88c, 0 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_6", 0x3f8e8, 0 },
+ { "LBIST", 7, 1 },
+ { "LOGICTEST", 6, 1 },
+ { "MAVDHI", 5, 1 },
+ { "AUXEN", 4, 1 },
+ { "JTAGMD", 3, 1 },
+ { "RXACMODE", 2, 1 },
+ { "HSSACJPC", 1, 1 },
+ { "HSSACJAC", 0, 1 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_5", 0x3f8ec, 0 },
+ { "REFVALIDD", 6, 1 },
+ { "REFVALIDC", 5, 1 },
+ { "REFVALIDB", 4, 1 },
+ { "REFVALIDA", 3, 1 },
+ { "REFSELRESET", 2, 1 },
+ { "SOFTRESET", 1, 1 },
+ { "MACROTEST", 0, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x3fb00, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x3fb04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x3fb08, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x3fb0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x3fb10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x3fb28, 0 },
+ { "MAC_PORT_PLLA_PCLK_CONTROL", 0x3fb3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x3fb40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x3fb44, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x3fb48, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x3fb4c, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x3fb50, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x3fbf0, 0 },
+ { "VBST", 1, 3 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x3fbf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "PDWNP", 2, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x3fbf8, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x3fbfc, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x3fc00, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x3fc04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x3fc08, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x3fc0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x3fc10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x3fc28, 0 },
+ { "MAC_PORT_PLLB_PCLK_CONTROL", 0x3fc3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x3fc40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x3fc44, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x3fc48, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x3fc4c, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x3fc50, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x3fcf0, 0 },
+ { "VBST", 1, 3 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x3fcf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "PDWNP", 2, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x3fcf8, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x3fcfc, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x3f000, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x3f004, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x3f008, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f00c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f010, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f014, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f018, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f01c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x3f020, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x3f024, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x3f028, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x3f030, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x3f034, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f038, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f03c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f040, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f044, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f048, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f060, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f064, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f068, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f070, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f074, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f078, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f07c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f080, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f084, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f088, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3f08c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x3f090, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x3f094, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x3f098, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3f09c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f0f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f0f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f0f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f0fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x3f100, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x3f104, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x3f108, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f10c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f110, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f114, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f118, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f11c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x3f120, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x3f124, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x3f128, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x3f130, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x3f134, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f138, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f13c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f140, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f144, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f148, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f160, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f164, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f168, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f170, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f174, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f178, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f17c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f180, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f184, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f188, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3f18c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x3f190, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x3f194, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x3f198, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3f19c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f1f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f1f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f1f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f1fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x3f400, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x3f404, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x3f408, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f40c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f410, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f414, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f418, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f41c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x3f420, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x3f424, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x3f428, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x3f430, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x3f434, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f438, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f43c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f440, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f444, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f448, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f460, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f464, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f468, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f470, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f474, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f478, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f47c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f480, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f484, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f488, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3f48c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x3f490, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x3f494, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x3f498, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3f49c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f4f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f4f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f4f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f4fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x3f500, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x3f504, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x3f508, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f50c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f510, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f514, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f518, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f51c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x3f520, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x3f524, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x3f528, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x3f530, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x3f534, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f538, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f53c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f540, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f544, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f548, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f560, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f564, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f568, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f570, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f574, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f578, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f57c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f580, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f584, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f588, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3f58c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x3f590, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x3f594, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x3f598, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3f59c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f5f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f5f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f5f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f5fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x3f900, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_EXTC16", 5, 1 },
+ { "T5_TX_DCKSEL", 4, 1 },
+ { "T5_TX_RXLOOP", 3, 1 },
+ { "T5_TX_BWSEL", 2, 1 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x3f904, 0 },
+ { "SPSEL", 11, 3 },
+ { "AFDWEN", 7, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x3f908, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "AMMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f90c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SASIMP", 4, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f910, 0 },
+ { "T5C2BUFDCEN", 5, 1 },
+ { "T5DCCEN", 4, 1 },
+ { "T5REGBYP", 3, 1 },
+ { "T5REGAEN", 2, 1 },
+ { "T5REGAMP", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f914, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f918, 0 },
+ { "CALSSTN", 3, 3 },
+ { "CALSSTP", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f91c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x3f920, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x3f924, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x3f928, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x3f930, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x3f934, 0 },
+ { "TXPOL", 4, 3 },
+ { "NXTPOL", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f938, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "C2UPDT", 4, 2 },
+ { "C1UPDT", 2, 2 },
+ { "C0UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f93c, 0 },
+ { "C2STAT", 4, 2 },
+ { "C1STAT", 2, 2 },
+ { "C0STAT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f940, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f944, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f948, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f960, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f964, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f968, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f970, 0 },
+ { "MAINSC", 6, 6 },
+ { "POSTSC", 0, 6 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f974, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f978, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f97c, 0 },
+ { "T5XADDR", 1, 5 },
+ { "T5XWR", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f980, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f984, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f988, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3f98c, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 14, 1 },
+ { "DCCLOCK", 13, 1 },
+ { "DCCOFFSET", 8, 5 },
+ { "DCCSTEP", 6, 2 },
+ { "DCCASTEP", 1, 5 },
+ { "DCCAEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x3f990, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x3f994, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x3f998, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3f99c, 0 },
+ { "LPIDCLK", 4, 1 },
+ { "LPITERM", 2, 2 },
+ { "LPIPRCD", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f9f0, 0 },
+ { "SDOVRDEN", 8, 1 },
+ { "SDOVRD", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f9f4, 0 },
+ { "SLEWCODE", 1, 2 },
+ { "ASEGEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f9f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f9fc, 0 },
+ { "C48DIVCTL", 12, 3 },
+ { "RATEDIVCTL", 9, 3 },
+ { "ANLGFLSH", 8, 1 },
+ { "DCCTSTOUT", 7, 1 },
+ { "BSOUT", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x3f200, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x3f204, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x3f208, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f20c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x3f210, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x3f214, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f218, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f21c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x3f220, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x3f224, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x3f228, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3f22c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x3f230, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x3f234, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x3f238, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x3f240, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x3f248, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f24c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x3f250, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f25c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f260, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f264, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f270, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x3f274, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x3f278, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3f27c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x3f280, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x3f284, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x3f288, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3f28c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x3f290, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x3f294, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x3f298, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3f29c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f2a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x3f2a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x3f2a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x3f2ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f2b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f2b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f2b8, 0 },
+ { "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x3f2c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKA_DFE_H1", 0x3f2c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DFE_H2", 0x3f2c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_H3", 0x3f2cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H4", 0x3f2d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H5", 0x3f2d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x3f2d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x3f2dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x3f2e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DFE_H12", 0x3f2e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f2f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f2fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x3f300, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x3f304, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x3f308, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f30c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x3f310, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x3f314, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f318, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f31c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x3f320, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x3f324, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x3f328, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3f32c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x3f330, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x3f334, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x3f338, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x3f340, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x3f348, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f34c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x3f350, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f35c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f360, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f364, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f370, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x3f374, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x3f378, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3f37c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x3f380, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x3f384, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x3f388, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3f38c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x3f390, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x3f394, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x3f398, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3f39c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f3a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x3f3a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x3f3a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x3f3ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f3b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f3b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f3b8, 0 },
+ { "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x3f3c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKB_DFE_H1", 0x3f3c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DFE_H2", 0x3f3c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_H3", 0x3f3cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H4", 0x3f3d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H5", 0x3f3d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x3f3d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x3f3dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x3f3e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DFE_H12", 0x3f3e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f3f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f3fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x3f600, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x3f604, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x3f608, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f60c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x3f610, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x3f614, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f618, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f61c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x3f620, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x3f624, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x3f628, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3f62c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x3f630, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x3f634, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x3f638, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x3f640, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x3f648, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f64c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x3f650, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f65c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f660, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f664, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f670, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x3f674, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x3f678, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3f67c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x3f680, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x3f684, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x3f688, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3f68c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x3f690, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x3f694, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x3f698, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3f69c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f6a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x3f6a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x3f6a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x3f6ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f6b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f6b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f6b8, 0 },
+ { "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x3f6c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKC_DFE_H1", 0x3f6c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DFE_H2", 0x3f6c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_H3", 0x3f6cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H4", 0x3f6d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H5", 0x3f6d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x3f6d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x3f6dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x3f6e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DFE_H12", 0x3f6e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f6f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f6fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x3f700, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x3f704, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x3f708, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f70c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x3f710, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x3f714, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f718, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f71c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x3f720, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x3f724, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x3f728, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3f72c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x3f730, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x3f734, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x3f738, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x3f740, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x3f748, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f74c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x3f750, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f75c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f760, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f764, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f770, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x3f774, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x3f778, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3f77c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x3f780, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x3f784, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x3f788, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3f78c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x3f790, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x3f794, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x3f798, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3f79c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f7a0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x3f7a4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x3f7a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x3f7ac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f7b0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f7b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f7b8, 0 },
+ { "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x3f7c0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINKD_DFE_H1", 0x3f7c4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DFE_H2", 0x3f7c8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_H3", 0x3f7cc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H4", 0x3f7d0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H5", 0x3f7d4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x3f7d8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x3f7dc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x3f7e0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DFE_H12", 0x3f7e4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f7f8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f7fc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x3fa00, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_AUXCLK", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x3fa04, 0 },
+ { "RCLKEN", 15, 1 },
+ { "RRATE", 13, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x3fa08, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x3fa0c, 0 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "OFFEN", 9, 1 },
+ { "TMSCAL", 7, 2 },
+ { "APADJ", 6, 1 },
+ { "RSEL", 5, 1 },
+ { "PHOFFS", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x3fa10, 0 },
+ { "ROT0A", 8, 6 },
+ { "ROT00", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x3fa14, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROT90", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3fa18, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOOFF", 10, 5 },
+ { "RAEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3fa1c, 0 },
+ { "RCALER", 15, 1 },
+ { "RBOOFF", 10, 5 },
+ { "RBEOFF", 5, 5 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x3fa20, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 9, 3 },
+ { "DFEPWR", 6, 3 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x3fa24, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x3fa28, 0 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x3fa2c, 0 },
+ { "POLE", 12, 2 },
+ { "PEAK", 8, 3 },
+ { "VOFFSN", 6, 2 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x3fa30, 0 },
+ { "T5SHORTV", 10, 1 },
+ { "T5VGAIN", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x3fa34, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x3fa38, 0 },
+ { "IQSEP", 10, 5 },
+ { "DUTYQ", 5, 5 },
+ { "DUTYI", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x3fa40, 0 },
+ { "DTHR", 8, 6 },
+ { "SNUL", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x3fa48, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x3fa4c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x3fa50, 0 },
+ { "ADSN_ReadWrite", 8, 1 },
+ { "ADSN_ReadOnly", 7, 1 },
+ { "ADMAG", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3fa5c, 0 },
+ { "H1O2", 8, 6 },
+ { "H1E2", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3fa60, 0 },
+ { "H1O3", 8, 6 },
+ { "H1E3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3fa64, 0 },
+ { "H1O4", 8, 6 },
+ { "H1E4", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3fa70, 0 },
+ { "DPCMD", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCTGT", 9, 3 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x3fa74, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "ODEC", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x3fa78, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5DQCCCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x3fa7c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x3fa80, 0 },
+ { "H25SPC", 15, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FINTTRIM", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FDCA", 1, 1 },
+ { "FDQCC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x3fa84, 0 },
+ { "LOFE2S_ReadWrite", 16, 1 },
+ { "LOFE2S_ReadOnly", 14, 2 },
+ { "LOFE2", 8, 6 },
+ { "LOFE1S_ReadWrite", 7, 1 },
+ { "LOFE1S_ReadOnly", 6, 1 },
+ { "LOFE1", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x3fa88, 0 },
+ { "LOFO2S_ReadWrite", 15, 1 },
+ { "LOFO2S_ReadOnly", 14, 1 },
+ { "LOFO2", 8, 6 },
+ { "LOFO1S_ReadWrite", 7, 1 },
+ { "LOFO1S_ReadOnly", 6, 1 },
+ { "LOFO1", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x3fa8c, 0 },
+ { "LOFE4S_ReadWrite", 15, 1 },
+ { "LOFE4S_ReadOnly", 14, 1 },
+ { "LOFE", 8, 6 },
+ { "LOFE3S_ReadWrite", 7, 1 },
+ { "LOFE3S_ReadOnly", 6, 1 },
+ { "LOFE3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x3fa90, 0 },
+ { "LOFO4S_ReadWrite", 15, 1 },
+ { "LOFO4S_ReadOnly", 14, 1 },
+ { "LOFO4", 8, 6 },
+ { "LOFO3S_ReadWrite", 7, 1 },
+ { "LOFO3S_ReadOnly", 6, 1 },
+ { "LOFO3", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x3fa94, 0 },
+ { "T5E1SN_ReadWrite", 15, 1 },
+ { "T5E1SN_ReadOnly", 14, 1 },
+ { "T5E1AMP", 8, 6 },
+ { "T5E0SN_ReadWrite", 7, 1 },
+ { "T5E0SN_ReadOnly", 6, 1 },
+ { "T5E0AMP", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x3fa98, 0 },
+ { "T5LFREG", 12, 1 },
+ { "T5LFRC", 11, 1 },
+ { "T5LFSEL", 8, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x3fa9c, 0 },
+ { "OFFSN_ReadWrite", 14, 1 },
+ { "OFFSN_ReadOnly", 13, 1 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3faa0, 0 },
+ { "T5_RX_SETHDIS", 7, 1 },
+ { "T5_RX_PDTERM", 6, 1 },
+ { "T5_RX_BYPASS", 5, 1 },
+ { "T5_RX_LPFEN", 4, 1 },
+ { "T5_RX_VGABOD", 3, 1 },
+ { "T5_RX_VTBYP", 2, 1 },
+ { "T5_RX_VTERM", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x3faa4, 0 },
+ { "ISTRIMS", 14, 2 },
+ { "ISTRIM", 8, 6 },
+ { "HALF1", 7, 1 },
+ { "HALF2", 6, 1 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x3faa8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x3faac, 0 },
+ { "T5SMQM", 13, 3 },
+ { "T5SMQ", 5, 8 },
+ { "T5EMMD", 3, 2 },
+ { "T5EMBRDY", 2, 1 },
+ { "T5EMBUMP", 1, 1 },
+ { "T5EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3fab0, 0 },
+ { "EMF8", 15, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3fab4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3fab8, 0 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x3fac0, 0 },
+ { "H_EN", 1, 12 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x3fac4, 0 },
+ { "H1OSN", 14, 2 },
+ { "H1OMAG", 8, 6 },
+ { "H1ESN", 6, 2 },
+ { "H1EMAG", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x3fac8, 0 },
+ { "H2OSN_ReadWrite", 14, 1 },
+ { "H2OSN_ReadOnly", 13, 1 },
+ { "H2OMAG", 8, 5 },
+ { "H2ESN_ReadWrite", 6, 1 },
+ { "H2ESN_ReadOnly", 5, 1 },
+ { "H2EMAG", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x3facc, 0 },
+ { "H3OSN_ReadWrite", 13, 1 },
+ { "H3OSN_ReadOnly", 12, 1 },
+ { "H3OMAG", 8, 4 },
+ { "H3ESN_ReadWrite", 5, 1 },
+ { "H3ESN_ReadOnly", 4, 1 },
+ { "H3EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x3fad0, 0 },
+ { "H4OGS", 14, 2 },
+ { "H4OSN_ReadWrite", 13, 1 },
+ { "H4OSN_ReadOnly", 12, 1 },
+ { "H4OMAG", 8, 4 },
+ { "H4EGS", 6, 2 },
+ { "H4ESN_ReadWrite", 5, 1 },
+ { "H4ESN_ReadOnly", 4, 1 },
+ { "H4EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x3fad4, 0 },
+ { "H5OGS", 14, 2 },
+ { "H5OSN_ReadWrite", 13, 1 },
+ { "H5OSN_ReadOnly", 12, 1 },
+ { "H5OMAG", 8, 4 },
+ { "H5EGS", 6, 2 },
+ { "H5ESN_ReadWrite", 5, 1 },
+ { "H5ESN_ReadOnly", 4, 1 },
+ { "H5EMAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x3fad8, 0 },
+ { "H7GS", 14, 2 },
+ { "H7SN_ReadWrite", 13, 1 },
+ { "H7SN_ReadOnly", 12, 1 },
+ { "H7MAG", 8, 4 },
+ { "H6GS", 6, 2 },
+ { "H6SN_ReadWrite", 5, 1 },
+ { "H6SN_ReadOnly", 4, 1 },
+ { "H6MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x3fadc, 0 },
+ { "H9GS", 14, 2 },
+ { "H9SN_ReadWrite", 13, 1 },
+ { "H9SN_ReadOnly", 12, 1 },
+ { "H9MAG", 8, 4 },
+ { "H8GS", 6, 2 },
+ { "H8SN_ReadWrite", 5, 1 },
+ { "H8SN_ReadOnly", 4, 1 },
+ { "H8MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x3fae0, 0 },
+ { "H11GS", 14, 2 },
+ { "H11SN_ReadWrite", 13, 1 },
+ { "H11SN_ReadOnly", 12, 1 },
+ { "H11MAG", 8, 4 },
+ { "H10GS", 6, 2 },
+ { "H10SN_ReadWrite", 5, 1 },
+ { "H10SN_ReadOnly", 4, 1 },
+ { "H10MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x3fae4, 0 },
+ { "H12GS", 6, 2 },
+ { "H12SN_ReadWrite", 5, 1 },
+ { "H12SN_ReadOnly", 4, 1 },
+ { "H12MAG", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x3faf8, 0 },
+ { "DFEDACLSSD", 6, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x3fafc, 0 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "AMPSEL", 7, 1 },
+ { "WHICHNRZ", 6, 1 },
+ { "BANKA", 5, 1 },
+ { "BANKB", 4, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t5_mc_0_regs[] = {
+ { "MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS", 0x47000, 0 },
+ { "DP18_PLL_LOCK", 1, 15 },
+ { "MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS", 0x47004, 0 },
+ { "AD32S_PLL_LOCK", 14, 2 },
+ { "MC_DDRPHY_PC_RANK_PAIR0", 0x47008, 0 },
+ { "RANK_PAIR0_PRI", 13, 3 },
+ { "RANK_PAIR0_PRI_V", 12, 1 },
+ { "RANK_PAIR0_SEC", 9, 3 },
+ { "RANK_PAIR0_SEC_V", 8, 1 },
+ { "RANK_PAIR1_PRI", 5, 3 },
+ { "RANK_PAIR1_PRI_V", 4, 1 },
+ { "RANK_PAIR1_SEC", 1, 3 },
+ { "RANK_PAIR1_SEC_V", 0, 1 },
+ { "MC_DDRPHY_PC_RANK_PAIR1", 0x4700c, 0 },
+ { "RANK_PAIR2_PRI", 13, 3 },
+ { "RANK_PAIR2_PRI_V", 12, 1 },
+ { "RANK_PAIR2_SEC", 9, 3 },
+ { "RANK_PAIR2_SEC_V", 8, 1 },
+ { "RANK_PAIR3_PRI", 5, 3 },
+ { "RANK_PAIR3_PRI_V", 4, 1 },
+ { "RANK_PAIR3_SEC", 1, 3 },
+ { "RANK_PAIR3_SEC_V", 0, 1 },
+ { "MC_DDRPHY_PC_BASE_CNTR0", 0x47010, 0 },
+ { "MC_DDRPHY_PC_RELOAD_VALUE0", 0x47014, 0 },
+ { "PERIODIC_CAL_REQ_EN", 15, 1 },
+ { "PERIODIC_RELOAD_VALUE0", 0, 15 },
+ { "MC_DDRPHY_PC_BASE_CNTR1", 0x47018, 0 },
+ { "MC_DDRPHY_PC_CAL_TIMER", 0x4701c, 0 },
+ { "MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE", 0x47020, 0 },
+ { "MC_DDRPHY_PC_ZCAL_TIMER", 0x47024, 0 },
+ { "MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE", 0x47028, 0 },
+ { "MC_DDRPHY_PC_PER_CAL_CONFIG", 0x4702c, 0 },
+ { "PER_ENA_RANK_PAIR", 12, 4 },
+ { "PER_ENA_ZCAL", 11, 1 },
+ { "PER_ENA_SYSCLK_ALIGN", 10, 1 },
+ { "ENA_PER_READ_CTR", 9, 1 },
+ { "ENA_PER_RDCLK_ALIGN", 8, 1 },
+ { "ENA_PER_DQS_ALIGN", 7, 1 },
+ { "PER_NEXT_RANK_PAIR", 5, 2 },
+ { "FAST_SIM_PER_CNTR", 4, 1 },
+ { "START_INIT_CAL", 3, 1 },
+ { "START_PER_CAL", 2, 1 },
+ { "ABORT_ON_ERR_EN", 1, 1 },
+ { "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4703c, 0 },
+ { "PER_ZCAL_ENA_RANK", 8, 8 },
+ { "PER_ZCAL_NEXT_RANK", 5, 3 },
+ { "START_PER_ZCAL", 4, 1 },
+ { "MC_DDRPHY_PC_CONFIG0", 0x47030, 0 },
+ { "PROTOCOL_DDR", 12, 4 },
+ { "DATA_MUX4_1MODE", 11, 1 },
+ { "DDR4_CMD_SIG_REDUCTION", 9, 1 },
+ { "SYSCLK_2X_MEMINTCLKO", 8, 1 },
+ { "RANK_OVERRIDE", 7, 1 },
+ { "RANK_OVERRIDE_VALUE", 4, 3 },
+ { "LOW_LATENCY", 3, 1 },
+ { "DDR4_BANK_REFRESH", 2, 1 },
+ { "DDR4_VLEVEL_BANK_GROUP", 1, 1 },
+ { "MC_DDRPHY_PC_CONFIG1", 0x47034, 0 },
+ { "WRITE_LATENCY_OFFSET", 12, 4 },
+ { "READ_LATENCY_OFFSET", 8, 4 },
+ { "MEMCTL_CIC_FAST", 7, 1 },
+ { "MEMCTL_CTRN_IGNORE", 6, 1 },
+ { "DISABLE_MEMCTL_CAL", 5, 1 },
+ { "MC_DDRPHY_PC_RESETS", 0x47038, 0 },
+ { "PLL_RESET", 15, 1 },
+ { "SYSCLK_RESET", 14, 1 },
+ { "MC_DDRPHY_PC_ERROR_STATUS0", 0x47048, 0 },
+ { "RC_ERROR", 15, 1 },
+ { "WC_ERROR", 14, 1 },
+ { "SEQ_ERROR", 13, 1 },
+ { "CC_ERROR", 12, 1 },
+ { "APB_ERROR", 11, 1 },
+ { "PC_ERROR", 10, 1 },
+ { "MC_DDRPHY_PC_ERROR_MASK0", 0x4704c, 0 },
+ { "RC_ERROR_MASK", 15, 1 },
+ { "WC_ERROR_MASK", 14, 1 },
+ { "SEQ_ERROR_MASK", 13, 1 },
+ { "CC_ERROR_MASK", 12, 1 },
+ { "APB_ERROR_MASK", 11, 1 },
+ { "PC_ERROR_MASK", 10, 1 },
+ { "MC_DDRPHY_PC_IO_PVT_FET_CONTROL", 0x47050, 0 },
+ { "PVTP", 11, 5 },
+ { "PVTN", 6, 5 },
+ { "PVT_OVERRIDE", 5, 1 },
+ { "ENABLE_ZCAL", 4, 1 },
+ { "MC_DDRPHY_PC_VREF_DRV_CONTROL", 0x47054, 0 },
+ { "VREFDQ0DSGN", 15, 1 },
+ { "VREFDQ0D", 11, 4 },
+ { "VREFDQ1DSGN", 10, 1 },
+ { "VREFDQ1D", 6, 4 },
+ { "MC_DDRPHY_PC_INIT_CAL_CONFIG0", 0x47058, 0 },
+ { "ENA_WR_LEVEL", 15, 1 },
+ { "ENA_INITIAL_PAT_WR", 14, 1 },
+ { "ENA_DQS_ALIGN", 13, 1 },
+ { "ENA_RDCLK_ALIGN", 12, 1 },
+ { "ENA_READ_CTR", 11, 1 },
+ { "ENA_WRITE_CTR", 10, 1 },
+ { "ENA_INITIAL_COARSE_WR", 9, 1 },
+ { "ENA_COARSE_RD", 8, 1 },
+ { "ENA_CUSTOM_RD", 7, 1 },
+ { "ENA_CUSTOM_WR", 6, 1 },
+ { "ABORT_ON_CAL_ERROR", 5, 1 },
+ { "ENA_DIGITAL_EYE", 4, 1 },
+ { "ENA_RANK_PAIR", 0, 4 },
+ { "MC_DDRPHY_PC_INIT_CAL_CONFIG1", 0x4705c, 0 },
+ { "REFRESH_COUNT", 12, 4 },
+ { "REFRESH_CONTROL", 10, 2 },
+ { "REFRESH_ALL_RANKS", 9, 1 },
+ { "REFRESH_INTERVAL", 0, 7 },
+ { "MC_DDRPHY_PC_INIT_CAL_ERROR", 0x47060, 0 },
+ { "ERROR_WR_LEVEL", 15, 1 },
+ { "ERROR_INITIAL_PAT_WRITE", 14, 1 },
+ { "ERROR_DQS_ALIGN", 13, 1 },
+ { "ERROR_RDCLK_ALIGN", 12, 1 },
+ { "ERROR_READ_CTR", 11, 1 },
+ { "ERROR_WRITE_CTR", 10, 1 },
+ { "ERROR_INITIAL_COARSE_WR", 9, 1 },
+ { "ERROR_COARSE_RD", 8, 1 },
+ { "ERROR_CUSTOM_RD", 7, 1 },
+ { "ERROR_CUSTOM_WR", 6, 1 },
+ { "ERROR_DIGITAL_EYE", 5, 1 },
+ { "ERROR_RANK_PAIR", 0, 4 },
+ { "MC_DDRPHY_PC_INIT_CAL_MASK", 0x47068, 0 },
+ { "ERROR_WR_LEVEL_MASK", 15, 1 },
+ { "ERROR_INITIAL_PAT_WRITE_MASK", 14, 1 },
+ { "ERROR_DQS_ALIGN_MASK", 13, 1 },
+ { "ERROR_RDCLK_ALIGN_MASK", 12, 1 },
+ { "ERROR_READ_CTR_MASK", 11, 1 },
+ { "ERROR_WRITE_CTR_MASK", 10, 1 },
+ { "ERROR_INITIAL_COARSE_WR_MASK", 9, 1 },
+ { "ERROR_COARSE_RD_MASK", 8, 1 },
+ { "ERROR_CUSTOM_RD_MASK", 7, 1 },
+ { "ERROR_CUSTOM_WR_MASK", 6, 1 },
+ { "ERROR_DIGITAL_EYE_MASK", 5, 1 },
+ { "MC_DDRPHY_PC_INIT_CAL_STATUS", 0x47064, 0 },
+ { "INIT_CAL_COMPLETE", 12, 4 },
+ { "MC_DDRPHY_PC_IO_PVT_FET_STATUS", 0x4706c, 0 },
+ { "PVTP", 11, 5 },
+ { "PVTN", 6, 5 },
+ { "MC_DDRPHY_PC_MR0_PRI_RP", 0x47070, 0 },
+ { "MC_DDRPHY_PC_MR1_PRI_RP", 0x47074, 0 },
+ { "MC_DDRPHY_PC_MR2_PRI_RP", 0x47078, 0 },
+ { "MC_DDRPHY_PC_MR3_PRI_RP", 0x4707c, 0 },
+ { "MC_DDRPHY_PC_MR0_SEC_RP", 0x47080, 0 },
+ { "MC_DDRPHY_PC_MR1_SEC_RP", 0x47084, 0 },
+ { "MC_DDRPHY_PC_MR2_SEC_RP", 0x47088, 0 },
+ { "MC_DDRPHY_PC_MR3_SEC_RP", 0x4708c, 0 },
+ { "MC_DDRPHY_PC_RANK_GROUP", 0x47044, 0 },
+ { "ADDR_MIRROR_RP0_PRI", 15, 1 },
+ { "ADDR_MIRROR_RP0_SEC", 14, 1 },
+ { "ADDR_MIRROR_RP1_PRI", 13, 1 },
+ { "ADDR_MIRROR_RP1_SEC", 12, 1 },
+ { "ADDR_MIRROR_RP2_PRI", 11, 1 },
+ { "ADDR_MIRROR_RP2_SEC", 10, 1 },
+ { "ADDR_MIRROR_RP3_PRI", 9, 1 },
+ { "ADDR_MIRROR_RP3_SEC", 8, 1 },
+ { "RANK_GROUPING", 6, 2 },
+ { "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45000, 0 },
+ { "BIT_ENABLE_0_11", 4, 12 },
+ { "BIT_ENABLE_12_15", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45004, 0 },
+ { "DI_ADR0_ADR1", 15, 1 },
+ { "DI_ADR2_ADR3", 14, 1 },
+ { "DI_ADR4_ADR5", 13, 1 },
+ { "DI_ADR6_ADR7", 12, 1 },
+ { "DI_ADR8_ADR9", 11, 1 },
+ { "DI_ADR10_ADR11", 10, 1 },
+ { "DI_ADR12_ADR13", 9, 1 },
+ { "DI_ADR14_ADR15", 8, 1 },
+ { "MC_ADR_DDRPHY_ADR_DELAY0", 0x45010, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY1", 0x45014, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY2", 0x45018, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY3", 0x4501c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY4", 0x45020, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY5", 0x45024, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY6", 0x45028, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY7", 0x4502c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45030, 0 },
+ { "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
+ { "ADR_TEST_DATA_EN", 7, 1 },
+ { "DADR_TEST_MODE", 5, 2 },
+ { "ADR_TEST_4TO1_MODE", 4, 1 },
+ { "ADR_TEST_RESET", 3, 1 },
+ { "ADR_TEST_GEN_EN", 2, 1 },
+ { "ADR_TEST_CLEAR_ERROR", 1, 1 },
+ { "ADR_TEST_CHECK_EN", 0, 1 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45040, 0 },
+ { "EN_SLICE_N_WR_0", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45044, 0 },
+ { "EN_SLICE_N_WR_1", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45048, 0 },
+ { "EN_SLICE_N_WR_2", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4504c, 0 },
+ { "EN_SLICE_N_WR_3", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45050, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45054, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45058, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4505c, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45080, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45084, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45060, 0 },
+ { "POST_CURSOR0", 12, 4 },
+ { "POST_CURSOR1", 8, 4 },
+ { "POST_CURSOR2", 4, 4 },
+ { "POST_CURSOR3", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x450a0, 0 },
+ { "POST_CUR_SEL_BITS0_1", 14, 2 },
+ { "POST_CUR_SEL_BITS2_3", 12, 2 },
+ { "POST_CUR_SEL_BITS4_5", 10, 2 },
+ { "POST_CUR_SEL_BITS6_7", 8, 2 },
+ { "POST_CUR_SEL_BITS8_9", 6, 2 },
+ { "POST_CUR_SEL_BITS10_11", 4, 2 },
+ { "POST_CUR_SEL_BITS12_13", 2, 2 },
+ { "POST_CUR_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x450a4, 0 },
+ { "POST_CUR_SEL_BITS0_1", 14, 2 },
+ { "POST_CUR_SEL_BITS2_3", 12, 2 },
+ { "POST_CUR_SEL_BITS4_5", 10, 2 },
+ { "POST_CUR_SEL_BITS6_7", 8, 2 },
+ { "POST_CUR_SEL_BITS8_9", 6, 2 },
+ { "POST_CUR_SEL_BITS10_11", 4, 2 },
+ { "POST_CUR_SEL_BITS12_13", 2, 2 },
+ { "POST_CUR_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45068, 0 },
+ { "SLEW_CTL0", 12, 4 },
+ { "SLEW_CTL1", 8, 4 },
+ { "SLEW_CTL2", 4, 4 },
+ { "SLEW_CTL3", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x450a8, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x450ac, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x450b0, 0 },
+ { "ADR_LANE_0_11_PD", 4, 12 },
+ { "ADR_LANE_12_15_PD", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45200, 0 },
+ { "BIT_ENABLE_0_11", 4, 12 },
+ { "BIT_ENABLE_12_15", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45204, 0 },
+ { "DI_ADR0_ADR1", 15, 1 },
+ { "DI_ADR2_ADR3", 14, 1 },
+ { "DI_ADR4_ADR5", 13, 1 },
+ { "DI_ADR6_ADR7", 12, 1 },
+ { "DI_ADR8_ADR9", 11, 1 },
+ { "DI_ADR10_ADR11", 10, 1 },
+ { "DI_ADR12_ADR13", 9, 1 },
+ { "DI_ADR14_ADR15", 8, 1 },
+ { "MC_ADR_DDRPHY_ADR_DELAY0", 0x45210, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY1", 0x45214, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY2", 0x45218, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY3", 0x4521c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY4", 0x45220, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY5", 0x45224, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY6", 0x45228, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY7", 0x4522c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45230, 0 },
+ { "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
+ { "ADR_TEST_DATA_EN", 7, 1 },
+ { "DADR_TEST_MODE", 5, 2 },
+ { "ADR_TEST_4TO1_MODE", 4, 1 },
+ { "ADR_TEST_RESET", 3, 1 },
+ { "ADR_TEST_GEN_EN", 2, 1 },
+ { "ADR_TEST_CLEAR_ERROR", 1, 1 },
+ { "ADR_TEST_CHECK_EN", 0, 1 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45240, 0 },
+ { "EN_SLICE_N_WR_0", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45244, 0 },
+ { "EN_SLICE_N_WR_1", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45248, 0 },
+ { "EN_SLICE_N_WR_2", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4524c, 0 },
+ { "EN_SLICE_N_WR_3", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45250, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45254, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45258, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4525c, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45280, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45284, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45260, 0 },
+ { "POST_CURSOR0", 12, 4 },
+ { "POST_CURSOR1", 8, 4 },
+ { "POST_CURSOR2", 4, 4 },
+ { "POST_CURSOR3", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x452a0, 0 },
+ { "POST_CUR_SEL_BITS0_1", 14, 2 },
+ { "POST_CUR_SEL_BITS2_3", 12, 2 },
+ { "POST_CUR_SEL_BITS4_5", 10, 2 },
+ { "POST_CUR_SEL_BITS6_7", 8, 2 },
+ { "POST_CUR_SEL_BITS8_9", 6, 2 },
+ { "POST_CUR_SEL_BITS10_11", 4, 2 },
+ { "POST_CUR_SEL_BITS12_13", 2, 2 },
+ { "POST_CUR_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x452a4, 0 },
+ { "POST_CUR_SEL_BITS0_1", 14, 2 },
+ { "POST_CUR_SEL_BITS2_3", 12, 2 },
+ { "POST_CUR_SEL_BITS4_5", 10, 2 },
+ { "POST_CUR_SEL_BITS6_7", 8, 2 },
+ { "POST_CUR_SEL_BITS8_9", 6, 2 },
+ { "POST_CUR_SEL_BITS10_11", 4, 2 },
+ { "POST_CUR_SEL_BITS12_13", 2, 2 },
+ { "POST_CUR_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45268, 0 },
+ { "SLEW_CTL0", 12, 4 },
+ { "SLEW_CTL1", 8, 4 },
+ { "SLEW_CTL2", 4, 4 },
+ { "SLEW_CTL3", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x452a8, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x452ac, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x452b0, 0 },
+ { "ADR_LANE_0_11_PD", 4, 12 },
+ { "ADR_LANE_12_15_PD", 0, 4 },
+ { "MC_DDRPHY_ADR_PLL_VREG_CONFIG_0", 0x460c0, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_ADR_PLL_VREG_CONFIG_1", 0x460c4, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "VREG_VREGSPARE", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "INTERP_SIG_SLEW_0_3", 1, 4 },
+ { "ANALOG_WRAPON", 0, 1 },
+ { "MC_DDRPHY_ADR_SYSCLK_CNTL_PR", 0x460c8, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESE", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "CE0DLTVCC", 0, 2 },
+ { "MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET", 0x460cc, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO", 0x460d0, 0 },
+ { "SLEW_LATE_SAMPLE", 15, 1 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "SLEW_EARLY_SAMPLE", 6, 1 },
+ { "SLEW_DONE_STATUS", 4, 2 },
+ { "SLEW_CNTL", 0, 4 },
+ { "MC_DDRPHY_ADR_GMTEST_ATEST_CNTL", 0x460d4, 0 },
+ { "FLUSH", 15, 1 },
+ { "GIANT_MUX_TEST_EN", 14, 1 },
+ { "GIANT_MUX_TEST_VAL", 13, 1 },
+ { "HS_PROBE_A_SEL_", 8, 4 },
+ { "HS_PROBE_B_SEL_", 4, 4 },
+ { "ATEST1CTL0", 3, 1 },
+ { "ATEST1CTL1", 2, 1 },
+ { "ATEST1CTL2", 1, 1 },
+ { "ATEST1CTL3", 0, 1 },
+ { "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0", 0x460d8, 0 },
+ { "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1", 0x460dc, 0 },
+ { "MC_DDRPHY_ADR_POWERDOWN_1", 0x460e0, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_ADR_SLEW_CAL_CNTL", 0x460e4, 0 },
+ { "SLEW_CAL_ENABLE", 15, 1 },
+ { "SLEW_CAL_START", 14, 1 },
+ { "SLEW_CAL_OVERRIDE_EN", 12, 1 },
+ { "SLEW_CAL_OVERRIDE", 8, 4 },
+ { "SLEW_TARGET_PR_OFFSET", 0, 5 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44000, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44004, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "WRAPSEL", 5, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x441f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x441f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44008, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4400c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44010, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44014, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x441f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44018, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4401c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x441cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x441d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x440c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x440c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44024, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44170, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44174, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x440e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x440e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x440e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x440ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x440f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x440f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x440f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x440fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44100, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44104, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44108, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4410c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44110, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44114, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44118, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4411c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44120, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44124, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44128, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4412c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44130, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44134, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44138, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4413c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44140, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44144, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44148, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4414c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44150, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44154, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44158, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4415c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44160, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44164, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44168, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4416c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44030, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44034, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x441c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x441c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x441c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44180, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44184, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44188, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4418c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44190, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44194, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44198, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4419c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x441a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x441a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x441a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x441ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44028, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44038, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4403c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44040, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44044, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4404c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44050, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44054, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4405c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44060, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "DDONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44064, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44068, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4406c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44070, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x441d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x441dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x441e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x441e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x441e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x441ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x441d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44074, 0 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44020, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x440c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x440cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x440d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44078, 0 },
+ { "SYSCLK_RDCLK_OFFSET", 8, 7 },
+ { "SYSCLK_DQSCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x440d4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x440d8, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x441b4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x441b8, 0 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x440dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4402c, 0 },
+ { "HS_PROBE_A_SEL", 11, 5 },
+ { "HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x441fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44048, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DYN_MCTERM_CNTL_EN", 14, 1 },
+ { "DYN_RX_GATE_CNTL_EN", 13, 1 },
+ { "CALGATE_ON", 12, 1 },
+ { "PER_RDCLK_UPDATE_DIS", 11, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44200, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44204, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "WRAPSEL", 5, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x443f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x443f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44208, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4420c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44210, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44214, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x443f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44218, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4421c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x443cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x443d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x442c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x442c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44224, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44370, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44374, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x442e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x442e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x442e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x442ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x442f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x442f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x442f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x442fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44300, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44304, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44308, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4430c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44310, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44314, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44318, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4431c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44320, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44324, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44328, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4432c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44330, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44334, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44338, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4433c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44340, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44344, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44348, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4434c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44350, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44354, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44358, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4435c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44360, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44364, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44368, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4436c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44230, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44234, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x443c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x443c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x443c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44380, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44384, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44388, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4438c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44390, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44394, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44398, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4439c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x443a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x443a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x443a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x443ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44228, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44238, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4423c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44240, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44244, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4424c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44250, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44254, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4425c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44260, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "DDONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44264, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44268, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4426c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44270, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x443d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x443dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x443e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x443e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x443e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x443ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x443d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44274, 0 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44220, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x442c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x442cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x442d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44278, 0 },
+ { "SYSCLK_RDCLK_OFFSET", 8, 7 },
+ { "SYSCLK_DQSCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x442d4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x442d8, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x443b4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x443b8, 0 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x442dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4422c, 0 },
+ { "HS_PROBE_A_SEL", 11, 5 },
+ { "HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x443fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44248, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DYN_MCTERM_CNTL_EN", 14, 1 },
+ { "DYN_RX_GATE_CNTL_EN", 13, 1 },
+ { "CALGATE_ON", 12, 1 },
+ { "PER_RDCLK_UPDATE_DIS", 11, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44400, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44404, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "WRAPSEL", 5, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x445f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x445f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44408, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4440c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44410, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44414, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x445f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44418, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4441c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x445cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x445d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x444c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x444c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44424, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44570, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44574, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x444e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x444e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x444e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x444ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x444f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x444f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x444f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x444fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44500, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44504, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44508, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4450c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44510, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44514, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44518, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4451c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44520, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44524, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44528, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4452c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44530, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44534, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44538, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4453c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44540, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44544, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44548, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4454c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44550, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44554, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44558, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4455c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44560, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44564, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44568, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4456c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44430, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44434, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x445c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x445c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x445c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44580, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44584, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44588, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4458c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44590, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44594, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44598, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4459c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x445a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x445a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x445a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x445ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44428, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44438, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4443c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44440, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44444, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4444c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44450, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44454, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4445c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44460, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "DDONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44464, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44468, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4446c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44470, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x445d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x445dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x445e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x445e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x445e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x445ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x445d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44474, 0 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44420, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x444c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x444cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x444d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44478, 0 },
+ { "SYSCLK_RDCLK_OFFSET", 8, 7 },
+ { "SYSCLK_DQSCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x444d4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x444d8, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x445b4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x445b8, 0 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x444dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4442c, 0 },
+ { "HS_PROBE_A_SEL", 11, 5 },
+ { "HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x445fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44448, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DYN_MCTERM_CNTL_EN", 14, 1 },
+ { "DYN_RX_GATE_CNTL_EN", 13, 1 },
+ { "CALGATE_ON", 12, 1 },
+ { "PER_RDCLK_UPDATE_DIS", 11, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44600, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44604, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "WRAPSEL", 5, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x447f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x447f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44608, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4460c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44610, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44614, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x447f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44618, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4461c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x447cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x447d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x446c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x446c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44624, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44770, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44774, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x446e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x446e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x446e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x446ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x446f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x446f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x446f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x446fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44700, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44704, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44708, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4470c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44710, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44714, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44718, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4471c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44720, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44724, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44728, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4472c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44730, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44734, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44738, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4473c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44740, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44744, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44748, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4474c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44750, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44754, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44758, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4475c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44760, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44764, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44768, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4476c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44630, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44634, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x447c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x447c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x447c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44780, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44784, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44788, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4478c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44790, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44794, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44798, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4479c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x447a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x447a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x447a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x447ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44628, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44638, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4463c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44640, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44644, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4464c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44650, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44654, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4465c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44660, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "DDONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44664, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44668, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4466c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44670, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x447d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x447dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x447e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x447e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x447e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x447ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x447d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44674, 0 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44620, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x446c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x446cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x446d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44678, 0 },
+ { "SYSCLK_RDCLK_OFFSET", 8, 7 },
+ { "SYSCLK_DQSCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x446d4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x446d8, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x447b4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x447b8, 0 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x446dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4462c, 0 },
+ { "HS_PROBE_A_SEL", 11, 5 },
+ { "HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x447fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44648, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DYN_MCTERM_CNTL_EN", 14, 1 },
+ { "DYN_RX_GATE_CNTL_EN", 13, 1 },
+ { "CALGATE_ON", 12, 1 },
+ { "PER_RDCLK_UPDATE_DIS", 11, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44800, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44804, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "WRAPSEL", 5, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x449f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x449f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44808, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4480c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44810, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44814, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x449f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44818, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4481c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x449cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x449d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x448c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x448c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44824, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44970, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44974, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x448e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x448e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x448e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x448ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x448f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x448f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x448f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x448fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44900, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44904, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44908, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4490c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44910, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44914, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44918, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4491c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44920, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44924, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44928, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4492c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44930, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44934, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44938, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4493c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44940, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44944, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44948, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4494c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44950, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44954, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44958, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4495c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44960, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44964, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44968, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4496c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44830, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44834, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x449c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x449c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x449c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44980, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44984, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44988, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4498c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44990, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44994, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44998, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4499c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x449a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x449a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x449a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x449ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44828, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44838, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4483c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44840, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44844, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4484c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44850, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44854, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4485c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44860, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "DDONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44864, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44868, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4486c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44870, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x449d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x449dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x449e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x449e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x449e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x449ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x449d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44874, 0 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44820, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x448c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x448cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x448d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44878, 0 },
+ { "SYSCLK_RDCLK_OFFSET", 8, 7 },
+ { "SYSCLK_DQSCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x448d4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x448d8, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x449b4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x449b8, 0 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x448dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4482c, 0 },
+ { "HS_PROBE_A_SEL", 11, 5 },
+ { "HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x449fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44848, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DYN_MCTERM_CNTL_EN", 14, 1 },
+ { "DYN_RX_GATE_CNTL_EN", 13, 1 },
+ { "CALGATE_ON", 12, 1 },
+ { "PER_RDCLK_UPDATE_DIS", 11, 1 },
+ { "MC_DDRPHY_SEQ_RD_WR_DATA0", 0x47200, 0 },
+ { "MC_DDRPHY_SEQ_RD_WR_DATA1", 0x47204, 0 },
+ { "MC_DDRPHY_SEQ_CONFIG0", 0x47208, 0 },
+ { "MPR_PATTERN_BIT", 15, 1 },
+ { "TWO_CYCLE_ADDR_EN", 14, 1 },
+ { "MR_MASK_EN", 10, 4 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR0", 0x4720c, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR1", 0x47210, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR2", 0x47214, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR3", 0x47218, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR4", 0x4721c, 0 },
+ { "MC_DDRPHY_SEQ_ERROR_STATUS0", 0x47220, 0 },
+ { "MULTIPLE_REQ_ERROR", 15, 1 },
+ { "INVALID_REQTYPE_ERRO", 14, 1 },
+ { "EARLY_REQ_ERROR", 13, 1 },
+ { "MULTIPLE_REQ_SOURCE", 10, 3 },
+ { "INVALID_REQTYPE", 6, 4 },
+ { "INVALID_REQ_SOURCE", 3, 3 },
+ { "EARLY_REQ_SOURCE", 0, 3 },
+ { "MC_DDRPHY_SEQ_ERROR_MASK0", 0x47224, 0 },
+ { "MULT_REQ_ERR_MASK", 15, 1 },
+ { "INVALID_REQTYPE_ERR_MASK", 14, 1 },
+ { "EARLY_REQ_ERR_MASK", 13, 1 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG0", 0x47228, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG1", 0x4722c, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG2", 0x47230, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG3", 0x47234, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG0", 0x47238, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG1", 0x4723c, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG2", 0x47240, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG3", 0x47244, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM0", 0x47248, 0 },
+ { "TMOD_CYCLES", 12, 4 },
+ { "TRCD_CYCLES", 8, 4 },
+ { "TRP_CYCLES", 4, 4 },
+ { "TRFC_CYCLES", 0, 4 },
+ { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM1", 0x4724c, 0 },
+ { "TZQINIT_CYCLES", 12, 4 },
+ { "TZQCS_CYCLES", 8, 4 },
+ { "TWLDQSEN_CYCLES", 4, 4 },
+ { "TWRMRD_CYCLES", 0, 4 },
+ { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM2", 0x47250, 0 },
+ { "TODTLON_OFF_CYCLES", 12, 4 },
+ { "TRC_CYCLES", 8, 4 },
+ { "TMRSC_CYCLES", 4, 4 },
+ { "MC_DDRPHY_WC_CONFIG0", 0x47600, 0 },
+ { "TWLO_TWLOE", 8, 8 },
+ { "WL_ONE_DQS_PULSE", 7, 1 },
+ { "FW_WR_RD", 1, 6 },
+ { "CUSTOM_INIT_WRITE", 0, 1 },
+ { "MC_DDRPHY_WC_CONFIG1", 0x47604, 0 },
+ { "BIG_STEP", 12, 4 },
+ { "SMALL_STEP", 9, 3 },
+ { "WR_PRE_DLY", 3, 6 },
+ { "MC_DDRPHY_WC_CONFIG2", 0x47608, 0 },
+ { "NUM_VALID_SAMPLES", 12, 4 },
+ { "FW_RD_WR", 6, 6 },
+ { "EN_RESET_WR_DELAY_WL", 0, 1 },
+ { "MC_DDRPHY_WC_CONFIG3", 0x47614, 0 },
+ { "DDR4_MRS_CMD_DQ_EN", 15, 1 },
+ { "MRS_CMD_DQ_ON", 9, 6 },
+ { "MRS_CMD_DQ_OFF", 3, 6 },
+ { "MC_DDRPHY_WC_WRCLK_CNTL", 0x47618, 0 },
+ { "WRCLK_CAL_START", 15, 1 },
+ { "WRCLK_CAL_DONE", 14, 1 },
+ { "MC_DDRPHY_WC_ERROR_STATUS0", 0x4760c, 0 },
+ { "WR_CNTL_ERROR", 15, 1 },
+ { "MC_DDRPHY_WC_ERROR_MASK0", 0x47610, 0 },
+ { "WR_CNTL_ERROR_MASK", 15, 1 },
+ { "MC_DDRPHY_RC_CONFIG0", 0x47400, 0 },
+ { "GLOBAL_PHY_OFFSET", 12, 4 },
+ { "ADVANCE_RD_VALID", 11, 1 },
+ { "SINGLE_BIT_MPR_RP0", 6, 1 },
+ { "SINGLE_BIT_MPR_RP1", 5, 1 },
+ { "SINGLE_BIT_MPR_RP2", 4, 1 },
+ { "SINGLE_BIT_MPR_RP3", 3, 1 },
+ { "ALIGN_ON_EVEN_CYCLES", 2, 1 },
+ { "PERFORM_RDCLK_ALIGN", 1, 1 },
+ { "STAGGERED_PATTERN", 0, 1 },
+ { "MC_DDRPHY_RC_CONFIG1", 0x47404, 0 },
+ { "OUTER_LOOP_CNT", 2, 14 },
+ { "MC_DDRPHY_RC_CONFIG2", 0x47408, 0 },
+ { "CONSEQ_PASS", 11, 5 },
+ { "BURST_WINDOW", 5, 2 },
+ { "ALLOW_RD_FIFO_AUTO_R_ESET", 4, 1 },
+ { "MC_DDRPHY_RC_CONFIG3", 0x4741c, 0 },
+ { "FINE_CAL_STEP_SIZE", 13, 3 },
+ { "COARSE_CAL_STEP_SIZE", 9, 4 },
+ { "DQ_SEL_QUAD", 7, 2 },
+ { "DQ_SEL_LANE", 4, 3 },
+ { "MC_DDRPHY_RC_PERIODIC", 0x47420, 0 },
+ { "MC_DDRPHY_RC_ERROR_STATUS0", 0x47414, 0 },
+ { "RD_CNTL_ERROR", 15, 1 },
+ { "MC_DDRPHY_RC_ERROR_MASK0", 0x47418, 0 },
+ { "RD_CNTL_ERROR_MASK", 15, 1 },
+ { "MC_DDRPHY_APB_CONFIG0", 0x47800, 0 },
+ { "DISABLE_PARITY_CHECKER", 15, 1 },
+ { "GENERATE_EVEN_PARITY", 14, 1 },
+ { "FORCE_ON_CLK_GATE", 13, 1 },
+ { "DEBUG_BUS_SEL_LO", 12, 1 },
+ { "DEBUG_BUS_SEL_HI", 8, 4 },
+ { "MC_DDRPHY_APB_ERROR_STATUS0", 0x47804, 0 },
+ { "INVALID_ADDRESS", 15, 1 },
+ { "WR_PAR_ERR", 14, 1 },
+ { "MC_DDRPHY_APB_ERROR_MASK0", 0x47808, 0 },
+ { "INVALID_ADDRESS_MASK", 15, 1 },
+ { "WR_PAR_ERR_MASK", 14, 1 },
+ { "MC_DDRPHY_APB_DP18_POPULATION", 0x4780c, 0 },
+ { "DP18_0_Populated", 15, 1 },
+ { "DP18_1_Populated", 14, 1 },
+ { "DP18_2_Populated", 13, 1 },
+ { "DP18_3_Populated", 12, 1 },
+ { "DP18_4_Populated", 11, 1 },
+ { "DP18_5_Populated", 10, 1 },
+ { "DP18_6_Populated", 9, 1 },
+ { "DP18_7_Populated", 8, 1 },
+ { "DP18_8_Populated", 7, 1 },
+ { "DP18_9_Populated", 6, 1 },
+ { "DP18_10_Populated", 5, 1 },
+ { "DP18_11_Populated", 4, 1 },
+ { "DP18_12_Populated", 3, 1 },
+ { "DP18_13_Populated", 2, 1 },
+ { "DP18_14_Populated", 1, 1 },
+ { "MC_DDRPHY_APB_ADR_POPULATION", 0x47810, 0 },
+ { "ADR16_0_Populated", 15, 1 },
+ { "ADR16_1_Populated", 14, 1 },
+ { "ADR16_2_Populated", 13, 1 },
+ { "ADR16_3_Populated", 12, 1 },
+ { "ADR12_0_Populated", 7, 1 },
+ { "ADR12_1_Populated", 6, 1 },
+ { "ADR12_2_Populated", 5, 1 },
+ { "ADR12_3_Populated", 4, 1 },
+ { "MC_DDRPHY_APB_ATEST_MUX_SEL", 0x47814, 0 },
+ { "ATEST_CNTL", 10, 6 },
+ { "MC_UPCTL_SCFG", 0x40000, 0 },
+ { "bbflags_timing", 8, 4 },
+ { "nfifo_nif1_dis", 6, 1 },
+ { "hw_low_power_en", 0, 1 },
+ { "MC_UPCTL_SCTL", 0x40004, 0 },
+ { "MC_UPCTL_STAT", 0x40008, 0 },
+ { "lp_trig", 4, 3 },
+ { "ctl_stat", 0, 3 },
+ { "MC_UPCTL_INTRSTAT", 0x4000c, 0 },
+ { "parity_intr", 1, 1 },
+ { "ecc_intr", 0, 1 },
+ { "MC_UPCTL_MCMD", 0x40040, 0 },
+ { "start_cmd", 31, 1 },
+ { "cmd_add_del", 24, 4 },
+ { "rank_sel", 20, 4 },
+ { "bank_addr", 17, 3 },
+ { "cmd_addr", 4, 13 },
+ { "cmd_opcode0", 0, 4 },
+ { "MC_UPCTL_POWCTL", 0x40044, 0 },
+ { "MC_UPCTL_POWSTAT", 0x40048, 0 },
+ { "MC_UPCTL_CMDTSTAT", 0x4004c, 0 },
+ { "MC_UPCTL_CMDTSTATEN", 0x40050, 0 },
+ { "MC_UPCTL_MRRCFG0", 0x40060, 0 },
+ { "MC_UPCTL_MRRSTAT0", 0x40064, 0 },
+ { "mrrstat_beat3", 24, 8 },
+ { "mrrstat_beat2", 16, 8 },
+ { "mrrstat_beat1", 8, 8 },
+ { "mrrstat_beat0", 0, 8 },
+ { "MC_UPCTL_MRRSTAT1", 0x40068, 0 },
+ { "mrrstat_beat7", 24, 8 },
+ { "mrrstat_beat6", 16, 8 },
+ { "mrrstat_beat5", 8, 8 },
+ { "mrrstat_beat4", 0, 8 },
+ { "MC_UPCTL_MCFG1", 0x4007c, 0 },
+ { "hw_exit_idle_en", 31, 1 },
+ { "hw_idle", 16, 8 },
+ { "sr_idle", 0, 8 },
+ { "MC_UPCTL_MCFG", 0x40080, 0 },
+ { "mddr_lpddr2_clk_stop_idle", 24, 8 },
+ { "mddr_lpddr2_en", 22, 2 },
+ { "mddr_lpddr2_bl", 20, 2 },
+ { "tfaw_cfg", 18, 2 },
+ { "pd_exit_mode", 17, 1 },
+ { "pd_type", 16, 1 },
+ { "pd_idle", 8, 8 },
+ { "lpddr2_s4", 6, 1 },
+ { "ddr3_en", 5, 1 },
+ { "stagger_cs", 4, 1 },
+ { "two_t_en", 3, 1 },
+ { "bl8int_en", 2, 1 },
+ { "cke_or_en", 1, 1 },
+ { "mem_bl", 0, 1 },
+ { "MC_UPCTL_PPCFG", 0x40084, 0 },
+ { "rpmem_dis", 1, 8 },
+ { "ppmem_en", 0, 1 },
+ { "MC_UPCTL_MSTAT", 0x40088, 0 },
+ { "self_refresh", 2, 1 },
+ { "clock_stop", 1, 1 },
+ { "power_down", 0, 1 },
+ { "MC_UPCTL_LPDDR2ZQCFG", 0x4008c, 0 },
+ { "zqcl_op", 24, 8 },
+ { "zqcl_ma", 16, 8 },
+ { "zqcs_op", 8, 8 },
+ { "zqcs_ma", 0, 8 },
+ { "MC_UPCTL_DTUPDES", 0x40094, 0 },
+ { "dtu_rd_missing", 13, 1 },
+ { "dtu_eaffl", 9, 4 },
+ { "dtu_random_error", 8, 1 },
+ { "dtu_err_b7", 7, 1 },
+ { "dtu_err_b6", 6, 1 },
+ { "dtu_err_b5", 5, 1 },
+ { "dtu_err_b4", 4, 1 },
+ { "dtu_err_b3", 3, 1 },
+ { "dtu_err_b2", 2, 1 },
+ { "dtu_err_b1", 1, 1 },
+ { "dtu_err_b0", 0, 1 },
+ { "MC_UPCTL_DTUNA", 0x40098, 0 },
+ { "MC_UPCTL_DTUNE", 0x4009c, 0 },
+ { "MC_UPCTL_DTUPRD0", 0x400a0, 0 },
+ { "dtu_allbits_1", 16, 16 },
+ { "dtu_allbits_0", 0, 16 },
+ { "MC_UPCTL_DTUPRD1", 0x400a4, 0 },
+ { "dtu_allbits_3", 16, 16 },
+ { "dtu_allbits_2", 0, 16 },
+ { "MC_UPCTL_DTUPRD2", 0x400a8, 0 },
+ { "dtu_allbits_5", 16, 16 },
+ { "dtu_allbits_4", 0, 16 },
+ { "MC_UPCTL_DTUPRD3", 0x400ac, 0 },
+ { "dtu_allbits_7", 16, 16 },
+ { "dtu_allbits_6", 0, 16 },
+ { "MC_UPCTL_DTUAWDT", 0x400b0, 0 },
+ { "number_ranks", 9, 2 },
+ { "row_addr_width", 6, 2 },
+ { "bank_addr_width", 3, 2 },
+ { "column_addr_width", 0, 2 },
+ { "MC_UPCTL_TOGCNT1U", 0x400c0, 0 },
+ { "MC_UPCTL_TINIT", 0x400c4, 0 },
+ { "MC_UPCTL_TRSTH", 0x400c8, 0 },
+ { "MC_UPCTL_TOGCNT100N", 0x400cc, 0 },
+ { "MC_UPCTL_TREFI", 0x400d0, 0 },
+ { "MC_UPCTL_TMRD", 0x400d4, 0 },
+ { "MC_UPCTL_TRFC", 0x400d8, 0 },
+ { "MC_UPCTL_TRP", 0x400dc, 0 },
+ { "prea_extra", 16, 2 },
+ { "t_rp", 0, 4 },
+ { "MC_UPCTL_TRTW", 0x400e0, 0 },
+ { "MC_UPCTL_TAL", 0x400e4, 0 },
+ { "MC_UPCTL_TCL", 0x400e8, 0 },
+ { "MC_UPCTL_TCWL", 0x400ec, 0 },
+ { "MC_UPCTL_TRAS", 0x400f0, 0 },
+ { "MC_UPCTL_TRC", 0x400f4, 0 },
+ { "MC_UPCTL_TRCD", 0x400f8, 0 },
+ { "MC_UPCTL_TRRD", 0x400fc, 0 },
+ { "MC_UPCTL_TRTP", 0x40100, 0 },
+ { "MC_UPCTL_TWR", 0x40104, 0 },
+ { "MC_UPCTL_TWTR", 0x40108, 0 },
+ { "MC_UPCTL_TEXSR", 0x4010c, 0 },
+ { "MC_UPCTL_TXP", 0x40110, 0 },
+ { "MC_UPCTL_TXPDLL", 0x40114, 0 },
+ { "MC_UPCTL_TZQCS", 0x40118, 0 },
+ { "MC_UPCTL_TZQCSI", 0x4011c, 0 },
+ { "MC_UPCTL_TDQS", 0x40120, 0 },
+ { "MC_UPCTL_TCKSRE", 0x40124, 0 },
+ { "MC_UPCTL_TCKSRX", 0x40128, 0 },
+ { "MC_UPCTL_TCKE", 0x4012c, 0 },
+ { "MC_UPCTL_TMOD", 0x40130, 0 },
+ { "MC_UPCTL_TRSTL", 0x40134, 0 },
+ { "MC_UPCTL_TZQCL", 0x40138, 0 },
+ { "MC_UPCTL_TMRR", 0x4013c, 0 },
+ { "MC_UPCTL_TCKESR", 0x40140, 0 },
+ { "MC_UPCTL_TDPD", 0x40144, 0 },
+ { "MC_UPCTL_ECCCFG", 0x40180, 0 },
+ { "inline_syn_en", 4, 1 },
+ { "ecc_en", 3, 1 },
+ { "ecc_intr_en", 2, 1 },
+ { "MC_UPCTL_ECCTST", 0x40184, 0 },
+ { "MC_UPCTL_ECCCLR", 0x40188, 0 },
+ { "clr_ecc_log", 1, 1 },
+ { "clr_ecc_intr", 0, 1 },
+ { "MC_UPCTL_ECCLOG", 0x4018c, 0 },
+ { "MC_UPCTL_DTUWACTL", 0x40200, 0 },
+ { "dtu_wr_rank", 30, 2 },
+ { "dtu_wr_row0", 13, 16 },
+ { "dtu_wr_bank", 10, 3 },
+ { "dtu_wr_col", 0, 10 },
+ { "MC_UPCTL_DTURACTL", 0x40204, 0 },
+ { "dtu_rd_rank", 30, 2 },
+ { "dtu_rd_row0", 13, 16 },
+ { "dtu_rd_bank", 10, 3 },
+ { "dtu_rd_col", 0, 10 },
+ { "MC_UPCTL_DTUCFG", 0x40208, 0 },
+ { "dtu_row_increments", 16, 7 },
+ { "dtu_wr_multi_rd", 15, 1 },
+ { "dtu_data_mask_en", 14, 1 },
+ { "dtu_target_lane", 10, 4 },
+ { "dtu_generate_random", 9, 1 },
+ { "dtu_incr_banks", 8, 1 },
+ { "dtu_incr_cols", 7, 1 },
+ { "dtu_nalen", 1, 6 },
+ { "dtu_enable", 0, 1 },
+ { "MC_UPCTL_DTUECTL", 0x4020c, 0 },
+ { "wr_multi_rd_rst", 2, 1 },
+ { "run_error_reports", 1, 1 },
+ { "run_dtu", 0, 1 },
+ { "MC_UPCTL_DTUWD0", 0x40210, 0 },
+ { "dtu_wr_byte3", 24, 8 },
+ { "dtu_wr_byte2", 16, 8 },
+ { "dtu_wr_byte1", 8, 8 },
+ { "dtu_wr_byte0", 0, 8 },
+ { "MC_UPCTL_DTUWD1", 0x40214, 0 },
+ { "dtu_wr_byte7", 24, 8 },
+ { "dtu_wr_byte6", 16, 8 },
+ { "dtu_wr_byte5", 8, 8 },
+ { "dtu_wr_byte4", 0, 8 },
+ { "MC_UPCTL_DTUWD2", 0x40218, 0 },
+ { "dtu_wr_byte11", 24, 8 },
+ { "dtu_wr_byte10", 16, 8 },
+ { "dtu_wr_byte9", 8, 8 },
+ { "dtu_wr_byte8", 0, 8 },
+ { "MC_UPCTL_DTUWD3", 0x4021c, 0 },
+ { "dtu_wr_byte15", 24, 8 },
+ { "dtu_wr_byte14", 16, 8 },
+ { "dtu_wr_byte13", 8, 8 },
+ { "dtu_wr_byte12", 0, 8 },
+ { "MC_UPCTL_DTUWDM", 0x40220, 0 },
+ { "MC_UPCTL_DTURD0", 0x40224, 0 },
+ { "dtu_rd_byte3", 24, 8 },
+ { "dtu_rd_byte2", 16, 8 },
+ { "dtu_rd_byte1", 8, 8 },
+ { "dtu_rd_byte0", 0, 8 },
+ { "MC_UPCTL_DTURD1", 0x40228, 0 },
+ { "dtu_rd_byte7", 24, 8 },
+ { "dtu_rd_byte6", 16, 8 },
+ { "dtu_rd_byte5", 8, 8 },
+ { "dtu_rd_byte4", 0, 8 },
+ { "MC_UPCTL_DTURD2", 0x4022c, 0 },
+ { "dtu_rd_byte11", 24, 8 },
+ { "dtu_rd_byte10", 16, 8 },
+ { "dtu_rd_byte9", 8, 8 },
+ { "dtu_rd_byte8", 0, 8 },
+ { "MC_UPCTL_DTURD3", 0x40230, 0 },
+ { "dtu_rd_byte15", 24, 8 },
+ { "dtu_rd_byte14", 16, 8 },
+ { "dtu_rd_byte13", 8, 8 },
+ { "dtu_rd_byte12", 0, 8 },
+ { "MC_UPCTL_DTULFSRWD", 0x40234, 0 },
+ { "MC_UPCTL_DTULFSRRD", 0x40238, 0 },
+ { "MC_UPCTL_DTUEAF", 0x4023c, 0 },
+ { "ea_rank", 30, 2 },
+ { "ea_row0", 13, 16 },
+ { "ea_bank", 10, 3 },
+ { "ea_column", 0, 10 },
+ { "MC_UPCTL_DFITCTRLDELAY", 0x40240, 0 },
+ { "MC_UPCTL_DFIODTCFG", 0x40244, 0 },
+ { "rank3_odt_default", 28, 1 },
+ { "rank3_odt_write_sel", 27, 1 },
+ { "rank3_odt_write_nsel", 26, 1 },
+ { "rank3_odt_read_sel", 25, 1 },
+ { "rank3_odt_read_nsel", 24, 1 },
+ { "rank2_odt_default", 20, 1 },
+ { "rank2_odt_write_sel", 19, 1 },
+ { "rank2_odt_write_nsel", 18, 1 },
+ { "rank2_odt_read_sel", 17, 1 },
+ { "rank2_odt_read_nsel", 16, 1 },
+ { "rank1_odt_default", 12, 1 },
+ { "rank1_odt_write_sel", 11, 1 },
+ { "rank1_odt_write_nsel", 10, 1 },
+ { "rank1_odt_read_sel", 9, 1 },
+ { "rank1_odt_read_nsel", 8, 1 },
+ { "rank0_odt_default", 4, 1 },
+ { "rank0_odt_write_sel", 3, 1 },
+ { "rank0_odt_write_nsel", 2, 1 },
+ { "rank0_odt_read_sel", 1, 1 },
+ { "rank0_odt_read_nsel", 0, 1 },
+ { "MC_UPCTL_DFIODTCFG1", 0x40248, 0 },
+ { "odt_len_b8_r", 24, 3 },
+ { "odt_len_bl8_w", 16, 3 },
+ { "odt_lat_r", 8, 5 },
+ { "odt_lat_w", 0, 5 },
+ { "MC_UPCTL_DFIODTRANKMAP", 0x4024c, 0 },
+ { "odt_rank_map3", 12, 4 },
+ { "odt_rank_map2", 8, 4 },
+ { "odt_rank_map1", 4, 4 },
+ { "odt_rank_map0", 0, 4 },
+ { "MC_UPCTL_DFITPHYWRDATA", 0x40250, 0 },
+ { "MC_UPCTL_DFITPHYWRLAT", 0x40254, 0 },
+ { "MC_UPCTL_DFITRDDATAEN", 0x40260, 0 },
+ { "MC_UPCTL_DFITPHYRDLAT", 0x40264, 0 },
+ { "MC_UPCTL_DFITPHYUPDTYPE0", 0x40270, 0 },
+ { "MC_UPCTL_DFITPHYUPDTYPE1", 0x40274, 0 },
+ { "MC_UPCTL_DFITPHYUPDTYPE2", 0x40278, 0 },
+ { "MC_UPCTL_DFITPHYUPDTYPE3", 0x4027c, 0 },
+ { "MC_UPCTL_DFITCTRLUPDMIN", 0x40280, 0 },
+ { "MC_UPCTL_DFITCTRLUPDMAX", 0x40284, 0 },
+ { "MC_UPCTL_DFITCTRLUPDDLY", 0x40288, 0 },
+ { "MC_UPCTL_DFIUPDCFG", 0x40290, 0 },
+ { "dfi_phyupd_en", 1, 1 },
+ { "dfi_ctrlupd_en", 0, 1 },
+ { "MC_UPCTL_DFITREFMSKI", 0x40294, 0 },
+ { "MC_UPCTL_DFITCTRLUPDI", 0x40298, 0 },
+ { "MC_UPCTL_DFITRCFG0", 0x402ac, 0 },
+ { "dfi_wrlvl_rank_sel", 16, 4 },
+ { "dfi_rdlvl_edge", 4, 9 },
+ { "dfi_rdlvl_rank_sel", 0, 4 },
+ { "MC_UPCTL_DFITRSTAT0", 0x402b0, 0 },
+ { "dfi_wrlvl_mode", 16, 2 },
+ { "dfi_rdlvl_gate_mode", 8, 2 },
+ { "dfi_rdlvl_mode", 0, 2 },
+ { "MC_UPCTL_DFITRWRLVLEN", 0x402b4, 0 },
+ { "MC_UPCTL_DFITRRDLVLEN", 0x402b8, 0 },
+ { "MC_UPCTL_DFITRRDLVLGATEEN", 0x402bc, 0 },
+ { "MC_UPCTL_DFISTSTAT0", 0x402c0, 0 },
+ { "dfi_data_byte_disable", 16, 9 },
+ { "dfi_freq_ratio", 4, 2 },
+ { "dfi_init_start0", 1, 1 },
+ { "dfi_init_complete", 0, 1 },
+ { "MC_UPCTL_DFISTCFG0", 0x402c4, 0 },
+ { "dfi_data_byte_disable_en", 2, 1 },
+ { "dfi_freq_ratio_en", 1, 1 },
+ { "dfi_init_start", 0, 1 },
+ { "MC_UPCTL_DFISTCFG1", 0x402c8, 0 },
+ { "dfi_dram_clk_disable_en_dpd", 1, 1 },
+ { "dfi_dram_clk_disable_en", 0, 1 },
+ { "MC_UPCTL_DFITDRAMCLKEN", 0x402d0, 0 },
+ { "MC_UPCTL_DFITDRAMCLKDIS", 0x402d4, 0 },
+ { "MC_UPCTL_DFISTCFG2", 0x402d8, 0 },
+ { "parity_en", 1, 1 },
+ { "parity_intr_en", 0, 1 },
+ { "MC_UPCTL_DFISTPARCLR", 0x402dc, 0 },
+ { "parity_log_clr", 1, 1 },
+ { "parity_intr_clr", 0, 1 },
+ { "MC_UPCTL_DFISTPARLOG", 0x402e0, 0 },
+ { "MC_UPCTL_DFILPCFG0", 0x402f0, 0 },
+ { "dfi_lp_wakeup_dpd", 28, 4 },
+ { "dfi_lp_en_dpd", 24, 1 },
+ { "dfi_tlp_resp", 16, 4 },
+ { "dfi_lp_en_sr", 8, 1 },
+ { "dfi_lp_wakeup_pd", 4, 4 },
+ { "dfi_lp_en_pd", 0, 1 },
+ { "MC_UPCTL_DFITRWRLVLRESP0", 0x40300, 0 },
+ { "MC_UPCTL_DFITRWRLVLRESP1", 0x40304, 0 },
+ { "MC_UPCTL_DFITRWRLVLRESP2", 0x40308, 0 },
+ { "MC_UPCTL_DFITRRDLVLRESP0", 0x4030c, 0 },
+ { "MC_UPCTL_DFITRRDLVLRESP1", 0x40310, 0 },
+ { "MC_UPCTL_DFITRRDLVLRESP2", 0x40314, 0 },
+ { "MC_UPCTL_DFITRWRLVLDELAY0", 0x40318, 0 },
+ { "MC_UPCTL_DFITRWRLVLDELAY1", 0x4031c, 0 },
+ { "MC_UPCTL_DFITRWRLVLDELAY2", 0x40320, 0 },
+ { "MC_UPCTL_DFITRRDLVLDELAY0", 0x40324, 0 },
+ { "MC_UPCTL_DFITRRDLVLDELAY1", 0x40328, 0 },
+ { "MC_UPCTL_DFITRRDLVLDELAY2", 0x4032c, 0 },
+ { "MC_UPCTL_DFITRRDLVLGATEDELAY0", 0x40330, 0 },
+ { "MC_UPCTL_DFITRRDLVLGATEDELAY1", 0x40334, 0 },
+ { "MC_UPCTL_DFITRRDLVLGATEDELAY2", 0x40338, 0 },
+ { "MC_UPCTL_DFITRCMD", 0x4033c, 0 },
+ { "dfitrcmd_start", 31, 1 },
+ { "dfitrcmd_en", 4, 9 },
+ { "dfitrcmd_opcode", 0, 2 },
+ { "MC_UPCTL_IPVR", 0x403f8, 0 },
+ { "MC_UPCTL_IPTR", 0x403fc, 0 },
+ { "MC_P_DDRPHY_RST_CTRL", 0x41300, 0 },
+ { "PHY_DRAM_WL", 17, 5 },
+ { "PHY_CALIB_DONE", 5, 1 },
+ { "CTL_CAL_REQ", 4, 1 },
+ { "CTL_CKE", 3, 1 },
+ { "CTL_RST_N", 2, 1 },
+ { "DDRIO_ENABLE", 1, 1 },
+ { "PHY_RST_N", 0, 1 },
+ { "MC_P_PERFORMANCE_CTRL", 0x41304, 0 },
+ { "STALL_CHK_BIT", 2, 1 },
+ { "DDR3_BRC_MODE", 1, 1 },
+ { "RMW_PERF_CTRL", 0, 1 },
+ { "MC_P_ECC_CTRL", 0x41308, 0 },
+ { "ECC_BYPASS_BIST", 1, 1 },
+ { "ECC_DISABLE", 0, 1 },
+ { "MC_P_PAR_ENABLE", 0x4130c, 0 },
+ { "ECC_UE_PAR_ENABLE", 3, 1 },
+ { "ECC_CE_PAR_ENABLE", 2, 1 },
+ { "PERR_REG_INT_ENABLE", 1, 1 },
+ { "PERR_BLK_INT_ENABLE", 0, 1 },
+ { "MC_P_PAR_CAUSE", 0x41310, 0 },
+ { "ECC_UE_PAR_CAUSE", 3, 1 },
+ { "ECC_CE_PAR_CAUSE", 2, 1 },
+ { "FIFOR_PAR_CAUSE", 1, 1 },
+ { "RDATA_FIFOR_PAR_CAUSE", 0, 1 },
+ { "MC_P_INT_ENABLE", 0x41314, 0 },
+ { "ECC_UE_INT_ENABLE", 2, 1 },
+ { "ECC_CE_INT_ENABLE", 1, 1 },
+ { "PERR_INT_ENABLE", 0, 1 },
+ { "MC_P_INT_CAUSE", 0x41318, 0 },
+ { "ECC_UE_INT_CAUSE", 2, 1 },
+ { "ECC_CE_INT_CAUSE", 1, 1 },
+ { "PERR_INT_CAUSE", 0, 1 },
+ { "MC_P_ECC_STATUS", 0x4131c, 0 },
+ { "ECC_CECNT", 16, 16 },
+ { "ECC_UECNT", 0, 16 },
+ { "MC_P_PHY_CTRL", 0x41320, 0 },
+ { "MC_P_STATIC_CFG_STATUS", 0x41324, 0 },
+ { "STATIC_AWEN", 23, 1 },
+ { "STATIC_SWLAT", 18, 5 },
+ { "STATIC_WLAT", 17, 1 },
+ { "STATIC_ALIGN", 16, 1 },
+ { "STATIC_SLAT", 11, 5 },
+ { "STATIC_LAT", 10, 1 },
+ { "STATIC_MODE", 9, 1 },
+ { "STATIC_DEN", 6, 3 },
+ { "STATIC_ORG", 5, 1 },
+ { "STATIC_RKS", 4, 1 },
+ { "STATIC_WIDTH", 1, 3 },
+ { "STATIC_SLOW", 0, 1 },
+ { "MC_P_CORE_PCTL_STAT", 0x41328, 0 },
+ { "MC_P_DEBUG_CNT", 0x4132c, 0 },
+ { "WDATA_OCNT", 8, 5 },
+ { "RDATA_OCNT", 0, 5 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41330, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41334, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41338, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x4133c, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41340, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41344, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41348, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x4134c, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x41350, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x41354, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x41358, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x4135c, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x41360, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x41364, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x41368, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x4136c, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41370, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41374, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41378, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x4137c, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41380, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41384, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41388, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x4138c, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x41390, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x41394, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x41398, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x4139c, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x413a0, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x413a4, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x413a8, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x413ac, 0 },
+ { "MC_CE_ADDR", 0x413b0, 0 },
+ { "MC_UE_ADDR", 0x413b4, 0 },
+ { "MC_P_DEEP_SLEEP", 0x413b8, 0 },
+ { "SleepStatus", 1, 1 },
+ { "SleepReq", 0, 1 },
+ { "MC_P_FPGA_BONUS", 0x413bc, 0 },
+ { "MC_P_DEBUG_CFG", 0x413c0, 0 },
+ { "DEBUG_OR", 15, 1 },
+ { "DEBUG_HI", 14, 1 },
+ { "DEBUG_RPT", 13, 1 },
+ { "DEBUGPAGE", 10, 3 },
+ { "DEBUGSELH", 5, 5 },
+ { "DEBUGSELL", 0, 5 },
+ { "MC_P_DEBUG_RPT", 0x413c4, 0 },
+ { "MC_P_BIST_CMD", 0x41400, 0 },
+ { "START_BIST", 31, 1 },
+ { "BURST_LEN", 16, 2 },
+ { "BIST_CMD_GAP", 8, 8 },
+ { "BIST_OPCODE", 0, 2 },
+ { "MC_P_BIST_CMD_ADDR", 0x41404, 0 },
+ { "MC_P_BIST_CMD_LEN", 0x41408, 0 },
+ { "MC_P_BIST_DATA_PATTERN", 0x4140c, 0 },
+ { "MC_P_BIST_USER_WDATA0", 0x41414, 0 },
+ { "MC_P_BIST_USER_WDATA1", 0x41418, 0 },
+ { "MC_P_BIST_USER_WDATA2", 0x4141c, 0 },
+ { "USER_DATA_MASK", 8, 9 },
+ { "USER_DATA2", 0, 8 },
+ { "MC_P_BIST_NUM_ERR", 0x41480, 0 },
+ { "MC_P_BIST_ERR_FIRST_ADDR", 0x41484, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x41488, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x4148c, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x41490, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x41494, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x41498, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x4149c, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414a0, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414a4, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414a8, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414ac, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414b0, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414b4, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414b8, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414bc, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414c0, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414c4, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414c8, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414cc, 0 },
+ { "MC_P_BIST_CRC_SEED", 0x414d0, 0 },
+ { NULL }
+};
+
+struct reg_info t5_mc_1_regs[] = {
+ { "MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS", 0x4f000, 0 },
+ { "DP18_PLL_LOCK", 1, 15 },
+ { "MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS", 0x4f004, 0 },
+ { "AD32S_PLL_LOCK", 14, 2 },
+ { "MC_DDRPHY_PC_RANK_PAIR0", 0x4f008, 0 },
+ { "RANK_PAIR0_PRI", 13, 3 },
+ { "RANK_PAIR0_PRI_V", 12, 1 },
+ { "RANK_PAIR0_SEC", 9, 3 },
+ { "RANK_PAIR0_SEC_V", 8, 1 },
+ { "RANK_PAIR1_PRI", 5, 3 },
+ { "RANK_PAIR1_PRI_V", 4, 1 },
+ { "RANK_PAIR1_SEC", 1, 3 },
+ { "RANK_PAIR1_SEC_V", 0, 1 },
+ { "MC_DDRPHY_PC_RANK_PAIR1", 0x4f00c, 0 },
+ { "RANK_PAIR2_PRI", 13, 3 },
+ { "RANK_PAIR2_PRI_V", 12, 1 },
+ { "RANK_PAIR2_SEC", 9, 3 },
+ { "RANK_PAIR2_SEC_V", 8, 1 },
+ { "RANK_PAIR3_PRI", 5, 3 },
+ { "RANK_PAIR3_PRI_V", 4, 1 },
+ { "RANK_PAIR3_SEC", 1, 3 },
+ { "RANK_PAIR3_SEC_V", 0, 1 },
+ { "MC_DDRPHY_PC_BASE_CNTR0", 0x4f010, 0 },
+ { "MC_DDRPHY_PC_RELOAD_VALUE0", 0x4f014, 0 },
+ { "PERIODIC_CAL_REQ_EN", 15, 1 },
+ { "PERIODIC_RELOAD_VALUE0", 0, 15 },
+ { "MC_DDRPHY_PC_BASE_CNTR1", 0x4f018, 0 },
+ { "MC_DDRPHY_PC_CAL_TIMER", 0x4f01c, 0 },
+ { "MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE", 0x4f020, 0 },
+ { "MC_DDRPHY_PC_ZCAL_TIMER", 0x4f024, 0 },
+ { "MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE", 0x4f028, 0 },
+ { "MC_DDRPHY_PC_PER_CAL_CONFIG", 0x4f02c, 0 },
+ { "PER_ENA_RANK_PAIR", 12, 4 },
+ { "PER_ENA_ZCAL", 11, 1 },
+ { "PER_ENA_SYSCLK_ALIGN", 10, 1 },
+ { "ENA_PER_READ_CTR", 9, 1 },
+ { "ENA_PER_RDCLK_ALIGN", 8, 1 },
+ { "ENA_PER_DQS_ALIGN", 7, 1 },
+ { "PER_NEXT_RANK_PAIR", 5, 2 },
+ { "FAST_SIM_PER_CNTR", 4, 1 },
+ { "START_INIT_CAL", 3, 1 },
+ { "START_PER_CAL", 2, 1 },
+ { "ABORT_ON_ERR_EN", 1, 1 },
+ { "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4f03c, 0 },
+ { "PER_ZCAL_ENA_RANK", 8, 8 },
+ { "PER_ZCAL_NEXT_RANK", 5, 3 },
+ { "START_PER_ZCAL", 4, 1 },
+ { "MC_DDRPHY_PC_CONFIG0", 0x4f030, 0 },
+ { "PROTOCOL_DDR", 12, 4 },
+ { "DATA_MUX4_1MODE", 11, 1 },
+ { "DDR4_CMD_SIG_REDUCTION", 9, 1 },
+ { "SYSCLK_2X_MEMINTCLKO", 8, 1 },
+ { "RANK_OVERRIDE", 7, 1 },
+ { "RANK_OVERRIDE_VALUE", 4, 3 },
+ { "LOW_LATENCY", 3, 1 },
+ { "DDR4_BANK_REFRESH", 2, 1 },
+ { "DDR4_VLEVEL_BANK_GROUP", 1, 1 },
+ { "MC_DDRPHY_PC_CONFIG1", 0x4f034, 0 },
+ { "WRITE_LATENCY_OFFSET", 12, 4 },
+ { "READ_LATENCY_OFFSET", 8, 4 },
+ { "MEMCTL_CIC_FAST", 7, 1 },
+ { "MEMCTL_CTRN_IGNORE", 6, 1 },
+ { "DISABLE_MEMCTL_CAL", 5, 1 },
+ { "MC_DDRPHY_PC_RESETS", 0x4f038, 0 },
+ { "PLL_RESET", 15, 1 },
+ { "SYSCLK_RESET", 14, 1 },
+ { "MC_DDRPHY_PC_ERROR_STATUS0", 0x4f048, 0 },
+ { "RC_ERROR", 15, 1 },
+ { "WC_ERROR", 14, 1 },
+ { "SEQ_ERROR", 13, 1 },
+ { "CC_ERROR", 12, 1 },
+ { "APB_ERROR", 11, 1 },
+ { "PC_ERROR", 10, 1 },
+ { "MC_DDRPHY_PC_ERROR_MASK0", 0x4f04c, 0 },
+ { "RC_ERROR_MASK", 15, 1 },
+ { "WC_ERROR_MASK", 14, 1 },
+ { "SEQ_ERROR_MASK", 13, 1 },
+ { "CC_ERROR_MASK", 12, 1 },
+ { "APB_ERROR_MASK", 11, 1 },
+ { "PC_ERROR_MASK", 10, 1 },
+ { "MC_DDRPHY_PC_IO_PVT_FET_CONTROL", 0x4f050, 0 },
+ { "PVTP", 11, 5 },
+ { "PVTN", 6, 5 },
+ { "PVT_OVERRIDE", 5, 1 },
+ { "ENABLE_ZCAL", 4, 1 },
+ { "MC_DDRPHY_PC_VREF_DRV_CONTROL", 0x4f054, 0 },
+ { "VREFDQ0DSGN", 15, 1 },
+ { "VREFDQ0D", 11, 4 },
+ { "VREFDQ1DSGN", 10, 1 },
+ { "VREFDQ1D", 6, 4 },
+ { "MC_DDRPHY_PC_INIT_CAL_CONFIG0", 0x4f058, 0 },
+ { "ENA_WR_LEVEL", 15, 1 },
+ { "ENA_INITIAL_PAT_WR", 14, 1 },
+ { "ENA_DQS_ALIGN", 13, 1 },
+ { "ENA_RDCLK_ALIGN", 12, 1 },
+ { "ENA_READ_CTR", 11, 1 },
+ { "ENA_WRITE_CTR", 10, 1 },
+ { "ENA_INITIAL_COARSE_WR", 9, 1 },
+ { "ENA_COARSE_RD", 8, 1 },
+ { "ENA_CUSTOM_RD", 7, 1 },
+ { "ENA_CUSTOM_WR", 6, 1 },
+ { "ABORT_ON_CAL_ERROR", 5, 1 },
+ { "ENA_DIGITAL_EYE", 4, 1 },
+ { "ENA_RANK_PAIR", 0, 4 },
+ { "MC_DDRPHY_PC_INIT_CAL_CONFIG1", 0x4f05c, 0 },
+ { "REFRESH_COUNT", 12, 4 },
+ { "REFRESH_CONTROL", 10, 2 },
+ { "REFRESH_ALL_RANKS", 9, 1 },
+ { "REFRESH_INTERVAL", 0, 7 },
+ { "MC_DDRPHY_PC_INIT_CAL_ERROR", 0x4f060, 0 },
+ { "ERROR_WR_LEVEL", 15, 1 },
+ { "ERROR_INITIAL_PAT_WRITE", 14, 1 },
+ { "ERROR_DQS_ALIGN", 13, 1 },
+ { "ERROR_RDCLK_ALIGN", 12, 1 },
+ { "ERROR_READ_CTR", 11, 1 },
+ { "ERROR_WRITE_CTR", 10, 1 },
+ { "ERROR_INITIAL_COARSE_WR", 9, 1 },
+ { "ERROR_COARSE_RD", 8, 1 },
+ { "ERROR_CUSTOM_RD", 7, 1 },
+ { "ERROR_CUSTOM_WR", 6, 1 },
+ { "ERROR_DIGITAL_EYE", 5, 1 },
+ { "ERROR_RANK_PAIR", 0, 4 },
+ { "MC_DDRPHY_PC_INIT_CAL_MASK", 0x4f068, 0 },
+ { "ERROR_WR_LEVEL_MASK", 15, 1 },
+ { "ERROR_INITIAL_PAT_WRITE_MASK", 14, 1 },
+ { "ERROR_DQS_ALIGN_MASK", 13, 1 },
+ { "ERROR_RDCLK_ALIGN_MASK", 12, 1 },
+ { "ERROR_READ_CTR_MASK", 11, 1 },
+ { "ERROR_WRITE_CTR_MASK", 10, 1 },
+ { "ERROR_INITIAL_COARSE_WR_MASK", 9, 1 },
+ { "ERROR_COARSE_RD_MASK", 8, 1 },
+ { "ERROR_CUSTOM_RD_MASK", 7, 1 },
+ { "ERROR_CUSTOM_WR_MASK", 6, 1 },
+ { "ERROR_DIGITAL_EYE_MASK", 5, 1 },
+ { "MC_DDRPHY_PC_INIT_CAL_STATUS", 0x4f064, 0 },
+ { "INIT_CAL_COMPLETE", 12, 4 },
+ { "MC_DDRPHY_PC_IO_PVT_FET_STATUS", 0x4f06c, 0 },
+ { "PVTP", 11, 5 },
+ { "PVTN", 6, 5 },
+ { "MC_DDRPHY_PC_MR0_PRI_RP", 0x4f070, 0 },
+ { "MC_DDRPHY_PC_MR1_PRI_RP", 0x4f074, 0 },
+ { "MC_DDRPHY_PC_MR2_PRI_RP", 0x4f078, 0 },
+ { "MC_DDRPHY_PC_MR3_PRI_RP", 0x4f07c, 0 },
+ { "MC_DDRPHY_PC_MR0_SEC_RP", 0x4f080, 0 },
+ { "MC_DDRPHY_PC_MR1_SEC_RP", 0x4f084, 0 },
+ { "MC_DDRPHY_PC_MR2_SEC_RP", 0x4f088, 0 },
+ { "MC_DDRPHY_PC_MR3_SEC_RP", 0x4f08c, 0 },
+ { "MC_DDRPHY_PC_RANK_GROUP", 0x4f044, 0 },
+ { "ADDR_MIRROR_RP0_PRI", 15, 1 },
+ { "ADDR_MIRROR_RP0_SEC", 14, 1 },
+ { "ADDR_MIRROR_RP1_PRI", 13, 1 },
+ { "ADDR_MIRROR_RP1_SEC", 12, 1 },
+ { "ADDR_MIRROR_RP2_PRI", 11, 1 },
+ { "ADDR_MIRROR_RP2_SEC", 10, 1 },
+ { "ADDR_MIRROR_RP3_PRI", 9, 1 },
+ { "ADDR_MIRROR_RP3_SEC", 8, 1 },
+ { "RANK_GROUPING", 6, 2 },
+ { "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x4d000, 0 },
+ { "BIT_ENABLE_0_11", 4, 12 },
+ { "BIT_ENABLE_12_15", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x4d004, 0 },
+ { "DI_ADR0_ADR1", 15, 1 },
+ { "DI_ADR2_ADR3", 14, 1 },
+ { "DI_ADR4_ADR5", 13, 1 },
+ { "DI_ADR6_ADR7", 12, 1 },
+ { "DI_ADR8_ADR9", 11, 1 },
+ { "DI_ADR10_ADR11", 10, 1 },
+ { "DI_ADR12_ADR13", 9, 1 },
+ { "DI_ADR14_ADR15", 8, 1 },
+ { "MC_ADR_DDRPHY_ADR_DELAY0", 0x4d010, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY1", 0x4d014, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY2", 0x4d018, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY3", 0x4d01c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY4", 0x4d020, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY5", 0x4d024, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY6", 0x4d028, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY7", 0x4d02c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x4d030, 0 },
+ { "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
+ { "ADR_TEST_DATA_EN", 7, 1 },
+ { "DADR_TEST_MODE", 5, 2 },
+ { "ADR_TEST_4TO1_MODE", 4, 1 },
+ { "ADR_TEST_RESET", 3, 1 },
+ { "ADR_TEST_GEN_EN", 2, 1 },
+ { "ADR_TEST_CLEAR_ERROR", 1, 1 },
+ { "ADR_TEST_CHECK_EN", 0, 1 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x4d040, 0 },
+ { "EN_SLICE_N_WR_0", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x4d044, 0 },
+ { "EN_SLICE_N_WR_1", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x4d048, 0 },
+ { "EN_SLICE_N_WR_2", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4d04c, 0 },
+ { "EN_SLICE_N_WR_3", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x4d050, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x4d054, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x4d058, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4d05c, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x4d080, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x4d084, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x4d060, 0 },
+ { "POST_CURSOR0", 12, 4 },
+ { "POST_CURSOR1", 8, 4 },
+ { "POST_CURSOR2", 4, 4 },
+ { "POST_CURSOR3", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x4d0a0, 0 },
+ { "POST_CUR_SEL_BITS0_1", 14, 2 },
+ { "POST_CUR_SEL_BITS2_3", 12, 2 },
+ { "POST_CUR_SEL_BITS4_5", 10, 2 },
+ { "POST_CUR_SEL_BITS6_7", 8, 2 },
+ { "POST_CUR_SEL_BITS8_9", 6, 2 },
+ { "POST_CUR_SEL_BITS10_11", 4, 2 },
+ { "POST_CUR_SEL_BITS12_13", 2, 2 },
+ { "POST_CUR_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x4d0a4, 0 },
+ { "POST_CUR_SEL_BITS0_1", 14, 2 },
+ { "POST_CUR_SEL_BITS2_3", 12, 2 },
+ { "POST_CUR_SEL_BITS4_5", 10, 2 },
+ { "POST_CUR_SEL_BITS6_7", 8, 2 },
+ { "POST_CUR_SEL_BITS8_9", 6, 2 },
+ { "POST_CUR_SEL_BITS10_11", 4, 2 },
+ { "POST_CUR_SEL_BITS12_13", 2, 2 },
+ { "POST_CUR_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x4d068, 0 },
+ { "SLEW_CTL0", 12, 4 },
+ { "SLEW_CTL1", 8, 4 },
+ { "SLEW_CTL2", 4, 4 },
+ { "SLEW_CTL3", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x4d0a8, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x4d0ac, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x4d0b0, 0 },
+ { "ADR_LANE_0_11_PD", 4, 12 },
+ { "ADR_LANE_12_15_PD", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x4d200, 0 },
+ { "BIT_ENABLE_0_11", 4, 12 },
+ { "BIT_ENABLE_12_15", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x4d204, 0 },
+ { "DI_ADR0_ADR1", 15, 1 },
+ { "DI_ADR2_ADR3", 14, 1 },
+ { "DI_ADR4_ADR5", 13, 1 },
+ { "DI_ADR6_ADR7", 12, 1 },
+ { "DI_ADR8_ADR9", 11, 1 },
+ { "DI_ADR10_ADR11", 10, 1 },
+ { "DI_ADR12_ADR13", 9, 1 },
+ { "DI_ADR14_ADR15", 8, 1 },
+ { "MC_ADR_DDRPHY_ADR_DELAY0", 0x4d210, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY1", 0x4d214, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY2", 0x4d218, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY3", 0x4d21c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY4", 0x4d220, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY5", 0x4d224, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY6", 0x4d228, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY7", 0x4d22c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x4d230, 0 },
+ { "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
+ { "ADR_TEST_DATA_EN", 7, 1 },
+ { "DADR_TEST_MODE", 5, 2 },
+ { "ADR_TEST_4TO1_MODE", 4, 1 },
+ { "ADR_TEST_RESET", 3, 1 },
+ { "ADR_TEST_GEN_EN", 2, 1 },
+ { "ADR_TEST_CLEAR_ERROR", 1, 1 },
+ { "ADR_TEST_CHECK_EN", 0, 1 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x4d240, 0 },
+ { "EN_SLICE_N_WR_0", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x4d244, 0 },
+ { "EN_SLICE_N_WR_1", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x4d248, 0 },
+ { "EN_SLICE_N_WR_2", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4d24c, 0 },
+ { "EN_SLICE_N_WR_3", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x4d250, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x4d254, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x4d258, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4d25c, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x4d280, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x4d284, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x4d260, 0 },
+ { "POST_CURSOR0", 12, 4 },
+ { "POST_CURSOR1", 8, 4 },
+ { "POST_CURSOR2", 4, 4 },
+ { "POST_CURSOR3", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x4d2a0, 0 },
+ { "POST_CUR_SEL_BITS0_1", 14, 2 },
+ { "POST_CUR_SEL_BITS2_3", 12, 2 },
+ { "POST_CUR_SEL_BITS4_5", 10, 2 },
+ { "POST_CUR_SEL_BITS6_7", 8, 2 },
+ { "POST_CUR_SEL_BITS8_9", 6, 2 },
+ { "POST_CUR_SEL_BITS10_11", 4, 2 },
+ { "POST_CUR_SEL_BITS12_13", 2, 2 },
+ { "POST_CUR_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x4d2a4, 0 },
+ { "POST_CUR_SEL_BITS0_1", 14, 2 },
+ { "POST_CUR_SEL_BITS2_3", 12, 2 },
+ { "POST_CUR_SEL_BITS4_5", 10, 2 },
+ { "POST_CUR_SEL_BITS6_7", 8, 2 },
+ { "POST_CUR_SEL_BITS8_9", 6, 2 },
+ { "POST_CUR_SEL_BITS10_11", 4, 2 },
+ { "POST_CUR_SEL_BITS12_13", 2, 2 },
+ { "POST_CUR_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x4d268, 0 },
+ { "SLEW_CTL0", 12, 4 },
+ { "SLEW_CTL1", 8, 4 },
+ { "SLEW_CTL2", 4, 4 },
+ { "SLEW_CTL3", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x4d2a8, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x4d2ac, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x4d2b0, 0 },
+ { "ADR_LANE_0_11_PD", 4, 12 },
+ { "ADR_LANE_12_15_PD", 0, 4 },
+ { "MC_DDRPHY_ADR_PLL_VREG_CONFIG_0", 0x4e0c0, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_ADR_PLL_VREG_CONFIG_1", 0x4e0c4, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "VREG_VREGSPARE", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "INTERP_SIG_SLEW_0_3", 1, 4 },
+ { "ANALOG_WRAPON", 0, 1 },
+ { "MC_DDRPHY_ADR_SYSCLK_CNTL_PR", 0x4e0c8, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESE", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "CE0DLTVCC", 0, 2 },
+ { "MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET", 0x4e0cc, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO", 0x4e0d0, 0 },
+ { "SLEW_LATE_SAMPLE", 15, 1 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "SLEW_EARLY_SAMPLE", 6, 1 },
+ { "SLEW_DONE_STATUS", 4, 2 },
+ { "SLEW_CNTL", 0, 4 },
+ { "MC_DDRPHY_ADR_GMTEST_ATEST_CNTL", 0x4e0d4, 0 },
+ { "FLUSH", 15, 1 },
+ { "GIANT_MUX_TEST_EN", 14, 1 },
+ { "GIANT_MUX_TEST_VAL", 13, 1 },
+ { "HS_PROBE_A_SEL_", 8, 4 },
+ { "HS_PROBE_B_SEL_", 4, 4 },
+ { "ATEST1CTL0", 3, 1 },
+ { "ATEST1CTL1", 2, 1 },
+ { "ATEST1CTL2", 1, 1 },
+ { "ATEST1CTL3", 0, 1 },
+ { "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0", 0x4e0d8, 0 },
+ { "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1", 0x4e0dc, 0 },
+ { "MC_DDRPHY_ADR_POWERDOWN_1", 0x4e0e0, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_ADR_SLEW_CAL_CNTL", 0x4e0e4, 0 },
+ { "SLEW_CAL_ENABLE", 15, 1 },
+ { "SLEW_CAL_START", 14, 1 },
+ { "SLEW_CAL_OVERRIDE_EN", 12, 1 },
+ { "SLEW_CAL_OVERRIDE", 8, 4 },
+ { "SLEW_TARGET_PR_OFFSET", 0, 5 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c000, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c004, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "WRAPSEL", 5, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c1f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c1f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c008, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c00c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c010, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c014, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c1f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c018, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c01c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c1cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x4c1d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c0c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c0c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c024, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c170, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c174, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c0e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c0e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c0e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c0ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c0f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c0f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c0f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c0fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c100, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c104, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c108, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c10c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c110, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c114, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c118, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c11c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c120, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c124, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c128, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c12c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c130, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c134, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c138, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c13c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c140, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c144, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c148, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c14c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c150, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c154, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c158, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c15c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c160, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c164, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c168, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c16c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c030, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c034, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c1c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c1c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c1c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c180, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c184, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c188, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c18c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c190, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c194, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c198, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c19c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c1a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c1a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c1a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c1ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c028, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c038, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c03c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c040, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c044, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c04c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x4c050, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c054, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c05c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c060, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "DDONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c064, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c068, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4c06c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c070, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c1d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c1dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c1e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c1e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c1e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c1ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c1d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c074, 0 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c020, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c0c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c0cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c0d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c078, 0 },
+ { "SYSCLK_RDCLK_OFFSET", 8, 7 },
+ { "SYSCLK_DQSCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c0d4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c0d8, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c1b4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c1b8, 0 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c0dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c02c, 0 },
+ { "HS_PROBE_A_SEL", 11, 5 },
+ { "HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c1fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c048, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DYN_MCTERM_CNTL_EN", 14, 1 },
+ { "DYN_RX_GATE_CNTL_EN", 13, 1 },
+ { "CALGATE_ON", 12, 1 },
+ { "PER_RDCLK_UPDATE_DIS", 11, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c200, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c204, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "WRAPSEL", 5, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c3f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c3f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c208, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c20c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c210, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c214, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c3f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c218, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c21c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c3cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x4c3d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c2c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c2c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c224, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c370, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c374, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c2e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c2e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c2e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c2ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c2f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c2f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c2f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c2fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c300, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c304, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c308, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c30c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c310, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c314, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c318, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c31c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c320, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c324, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c328, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c32c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c330, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c334, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c338, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c33c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c340, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c344, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c348, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c34c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c350, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c354, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c358, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c35c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c360, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c364, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c368, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c36c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c230, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c234, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c3c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c3c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c3c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c380, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c384, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c388, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c38c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c390, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c394, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c398, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c39c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c3a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c3a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c3a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c3ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c228, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c238, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c23c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c240, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c244, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c24c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x4c250, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c254, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c25c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c260, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "DDONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c264, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c268, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4c26c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c270, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c3d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c3dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c3e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c3e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c3e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c3ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c3d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c274, 0 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c220, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c2c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c2cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c2d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c278, 0 },
+ { "SYSCLK_RDCLK_OFFSET", 8, 7 },
+ { "SYSCLK_DQSCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c2d4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c2d8, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c3b4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c3b8, 0 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c2dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c22c, 0 },
+ { "HS_PROBE_A_SEL", 11, 5 },
+ { "HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c3fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c248, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DYN_MCTERM_CNTL_EN", 14, 1 },
+ { "DYN_RX_GATE_CNTL_EN", 13, 1 },
+ { "CALGATE_ON", 12, 1 },
+ { "PER_RDCLK_UPDATE_DIS", 11, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c400, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c404, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "WRAPSEL", 5, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c5f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c5f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c408, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c40c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c410, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c414, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c5f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c418, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c41c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c5cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x4c5d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c4c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c4c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c424, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c570, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c574, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c4e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c4e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c4e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c4ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c4f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c4f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c4f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c4fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c500, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c504, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c508, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c50c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c510, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c514, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c518, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c51c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c520, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c524, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c528, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c52c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c530, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c534, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c538, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c53c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c540, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c544, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c548, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c54c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c550, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c554, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c558, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c55c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c560, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c564, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c568, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c56c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c430, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c434, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c5c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c5c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c5c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c580, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c584, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c588, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c58c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c590, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c594, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c598, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c59c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c5a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c5a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c5a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c5ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c428, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c438, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c43c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c440, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c444, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c44c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x4c450, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c454, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c45c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c460, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "DDONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c464, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c468, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4c46c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c470, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c5d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c5dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c5e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c5e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c5e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c5ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c5d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c474, 0 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c420, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c4c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c4cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c4d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c478, 0 },
+ { "SYSCLK_RDCLK_OFFSET", 8, 7 },
+ { "SYSCLK_DQSCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c4d4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c4d8, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c5b4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c5b8, 0 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c4dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c42c, 0 },
+ { "HS_PROBE_A_SEL", 11, 5 },
+ { "HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c5fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c448, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DYN_MCTERM_CNTL_EN", 14, 1 },
+ { "DYN_RX_GATE_CNTL_EN", 13, 1 },
+ { "CALGATE_ON", 12, 1 },
+ { "PER_RDCLK_UPDATE_DIS", 11, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c600, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c604, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "WRAPSEL", 5, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c7f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c7f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c608, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c60c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c610, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c614, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c7f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c618, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c61c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c7cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x4c7d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c6c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c6c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c624, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c770, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c774, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c6e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c6e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c6e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c6ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c6f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c6f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c6f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c6fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c700, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c704, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c708, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c70c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c710, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c714, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c718, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c71c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c720, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c724, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c728, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c72c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c730, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c734, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c738, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c73c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c740, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c744, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c748, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c74c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c750, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c754, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c758, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c75c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c760, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c764, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c768, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c76c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c630, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c634, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c7c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c7c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c7c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c780, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c784, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c788, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c78c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c790, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c794, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c798, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c79c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c7a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c7a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c7a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c7ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c628, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c638, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c63c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c640, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c644, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c64c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x4c650, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c654, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c65c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c660, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "DDONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c664, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c668, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4c66c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c670, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c7d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c7dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c7e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c7e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c7e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c7ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c7d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c674, 0 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c620, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c6c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c6cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c6d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c678, 0 },
+ { "SYSCLK_RDCLK_OFFSET", 8, 7 },
+ { "SYSCLK_DQSCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c6d4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c6d8, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c7b4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c7b8, 0 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c6dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c62c, 0 },
+ { "HS_PROBE_A_SEL", 11, 5 },
+ { "HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c7fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c648, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DYN_MCTERM_CNTL_EN", 14, 1 },
+ { "DYN_RX_GATE_CNTL_EN", 13, 1 },
+ { "CALGATE_ON", 12, 1 },
+ { "PER_RDCLK_UPDATE_DIS", 11, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c800, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c804, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "WRAPSEL", 5, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c9f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c9f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c808, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c80c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c810, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c814, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c9f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c818, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c81c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c9cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x4c9d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c8c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c8c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c824, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c970, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c974, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c8e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c8e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c8e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c8ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c8f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c8f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c8f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c8fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c900, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c904, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c908, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c90c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c910, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c914, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c918, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c91c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c920, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c924, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c928, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c92c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c930, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c934, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c938, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c93c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c940, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c944, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c948, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c94c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c950, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c954, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c958, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c95c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c960, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c964, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c968, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c96c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c830, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c834, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c9c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c9c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c9c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c980, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c984, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c988, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c98c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c990, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c994, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c998, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c99c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c9a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c9a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c9a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c9ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c828, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c838, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c83c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c840, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c844, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c84c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x4c850, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c854, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c85c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c860, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "DDONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c864, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c868, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4c86c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c870, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c9d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c9dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c9e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c9e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c9e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c9ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c9d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c874, 0 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c820, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c8c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c8cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c8d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c878, 0 },
+ { "SYSCLK_RDCLK_OFFSET", 8, 7 },
+ { "SYSCLK_DQSCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c8d4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c8d8, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c9b4, 0 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c9b8, 0 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c8dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c82c, 0 },
+ { "HS_PROBE_A_SEL", 11, 5 },
+ { "HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c9fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c848, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DYN_MCTERM_CNTL_EN", 14, 1 },
+ { "DYN_RX_GATE_CNTL_EN", 13, 1 },
+ { "CALGATE_ON", 12, 1 },
+ { "PER_RDCLK_UPDATE_DIS", 11, 1 },
+ { "MC_DDRPHY_SEQ_RD_WR_DATA0", 0x4f200, 0 },
+ { "MC_DDRPHY_SEQ_RD_WR_DATA1", 0x4f204, 0 },
+ { "MC_DDRPHY_SEQ_CONFIG0", 0x4f208, 0 },
+ { "MPR_PATTERN_BIT", 15, 1 },
+ { "TWO_CYCLE_ADDR_EN", 14, 1 },
+ { "MR_MASK_EN", 10, 4 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR0", 0x4f20c, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR1", 0x4f210, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR2", 0x4f214, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR3", 0x4f218, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR4", 0x4f21c, 0 },
+ { "MC_DDRPHY_SEQ_ERROR_STATUS0", 0x4f220, 0 },
+ { "MULTIPLE_REQ_ERROR", 15, 1 },
+ { "INVALID_REQTYPE_ERRO", 14, 1 },
+ { "EARLY_REQ_ERROR", 13, 1 },
+ { "MULTIPLE_REQ_SOURCE", 10, 3 },
+ { "INVALID_REQTYPE", 6, 4 },
+ { "INVALID_REQ_SOURCE", 3, 3 },
+ { "EARLY_REQ_SOURCE", 0, 3 },
+ { "MC_DDRPHY_SEQ_ERROR_MASK0", 0x4f224, 0 },
+ { "MULT_REQ_ERR_MASK", 15, 1 },
+ { "INVALID_REQTYPE_ERR_MASK", 14, 1 },
+ { "EARLY_REQ_ERR_MASK", 13, 1 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG0", 0x4f228, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG1", 0x4f22c, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG2", 0x4f230, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG3", 0x4f234, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG0", 0x4f238, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG1", 0x4f23c, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG2", 0x4f240, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG3", 0x4f244, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM0", 0x4f248, 0 },
+ { "TMOD_CYCLES", 12, 4 },
+ { "TRCD_CYCLES", 8, 4 },
+ { "TRP_CYCLES", 4, 4 },
+ { "TRFC_CYCLES", 0, 4 },
+ { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM1", 0x4f24c, 0 },
+ { "TZQINIT_CYCLES", 12, 4 },
+ { "TZQCS_CYCLES", 8, 4 },
+ { "TWLDQSEN_CYCLES", 4, 4 },
+ { "TWRMRD_CYCLES", 0, 4 },
+ { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM2", 0x4f250, 0 },
+ { "TODTLON_OFF_CYCLES", 12, 4 },
+ { "TRC_CYCLES", 8, 4 },
+ { "TMRSC_CYCLES", 4, 4 },
+ { "MC_DDRPHY_WC_CONFIG0", 0x4f600, 0 },
+ { "TWLO_TWLOE", 8, 8 },
+ { "WL_ONE_DQS_PULSE", 7, 1 },
+ { "FW_WR_RD", 1, 6 },
+ { "CUSTOM_INIT_WRITE", 0, 1 },
+ { "MC_DDRPHY_WC_CONFIG1", 0x4f604, 0 },
+ { "BIG_STEP", 12, 4 },
+ { "SMALL_STEP", 9, 3 },
+ { "WR_PRE_DLY", 3, 6 },
+ { "MC_DDRPHY_WC_CONFIG2", 0x4f608, 0 },
+ { "NUM_VALID_SAMPLES", 12, 4 },
+ { "FW_RD_WR", 6, 6 },
+ { "EN_RESET_WR_DELAY_WL", 0, 1 },
+ { "MC_DDRPHY_WC_CONFIG3", 0x4f614, 0 },
+ { "DDR4_MRS_CMD_DQ_EN", 15, 1 },
+ { "MRS_CMD_DQ_ON", 9, 6 },
+ { "MRS_CMD_DQ_OFF", 3, 6 },
+ { "MC_DDRPHY_WC_WRCLK_CNTL", 0x4f618, 0 },
+ { "WRCLK_CAL_START", 15, 1 },
+ { "WRCLK_CAL_DONE", 14, 1 },
+ { "MC_DDRPHY_WC_ERROR_STATUS0", 0x4f60c, 0 },
+ { "WR_CNTL_ERROR", 15, 1 },
+ { "MC_DDRPHY_WC_ERROR_MASK0", 0x4f610, 0 },
+ { "WR_CNTL_ERROR_MASK", 15, 1 },
+ { "MC_DDRPHY_RC_CONFIG0", 0x4f400, 0 },
+ { "GLOBAL_PHY_OFFSET", 12, 4 },
+ { "ADVANCE_RD_VALID", 11, 1 },
+ { "SINGLE_BIT_MPR_RP0", 6, 1 },
+ { "SINGLE_BIT_MPR_RP1", 5, 1 },
+ { "SINGLE_BIT_MPR_RP2", 4, 1 },
+ { "SINGLE_BIT_MPR_RP3", 3, 1 },
+ { "ALIGN_ON_EVEN_CYCLES", 2, 1 },
+ { "PERFORM_RDCLK_ALIGN", 1, 1 },
+ { "STAGGERED_PATTERN", 0, 1 },
+ { "MC_DDRPHY_RC_CONFIG1", 0x4f404, 0 },
+ { "OUTER_LOOP_CNT", 2, 14 },
+ { "MC_DDRPHY_RC_CONFIG2", 0x4f408, 0 },
+ { "CONSEQ_PASS", 11, 5 },
+ { "BURST_WINDOW", 5, 2 },
+ { "ALLOW_RD_FIFO_AUTO_R_ESET", 4, 1 },
+ { "MC_DDRPHY_RC_CONFIG3", 0x4f41c, 0 },
+ { "FINE_CAL_STEP_SIZE", 13, 3 },
+ { "COARSE_CAL_STEP_SIZE", 9, 4 },
+ { "DQ_SEL_QUAD", 7, 2 },
+ { "DQ_SEL_LANE", 4, 3 },
+ { "MC_DDRPHY_RC_PERIODIC", 0x4f420, 0 },
+ { "MC_DDRPHY_RC_ERROR_STATUS0", 0x4f414, 0 },
+ { "RD_CNTL_ERROR", 15, 1 },
+ { "MC_DDRPHY_RC_ERROR_MASK0", 0x4f418, 0 },
+ { "RD_CNTL_ERROR_MASK", 15, 1 },
+ { "MC_DDRPHY_APB_CONFIG0", 0x4f800, 0 },
+ { "DISABLE_PARITY_CHECKER", 15, 1 },
+ { "GENERATE_EVEN_PARITY", 14, 1 },
+ { "FORCE_ON_CLK_GATE", 13, 1 },
+ { "DEBUG_BUS_SEL_LO", 12, 1 },
+ { "DEBUG_BUS_SEL_HI", 8, 4 },
+ { "MC_DDRPHY_APB_ERROR_STATUS0", 0x4f804, 0 },
+ { "INVALID_ADDRESS", 15, 1 },
+ { "WR_PAR_ERR", 14, 1 },
+ { "MC_DDRPHY_APB_ERROR_MASK0", 0x4f808, 0 },
+ { "INVALID_ADDRESS_MASK", 15, 1 },
+ { "WR_PAR_ERR_MASK", 14, 1 },
+ { "MC_DDRPHY_APB_DP18_POPULATION", 0x4f80c, 0 },
+ { "DP18_0_Populated", 15, 1 },
+ { "DP18_1_Populated", 14, 1 },
+ { "DP18_2_Populated", 13, 1 },
+ { "DP18_3_Populated", 12, 1 },
+ { "DP18_4_Populated", 11, 1 },
+ { "DP18_5_Populated", 10, 1 },
+ { "DP18_6_Populated", 9, 1 },
+ { "DP18_7_Populated", 8, 1 },
+ { "DP18_8_Populated", 7, 1 },
+ { "DP18_9_Populated", 6, 1 },
+ { "DP18_10_Populated", 5, 1 },
+ { "DP18_11_Populated", 4, 1 },
+ { "DP18_12_Populated", 3, 1 },
+ { "DP18_13_Populated", 2, 1 },
+ { "DP18_14_Populated", 1, 1 },
+ { "MC_DDRPHY_APB_ADR_POPULATION", 0x4f810, 0 },
+ { "ADR16_0_Populated", 15, 1 },
+ { "ADR16_1_Populated", 14, 1 },
+ { "ADR16_2_Populated", 13, 1 },
+ { "ADR16_3_Populated", 12, 1 },
+ { "ADR12_0_Populated", 7, 1 },
+ { "ADR12_1_Populated", 6, 1 },
+ { "ADR12_2_Populated", 5, 1 },
+ { "ADR12_3_Populated", 4, 1 },
+ { "MC_DDRPHY_APB_ATEST_MUX_SEL", 0x4f814, 0 },
+ { "ATEST_CNTL", 10, 6 },
+ { "MC_UPCTL_SCFG", 0x48000, 0 },
+ { "bbflags_timing", 8, 4 },
+ { "nfifo_nif1_dis", 6, 1 },
+ { "hw_low_power_en", 0, 1 },
+ { "MC_UPCTL_SCTL", 0x48004, 0 },
+ { "MC_UPCTL_STAT", 0x48008, 0 },
+ { "lp_trig", 4, 3 },
+ { "ctl_stat", 0, 3 },
+ { "MC_UPCTL_INTRSTAT", 0x4800c, 0 },
+ { "parity_intr", 1, 1 },
+ { "ecc_intr", 0, 1 },
+ { "MC_UPCTL_MCMD", 0x48040, 0 },
+ { "start_cmd", 31, 1 },
+ { "cmd_add_del", 24, 4 },
+ { "rank_sel", 20, 4 },
+ { "bank_addr", 17, 3 },
+ { "cmd_addr", 4, 13 },
+ { "cmd_opcode0", 0, 4 },
+ { "MC_UPCTL_POWCTL", 0x48044, 0 },
+ { "MC_UPCTL_POWSTAT", 0x48048, 0 },
+ { "MC_UPCTL_CMDTSTAT", 0x4804c, 0 },
+ { "MC_UPCTL_CMDTSTATEN", 0x48050, 0 },
+ { "MC_UPCTL_MRRCFG0", 0x48060, 0 },
+ { "MC_UPCTL_MRRSTAT0", 0x48064, 0 },
+ { "mrrstat_beat3", 24, 8 },
+ { "mrrstat_beat2", 16, 8 },
+ { "mrrstat_beat1", 8, 8 },
+ { "mrrstat_beat0", 0, 8 },
+ { "MC_UPCTL_MRRSTAT1", 0x48068, 0 },
+ { "mrrstat_beat7", 24, 8 },
+ { "mrrstat_beat6", 16, 8 },
+ { "mrrstat_beat5", 8, 8 },
+ { "mrrstat_beat4", 0, 8 },
+ { "MC_UPCTL_MCFG1", 0x4807c, 0 },
+ { "hw_exit_idle_en", 31, 1 },
+ { "hw_idle", 16, 8 },
+ { "sr_idle", 0, 8 },
+ { "MC_UPCTL_MCFG", 0x48080, 0 },
+ { "mddr_lpddr2_clk_stop_idle", 24, 8 },
+ { "mddr_lpddr2_en", 22, 2 },
+ { "mddr_lpddr2_bl", 20, 2 },
+ { "tfaw_cfg", 18, 2 },
+ { "pd_exit_mode", 17, 1 },
+ { "pd_type", 16, 1 },
+ { "pd_idle", 8, 8 },
+ { "lpddr2_s4", 6, 1 },
+ { "ddr3_en", 5, 1 },
+ { "stagger_cs", 4, 1 },
+ { "two_t_en", 3, 1 },
+ { "bl8int_en", 2, 1 },
+ { "cke_or_en", 1, 1 },
+ { "mem_bl", 0, 1 },
+ { "MC_UPCTL_PPCFG", 0x48084, 0 },
+ { "rpmem_dis", 1, 8 },
+ { "ppmem_en", 0, 1 },
+ { "MC_UPCTL_MSTAT", 0x48088, 0 },
+ { "self_refresh", 2, 1 },
+ { "clock_stop", 1, 1 },
+ { "power_down", 0, 1 },
+ { "MC_UPCTL_LPDDR2ZQCFG", 0x4808c, 0 },
+ { "zqcl_op", 24, 8 },
+ { "zqcl_ma", 16, 8 },
+ { "zqcs_op", 8, 8 },
+ { "zqcs_ma", 0, 8 },
+ { "MC_UPCTL_DTUPDES", 0x48094, 0 },
+ { "dtu_rd_missing", 13, 1 },
+ { "dtu_eaffl", 9, 4 },
+ { "dtu_random_error", 8, 1 },
+ { "dtu_err_b7", 7, 1 },
+ { "dtu_err_b6", 6, 1 },
+ { "dtu_err_b5", 5, 1 },
+ { "dtu_err_b4", 4, 1 },
+ { "dtu_err_b3", 3, 1 },
+ { "dtu_err_b2", 2, 1 },
+ { "dtu_err_b1", 1, 1 },
+ { "dtu_err_b0", 0, 1 },
+ { "MC_UPCTL_DTUNA", 0x48098, 0 },
+ { "MC_UPCTL_DTUNE", 0x4809c, 0 },
+ { "MC_UPCTL_DTUPRD0", 0x480a0, 0 },
+ { "dtu_allbits_1", 16, 16 },
+ { "dtu_allbits_0", 0, 16 },
+ { "MC_UPCTL_DTUPRD1", 0x480a4, 0 },
+ { "dtu_allbits_3", 16, 16 },
+ { "dtu_allbits_2", 0, 16 },
+ { "MC_UPCTL_DTUPRD2", 0x480a8, 0 },
+ { "dtu_allbits_5", 16, 16 },
+ { "dtu_allbits_4", 0, 16 },
+ { "MC_UPCTL_DTUPRD3", 0x480ac, 0 },
+ { "dtu_allbits_7", 16, 16 },
+ { "dtu_allbits_6", 0, 16 },
+ { "MC_UPCTL_DTUAWDT", 0x480b0, 0 },
+ { "number_ranks", 9, 2 },
+ { "row_addr_width", 6, 2 },
+ { "bank_addr_width", 3, 2 },
+ { "column_addr_width", 0, 2 },
+ { "MC_UPCTL_TOGCNT1U", 0x480c0, 0 },
+ { "MC_UPCTL_TINIT", 0x480c4, 0 },
+ { "MC_UPCTL_TRSTH", 0x480c8, 0 },
+ { "MC_UPCTL_TOGCNT100N", 0x480cc, 0 },
+ { "MC_UPCTL_TREFI", 0x480d0, 0 },
+ { "MC_UPCTL_TMRD", 0x480d4, 0 },
+ { "MC_UPCTL_TRFC", 0x480d8, 0 },
+ { "MC_UPCTL_TRP", 0x480dc, 0 },
+ { "prea_extra", 16, 2 },
+ { "t_rp", 0, 4 },
+ { "MC_UPCTL_TRTW", 0x480e0, 0 },
+ { "MC_UPCTL_TAL", 0x480e4, 0 },
+ { "MC_UPCTL_TCL", 0x480e8, 0 },
+ { "MC_UPCTL_TCWL", 0x480ec, 0 },
+ { "MC_UPCTL_TRAS", 0x480f0, 0 },
+ { "MC_UPCTL_TRC", 0x480f4, 0 },
+ { "MC_UPCTL_TRCD", 0x480f8, 0 },
+ { "MC_UPCTL_TRRD", 0x480fc, 0 },
+ { "MC_UPCTL_TRTP", 0x48100, 0 },
+ { "MC_UPCTL_TWR", 0x48104, 0 },
+ { "MC_UPCTL_TWTR", 0x48108, 0 },
+ { "MC_UPCTL_TEXSR", 0x4810c, 0 },
+ { "MC_UPCTL_TXP", 0x48110, 0 },
+ { "MC_UPCTL_TXPDLL", 0x48114, 0 },
+ { "MC_UPCTL_TZQCS", 0x48118, 0 },
+ { "MC_UPCTL_TZQCSI", 0x4811c, 0 },
+ { "MC_UPCTL_TDQS", 0x48120, 0 },
+ { "MC_UPCTL_TCKSRE", 0x48124, 0 },
+ { "MC_UPCTL_TCKSRX", 0x48128, 0 },
+ { "MC_UPCTL_TCKE", 0x4812c, 0 },
+ { "MC_UPCTL_TMOD", 0x48130, 0 },
+ { "MC_UPCTL_TRSTL", 0x48134, 0 },
+ { "MC_UPCTL_TZQCL", 0x48138, 0 },
+ { "MC_UPCTL_TMRR", 0x4813c, 0 },
+ { "MC_UPCTL_TCKESR", 0x48140, 0 },
+ { "MC_UPCTL_TDPD", 0x48144, 0 },
+ { "MC_UPCTL_ECCCFG", 0x48180, 0 },
+ { "inline_syn_en", 4, 1 },
+ { "ecc_en", 3, 1 },
+ { "ecc_intr_en", 2, 1 },
+ { "MC_UPCTL_ECCTST", 0x48184, 0 },
+ { "MC_UPCTL_ECCCLR", 0x48188, 0 },
+ { "clr_ecc_log", 1, 1 },
+ { "clr_ecc_intr", 0, 1 },
+ { "MC_UPCTL_ECCLOG", 0x4818c, 0 },
+ { "MC_UPCTL_DTUWACTL", 0x48200, 0 },
+ { "dtu_wr_rank", 30, 2 },
+ { "dtu_wr_row0", 13, 16 },
+ { "dtu_wr_bank", 10, 3 },
+ { "dtu_wr_col", 0, 10 },
+ { "MC_UPCTL_DTURACTL", 0x48204, 0 },
+ { "dtu_rd_rank", 30, 2 },
+ { "dtu_rd_row0", 13, 16 },
+ { "dtu_rd_bank", 10, 3 },
+ { "dtu_rd_col", 0, 10 },
+ { "MC_UPCTL_DTUCFG", 0x48208, 0 },
+ { "dtu_row_increments", 16, 7 },
+ { "dtu_wr_multi_rd", 15, 1 },
+ { "dtu_data_mask_en", 14, 1 },
+ { "dtu_target_lane", 10, 4 },
+ { "dtu_generate_random", 9, 1 },
+ { "dtu_incr_banks", 8, 1 },
+ { "dtu_incr_cols", 7, 1 },
+ { "dtu_nalen", 1, 6 },
+ { "dtu_enable", 0, 1 },
+ { "MC_UPCTL_DTUECTL", 0x4820c, 0 },
+ { "wr_multi_rd_rst", 2, 1 },
+ { "run_error_reports", 1, 1 },
+ { "run_dtu", 0, 1 },
+ { "MC_UPCTL_DTUWD0", 0x48210, 0 },
+ { "dtu_wr_byte3", 24, 8 },
+ { "dtu_wr_byte2", 16, 8 },
+ { "dtu_wr_byte1", 8, 8 },
+ { "dtu_wr_byte0", 0, 8 },
+ { "MC_UPCTL_DTUWD1", 0x48214, 0 },
+ { "dtu_wr_byte7", 24, 8 },
+ { "dtu_wr_byte6", 16, 8 },
+ { "dtu_wr_byte5", 8, 8 },
+ { "dtu_wr_byte4", 0, 8 },
+ { "MC_UPCTL_DTUWD2", 0x48218, 0 },
+ { "dtu_wr_byte11", 24, 8 },
+ { "dtu_wr_byte10", 16, 8 },
+ { "dtu_wr_byte9", 8, 8 },
+ { "dtu_wr_byte8", 0, 8 },
+ { "MC_UPCTL_DTUWD3", 0x4821c, 0 },
+ { "dtu_wr_byte15", 24, 8 },
+ { "dtu_wr_byte14", 16, 8 },
+ { "dtu_wr_byte13", 8, 8 },
+ { "dtu_wr_byte12", 0, 8 },
+ { "MC_UPCTL_DTUWDM", 0x48220, 0 },
+ { "MC_UPCTL_DTURD0", 0x48224, 0 },
+ { "dtu_rd_byte3", 24, 8 },
+ { "dtu_rd_byte2", 16, 8 },
+ { "dtu_rd_byte1", 8, 8 },
+ { "dtu_rd_byte0", 0, 8 },
+ { "MC_UPCTL_DTURD1", 0x48228, 0 },
+ { "dtu_rd_byte7", 24, 8 },
+ { "dtu_rd_byte6", 16, 8 },
+ { "dtu_rd_byte5", 8, 8 },
+ { "dtu_rd_byte4", 0, 8 },
+ { "MC_UPCTL_DTURD2", 0x4822c, 0 },
+ { "dtu_rd_byte11", 24, 8 },
+ { "dtu_rd_byte10", 16, 8 },
+ { "dtu_rd_byte9", 8, 8 },
+ { "dtu_rd_byte8", 0, 8 },
+ { "MC_UPCTL_DTURD3", 0x48230, 0 },
+ { "dtu_rd_byte15", 24, 8 },
+ { "dtu_rd_byte14", 16, 8 },
+ { "dtu_rd_byte13", 8, 8 },
+ { "dtu_rd_byte12", 0, 8 },
+ { "MC_UPCTL_DTULFSRWD", 0x48234, 0 },
+ { "MC_UPCTL_DTULFSRRD", 0x48238, 0 },
+ { "MC_UPCTL_DTUEAF", 0x4823c, 0 },
+ { "ea_rank", 30, 2 },
+ { "ea_row0", 13, 16 },
+ { "ea_bank", 10, 3 },
+ { "ea_column", 0, 10 },
+ { "MC_UPCTL_DFITCTRLDELAY", 0x48240, 0 },
+ { "MC_UPCTL_DFIODTCFG", 0x48244, 0 },
+ { "rank3_odt_default", 28, 1 },
+ { "rank3_odt_write_sel", 27, 1 },
+ { "rank3_odt_write_nsel", 26, 1 },
+ { "rank3_odt_read_sel", 25, 1 },
+ { "rank3_odt_read_nsel", 24, 1 },
+ { "rank2_odt_default", 20, 1 },
+ { "rank2_odt_write_sel", 19, 1 },
+ { "rank2_odt_write_nsel", 18, 1 },
+ { "rank2_odt_read_sel", 17, 1 },
+ { "rank2_odt_read_nsel", 16, 1 },
+ { "rank1_odt_default", 12, 1 },
+ { "rank1_odt_write_sel", 11, 1 },
+ { "rank1_odt_write_nsel", 10, 1 },
+ { "rank1_odt_read_sel", 9, 1 },
+ { "rank1_odt_read_nsel", 8, 1 },
+ { "rank0_odt_default", 4, 1 },
+ { "rank0_odt_write_sel", 3, 1 },
+ { "rank0_odt_write_nsel", 2, 1 },
+ { "rank0_odt_read_sel", 1, 1 },
+ { "rank0_odt_read_nsel", 0, 1 },
+ { "MC_UPCTL_DFIODTCFG1", 0x48248, 0 },
+ { "odt_len_b8_r", 24, 3 },
+ { "odt_len_bl8_w", 16, 3 },
+ { "odt_lat_r", 8, 5 },
+ { "odt_lat_w", 0, 5 },
+ { "MC_UPCTL_DFIODTRANKMAP", 0x4824c, 0 },
+ { "odt_rank_map3", 12, 4 },
+ { "odt_rank_map2", 8, 4 },
+ { "odt_rank_map1", 4, 4 },
+ { "odt_rank_map0", 0, 4 },
+ { "MC_UPCTL_DFITPHYWRDATA", 0x48250, 0 },
+ { "MC_UPCTL_DFITPHYWRLAT", 0x48254, 0 },
+ { "MC_UPCTL_DFITRDDATAEN", 0x48260, 0 },
+ { "MC_UPCTL_DFITPHYRDLAT", 0x48264, 0 },
+ { "MC_UPCTL_DFITPHYUPDTYPE0", 0x48270, 0 },
+ { "MC_UPCTL_DFITPHYUPDTYPE1", 0x48274, 0 },
+ { "MC_UPCTL_DFITPHYUPDTYPE2", 0x48278, 0 },
+ { "MC_UPCTL_DFITPHYUPDTYPE3", 0x4827c, 0 },
+ { "MC_UPCTL_DFITCTRLUPDMIN", 0x48280, 0 },
+ { "MC_UPCTL_DFITCTRLUPDMAX", 0x48284, 0 },
+ { "MC_UPCTL_DFITCTRLUPDDLY", 0x48288, 0 },
+ { "MC_UPCTL_DFIUPDCFG", 0x48290, 0 },
+ { "dfi_phyupd_en", 1, 1 },
+ { "dfi_ctrlupd_en", 0, 1 },
+ { "MC_UPCTL_DFITREFMSKI", 0x48294, 0 },
+ { "MC_UPCTL_DFITCTRLUPDI", 0x48298, 0 },
+ { "MC_UPCTL_DFITRCFG0", 0x482ac, 0 },
+ { "dfi_wrlvl_rank_sel", 16, 4 },
+ { "dfi_rdlvl_edge", 4, 9 },
+ { "dfi_rdlvl_rank_sel", 0, 4 },
+ { "MC_UPCTL_DFITRSTAT0", 0x482b0, 0 },
+ { "dfi_wrlvl_mode", 16, 2 },
+ { "dfi_rdlvl_gate_mode", 8, 2 },
+ { "dfi_rdlvl_mode", 0, 2 },
+ { "MC_UPCTL_DFITRWRLVLEN", 0x482b4, 0 },
+ { "MC_UPCTL_DFITRRDLVLEN", 0x482b8, 0 },
+ { "MC_UPCTL_DFITRRDLVLGATEEN", 0x482bc, 0 },
+ { "MC_UPCTL_DFISTSTAT0", 0x482c0, 0 },
+ { "dfi_data_byte_disable", 16, 9 },
+ { "dfi_freq_ratio", 4, 2 },
+ { "dfi_init_start0", 1, 1 },
+ { "dfi_init_complete", 0, 1 },
+ { "MC_UPCTL_DFISTCFG0", 0x482c4, 0 },
+ { "dfi_data_byte_disable_en", 2, 1 },
+ { "dfi_freq_ratio_en", 1, 1 },
+ { "dfi_init_start", 0, 1 },
+ { "MC_UPCTL_DFISTCFG1", 0x482c8, 0 },
+ { "dfi_dram_clk_disable_en_dpd", 1, 1 },
+ { "dfi_dram_clk_disable_en", 0, 1 },
+ { "MC_UPCTL_DFITDRAMCLKEN", 0x482d0, 0 },
+ { "MC_UPCTL_DFITDRAMCLKDIS", 0x482d4, 0 },
+ { "MC_UPCTL_DFISTCFG2", 0x482d8, 0 },
+ { "parity_en", 1, 1 },
+ { "parity_intr_en", 0, 1 },
+ { "MC_UPCTL_DFISTPARCLR", 0x482dc, 0 },
+ { "parity_log_clr", 1, 1 },
+ { "parity_intr_clr", 0, 1 },
+ { "MC_UPCTL_DFISTPARLOG", 0x482e0, 0 },
+ { "MC_UPCTL_DFILPCFG0", 0x482f0, 0 },
+ { "dfi_lp_wakeup_dpd", 28, 4 },
+ { "dfi_lp_en_dpd", 24, 1 },
+ { "dfi_tlp_resp", 16, 4 },
+ { "dfi_lp_en_sr", 8, 1 },
+ { "dfi_lp_wakeup_pd", 4, 4 },
+ { "dfi_lp_en_pd", 0, 1 },
+ { "MC_UPCTL_DFITRWRLVLRESP0", 0x48300, 0 },
+ { "MC_UPCTL_DFITRWRLVLRESP1", 0x48304, 0 },
+ { "MC_UPCTL_DFITRWRLVLRESP2", 0x48308, 0 },
+ { "MC_UPCTL_DFITRRDLVLRESP0", 0x4830c, 0 },
+ { "MC_UPCTL_DFITRRDLVLRESP1", 0x48310, 0 },
+ { "MC_UPCTL_DFITRRDLVLRESP2", 0x48314, 0 },
+ { "MC_UPCTL_DFITRWRLVLDELAY0", 0x48318, 0 },
+ { "MC_UPCTL_DFITRWRLVLDELAY1", 0x4831c, 0 },
+ { "MC_UPCTL_DFITRWRLVLDELAY2", 0x48320, 0 },
+ { "MC_UPCTL_DFITRRDLVLDELAY0", 0x48324, 0 },
+ { "MC_UPCTL_DFITRRDLVLDELAY1", 0x48328, 0 },
+ { "MC_UPCTL_DFITRRDLVLDELAY2", 0x4832c, 0 },
+ { "MC_UPCTL_DFITRRDLVLGATEDELAY0", 0x48330, 0 },
+ { "MC_UPCTL_DFITRRDLVLGATEDELAY1", 0x48334, 0 },
+ { "MC_UPCTL_DFITRRDLVLGATEDELAY2", 0x48338, 0 },
+ { "MC_UPCTL_DFITRCMD", 0x4833c, 0 },
+ { "dfitrcmd_start", 31, 1 },
+ { "dfitrcmd_en", 4, 9 },
+ { "dfitrcmd_opcode", 0, 2 },
+ { "MC_UPCTL_IPVR", 0x483f8, 0 },
+ { "MC_UPCTL_IPTR", 0x483fc, 0 },
+ { "MC_P_DDRPHY_RST_CTRL", 0x49300, 0 },
+ { "PHY_DRAM_WL", 17, 5 },
+ { "PHY_CALIB_DONE", 5, 1 },
+ { "CTL_CAL_REQ", 4, 1 },
+ { "CTL_CKE", 3, 1 },
+ { "CTL_RST_N", 2, 1 },
+ { "DDRIO_ENABLE", 1, 1 },
+ { "PHY_RST_N", 0, 1 },
+ { "MC_P_PERFORMANCE_CTRL", 0x49304, 0 },
+ { "STALL_CHK_BIT", 2, 1 },
+ { "DDR3_BRC_MODE", 1, 1 },
+ { "RMW_PERF_CTRL", 0, 1 },
+ { "MC_P_ECC_CTRL", 0x49308, 0 },
+ { "ECC_BYPASS_BIST", 1, 1 },
+ { "ECC_DISABLE", 0, 1 },
+ { "MC_P_PAR_ENABLE", 0x4930c, 0 },
+ { "ECC_UE_PAR_ENABLE", 3, 1 },
+ { "ECC_CE_PAR_ENABLE", 2, 1 },
+ { "PERR_REG_INT_ENABLE", 1, 1 },
+ { "PERR_BLK_INT_ENABLE", 0, 1 },
+ { "MC_P_PAR_CAUSE", 0x49310, 0 },
+ { "ECC_UE_PAR_CAUSE", 3, 1 },
+ { "ECC_CE_PAR_CAUSE", 2, 1 },
+ { "FIFOR_PAR_CAUSE", 1, 1 },
+ { "RDATA_FIFOR_PAR_CAUSE", 0, 1 },
+ { "MC_P_INT_ENABLE", 0x49314, 0 },
+ { "ECC_UE_INT_ENABLE", 2, 1 },
+ { "ECC_CE_INT_ENABLE", 1, 1 },
+ { "PERR_INT_ENABLE", 0, 1 },
+ { "MC_P_INT_CAUSE", 0x49318, 0 },
+ { "ECC_UE_INT_CAUSE", 2, 1 },
+ { "ECC_CE_INT_CAUSE", 1, 1 },
+ { "PERR_INT_CAUSE", 0, 1 },
+ { "MC_P_ECC_STATUS", 0x4931c, 0 },
+ { "ECC_CECNT", 16, 16 },
+ { "ECC_UECNT", 0, 16 },
+ { "MC_P_PHY_CTRL", 0x49320, 0 },
+ { "MC_P_STATIC_CFG_STATUS", 0x49324, 0 },
+ { "STATIC_AWEN", 23, 1 },
+ { "STATIC_SWLAT", 18, 5 },
+ { "STATIC_WLAT", 17, 1 },
+ { "STATIC_ALIGN", 16, 1 },
+ { "STATIC_SLAT", 11, 5 },
+ { "STATIC_LAT", 10, 1 },
+ { "STATIC_MODE", 9, 1 },
+ { "STATIC_DEN", 6, 3 },
+ { "STATIC_ORG", 5, 1 },
+ { "STATIC_RKS", 4, 1 },
+ { "STATIC_WIDTH", 1, 3 },
+ { "STATIC_SLOW", 0, 1 },
+ { "MC_P_CORE_PCTL_STAT", 0x49328, 0 },
+ { "MC_P_DEBUG_CNT", 0x4932c, 0 },
+ { "WDATA_OCNT", 8, 5 },
+ { "RDATA_OCNT", 0, 5 },
+ { "MC_CE_ERR_DATA_RDATA", 0x49330, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x49334, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x49338, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x4933c, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x49340, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x49344, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x49348, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x4934c, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x49350, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x49354, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x49358, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x4935c, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x49360, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x49364, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x49368, 0 },
+ { "MC_CE_COR_DATA_RDATA", 0x4936c, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x49370, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x49374, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x49378, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x4937c, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x49380, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x49384, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x49388, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x4938c, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x49390, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x49394, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x49398, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x4939c, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x493a0, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x493a4, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x493a8, 0 },
+ { "MC_UE_COR_DATA_RDATA", 0x493ac, 0 },
+ { "MC_CE_ADDR", 0x493b0, 0 },
+ { "MC_UE_ADDR", 0x493b4, 0 },
+ { "MC_P_DEEP_SLEEP", 0x493b8, 0 },
+ { "SleepStatus", 1, 1 },
+ { "SleepReq", 0, 1 },
+ { "MC_P_FPGA_BONUS", 0x493bc, 0 },
+ { "MC_P_DEBUG_CFG", 0x493c0, 0 },
+ { "DEBUG_OR", 15, 1 },
+ { "DEBUG_HI", 14, 1 },
+ { "DEBUG_RPT", 13, 1 },
+ { "DEBUGPAGE", 10, 3 },
+ { "DEBUGSELH", 5, 5 },
+ { "DEBUGSELL", 0, 5 },
+ { "MC_P_DEBUG_RPT", 0x493c4, 0 },
+ { "MC_P_BIST_CMD", 0x49400, 0 },
+ { "START_BIST", 31, 1 },
+ { "BURST_LEN", 16, 2 },
+ { "BIST_CMD_GAP", 8, 8 },
+ { "BIST_OPCODE", 0, 2 },
+ { "MC_P_BIST_CMD_ADDR", 0x49404, 0 },
+ { "MC_P_BIST_CMD_LEN", 0x49408, 0 },
+ { "MC_P_BIST_DATA_PATTERN", 0x4940c, 0 },
+ { "MC_P_BIST_USER_WDATA0", 0x49414, 0 },
+ { "MC_P_BIST_USER_WDATA1", 0x49418, 0 },
+ { "MC_P_BIST_USER_WDATA2", 0x4941c, 0 },
+ { "USER_DATA_MASK", 8, 9 },
+ { "USER_DATA2", 0, 8 },
+ { "MC_P_BIST_NUM_ERR", 0x49480, 0 },
+ { "MC_P_BIST_ERR_FIRST_ADDR", 0x49484, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x49488, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x4948c, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x49490, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x49494, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x49498, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x4949c, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494a0, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494a4, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494a8, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494ac, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494b0, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494b4, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494b8, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494bc, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494c0, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494c4, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494c8, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x494cc, 0 },
+ { "MC_P_BIST_CRC_SEED", 0x494d0, 0 },
+ { NULL }
+};
+
+struct reg_info t5_edc_t50_regs[] = {
+ { "EDC_H_REF", 0x50000, 0 },
+ { "SleepStatus", 31, 1 },
+ { "SleepReq", 30, 1 },
+ { "PING_PONG", 29, 1 },
+ { "EDC_INST_NUM", 18, 1 },
+ { "ENABLE_PERF", 17, 1 },
+ { "ECC_BYPASS", 16, 1 },
+ { "RefFreq", 0, 16 },
+ { "EDC_H_BIST_CMD", 0x50004, 0 },
+ { "START_BIST", 31, 1 },
+ { "BURST_LEN", 16, 2 },
+ { "BIST_CMD_GAP", 8, 8 },
+ { "BIST_OPCODE", 0, 2 },
+ { "EDC_H_BIST_CMD_ADDR", 0x50008, 0 },
+ { "EDC_H_BIST_CMD_LEN", 0x5000c, 0 },
+ { "EDC_H_BIST_DATA_PATTERN", 0x50010, 0 },
+ { "EDC_H_BIST_USER_WDATA0", 0x50014, 0 },
+ { "EDC_H_BIST_USER_WDATA1", 0x50018, 0 },
+ { "EDC_H_BIST_USER_WDATA2", 0x5001c, 0 },
+ { "USER_DATA_MASK", 8, 9 },
+ { "USER_DATA2", 0, 8 },
+ { "EDC_H_BIST_NUM_ERR", 0x50020, 0 },
+ { "EDC_H_BIST_ERR_FIRST_ADDR", 0x50024, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50028, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5002c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50030, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50034, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50038, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5003c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50040, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50044, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50048, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5004c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50050, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50054, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50058, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5005c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50060, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50064, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50068, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5006c, 0 },
+ { "EDC_H_PAR_ENABLE", 0x50070, 0 },
+ { "ECC_UE_PAR_ENABLE", 2, 1 },
+ { "ECC_CE_PAR_ENABLE", 1, 1 },
+ { "PERR_PAR_ENABLE", 0, 1 },
+ { "EDC_H_INT_ENABLE", 0x50074, 0 },
+ { "ECC_UE_INT_ENABLE", 2, 1 },
+ { "ECC_CE_INT_ENABLE", 1, 1 },
+ { "PERR_INT_ENABLE", 0, 1 },
+ { "EDC_H_INT_CAUSE", 0x50078, 0 },
+ { "ECC_UE_INT0_CAUSE", 5, 1 },
+ { "ECC_CE_INT0_CAUSE", 4, 1 },
+ { "PERR_INT0_CAUSE", 3, 1 },
+ { "ECC_UE_INT_CAUSE", 2, 1 },
+ { "ECC_CE_INT_CAUSE", 1, 1 },
+ { "PERR_INT_CAUSE", 0, 1 },
+ { "EDC_H_ECC_STATUS", 0x5007c, 0 },
+ { "ECC_CECNT", 16, 16 },
+ { "ECC_UECNT", 0, 16 },
+ { "EDC_H_ECC_ERR_SEL", 0x50080, 0 },
+ { "EDC_H_ECC_ERR_ADDR", 0x50084, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50090, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50094, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50098, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x5009c, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500a0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500a4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500a8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500ac, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500b0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500b4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500b8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500bc, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500c0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500c4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500c8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500cc, 0 },
+ { "EDC_H_BIST_CRC_SEED", 0x50400, 0 },
+ { NULL }
+};
+
+struct reg_info t5_edc_t51_regs[] = {
+ { "EDC_H_REF", 0x50800, 0 },
+ { "SleepStatus", 31, 1 },
+ { "SleepReq", 30, 1 },
+ { "PING_PONG", 29, 1 },
+ { "EDC_INST_NUM", 18, 1 },
+ { "ENABLE_PERF", 17, 1 },
+ { "ECC_BYPASS", 16, 1 },
+ { "RefFreq", 0, 16 },
+ { "EDC_H_BIST_CMD", 0x50804, 0 },
+ { "START_BIST", 31, 1 },
+ { "BURST_LEN", 16, 2 },
+ { "BIST_CMD_GAP", 8, 8 },
+ { "BIST_OPCODE", 0, 2 },
+ { "EDC_H_BIST_CMD_ADDR", 0x50808, 0 },
+ { "EDC_H_BIST_CMD_LEN", 0x5080c, 0 },
+ { "EDC_H_BIST_DATA_PATTERN", 0x50810, 0 },
+ { "EDC_H_BIST_USER_WDATA0", 0x50814, 0 },
+ { "EDC_H_BIST_USER_WDATA1", 0x50818, 0 },
+ { "EDC_H_BIST_USER_WDATA2", 0x5081c, 0 },
+ { "USER_DATA_MASK", 8, 9 },
+ { "USER_DATA2", 0, 8 },
+ { "EDC_H_BIST_NUM_ERR", 0x50820, 0 },
+ { "EDC_H_BIST_ERR_FIRST_ADDR", 0x50824, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50828, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5082c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50830, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50834, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50838, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5083c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50840, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50844, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50848, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5084c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50850, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50854, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50858, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5085c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50860, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50864, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50868, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5086c, 0 },
+ { "EDC_H_PAR_ENABLE", 0x50870, 0 },
+ { "ECC_UE_PAR_ENABLE", 2, 1 },
+ { "ECC_CE_PAR_ENABLE", 1, 1 },
+ { "PERR_PAR_ENABLE", 0, 1 },
+ { "EDC_H_INT_ENABLE", 0x50874, 0 },
+ { "ECC_UE_INT_ENABLE", 2, 1 },
+ { "ECC_CE_INT_ENABLE", 1, 1 },
+ { "PERR_INT_ENABLE", 0, 1 },
+ { "EDC_H_INT_CAUSE", 0x50878, 0 },
+ { "ECC_UE_INT0_CAUSE", 5, 1 },
+ { "ECC_CE_INT0_CAUSE", 4, 1 },
+ { "PERR_INT0_CAUSE", 3, 1 },
+ { "ECC_UE_INT_CAUSE", 2, 1 },
+ { "ECC_CE_INT_CAUSE", 1, 1 },
+ { "PERR_INT_CAUSE", 0, 1 },
+ { "EDC_H_ECC_STATUS", 0x5087c, 0 },
+ { "ECC_CECNT", 16, 16 },
+ { "ECC_UECNT", 0, 16 },
+ { "EDC_H_ECC_ERR_SEL", 0x50880, 0 },
+ { "EDC_H_ECC_ERR_ADDR", 0x50884, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50890, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50894, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50898, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x5089c, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508a0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508a4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508a8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508ac, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508b0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508b4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508b8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508bc, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508c0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508c4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508c8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508cc, 0 },
+ { "EDC_H_BIST_CRC_SEED", 0x50c00, 0 },
+ { NULL }
+};
+
+struct reg_info t5_hma_t5_regs[] = {
+ { "HMA_TABLE_ACCESS", 0x51000, 0 },
+ { "TRIG", 31, 1 },
+ { "RW", 30, 1 },
+ { "L_SEL", 0, 4 },
+ { "HMA_TABLE_LINE0", 0x51004, 0 },
+ { "HMA_TABLE_LINE1", 0x51008, 0 },
+ { "HMA_TABLE_LINE2", 0x5100c, 0 },
+ { "HMA_TABLE_LINE3", 0x51010, 0 },
+ { "HMA_TABLE_LINE4", 0x51014, 0 },
+ { "HMA_TABLE_LINE5", 0x51018, 0 },
+ { "FID", 16, 11 },
+ { "NOS", 15, 1 },
+ { "RO", 14, 1 },
+ { "HMA_COOKIE", 0x5101c, 0 },
+ { "C_REQ", 31, 1 },
+ { "C_FID", 18, 11 },
+ { "C_VAL", 8, 10 },
+ { "C_SEL", 0, 4 },
+ { "HMA_PAR_ENABLE", 0x51300, 0 },
+ { "HMA_INT_ENABLE", 0x51304, 0 },
+ { "HMA_INT_CAUSE", 0x51308, 0 },
+ { NULL }
+};
diff --git a/usr/src/cmd/cxgbetool/reg_defs_t6.c b/usr/src/cmd/cxgbetool/reg_defs_t6.c
new file mode 100644
index 0000000000..62e281d67f
--- /dev/null
+++ b/usr/src/cmd/cxgbetool/reg_defs_t6.c
@@ -0,0 +1,56438 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright (c) 2019 by Chelsio Communications, Inc.
+ */
+
+struct reg_info t6_sge_regs[] = {
+ { "SGE_PF_KDOORBELL", 0x1e000, 0 },
+ { "QID", 15, 17 },
+ { "Sync", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1e004, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1e008, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1e00c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1e400, 0 },
+ { "QID", 15, 17 },
+ { "Sync", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1e404, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1e408, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1e40c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1e800, 0 },
+ { "QID", 15, 17 },
+ { "Sync", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1e804, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1e808, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1e80c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1ec00, 0 },
+ { "QID", 15, 17 },
+ { "Sync", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1ec04, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1ec08, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1ec0c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1f000, 0 },
+ { "QID", 15, 17 },
+ { "Sync", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1f004, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1f008, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1f00c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1f400, 0 },
+ { "QID", 15, 17 },
+ { "Sync", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1f404, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1f408, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1f40c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1f800, 0 },
+ { "QID", 15, 17 },
+ { "Sync", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1f804, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1f808, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1f80c, 0 },
+ { "SGE_PF_KDOORBELL", 0x1fc00, 0 },
+ { "QID", 15, 17 },
+ { "Sync", 14, 1 },
+ { "Type", 13, 1 },
+ { "PIDX", 0, 13 },
+ { "SGE_PF_GTS", 0x1fc04, 0 },
+ { "IngressQID", 16, 16 },
+ { "TimerReg", 13, 3 },
+ { "SEIntArm", 12, 1 },
+ { "CIDXInc", 0, 12 },
+ { "SGE_PF_KTIMESTAMP_LO", 0x1fc08, 0 },
+ { "SGE_PF_KTIMESTAMP_HI", 0x1fc0c, 0 },
+ { "SGE_CONTROL", 0x1008, 0 },
+ { "IgrAllCPLtoFL", 31, 1 },
+ { "FLSplitMin", 22, 9 },
+ { "RxPktCPLMode", 18, 1 },
+ { "EgrStatusPageSize", 17, 1 },
+ { "IngHintEnable1", 15, 1 },
+ { "IngHintEnable0", 14, 1 },
+ { "IngIntCompareIDX", 13, 1 },
+ { "PktShift", 10, 3 },
+ { "IngPCIeBoundary", 7, 3 },
+ { "IngPadBoundary", 4, 3 },
+ { "GlobalEnable", 0, 1 },
+ { "SGE_HOST_PAGE_SIZE", 0x100c, 0 },
+ { "HostPageSizePF7", 28, 4 },
+ { "HostPageSizePF6", 24, 4 },
+ { "HostPageSizePF5", 20, 4 },
+ { "HostPageSizePF4", 16, 4 },
+ { "HostPageSizePF3", 12, 4 },
+ { "HostPageSizePF2", 8, 4 },
+ { "HostPageSizePF1", 4, 4 },
+ { "HostPageSizePF0", 0, 4 },
+ { "SGE_EGRESS_QUEUES_PER_PAGE_PF", 0x1010, 0 },
+ { "QueuesPerPagePF7", 28, 4 },
+ { "QueuesPerPagePF6", 24, 4 },
+ { "QueuesPerPagePF5", 20, 4 },
+ { "QueuesPerPagePF4", 16, 4 },
+ { "QueuesPerPagePF3", 12, 4 },
+ { "QueuesPerPagePF2", 8, 4 },
+ { "QueuesPerPagePF1", 4, 4 },
+ { "QueuesPerPagePF0", 0, 4 },
+ { "SGE_EGRESS_QUEUES_PER_PAGE_VF", 0x1014, 0 },
+ { "QueuesPerPageVFPF7", 28, 4 },
+ { "QueuesPerPageVFPF6", 24, 4 },
+ { "QueuesPerPageVFPF5", 20, 4 },
+ { "QueuesPerPageVFPF4", 16, 4 },
+ { "QueuesPerPageVFPF3", 12, 4 },
+ { "QueuesPerPageVFPF2", 8, 4 },
+ { "QueuesPerPageVFPF1", 4, 4 },
+ { "QueuesPerPageVFPF0", 0, 4 },
+ { "SGE_USER_MODE_LIMITS", 0x1018, 0 },
+ { "Opcode_Min", 24, 8 },
+ { "Opcode_Max", 16, 8 },
+ { "Length_Min", 8, 8 },
+ { "Length_Max", 0, 8 },
+ { "SGE_WR_ERROR", 0x101c, 0 },
+ { "SGE_INT_CAUSE1", 0x1024, 0 },
+ { "perr_flm_CreditFifo", 30, 1 },
+ { "perr_imsg_hint_fifo", 29, 1 },
+ { "perr_pc_rsp", 23, 1 },
+ { "perr_pc_req", 22, 1 },
+ { "perr_dbp_pc_rsp_fifo3", 21, 1 },
+ { "perr_dbp_pc_rsp_fifo2", 20, 1 },
+ { "perr_dbp_pc_rsp_fifo1", 19, 1 },
+ { "perr_dbp_pc_rsp_fifo0", 18, 1 },
+ { "perr_dmarbt", 17, 1 },
+ { "perr_flm_DbpFifo", 16, 1 },
+ { "perr_flm_MCReq_fifo", 15, 1 },
+ { "perr_flm_HintFifo", 14, 1 },
+ { "perr_align_ctl_fifo3", 13, 1 },
+ { "perr_align_ctl_fifo2", 12, 1 },
+ { "perr_align_ctl_fifo1", 11, 1 },
+ { "perr_align_ctl_fifo0", 10, 1 },
+ { "perr_edma_fifo3", 9, 1 },
+ { "perr_edma_fifo2", 8, 1 },
+ { "perr_edma_fifo1", 7, 1 },
+ { "perr_edma_fifo0", 6, 1 },
+ { "perr_pd_fifo3", 5, 1 },
+ { "perr_pd_fifo2", 4, 1 },
+ { "perr_pd_fifo1", 3, 1 },
+ { "perr_pd_fifo0", 2, 1 },
+ { "perr_ing_ctxt_mifrsp", 1, 1 },
+ { "perr_egr_ctxt_mifrsp", 0, 1 },
+ { "SGE_INT_ENABLE1", 0x1028, 0 },
+ { "perr_flm_CreditFifo", 30, 1 },
+ { "perr_imsg_hint_fifo", 29, 1 },
+ { "perr_pc_rsp", 23, 1 },
+ { "perr_pc_req", 22, 1 },
+ { "perr_dbp_pc_rsp_fifo3", 21, 1 },
+ { "perr_dbp_pc_rsp_fifo2", 20, 1 },
+ { "perr_dbp_pc_rsp_fifo1", 19, 1 },
+ { "perr_dbp_pc_rsp_fifo0", 18, 1 },
+ { "perr_dmarbt", 17, 1 },
+ { "perr_flm_DbpFifo", 16, 1 },
+ { "perr_flm_MCReq_fifo", 15, 1 },
+ { "perr_flm_HintFifo", 14, 1 },
+ { "perr_align_ctl_fifo3", 13, 1 },
+ { "perr_align_ctl_fifo2", 12, 1 },
+ { "perr_align_ctl_fifo1", 11, 1 },
+ { "perr_align_ctl_fifo0", 10, 1 },
+ { "perr_edma_fifo3", 9, 1 },
+ { "perr_edma_fifo2", 8, 1 },
+ { "perr_edma_fifo1", 7, 1 },
+ { "perr_edma_fifo0", 6, 1 },
+ { "perr_pd_fifo3", 5, 1 },
+ { "perr_pd_fifo2", 4, 1 },
+ { "perr_pd_fifo1", 3, 1 },
+ { "perr_pd_fifo0", 2, 1 },
+ { "perr_ing_ctxt_mifrsp", 1, 1 },
+ { "perr_egr_ctxt_mifrsp", 0, 1 },
+ { "SGE_PERR_ENABLE1", 0x102c, 0 },
+ { "perr_flm_CreditFifo", 30, 1 },
+ { "perr_imsg_hint_fifo", 29, 1 },
+ { "perr_pc_rsp", 23, 1 },
+ { "perr_pc_req", 22, 1 },
+ { "perr_dbp_pc_rsp_fifo3", 21, 1 },
+ { "perr_dbp_pc_rsp_fifo2", 20, 1 },
+ { "perr_dbp_pc_rsp_fifo1", 19, 1 },
+ { "perr_dbp_pc_rsp_fifo0", 18, 1 },
+ { "perr_dmarbt", 17, 1 },
+ { "perr_flm_DbpFifo", 16, 1 },
+ { "perr_flm_MCReq_fifo", 15, 1 },
+ { "perr_flm_HintFifo", 14, 1 },
+ { "perr_align_ctl_fifo3", 13, 1 },
+ { "perr_align_ctl_fifo2", 12, 1 },
+ { "perr_align_ctl_fifo1", 11, 1 },
+ { "perr_align_ctl_fifo0", 10, 1 },
+ { "perr_edma_fifo3", 9, 1 },
+ { "perr_edma_fifo2", 8, 1 },
+ { "perr_edma_fifo1", 7, 1 },
+ { "perr_edma_fifo0", 6, 1 },
+ { "perr_pd_fifo3", 5, 1 },
+ { "perr_pd_fifo2", 4, 1 },
+ { "perr_pd_fifo1", 3, 1 },
+ { "perr_pd_fifo0", 2, 1 },
+ { "perr_ing_ctxt_mifrsp", 1, 1 },
+ { "perr_egr_ctxt_mifrsp", 0, 1 },
+ { "SGE_INT_CAUSE2", 0x1030, 0 },
+ { "perr_dbp_hint_fl_fifo", 24, 1 },
+ { "perr_egr_dbp_tx_coal", 23, 1 },
+ { "perr_dbp_fl_fifo", 22, 1 },
+ { "deq_ll_perr", 21, 1 },
+ { "enq_perr", 20, 1 },
+ { "deq_out_perr", 19, 1 },
+ { "buf_perr", 18, 1 },
+ { "perr_conm_sram", 14, 1 },
+ { "perr_isw_idma0_fifo", 12, 1 },
+ { "perr_isw_idma1_fifo", 11, 1 },
+ { "perr_isw_dbp_fifo", 10, 1 },
+ { "perr_isw_gts_fifo", 9, 1 },
+ { "perr_itp_evr", 8, 1 },
+ { "perr_flm_cntxmem", 7, 1 },
+ { "perr_flm_l1Cache", 6, 1 },
+ { "perr_dbp_hint_fifo", 5, 1 },
+ { "perr_dbp_hp_fifo", 4, 1 },
+ { "perr_db_fifo", 3, 1 },
+ { "perr_ing_ctxt_cache", 2, 1 },
+ { "perr_egr_ctxt_cache", 1, 1 },
+ { "perr_base_size", 0, 1 },
+ { "SGE_INT_ENABLE2", 0x1034, 0 },
+ { "perr_dbp_hint_fl_fifo", 24, 1 },
+ { "perr_egr_dbp_tx_coal", 23, 1 },
+ { "perr_dbp_fl_fifo", 22, 1 },
+ { "deq_ll_perr", 21, 1 },
+ { "enq_perr", 20, 1 },
+ { "deq_out_perr", 19, 1 },
+ { "buf_perr", 18, 1 },
+ { "perr_conm_sram", 14, 1 },
+ { "perr_isw_idma0_fifo", 12, 1 },
+ { "perr_isw_idma1_fifo", 11, 1 },
+ { "perr_isw_dbp_fifo", 10, 1 },
+ { "perr_isw_gts_fifo", 9, 1 },
+ { "perr_itp_evr", 8, 1 },
+ { "perr_flm_cntxmem", 7, 1 },
+ { "perr_flm_l1Cache", 6, 1 },
+ { "perr_dbp_hint_fifo", 5, 1 },
+ { "perr_dbp_hp_fifo", 4, 1 },
+ { "perr_db_fifo", 3, 1 },
+ { "perr_ing_ctxt_cache", 2, 1 },
+ { "perr_egr_ctxt_cache", 1, 1 },
+ { "perr_base_size", 0, 1 },
+ { "SGE_PERR_ENABLE2", 0x1038, 0 },
+ { "perr_dbp_hint_fl_fifo", 24, 1 },
+ { "perr_egr_dbp_tx_coal", 23, 1 },
+ { "perr_dbp_fl_fifo", 22, 1 },
+ { "deq_ll_perr", 21, 1 },
+ { "enq_perr", 20, 1 },
+ { "deq_out_perr", 19, 1 },
+ { "buf_perr", 18, 1 },
+ { "perr_conm_sram", 14, 1 },
+ { "perr_isw_idma0_fifo", 12, 1 },
+ { "perr_isw_idma1_fifo", 11, 1 },
+ { "perr_isw_dbp_fifo", 10, 1 },
+ { "perr_isw_gts_fifo", 9, 1 },
+ { "perr_itp_evr", 8, 1 },
+ { "perr_flm_cntxmem", 7, 1 },
+ { "perr_flm_l1Cache", 6, 1 },
+ { "perr_dbp_hint_fifo", 5, 1 },
+ { "perr_dbp_hp_fifo", 4, 1 },
+ { "perr_dbp_lp_fifo", 3, 1 },
+ { "perr_ing_ctxt_cache", 2, 1 },
+ { "perr_egr_ctxt_cache", 1, 1 },
+ { "perr_base_size", 0, 1 },
+ { "SGE_INT_CAUSE3", 0x103c, 0 },
+ { "err_flm_dbp", 31, 1 },
+ { "err_flm_idma1", 30, 1 },
+ { "err_flm_idma0", 29, 1 },
+ { "err_flm_hint", 28, 1 },
+ { "err_pcie_error3", 27, 1 },
+ { "err_pcie_error2", 26, 1 },
+ { "err_pcie_error1", 25, 1 },
+ { "err_pcie_error0", 24, 1 },
+ { "err_timer_above_max_qid", 23, 1 },
+ { "err_cpl_exceed_iqe_size", 22, 1 },
+ { "err_invalid_cidx_inc", 21, 1 },
+ { "err_itp_time_paused", 20, 1 },
+ { "err_cpl_opcode_0", 19, 1 },
+ { "err_dropped_db", 18, 1 },
+ { "err_data_cpl_on_high_qid1", 17, 1 },
+ { "err_data_cpl_on_high_qid0", 16, 1 },
+ { "err_bad_db_pidx3", 15, 1 },
+ { "err_bad_db_pidx2", 14, 1 },
+ { "err_bad_db_pidx1", 13, 1 },
+ { "err_bad_db_pidx0", 12, 1 },
+ { "err_ing_pcie_chan", 11, 1 },
+ { "err_ing_ctxt_prio", 10, 1 },
+ { "err_egr_ctxt_prio", 9, 1 },
+ { "dbp_tbuf_full", 8, 1 },
+ { "fatal_wre_len", 7, 1 },
+ { "reg_address_err", 6, 1 },
+ { "ingress_size_err", 5, 1 },
+ { "egress_size_err", 4, 1 },
+ { "err_inv_ctxt3", 3, 1 },
+ { "err_inv_ctxt2", 2, 1 },
+ { "err_inv_ctxt1", 1, 1 },
+ { "err_inv_ctxt0", 0, 1 },
+ { "SGE_INT_ENABLE3", 0x1040, 0 },
+ { "err_flm_dbp", 31, 1 },
+ { "err_flm_idma1", 30, 1 },
+ { "err_flm_idma0", 29, 1 },
+ { "err_flm_hint", 28, 1 },
+ { "err_pcie_error3", 27, 1 },
+ { "err_pcie_error2", 26, 1 },
+ { "err_pcie_error1", 25, 1 },
+ { "err_pcie_error0", 24, 1 },
+ { "err_timer_above_max_qid", 23, 1 },
+ { "err_cpl_exceed_iqe_size", 22, 1 },
+ { "err_invalid_cidx_inc", 21, 1 },
+ { "err_itp_time_paused", 20, 1 },
+ { "err_cpl_opcode_0", 19, 1 },
+ { "err_dropped_db", 18, 1 },
+ { "err_data_cpl_on_high_qid1", 17, 1 },
+ { "err_data_cpl_on_high_qid0", 16, 1 },
+ { "err_bad_db_pidx3", 15, 1 },
+ { "err_bad_db_pidx2", 14, 1 },
+ { "err_bad_db_pidx1", 13, 1 },
+ { "err_bad_db_pidx0", 12, 1 },
+ { "err_ing_pcie_chan", 11, 1 },
+ { "err_ing_ctxt_prio", 10, 1 },
+ { "err_egr_ctxt_prio", 9, 1 },
+ { "dbp_tbuf_full", 8, 1 },
+ { "fatal_wre_len", 7, 1 },
+ { "reg_address_err", 6, 1 },
+ { "ingress_size_err", 5, 1 },
+ { "egress_size_err", 4, 1 },
+ { "err_inv_ctxt3", 3, 1 },
+ { "err_inv_ctxt2", 2, 1 },
+ { "err_inv_ctxt1", 1, 1 },
+ { "err_inv_ctxt0", 0, 1 },
+ { "SGE_FL_BUFFER_SIZE0", 0x1044, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE1", 0x1048, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE2", 0x104c, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE3", 0x1050, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE4", 0x1054, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE5", 0x1058, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE6", 0x105c, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE7", 0x1060, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE8", 0x1064, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE9", 0x1068, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE10", 0x106c, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE11", 0x1070, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE12", 0x1074, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE13", 0x1078, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE14", 0x107c, 0 },
+ { "Size", 4, 20 },
+ { "SGE_FL_BUFFER_SIZE15", 0x1080, 0 },
+ { "Size", 4, 20 },
+ { "SGE_DBQ_CTXT_BADDR", 0x1084, 0 },
+ { "BaseAddr", 3, 29 },
+ { "SGE_IMSG_CTXT_BADDR", 0x1088, 0 },
+ { "BaseAddr", 3, 29 },
+ { "SGE_FLM_CACHE_BADDR", 0x108c, 0 },
+ { "BaseAddr", 3, 29 },
+ { "SGE_FLM_CFG", 0x1090, 0 },
+ { "OpMode", 26, 6 },
+ { "NullPtr", 20, 4 },
+ { "NullPtrEn", 19, 1 },
+ { "NoHdr", 18, 1 },
+ { "CachePtrCnt", 16, 2 },
+ { "EDRAMPtrCnt", 14, 2 },
+ { "HdrStartFLQ", 11, 3 },
+ { "FetchThresh", 6, 5 },
+ { "CreditCnt", 4, 2 },
+ { "CreditCntPacking", 2, 2 },
+ { "NoEDRAM", 0, 1 },
+ { "SGE_CONM_CTRL", 0x1094, 0 },
+ { "EgrThresholdPacking", 16, 8 },
+ { "EgrThreshold", 8, 8 },
+ { "IngThreshold", 2, 6 },
+ { "SGE_TIMESTAMP_LO", 0x1098, 0 },
+ { "SGE_TIMESTAMP_HI", 0x109c, 0 },
+ { "Opcode", 28, 2 },
+ { "Value", 0, 28 },
+ { "SGE_INGRESS_RX_THRESHOLD", 0x10a0, 0 },
+ { "Threshold_0", 24, 6 },
+ { "Threshold_1", 16, 6 },
+ { "Threshold_2", 8, 6 },
+ { "Threshold_3", 0, 6 },
+ { "SGE_DBFIFO_STATUS", 0x10a4, 0 },
+ { "vfifo_cnt", 15, 17 },
+ { "coal_ctl_fifo_cnt", 8, 6 },
+ { "merge_fifo_cnt", 0, 6 },
+ { "SGE_DOORBELL_CONTROL", 0x10a8, 0 },
+ { "HintDepthCtl", 27, 5 },
+ { "NoCoalesce", 26, 1 },
+ { "HP_Weight", 24, 2 },
+ { "HP_Disable", 23, 1 },
+ { "ForceUserDBtoLP", 22, 1 },
+ { "ForceVFPF0DBtoLP", 21, 1 },
+ { "ForceVFPF1DBtoLP", 20, 1 },
+ { "ForceVFPF2DBtoLP", 19, 1 },
+ { "ForceVFPF3DBtoLP", 18, 1 },
+ { "ForceVFPF4DBtoLP", 17, 1 },
+ { "ForceVFPF5DBtoLP", 16, 1 },
+ { "ForceVFPF6DBtoLP", 15, 1 },
+ { "ForceVFPF7DBtoLP", 14, 1 },
+ { "Enable_Drop", 13, 1 },
+ { "Drop_Timeout", 7, 6 },
+ { "InvOnDBSync", 6, 1 },
+ { "InvOnGTSSync", 5, 1 },
+ { "db_dbg_en", 4, 1 },
+ { "gts_dbg_timer_reg", 1, 3 },
+ { "gts_dbg_en", 0, 1 },
+ { "SGE_ITP_CONTROL", 0x10b4, 0 },
+ { "TScale", 28, 4 },
+ { "Critical_Time", 10, 15 },
+ { "LL_Empty", 4, 6 },
+ { "LL_Read_Wait_Disable", 0, 1 },
+ { "SGE_TIMER_VALUE_0_AND_1", 0x10b8, 0 },
+ { "TimerValue0", 16, 16 },
+ { "TimerValue1", 0, 16 },
+ { "SGE_TIMER_VALUE_2_AND_3", 0x10bc, 0 },
+ { "TimerValue2", 16, 16 },
+ { "TimerValue3", 0, 16 },
+ { "SGE_TIMER_VALUE_4_AND_5", 0x10c0, 0 },
+ { "TimerValue4", 16, 16 },
+ { "TimerValue5", 0, 16 },
+ { "SGE_GK_CONTROL", 0x10c4, 0 },
+ { "en_flm_fifth", 29, 1 },
+ { "fl_prog_thresh", 20, 9 },
+ { "coal_all_thread", 19, 1 },
+ { "en_pshb", 18, 1 },
+ { "en_db_fifth", 17, 1 },
+ { "db_prog_thresh", 8, 9 },
+ { "100ns_timer", 0, 8 },
+ { "SGE_GK_CONTROL2", 0x10c8, 0 },
+ { "dbq_timer_tick", 16, 16 },
+ { "fl_merge_cnt_thresh", 8, 4 },
+ { "merge_cnt_thresh", 0, 6 },
+ { "SGE_DEBUG_INDEX", 0x10cc, 0 },
+ { "SGE_DEBUG_DATA_HIGH", 0x10d0, 0 },
+ { "SGE_DEBUG_DATA_LOW", 0x10d4, 0 },
+ { "SGE_REVISION", 0x10d8, 0 },
+ { "SGE_INT_CAUSE4", 0x10dc, 0 },
+ { "err_ishift_ur1", 31, 1 },
+ { "err_ishift_ur0", 30, 1 },
+ { "bar2_egress_len_or_addr_err", 29, 1 },
+ { "err_cpl_exceed_max_iqe_size1", 28, 1 },
+ { "err_cpl_exceed_max_iqe_size0", 27, 1 },
+ { "err_wr_len_too_large3", 26, 1 },
+ { "err_wr_len_too_large2", 25, 1 },
+ { "err_wr_len_too_large1", 24, 1 },
+ { "err_wr_len_too_large0", 23, 1 },
+ { "err_large_minfetch_with_txcoal3", 22, 1 },
+ { "err_large_minfetch_with_txcoal2", 21, 1 },
+ { "err_large_minfetch_with_txcoal1", 20, 1 },
+ { "err_large_minfetch_with_txcoal0", 19, 1 },
+ { "coal_with_hp_disable_err", 18, 1 },
+ { "bar2_egress_coal0_err", 17, 1 },
+ { "bar2_egress_size_err", 16, 1 },
+ { "flm_pc_rsp_err", 15, 1 },
+ { "err_th3_max_fetch", 14, 1 },
+ { "err_th2_max_fetch", 13, 1 },
+ { "err_th1_max_fetch", 12, 1 },
+ { "err_th0_max_fetch", 11, 1 },
+ { "err_rx_cpl_packet_size1", 10, 1 },
+ { "err_rx_cpl_packet_size0", 9, 1 },
+ { "err_bad_upfl_inc_credit3", 8, 1 },
+ { "err_bad_upfl_inc_credit2", 7, 1 },
+ { "err_bad_upfl_inc_credit1", 6, 1 },
+ { "err_bad_upfl_inc_credit0", 5, 1 },
+ { "err_physaddr_len0_idma1", 4, 1 },
+ { "err_physaddr_len0_idma0", 3, 1 },
+ { "err_flm_invalid_pkt_drop1", 2, 1 },
+ { "err_flm_invalid_pkt_drop0", 1, 1 },
+ { "err_unexpected_timer", 0, 1 },
+ { "SGE_INT_ENABLE4", 0x10e0, 0 },
+ { "err_ishift_ur1", 31, 1 },
+ { "err_ishift_ur0", 30, 1 },
+ { "bar2_egress_len_or_addr_err", 29, 1 },
+ { "err_cpl_exceed_max_iqe_size1", 28, 1 },
+ { "err_cpl_exceed_max_iqe_size0", 27, 1 },
+ { "err_wr_len_too_large3", 26, 1 },
+ { "err_wr_len_too_large2", 25, 1 },
+ { "err_wr_len_too_large1", 24, 1 },
+ { "err_wr_len_too_large0", 23, 1 },
+ { "err_large_minfetch_with_txcoal3", 22, 1 },
+ { "err_large_minfetch_with_txcoal2", 21, 1 },
+ { "err_large_minfetch_with_txcoal1", 20, 1 },
+ { "err_large_minfetch_with_txcoal0", 19, 1 },
+ { "coal_with_hp_disable_err", 18, 1 },
+ { "bar2_egress_coal0_err", 17, 1 },
+ { "bar2_egress_size_err", 16, 1 },
+ { "flm_pc_rsp_err", 15, 1 },
+ { "err_th3_max_fetch", 14, 1 },
+ { "err_th2_max_fetch", 13, 1 },
+ { "err_th1_max_fetch", 12, 1 },
+ { "err_th0_max_fetch", 11, 1 },
+ { "err_rx_cpl_packet_size1", 10, 1 },
+ { "err_rx_cpl_packet_size0", 9, 1 },
+ { "err_bad_upfl_inc_credit3", 8, 1 },
+ { "err_bad_upfl_inc_credit2", 7, 1 },
+ { "err_bad_upfl_inc_credit1", 6, 1 },
+ { "err_bad_upfl_inc_credit0", 5, 1 },
+ { "err_physaddr_len0_idma1", 4, 1 },
+ { "err_physaddr_len0_idma0", 3, 1 },
+ { "err_flm_invalid_pkt_drop1", 2, 1 },
+ { "err_flm_invalid_pkt_drop0", 1, 1 },
+ { "err_unexpected_timer", 0, 1 },
+ { "SGE_STAT_TOTAL", 0x10e4, 0 },
+ { "SGE_STAT_MATCH", 0x10e8, 0 },
+ { "SGE_STAT_CFG", 0x10ec, 0 },
+ { "StatSource", 9, 4 },
+ { "ITPOpMode", 8, 1 },
+ { "EgrCtxtOpMode", 6, 2 },
+ { "IngCtxtOpMode", 4, 2 },
+ { "StatMode", 0, 4 },
+ { "SGE_HINT_CFG", 0x10f0, 0 },
+ { "uPCutoffThreshLp", 12, 11 },
+ { "HintsAllowedNoHdr", 6, 6 },
+ { "HintsAllowedHdr", 0, 6 },
+ { "SGE_INGRESS_QUEUES_PER_PAGE_PF", 0x10f4, 0 },
+ { "QueuesPerPagePF7", 28, 4 },
+ { "QueuesPerPagePF6", 24, 4 },
+ { "QueuesPerPagePF5", 20, 4 },
+ { "QueuesPerPagePF4", 16, 4 },
+ { "QueuesPerPagePF3", 12, 4 },
+ { "QueuesPerPagePF2", 8, 4 },
+ { "QueuesPerPagePF1", 4, 4 },
+ { "QueuesPerPagePF0", 0, 4 },
+ { "SGE_INGRESS_QUEUES_PER_PAGE_VF", 0x10f8, 0 },
+ { "QueuesPerPageVFPF7", 28, 4 },
+ { "QueuesPerPageVFPF6", 24, 4 },
+ { "QueuesPerPageVFPF5", 20, 4 },
+ { "QueuesPerPageVFPF4", 16, 4 },
+ { "QueuesPerPageVFPF3", 12, 4 },
+ { "QueuesPerPageVFPF2", 8, 4 },
+ { "QueuesPerPageVFPF1", 4, 4 },
+ { "QueuesPerPageVFPF0", 0, 4 },
+ { "SGE_ERROR_STATS", 0x1100, 0 },
+ { "Cause_Register", 24, 3 },
+ { "Cause_Bit", 19, 5 },
+ { "Uncaptured_Error", 18, 1 },
+ { "Error_QID_Valid", 17, 1 },
+ { "Error_QID", 0, 17 },
+ { "SGE_IDMA0_DROP_CNT", 0x1104, 0 },
+ { "SGE_IDMA1_DROP_CNT", 0x1108, 0 },
+ { "SGE_INT_CAUSE5", 0x110c, 0 },
+ { "err_T_RxCRC", 31, 1 },
+ { "perr_MC_RspData", 30, 1 },
+ { "perr_PC_RspData", 29, 1 },
+ { "perr_PD_RdRspData", 28, 1 },
+ { "perr_U_RxData", 27, 1 },
+ { "perr_UD_RxData", 26, 1 },
+ { "perr_uP_Data", 25, 1 },
+ { "perr_CIM2SGE_RxData", 24, 1 },
+ { "perr_hint_delay_fifo1", 23, 1 },
+ { "perr_hint_delay_fifo0", 22, 1 },
+ { "perr_imsg_pd_fifo", 21, 1 },
+ { "perr_ulptx_fifo1", 20, 1 },
+ { "perr_ulptx_fifo0", 19, 1 },
+ { "perr_idma2imsg_fifo1", 18, 1 },
+ { "perr_idma2imsg_fifo0", 17, 1 },
+ { "perr_pointer_data_fifo0", 16, 1 },
+ { "perr_pointer_data_fifo1", 15, 1 },
+ { "perr_pointer_hdr_fifo0", 14, 1 },
+ { "perr_pointer_hdr_fifo1", 13, 1 },
+ { "perr_payload_fifo0", 12, 1 },
+ { "perr_payload_fifo1", 11, 1 },
+ { "perr_edma_input_fifo3", 10, 1 },
+ { "perr_edma_input_fifo2", 9, 1 },
+ { "perr_edma_input_fifo1", 8, 1 },
+ { "perr_edma_input_fifo0", 7, 1 },
+ { "perr_mgt_bar2_fifo", 6, 1 },
+ { "perr_headersplit_fifo1", 5, 1 },
+ { "perr_headersplit_fifo0", 4, 1 },
+ { "perr_cim_fifo1", 3, 1 },
+ { "perr_cim_fifo0", 2, 1 },
+ { "perr_idma_switch_output_fifo1", 1, 1 },
+ { "perr_idma_switch_output_fifo0", 0, 1 },
+ { "SGE_INT_ENABLE5", 0x1110, 0 },
+ { "err_T_RxCRC", 31, 1 },
+ { "perr_MC_RspData", 30, 1 },
+ { "perr_PC_RspData", 29, 1 },
+ { "perr_PD_RdRspData", 28, 1 },
+ { "perr_U_RxData", 27, 1 },
+ { "perr_UD_RxData", 26, 1 },
+ { "perr_uP_Data", 25, 1 },
+ { "perr_CIM2SGE_RxData", 24, 1 },
+ { "perr_hint_delay_fifo1", 23, 1 },
+ { "perr_hint_delay_fifo0", 22, 1 },
+ { "perr_imsg_pd_fifo", 21, 1 },
+ { "perr_ulptx_fifo1", 20, 1 },
+ { "perr_ulptx_fifo0", 19, 1 },
+ { "perr_idma2imsg_fifo1", 18, 1 },
+ { "perr_idma2imsg_fifo0", 17, 1 },
+ { "perr_pointer_data_fifo0", 16, 1 },
+ { "perr_pointer_data_fifo1", 15, 1 },
+ { "perr_pointer_hdr_fifo0", 14, 1 },
+ { "perr_pointer_hdr_fifo1", 13, 1 },
+ { "perr_payload_fifo0", 12, 1 },
+ { "perr_payload_fifo1", 11, 1 },
+ { "perr_edma_input_fifo3", 10, 1 },
+ { "perr_edma_input_fifo2", 9, 1 },
+ { "perr_edma_input_fifo1", 8, 1 },
+ { "perr_edma_input_fifo0", 7, 1 },
+ { "perr_mgt_bar2_fifo", 6, 1 },
+ { "perr_headersplit_fifo1", 5, 1 },
+ { "perr_headersplit_fifo0", 4, 1 },
+ { "perr_cim_fifo1", 3, 1 },
+ { "perr_cim_fifo0", 2, 1 },
+ { "perr_idma_switch_output_fifo1", 1, 1 },
+ { "perr_idma_switch_output_fifo0", 0, 1 },
+ { "SGE_PERR_ENABLE5", 0x1114, 0 },
+ { "err_T_RxCRC", 31, 1 },
+ { "perr_MC_RspData", 30, 1 },
+ { "perr_PC_RspData", 29, 1 },
+ { "perr_PD_RdRspData", 28, 1 },
+ { "perr_U_RxData", 27, 1 },
+ { "perr_UD_RxData", 26, 1 },
+ { "perr_uP_Data", 25, 1 },
+ { "perr_CIM2SGE_RxData", 24, 1 },
+ { "perr_hint_delay_fifo1", 23, 1 },
+ { "perr_hint_delay_fifo0", 22, 1 },
+ { "perr_imsg_pd_fifo", 21, 1 },
+ { "perr_ulptx_fifo1", 20, 1 },
+ { "perr_ulptx_fifo0", 19, 1 },
+ { "perr_idma2imsg_fifo1", 18, 1 },
+ { "perr_idma2imsg_fifo0", 17, 1 },
+ { "perr_pointer_data_fifo0", 16, 1 },
+ { "perr_pointer_data_fifo1", 15, 1 },
+ { "perr_pointer_hdr_fifo0", 14, 1 },
+ { "perr_pointer_hdr_fifo1", 13, 1 },
+ { "perr_payload_fifo0", 12, 1 },
+ { "perr_payload_fifo1", 11, 1 },
+ { "perr_edma_input_fifo3", 10, 1 },
+ { "perr_edma_input_fifo2", 9, 1 },
+ { "perr_edma_input_fifo1", 8, 1 },
+ { "perr_edma_input_fifo0", 7, 1 },
+ { "perr_mgt_bar2_fifo", 6, 1 },
+ { "perr_headersplit_fifo1", 5, 1 },
+ { "perr_headersplit_fifo0", 4, 1 },
+ { "perr_cim_fifo1", 3, 1 },
+ { "perr_cim_fifo0", 2, 1 },
+ { "perr_idma_switch_output_fifo1", 1, 1 },
+ { "perr_idma_switch_output_fifo0", 0, 1 },
+ { "SGE_FETCH_BURST_MAX_0_AND_1", 0x111c, 0 },
+ { "FetchBurstMax0", 16, 10 },
+ { "FetchBurstMax1", 0, 10 },
+ { "SGE_FETCH_BURST_MAX_2_AND_3", 0x1120, 0 },
+ { "FetchBurstMax2", 16, 10 },
+ { "FetchBurstMax3", 0, 10 },
+ { "SGE_CONTROL2", 0x1124, 0 },
+ { "uPFLCutoffDis", 21, 1 },
+ { "RxCplSizeAutocorrect", 20, 1 },
+ { "IdmaArbRoundRobin", 19, 1 },
+ { "IngPackBoundary", 16, 3 },
+ { "CGEN_Egress_Context", 15, 1 },
+ { "CGEN_Ingress_Context", 14, 1 },
+ { "CGEN_IDMA", 13, 1 },
+ { "CGEN_DBP", 12, 1 },
+ { "CGEN_EDMA", 11, 1 },
+ { "VFIFO_Enable", 10, 1 },
+ { "FLM_Reschedule_Mode", 9, 1 },
+ { "HintDepthCtlFL", 4, 5 },
+ { "Force_Ordering", 3, 1 },
+ { "TX_Coalesce_Size", 2, 1 },
+ { "Coal_Strict_CIM_Pri", 1, 1 },
+ { "TX_Coalesce_Pri", 0, 1 },
+ { "SGE_INT_CAUSE6", 0x1128, 0 },
+ { "err_db_sync", 21, 1 },
+ { "err_gts_sync", 20, 1 },
+ { "fatal_large_coal", 19, 1 },
+ { "pl_bar2_frm_err", 18, 1 },
+ { "silent_drop_tx_coal", 17, 1 },
+ { "err_inv_ctxt4", 16, 1 },
+ { "err_bad_db_pidx4", 15, 1 },
+ { "err_bad_upfl_inc_credit4", 14, 1 },
+ { "fatal_tag_mismatch", 13, 1 },
+ { "fatal_enq_ctl_rdy", 12, 1 },
+ { "err_pc_rsp_len3", 11, 1 },
+ { "err_pc_rsp_len2", 10, 1 },
+ { "err_pc_rsp_len1", 9, 1 },
+ { "err_pc_rsp_len0", 8, 1 },
+ { "fatal_enq2ll_vld", 7, 1 },
+ { "fatal_ll_empty", 6, 1 },
+ { "fatal_off_wdenq", 5, 1 },
+ { "fatal_deq_drdy", 3, 2 },
+ { "fatal_outp_drdy", 1, 2 },
+ { "fatal_deq", 0, 1 },
+ { "SGE_INT_ENABLE6", 0x112c, 0 },
+ { "err_db_sync", 21, 1 },
+ { "err_gts_sync", 20, 1 },
+ { "fatal_large_coal", 19, 1 },
+ { "pl_bar2_frm_err", 18, 1 },
+ { "silent_drop_tx_coal", 17, 1 },
+ { "err_inv_ctxt4", 16, 1 },
+ { "err_bad_db_pidx4", 15, 1 },
+ { "err_bad_upfl_inc_credit4", 14, 1 },
+ { "fatal_tag_mismatch", 13, 1 },
+ { "fatal_enq_ctl_rdy", 12, 1 },
+ { "err_pc_rsp_len3", 11, 1 },
+ { "err_pc_rsp_len2", 10, 1 },
+ { "err_pc_rsp_len1", 9, 1 },
+ { "err_pc_rsp_len0", 8, 1 },
+ { "fatal_enq2ll_vld", 7, 1 },
+ { "fatal_ll_empty", 6, 1 },
+ { "fatal_off_wdenq", 5, 1 },
+ { "fatal_deq_drdy", 3, 2 },
+ { "fatal_outp_drdy", 1, 2 },
+ { "fatal_deq", 0, 1 },
+ { "SGE_DBVFIFO_BADDR", 0x1138, 0 },
+ { "BaseAddr", 3, 29 },
+ { "SGE_DBVFIFO_SIZE", 0x113c, 0 },
+ { "SGE_CHANGESET", 0x1144, 0 },
+ { "SGE_PC_RSP_ERROR", 0x1148, 0 },
+ { "SGE_TBUF_CONTROL", 0x114c, 0 },
+ { "DbpTbufRsv1", 9, 9 },
+ { "DbpTbufRsv0", 0, 9 },
+ { "SGE_PC0_REQ_BIST_CMD", 0x1180, 0 },
+ { "SGE_PC0_REQ_BIST_ERROR_CNT", 0x1184, 0 },
+ { "SGE_PC1_REQ_BIST_CMD", 0x1190, 0 },
+ { "SGE_PC1_REQ_BIST_ERROR_CNT", 0x1194, 0 },
+ { "SGE_PC0_RSP_BIST_CMD", 0x11a0, 0 },
+ { "SGE_PC0_RSP_BIST_ERROR_CNT", 0x11a4, 0 },
+ { "SGE_PC1_RSP_BIST_CMD", 0x11b0, 0 },
+ { "SGE_PC1_RSP_BIST_ERROR_CNT", 0x11b4, 0 },
+ { "SGE_DBQ_TIMER_THRESH0", 0x11b8, 0 },
+ { "TxTimeTh3", 24, 6 },
+ { "TxTimeTh2", 16, 6 },
+ { "TxTimeTh1", 8, 6 },
+ { "TxTimeTh0", 0, 6 },
+ { "SGE_DBQ_TIMER_THRESH1", 0x11bc, 0 },
+ { "TxTimeTh7", 24, 6 },
+ { "TxTimeTh6", 16, 6 },
+ { "TxTimeTh5", 8, 6 },
+ { "TxTimeTh4", 0, 6 },
+ { "SGE_DBQ_TIMER_CONFIG", 0x11c0, 0 },
+ { "SGE_DBQ_TIMER_DBG", 0x11c4, 0 },
+ { "dbq_timer_cmd", 31, 1 },
+ { "dbq_timer_index", 24, 6 },
+ { "dbq_timer_qcnt", 0, 17 },
+ { "SGE_CTXT_CMD", 0x11fc, 0 },
+ { "Busy", 31, 1 },
+ { "Opcode", 28, 2 },
+ { "CtxtType", 24, 2 },
+ { "QID", 0, 17 },
+ { "SGE_CTXT_DATA0", 0x1200, 0 },
+ { "SGE_CTXT_DATA1", 0x1204, 0 },
+ { "SGE_CTXT_DATA2", 0x1208, 0 },
+ { "SGE_CTXT_DATA3", 0x120c, 0 },
+ { "SGE_CTXT_DATA4", 0x1210, 0 },
+ { "SGE_CTXT_DATA5", 0x1214, 0 },
+ { "SGE_CTXT_DATA6", 0x1218, 0 },
+ { "SGE_CTXT_DATA7", 0x121c, 0 },
+ { "SGE_CTXT_MASK0", 0x1220, 0 },
+ { "SGE_CTXT_MASK1", 0x1224, 0 },
+ { "SGE_CTXT_MASK2", 0x1228, 0 },
+ { "SGE_CTXT_MASK3", 0x122c, 0 },
+ { "SGE_CTXT_MASK4", 0x1230, 0 },
+ { "SGE_CTXT_MASK5", 0x1234, 0 },
+ { "SGE_CTXT_MASK6", 0x1238, 0 },
+ { "SGE_CTXT_MASK7", 0x123c, 0 },
+ { "SGE_QBASE_MAP0", 0x1240, 0 },
+ { "Egress0_Size", 24, 5 },
+ { "Egress1_Size", 16, 5 },
+ { "Ingress0_Size", 8, 5 },
+ { "Ingress1_Size", 0, 5 },
+ { "SGE_QBASE_MAP1", 0x1244, 0 },
+ { "SGE_QBASE_MAP2", 0x1248, 0 },
+ { "SGE_QBASE_MAP3", 0x124c, 0 },
+ { "Ingress1_Base", 16, 16 },
+ { "Ingress0_Base", 0, 16 },
+ { "SGE_QBASE_INDEX", 0x1250, 0 },
+ { "SGE_CONM_CTRL2", 0x1254, 0 },
+ { "FlmThreshPack", 8, 7 },
+ { "FlmThresh", 0, 7 },
+ { "SGE_DEBUG_CONM", 0x1258, 0 },
+ { "mps_ch_cng", 16, 16 },
+ { "tp_ch_cng", 14, 2 },
+ { "st_cong", 12, 2 },
+ { "last_xoff", 10, 1 },
+ { "last_qid", 0, 10 },
+ { "SGE_DBG_QUEUE_STAT0_CTRL", 0x125c, 0 },
+ { "imsg_gts_sel", 18, 1 },
+ { "mgt_sel", 17, 1 },
+ { "db_gts_qid", 0, 17 },
+ { "SGE_DBG_QUEUE_STAT1_CTRL", 0x1260, 0 },
+ { "imsg_gts_sel", 18, 1 },
+ { "mgt_sel", 17, 1 },
+ { "db_gts_qid", 0, 17 },
+ { "SGE_DBG_QUEUE_STAT0", 0x1264, 0 },
+ { "SGE_DBG_QUEUE_STAT1", 0x1268, 0 },
+ { "SGE_DBG_BAR2_PKT_CNT", 0x126c, 0 },
+ { "SGE_DBG_DB_PKT_CNT", 0x1270, 0 },
+ { "SGE_DBG_GTS_PKT_CNT", 0x1274, 0 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_0", 0x1280, 0 },
+ { "debug_bar2_sop_cnt", 28, 4 },
+ { "debug_bar2_eop_cnt", 24, 4 },
+ { "debug_uP_SOP_cnt", 20, 4 },
+ { "debug_uP_EOP_cnt", 16, 4 },
+ { "debug_CIM_SOP1_cnt", 12, 4 },
+ { "debug_CIM_EOP1_cnt", 8, 4 },
+ { "debug_CIM_SOP0_cnt", 4, 4 },
+ { "debug_CIM_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_1", 0x1284, 0 },
+ { "debug_T_Rx_SOP1_cnt", 28, 4 },
+ { "debug_T_Rx_EOP1_cnt", 24, 4 },
+ { "debug_T_Rx_SOP0_cnt", 20, 4 },
+ { "debug_T_Rx_EOP0_cnt", 16, 4 },
+ { "debug_U_Rx_SOP1_cnt", 12, 4 },
+ { "debug_U_Rx_EOP1_cnt", 8, 4 },
+ { "debug_U_Rx_SOP0_cnt", 4, 4 },
+ { "debug_U_Rx_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_2", 0x1288, 0 },
+ { "dbg_tbuf_used1", 9, 9 },
+ { "dbg_tbuf_used0", 0, 9 },
+ { "SGE_DEBUG1_DBP_THREAD", 0x128c, 0 },
+ { "wr_deq_cnt", 12, 4 },
+ { "wr_enq_cnt", 8, 4 },
+ { "fl_deq_cnt", 4, 4 },
+ { "fl_enq_cnt", 0, 4 },
+ { "SGE_DEBUG1_DBP_THREAD", 0x1290, 0 },
+ { "wr_deq_cnt", 12, 4 },
+ { "wr_enq_cnt", 8, 4 },
+ { "fl_deq_cnt", 4, 4 },
+ { "fl_enq_cnt", 0, 4 },
+ { "SGE_DEBUG1_DBP_THREAD", 0x1294, 0 },
+ { "wr_deq_cnt", 12, 4 },
+ { "wr_enq_cnt", 8, 4 },
+ { "fl_deq_cnt", 4, 4 },
+ { "fl_enq_cnt", 0, 4 },
+ { "SGE_DEBUG1_DBP_THREAD", 0x1298, 0 },
+ { "wr_deq_cnt", 12, 4 },
+ { "wr_enq_cnt", 8, 4 },
+ { "fl_deq_cnt", 4, 4 },
+ { "fl_enq_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_7", 0x129c, 0 },
+ { "debug_PC_Rsp_SOP_cnt", 28, 4 },
+ { "debug_PC_Rsp_EOP_cnt", 24, 4 },
+ { "debug_PC_Req_SOP_cnt", 20, 4 },
+ { "debug_PC_Req_EOP_cnt", 16, 4 },
+ { "debug_PD_WrReq_SOP1_cnt", 12, 4 },
+ { "debug_PD_WrReq_EOP1_cnt", 8, 4 },
+ { "debug_PD_WrReq_SOP0_cnt", 4, 4 },
+ { "debug_PD_WrReq_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_8", 0x12a0, 0 },
+ { "debug_PL_BAR2_ReqVld", 31, 1 },
+ { "debug_PL_BAR2_ReqFull", 30, 1 },
+ { "GlobalEnable_Off", 29, 1 },
+ { "debug_CIM2SGE_RxAFull_d", 27, 2 },
+ { "debug_CPLSW_CIM_TxAFull_d", 25, 2 },
+ { "debug_uP_Full", 24, 1 },
+ { "debug_M_rd_req_outstanding_PC", 23, 1 },
+ { "debug_M_rd_req_outstanding_VFIFO", 22, 1 },
+ { "debug_M_rd_req_outstanding_IMSG", 21, 1 },
+ { "debug_M_rd_req_outstanding_CMARB", 20, 1 },
+ { "debug_M_rd_req_outstanding_FLM", 19, 1 },
+ { "debug_M_ReqVld", 18, 1 },
+ { "debug_M_ReqRdy", 17, 1 },
+ { "debug_M_RspVld", 16, 1 },
+ { "debug_PD_WrReq_Int3_cnt", 12, 4 },
+ { "debug_PD_WrReq_Int2_cnt", 8, 4 },
+ { "debug_PD_WrReq_Int1_cnt", 4, 4 },
+ { "debug_PD_WrReq_Int0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_9", 0x12a4, 0 },
+ { "debug_CPLSW_TP_Rx_SOP1_cnt", 28, 4 },
+ { "debug_CPLSW_TP_Rx_EOP1_cnt", 24, 4 },
+ { "debug_CPLSW_TP_Rx_SOP0_cnt", 20, 4 },
+ { "debug_CPLSW_TP_Rx_EOP0_cnt", 16, 4 },
+ { "debug_CPLSW_CIM_SOP0_cnt", 4, 4 },
+ { "debug_CPLSW_CIM_EOP0_cnt", 0, 4 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_10", 0x12a8, 0 },
+ { "debug_idma1_s_cpl_flit_remaining", 28, 4 },
+ { "debug_idma1_idma2imsg_cmp_out_srdy", 27, 1 },
+ { "debug_idma1_idma2imsg_cmp_out_rss", 26, 1 },
+ { "debug_idma1_idma2imsg_cmp_out_nocpl", 25, 1 },
+ { "debug_idma1_IDMA2IMSG_Full", 24, 1 },
+ { "debug_idma1_IDMA2IMSG_EOP", 23, 1 },
+ { "debug_idma1_idma2imsg_fifo_in_drdy", 22, 1 },
+ { "debug_idma1_idma2imsg_cmp_in_drdy", 21, 1 },
+ { "debug_idma0_s_cpl_flit_remaining", 17, 4 },
+ { "debug_idma0_idma2imsg_cmp_out_srdy", 16, 1 },
+ { "debug_idma0_idma2imsg_cmp_out_rss", 15, 1 },
+ { "debug_idma0_idma2imsg_cmp_out_nocpl", 14, 1 },
+ { "debug_idma0_IDMA2IMSG_Full", 13, 1 },
+ { "debug_idma0_IDMA2IMSG_EOP", 12, 1 },
+ { "debug_idma0_idma2imsg_cmp_in_drdy", 11, 1 },
+ { "debug_idma0_idma2imsg_fifo_in_drdy", 10, 1 },
+ { "debug_T_RxAFull_d", 8, 2 },
+ { "debug_PD_WrReqAFull_d", 6, 2 },
+ { "debug_PC_RspAFull_d", 5, 1 },
+ { "debug_PC_ReqAFull_d", 4, 1 },
+ { "debug_U_RxAFull_d", 2, 2 },
+ { "debug_CIM_AFull_d", 0, 1 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_11", 0x12ac, 0 },
+ { "debug_flm_idma1_cache_data_active", 24, 1 },
+ { "debug_flm_idma1_cache_hdr_active", 23, 1 },
+ { "debug_flm_idma1_ctxt_data_active", 22, 1 },
+ { "debug_flm_idma1_ctxt_hdr_active", 21, 1 },
+ { "debug_st_flm_idma1_cache", 19, 2 },
+ { "debug_st_flm_idma1_ctxt", 16, 3 },
+ { "debug_flm_idma0_cache_data_active", 8, 1 },
+ { "debug_flm_idma0_cache_hdr_active", 7, 1 },
+ { "debug_flm_idma0_ctxt_data_active", 6, 1 },
+ { "debug_flm_idma0_ctxt_hdr_active", 5, 1 },
+ { "debug_st_flm_idma0_cache", 3, 2 },
+ { "debug_st_flm_idma0_ctxt", 0, 3 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_12", 0x12b0, 0 },
+ { "debug_CPLSW_SOP1_cnt", 28, 4 },
+ { "debug_CPLSW_EOP1_cnt", 24, 4 },
+ { "debug_CPLSW_SOP0_cnt", 20, 4 },
+ { "debug_CPLSW_EOP0_cnt", 16, 4 },
+ { "debug_idma1_ishift_tx_size", 8, 7 },
+ { "debug_idma0_ishift_tx_size", 0, 7 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_13", 0x12b4, 0 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_14", 0x12b8, 0 },
+ { "SGE_DEBUG_DATA_HIGH_INDEX_15", 0x12bc, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_0", 0x12c0, 0 },
+ { "debug_st_idma1_flm_req", 29, 3 },
+ { "debug_st_idma0_flm_req", 26, 3 },
+ { "debug_st_imsg_ctxt", 23, 3 },
+ { "debug_st_imsg", 18, 5 },
+ { "debug_st_idma1_ialn", 16, 2 },
+ { "debug_st_idma1_idma2imsg", 15, 1 },
+ { "debug_st_idma1_idma_sm", 9, 6 },
+ { "debug_st_idma0_ialn", 7, 2 },
+ { "debug_st_idma0_idma2imsg", 6, 1 },
+ { "debug_st_idma0_idma_sm", 0, 6 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_1", 0x12c4, 0 },
+ { "debug_itp_empty", 12, 6 },
+ { "debug_itp_expired", 6, 6 },
+ { "debug_itp_pause", 5, 1 },
+ { "debug_itp_del_done", 4, 1 },
+ { "debug_itp_add_done", 3, 1 },
+ { "debug_itp_evr_state", 0, 3 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_2", 0x12c8, 0 },
+ { "debug_st_dbp_upcp_main", 14, 3 },
+ { "debug_st_dbp_dbfifo_main", 13, 1 },
+ { "debug_st_dbp_ctxt", 10, 3 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_3", 0x12cc, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_4", 0x12d0, 0 },
+ { "debug_st_flm_dbptr", 30, 2 },
+ { "debug_flm_cache_locked_count", 23, 7 },
+ { "debug_flm_cache_agent", 20, 3 },
+ { "debug_st_flm_cache", 16, 4 },
+ { "debug_flm_dbptr_cidx_stall", 12, 1 },
+ { "debug_flm_dbptr_qid", 0, 12 },
+ { "SGE_DEBUG0_DBP_THREAD", 0x12d4, 0 },
+ { "thread_st_main", 25, 6 },
+ { "thread_st_cimfl", 21, 4 },
+ { "thread_cmdop", 17, 4 },
+ { "thread_qid", 0, 17 },
+ { "SGE_DEBUG0_DBP_THREAD", 0x12d8, 0 },
+ { "thread_st_main", 25, 6 },
+ { "thread_st_cimfl", 21, 4 },
+ { "thread_cmdop", 17, 4 },
+ { "thread_qid", 0, 17 },
+ { "SGE_DEBUG0_DBP_THREAD", 0x12dc, 0 },
+ { "thread_st_main", 25, 6 },
+ { "thread_st_cimfl", 21, 4 },
+ { "thread_cmdop", 17, 4 },
+ { "thread_qid", 0, 17 },
+ { "SGE_DEBUG0_DBP_THREAD", 0x12e0, 0 },
+ { "thread_st_main", 25, 6 },
+ { "thread_st_cimfl", 21, 4 },
+ { "thread_cmdop", 17, 4 },
+ { "thread_qid", 0, 17 },
+ { "SGE_DEBUG0_DBP_THREAD", 0x12e4, 0 },
+ { "thread_st_main", 25, 6 },
+ { "thread_st_cimfl", 21, 4 },
+ { "thread_cmdop", 17, 4 },
+ { "thread_qid", 0, 17 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_10", 0x12e8, 0 },
+ { "debug_imsg_cpl", 16, 8 },
+ { "debug_imsg_qid", 0, 16 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_11", 0x12ec, 0 },
+ { "debug_idma1_qid", 16, 16 },
+ { "debug_idma0_qid", 0, 16 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_12", 0x12f0, 0 },
+ { "debug_idma1_flm_req_qid", 16, 16 },
+ { "debug_idma0_flm_req_qid", 0, 16 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_13", 0x12f4, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_14", 0x12f8, 0 },
+ { "SGE_DEBUG_DATA_LOW_INDEX_15", 0x12fc, 0 },
+ { "SGE_WC_EGRS_BAR2_OFF_PF", 0x1300, 0 },
+ { "PfIQsPerPage", 28, 4 },
+ { "PfEQsPerPage", 24, 4 },
+ { "PfWCQsPerPage", 20, 4 },
+ { "PfWCOffEn", 19, 1 },
+ { "PfMaxWCSize", 17, 2 },
+ { "PfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_PF", 0x1304, 0 },
+ { "PfIQsPerPage", 28, 4 },
+ { "PfEQsPerPage", 24, 4 },
+ { "PfWCQsPerPage", 20, 4 },
+ { "PfWCOffEn", 19, 1 },
+ { "PfMaxWCSize", 17, 2 },
+ { "PfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_PF", 0x1308, 0 },
+ { "PfIQsPerPage", 28, 4 },
+ { "PfEQsPerPage", 24, 4 },
+ { "PfWCQsPerPage", 20, 4 },
+ { "PfWCOffEn", 19, 1 },
+ { "PfMaxWCSize", 17, 2 },
+ { "PfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_PF", 0x130c, 0 },
+ { "PfIQsPerPage", 28, 4 },
+ { "PfEQsPerPage", 24, 4 },
+ { "PfWCQsPerPage", 20, 4 },
+ { "PfWCOffEn", 19, 1 },
+ { "PfMaxWCSize", 17, 2 },
+ { "PfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_PF", 0x1310, 0 },
+ { "PfIQsPerPage", 28, 4 },
+ { "PfEQsPerPage", 24, 4 },
+ { "PfWCQsPerPage", 20, 4 },
+ { "PfWCOffEn", 19, 1 },
+ { "PfMaxWCSize", 17, 2 },
+ { "PfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_PF", 0x1314, 0 },
+ { "PfIQsPerPage", 28, 4 },
+ { "PfEQsPerPage", 24, 4 },
+ { "PfWCQsPerPage", 20, 4 },
+ { "PfWCOffEn", 19, 1 },
+ { "PfMaxWCSize", 17, 2 },
+ { "PfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_PF", 0x1318, 0 },
+ { "PfIQsPerPage", 28, 4 },
+ { "PfEQsPerPage", 24, 4 },
+ { "PfWCQsPerPage", 20, 4 },
+ { "PfWCOffEn", 19, 1 },
+ { "PfMaxWCSize", 17, 2 },
+ { "PfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_PF", 0x131c, 0 },
+ { "PfIQsPerPage", 28, 4 },
+ { "PfEQsPerPage", 24, 4 },
+ { "PfWCQsPerPage", 20, 4 },
+ { "PfWCOffEn", 19, 1 },
+ { "PfMaxWCSize", 17, 2 },
+ { "PfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_VF", 0x1320, 0 },
+ { "VfIQsPerPage", 28, 4 },
+ { "VfEQsPerPage", 24, 4 },
+ { "VfWCQsPerPage", 20, 4 },
+ { "VfWCOffEn", 19, 1 },
+ { "VfMaxWCSize", 17, 2 },
+ { "VfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_VF", 0x1324, 0 },
+ { "VfIQsPerPage", 28, 4 },
+ { "VfEQsPerPage", 24, 4 },
+ { "VfWCQsPerPage", 20, 4 },
+ { "VfWCOffEn", 19, 1 },
+ { "VfMaxWCSize", 17, 2 },
+ { "VfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_VF", 0x1328, 0 },
+ { "VfIQsPerPage", 28, 4 },
+ { "VfEQsPerPage", 24, 4 },
+ { "VfWCQsPerPage", 20, 4 },
+ { "VfWCOffEn", 19, 1 },
+ { "VfMaxWCSize", 17, 2 },
+ { "VfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_VF", 0x132c, 0 },
+ { "VfIQsPerPage", 28, 4 },
+ { "VfEQsPerPage", 24, 4 },
+ { "VfWCQsPerPage", 20, 4 },
+ { "VfWCOffEn", 19, 1 },
+ { "VfMaxWCSize", 17, 2 },
+ { "VfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_VF", 0x1330, 0 },
+ { "VfIQsPerPage", 28, 4 },
+ { "VfEQsPerPage", 24, 4 },
+ { "VfWCQsPerPage", 20, 4 },
+ { "VfWCOffEn", 19, 1 },
+ { "VfMaxWCSize", 17, 2 },
+ { "VfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_VF", 0x1334, 0 },
+ { "VfIQsPerPage", 28, 4 },
+ { "VfEQsPerPage", 24, 4 },
+ { "VfWCQsPerPage", 20, 4 },
+ { "VfWCOffEn", 19, 1 },
+ { "VfMaxWCSize", 17, 2 },
+ { "VfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_VF", 0x1338, 0 },
+ { "VfIQsPerPage", 28, 4 },
+ { "VfEQsPerPage", 24, 4 },
+ { "VfWCQsPerPage", 20, 4 },
+ { "VfWCOffEn", 19, 1 },
+ { "VfMaxWCSize", 17, 2 },
+ { "VfWCOffset", 0, 17 },
+ { "SGE_WC_EGRS_BAR2_OFF_VF", 0x133c, 0 },
+ { "VfIQsPerPage", 28, 4 },
+ { "VfEQsPerPage", 24, 4 },
+ { "VfWCQsPerPage", 20, 4 },
+ { "VfWCOffEn", 19, 1 },
+ { "VfMaxWCSize", 17, 2 },
+ { "VfWCOffset", 0, 17 },
+ { "SGE_LA_RDPTR_0", 0x1800, 0 },
+ { "SGE_LA_RDDATA_0", 0x1804, 0 },
+ { "SGE_LA_WRPTR_0", 0x1808, 0 },
+ { "SGE_LA_RESERVED_0", 0x180c, 0 },
+ { "SGE_LA_RDPTR_1", 0x1810, 0 },
+ { "SGE_LA_RDDATA_1", 0x1814, 0 },
+ { "SGE_LA_WRPTR_1", 0x1818, 0 },
+ { "SGE_LA_RESERVED_1", 0x181c, 0 },
+ { "SGE_LA_RDPTR_2", 0x1820, 0 },
+ { "SGE_LA_RDDATA_2", 0x1824, 0 },
+ { "SGE_LA_WRPTR_2", 0x1828, 0 },
+ { "SGE_LA_RESERVED_2", 0x182c, 0 },
+ { "SGE_LA_RDPTR_3", 0x1830, 0 },
+ { "SGE_LA_RDDATA_3", 0x1834, 0 },
+ { "SGE_LA_WRPTR_3", 0x1838, 0 },
+ { "SGE_LA_RESERVED_3", 0x183c, 0 },
+ { "SGE_LA_RDPTR_4", 0x1840, 0 },
+ { "SGE_LA_RDDATA_4", 0x1844, 0 },
+ { "SGE_LA_WRPTR_4", 0x1848, 0 },
+ { "SGE_LA_RESERVED_4", 0x184c, 0 },
+ { "SGE_LA_RDPTR_5", 0x1850, 0 },
+ { "SGE_LA_RDDATA_5", 0x1854, 0 },
+ { "SGE_LA_WRPTR_5", 0x1858, 0 },
+ { "SGE_LA_RESERVED_5", 0x185c, 0 },
+ { "SGE_LA_RDPTR_6", 0x1860, 0 },
+ { "SGE_LA_RDDATA_6", 0x1864, 0 },
+ { "SGE_LA_WRPTR_6", 0x1868, 0 },
+ { "SGE_LA_RESERVED_6", 0x186c, 0 },
+ { "SGE_LA_RDPTR_7", 0x1870, 0 },
+ { "SGE_LA_RDDATA_7", 0x1874, 0 },
+ { "SGE_LA_WRPTR_7", 0x1878, 0 },
+ { "SGE_LA_RESERVED_7", 0x187c, 0 },
+ { "SGE_LA_RDPTR_8", 0x1880, 0 },
+ { "SGE_LA_RDDATA_8", 0x1884, 0 },
+ { "SGE_LA_WRPTR_8", 0x1888, 0 },
+ { "SGE_LA_RESERVED_8", 0x188c, 0 },
+ { "SGE_LA_RDPTR_9", 0x1890, 0 },
+ { "SGE_LA_RDDATA_9", 0x1894, 0 },
+ { "SGE_LA_WRPTR_9", 0x1898, 0 },
+ { "SGE_LA_RESERVED_9", 0x189c, 0 },
+ { "SGE_LA_RDPTR_10", 0x18a0, 0 },
+ { "SGE_LA_RDDATA_10", 0x18a4, 0 },
+ { "SGE_LA_WRPTR_10", 0x18a8, 0 },
+ { "SGE_LA_RESERVED_10", 0x18ac, 0 },
+ { "SGE_LA_RDPTR_11", 0x18b0, 0 },
+ { "SGE_LA_RDDATA_11", 0x18b4, 0 },
+ { "SGE_LA_WRPTR_11", 0x18b8, 0 },
+ { "SGE_LA_RESERVED_11", 0x18bc, 0 },
+ { "SGE_LA_RDPTR_12", 0x18c0, 0 },
+ { "SGE_LA_RDDATA_12", 0x18c4, 0 },
+ { "SGE_LA_WRPTR_12", 0x18c8, 0 },
+ { "SGE_LA_RESERVED_12", 0x18cc, 0 },
+ { "SGE_LA_RDPTR_13", 0x18d0, 0 },
+ { "SGE_LA_RDDATA_13", 0x18d4, 0 },
+ { "SGE_LA_WRPTR_13", 0x18d8, 0 },
+ { "SGE_LA_RESERVED_13", 0x18dc, 0 },
+ { "SGE_LA_RDPTR_14", 0x18e0, 0 },
+ { "SGE_LA_RDDATA_14", 0x18e4, 0 },
+ { "SGE_LA_WRPTR_14", 0x18e8, 0 },
+ { "SGE_LA_RESERVED_14", 0x18ec, 0 },
+ { "SGE_LA_RDPTR_15", 0x18f0, 0 },
+ { "SGE_LA_RDDATA_15", 0x18f4, 0 },
+ { "SGE_LA_WRPTR_15", 0x18f8, 0 },
+ { "SGE_LA_RESERVED_15", 0x18fc, 0 },
+ { NULL }
+};
+
+struct reg_info t6_pcie_regs[] = {
+ { "PCIE_INT_ENABLE", 0x3000, 0 },
+ { "IPGrpPerr", 31, 1 },
+ { "NonFatalErr", 30, 1 },
+ { "RdRspErr", 29, 1 },
+ { "TRGT1GrpPerr", 28, 1 },
+ { "IPSOTPerr", 27, 1 },
+ { "IPRetryPerr", 26, 1 },
+ { "IPRxDataGrpPerr", 25, 1 },
+ { "IPRxHdrGrpPerr", 24, 1 },
+ { "PIOTagQPerr", 23, 1 },
+ { "MAGrpPerr", 22, 1 },
+ { "VFIDPerr", 21, 1 },
+ { "FIDPerr", 20, 1 },
+ { "CfgSnpPerr", 19, 1 },
+ { "HRspPerr", 18, 1 },
+ { "HReqRdPerr", 17, 1 },
+ { "HReqWrPerr", 16, 1 },
+ { "DRspPerr", 15, 1 },
+ { "DReqRdPerr", 14, 1 },
+ { "DReqWrPerr", 13, 1 },
+ { "CRspPerr", 12, 1 },
+ { "CReqRdPerr", 11, 1 },
+ { "MstTagQPerr", 10, 1 },
+ { "TgtTagQPerr", 9, 1 },
+ { "PIOReqGrpPerr", 8, 1 },
+ { "PIOCplGrpPerr", 7, 1 },
+ { "MSIXDIPerr", 6, 1 },
+ { "MSIXDataPerr", 5, 1 },
+ { "MSIXAddrHPerr", 4, 1 },
+ { "MSIXAddrLPerr", 3, 1 },
+ { "MSIXStiPerr", 2, 1 },
+ { "MstTimeoutPerr", 1, 1 },
+ { "MstGrpPerr", 0, 1 },
+ { "PCIE_INT_CAUSE", 0x3004, 0 },
+ { "IPGrpPerr", 31, 1 },
+ { "NonFatalErr", 30, 1 },
+ { "RdRspErr", 29, 1 },
+ { "TRGT1GrpPerr", 28, 1 },
+ { "IPSOTPerr", 27, 1 },
+ { "IPRetryPerr", 26, 1 },
+ { "IPRxDataGrpPerr", 25, 1 },
+ { "IPRxHdrGrpPerr", 24, 1 },
+ { "PIOTagQPerr", 23, 1 },
+ { "MAGrpPerr", 22, 1 },
+ { "VFIDPerr", 21, 1 },
+ { "FIDPerr", 20, 1 },
+ { "CfgSnpPerr", 19, 1 },
+ { "HRspPerr", 18, 1 },
+ { "HReqRdPerr", 17, 1 },
+ { "HReqWrPerr", 16, 1 },
+ { "DRspPerr", 15, 1 },
+ { "DReqRdPerr", 14, 1 },
+ { "DReqWrPerr", 13, 1 },
+ { "CRspPerr", 12, 1 },
+ { "CReqRdPerr", 11, 1 },
+ { "MstTagQPerr", 10, 1 },
+ { "TgtTagQPerr", 9, 1 },
+ { "PIOReqGrpPerr", 8, 1 },
+ { "PIOCplGrpPerr", 7, 1 },
+ { "MSIXDIPerr", 6, 1 },
+ { "MSIXDataPerr", 5, 1 },
+ { "MSIXAddrHPerr", 4, 1 },
+ { "MSIXAddrLPerr", 3, 1 },
+ { "MSIXStiPerr", 2, 1 },
+ { "MstTimeoutPerr", 1, 1 },
+ { "MstGrpPerr", 0, 1 },
+ { "PCIE_PERR_ENABLE", 0x3008, 0 },
+ { "IPGrpPerr", 31, 1 },
+ { "TRGT1GrpPerr", 28, 1 },
+ { "IPSOTPerr", 27, 1 },
+ { "IPRetryPerr", 26, 1 },
+ { "IPRxDataGrpPerr", 25, 1 },
+ { "IPRxHdrGrpPerr", 24, 1 },
+ { "PIOTagQPerr", 23, 1 },
+ { "MAGrpPerr", 22, 1 },
+ { "VFIDPerr", 21, 1 },
+ { "FIDPerr", 20, 1 },
+ { "CfgSnpPerr", 19, 1 },
+ { "HRspPerr", 18, 1 },
+ { "HReqRdPerr", 17, 1 },
+ { "HReqWrPerr", 16, 1 },
+ { "DRspPerr", 15, 1 },
+ { "DReqRdPerr", 14, 1 },
+ { "DReqWrPerr", 13, 1 },
+ { "CRspPerr", 12, 1 },
+ { "CReqRdPerr", 11, 1 },
+ { "MstTagQPerr", 10, 1 },
+ { "TgtTagQPerr", 9, 1 },
+ { "PIOReqGrpPerr", 8, 1 },
+ { "PIOCplGrpPerr", 7, 1 },
+ { "MSIXDIPerr", 6, 1 },
+ { "MSIXDataPerr", 5, 1 },
+ { "MSIXAddrHPerr", 4, 1 },
+ { "MSIXAddrLPerr", 3, 1 },
+ { "MSIXStiPerr", 2, 1 },
+ { "MstTimeoutPerr", 1, 1 },
+ { "MstGrpPerr", 0, 1 },
+ { "PCIE_PERR_INJECT", 0x300c, 0 },
+ { "MemSel", 1, 5 },
+ { "IDE", 0, 1 },
+ { "PCIE_NONFAT_ERR", 0x3010, 0 },
+ { "MARspUE", 30, 1 },
+ { "MAReqTimeout", 29, 1 },
+ { "TRGT1BARTypeErr", 28, 1 },
+ { "MAExtraRspErr", 27, 1 },
+ { "MARspTimeout", 26, 1 },
+ { "INTVFAllMSIDisErr", 25, 1 },
+ { "INTVFRangeErr", 24, 1 },
+ { "INTPLIRspErr", 23, 1 },
+ { "MEMReqRdTagErr", 22, 1 },
+ { "CFGInitDoneErr", 21, 1 },
+ { "BAR2Timeout", 20, 1 },
+ { "VPDTimeout", 19, 1 },
+ { "MEMRspRdTagErr", 18, 1 },
+ { "MEMRspWrTagErr", 17, 1 },
+ { "PIORspRdTagErr", 16, 1 },
+ { "PIORspWrTagErr", 15, 1 },
+ { "DBITimeout", 14, 1 },
+ { "PIOUnAlindWr", 13, 1 },
+ { "BAR2RdErr", 12, 1 },
+ { "MAWrEOPErr", 11, 1 },
+ { "MARdEOPErr", 10, 1 },
+ { "RdRspErr", 9, 1 },
+ { "VPDRspErr", 8, 1 },
+ { "KDBEOPErr", 7, 1 },
+ { "MemReq", 4, 1 },
+ { "PIOReq", 3, 1 },
+ { "BAR2Req", 2, 1 },
+ { "CfgSnp", 0, 1 },
+ { "PCIE_CFG", 0x3014, 0 },
+ { "PIOStopEn", 31, 1 },
+ { "DiagCtrlBus", 28, 3 },
+ { "IPPerrEn", 27, 1 },
+ { "CfgdExtTagEn", 26, 1 },
+ { "CfgdMaxPyldSz", 23, 3 },
+ { "CfgdMaxRdReqSz", 20, 3 },
+ { "DCAEn", 17, 1 },
+ { "CMDReqPriority", 16, 1 },
+ { "VPDReqProtect", 14, 2 },
+ { "DroppedRdRspData", 12, 1 },
+ { "AI_INTX_ReAssertEn", 11, 1 },
+ { "AutoTxnDisable", 10, 1 },
+ { "TC0_Stamp", 9, 1 },
+ { "AI_TCVal", 6, 3 },
+ { "DMAStopEn", 5, 1 },
+ { "DevStateRstMode", 4, 1 },
+ { "LinkReqRstPCIeCRstMode", 3, 1 },
+ { "LinkDnRstEn", 0, 1 },
+ { "PCIE_CFG2", 0x3018, 0 },
+ { "BAR2Timer", 4, 12 },
+ { "MstReqRdRRASimple", 3, 1 },
+ { "TotMaxTag", 0, 3 },
+ { "PCIE_CFG3", 0x301c, 0 },
+ { "AutoPIOCookieMatch", 6, 1 },
+ { "FLRPndCplMode", 4, 2 },
+ { "HMADCASTFirstOnly", 2, 1 },
+ { "CMDDCASTFirstOnly", 1, 1 },
+ { "DMADCASTFirstOnly", 0, 1 },
+ { "PCIE_CFG4", 0x3020, 0 },
+ { "L1ClkRemovalEn", 17, 1 },
+ { "ReadyEnterL23", 16, 1 },
+ { "ExitL1", 12, 1 },
+ { "EnterL1", 8, 1 },
+ { "GenPME", 0, 8 },
+ { "PCIE_CFG5", 0x3024, 0 },
+ { "EnableSKPParityFix", 2, 1 },
+ { "EnableL2EntryInL1", 1, 1 },
+ { "HoldCplEnteringL1", 0, 1 },
+ { "PCIE_CFG6", 0x3028, 0 },
+ { "PERstTimerCount", 12, 14 },
+ { "PERstTimeout", 8, 1 },
+ { "PERstTimer", 0, 4 },
+ { "PCIE_CFG7", 0x302c, 0 },
+ { "PCIE_CFG_SPACE_REQ", 0x3060, 0 },
+ { "Enable", 31, 1 },
+ { "AI", 30, 1 },
+ { "CS2", 29, 1 },
+ { "WrBE", 25, 4 },
+ { "VFVld", 24, 1 },
+ { "RVF", 16, 8 },
+ { "PF", 12, 3 },
+ { "ExtRegister", 8, 4 },
+ { "Register", 0, 8 },
+ { "PCIE_CFG_SPACE_DATA", 0x3064, 0 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3068, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x306c, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3070, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x3074, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3078, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x307c, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3080, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x3084, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3088, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x308c, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3090, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x3094, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x3098, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x309c, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MEM_ACCESS_BASE_WIN", 0x30a0, 0 },
+ { "PCIEOfst", 10, 22 },
+ { "BIR", 8, 2 },
+ { "Window", 0, 8 },
+ { "PCIE_MEM_ACCESS_OFFSET", 0x30a4, 0 },
+ { "MemOfst", 7, 25 },
+ { "PFNum", 0, 3 },
+ { "PCIE_MAILBOX_BASE_WIN", 0x30a8, 0 },
+ { "PCIEOfst", 6, 26 },
+ { "BIR", 4, 2 },
+ { "Window", 0, 2 },
+ { "PCIE_MAILBOX_OFFSET", 0x30ac, 0 },
+ { "MemOfst", 7, 25 },
+ { "PCIE_MA_CTRL", 0x30b0, 0 },
+ { "TagFree", 29, 1 },
+ { "MaxRspCnt", 24, 5 },
+ { "MaxReqCnt", 16, 7 },
+ { "MaxReqSize", 8, 3 },
+ { "MaxTag", 0, 5 },
+ { "PCIE_FW", 0x30b8, 0 },
+ { "PCIE_FW_PF", 0x30bc, 0 },
+ { "PCIE_FW_PF", 0x30c0, 0 },
+ { "PCIE_FW_PF", 0x30c4, 0 },
+ { "PCIE_FW_PF", 0x30c8, 0 },
+ { "PCIE_FW_PF", 0x30cc, 0 },
+ { "PCIE_FW_PF", 0x30d0, 0 },
+ { "PCIE_FW_PF", 0x30d4, 0 },
+ { "PCIE_FW_PF", 0x30d8, 0 },
+ { "PCIE_PIO_PAUSE", 0x30dc, 0 },
+ { "PIOPauseDone", 31, 1 },
+ { "MSTPauseDone", 30, 1 },
+ { "PauseTime", 4, 24 },
+ { "MSTPause", 1, 1 },
+ { "PIOPause", 0, 1 },
+ { "PCIE_MA_STAT", 0x30e0, 0 },
+ { "PCIE_STATIC_CFG1", 0x30e4, 0 },
+ { "AUXPOWER_DETECTED", 27, 1 },
+ { "PCIE_STATIC_CFG2", 0x30e8, 0 },
+ { "PL_CONTROL", 16, 16 },
+ { "STATIC_SPARE3", 0, 14 },
+ { "PCIE_DBG_INDIR_REQ", 0x30ec, 0 },
+ { "Enable", 31, 1 },
+ { "AI", 30, 1 },
+ { "Pointer", 8, 16 },
+ { "Select", 0, 4 },
+ { "PCIE_DBG_INDIR_DATA_0", 0x30f0, 0 },
+ { "PCIE_DBG_INDIR_DATA_1", 0x30f4, 0 },
+ { "PCIE_DBG_INDIR_DATA_2", 0x30f8, 0 },
+ { "PCIE_DBG_INDIR_DATA_3", 0x30fc, 0 },
+ { "PCIE_PF_INT_CFG", 0x3140, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x3144, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3148, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x314c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3150, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x3154, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3158, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x315c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3160, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x3164, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3168, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x316c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3170, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x3174, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_INT_CFG", 0x3178, 0 },
+ { "PBAOfst", 28, 4 },
+ { "TABOfst", 24, 4 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_PF_INT_CFG2", 0x317c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3180, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3184, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3188, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x318c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3190, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3194, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3198, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x319c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31a0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31a4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31a8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31ac, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31b0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31b4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31b8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31bc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31c0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31c4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31c8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31cc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31d0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31d4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31d8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31dc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31e0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31e4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31e8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31ec, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31f0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31f4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x31f8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x31fc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3200, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3204, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3208, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x320c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3210, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3214, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3218, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x321c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3220, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3224, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3228, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x322c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3230, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3234, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3238, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x323c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3240, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3244, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3248, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x324c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3250, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3254, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3258, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x325c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3260, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3264, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3268, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x326c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3270, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3274, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3278, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x327c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3280, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3284, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3288, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x328c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3290, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3294, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3298, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x329c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32a0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32a4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32a8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32ac, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32b0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32b4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32b8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32bc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32c0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32c4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32c8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32cc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32d0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32d4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32d8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32dc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32e0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32e4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32e8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32ec, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32f0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32f4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x32f8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x32fc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3300, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3304, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3308, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x330c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3310, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3314, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3318, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x331c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3320, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3324, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3328, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x332c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3330, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3334, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3338, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x333c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3340, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3344, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3348, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x334c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3350, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3354, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3358, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x335c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3360, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3364, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3368, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x336c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3370, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3374, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3378, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x337c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3380, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3384, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3388, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x338c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3390, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3394, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3398, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x339c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33a0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33a4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33a8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33ac, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33b0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33b4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33b8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33bc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33c0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33c4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33c8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33cc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33d0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33d4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33d8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33dc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33e0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33e4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33e8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33ec, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33f0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33f4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x33f8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x33fc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3400, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3404, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3408, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x340c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3410, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3414, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3418, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x341c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3420, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3424, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3428, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x342c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3430, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3434, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3438, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x343c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3440, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3444, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3448, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x344c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3450, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3454, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3458, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x345c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3460, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3464, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3468, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x346c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3470, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3474, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3478, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x347c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3480, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3484, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3488, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x348c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3490, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3494, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3498, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x349c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34a0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34a4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34a8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34ac, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34b0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34b4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34b8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34bc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34c0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34c4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34c8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34cc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34d0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34d4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34d8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34dc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34e0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34e4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34e8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34ec, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34f0, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34f4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x34f8, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x34fc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3500, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3504, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3508, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x350c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3510, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3514, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3518, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x351c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3520, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3524, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3528, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x352c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3530, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3534, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3538, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x353c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3540, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3544, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3548, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x354c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3550, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3554, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3558, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x355c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3560, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3564, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3568, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x356c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3570, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x3574, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_INT_CFG", 0x3578, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_INT_CFG2", 0x357c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_PF_MSI_EN", 0x35a8, 0 },
+ { "PCIE_VF_MSI_EN_0", 0x35ac, 0 },
+ { "PCIE_VF_MSI_EN_1", 0x35b0, 0 },
+ { "PCIE_VF_MSI_EN_2", 0x35b4, 0 },
+ { "PCIE_VF_MSI_EN_3", 0x35b8, 0 },
+ { "PCIE_PF_MSIX_EN", 0x35bc, 0 },
+ { "PCIE_VF_MSIX_EN_0", 0x35c0, 0 },
+ { "PCIE_VF_MSIX_EN_1", 0x35c4, 0 },
+ { "PCIE_VF_MSIX_EN_2", 0x35c8, 0 },
+ { "PCIE_VF_MSIX_EN_3", 0x35cc, 0 },
+ { "PCIE_FID_VFID_SEL", 0x35ec, 0 },
+ { "PCIE_FID_VFID", 0x3600, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3604, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3608, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x360c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3610, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3614, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3618, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x361c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3620, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3624, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3628, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x362c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3630, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3634, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3638, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x363c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3640, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3644, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3648, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x364c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3650, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3654, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3658, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x365c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3660, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3664, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3668, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x366c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3670, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3674, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3678, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x367c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3680, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3684, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3688, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x368c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3690, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3694, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x3698, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x369c, 0 },
+ { "Select", 30, 2 },
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+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5560, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5564, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5568, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x556c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5570, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5574, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5578, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x557c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5580, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5584, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5588, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x558c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5590, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5594, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x5598, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x559c, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55a0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55a4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55a8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55ac, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55b0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55b4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55b8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55bc, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55c0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55c4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55c8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55cc, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55d0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55d4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55d8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55dc, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55e0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55e4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55e8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55ec, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55f0, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55f4, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55f8, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_FID_VFID", 0x55fc, 0 },
+ { "Select", 30, 2 },
+ { "IDO", 24, 1 },
+ { "VFID", 15, 9 },
+ { "TC", 12, 3 },
+ { "VFVld", 11, 1 },
+ { "PF", 8, 3 },
+ { "RVF", 0, 8 },
+ { "PCIE_COOKIE_STAT", 0x5600, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x5604, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x5608, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x560c, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x5610, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x5614, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x5618, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_COOKIE_STAT", 0x561c, 0 },
+ { "CookieB", 16, 10 },
+ { "CookieA", 0, 10 },
+ { "PCIE_FLR_PIO", 0x5620, 0 },
+ { "RcvdBAR2Cookie", 24, 8 },
+ { "RcvdMARspCookie", 16, 8 },
+ { "RcvdPIORspCookie", 8, 8 },
+ { "ExpdCookie", 0, 8 },
+ { "PCIE_FLR_PIO2", 0x5624, 0 },
+ { "RcvdVDMRxCookie", 24, 8 },
+ { "RcvdVDMTxCookie", 16, 8 },
+ { "RcvdMAReqCookie", 8, 8 },
+ { "RcvdPIOReqCookie", 0, 8 },
+ { "PCIE_VC0_CDTS0", 0x56cc, 0 },
+ { "CPLD0", 20, 12 },
+ { "PH0", 12, 8 },
+ { "PD0", 0, 12 },
+ { "PCIE_VC0_CDTS1", 0x56d0, 0 },
+ { "CPLH0", 20, 8 },
+ { "NPH0", 12, 8 },
+ { "NPD0", 0, 12 },
+ { "PCIE_VC1_CDTS0", 0x56d4, 0 },
+ { "CPLD1", 20, 12 },
+ { "PH1", 12, 8 },
+ { "PD1", 0, 12 },
+ { "PCIE_VC1_CDTS1", 0x56d8, 0 },
+ { "CPLH1", 20, 8 },
+ { "NPH1", 12, 8 },
+ { "NPD1", 0, 12 },
+ { "PCIE_FLR_PF_STATUS", 0x56dc, 0 },
+ { "PCIE_FLR_VF0_STATUS", 0x56e0, 0 },
+ { "PCIE_FLR_VF1_STATUS", 0x56e4, 0 },
+ { "PCIE_FLR_VF2_STATUS", 0x56e8, 0 },
+ { "PCIE_FLR_VF3_STATUS", 0x56ec, 0 },
+ { "PCIE_STAT", 0x56f4, 0 },
+ { "PM_Status", 24, 8 },
+ { "PM_CurrentState", 20, 3 },
+ { "LTSSMEnable", 12, 1 },
+ { "StateCfgInitF", 4, 8 },
+ { "StateCfgInit", 0, 4 },
+ { "PCIE_CRS", 0x56f8, 0 },
+ { "PCIE_LTSSM", 0x56fc, 0 },
+ { "Stall_Disable", 1, 1 },
+ { "Enable", 0, 1 },
+ { "PCIE_PF_CFG", 0x1e040, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1e044, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1e04c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1e440, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1e444, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1e44c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1e840, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1e844, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1e84c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1ec40, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1ec44, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1ec4c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1f040, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1f044, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1f04c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1f440, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1f444, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1f44c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1f840, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1f844, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1f84c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_PF_CFG", 0x1fc40, 0 },
+ { "INTXStat", 16, 1 },
+ { "AIVec", 4, 10 },
+ { "D3HotEn", 1, 1 },
+ { "CLIDecEn", 0, 1 },
+ { "PCIE_PF_CLI", 0x1fc44, 0 },
+ { "PCIE_PF_EXPROM_OFST", 0x1fc4c, 0 },
+ { "Offset", 10, 14 },
+ { "PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER", 0x5700, 0 },
+ { "Replay_Time_Limit", 16, 16 },
+ { "Ack_Latency_Timer_Limit", 0, 16 },
+ { "PCIE_CORE_VENDOR_SPECIFIC_DLLP", 0x5704, 0 },
+ { "PCIE_CORE_PORT_FORCE_LINK", 0x5708, 0 },
+ { "Low_Power_Entrance_Count", 24, 8 },
+ { "Link_State", 16, 6 },
+ { "Force_Link", 15, 1 },
+ { "Link_Number", 0, 8 },
+ { "PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL", 0x570c, 0 },
+ { "Enter_ASPM_L1_wo_L0s", 30, 1 },
+ { "L1_Entrance_Latency", 27, 3 },
+ { "L0s_Entrance_Latency", 24, 3 },
+ { "Common_Clock_N_FTS", 16, 8 },
+ { "N_FTS", 8, 8 },
+ { "Ack_Frequency", 0, 8 },
+ { "PCIE_CORE_PORT_LINK_CONTROL", 0x5710, 0 },
+ { "Crosslink_Active", 23, 1 },
+ { "Crosslink_Enable", 22, 1 },
+ { "Link_Mode_Enable", 16, 6 },
+ { "Fast_Link_Mode", 7, 1 },
+ { "DLL_Link_Enable", 5, 1 },
+ { "Reset_Assert", 3, 1 },
+ { "Loopback_Enable", 2, 1 },
+ { "Scramble_Disable", 1, 1 },
+ { "Vendor_Specific_DLLP_Request", 0, 1 },
+ { "PCIE_CORE_LANE_SKEW", 0x5714, 0 },
+ { "Disable_DeSkew", 31, 1 },
+ { "Ack_Nak_Disable", 25, 1 },
+ { "Flow_Control_Disable", 24, 1 },
+ { "Insert_TxSkew", 0, 24 },
+ { "PCIE_CORE_SYMBOL_NUMBER", 0x5718, 0 },
+ { "Ack_Nak_Timer_Modifier", 19, 5 },
+ { "Replay_Timer_Modifier", 14, 5 },
+ { "MaxFunc", 0, 3 },
+ { "PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1", 0x571c, 0 },
+ { "Mask_RADM_Filter", 16, 16 },
+ { "Disable_FC_Watchdog", 15, 1 },
+ { "SKP_Interval", 0, 11 },
+ { "PCIE_CORE_FILTER_MASK2", 0x5720, 0 },
+ { "PCIE_CORE_DEBUG_0", 0x5728, 0 },
+ { "PCIE_CORE_DEBUG_1", 0x572c, 0 },
+ { "PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS", 0x5730, 0 },
+ { "TxPH_FC", 12, 8 },
+ { "TxPD_FC", 0, 12 },
+ { "PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS", 0x5734, 0 },
+ { "TxNPH_FC", 12, 8 },
+ { "TxNPD_FC", 0, 12 },
+ { "PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS", 0x5738, 0 },
+ { "TxCPLH_FC", 12, 8 },
+ { "TxCPLD_FC", 0, 12 },
+ { "PCIE_CORE_QUEUE_STATUS", 0x573c, 0 },
+ { "RxQueue_Not_Empty", 2, 1 },
+ { "TxRetryBuf_Not_Empty", 1, 1 },
+ { "RxTLP_FC_Not_Returned", 0, 1 },
+ { "PCIE_CORE_VC_TRANSMIT_ARBITRATION_1", 0x5740, 0 },
+ { "VC3_WRR", 24, 8 },
+ { "VC2_WRR", 16, 8 },
+ { "VC1_WRR", 8, 8 },
+ { "VC0_WRR", 0, 8 },
+ { "PCIE_CORE_VC_TRANSMIT_ARBITRATION_2", 0x5744, 0 },
+ { "VC7_WRR", 24, 8 },
+ { "VC6_WRR", 16, 8 },
+ { "VC5_WRR", 8, 8 },
+ { "VC4_WRR", 0, 8 },
+ { "PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL", 0x5748, 0 },
+ { "VC0_Rx_Ordering", 31, 1 },
+ { "VC0_TLP_Ordering", 30, 1 },
+ { "VC0_PTLP_Queue_Mode", 21, 3 },
+ { "VC0_PH_Credits", 12, 8 },
+ { "VC0_PD_Credits", 0, 12 },
+ { "PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x574c, 0 },
+ { "VC0_NPTLP_Queue_Mode", 21, 3 },
+ { "VC0_NPH_Credits", 12, 8 },
+ { "VC0_NPD_Credits", 0, 12 },
+ { "PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x5750, 0 },
+ { "VC0_CPLTLP_Queue_Mode", 21, 3 },
+ { "VC0_CPLH_Credits", 12, 8 },
+ { "VC0_CPLD_Credits", 0, 12 },
+ { "PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL", 0x5754, 0 },
+ { "VC1_TLP_Ordering", 30, 1 },
+ { "VC1_PTLP_Queue_Mode", 21, 3 },
+ { "VC1_PH_Credits", 12, 8 },
+ { "VC1_PD_Credits", 0, 12 },
+ { "PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x5758, 0 },
+ { "VC1_NPTLP_Queue_Mode", 21, 3 },
+ { "VC1_NPH_Credits", 12, 8 },
+ { "VC1_NPD_Credits", 0, 12 },
+ { "PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x575c, 0 },
+ { "VC1_CPLTLP_Queue_Mode", 21, 3 },
+ { "VC1_CPLH_Credits", 12, 8 },
+ { "VC1_CPLD_Credits", 0, 12 },
+ { "PCIE_CORE_LINK_WIDTH_SPEED_CHANGE", 0x580c, 0 },
+ { "Sel_DeEmphasis", 20, 1 },
+ { "TxCmplRcv", 19, 1 },
+ { "PhyTxSwing", 18, 1 },
+ { "DirSpdChange", 17, 1 },
+ { "Auto_Lane_Flip_Ctrl_En", 16, 1 },
+ { "Num_Lanes", 8, 5 },
+ { "NFTS_Gen2_3", 0, 8 },
+ { "PCIE_CORE_PHY_STATUS", 0x5810, 0 },
+ { "PCIE_CORE_PHY_CONTROL", 0x5814, 0 },
+ { "PCIE_CORE_GEN3_CONTROL", 0x5890, 0 },
+ { "DC_Balance_Disable", 18, 1 },
+ { "DLLP_Delay_Disable", 17, 1 },
+ { "Eql_Disable", 16, 1 },
+ { "Eql_Redo_Disable", 11, 1 },
+ { "Eql_EIEOS_CntRst_Disable", 10, 1 },
+ { "Eql_PH2_PH3_Disable", 9, 1 },
+ { "Disable_Scrambler", 8, 1 },
+ { "PCIE_CORE_GEN3_EQ_FS_LF", 0x5894, 0 },
+ { "Full_Swing", 6, 6 },
+ { "Low_Frequency", 0, 6 },
+ { "PCIE_CORE_GEN3_EQ_PRESET_COEFF", 0x5898, 0 },
+ { "PostCursor", 12, 6 },
+ { "Cursor", 6, 6 },
+ { "PreCursor", 0, 6 },
+ { "PCIE_CORE_GEN3_EQ_PRESET_INDEX", 0x589c, 0 },
+ { "PCIE_CORE_GEN3_EQ_STATUS", 0x58a4, 0 },
+ { "PCIE_CORE_GEN3_EQ_CONTROL", 0x58a8, 0 },
+ { "Include_Initial_FOM", 24, 1 },
+ { "Preset_Request_Vector", 8, 16 },
+ { "Phase23_2ms_Timeout_Disable", 5, 1 },
+ { "After24ms", 4, 1 },
+ { "Feedback_Mode", 0, 4 },
+ { "PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK", 0x58ac, 0 },
+ { "WinAperture_CPlus1", 14, 4 },
+ { "WinAperture_CMins1", 10, 4 },
+ { "Convergence_WinDepth", 5, 5 },
+ { "EQMasterPhase_MinTime", 0, 5 },
+ { "PCIE_CORE_PIPE_CONTROL", 0x58b8, 0 },
+ { "Loopback_Enable", 31, 1 },
+ { "PCIE_CORE_DBI_RO_WE", 0x58bc, 0 },
+ { "PCIE_DMA_CFG", 0x5940, 0 },
+ { "MaxPyldSize", 28, 3 },
+ { "MaxReqCnt", 20, 7 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 9, 8 },
+ { "SeqChkDis", 8, 1 },
+ { "MinTag", 0, 8 },
+ { "PCIE_DMA_STAT", 0x5944, 0 },
+ { "RspCnt", 20, 10 },
+ { "RdReqCnt", 12, 6 },
+ { "WrReqCnt", 0, 9 },
+ { "PCIE_DMA_STAT2", 0x5948, 0 },
+ { "CookieCnt", 24, 4 },
+ { "RdSeqNumUpdCnt", 20, 4 },
+ { "SIReqCnt", 16, 4 },
+ { "WrEOPMatchSOP", 12, 1 },
+ { "WrSOPCnt", 8, 4 },
+ { "RdSOPCnt", 0, 8 },
+ { "PCIE_DMA_STAT3", 0x594c, 0 },
+ { "AtmReqSOPCnt", 24, 8 },
+ { "AtmEOPMatchSOP", 17, 1 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_DMA_CFG", 0x5950, 0 },
+ { "MaxPyldSize", 28, 3 },
+ { "MaxReqCnt", 20, 7 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 9, 8 },
+ { "SeqChkDis", 8, 1 },
+ { "MinTag", 0, 8 },
+ { "PCIE_DMA_STAT", 0x5954, 0 },
+ { "RspCnt", 20, 10 },
+ { "RdReqCnt", 12, 6 },
+ { "WrReqCnt", 0, 9 },
+ { "PCIE_DMA_STAT2", 0x5958, 0 },
+ { "CookieCnt", 24, 4 },
+ { "RdSeqNumUpdCnt", 20, 4 },
+ { "SIReqCnt", 16, 4 },
+ { "WrEOPMatchSOP", 12, 1 },
+ { "WrSOPCnt", 8, 4 },
+ { "RdSOPCnt", 0, 8 },
+ { "PCIE_DMA_STAT3", 0x595c, 0 },
+ { "AtmReqSOPCnt", 24, 8 },
+ { "AtmEOPMatchSOP", 17, 1 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_CMD_CFG", 0x5980, 0 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 9, 6 },
+ { "UseCmdPool", 8, 1 },
+ { "MinTag", 0, 8 },
+ { "PCIE_CMD_STAT", 0x5984, 0 },
+ { "RspCnt", 20, 8 },
+ { "RdReqCnt", 12, 4 },
+ { "PCIE_CMD_STAT2", 0x5988, 0 },
+ { "PCIE_CMD_STAT3", 0x598c, 0 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_HMA_CFG", 0x59b0, 0 },
+ { "MaxPyldSize", 28, 3 },
+ { "MaxReqCnt", 20, 7 },
+ { "MaxRdReqSize", 17, 3 },
+ { "MaxRspCnt", 9, 8 },
+ { "SeqChkDis", 8, 1 },
+ { "MinTag", 0, 8 },
+ { "PCIE_HMA_STAT", 0x59b4, 0 },
+ { "RspCnt", 20, 10 },
+ { "RdReqCnt", 12, 6 },
+ { "WrReqCnt", 0, 9 },
+ { "PCIE_HMA_STAT2", 0x59b8, 0 },
+ { "CookieCnt", 24, 4 },
+ { "RdSeqNumUpdCnt", 20, 4 },
+ { "WrEOPMatchSOP", 12, 1 },
+ { "WrSOPCnt", 8, 4 },
+ { "RdSOPCnt", 0, 8 },
+ { "PCIE_HMA_STAT3", 0x59bc, 0 },
+ { "RspEOPMatchSOP", 16, 1 },
+ { "RspErrCnt", 8, 8 },
+ { "RspSOPCnt", 0, 8 },
+ { "PCIE_CGEN", 0x59c0, 0 },
+ { "VPD_Dynamic_CGEN", 26, 1 },
+ { "MA_Dynamic_CGEN", 25, 1 },
+ { "Tagq_Dynamic_CGEN", 24, 1 },
+ { "ReqCtl_Dynamic_CGEN", 23, 1 },
+ { "RspDataProc_Dynamic_CGEN", 22, 1 },
+ { "RspRdq_Dynamic_CGEN", 21, 1 },
+ { "RspIPif_Dynamic_CGEN", 20, 1 },
+ { "HMA_Static_CGEN", 19, 1 },
+ { "HMA_Dynamic_CGEN", 18, 1 },
+ { "CMD_Static_CGEN", 16, 1 },
+ { "CMD_Dynamic_CGEN", 15, 1 },
+ { "DMA_Static_CGEN", 13, 1 },
+ { "DMA_Dynamic_CGEN", 12, 1 },
+ { "VFID_SleepStatus", 10, 1 },
+ { "VC1_SleepStatus", 9, 1 },
+ { "STI_SleepStatus", 8, 1 },
+ { "VFID_SleepReq", 2, 1 },
+ { "VC1_SleepReq", 1, 1 },
+ { "STI_SleepReq", 0, 1 },
+ { "PCIE_MA_RSP", 0x59c4, 0 },
+ { "TimerValue", 8, 24 },
+ { "MAReqTimerEn", 1, 1 },
+ { "TimerEn", 0, 1 },
+ { "PCIE_HPRD", 0x59c8, 0 },
+ { "NPH_CreditsAvailVC0", 19, 2 },
+ { "NPD_CreditsAvailVC0", 17, 2 },
+ { "NPH_CreditsAvailVC1", 15, 2 },
+ { "NPD_CreditsAvailVC1", 13, 2 },
+ { "NPH_CreditsRequired", 11, 2 },
+ { "NPD_CreditsRequired", 9, 2 },
+ { "ReqBurstCount", 5, 4 },
+ { "ReqBurstFrequency", 1, 4 },
+ { "EnableVC1", 0, 1 },
+ { "PCIE_PERR_GROUP", 0x59d0, 0 },
+ { "MA_RspCtlPerr", 26, 1 },
+ { "MST_DataPathPerr", 25, 1 },
+ { "MST_RspRdQPerr", 24, 1 },
+ { "TRGT1_FIDLkUpHdrPerr", 20, 1 },
+ { "TRGT1_AlindDataPerr", 19, 1 },
+ { "TRGT1_UnAlinDataPerr", 18, 1 },
+ { "TRGT1_ReqDataPerr", 17, 1 },
+ { "TRGT1_ReqHdrPerr", 16, 1 },
+ { "IPRxData_VC0Perr", 15, 1 },
+ { "IPRxHdr_VC0Perr", 14, 1 },
+ { "PIOCpl_VDMTxCtlPerr", 13, 1 },
+ { "PIOCpl_VDMTxDataPerr", 12, 1 },
+ { "MA_RspDataPerr", 11, 1 },
+ { "MA_CplTagQPerr", 10, 1 },
+ { "MA_ReqTagQPerr", 9, 1 },
+ { "PIOReq_BAR2CtlPerr", 8, 1 },
+ { "PIOReq_MEMCtlPerr", 7, 1 },
+ { "PIOReq_PLMCtlPerr", 6, 1 },
+ { "PIOReq_BAR2DataPerr", 5, 1 },
+ { "PIOReq_MEMDataPerr", 4, 1 },
+ { "PIOReq_PLMDataPerr", 3, 1 },
+ { "PIOCpl_CtlPerr", 2, 1 },
+ { "PIOCpl_DataPerr", 1, 1 },
+ { "PIOCpl_PLMRspPerr", 0, 1 },
+ { "PCIE_RSP_ERR_INT_LOG_EN", 0x59d4, 0 },
+ { "CplStatusIntEn", 12, 1 },
+ { "TimeoutIntEn", 11, 1 },
+ { "DisabledIntEn", 10, 1 },
+ { "RspDropFLRIntEn", 9, 1 },
+ { "ReqUnderFLRIntEn", 8, 1 },
+ { "CplStatusLogEn", 4, 1 },
+ { "TimeoutLogEn", 3, 1 },
+ { "DisabledLogEn", 2, 1 },
+ { "RspDropFLRLogEn", 1, 1 },
+ { "ReqUnderFLRLogEn", 0, 1 },
+ { "PCIE_RSP_ERR_LOG1", 0x59d8, 0 },
+ { "Tag", 25, 7 },
+ { "CID", 22, 3 },
+ { "ChNum", 19, 3 },
+ { "ByteLen", 6, 13 },
+ { "Reason", 3, 3 },
+ { "CplStatus", 0, 3 },
+ { "PCIE_RSP_ERR_LOG2", 0x59dc, 0 },
+ { "Valid", 31, 1 },
+ { "Addr10b", 9, 10 },
+ { "VFID", 0, 9 },
+ { "PCIE_REVISION", 0x5a00, 0 },
+ { "PCIE_PDEBUG_INDEX", 0x5a04, 0 },
+ { "PDEBUGSelH", 16, 7 },
+ { "PDEBUGSelL", 0, 7 },
+ { "PCIE_PDEBUG_DATA_HIGH", 0x5a08, 0 },
+ { "PCIE_PDEBUG_DATA_LOW", 0x5a0c, 0 },
+ { "PCIE_CDEBUG_INDEX", 0x5a10, 0 },
+ { "CDEBUGSelH", 16, 8 },
+ { "CDEBUGSelL", 0, 8 },
+ { "PCIE_CDEBUG_DATA_HIGH", 0x5a14, 0 },
+ { "PCIE_CDEBUG_DATA_LOW", 0x5a18, 0 },
+ { "PCIE_BUS_MST_STAT_0", 0x5a60, 0 },
+ { "PCIE_BUS_MST_STAT_1", 0x5a64, 0 },
+ { "PCIE_BUS_MST_STAT_2", 0x5a68, 0 },
+ { "PCIE_BUS_MST_STAT_3", 0x5a6c, 0 },
+ { "PCIE_RSP_ERR_STAT_0", 0x5a80, 0 },
+ { "PCIE_RSP_ERR_STAT_1", 0x5a84, 0 },
+ { "PCIE_RSP_ERR_STAT_2", 0x5a88, 0 },
+ { "PCIE_RSP_ERR_STAT_3", 0x5a8c, 0 },
+ { "PCIE_DBI_TIMEOUT_CTL", 0x5a94, 0 },
+ { "PCIE_DBI_TIMEOUT_STATUS0", 0x5a98, 0 },
+ { "PCIE_DBI_TIMEOUT_STATUS1", 0x5a9c, 0 },
+ { "Valid", 31, 1 },
+ { "Source", 17, 2 },
+ { "Write", 13, 4 },
+ { "CS2", 12, 1 },
+ { "PF", 9, 3 },
+ { "VFVld", 8, 1 },
+ { "VF", 0, 8 },
+ { "PCIE_PB_CTL", 0x5b94, 0 },
+ { "PB_Sel", 16, 8 },
+ { "PB_SelReg", 8, 8 },
+ { "PB_Func", 0, 3 },
+ { "PCIE_PB_DATA", 0x5b98, 0 },
+ { "PCIE_CHANGESET", 0x59fc, 0 },
+ { "PCIE_CUR_LINK", 0x5b9c, 0 },
+ { "CfgInitCoeffDoneSeen", 22, 1 },
+ { "CfgInitCoeffDone", 21, 1 },
+ { "xmlh_link_up", 20, 1 },
+ { "pm_linkst_in_l0s", 19, 1 },
+ { "pm_linkst_in_l1", 18, 1 },
+ { "pm_linkst_in_l2", 17, 1 },
+ { "pm_linkst_l2_exit", 16, 1 },
+ { "xmlh_in_rl0s", 15, 1 },
+ { "xmlh_ltssm_state_rcvry_eq", 14, 1 },
+ { "NegotiatedWidth", 8, 6 },
+ { "ActiveLanes", 0, 8 },
+ { "PCIE_PHY_REQRXPWR", 0x5ba0, 0 },
+ { "Req_LnH_RxStateDone", 31, 1 },
+ { "Req_LnH_RxStateReq", 30, 1 },
+ { "Req_LnH_RxPwrState", 28, 2 },
+ { "Req_LnG_RxStateDone", 27, 1 },
+ { "Req_LnG_RxStateReq", 26, 1 },
+ { "Req_LnG_RxPwrState", 24, 2 },
+ { "Req_LnF_RxStateDone", 23, 1 },
+ { "Req_LnF_RxStateReq", 22, 1 },
+ { "Req_LnF_RxPwrState", 20, 2 },
+ { "Req_LnE_RxStateDone", 19, 1 },
+ { "Req_LnE_RxStateReq", 18, 1 },
+ { "Req_LnE_RxPwrState", 16, 2 },
+ { "Req_LnD_RxStateDone", 15, 1 },
+ { "Req_LnD_RxStateReq", 14, 1 },
+ { "Req_LnD_RxPwrState", 12, 2 },
+ { "Req_LnC_RxStateDone", 11, 1 },
+ { "Req_LnC_RxStateReq", 10, 1 },
+ { "Req_LnC_RxPwrState", 8, 2 },
+ { "Req_LnB_RxStateDone", 7, 1 },
+ { "Req_LnB_RxStateReq", 6, 1 },
+ { "Req_LnB_RxPwrState", 4, 2 },
+ { "Req_LnA_RxStateDone", 3, 1 },
+ { "Req_LnA_RxStateReq", 2, 1 },
+ { "Req_LnA_RxPwrState", 0, 2 },
+ { "PCIE_PHY_CURRXPWR", 0x5ba4, 0 },
+ { "Cur_LnH_RxPwrState", 28, 3 },
+ { "Cur_LnG_RxPwrState", 24, 3 },
+ { "Cur_LnF_RxPwrState", 20, 3 },
+ { "Cur_LnE_RxPwrState", 16, 3 },
+ { "Cur_LnD_RxPwrState", 12, 3 },
+ { "Cur_LnC_RxPwrState", 8, 3 },
+ { "Cur_LnB_RxPwrState", 4, 3 },
+ { "Cur_LnA_RxPwrState", 0, 3 },
+ { "PCIE_PHY_GEN3_AE0", 0x5ba8, 0 },
+ { "LnD_STAT", 28, 3 },
+ { "LnD_CMD", 24, 3 },
+ { "LnC_STAT", 20, 3 },
+ { "LnC_CMD", 16, 3 },
+ { "LnB_STAT", 12, 3 },
+ { "LnB_CMD", 8, 3 },
+ { "LnA_STAT", 4, 3 },
+ { "LnA_CMD", 0, 3 },
+ { "PCIE_PHY_GEN3_AE1", 0x5bac, 0 },
+ { "LnH_STAT", 28, 3 },
+ { "LnH_CMD", 24, 3 },
+ { "LnG_STAT", 20, 3 },
+ { "LnG_CMD", 16, 3 },
+ { "LnF_STAT", 12, 3 },
+ { "LnF_CMD", 8, 3 },
+ { "LnE_STAT", 4, 3 },
+ { "LnE_CMD", 0, 3 },
+ { "PCIE_PHY_FS_LF0", 0x5bb0, 0 },
+ { "Lane1LF", 24, 6 },
+ { "Lane1FS", 16, 6 },
+ { "Lane0LF", 8, 6 },
+ { "Lane0FS", 0, 6 },
+ { "PCIE_PHY_FS_LF1", 0x5bb4, 0 },
+ { "Lane3LF", 24, 6 },
+ { "Lane3FS", 16, 6 },
+ { "Lane2LF", 8, 6 },
+ { "Lane2FS", 0, 6 },
+ { "PCIE_PHY_FS_LF2", 0x5bb8, 0 },
+ { "Lane5LF", 24, 6 },
+ { "Lane5FS", 16, 6 },
+ { "Lane4LF", 8, 6 },
+ { "Lane4FS", 0, 6 },
+ { "PCIE_PHY_FS_LF3", 0x5bbc, 0 },
+ { "Lane7LF", 24, 6 },
+ { "Lane7FS", 16, 6 },
+ { "Lane6LF", 8, 6 },
+ { "Lane6FS", 0, 6 },
+ { "PCIE_PHY_PRESET_REQ", 0x5bc0, 0 },
+ { "CoeffDone", 16, 1 },
+ { "CoeffLane", 8, 4 },
+ { "CoeffStart", 0, 1 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bc4, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bc8, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bcc, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bd0, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bd4, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bd8, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bdc, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5be0, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5be4, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5be8, 0 },
+ { "PCIE_PHY_PRESET_COEFF", 0x5bec, 0 },
+ { "PCIE_PHY_INDIR_REQ", 0x5bf0, 0 },
+ { "Enable", 31, 1 },
+ { "RegAddr", 0, 16 },
+ { "PCIE_PHY_INDIR_DATA", 0x5bf4, 0 },
+ { "PCIE_STATIC_SPARE1", 0x5bf8, 0 },
+ { "PCIE_STATIC_SPARE2", 0x5bfc, 0 },
+ { "PCIE_KDOORBELL_GTS_PF_BASE_LEN", 0x5c10, 0 },
+ { "KDB_PF_Len", 24, 5 },
+ { "KDB_PF_BaseAddr", 0, 20 },
+ { "PCIE_KDOORBELL_GTS_VF_BASE_LEN", 0x5c14, 0 },
+ { "KDB_VF_Len", 24, 5 },
+ { "KDB_VF_BaseAddr", 0, 20 },
+ { "PCIE_KDOORBELL_GTS_VF_OFFSET", 0x5c18, 0 },
+ { "PCIE_PHY_REQRXPWR1", 0x5c1c, 0 },
+ { "Req_LnP_RxStateDone", 31, 1 },
+ { "Req_LnP_RxStateReq", 30, 1 },
+ { "Req_LnP_RxPwrState", 28, 2 },
+ { "Req_LnO_RxStateDone", 27, 1 },
+ { "Req_LnO_RxStateReq", 26, 1 },
+ { "Req_LnO_RxPwrState", 24, 2 },
+ { "Req_LnN_RxStateDone", 23, 1 },
+ { "Req_LnN_RxStateReq", 22, 1 },
+ { "Req_LnN_RxPwrState", 20, 2 },
+ { "Req_LnM_RxStateDone", 19, 1 },
+ { "Req_LnM_RxStateReq", 18, 1 },
+ { "Req_LnM_RxPwrState", 16, 2 },
+ { "Req_LnL_RxStateDone", 15, 1 },
+ { "Req_LnL_RxStateReq", 14, 1 },
+ { "Req_LnL_RxPwrState", 12, 2 },
+ { "Req_LnK_RxStateDone", 11, 1 },
+ { "Req_LnK_RxStateReq", 10, 1 },
+ { "Req_LnK_RxPwrState", 8, 2 },
+ { "Req_LnJ_RxStateDone", 7, 1 },
+ { "Req_LnJ_RxStateReq", 6, 1 },
+ { "Req_LnJ_RxPwrState", 4, 2 },
+ { "Req_LnI_RxStateDone", 3, 1 },
+ { "Req_LnI_RxStateReq", 2, 1 },
+ { "Req_LnI_RxPwrState", 0, 2 },
+ { "PCIE_PHY_CURRXPWR1", 0x5c20, 0 },
+ { "Cur_LnP_RxPwrState", 28, 3 },
+ { "Cur_LnO_RxPwrState", 24, 3 },
+ { "Cur_LnN_RxPwrState", 20, 3 },
+ { "Cur_LnM_RxPwrState", 16, 3 },
+ { "Cur_LnL_RxPwrState", 12, 3 },
+ { "Cur_LnK_RxPwrState", 8, 3 },
+ { "Cur_LnJ_RxPwrState", 4, 3 },
+ { "Cur_LnI_RxPwrState", 0, 3 },
+ { "PCIE_PHY_GEN3_AE2", 0x5c24, 0 },
+ { "LnL_STAT", 28, 3 },
+ { "LnL_CMD", 24, 3 },
+ { "LnK_STAT", 20, 3 },
+ { "LnK_CMD", 16, 3 },
+ { "LnJ_STAT", 12, 3 },
+ { "LnJ_CMD", 8, 3 },
+ { "LnI_STAT", 4, 3 },
+ { "LnI_CMD", 0, 3 },
+ { "PCIE_PHY_GEN3_AE3", 0x5c28, 0 },
+ { "LnP_STAT", 28, 3 },
+ { "LnP_CMD", 24, 3 },
+ { "LnO_STAT", 20, 3 },
+ { "LnO_CMD", 16, 3 },
+ { "LnN_STAT", 12, 3 },
+ { "LnN_CMD", 8, 3 },
+ { "LnM_STAT", 4, 3 },
+ { "LnM_CMD", 0, 3 },
+ { "PCIE_PHY_FS_LF4", 0x5c2c, 0 },
+ { "Lane9LF", 24, 6 },
+ { "Lane9FS", 16, 6 },
+ { "Lane8LF", 8, 6 },
+ { "Lane8FS", 0, 6 },
+ { "PCIE_PHY_FS_LF5", 0x5c30, 0 },
+ { "Lane11LF", 24, 6 },
+ { "Lane11FS", 16, 6 },
+ { "Lane10LF", 8, 6 },
+ { "Lane10FS", 0, 6 },
+ { "PCIE_PHY_FS_LF6", 0x5c34, 0 },
+ { "Lane13LF", 24, 6 },
+ { "Lane13FS", 16, 6 },
+ { "Lane12LF", 8, 6 },
+ { "Lane12FS", 0, 6 },
+ { "PCIE_PHY_FS_LF7", 0x5c38, 0 },
+ { "Lane15LF", 24, 6 },
+ { "Lane15FS", 16, 6 },
+ { "Lane14LF", 8, 6 },
+ { "Lane14FS", 0, 6 },
+ { "PCIE_MULTI_PHY_INDIR_REQ", 0x5c3c, 0 },
+ { "Phy_Reg_Enable", 31, 1 },
+ { "Phy_Reg_Select", 22, 2 },
+ { "Phy_Reg_RegAddr", 0, 16 },
+ { "PCIE_MULTI_PHY_INDIR_DATA", 0x5c40, 0 },
+ { "PCIE_VF_INT_INDIR_REQ", 0x5c44, 0 },
+ { "Enable", 24, 1 },
+ { "AI", 23, 1 },
+ { "VFID", 0, 10 },
+ { "PCIE_VF_INT_INDIR_DATA", 0x5c48, 0 },
+ { "VecNum", 12, 10 },
+ { "VecBase", 0, 11 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c4c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c50, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c54, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c58, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c5c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c60, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c64, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c68, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c6c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c70, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c74, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c78, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c7c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c80, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c84, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c88, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c8c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c90, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c94, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c98, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5c9c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5ca0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5ca4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5ca8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cac, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cb0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cb4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cb8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cbc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cc0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cc4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cc8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5ccc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cd0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cd4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cd8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cdc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5ce0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5ce4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5ce8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cec, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cf0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cf4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cf8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5cfc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d00, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d04, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d08, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d0c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d10, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d14, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d18, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d1c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d20, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d24, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d28, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d2c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d30, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d34, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d38, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d3c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d40, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d44, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d48, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d4c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d50, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d54, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d58, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d5c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d60, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d64, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d68, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d6c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d70, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d74, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d78, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d7c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d80, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d84, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d88, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d8c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d90, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d94, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d98, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5d9c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5da0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5da4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5da8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dac, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5db0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5db4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5db8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dbc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dc0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dc4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dc8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dcc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dd0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dd4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dd8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5ddc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5de0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5de4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5de8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dec, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5df0, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5df4, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5df8, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5dfc, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e00, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e04, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e08, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e0c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e10, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e14, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e18, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e1c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e20, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e24, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e28, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e2c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e30, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e34, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e38, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e3c, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e40, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e44, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_256_INT_CFG2", 0x5e48, 0 },
+ { "SendFLRRsp", 31, 1 },
+ { "ImmFLRRsp", 24, 1 },
+ { "TxnDisable", 20, 1 },
+ { "PCIE_VF_MSI_EN_4", 0x5e50, 0 },
+ { "PCIE_VF_MSI_EN_5", 0x5e54, 0 },
+ { "PCIE_VF_MSI_EN_6", 0x5e58, 0 },
+ { "PCIE_VF_MSI_EN_7", 0x5e5c, 0 },
+ { "PCIE_VF_MSIX_EN_4", 0x5e60, 0 },
+ { "PCIE_VF_MSIX_EN_5", 0x5e64, 0 },
+ { "PCIE_VF_MSIX_EN_6", 0x5e68, 0 },
+ { "PCIE_VF_MSIX_EN_7", 0x5e6c, 0 },
+ { "PCIE_FLR_VF4_STATUS", 0x5e70, 0 },
+ { "PCIE_FLR_VF5_STATUS", 0x5e74, 0 },
+ { "PCIE_FLR_VF6_STATUS", 0x5e78, 0 },
+ { "PCIE_FLR_VF7_STATUS", 0x5e7c, 0 },
+ { "PCIE_BUS_MST_STAT_4", 0x5e80, 0 },
+ { "PCIE_BUS_MST_STAT_5", 0x5e84, 0 },
+ { "PCIE_BUS_MST_STAT_6", 0x5e88, 0 },
+ { "PCIE_BUS_MST_STAT_7", 0x5e8c, 0 },
+ { "PCIE_BUS_MST_STAT_8", 0x5e90, 0 },
+ { "PCIE_TGT_SKID_FIFO", 0x5e94, 0 },
+ { "HdrFreeCnt", 16, 12 },
+ { "DataFreeCnt", 0, 12 },
+ { "PCIE_RSP_ERR_STAT_4", 0x5ea0, 0 },
+ { "PCIE_RSP_ERR_STAT_5", 0x5ea4, 0 },
+ { "PCIE_RSP_ERR_STAT_6", 0x5ea8, 0 },
+ { "PCIE_RSP_ERR_STAT_7", 0x5eac, 0 },
+ { "PCIE_RSP_ERR_STAT_8", 0x5eb0, 0 },
+ { "PCIE_PHY_STAT1", 0x5ec0, 0 },
+ { "PHY0_RTune_Ack", 31, 1 },
+ { "PHY1_RTune_Ack", 30, 1 },
+ { "PCIE_PHY_CTRL1", 0x5ec4, 0 },
+ { "PHY0_RTune_Req", 31, 1 },
+ { "PHY1_RTune_Req", 30, 1 },
+ { "TxDeemph_gen1", 16, 8 },
+ { "TxDeemph_gen2_3p5db", 8, 8 },
+ { "TxDeemph_gen2_6db", 0, 8 },
+ { "PCIE_PCIE_SPARE0", 0x5ec8, 0 },
+ { "PCIE_RESET_STAT", 0x5ecc, 0 },
+ { "PON_RST_STATE_flag", 11, 1 },
+ { "BUS_RST_STATE_flag", 10, 1 },
+ { "DL_DOWN_PCIeCRST_MODE0_STATE_flag", 9, 1 },
+ { "DL_DOWN_PCIeCRST_MODE1_STATE_flag", 8, 1 },
+ { "PCIe_WARM_RST_MODE0_STATE_flag", 7, 1 },
+ { "PCIe_WARM_RST_MODE1_STATE_flag", 6, 1 },
+ { "PIO_WARM_RST_MODE0_STATE_flag", 5, 1 },
+ { "PIO_WARM_RST_MODE1_STATE_flag", 4, 1 },
+ { "LastResetState", 0, 3 },
+ { "PCIE_FUNC_DSTATE", 0x5ed0, 0 },
+ { "PF7_DState", 21, 3 },
+ { "PF6_DState", 18, 3 },
+ { "PF5_DState", 15, 3 },
+ { "PF4_DState", 12, 3 },
+ { "PF3_DState", 9, 3 },
+ { "PF2_DState", 6, 3 },
+ { "PF1_DState", 3, 3 },
+ { "PF0_DState", 0, 3 },
+ { "PCIE_DEBUG_ADDR_RANGE1", 0x5ee0, 0 },
+ { "PCIE_DEBUG_ADDR_RANGE2", 0x5ef0, 0 },
+ { "PCIE_DEBUG_ADDR_RANGE_CNT", 0x5f00, 0 },
+ { NULL }
+};
+
+struct reg_info t6_dbg_regs[] = {
+ { "DBG_DBG0_CFG", 0x6000, 0 },
+ { "ModuleSelect", 12, 8 },
+ { "RegSelect", 4, 8 },
+ { "ClkSelect", 0, 4 },
+ { "DBG_DBG0_EN", 0x6004, 0 },
+ { "SDRHalfWord0", 8, 1 },
+ { "DDREn", 4, 1 },
+ { "PortEn", 0, 1 },
+ { "DBG_DBG1_CFG", 0x6008, 0 },
+ { "ModuleSelect", 12, 8 },
+ { "RegSelect", 4, 8 },
+ { "ClkSelect", 0, 4 },
+ { "DBG_DBG1_EN", 0x600c, 0 },
+ { "Clk_en_on_dbg1", 20, 1 },
+ { "SDRHalfWord0", 8, 1 },
+ { "DDREn", 4, 1 },
+ { "PortEn", 0, 1 },
+ { "DBG_GPIO_EN", 0x6010, 0 },
+ { "GPIO15_OEn", 31, 1 },
+ { "GPIO14_OEn", 30, 1 },
+ { "GPIO13_OEn", 29, 1 },
+ { "GPIO12_OEn", 28, 1 },
+ { "GPIO11_OEn", 27, 1 },
+ { "GPIO10_OEn", 26, 1 },
+ { "GPIO9_OEn", 25, 1 },
+ { "GPIO8_OEn", 24, 1 },
+ { "GPIO7_OEn", 23, 1 },
+ { "GPIO6_OEn", 22, 1 },
+ { "GPIO5_OEn", 21, 1 },
+ { "GPIO4_OEn", 20, 1 },
+ { "GPIO3_OEn", 19, 1 },
+ { "GPIO2_OEn", 18, 1 },
+ { "GPIO1_OEn", 17, 1 },
+ { "GPIO0_OEn", 16, 1 },
+ { "GPIO15_Out_Val", 15, 1 },
+ { "GPIO14_Out_Val", 14, 1 },
+ { "GPIO13_Out_Val", 13, 1 },
+ { "GPIO12_Out_Val", 12, 1 },
+ { "GPIO11_Out_Val", 11, 1 },
+ { "GPIO10_Out_Val", 10, 1 },
+ { "GPIO9_Out_Val", 9, 1 },
+ { "GPIO8_Out_Val", 8, 1 },
+ { "GPIO7_Out_Val", 7, 1 },
+ { "GPIO6_Out_Val", 6, 1 },
+ { "GPIO5_Out_Val", 5, 1 },
+ { "GPIO4_Out_Val", 4, 1 },
+ { "GPIO3_Out_Val", 3, 1 },
+ { "GPIO2_Out_Val", 2, 1 },
+ { "GPIO1_Out_Val", 1, 1 },
+ { "GPIO0_Out_Val", 0, 1 },
+ { "DBG_GPIO_IN", 0x6014, 0 },
+ { "GPIO15_CHG_DET", 31, 1 },
+ { "GPIO14_CHG_DET", 30, 1 },
+ { "GPIO13_CHG_DET", 29, 1 },
+ { "GPIO12_CHG_DET", 28, 1 },
+ { "GPIO11_CHG_DET", 27, 1 },
+ { "GPIO10_CHG_DET", 26, 1 },
+ { "GPIO9_CHG_DET", 25, 1 },
+ { "GPIO8_CHG_DET", 24, 1 },
+ { "GPIO7_CHG_DET", 23, 1 },
+ { "GPIO6_CHG_DET", 22, 1 },
+ { "GPIO5_CHG_DET", 21, 1 },
+ { "GPIO4_CHG_DET", 20, 1 },
+ { "GPIO3_CHG_DET", 19, 1 },
+ { "GPIO2_CHG_DET", 18, 1 },
+ { "GPIO1_CHG_DET", 17, 1 },
+ { "GPIO0_CHG_DET", 16, 1 },
+ { "GPIO15_IN", 15, 1 },
+ { "GPIO14_IN", 14, 1 },
+ { "GPIO13_IN", 13, 1 },
+ { "GPIO12_IN", 12, 1 },
+ { "GPIO11_IN", 11, 1 },
+ { "GPIO10_IN", 10, 1 },
+ { "GPIO9_IN", 9, 1 },
+ { "GPIO8_IN", 8, 1 },
+ { "GPIO7_IN", 7, 1 },
+ { "GPIO6_IN", 6, 1 },
+ { "GPIO5_IN", 5, 1 },
+ { "GPIO4_IN", 4, 1 },
+ { "GPIO3_IN", 3, 1 },
+ { "GPIO2_IN", 2, 1 },
+ { "GPIO1_IN", 1, 1 },
+ { "GPIO0_IN", 0, 1 },
+ { "DBG_GPIO_EN_NEW", 0x6100, 0 },
+ { "GPIO16_OEn", 7, 1 },
+ { "GPIO17_OEn", 6, 1 },
+ { "GPIO18_OEn", 5, 1 },
+ { "GPIO19_OEn", 4, 1 },
+ { "GPIO16_Out_Val", 3, 1 },
+ { "GPIO17_Out_Val", 2, 1 },
+ { "GPIO18_Out_Val", 1, 1 },
+ { "GPIO19_Out_Val", 0, 1 },
+ { "DBG_GPIO_IN_NEW", 0x6104, 0 },
+ { "GPIO16_CHG_DET", 7, 1 },
+ { "GPIO17_CHG_DET", 6, 1 },
+ { "GPIO18_CHG_DET", 5, 1 },
+ { "GPIO19_CHG_DET", 4, 1 },
+ { "GPIO19_IN", 3, 1 },
+ { "GPIO18_IN", 2, 1 },
+ { "GPIO17_IN", 1, 1 },
+ { "GPIO16_IN", 0, 1 },
+ { "DBG_INT_ENABLE", 0x6018, 0 },
+ { "GPIO19", 29, 1 },
+ { "GPIO18", 28, 1 },
+ { "GPIO17", 27, 1 },
+ { "GPIO16", 26, 1 },
+ { "IBM_FDL_FAIL_int_enbl", 25, 1 },
+ { "pll_lock_lost_int_enbl", 22, 1 },
+ { "C_LOCK", 21, 1 },
+ { "M_LOCK", 20, 1 },
+ { "U_LOCK", 19, 1 },
+ { "PCIe_LOCK", 18, 1 },
+ { "KX_LOCK", 17, 1 },
+ { "KR_LOCK", 16, 1 },
+ { "GPIO15", 15, 1 },
+ { "GPIO14", 14, 1 },
+ { "GPIO13", 13, 1 },
+ { "GPIO12", 12, 1 },
+ { "GPIO11", 11, 1 },
+ { "GPIO10", 10, 1 },
+ { "GPIO9", 9, 1 },
+ { "GPIO8", 8, 1 },
+ { "GPIO7", 7, 1 },
+ { "GPIO6", 6, 1 },
+ { "GPIO5", 5, 1 },
+ { "GPIO4", 4, 1 },
+ { "GPIO3", 3, 1 },
+ { "GPIO2", 2, 1 },
+ { "GPIO1", 1, 1 },
+ { "GPIO0", 0, 1 },
+ { "DBG_INT_CAUSE", 0x601c, 0 },
+ { "GPIO19", 29, 1 },
+ { "GPIO18", 28, 1 },
+ { "GPIO17", 27, 1 },
+ { "GPIO16", 26, 1 },
+ { "IBM_FDL_FAIL_int_cause", 25, 1 },
+ { "pll_lock_lost_int_cause", 22, 1 },
+ { "C_LOCK", 21, 1 },
+ { "M_LOCK", 20, 1 },
+ { "U_LOCK", 19, 1 },
+ { "PCIe_LOCK", 18, 1 },
+ { "KX_LOCK", 17, 1 },
+ { "KR_LOCK", 16, 1 },
+ { "GPIO15", 15, 1 },
+ { "GPIO14", 14, 1 },
+ { "GPIO13", 13, 1 },
+ { "GPIO12", 12, 1 },
+ { "GPIO11", 11, 1 },
+ { "GPIO10", 10, 1 },
+ { "GPIO9", 9, 1 },
+ { "GPIO8", 8, 1 },
+ { "GPIO7", 7, 1 },
+ { "GPIO6", 6, 1 },
+ { "GPIO5", 5, 1 },
+ { "GPIO4", 4, 1 },
+ { "GPIO3", 3, 1 },
+ { "GPIO2", 2, 1 },
+ { "GPIO1", 1, 1 },
+ { "GPIO0", 0, 1 },
+ { "DBG_DBG0_RST_VALUE", 0x6020, 0 },
+ { "DBG_PLL_OCLK_PAD_EN", 0x6028, 0 },
+ { "PCIE_OCLK_En", 20, 1 },
+ { "KX_OCLK_En", 16, 1 },
+ { "U_OCLK_En", 12, 1 },
+ { "KR_OCLK_En", 8, 1 },
+ { "M_OCLK_En", 4, 1 },
+ { "C_OCLK_En", 0, 1 },
+ { "DBG_PLL_LOCK", 0x602c, 0 },
+ { "P_LOCK", 20, 1 },
+ { "KX_LOCK", 16, 1 },
+ { "U_LOCK", 12, 1 },
+ { "KR_LOCK", 8, 1 },
+ { "M_LOCK", 4, 1 },
+ { "C_LOCK", 0, 1 },
+ { "DBG_GPIO_ACT_LOW", 0x6030, 0 },
+ { "GPIO19_ACT_LOW", 25, 1 },
+ { "GPIO18_ACT_LOW", 24, 1 },
+ { "GPIO17_ACT_LOW", 23, 1 },
+ { "GPIO16_ACT_LOW", 22, 1 },
+ { "P_LOCK_ACT_LOW", 21, 1 },
+ { "C_LOCK_ACT_LOW", 20, 1 },
+ { "M_LOCK_ACT_LOW", 19, 1 },
+ { "U_LOCK_ACT_LOW", 18, 1 },
+ { "KR_LOCK_ACT_LOW", 17, 1 },
+ { "KX_LOCK_ACT_LOW", 16, 1 },
+ { "GPIO15_ACT_LOW", 15, 1 },
+ { "GPIO14_ACT_LOW", 14, 1 },
+ { "GPIO13_ACT_LOW", 13, 1 },
+ { "GPIO12_ACT_LOW", 12, 1 },
+ { "GPIO11_ACT_LOW", 11, 1 },
+ { "GPIO10_ACT_LOW", 10, 1 },
+ { "GPIO9_ACT_LOW", 9, 1 },
+ { "GPIO8_ACT_LOW", 8, 1 },
+ { "GPIO7_ACT_LOW", 7, 1 },
+ { "GPIO6_ACT_LOW", 6, 1 },
+ { "GPIO5_ACT_LOW", 5, 1 },
+ { "GPIO4_ACT_LOW", 4, 1 },
+ { "GPIO3_ACT_LOW", 3, 1 },
+ { "GPIO2_ACT_LOW", 2, 1 },
+ { "GPIO1_ACT_LOW", 1, 1 },
+ { "GPIO0_ACT_LOW", 0, 1 },
+ { "DBG_EFUSE_BYTE0_3", 0x6034, 0 },
+ { "DBG_EFUSE_BYTE4_7", 0x6038, 0 },
+ { "DBG_EFUSE_BYTE8_11", 0x603c, 0 },
+ { "DBG_EFUSE_BYTE12_15", 0x6040, 0 },
+ { "DBG_EXTRA_STATIC_BITS_CONF", 0x6058, 0 },
+ { "STATIC_M_PLL_RESET", 30, 1 },
+ { "STATIC_M_PLL_SLEEP", 29, 1 },
+ { "STATIC_M_PLL_BYPASS", 28, 1 },
+ { "STATIC_MPLL_CLK_SEL", 27, 1 },
+ { "STATIC_U_PLL_SLEEP", 26, 1 },
+ { "STATIC_C_PLL_SLEEP", 25, 1 },
+ { "STATIC_LVDS_CLKOUT_SEL", 23, 2 },
+ { "STATIC_LVDS_CLKOUT_EN", 22, 1 },
+ { "STATIC_CCLK_FREQ_SEL", 20, 2 },
+ { "STATIC_UCLK_FREQ_SEL", 18, 2 },
+ { "ExPHYClk_sel_en", 17, 1 },
+ { "ExPHYClk_sel", 15, 2 },
+ { "STATIC_U_PLL_BYPASS", 14, 1 },
+ { "STATIC_C_PLL_BYPASS", 13, 1 },
+ { "STATIC_KR_PLL_BYPASS", 12, 1 },
+ { "STATIC_KX_PLL_BYPASS", 11, 1 },
+ { "STATIC_KX_PLL_V", 7, 4 },
+ { "STATIC_KR_PLL_V", 3, 4 },
+ { "DBG_STATIC_OCLK_MUXSEL_CONF", 0x605c, 0 },
+ { "P_OCLK_MUXSEL", 13, 4 },
+ { "M_OCLK_MUXSEL", 12, 1 },
+ { "C_OCLK_MUXSEL", 10, 2 },
+ { "U_OCLK_MUXSEL", 8, 2 },
+ { "KX_OCLK_MUXSEL", 3, 3 },
+ { "KR_OCLK_MUXSEL", 0, 3 },
+ { "DBG_TRACE0_CONF_COMPREG0", 0x6060, 0 },
+ { "DBG_TRACE0_CONF_COMPREG1", 0x6064, 0 },
+ { "DBG_TRACE1_CONF_COMPREG0", 0x6068, 0 },
+ { "DBG_TRACE1_CONF_COMPREG1", 0x606c, 0 },
+ { "DBG_TRACE0_CONF_MASKREG0", 0x6070, 0 },
+ { "DBG_TRACE0_CONF_MASKREG1", 0x6074, 0 },
+ { "DBG_TRACE1_CONF_MASKREG0", 0x6078, 0 },
+ { "DBG_TRACE1_CONF_MASKREG1", 0x607c, 0 },
+ { "DBG_TRACE_COUNTER", 0x6080, 0 },
+ { "Counter1", 16, 16 },
+ { "Counter0", 0, 16 },
+ { "DBG_STATIC_REFCLK_PERIOD", 0x6084, 0 },
+ { "DBG_TRACE_CONF", 0x6088, 0 },
+ { "dbg_trace_operate_with_trg", 5, 1 },
+ { "dbg_trace_operate_en", 4, 1 },
+ { "dbg_operate_indv_combined", 3, 1 },
+ { "dbg_operate_order_of_trigger", 2, 1 },
+ { "dbg_operate_sgl_dbl_trigger", 1, 1 },
+ { "dbg_operate0_or_1", 0, 1 },
+ { "DBG_TRACE_RDEN", 0x608c, 0 },
+ { "RD_ADDR1", 11, 9 },
+ { "RD_ADDR0", 2, 9 },
+ { "Rd_en1", 1, 1 },
+ { "Rd_en0", 0, 1 },
+ { "DBG_TRACE_WRADDR", 0x6090, 0 },
+ { "Wr_pointer_addr1", 16, 9 },
+ { "Wr_pointer_addr0", 0, 9 },
+ { "DBG_TRACE0_DATA_OUT", 0x6094, 0 },
+ { "DBG_TRACE1_DATA_OUT", 0x6098, 0 },
+ { "DBG_FUSE_SENSE_DONE", 0x609c, 0 },
+ { "PSRO_sel", 1, 4 },
+ { "FUSE_DONE_SENSE", 0, 1 },
+ { "DBG_TVSENSE_EN", 0x60a8, 0 },
+ { "MCIMPED1_out", 29, 1 },
+ { "MCIMPED2_out", 28, 1 },
+ { "TVSENSE_SNSOUT", 17, 9 },
+ { "TVSENSE_OUTPUTVALID", 16, 1 },
+ { "TVSENSE_SLEEP", 11, 1 },
+ { "TVSENSE_SENSV", 10, 1 },
+ { "TVSENSE_RST", 9, 1 },
+ { "TVSENSE_RATIO", 0, 8 },
+ { "DBG_CUST_EFUSE_OUT_EN", 0x60ac, 0 },
+ { "DBG_CUST_EFUSE_SEL1_EN", 0x60b0, 0 },
+ { "DBG_CUST_EFUSE_SEL2_EN", 0x60b4, 0 },
+ { "DBG_FEENABLE", 29, 1 },
+ { "DBG_FEF", 23, 6 },
+ { "DBG_FEMIMICN", 22, 1 },
+ { "DBG_FEGATEC", 21, 1 },
+ { "DBG_FEPROGP", 20, 1 },
+ { "DBG_FEREADCLK", 19, 1 },
+ { "DBG_FERSEL", 3, 16 },
+ { "DBG_FETIME", 0, 3 },
+ { "DBG_STATIC_M_PLL_CONF1", 0x60b8, 0 },
+ { "STATIC_M_PLL_MULTFRAC", 8, 24 },
+ { "STATIC_M_PLL_FFSLEWRATE", 0, 8 },
+ { "DBG_STATIC_M_PLL_CONF2", 0x60bc, 0 },
+ { "STATIC_M_PLL_PREDIV", 24, 6 },
+ { "STATIC_M_PLL_DCO_BYPASS", 23, 1 },
+ { "STATIC_M_PLL_SDORDER", 21, 2 },
+ { "STATIC_M_PLL_FFENABLE", 20, 1 },
+ { "STATIC_M_PLL_STOPCLKB", 19, 1 },
+ { "STATIC_M_PLL_STOPCLKA", 18, 1 },
+ { "STATIC_M_PLL_SLEEP", 17, 1 },
+ { "STATIC_M_PLL_BYPASS", 16, 1 },
+ { "STATIC_M_PLL_LOCKTUNE", 0, 5 },
+ { "DBG_STATIC_M_PLL_CONF3", 0x60c0, 0 },
+ { "STATIC_M_PLL_MULTPRE", 30, 2 },
+ { "STATIC_M_PLL_LOCKSEL", 28, 1 },
+ { "STATIC_M_PLL_FFTUNE", 12, 16 },
+ { "STATIC_M_PLL_RANGEPRE", 10, 2 },
+ { "STATIC_M_PLL_RANGEB", 5, 5 },
+ { "STATIC_M_PLL_RANGEA", 0, 5 },
+ { "DBG_STATIC_M_PLL_CONF4", 0x60c4, 0 },
+ { "DBG_STATIC_M_PLL_CONF5", 0x60c8, 0 },
+ { "STATIC_M_PLL_VCVTUNE", 24, 3 },
+ { "STATIC_M_PLL_RESET", 23, 1 },
+ { "STATIC_MPLL_REFCLK_SEL", 22, 1 },
+ { "STATIC_M_PLL_LFTUNE_32_40", 13, 9 },
+ { "STATIC_M_PLL_MULT", 0, 8 },
+ { "DBG_STATIC_M_PLL_CONF6", 0x60cc, 0 },
+ { "STATIC_M_PLL_DIVCHANGE", 30, 1 },
+ { "STATIC_M_PLL_FRAMESTOP", 29, 1 },
+ { "STATIC_M_PLL_FASTSTOP", 28, 1 },
+ { "STATIC_M_PLL_FFBYPASS", 27, 1 },
+ { "STATIC_M_PLL_STARTUP", 25, 2 },
+ { "STATIC_M_PLL_VREGTUNE", 6, 19 },
+ { "STATIC_PHY0RecRst_", 5, 1 },
+ { "STATIC_PHY1RecRst_", 4, 1 },
+ { "STATIC_SWMC0Rst_", 3, 1 },
+ { "STATIC_SWMC0CfgRst_", 2, 1 },
+ { "STATIC_SWMC1Rst_", 1, 1 },
+ { "STATIC_SWMC1CfgRst_", 0, 1 },
+ { "DBG_STATIC_C_PLL_CONF1", 0x60d0, 0 },
+ { "STATIC_C_PLL_MULTFRAC", 8, 24 },
+ { "STATIC_C_PLL_FFSLEWRATE", 0, 8 },
+ { "DBG_STATIC_C_PLL_CONF2", 0x60d4, 0 },
+ { "STATIC_C_PLL_PREDIV", 26, 6 },
+ { "STATIC_C_PLL_STARTUP", 24, 2 },
+ { "STATIC_C_PLL_DCO_BYPASS", 23, 1 },
+ { "STATIC_C_PLL_SDORDER", 21, 2 },
+ { "STATIC_C_PLL_DIVCHANGE", 20, 1 },
+ { "STATIC_C_PLL_STOPCLKB", 19, 1 },
+ { "STATIC_C_PLL_STOPCLKA", 18, 1 },
+ { "STATIC_C_PLL_SLEEP", 17, 1 },
+ { "STATIC_C_PLL_BYPASS", 16, 1 },
+ { "STATIC_C_PLL_LOCKTUNE", 0, 5 },
+ { "DBG_STATIC_C_PLL_CONF3", 0x60d8, 0 },
+ { "STATIC_C_PLL_MULTPRE", 30, 2 },
+ { "STATIC_C_PLL_LOCKSEL", 28, 1 },
+ { "STATIC_C_PLL_FFTUNE", 12, 16 },
+ { "STATIC_C_PLL_RANGEPRE", 10, 2 },
+ { "STATIC_C_PLL_RANGEB", 5, 5 },
+ { "STATIC_C_PLL_RANGEA", 0, 5 },
+ { "DBG_STATIC_C_PLL_CONF4", 0x60dc, 0 },
+ { "DBG_STATIC_C_PLL_CONF5", 0x60e0, 0 },
+ { "STATIC_C_PLL_FFBYPASS", 27, 1 },
+ { "STATIC_C_PLL_FASTSTOP", 26, 1 },
+ { "STATIC_C_PLL_FRAMESTOP", 25, 1 },
+ { "STATIC_C_PLL_VCVTUNE", 22, 3 },
+ { "STATIC_C_PLL_LFTUNE_32_40", 13, 9 },
+ { "STATIC_C_PLL_PREDIV", 8, 5 },
+ { "STATIC_C_PLL_MULT", 0, 8 },
+ { "DBG_STATIC_U_PLL_CONF1", 0x60e4, 0 },
+ { "STATIC_U_PLL_MULTFRAC", 8, 24 },
+ { "STATIC_U_PLL_FFSLEWRATE", 0, 8 },
+ { "DBG_STATIC_U_PLL_CONF2", 0x60e8, 0 },
+ { "STATIC_U_PLL_PREDIV", 26, 6 },
+ { "STATIC_U_PLL_STARTUP", 24, 2 },
+ { "STATIC_U_PLL_DCO_BYPASS", 23, 1 },
+ { "STATIC_U_PLL_SDORDER", 21, 2 },
+ { "STATIC_U_PLL_DIVCHANGE", 20, 1 },
+ { "STATIC_U_PLL_STOPCLKB", 19, 1 },
+ { "STATIC_U_PLL_STOPCLKA", 18, 1 },
+ { "STATIC_U_PLL_SLEEP", 17, 1 },
+ { "STATIC_U_PLL_BYPASS", 16, 1 },
+ { "STATIC_U_PLL_LOCKTUNE", 0, 5 },
+ { "DBG_STATIC_U_PLL_CONF3", 0x60ec, 0 },
+ { "STATIC_U_PLL_MULTPRE", 30, 2 },
+ { "STATIC_U_PLL_LOCKSEL", 28, 1 },
+ { "STATIC_U_PLL_FFTUNE", 12, 16 },
+ { "STATIC_U_PLL_RANGEPRE", 10, 2 },
+ { "STATIC_U_PLL_RANGEB", 5, 5 },
+ { "STATIC_U_PLL_RANGEA", 0, 5 },
+ { "DBG_STATIC_U_PLL_CONF4", 0x60f0, 0 },
+ { "DBG_STATIC_U_PLL_CONF5", 0x60f4, 0 },
+ { "STATIC_U_PLL_FFBYPASS", 27, 1 },
+ { "STATIC_U_PLL_FASTSTOP", 26, 1 },
+ { "STATIC_U_PLL_FRAMESTOP", 25, 1 },
+ { "STATIC_U_PLL_VCVTUNE", 22, 3 },
+ { "STATIC_U_PLL_LFTUNE_32_40", 13, 9 },
+ { "STATIC_U_PLL_PREDIV", 8, 5 },
+ { "STATIC_U_PLL_MULT", 0, 8 },
+ { "DBG_STATIC_KR_PLL_CONF1", 0x60f8, 0 },
+ { "STATIC_KR_PLL_BYPASS", 30, 1 },
+ { "STATIC_KR_PLL_VBOOSTDIV", 27, 3 },
+ { "STATIC_KR_PLL_CPISEL", 24, 3 },
+ { "STATIC_KR_PLL_CCALMETHOD", 23, 1 },
+ { "STATIC_KR_PLL_CCALLOAD", 22, 1 },
+ { "STATIC_KR_PLL_CCALFMIN", 21, 1 },
+ { "STATIC_KR_PLL_CCALFMAX", 20, 1 },
+ { "STATIC_KR_PLL_CCALCVHOLD", 19, 1 },
+ { "STATIC_KR_PLL_CCALBANDSEL", 15, 4 },
+ { "STATIC_KR_PLL_BGOFFSET", 11, 4 },
+ { "STATIC_KR_PLL_P", 8, 3 },
+ { "STATIC_KR_PLL_N2", 4, 4 },
+ { "STATIC_KR_PLL_N1", 0, 4 },
+ { "DBG_STATIC_KR_PLL_CONF2", 0x60fc, 0 },
+ { "STATIC_KR_PLL_M", 11, 9 },
+ { "STATIC_KR_PLL_ANALOGTUNE", 0, 11 },
+ { "DBG_STATIC_KX_PLL_CONF1", 0x6108, 0 },
+ { "STATIC_KX_PLL_BYPASS", 30, 1 },
+ { "STATIC_KX_PLL_VBOOSTDIV", 27, 3 },
+ { "STATIC_KX_PLL_CPISEL", 24, 3 },
+ { "STATIC_KX_PLL_CCALMETHOD", 23, 1 },
+ { "STATIC_KX_PLL_CCALLOAD", 22, 1 },
+ { "STATIC_KX_PLL_CCALFMIN", 21, 1 },
+ { "STATIC_KX_PLL_CCALFMAX", 20, 1 },
+ { "STATIC_KX_PLL_CCALCVHOLD", 19, 1 },
+ { "STATIC_KX_PLL_CCALBANDSEL", 15, 4 },
+ { "STATIC_KX_PLL_BGOFFSET", 11, 4 },
+ { "STATIC_KX_PLL_P", 8, 3 },
+ { "STATIC_KX_PLL_N2", 4, 4 },
+ { "STATIC_KX_PLL_N1", 0, 4 },
+ { "DBG_STATIC_KX_PLL_CONF2", 0x610c, 0 },
+ { "STATIC_KX_PLL_M", 11, 9 },
+ { "STATIC_KX_PLL_ANALOGTUNE", 0, 11 },
+ { "DBG_STATIC_C_DFS_CONF", 0x6110, 0 },
+ { "STATIC_C_DFS_RANGEA", 8, 5 },
+ { "STATIC_C_DFS_RANGEB", 3, 5 },
+ { "STATIC_C_DFS_FFTUNE4", 2, 1 },
+ { "STATIC_C_DFS_FFTUNE5", 1, 1 },
+ { "STATIC_C_DFS_ENABLE", 0, 1 },
+ { "DBG_STATIC_U_DFS_CONF", 0x6114, 0 },
+ { "STATIC_U_DFS_RANGEA", 8, 5 },
+ { "STATIC_U_DFS_RANGEB", 3, 5 },
+ { "STATIC_U_DFS_FFTUNE4", 2, 1 },
+ { "STATIC_U_DFS_FFTUNE5", 1, 1 },
+ { "STATIC_U_DFS_ENABLE", 0, 1 },
+ { "DBG_GPIO_PE_EN", 0x6118, 0 },
+ { "GPIO19_PE_En", 19, 1 },
+ { "GPIO18_PE_En", 18, 1 },
+ { "GPIO17_PE_En", 17, 1 },
+ { "GPIO16_PE_En", 16, 1 },
+ { "GPIO15_PE_En", 15, 1 },
+ { "GPIO14_PE_En", 14, 1 },
+ { "GPIO13_PE_En", 13, 1 },
+ { "GPIO12_PE_En", 12, 1 },
+ { "GPIO11_PE_En", 11, 1 },
+ { "GPIO10_PE_En", 10, 1 },
+ { "GPIO9_PE_En", 9, 1 },
+ { "GPIO8_PE_En", 8, 1 },
+ { "GPIO7_PE_En", 7, 1 },
+ { "GPIO6_PE_En", 6, 1 },
+ { "GPIO5_PE_En", 5, 1 },
+ { "GPIO4_PE_En", 4, 1 },
+ { "GPIO3_PE_En", 3, 1 },
+ { "GPIO2_PE_En", 2, 1 },
+ { "GPIO1_PE_En", 1, 1 },
+ { "GPIO0_PE_En", 0, 1 },
+ { "DBG_GPIO_PS_EN", 0x611c, 0 },
+ { "GPIO19_PS_En", 19, 1 },
+ { "GPIO18_PS_En", 18, 1 },
+ { "GPIO17_PS_En", 17, 1 },
+ { "GPIO16_PS_En", 16, 1 },
+ { "GPIO15_PS_En", 15, 1 },
+ { "GPIO14_PS_En", 14, 1 },
+ { "GPIO13_PS_En", 13, 1 },
+ { "GPIO12_PS_En", 12, 1 },
+ { "GPIO11_PS_En", 11, 1 },
+ { "GPIO10_PS_En", 10, 1 },
+ { "GPIO9_PS_En", 9, 1 },
+ { "GPIO8_PS_En", 8, 1 },
+ { "GPIO7_PS_En", 7, 1 },
+ { "GPIO6_PS_En", 6, 1 },
+ { "GPIO5_PS_En", 5, 1 },
+ { "GPIO4_PS_En", 4, 1 },
+ { "GPIO3_PS_En", 3, 1 },
+ { "GPIO2_PS_En", 2, 1 },
+ { "GPIO1_PS_En", 1, 1 },
+ { "GPIO0_PS_En", 0, 1 },
+ { "DBG_EFUSE_BYTE16_19", 0x6120, 0 },
+ { "DBG_EFUSE_BYTE20_23", 0x6124, 0 },
+ { "DBG_EFUSE_BYTE24_27", 0x6128, 0 },
+ { "DBG_EFUSE_BYTE28_31", 0x612c, 0 },
+ { "DBG_EFUSE_BYTE32_35", 0x6130, 0 },
+ { "DBG_EFUSE_BYTE36_39", 0x6134, 0 },
+ { "DBG_EFUSE_BYTE40_43", 0x6138, 0 },
+ { "DBG_EFUSE_BYTE44_47", 0x613c, 0 },
+ { "DBG_EFUSE_BYTE48_51", 0x6140, 0 },
+ { "DBG_EFUSE_BYTE52_55", 0x6144, 0 },
+ { "DBG_EFUSE_BYTE56_59", 0x6148, 0 },
+ { "DBG_EFUSE_BYTE60_63", 0x614c, 0 },
+ { "DBG_STATIC_U_PLL_CONF6", 0x6150, 0 },
+ { "DBG_STATIC_C_PLL_CONF6", 0x6154, 0 },
+ { "DBG_CUST_EFUSE_PROGRAM", 0x6158, 0 },
+ { "EFUSE_PROG_PERIOD", 16, 16 },
+ { "EFUSE_OPER_TYP", 14, 2 },
+ { "EFUSE_ADDR", 8, 6 },
+ { "EFUSE_DIN", 0, 8 },
+ { "DBG_CUST_EFUSE_OUT", 0x615c, 0 },
+ { "EFUSE_OPER_DONE", 8, 1 },
+ { "EFUSE_DOUT", 0, 8 },
+ { "DBG_CUST_EFUSE_BYTE0_3", 0x6160, 0 },
+ { "DBG_CUST_EFUSE_BYTE4_7", 0x6164, 0 },
+ { "DBG_CUST_EFUSE_BYTE8_11", 0x6168, 0 },
+ { "DBG_CUST_EFUSE_BYTE12_15", 0x616c, 0 },
+ { "DBG_CUST_EFUSE_BYTE16_19", 0x6170, 0 },
+ { "DBG_CUST_EFUSE_BYTE20_23", 0x6174, 0 },
+ { "DBG_CUST_EFUSE_BYTE24_27", 0x6178, 0 },
+ { "DBG_CUST_EFUSE_BYTE28_31", 0x617c, 0 },
+ { "DBG_CUST_EFUSE_BYTE32_35", 0x6180, 0 },
+ { "DBG_CUST_EFUSE_BYTE36_39", 0x6184, 0 },
+ { "DBG_CUST_EFUSE_BYTE40_43", 0x6188, 0 },
+ { "DBG_CUST_EFUSE_BYTE44_47", 0x618c, 0 },
+ { "DBG_CUST_EFUSE_BYTE48_51", 0x6190, 0 },
+ { "DBG_CUST_EFUSE_BYTE52_55", 0x6194, 0 },
+ { "DBG_CUST_EFUSE_BYTE56_59", 0x6198, 0 },
+ { "DBG_CUST_EFUSE_BYTE60_63", 0x619c, 0 },
+ { NULL }
+};
+
+struct reg_info t6_ma_regs[] = {
+ { "MA_CLIENT0_RD_LATENCY_THRESHOLD", 0x7700, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT0_WR_LATENCY_THRESHOLD", 0x7704, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT1_RD_LATENCY_THRESHOLD", 0x7708, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT1_WR_LATENCY_THRESHOLD", 0x770c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT2_RD_LATENCY_THRESHOLD", 0x7710, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT2_WR_LATENCY_THRESHOLD", 0x7714, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT3_RD_LATENCY_THRESHOLD", 0x7718, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT3_WR_LATENCY_THRESHOLD", 0x771c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT4_RD_LATENCY_THRESHOLD", 0x7720, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT4_WR_LATENCY_THRESHOLD", 0x7724, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT5_RD_LATENCY_THRESHOLD", 0x7728, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT5_WR_LATENCY_THRESHOLD", 0x772c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT6_RD_LATENCY_THRESHOLD", 0x7730, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT6_WR_LATENCY_THRESHOLD", 0x7734, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT7_RD_LATENCY_THRESHOLD", 0x7738, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT7_WR_LATENCY_THRESHOLD", 0x773c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT8_RD_LATENCY_THRESHOLD", 0x7740, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT8_WR_LATENCY_THRESHOLD", 0x7744, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT9_RD_LATENCY_THRESHOLD", 0x7748, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT9_WR_LATENCY_THRESHOLD", 0x774c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT10_RD_LATENCY_THRESHOLD", 0x7750, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT10_WR_LATENCY_THRESHOLD", 0x7754, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT11_RD_LATENCY_THRESHOLD", 0x7758, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT11_WR_LATENCY_THRESHOLD", 0x775c, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT12_RD_LATENCY_THRESHOLD", 0x7760, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_CLIENT12_WR_LATENCY_THRESHOLD", 0x7764, 0 },
+ { "THRESHOLD1", 17, 15 },
+ { "THRESHOLD1_EN", 16, 1 },
+ { "THRESHOLD0", 1, 15 },
+ { "THRESHOLD0_EN", 0, 1 },
+ { "MA_SGE_TH0_DEBUG_CNT", 0x7768, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_SGE_TH1_DEBUG_CNT", 0x776c, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_ULPTX_DEBUG_CNT", 0x7770, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_ULPRX_DEBUG_CNT", 0x7774, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_ULPTXRX_DEBUG_CNT", 0x7778, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_TP_TH0_DEBUG_CNT", 0x777c, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_TP_TH1_DEBUG_CNT", 0x7780, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_LE_DEBUG_CNT", 0x7784, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_CIM_DEBUG_CNT", 0x7788, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_PCIE_DEBUG_CNT", 0x778c, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_PMTX_DEBUG_CNT", 0x7790, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_PMRX_DEBUG_CNT", 0x7794, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_HMA_DEBUG_CNT", 0x7798, 0 },
+ { "DBG_READ_DATA_CNT", 24, 8 },
+ { "DBG_READ_REQ_CNT", 16, 8 },
+ { "DBG_WRITE_DATA_CNT", 8, 8 },
+ { "DBG_WRITE_REQ_CNT", 0, 8 },
+ { "MA_EDRAM0_BAR", 0x77c0, 0 },
+ { "EDRAM0_BASE", 16, 12 },
+ { "EDRAM0_SIZE", 0, 12 },
+ { "MA_EDRAM1_BAR", 0x77c4, 0 },
+ { "EDRAM1_BASE", 16, 12 },
+ { "EDRAM1_SIZE", 0, 12 },
+ { "MA_EXT_MEMORY0_BAR", 0x77c8, 0 },
+ { "EXT_MEM0_BASE", 16, 12 },
+ { "EXT_MEM0_SIZE", 0, 12 },
+ { "MA_HOST_MEMORY_BAR", 0x77cc, 0 },
+ { "HMA_BASE", 16, 12 },
+ { "HMA_SIZE", 0, 12 },
+ { "MA_EXT_MEM_PAGE_SIZE", 0x77d0, 0 },
+ { "BRBC_MODE", 4, 1 },
+ { "BRC_MODE", 3, 1 },
+ { "EXT_MEM_PAGE_SIZE", 0, 3 },
+ { "MA_ARB_CTRL", 0x77d4, 0 },
+ { "HMA_WRT_EN", 26, 1 },
+ { "HMA_NUM_PG_128B_FDBK", 21, 5 },
+ { "HMA_DIS_128B_PG_CNT_FDBK", 20, 1 },
+ { "HMA_DIS_BG_ARB", 19, 1 },
+ { "HMA_DIS_BANK_FAIR", 18, 1 },
+ { "HMA_DIS_PAGE_HINT", 17, 1 },
+ { "HMA_DIS_ADV_ARB", 16, 1 },
+ { "NUM_PG_128B_FDBK", 5, 5 },
+ { "DIS_128B_PG_CNT_FDBK", 4, 1 },
+ { "DIS_BG_ARB", 3, 1 },
+ { "DIS_BANK_FAIR", 2, 1 },
+ { "DIS_PAGE_HINT", 1, 1 },
+ { "DIS_ADV_ARB", 0, 1 },
+ { "MA_TARGET_MEM_ENABLE", 0x77d8, 0 },
+ { "MC_SPLIT", 6, 1 },
+ { "HMA_MUX", 5, 1 },
+ { "EXT_MEM1_ENABLE", 4, 1 },
+ { "HMA_ENABLE", 3, 1 },
+ { "EXT_MEM0_ENABLE", 2, 1 },
+ { "EDRAM1_ENABLE", 1, 1 },
+ { "EDRAM0_ENABLE", 0, 1 },
+ { "MA_INT_ENABLE", 0x77dc, 0 },
+ { "MEM_TO_INT_ENABLE", 2, 1 },
+ { "MEM_PERR_INT_ENABLE", 1, 1 },
+ { "MEM_WRAP_INT_ENABLE", 0, 1 },
+ { "MA_INT_CAUSE", 0x77e0, 0 },
+ { "MEM_TO_INT_CAUSE", 2, 1 },
+ { "MEM_PERR_INT_CAUSE", 1, 1 },
+ { "MEM_WRAP_INT_CAUSE", 0, 1 },
+ { "MA_INT_WRAP_STATUS", 0x77e4, 0 },
+ { "MEM_WRAP_ADDRESS", 4, 28 },
+ { "MEM_WRAP_CLIENT_NUM", 0, 4 },
+ { "MA_TP_THREAD1_MAPPER", 0x77e8, 0 },
+ { "MA_SGE_THREAD1_MAPPER", 0x77ec, 0 },
+ { "MA_PARITY_ERROR_ENABLE1", 0x77f0, 0 },
+ { "TP_DMARBT_PAR_ERROR_EN", 31, 1 },
+ { "LOGIC_FIFO_PAR_ERROR_EN", 30, 1 },
+ { "ARB3_PAR_WRQUEUE_ERROR_EN", 29, 1 },
+ { "ARB2_PAR_WRQUEUE_ERROR_EN", 28, 1 },
+ { "ARB1_PAR_WRQUEUE_ERROR_EN", 27, 1 },
+ { "ARB0_PAR_WRQUEUE_ERROR_EN", 26, 1 },
+ { "ARB3_PAR_RDQUEUE_ERROR_EN", 25, 1 },
+ { "ARB2_PAR_RDQUEUE_ERROR_EN", 24, 1 },
+ { "ARB1_PAR_RDQUEUE_ERROR_EN", 23, 1 },
+ { "ARB0_PAR_RDQUEUE_ERROR_EN", 22, 1 },
+ { "CL10_PAR_WRQUEUE_ERROR_EN", 21, 1 },
+ { "CL9_PAR_WRQUEUE_ERROR_EN", 20, 1 },
+ { "CL8_PAR_WRQUEUE_ERROR_EN", 19, 1 },
+ { "CL7_PAR_WRQUEUE_ERROR_EN", 18, 1 },
+ { "CL6_PAR_WRQUEUE_ERROR_EN", 17, 1 },
+ { "CL5_PAR_WRQUEUE_ERROR_EN", 16, 1 },
+ { "CL4_PAR_WRQUEUE_ERROR_EN", 15, 1 },
+ { "CL3_PAR_WRQUEUE_ERROR_EN", 14, 1 },
+ { "CL2_PAR_WRQUEUE_ERROR_EN", 13, 1 },
+ { "CL1_PAR_WRQUEUE_ERROR_EN", 12, 1 },
+ { "CL0_PAR_WRQUEUE_ERROR_EN", 11, 1 },
+ { "CL10_PAR_RDQUEUE_ERROR_EN", 10, 1 },
+ { "CL9_PAR_RDQUEUE_ERROR_EN", 9, 1 },
+ { "CL8_PAR_RDQUEUE_ERROR_EN", 8, 1 },
+ { "CL7_PAR_RDQUEUE_ERROR_EN", 7, 1 },
+ { "CL6_PAR_RDQUEUE_ERROR_EN", 6, 1 },
+ { "CL5_PAR_RDQUEUE_ERROR_EN", 5, 1 },
+ { "CL4_PAR_RDQUEUE_ERROR_EN", 4, 1 },
+ { "CL3_PAR_RDQUEUE_ERROR_EN", 3, 1 },
+ { "CL2_PAR_RDQUEUE_ERROR_EN", 2, 1 },
+ { "CL1_PAR_RDQUEUE_ERROR_EN", 1, 1 },
+ { "CL0_PAR_RDQUEUE_ERROR_EN", 0, 1 },
+ { "MA_PARITY_ERROR_STATUS1", 0x77f4, 0 },
+ { "TP_DMARBT_PAR_ERROR", 31, 1 },
+ { "LOGIC_FIFO_PAR_ERROR", 30, 1 },
+ { "ARB3_PAR_WRQUEUE_ERROR", 29, 1 },
+ { "ARB2_PAR_WRQUEUE_ERROR", 28, 1 },
+ { "ARB1_PAR_WRQUEUE_ERROR", 27, 1 },
+ { "ARB0_PAR_WRQUEUE_ERROR", 26, 1 },
+ { "ARB3_PAR_RDQUEUE_ERROR", 25, 1 },
+ { "ARB2_PAR_RDQUEUE_ERROR", 24, 1 },
+ { "ARB1_PAR_RDQUEUE_ERROR", 23, 1 },
+ { "ARB0_PAR_RDQUEUE_ERROR", 22, 1 },
+ { "CL10_PAR_WRQUEUE_ERROR", 21, 1 },
+ { "CL9_PAR_WRQUEUE_ERROR", 20, 1 },
+ { "CL8_PAR_WRQUEUE_ERROR", 19, 1 },
+ { "CL7_PAR_WRQUEUE_ERROR", 18, 1 },
+ { "CL6_PAR_WRQUEUE_ERROR", 17, 1 },
+ { "CL5_PAR_WRQUEUE_ERROR", 16, 1 },
+ { "CL4_PAR_WRQUEUE_ERROR", 15, 1 },
+ { "CL3_PAR_WRQUEUE_ERROR", 14, 1 },
+ { "CL2_PAR_WRQUEUE_ERROR", 13, 1 },
+ { "CL1_PAR_WRQUEUE_ERROR", 12, 1 },
+ { "CL0_PAR_WRQUEUE_ERROR", 11, 1 },
+ { "CL10_PAR_RDQUEUE_ERROR", 10, 1 },
+ { "CL9_PAR_RDQUEUE_ERROR", 9, 1 },
+ { "CL8_PAR_RDQUEUE_ERROR", 8, 1 },
+ { "CL7_PAR_RDQUEUE_ERROR", 7, 1 },
+ { "CL6_PAR_RDQUEUE_ERROR", 6, 1 },
+ { "CL5_PAR_RDQUEUE_ERROR", 5, 1 },
+ { "CL4_PAR_RDQUEUE_ERROR", 4, 1 },
+ { "CL3_PAR_RDQUEUE_ERROR", 3, 1 },
+ { "CL2_PAR_RDQUEUE_ERROR", 2, 1 },
+ { "CL1_PAR_RDQUEUE_ERROR", 1, 1 },
+ { "CL0_PAR_RDQUEUE_ERROR", 0, 1 },
+ { "MA_SGE_PCIE_COHERANCY_CTRL", 0x77f8, 0 },
+ { "BONUS_REG", 6, 26 },
+ { "COHERANCY_CMD_TYPE", 4, 2 },
+ { "COHERANCY_THREAD_NUM", 1, 3 },
+ { "COHERANCY_ENABLE", 0, 1 },
+ { "MA_ERROR_ENABLE", 0x77fc, 0 },
+ { "FUTURE_EXPANSION_EE", 1, 31 },
+ { "UE_ENABLE", 0, 1 },
+ { "MA_PARITY_ERROR_ENABLE2", 0x7800, 0 },
+ { "ARB4_PAR_WRQUEUE_ERROR_EN", 1, 1 },
+ { "ARB4_PAR_RDQUEUE_ERROR_EN", 0, 1 },
+ { "MA_PARITY_ERROR_STATUS2", 0x7804, 0 },
+ { "ARB4_PAR_WRQUEUE_ERROR", 1, 1 },
+ { "ARB4_PAR_RDQUEUE_ERROR", 0, 1 },
+ { "MA_EXT_MEMORY1_BAR", 0x7808, 0 },
+ { "EXT_MEM1_BASE", 16, 12 },
+ { "EXT_MEM1_SIZE", 0, 12 },
+ { "MA_PMTX_THROTTLE", 0x780c, 0 },
+ { "FL_ENABLE", 31, 1 },
+ { "FL_LIMIT", 0, 8 },
+ { "MA_PMRX_THROTTLE", 0x7810, 0 },
+ { "FL_ENABLE", 31, 1 },
+ { "FL_LIMIT", 0, 8 },
+ { "MA_SGE_TH0_WRDATA_CNT", 0x7814, 0 },
+ { "MA_SGE_TH1_WRDATA_CNT", 0x7818, 0 },
+ { "MA_ULPTX_WRDATA_CNT", 0x781c, 0 },
+ { "MA_ULPRX_WRDATA_CNT", 0x7820, 0 },
+ { "MA_ULPTXRX_WRDATA_CNT", 0x7824, 0 },
+ { "MA_TP_TH0_WRDATA_CNT", 0x7828, 0 },
+ { "MA_TP_TH1_WRDATA_CNT", 0x782c, 0 },
+ { "MA_LE_WRDATA_CNT", 0x7830, 0 },
+ { "MA_CIM_WRDATA_CNT", 0x7834, 0 },
+ { "MA_PCIE_WRDATA_CNT", 0x7838, 0 },
+ { "MA_PMTX_WRDATA_CNT", 0x783c, 0 },
+ { "MA_PMRX_WRDATA_CNT", 0x7840, 0 },
+ { "MA_HMA_WRDATA_CNT", 0x7844, 0 },
+ { "MA_SGE_TH0_RDDATA_CNT", 0x7848, 0 },
+ { "MA_SGE_TH1_RDDATA_CNT", 0x784c, 0 },
+ { "MA_ULPTX_RDDATA_CNT", 0x7850, 0 },
+ { "MA_ULPRX_RDDATA_CNT", 0x7854, 0 },
+ { "MA_ULPTXRX_RDDATA_CNT", 0x7858, 0 },
+ { "MA_TP_TH0_RDDATA_CNT", 0x785c, 0 },
+ { "MA_TP_TH1_RDDATA_CNT", 0x7860, 0 },
+ { "MA_LE_RDDATA_CNT", 0x7864, 0 },
+ { "MA_CIM_RDDATA_CNT", 0x7868, 0 },
+ { "MA_PCIE_RDDATA_CNT", 0x786c, 0 },
+ { "MA_PMTX_RDDATA_CNT", 0x7870, 0 },
+ { "MA_PMRX_RDDATA_CNT", 0x7874, 0 },
+ { "MA_HMA_RDDATA_CNT", 0x7878, 0 },
+ { "MA_EXIT_ADDR_FAULT", 0x787c, 0 },
+ { "MA_DDR_DEVICE_CFG", 0x7880, 0 },
+ { "MEM_WIDTH", 1, 3 },
+ { "DDR_MODE", 0, 1 },
+ { "MA_TIMEOUT_CFG", 0x78cc, 0 },
+ { "CLR", 31, 1 },
+ { "CNT_LOCK", 30, 1 },
+ { "WRN", 24, 1 },
+ { "DIR", 23, 1 },
+ { "TYPE", 22, 1 },
+ { "CLIENT", 16, 4 },
+ { "DELAY", 0, 16 },
+ { "MA_TIMEOUT_CNT", 0x78d0, 0 },
+ { "DIR", 23, 1 },
+ { "TYPE", 22, 1 },
+ { "CLIENT", 16, 4 },
+ { "CNT_VAL", 0, 16 },
+ { "MA_WRITE_TIMEOUT_ERROR_ENABLE", 0x78d4, 0 },
+ { "FUTURE_CEXPANSION_WTE", 29, 3 },
+ { "CL12_WR_CMD_TO_EN", 28, 1 },
+ { "CL11_WR_CMD_TO_EN", 27, 1 },
+ { "CL10_WR_CMD_TO_EN", 26, 1 },
+ { "CL9_WR_CMD_TO_EN", 25, 1 },
+ { "CL8_WR_CMD_TO_EN", 24, 1 },
+ { "CL7_WR_CMD_TO_EN", 23, 1 },
+ { "CL6_WR_CMD_TO_EN", 22, 1 },
+ { "CL5_WR_CMD_TO_EN", 21, 1 },
+ { "CL4_WR_CMD_TO_EN", 20, 1 },
+ { "CL3_WR_CMD_TO_EN", 19, 1 },
+ { "CL2_WR_CMD_TO_EN", 18, 1 },
+ { "CL1_WR_CMD_TO_EN", 17, 1 },
+ { "CL0_WR_CMD_TO_EN", 16, 1 },
+ { "FUTURE_DEXPANSION_WTE", 13, 3 },
+ { "CL12_WR_DATA_TO_EN", 12, 1 },
+ { "CL11_WR_DATA_TO_EN", 11, 1 },
+ { "CL10_WR_DATA_TO_EN", 10, 1 },
+ { "CL9_WR_DATA_TO_EN", 9, 1 },
+ { "CL8_WR_DATA_TO_EN", 8, 1 },
+ { "CL7_WR_DATA_TO_EN", 7, 1 },
+ { "CL6_WR_DATA_TO_EN", 6, 1 },
+ { "CL5_WR_DATA_TO_EN", 5, 1 },
+ { "CL4_WR_DATA_TO_EN", 4, 1 },
+ { "CL3_WR_DATA_TO_EN", 3, 1 },
+ { "CL2_WR_DATA_TO_EN", 2, 1 },
+ { "CL1_WR_DATA_TO_EN", 1, 1 },
+ { "CL0_WR_DATA_TO_EN", 0, 1 },
+ { "MA_WRITE_TIMEOUT_ERROR_STATUS", 0x78d8, 0 },
+ { "FUTURE_CEXPANSION_WTS", 29, 3 },
+ { "CL12_WR_CMD_TO_ERROR", 28, 1 },
+ { "CL11_WR_CMD_TO_ERROR", 27, 1 },
+ { "CL10_WR_CMD_TO_ERROR", 26, 1 },
+ { "CL9_WR_CMD_TO_ERROR", 25, 1 },
+ { "CL8_WR_CMD_TO_ERROR", 24, 1 },
+ { "CL7_WR_CMD_TO_ERROR", 23, 1 },
+ { "CL6_WR_CMD_TO_ERROR", 22, 1 },
+ { "CL5_WR_CMD_TO_ERROR", 21, 1 },
+ { "CL4_WR_CMD_TO_ERROR", 20, 1 },
+ { "CL3_WR_CMD_TO_ERROR", 19, 1 },
+ { "CL2_WR_CMD_TO_ERROR", 18, 1 },
+ { "CL1_WR_CMD_TO_ERROR", 17, 1 },
+ { "CL0_WR_CMD_TO_ERROR", 16, 1 },
+ { "FUTURE_DEXPANSION_WTS", 13, 3 },
+ { "CL12_WR_DATA_TO_ERROR", 12, 1 },
+ { "CL11_WR_DATA_TO_ERROR", 11, 1 },
+ { "CL10_WR_DATA_TO_ERROR", 10, 1 },
+ { "CL9_WR_DATA_TO_ERROR", 9, 1 },
+ { "CL8_WR_DATA_TO_ERROR", 8, 1 },
+ { "CL7_WR_DATA_TO_ERROR", 7, 1 },
+ { "CL6_WR_DATA_TO_ERROR", 6, 1 },
+ { "CL5_WR_DATA_TO_ERROR", 5, 1 },
+ { "CL4_WR_DATA_TO_ERROR", 4, 1 },
+ { "CL3_WR_DATA_TO_ERROR", 3, 1 },
+ { "CL2_WR_DATA_TO_ERROR", 2, 1 },
+ { "CL1_WR_DATA_TO_ERROR", 1, 1 },
+ { "CL0_WR_DATA_TO_ERROR", 0, 1 },
+ { "MA_READ_TIMEOUT_ERROR_ENABLE", 0x78dc, 0 },
+ { "FUTURE_CEXPANSION_RTE", 29, 3 },
+ { "CL12_RD_CMD_TO_EN", 28, 1 },
+ { "CL11_RD_CMD_TO_EN", 27, 1 },
+ { "CL10_RD_CMD_TO_EN", 26, 1 },
+ { "CL9_RD_CMD_TO_EN", 25, 1 },
+ { "CL8_RD_CMD_TO_EN", 24, 1 },
+ { "CL7_RD_CMD_TO_EN", 23, 1 },
+ { "CL6_RD_CMD_TO_EN", 22, 1 },
+ { "CL5_RD_CMD_TO_EN", 21, 1 },
+ { "CL4_RD_CMD_TO_EN", 20, 1 },
+ { "CL3_RD_CMD_TO_EN", 19, 1 },
+ { "CL2_RD_CMD_TO_EN", 18, 1 },
+ { "CL1_RD_CMD_TO_EN", 17, 1 },
+ { "CL0_RD_CMD_TO_EN", 16, 1 },
+ { "FUTURE_DEXPANSION_RTE", 13, 3 },
+ { "CL12_RD_DATA_TO_EN", 12, 1 },
+ { "CL11_RD_DATA_TO_EN", 11, 1 },
+ { "CL10_RD_DATA_TO_EN", 10, 1 },
+ { "CL9_RD_DATA_TO_EN", 9, 1 },
+ { "CL8_RD_DATA_TO_EN", 8, 1 },
+ { "CL7_RD_DATA_TO_EN", 7, 1 },
+ { "CL6_RD_DATA_TO_EN", 6, 1 },
+ { "CL5_RD_DATA_TO_EN", 5, 1 },
+ { "CL4_RD_DATA_TO_EN", 4, 1 },
+ { "CL3_RD_DATA_TO_EN", 3, 1 },
+ { "CL2_RD_DATA_TO_EN", 2, 1 },
+ { "CL1_RD_DATA_TO_EN", 1, 1 },
+ { "CL0_RD_DATA_TO_EN", 0, 1 },
+ { "MA_READ_TIMEOUT_ERROR_STATUS", 0x78e0, 0 },
+ { "FUTURE_CEXPANSION_RTS", 29, 3 },
+ { "CL12_RD_CMD_TO_ERROR", 28, 1 },
+ { "CL11_RD_CMD_TO_ERROR", 27, 1 },
+ { "CL10_RD_CMD_TO_ERROR", 26, 1 },
+ { "CL9_RD_CMD_TO_ERROR", 25, 1 },
+ { "CL8_RD_CMD_TO_ERROR", 24, 1 },
+ { "CL7_RD_CMD_TO_ERROR", 23, 1 },
+ { "CL6_RD_CMD_TO_ERROR", 22, 1 },
+ { "CL5_RD_CMD_TO_ERROR", 21, 1 },
+ { "CL4_RD_CMD_TO_ERROR", 20, 1 },
+ { "CL3_RD_CMD_TO_ERROR", 19, 1 },
+ { "CL2_RD_CMD_TO_ERROR", 18, 1 },
+ { "CL1_RD_CMD_TO_ERROR", 17, 1 },
+ { "CL0_RD_CMD_TO_ERROR", 16, 1 },
+ { "FUTURE_DEXPANSION_RTS", 13, 3 },
+ { "CL12_RD_DATA_TO_ERROR", 12, 1 },
+ { "CL11_RD_DATA_TO_ERROR", 11, 1 },
+ { "CL10_RD_DATA_TO_ERROR", 10, 1 },
+ { "CL9_RD_DATA_TO_ERROR", 9, 1 },
+ { "CL8_RD_DATA_TO_ERROR", 8, 1 },
+ { "CL7_RD_DATA_TO_ERROR", 7, 1 },
+ { "CL6_RD_DATA_TO_ERROR", 6, 1 },
+ { "CL5_RD_DATA_TO_ERROR", 5, 1 },
+ { "CL4_RD_DATA_TO_ERROR", 4, 1 },
+ { "CL3_RD_DATA_TO_ERROR", 3, 1 },
+ { "CL2_RD_DATA_TO_ERROR", 2, 1 },
+ { "CL1_RD_DATA_TO_ERROR", 1, 1 },
+ { "CL0_RD_DATA_TO_ERROR", 0, 1 },
+ { "MA_BKP_CNT_SEL", 0x78e4, 0 },
+ { "TYPE", 30, 2 },
+ { "CLIENT", 24, 4 },
+ { "MA_BKP_CNT", 0x78e8, 0 },
+ { "MA_WRT_ARB", 0x78ec, 0 },
+ { "WRT_EN", 31, 1 },
+ { "WR_TIM", 16, 8 },
+ { "RD_WIN", 8, 8 },
+ { "WR_WIN", 0, 8 },
+ { "MA_IF_PARITY_ERROR_ENABLE", 0x78f0, 0 },
+ { "FUTURE_DEXPANSION_IPE", 13, 19 },
+ { "CL12_IF_PAR_EN", 12, 1 },
+ { "CL11_IF_PAR_EN", 11, 1 },
+ { "CL10_IF_PAR_EN", 10, 1 },
+ { "CL9_IF_PAR_EN", 9, 1 },
+ { "CL8_IF_PAR_EN", 8, 1 },
+ { "CL7_IF_PAR_EN", 7, 1 },
+ { "CL6_IF_PAR_EN", 6, 1 },
+ { "CL5_IF_PAR_EN", 5, 1 },
+ { "CL4_IF_PAR_EN", 4, 1 },
+ { "CL3_IF_PAR_EN", 3, 1 },
+ { "CL2_IF_PAR_EN", 2, 1 },
+ { "CL1_IF_PAR_EN", 1, 1 },
+ { "CL0_IF_PAR_EN", 0, 1 },
+ { "MA_IF_PARITY_ERROR_STATUS", 0x78f4, 0 },
+ { "FUTURE_DEXPANSION_IPS", 13, 19 },
+ { "CL12_IF_PAR_ERROR", 12, 1 },
+ { "CL11_IF_PAR_ERROR", 11, 1 },
+ { "CL10_IF_PAR_ERROR", 10, 1 },
+ { "CL9_IF_PAR_ERROR", 9, 1 },
+ { "CL8_IF_PAR_ERROR", 8, 1 },
+ { "CL7_IF_PAR_ERROR", 7, 1 },
+ { "CL6_IF_PAR_ERROR", 6, 1 },
+ { "CL5_IF_PAR_ERROR", 5, 1 },
+ { "CL4_IF_PAR_ERROR", 4, 1 },
+ { "CL3_IF_PAR_ERROR", 3, 1 },
+ { "CL2_IF_PAR_ERROR", 2, 1 },
+ { "CL1_IF_PAR_ERROR", 1, 1 },
+ { "CL0_IF_PAR_ERROR", 0, 1 },
+ { "MA_LOCAL_DEBUG_CFG", 0x78f8, 0 },
+ { "DEBUG_OR", 15, 1 },
+ { "DEBUG_HI", 14, 1 },
+ { "DEBUG_RPT", 13, 1 },
+ { "DEBUGPAGE", 10, 3 },
+ { "DEBUGSELH", 5, 5 },
+ { "DEBUGSELL", 0, 5 },
+ { "MA_LOCAL_DEBUG_RPT", 0x78fc, 0 },
+ { NULL }
+};
+
+struct reg_info t6_cim_regs[] = {
+ { "CIM_BOOT_CFG", 0x7b00, 0 },
+ { "BootAddr", 8, 24 },
+ { "uPGen", 2, 6 },
+ { "BootSdram", 1, 1 },
+ { "uPCRst", 0, 1 },
+ { "CIM_BOOT_LEN", 0x7bf0, 0 },
+ { "BootLen", 4, 28 },
+ { "CIM_FLASH_BASE_ADDR", 0x7b04, 0 },
+ { "FlashBaseAddr", 6, 18 },
+ { "CIM_FLASH_ADDR_SIZE", 0x7b08, 0 },
+ { "FlashAddrSize", 4, 20 },
+ { "CIM_EEPROM_BASE_ADDR", 0x7b0c, 0 },
+ { "EEPROMBaseAddr", 6, 18 },
+ { "CIM_EEPROM_ADDR_SIZE", 0x7b10, 0 },
+ { "EEPROMAddrSize", 4, 20 },
+ { "CIM_SDRAM_BASE_ADDR", 0x7b14, 0 },
+ { "SdramBaseAddr", 6, 26 },
+ { "CIM_SDRAM_ADDR_SIZE", 0x7b18, 0 },
+ { "SdramAddrSize", 4, 28 },
+ { "CIM_EXTMEM2_BASE_ADDR", 0x7b1c, 0 },
+ { "ExtMem2BaseAddr", 6, 26 },
+ { "CIM_EXTMEM2_ADDR_SIZE", 0x7b20, 0 },
+ { "ExtMem2AddrSize", 4, 28 },
+ { "CIM_UP_SPARE_INT", 0x7b24, 0 },
+ { "TDebugInt", 4, 1 },
+ { "BootVecSel", 3, 1 },
+ { "uPSpareInt", 0, 3 },
+ { "CIM_HOST_INT_ENABLE", 0x7b28, 0 },
+ { "PCIE2CIMIntfParErr", 29, 1 },
+ { "ma_cim_IntfPerr", 28, 1 },
+ { "PLCIM_MstRspDataParErr", 27, 1 },
+ { "NCSI2CIMIntfParErr", 26, 1 },
+ { "SGE2CIMIntfParErr", 25, 1 },
+ { "ULP2CIMIntfParErr", 24, 1 },
+ { "TP2CIMIntfParErr", 23, 1 },
+ { "OBQSGERx1ParErr", 22, 1 },
+ { "OBQSGERx0ParErr", 21, 1 },
+ { "TieQOutParErrIntEn", 20, 1 },
+ { "TieQInParErrIntEn", 19, 1 },
+ { "MBHostParErr", 18, 1 },
+ { "MBuPParErr", 17, 1 },
+ { "IBQTP0ParErr", 16, 1 },
+ { "IBQTP1ParErr", 15, 1 },
+ { "IBQULPParErr", 14, 1 },
+ { "IBQSGELOParErr", 13, 1 },
+ { "IBQPCIEParErr", 12, 1 },
+ { "IBQNCSIParErr", 11, 1 },
+ { "OBQULP0ParErr", 10, 1 },
+ { "OBQULP1ParErr", 9, 1 },
+ { "OBQULP2ParErr", 8, 1 },
+ { "OBQULP3ParErr", 7, 1 },
+ { "OBQSGEParErr", 6, 1 },
+ { "OBQNCSIParErr", 5, 1 },
+ { "Timer1IntEn", 3, 1 },
+ { "Timer0IntEn", 2, 1 },
+ { "PrefDropIntEn", 1, 1 },
+ { "CIM_HOST_INT_CAUSE", 0x7b2c, 0 },
+ { "PCIE2CIMIntfParErr", 29, 1 },
+ { "ma_cim_IntfPerr", 28, 1 },
+ { "PLCIM_MstRspDataParErr", 27, 1 },
+ { "NCSI2CIMIntfParErr", 26, 1 },
+ { "SGE2CIMIntfParErr", 25, 1 },
+ { "ULP2CIMIntfParErr", 24, 1 },
+ { "TP2CIMIntfParErr", 23, 1 },
+ { "OBQSGERx1ParErr", 22, 1 },
+ { "OBQSGERx0ParErr", 21, 1 },
+ { "TieQOutParErrInt", 20, 1 },
+ { "TieQInParErrInt", 19, 1 },
+ { "MBHostParErr", 18, 1 },
+ { "IBQTP0ParErr", 16, 1 },
+ { "IBQTP1ParErr", 15, 1 },
+ { "IBQULPParErr", 14, 1 },
+ { "IBQSGELOParErr", 13, 1 },
+ { "IBQPCIEParErr", 12, 1 },
+ { "IBQNCSIParErr", 11, 1 },
+ { "OBQULP0ParErr", 10, 1 },
+ { "OBQULP1ParErr", 9, 1 },
+ { "OBQULP2ParErr", 8, 1 },
+ { "OBQULP3ParErr", 7, 1 },
+ { "OBQSGEParErr", 6, 1 },
+ { "OBQNCSIParErr", 5, 1 },
+ { "Timer1Int", 3, 1 },
+ { "Timer0Int", 2, 1 },
+ { "PrefDropInt", 1, 1 },
+ { "uPAccNonZero", 0, 1 },
+ { "CIM_HOST_UPACC_INT_ENABLE", 0x7b30, 0 },
+ { "EEPROMWRIntEn", 30, 1 },
+ { "TimeOutMAIntEn", 29, 1 },
+ { "TimeOutIntEn", 28, 1 },
+ { "RspOvrLookupIntEn", 27, 1 },
+ { "ReqOvrLookupIntEn", 26, 1 },
+ { "BlkWrPlIntEn", 25, 1 },
+ { "BlkRdPlIntEn", 24, 1 },
+ { "SglWrPlIntEn", 23, 1 },
+ { "SglRdPlIntEn", 22, 1 },
+ { "BlkWrCtlIntEn", 21, 1 },
+ { "BlkRdCtlIntEn", 20, 1 },
+ { "SglWrCtlIntEn", 19, 1 },
+ { "SglRdCtlIntEn", 18, 1 },
+ { "BlkWrEEPROMIntEn", 17, 1 },
+ { "BlkRdEEPROMIntEn", 16, 1 },
+ { "SglWrEEPROMIntEn", 15, 1 },
+ { "SglRdEEPROMIntEn", 14, 1 },
+ { "BlkWrFlashIntEn", 13, 1 },
+ { "BlkRdFlashIntEn", 12, 1 },
+ { "SglWrFlashIntEn", 11, 1 },
+ { "SglRdFlashIntEn", 10, 1 },
+ { "BlkWrBootIntEn", 9, 1 },
+ { "BlkRdBootIntEn", 8, 1 },
+ { "SglWrBootIntEn", 7, 1 },
+ { "SglRdBootIntEn", 6, 1 },
+ { "IllWrBEIntEn", 5, 1 },
+ { "IllRdBEIntEn", 4, 1 },
+ { "IllRdIntEn", 3, 1 },
+ { "IllWrIntEn", 2, 1 },
+ { "IllTransIntEn", 1, 1 },
+ { "RsvdSpaceIntEn", 0, 1 },
+ { "CIM_HOST_UPACC_INT_CAUSE", 0x7b34, 0 },
+ { "EEPROMWRInt", 30, 1 },
+ { "TimeOutMAInt", 29, 1 },
+ { "TimeOutInt", 28, 1 },
+ { "RspOvrLookupInt", 27, 1 },
+ { "ReqOvrLookupInt", 26, 1 },
+ { "BlkWrPlInt", 25, 1 },
+ { "BlkRdPlInt", 24, 1 },
+ { "SglWrPlInt", 23, 1 },
+ { "SglRdPlInt", 22, 1 },
+ { "BlkWrCtlInt", 21, 1 },
+ { "BlkRdCtlInt", 20, 1 },
+ { "SglWrCtlInt", 19, 1 },
+ { "SglRdCtlInt", 18, 1 },
+ { "BlkWrEEPROMInt", 17, 1 },
+ { "BlkRdEEPROMInt", 16, 1 },
+ { "SglWrEEPROMInt", 15, 1 },
+ { "SglRdEEPROMInt", 14, 1 },
+ { "BlkWrFlashInt", 13, 1 },
+ { "BlkRdFlashInt", 12, 1 },
+ { "SglWrFlashInt", 11, 1 },
+ { "SglRdFlashInt", 10, 1 },
+ { "BlkWrBootInt", 9, 1 },
+ { "BlkRdBootInt", 8, 1 },
+ { "SglWrBootInt", 7, 1 },
+ { "SglRdBootInt", 6, 1 },
+ { "IllWrBEInt", 5, 1 },
+ { "IllRdBEInt", 4, 1 },
+ { "IllRdInt", 3, 1 },
+ { "IllWrInt", 2, 1 },
+ { "IllTransInt", 1, 1 },
+ { "RsvdSpaceInt", 0, 1 },
+ { "CIM_UP_INT_ENABLE", 0x7b38, 0 },
+ { "PCIE2CIMIntfParErr", 29, 1 },
+ { "ma_cim_IntfPerr", 28, 1 },
+ { "PLCIM_MstRspDataParErr", 27, 1 },
+ { "NCSI2CIMIntfParErr", 26, 1 },
+ { "SGE2CIMIntfParErr", 25, 1 },
+ { "ULP2CIMIntfParErr", 24, 1 },
+ { "TP2CIMIntfParErr", 23, 1 },
+ { "OBQSGERx1ParErr", 22, 1 },
+ { "OBQSGERx0ParErr", 21, 1 },
+ { "TieQOutParErrIntEn", 20, 1 },
+ { "TieQInParErrIntEn", 19, 1 },
+ { "MBHostParErr", 18, 1 },
+ { "MBuPParErr", 17, 1 },
+ { "IBQTP0ParErr", 16, 1 },
+ { "IBQTP1ParErr", 15, 1 },
+ { "IBQULPParErr", 14, 1 },
+ { "IBQSGELOParErr", 13, 1 },
+ { "IBQPCIEParErr", 12, 1 },
+ { "IBQNCSIParErr", 11, 1 },
+ { "OBQULP0ParErr", 10, 1 },
+ { "OBQULP1ParErr", 9, 1 },
+ { "OBQULP2ParErr", 8, 1 },
+ { "OBQULP3ParErr", 7, 1 },
+ { "OBQSGEParErr", 6, 1 },
+ { "OBQNCSIParErr", 5, 1 },
+ { "MstPlIntEn", 4, 1 },
+ { "Timer1IntEn", 3, 1 },
+ { "Timer0IntEn", 2, 1 },
+ { "PrefDropIntEn", 1, 1 },
+ { "CIM_UP_INT_CAUSE", 0x7b3c, 0 },
+ { "PCIE2CIMIntfParErr", 29, 1 },
+ { "ma_cim_IntfPerr", 28, 1 },
+ { "PLCIM_MstRspDataParErr", 27, 1 },
+ { "NCSI2CIMIntfParErr", 26, 1 },
+ { "SGE2CIMIntfParErr", 25, 1 },
+ { "ULP2CIMIntfParErr", 24, 1 },
+ { "TP2CIMIntfParErr", 23, 1 },
+ { "OBQSGERx1ParErr", 22, 1 },
+ { "OBQSGERx0ParErr", 21, 1 },
+ { "TieQOutParErrInt", 20, 1 },
+ { "TieQInParErrInt", 19, 1 },
+ { "MBHostParErr", 18, 1 },
+ { "IBQTP0ParErr", 16, 1 },
+ { "IBQTP1ParErr", 15, 1 },
+ { "IBQULPParErr", 14, 1 },
+ { "IBQSGELOParErr", 13, 1 },
+ { "IBQPCIEParErr", 12, 1 },
+ { "IBQNCSIParErr", 11, 1 },
+ { "OBQULP0ParErr", 10, 1 },
+ { "OBQULP1ParErr", 9, 1 },
+ { "OBQULP2ParErr", 8, 1 },
+ { "OBQULP3ParErr", 7, 1 },
+ { "OBQSGEParErr", 6, 1 },
+ { "OBQNCSIParErr", 5, 1 },
+ { "MstPlInt", 4, 1 },
+ { "Timer1Int", 3, 1 },
+ { "Timer0Int", 2, 1 },
+ { "PrefDropInt", 1, 1 },
+ { "uPAccNonZero", 0, 1 },
+ { "CIM_UP_ACC_INT_ENABLE", 0x7b40, 0 },
+ { "EEPROMWRIntEn", 30, 1 },
+ { "TimeOutMAIntEn", 29, 1 },
+ { "TimeOutIntEn", 28, 1 },
+ { "RspOvrLookupIntEn", 27, 1 },
+ { "ReqOvrLookupIntEn", 26, 1 },
+ { "BlkWrPlIntEn", 25, 1 },
+ { "BlkRdPlIntEn", 24, 1 },
+ { "SglWrPlIntEn", 23, 1 },
+ { "SglRdPlIntEn", 22, 1 },
+ { "BlkWrCtlIntEn", 21, 1 },
+ { "BlkRdCtlIntEn", 20, 1 },
+ { "SglWrCtlIntEn", 19, 1 },
+ { "SglRdCtlIntEn", 18, 1 },
+ { "BlkWrEEPROMIntEn", 17, 1 },
+ { "BlkRdEEPROMIntEn", 16, 1 },
+ { "SglWrEEPROMIntEn", 15, 1 },
+ { "SglRdEEPROMIntEn", 14, 1 },
+ { "BlkWrFlashIntEn", 13, 1 },
+ { "BlkRdFlashIntEn", 12, 1 },
+ { "SglWrFlashIntEn", 11, 1 },
+ { "SglRdFlashIntEn", 10, 1 },
+ { "BlkWrBootIntEn", 9, 1 },
+ { "BlkRdBootIntEn", 8, 1 },
+ { "SglWrBootIntEn", 7, 1 },
+ { "SglRdBootIntEn", 6, 1 },
+ { "IllWrBEIntEn", 5, 1 },
+ { "IllRdBEIntEn", 4, 1 },
+ { "IllRdIntEn", 3, 1 },
+ { "IllWrIntEn", 2, 1 },
+ { "IllTransIntEn", 1, 1 },
+ { "RsvdSpaceIntEn", 0, 1 },
+ { "CIM_UP_ACC_INT_CAUSE", 0x7b44, 0 },
+ { "EEPROMWRInt", 30, 1 },
+ { "TimeOutMAInt", 29, 1 },
+ { "TimeOutInt", 28, 1 },
+ { "RspOvrLookupInt", 27, 1 },
+ { "ReqOvrLookupInt", 26, 1 },
+ { "BlkWrPlInt", 25, 1 },
+ { "BlkRdPlInt", 24, 1 },
+ { "SglWrPlInt", 23, 1 },
+ { "SglRdPlInt", 22, 1 },
+ { "BlkWrCtlInt", 21, 1 },
+ { "BlkRdCtlInt", 20, 1 },
+ { "SglWrCtlInt", 19, 1 },
+ { "SglRdCtlInt", 18, 1 },
+ { "BlkWrEEPROMInt", 17, 1 },
+ { "BlkRdEEPROMInt", 16, 1 },
+ { "SglWrEEPROMInt", 15, 1 },
+ { "SglRdEEPROMInt", 14, 1 },
+ { "BlkWrFlashInt", 13, 1 },
+ { "BlkRdFlashInt", 12, 1 },
+ { "SglWrFlashInt", 11, 1 },
+ { "SglRdFlashInt", 10, 1 },
+ { "BlkWrBootInt", 9, 1 },
+ { "BlkRdBootInt", 8, 1 },
+ { "SglWrBootInt", 7, 1 },
+ { "SglRdBootInt", 6, 1 },
+ { "IllWrBEInt", 5, 1 },
+ { "IllRdBEInt", 4, 1 },
+ { "IllRdInt", 3, 1 },
+ { "IllWrInt", 2, 1 },
+ { "IllTransInt", 1, 1 },
+ { "RsvdSpaceInt", 0, 1 },
+ { "CIM_QUEUE_CONFIG_REF", 0x7b48, 0 },
+ { "OBQSelect", 4, 1 },
+ { "IBQSelect", 3, 1 },
+ { "QueNumSelect", 0, 3 },
+ { "CIM_QUEUE_CONFIG_CTRL", 0x7b4c, 0 },
+ { "Que1KEn", 30, 1 },
+ { "QueSize", 24, 6 },
+ { "QueBase", 16, 6 },
+ { "QueDbg8BEn", 9, 1 },
+ { "QueFullThrsh", 0, 9 },
+ { "CIM_HOST_ACC_CTRL", 0x7b50, 0 },
+ { "HostBusy", 17, 1 },
+ { "HostWrite", 16, 1 },
+ { "HostAddr", 0, 16 },
+ { "CIM_HOST_ACC_DATA", 0x7b54, 0 },
+ { "CIM_CDEBUGDATA", 0x7b58, 0 },
+ { "CDebugDataH", 16, 16 },
+ { "CDebugDataL", 0, 16 },
+ { "CIM_IBQ_DBG_CFG", 0x7b60, 0 },
+ { "IbqDbgAddr", 16, 12 },
+ { "IbqDbgWr", 2, 1 },
+ { "IbqDbgBusy", 1, 1 },
+ { "IbqDbgEn", 0, 1 },
+ { "CIM_OBQ_DBG_CFG", 0x7b64, 0 },
+ { "ObqDbgAddr", 16, 12 },
+ { "ObqDbgWr", 2, 1 },
+ { "ObqDbgBusy", 1, 1 },
+ { "ObqDbgEn", 0, 1 },
+ { "CIM_IBQ_DBG_DATA", 0x7b68, 0 },
+ { "CIM_OBQ_DBG_DATA", 0x7b6c, 0 },
+ { "CIM_DEBUGCFG", 0x7b70, 0 },
+ { "POLADbgRdPtr", 23, 9 },
+ { "PILADbgRdPtr", 14, 9 },
+ { "LAMaskTrig", 13, 1 },
+ { "LADbgEn", 12, 1 },
+ { "LAFillOnce", 11, 1 },
+ { "LAMaskStop", 10, 1 },
+ { "DebugSelH", 5, 5 },
+ { "DebugSelL", 0, 5 },
+ { "CIM_DEBUGSTS", 0x7b74, 0 },
+ { "LAReset", 31, 1 },
+ { "POLADbgWrPtr", 16, 9 },
+ { "PILADbgWrPtr", 0, 9 },
+ { "CIM_PO_LA_DEBUGDATA", 0x7b78, 0 },
+ { "CIM_PI_LA_DEBUGDATA", 0x7b7c, 0 },
+ { "CIM_PO_LA_MADEBUGDATA", 0x7b80, 0 },
+ { "CIM_PI_LA_MADEBUGDATA", 0x7b84, 0 },
+ { "CIM_PO_LA_PIFSMDEBUGDATA", 0x7b8c, 0 },
+ { "CIM_MEM_ZONE0_VA", 0x7b90, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE0_BA", 0x7b94, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE0_LEN", 0x7b98, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE1_VA", 0x7b9c, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE1_BA", 0x7ba0, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE1_LEN", 0x7ba4, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE2_VA", 0x7ba8, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE2_BA", 0x7bac, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE2_LEN", 0x7bb0, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE3_VA", 0x7bb4, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE3_BA", 0x7bb8, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE3_LEN", 0x7bbc, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE4_VA", 0x7bc0, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE4_BA", 0x7bc4, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE4_LEN", 0x7bc8, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE5_VA", 0x7bcc, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE5_BA", 0x7bd0, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE5_LEN", 0x7bd4, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE6_VA", 0x7bd8, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE6_BA", 0x7bdc, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE6_LEN", 0x7be0, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_MEM_ZONE7_VA", 0x7be4, 0 },
+ { "MEM_ZONE_VA", 4, 28 },
+ { "CIM_MEM_ZONE7_BA", 0x7be8, 0 },
+ { "MEM_ZONE_BA", 6, 26 },
+ { "PBT_enable", 5, 1 },
+ { "ZONE_DST", 0, 2 },
+ { "CIM_MEM_ZONE7_LEN", 0x7bec, 0 },
+ { "MEM_ZONE_LEN", 4, 28 },
+ { "CIM_GLB_TIMER_CTL", 0x7bf4, 0 },
+ { "Timer1En", 4, 1 },
+ { "Timer0En", 3, 1 },
+ { "TimerEn", 1, 1 },
+ { "CIM_GLB_TIMER", 0x7bf8, 0 },
+ { "CIM_GLB_TIMER_TICK", 0x7bfc, 0 },
+ { "CIM_TIMER0", 0x7c00, 0 },
+ { "CIM_TIMER1", 0x7c04, 0 },
+ { "CIM_DEBUG_ADDR_TIMEOUT", 0x7c08, 0 },
+ { "DAddrTimeOut", 2, 30 },
+ { "DAddrTimeOutType", 0, 2 },
+ { "CIM_DEBUG_ADDR_ILLEGAL", 0x7c0c, 0 },
+ { "DAddrIllegal", 2, 30 },
+ { "DAddrIllegalType", 0, 2 },
+ { "CIM_DEBUG_PIF_CAUSE_MASK", 0x7c10, 0 },
+ { "CIM_DEBUG_PIF_UPACC_CAUSE_MASK", 0x7c14, 0 },
+ { "CIM_DEBUG_UP_CAUSE_MASK", 0x7c18, 0 },
+ { "CIM_DEBUG_UP_UPACC_CAUSE_MASK", 0x7c1c, 0 },
+ { "CIM_PERR_INJECT", 0x7c20, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "CIM_PERR_ENABLE", 0x7c24, 0 },
+ { "CIM_EEPROM_BUSY_BIT", 0x7c28, 0 },
+ { "CIM_MA_TIMER_EN", 0x7c2c, 0 },
+ { "slow_timer_enable", 1, 1 },
+ { "ma_timer_enable", 0, 1 },
+ { "CIM_UP_PO_SINGLE_OUTSTANDING", 0x7c30, 0 },
+ { "CIM_CIM_DEBUG_SPARE", 0x7c34, 0 },
+ { "CIM_UP_OPERATION_FREQ", 0x7c38, 0 },
+ { "CIM_CIM_IBQ_ERR_CODE", 0x7c3c, 0 },
+ { "CIM_ULP_TX_PKT_ERR_CODE", 16, 8 },
+ { "CIM_PCIE_PKT_ERR_CODE", 8, 8 },
+ { "CIM_SGE0_PKT_ERR_CODE", 0, 8 },
+ { "CIM_IBQ_DBG_WAIT_COUNTER", 0x7c40, 0 },
+ { "CIM_PIO_UP_MST_CFG_SEL", 0x7c44, 0 },
+ { "CIM_CGEN", 0x7c48, 0 },
+ { "CIM_QUEUE_FEATURE_DISABLE", 0x7c4c, 0 },
+ { "pcie_obq_if_disable", 5, 1 },
+ { "obq_throuttle_on_eop", 4, 1 },
+ { "obq_read_ctl_perf_mode_disable", 3, 1 },
+ { "obq_wait_for_eop_flush_disable", 2, 1 },
+ { "ibq_rra_dsbl", 1, 1 },
+ { "ibq_skid_fifo_eop_flsh_dsbl", 0, 1 },
+ { "CIM_CGEN_GLOBAL", 0x7c50, 0 },
+ { "CIM_DPSLP_EN", 0x7c54, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e240, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e244, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e248, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e24c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e250, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e254, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e258, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e25c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e260, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e264, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e268, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e26c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e270, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e274, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e278, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e27c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1e280, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1e284, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1e288, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1e28c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e290, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e640, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e644, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e648, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e64c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e650, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e654, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e658, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e65c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e660, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e664, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e668, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e66c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e670, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e674, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e678, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1e67c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1e680, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1e684, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1e688, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1e68c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e690, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea40, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea44, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea48, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea4c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea50, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea54, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea58, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea5c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea60, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea64, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea68, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea6c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea70, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea74, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea78, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ea7c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1ea80, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1ea84, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1ea88, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1ea8c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ea90, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee40, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee44, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee48, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee4c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee50, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee54, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee58, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee5c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee60, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee64, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee68, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee6c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee70, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee74, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee78, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1ee7c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1ee80, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1ee84, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1ee88, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1ee8c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ee90, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f240, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f244, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f248, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f24c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f250, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f254, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f258, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f25c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f260, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f264, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f268, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f26c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f270, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f274, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f278, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f27c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1f280, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1f284, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1f288, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1f28c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f290, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f640, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f644, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f648, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f64c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f650, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f654, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f658, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f65c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f660, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f664, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f668, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f66c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f670, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f674, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f678, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1f67c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1f680, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1f684, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1f688, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1f68c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f690, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa40, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa44, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa48, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa4c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa50, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa54, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa58, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa5c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa60, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa64, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa68, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa6c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa70, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa74, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa78, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fa7c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1fa80, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1fa84, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1fa88, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1fa8c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fa90, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe40, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe44, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe48, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe4c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe50, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe54, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe58, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe5c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe60, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe64, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe68, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe6c, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe70, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe74, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe78, 0 },
+ { "CIM_PF_MAILBOX_DATA", 0x1fe7c, 0 },
+ { "CIM_PF_MAILBOX_CTRL", 0x1fe80, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { "CIM_PF_MAILBOX_ACC_STATUS", 0x1fe84, 0 },
+ { "MBWrBusy", 31, 1 },
+ { "CIM_PF_HOST_INT_ENABLE", 0x1fe88, 0 },
+ { "MBMsgRdyIntEn", 19, 1 },
+ { "CIM_PF_HOST_INT_CAUSE", 0x1fe8c, 0 },
+ { "MBMsgRdyInt", 19, 1 },
+ { "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fe90, 0 },
+ { "MBGeneric", 4, 28 },
+ { "MBMsgValid", 3, 1 },
+ { "MBIntReq", 2, 1 },
+ { "MBOwner", 0, 2 },
+ { NULL }
+};
+
+struct reg_info t6_tp_regs[] = {
+ { "TP_IN_CONFIG", 0x7d00, 0 },
+ { "VLANExtEnPort3", 31, 1 },
+ { "VLANExtEnPort2", 30, 1 },
+ { "VLANExtEnPort1", 29, 1 },
+ { "VLANExtEnPort0", 28, 1 },
+ { "TcpOptParserDisCh3", 27, 1 },
+ { "TcpOptParserDisCh2", 26, 1 },
+ { "TcpOptParserDisCh1", 25, 1 },
+ { "TcpOptParserDisCh0", 24, 1 },
+ { "CrcPassPrt3", 23, 1 },
+ { "CrcPassPrt2", 22, 1 },
+ { "CrcPassPrt1", 21, 1 },
+ { "CrcPassPrt0", 20, 1 },
+ { "VepaMode", 19, 1 },
+ { "FipUpEn", 18, 1 },
+ { "FcoeUpEn", 17, 1 },
+ { "FcoeEnable", 16, 1 },
+ { "IPv6Enable", 15, 1 },
+ { "NICMode", 14, 1 },
+ { "VnTagDefaultVal", 13, 1 },
+ { "ECheckUDPLen", 12, 1 },
+ { "EReportUdpHdrLen", 11, 1 },
+ { "FcoeFPMA", 10, 1 },
+ { "VnTagEnable", 9, 1 },
+ { "VnTagEthEnable", 8, 1 },
+ { "CChecksumCheckIP", 7, 1 },
+ { "CChecksumCheckUDP", 6, 1 },
+ { "CChecksumCheckTCP", 5, 1 },
+ { "CTag", 4, 1 },
+ { "CXoffOverride", 3, 1 },
+ { "EthUpEn", 2, 1 },
+ { "EGreDropEn", 1, 1 },
+ { "CFastDemuxEn", 0, 1 },
+ { "TP_OUT_CONFIG", 0x7d04, 0 },
+ { "PortQfcEn", 28, 4 },
+ { "EPktDistChn3", 23, 1 },
+ { "EPktDistChn2", 22, 1 },
+ { "EPktDistChn1", 21, 1 },
+ { "EPktDistChn0", 20, 1 },
+ { "TtlMode", 19, 1 },
+ { "EQfcDmac", 18, 1 },
+ { "ELpbkIncMpsStat", 17, 1 },
+ { "IPIDSplitMode", 16, 1 },
+ { "CCplAckMode", 13, 1 },
+ { "RMWHintEnable", 12, 1 },
+ { "EChecksumInsertTCP", 11, 1 },
+ { "EChecksumInsertIP", 10, 1 },
+ { "EVnTagEn", 9, 1 },
+ { "EV6FlwEn", 8, 1 },
+ { "EPriority", 7, 1 },
+ { "EVlanPrio", 6, 1 },
+ { "CChecksumInsertTCP", 5, 1 },
+ { "CChecksumInsertIP", 4, 1 },
+ { "CRxPktEnc", 3, 1 },
+ { "CCPL", 2, 1 },
+ { "CRxPktXt", 1, 1 },
+ { "CEthernet", 0, 1 },
+ { "TP_GLOBAL_CONFIG", 0x7d08, 0 },
+ { "SYNCookieParams", 26, 6 },
+ { "RXFlowControlDisable", 25, 1 },
+ { "TXPacingEnable", 24, 1 },
+ { "ActiveFilterCounts", 22, 1 },
+ { "ProtectedMode", 21, 1 },
+ { "FiveTupleLookup", 17, 2 },
+ { "OfdMpsStats", 16, 1 },
+ { "DontFragment", 15, 1 },
+ { "IPIdentSplit", 14, 1 },
+ { "RssSynSteerEnable", 12, 1 },
+ { "IssFromCplEnable", 11, 1 },
+ { "RssLoopbackEnable", 10, 1 },
+ { "TCAMServerUse", 8, 2 },
+ { "IPTTL", 0, 8 },
+ { "TP_DB_CONFIG", 0x7d0c, 0 },
+ { "DBMaxOpCnt", 24, 8 },
+ { "CxMaxOpCntDisable", 23, 1 },
+ { "CxMaxOpCnt", 16, 7 },
+ { "TxMaxOpCntDisable", 15, 1 },
+ { "TxMaxOpCnt", 8, 7 },
+ { "RxMaxOpCntDisable", 7, 1 },
+ { "RxMaxOpCnt", 0, 7 },
+ { "TP_CMM_TCB_BASE", 0x7d10, 0 },
+ { "TP_CMM_MM_BASE", 0x7d14, 0 },
+ { "TP_CMM_TIMER_BASE", 0x7d18, 0 },
+ { "TP_CMM_MM_FLST_SIZE", 0x7d1c, 0 },
+ { "RxPoolSize", 16, 16 },
+ { "TxPoolSize", 0, 16 },
+ { "TP_PMM_TX_BASE", 0x7d20, 0 },
+ { "TP_PMM_DEFRAG_BASE", 0x7d24, 0 },
+ { "TP_PMM_RX_BASE", 0x7d28, 0 },
+ { "TP_PMM_RX_PAGE_SIZE", 0x7d2c, 0 },
+ { "TP_PMM_RX_MAX_PAGE", 0x7d30, 0 },
+ { "PMRxNumChn", 31, 1 },
+ { "PMRxMaxPage", 0, 21 },
+ { "TP_PMM_TX_PAGE_SIZE", 0x7d34, 0 },
+ { "TP_PMM_TX_MAX_PAGE", 0x7d38, 0 },
+ { "PMTxNumChn", 30, 2 },
+ { "PMTxMaxPage", 0, 21 },
+ { "TP_TCP_OPTIONS", 0x7d40, 0 },
+ { "MTUDefault", 16, 16 },
+ { "MTUEnable", 10, 1 },
+ { "SACKTx", 9, 1 },
+ { "SACKRx", 8, 1 },
+ { "SACKMode", 4, 2 },
+ { "WindowScaleMode", 2, 2 },
+ { "TimestampsMode", 0, 2 },
+ { "TP_DACK_CONFIG", 0x7d44, 0 },
+ { "AutoState3", 30, 2 },
+ { "AutoState2", 28, 2 },
+ { "AutoState1", 26, 2 },
+ { "ByteThreshold", 8, 18 },
+ { "MSSThreshold", 4, 3 },
+ { "AutoCareful", 2, 1 },
+ { "AutoEnable", 1, 1 },
+ { "Mode", 0, 1 },
+ { "TP_PC_CONFIG", 0x7d48, 0 },
+ { "EnableFinCheck", 31, 1 },
+ { "EnableOcspiFull", 30, 1 },
+ { "EnableFLMErrorDDP", 29, 1 },
+ { "LockTid", 28, 1 },
+ { "DisableInvPend", 27, 1 },
+ { "EnableFilterCount", 26, 1 },
+ { "RddpCongEn", 25, 1 },
+ { "EnableOnFlyPDU", 24, 1 },
+ { "EnableMinRcvWnd", 23, 1 },
+ { "EnableMaxRcvWnd", 22, 1 },
+ { "EnableMibVfPld", 21, 1 },
+ { "TxDeferEnable", 20, 1 },
+ { "RxCongestionMode", 19, 1 },
+ { "HearbeatOnceDACK", 18, 1 },
+ { "HearbeatOnceHeap", 17, 1 },
+ { "HearbeatDACK", 16, 1 },
+ { "TxCongestionMode", 15, 1 },
+ { "AcceptLatestRcvAdv", 14, 1 },
+ { "DisableSYNData", 13, 1 },
+ { "DisableWindowPSH", 12, 1 },
+ { "DisableFINOldData", 11, 1 },
+ { "EnableFLMError", 10, 1 },
+ { "EnableOptMtu", 9, 1 },
+ { "FilterPeerFIN", 8, 1 },
+ { "EnableFeedbackSend", 7, 1 },
+ { "EnableRDMAError", 6, 1 },
+ { "EnableFilterNat", 5, 1 },
+ { "DisableSepPshFlag", 4, 1 },
+ { "EnableOfdoVLAN", 3, 1 },
+ { "DisableTimeWait", 2, 1 },
+ { "EnableVlanCheck", 1, 1 },
+ { "TxDataAckPageEnable", 0, 1 },
+ { "TP_PC_CONFIG2", 0x7d4c, 0 },
+ { "EnableMtuVfMode", 31, 1 },
+ { "EnableMibVfMode", 30, 1 },
+ { "DisableLbkCheck", 29, 1 },
+ { "EnableUrgDdpOff", 28, 1 },
+ { "EnableFilterLpbk", 27, 1 },
+ { "DisableTblMmgr", 26, 1 },
+ { "CngRecSndNxt", 25, 1 },
+ { "EnableLbkChn", 24, 1 },
+ { "EnableLroEcn", 23, 1 },
+ { "EnablePcmdCheck", 22, 1 },
+ { "EnableELbkAFull", 21, 1 },
+ { "EnableCLbkAFull", 20, 1 },
+ { "EnableOespiFull", 19, 1 },
+ { "DisableHitCheck", 18, 1 },
+ { "EnableRssErrCheck", 17, 1 },
+ { "DisableNewPshFlag", 16, 1 },
+ { "EnableRddpRcvAdvClr", 15, 1 },
+ { "EnableFinDdpOff", 14, 1 },
+ { "EnableArpMiss", 13, 1 },
+ { "EnableRstPaws", 12, 1 },
+ { "EnableIPv6RSS", 11, 1 },
+ { "EnableNonOfdHybRss", 10, 1 },
+ { "EnableUDP4TupRss", 9, 1 },
+ { "EnableRxPktTmstpRss", 8, 1 },
+ { "EnableEPCMDAFull", 7, 1 },
+ { "EnableCPCMDAFull", 6, 1 },
+ { "EnableEHdrAFull", 5, 1 },
+ { "EnableCHdrAFull", 4, 1 },
+ { "EnableEMacAFull", 3, 1 },
+ { "EnableNonOfdTidRss", 2, 1 },
+ { "EnableNonOfdTcbRss", 1, 1 },
+ { "EnableTnlOfdClosed", 0, 1 },
+ { "TP_TCP_BACKOFF_REG0", 0x7d50, 0 },
+ { "TimerBackoffIndex3", 24, 8 },
+ { "TimerBackoffIndex2", 16, 8 },
+ { "TimerBackoffIndex1", 8, 8 },
+ { "TimerBackoffIndex0", 0, 8 },
+ { "TP_TCP_BACKOFF_REG1", 0x7d54, 0 },
+ { "TimerBackoffIndex7", 24, 8 },
+ { "TimerBackoffIndex6", 16, 8 },
+ { "TimerBackoffIndex5", 8, 8 },
+ { "TimerBackoffIndex4", 0, 8 },
+ { "TP_TCP_BACKOFF_REG2", 0x7d58, 0 },
+ { "TimerBackoffIndex11", 24, 8 },
+ { "TimerBackoffIndex10", 16, 8 },
+ { "TimerBackoffIndex9", 8, 8 },
+ { "TimerBackoffIndex8", 0, 8 },
+ { "TP_TCP_BACKOFF_REG3", 0x7d5c, 0 },
+ { "TimerBackoffIndex15", 24, 8 },
+ { "TimerBackoffIndex14", 16, 8 },
+ { "TimerBackoffIndex13", 8, 8 },
+ { "TimerBackoffIndex12", 0, 8 },
+ { "TP_PARA_REG0", 0x7d60, 0 },
+ { "LimTxThresh", 28, 4 },
+ { "InitCwndIdle", 27, 1 },
+ { "InitCwnd", 24, 3 },
+ { "DupAckThresh", 20, 4 },
+ { "EcnCngFifo", 19, 1 },
+ { "EcnSynAck", 18, 1 },
+ { "EcnThresh", 16, 2 },
+ { "EcnMode", 15, 1 },
+ { "EcnModeCwr", 14, 1 },
+ { "SetTimeEnable", 13, 1 },
+ { "CplErrEnable", 12, 1 },
+ { "FastTnlCnt", 11, 1 },
+ { "ForceShove", 10, 1 },
+ { "TpTcamKey", 9, 1 },
+ { "SwsMode", 8, 1 },
+ { "TsmpMode", 6, 2 },
+ { "ByteCountLimit", 4, 2 },
+ { "SwsShove", 3, 1 },
+ { "TblTimer", 2, 1 },
+ { "RxtPace", 1, 1 },
+ { "SwsTimer", 0, 1 },
+ { "TP_PARA_REG1", 0x7d64, 0 },
+ { "InitRwnd", 16, 16 },
+ { "InitialSSThresh", 0, 16 },
+ { "TP_PARA_REG2", 0x7d68, 0 },
+ { "MaxRxData", 16, 16 },
+ { "RxCoalesceSize", 0, 16 },
+ { "TP_PARA_REG3", 0x7d6c, 0 },
+ { "EnableTnlCngLpbk", 31, 1 },
+ { "EnableTnlCngFifo", 30, 1 },
+ { "EnableTnlCngHdr", 29, 1 },
+ { "EnableTnlCngSge", 28, 1 },
+ { "RxMacCheck", 27, 1 },
+ { "RxSynFilter", 26, 1 },
+ { "CngCtrlECN", 25, 1 },
+ { "RxDdpOffInit", 24, 1 },
+ { "TunnelCngDrop3", 23, 1 },
+ { "TunnelCngDrop2", 22, 1 },
+ { "TunnelCngDrop1", 21, 1 },
+ { "TunnelCngDrop0", 20, 1 },
+ { "TxDataAckIdx", 16, 4 },
+ { "RxFragEnable", 12, 3 },
+ { "TxPaceFixedStrict", 11, 1 },
+ { "TxPaceAutoStrict", 10, 1 },
+ { "TxPaceFixed", 9, 1 },
+ { "TxPaceAuto", 8, 1 },
+ { "RxChnTunnel", 7, 1 },
+ { "RxUrgTunnel", 6, 1 },
+ { "RxUrgMode", 5, 1 },
+ { "TxUrgMode", 4, 1 },
+ { "CngCtrlMode", 2, 2 },
+ { "RxCoalesceEnable", 1, 1 },
+ { "RxCoalescePshEn", 0, 1 },
+ { "TP_PARA_REG4", 0x7d70, 0 },
+ { "IdleCwndHighSpeed", 28, 1 },
+ { "RxmtCwndHighSpeed", 27, 1 },
+ { "OverdriveHighSpeed", 25, 2 },
+ { "ByteCountHighSpeed", 24, 1 },
+ { "IdleCwndNewReno", 20, 1 },
+ { "RxmtCwndNewReno", 19, 1 },
+ { "OverdriveNewReno", 17, 2 },
+ { "ByteCountNewReno", 16, 1 },
+ { "IdleCwndTahoe", 12, 1 },
+ { "RxmtCwndTahoe", 11, 1 },
+ { "OverdriveTahoe", 9, 2 },
+ { "ByteCountTahoe", 8, 1 },
+ { "IdleCwndReno", 4, 1 },
+ { "RxmtCwndReno", 3, 1 },
+ { "OverdriveReno", 1, 2 },
+ { "ByteCountReno", 0, 1 },
+ { "TP_PARA_REG5", 0x7d74, 0 },
+ { "IndicateSize", 16, 16 },
+ { "MaxProxySize", 12, 4 },
+ { "EnableReadPdu", 11, 1 },
+ { "EnableReadAhead", 10, 1 },
+ { "EmptyRqEnable", 9, 1 },
+ { "SchdEnable", 8, 1 },
+ { "EnableXoffPdu", 7, 1 },
+ { "EnableFcoeCheck", 6, 1 },
+ { "EnableFragCheck", 5, 1 },
+ { "RearmDdpOffset", 4, 1 },
+ { "ResetDdpOffset", 3, 1 },
+ { "OnFlyDDPEnable", 2, 1 },
+ { "EnableRdmaFix", 1, 1 },
+ { "PushTimerEnable", 0, 1 },
+ { "TP_PARA_REG6", 0x7d78, 0 },
+ { "TxPDUSizeAdj", 24, 8 },
+ { "TxTcamKey", 22, 1 },
+ { "EnableCByp", 21, 1 },
+ { "DisablePDUAck", 20, 1 },
+ { "EnableCSav", 19, 1 },
+ { "EnableDeferPDU", 18, 1 },
+ { "EnableFlush", 17, 1 },
+ { "EnableBytePersist", 16, 1 },
+ { "DisableTmoCng", 15, 1 },
+ { "EnableReadAhead", 14, 1 },
+ { "AllowExeption", 13, 1 },
+ { "EnableDeferACK", 12, 1 },
+ { "EnableESnd", 11, 1 },
+ { "EnableCSnd", 10, 1 },
+ { "EnablePDUE", 9, 1 },
+ { "EnablePDUC", 8, 1 },
+ { "EnableBUFI", 7, 1 },
+ { "EnableBUFE", 6, 1 },
+ { "EnableDefer", 5, 1 },
+ { "EnableClearRxmtOos", 4, 1 },
+ { "DisablePDUCng", 3, 1 },
+ { "DisablePDUTimeout", 2, 1 },
+ { "DisablePDURxmt", 1, 1 },
+ { "DisablePDUxmt", 0, 1 },
+ { "TP_PARA_REG7", 0x7d7c, 0 },
+ { "PMMaxXferLen1", 16, 16 },
+ { "PMMaxXferLen0", 0, 16 },
+ { "TP_ENG_CONFIG", 0x7d80, 0 },
+ { "TableLatencyDone", 28, 4 },
+ { "TableLatencyStart", 24, 4 },
+ { "EngineLatencyDelta", 16, 4 },
+ { "EngineLatencyMmgr", 12, 4 },
+ { "EngineLatencyWireIp6", 8, 4 },
+ { "EngineLatencyWire", 4, 4 },
+ { "EngineLatencyBase", 0, 4 },
+ { "TP_PARA_REG8", 0x7d84, 0 },
+ { "EcnAckEct", 2, 1 },
+ { "EcnFinEct", 1, 1 },
+ { "EcnSynEct", 0, 1 },
+ { "TP_ERR_CONFIG", 0x7d8c, 0 },
+ { "TnlErrorFPMA", 31, 1 },
+ { "TnlErrorPing", 30, 1 },
+ { "TnlErrorCsum", 29, 1 },
+ { "TnlErrorCsumIP", 28, 1 },
+ { "TnlErrorOpaque", 27, 1 },
+ { "TnlErrorIp6Opt", 26, 1 },
+ { "TnlErrorTcpOpt", 25, 1 },
+ { "TnlErrorPktLen", 24, 1 },
+ { "TnlErrorTcpHdrLen", 23, 1 },
+ { "TnlErrorIpHdrLen", 22, 1 },
+ { "TnlErrorEthHdrLen", 21, 1 },
+ { "TnlErrorAttack", 20, 1 },
+ { "TnlErrorFrag", 19, 1 },
+ { "TnlErrorIpVer", 18, 1 },
+ { "TnlErrorMac", 17, 1 },
+ { "TnlErrorAny", 16, 1 },
+ { "DropErrorFPMA", 15, 1 },
+ { "DropErrorPing", 14, 1 },
+ { "DropErrorCsum", 13, 1 },
+ { "DropErrorCsumIP", 12, 1 },
+ { "DropErrorOpaque", 11, 1 },
+ { "DropErrorIp6Opt", 10, 1 },
+ { "DropErrorTcpOpt", 9, 1 },
+ { "DropErrorPktLen", 8, 1 },
+ { "DropErrorTcpHdrLen", 7, 1 },
+ { "DropErrorIpHdrLen", 6, 1 },
+ { "DropErrorEthHdrLen", 5, 1 },
+ { "DropErrorAttack", 4, 1 },
+ { "DropErrorFrag", 3, 1 },
+ { "DropErrorIpVer", 2, 1 },
+ { "DropErrorMac", 1, 1 },
+ { "DropErrorAny", 0, 1 },
+ { "TP_TIMER_RESOLUTION", 0x7d90, 0 },
+ { "TimerResolution", 16, 8 },
+ { "TimestampResolution", 8, 8 },
+ { "DelayedACKResolution", 0, 8 },
+ { "TP_MSL", 0x7d94, 0 },
+ { "TP_RXT_MIN", 0x7d98, 0 },
+ { "TP_RXT_MAX", 0x7d9c, 0 },
+ { "TP_PERS_MIN", 0x7da0, 0 },
+ { "TP_PERS_MAX", 0x7da4, 0 },
+ { "TP_KEEP_IDLE", 0x7da8, 0 },
+ { "TP_KEEP_INTVL", 0x7dac, 0 },
+ { "TP_INIT_SRTT", 0x7db0, 0 },
+ { "MaxRtt", 16, 16 },
+ { "InitSrtt", 0, 16 },
+ { "TP_DACK_TIMER", 0x7db4, 0 },
+ { "TP_FINWAIT2_TIMER", 0x7db8, 0 },
+ { "TP_FAST_FINWAIT2_TIMER", 0x7dbc, 0 },
+ { "TP_SHIFT_CNT", 0x7dc0, 0 },
+ { "SynShiftMax", 24, 4 },
+ { "RxtShiftMaxR1", 20, 4 },
+ { "RxtShiftMaxR2", 16, 4 },
+ { "PerShiftBackoffMax", 12, 4 },
+ { "PerShiftMax", 8, 4 },
+ { "KeepaliveMaxR1", 4, 4 },
+ { "KeepaliveMaxR2", 0, 4 },
+ { "TP_TM_CONFIG", 0x7dc4, 0 },
+ { "TP_TIME_LO", 0x7dc8, 0 },
+ { "TP_TIME_HI", 0x7dcc, 0 },
+ { "TP_PORT_MTU_0", 0x7dd0, 0 },
+ { "Port1MTUValue", 16, 16 },
+ { "Port0MTUValue", 0, 16 },
+ { "TP_PORT_MTU_1", 0x7dd4, 0 },
+ { "Port3MTUValue", 16, 16 },
+ { "Port2MTUValue", 0, 16 },
+ { "TP_PACE_TABLE", 0x7dd8, 0 },
+ { "TP_CCTRL_TABLE", 0x7ddc, 0 },
+ { "RowIndex", 16, 16 },
+ { "RowValue", 0, 16 },
+ { "TP_MTU_TABLE", 0x7de4, 0 },
+ { "MTUIndex", 24, 8 },
+ { "MTUWidth", 16, 4 },
+ { "MTUValue", 0, 14 },
+ { "TP_ULP_TABLE", 0x7de8, 0 },
+ { "ULPType7Length", 31, 1 },
+ { "ULPType7Offset", 28, 3 },
+ { "ULPType6Length", 27, 1 },
+ { "ULPType6Offset", 24, 3 },
+ { "ULPType5Length", 23, 1 },
+ { "ULPType5Offset", 20, 3 },
+ { "ULPType4Length", 19, 1 },
+ { "ULPType4Offset", 16, 3 },
+ { "ULPType3Length", 15, 1 },
+ { "ULPType3Offset", 12, 3 },
+ { "ULPType2Length", 11, 1 },
+ { "ULPType2Offset", 8, 3 },
+ { "ULPType1Length", 7, 1 },
+ { "ULPType1Offset", 4, 3 },
+ { "ULPType0Length", 3, 1 },
+ { "ULPType0Offset", 0, 3 },
+ { "TP_RSS_LKP_TABLE", 0x7dec, 0 },
+ { "LkpTblRowVld", 31, 1 },
+ { "LkpTblRowIdx", 20, 11 },
+ { "LkpTblQueue1", 10, 10 },
+ { "LkpTblQueue0", 0, 10 },
+ { "TP_RSS_CONFIG", 0x7df0, 0 },
+ { "TNL4tupEnIpv6", 31, 1 },
+ { "TNL2tupEnIpv6", 30, 1 },
+ { "TNL4tupEnIpv4", 29, 1 },
+ { "TNL2tupEnIpv4", 28, 1 },
+ { "TNLTcpSel", 27, 1 },
+ { "TNLIp6Sel", 26, 1 },
+ { "TNLVrtSel", 25, 1 },
+ { "TNLMapEn", 24, 1 },
+ { "TNLFcoeMode", 23, 1 },
+ { "TNLFcoeSid", 22, 1 },
+ { "TNLFcoeEn", 21, 1 },
+ { "HashXor", 20, 1 },
+ { "OFDHashSave", 19, 1 },
+ { "OFDVrtSel", 18, 1 },
+ { "OFDMapEn", 17, 1 },
+ { "OFDLkpEn", 16, 1 },
+ { "SYN4tupEnIpv6", 15, 1 },
+ { "SYN2tupEnIpv6", 14, 1 },
+ { "SYN4tupEnIpv4", 13, 1 },
+ { "SYN2tupEnIpv4", 12, 1 },
+ { "SYNIp6Sel", 11, 1 },
+ { "SYNVrtSel", 10, 1 },
+ { "SYNMapEn", 9, 1 },
+ { "SYNLkpEn", 8, 1 },
+ { "ChannelEnable", 7, 1 },
+ { "PortEnable", 6, 1 },
+ { "TNLAllLookup", 5, 1 },
+ { "VirtEnable", 4, 1 },
+ { "CongestionEnable", 3, 1 },
+ { "HashToeplitz", 2, 1 },
+ { "UdpEnable", 1, 1 },
+ { "Disable", 0, 1 },
+ { "TP_RSS_CONFIG_TNL", 0x7df4, 0 },
+ { "MaskSize", 28, 4 },
+ { "MaskFilter", 16, 11 },
+ { "HashAll", 2, 1 },
+ { "HashEth", 1, 1 },
+ { "UseWireCh", 0, 1 },
+ { "TP_RSS_CONFIG_OFD", 0x7df8, 0 },
+ { "MaskSize", 28, 4 },
+ { "RRCPLMapEn", 20, 1 },
+ { "RRCPLQueWidth", 16, 4 },
+ { "FrmwrQueMask", 12, 4 },
+ { "TP_RSS_CONFIG_SYN", 0x7dfc, 0 },
+ { "MaskSize", 28, 4 },
+ { "UseWireCh", 0, 1 },
+ { "TP_RSS_CONFIG_VRT", 0x7e00, 0 },
+ { "KeyWrAddrX", 30, 2 },
+ { "KeyExtend", 26, 1 },
+ { "VfRdRg", 25, 1 },
+ { "VfRdEn", 24, 1 },
+ { "VfPerrEn", 23, 1 },
+ { "KeyPerrEn", 22, 1 },
+ { "VfVlanEn", 21, 1 },
+ { "VfFwEn", 20, 1 },
+ { "HashDelay", 16, 4 },
+ { "VfWrAddr", 8, 8 },
+ { "KeyMode", 6, 2 },
+ { "VfWrEn", 5, 1 },
+ { "KeyWrEn", 4, 1 },
+ { "KeyWrAddr", 0, 4 },
+ { "TP_RSS_CONFIG_CNG", 0x7e04, 0 },
+ { "ChnCount3", 31, 1 },
+ { "ChnCount2", 30, 1 },
+ { "ChnCount1", 29, 1 },
+ { "ChnCount0", 28, 1 },
+ { "ChnUndFlow3", 27, 1 },
+ { "ChnUndFlow2", 26, 1 },
+ { "ChnUndFlow1", 25, 1 },
+ { "ChnUndFlow0", 24, 1 },
+ { "ChnOvrFlow3", 23, 1 },
+ { "ChnOvrFlow2", 22, 1 },
+ { "ChnOvrFlow1", 21, 1 },
+ { "ChnOvrFlow0", 20, 1 },
+ { "RstChn3", 19, 1 },
+ { "RstChn2", 18, 1 },
+ { "RstChn1", 17, 1 },
+ { "RstChn0", 16, 1 },
+ { "UpdVld", 15, 1 },
+ { "Xoff", 14, 1 },
+ { "UpdChn3", 13, 1 },
+ { "UpdChn2", 12, 1 },
+ { "UpdChn1", 11, 1 },
+ { "UpdChn0", 10, 1 },
+ { "Queue", 0, 10 },
+ { "TP_LA_TABLE_0", 0x7e10, 0 },
+ { "VirtPort1Table", 16, 16 },
+ { "VirtPort0Table", 0, 16 },
+ { "TP_LA_TABLE_1", 0x7e14, 0 },
+ { "VirtPort3Table", 16, 16 },
+ { "VirtPort2Table", 0, 16 },
+ { "TP_TM_PIO_ADDR", 0x7e18, 0 },
+ { "TP_TM_PIO_DATA", 0x7e1c, 0 },
+ { "TP_MOD_CONFIG", 0x7e24, 0 },
+ { "RxChannelWeight1", 24, 8 },
+ { "RXChannelWeight0", 16, 8 },
+ { "TimerMode", 8, 8 },
+ { "TxChannelXoffEn", 0, 4 },
+ { "TP_TX_MOD_QUEUE_REQ_MAP", 0x7e28, 0 },
+ { "RX_MOD_WEIGHT", 24, 8 },
+ { "TX_MOD_WEIGHT", 16, 8 },
+ { "TX_MOD_QUEUE_REQ_MAP", 0, 16 },
+ { "TP_TX_MOD_QUEUE_WEIGHT1", 0x7e2c, 0 },
+ { "TP_TX_MOD_QUEUE_WEIGHT7", 24, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT6", 16, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT5", 8, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT4", 0, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT0", 0x7e30, 0 },
+ { "TP_TX_MOD_QUEUE_WEIGHT3", 24, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT2", 16, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT1", 8, 8 },
+ { "TP_TX_MOD_QUEUE_WEIGHT0", 0, 8 },
+ { "TP_TX_MOD_CHANNEL_WEIGHT", 0x7e34, 0 },
+ { "CH3", 24, 8 },
+ { "CH2", 16, 8 },
+ { "CH1", 8, 8 },
+ { "CH0", 0, 8 },
+ { "TP_MOD_RATE_LIMIT", 0x7e38, 0 },
+ { "RX_MOD_RATE_LIMIT_INC", 24, 8 },
+ { "RX_MOD_RATE_LIMIT_TICK", 16, 8 },
+ { "TX_MOD_RATE_LIMIT_INC", 8, 8 },
+ { "TX_MOD_RATE_LIMIT_TICK", 0, 8 },
+ { "TP_PIO_ADDR", 0x7e40, 0 },
+ { "TP_PIO_DATA", 0x7e44, 0 },
+ { "TP_RESET", 0x7e4c, 0 },
+ { "FlstInitEnable", 1, 1 },
+ { "TPReset", 0, 1 },
+ { "TP_MIB_INDEX", 0x7e50, 0 },
+ { "TP_MIB_DATA", 0x7e54, 0 },
+ { "TP_SYNC_TIME_HI", 0x7e58, 0 },
+ { "TP_SYNC_TIME_LO", 0x7e5c, 0 },
+ { "TP_CMM_MM_RX_FLST_BASE", 0x7e60, 0 },
+ { "TP_CMM_MM_TX_FLST_BASE", 0x7e64, 0 },
+ { "TP_CMM_MM_PS_FLST_BASE", 0x7e68, 0 },
+ { "TP_CMM_MM_MAX_PSTRUCT", 0x7e6c, 0 },
+ { "TP_INT_ENABLE", 0x7e70, 0 },
+ { "FlmTxFlstEmpty", 30, 1 },
+ { "RssLkpPerr", 29, 1 },
+ { "FlmPerrSet", 28, 1 },
+ { "ProtocolSramPerr", 27, 1 },
+ { "ArpLutPerr", 26, 1 },
+ { "CmRcfOpPerr", 25, 1 },
+ { "CmCachePerr", 24, 1 },
+ { "CmRcfDataPerr", 23, 1 },
+ { "DbL2tLutPerr", 22, 1 },
+ { "DbTxTidPerr", 21, 1 },
+ { "DbExtPerr", 20, 1 },
+ { "DbOpPerr", 19, 1 },
+ { "TmCachePerr", 18, 1 },
+ { "ETpOutCplFifoPerr", 17, 1 },
+ { "ETpOutTcpFifoPerr", 16, 1 },
+ { "ETpOutIpFifoPerr", 15, 1 },
+ { "ETpOutEthFifoPerr", 14, 1 },
+ { "ETpInCplFifoPerr", 13, 1 },
+ { "ETpInTcpOptFifoPerr", 12, 1 },
+ { "ETpInTcpFifoPerr", 11, 1 },
+ { "ETpInIpFifoPerr", 10, 1 },
+ { "ETpInEthFifoPerr", 9, 1 },
+ { "CTpOutCplFifoPerr", 8, 1 },
+ { "CTpOutPldFifoPerr", 7, 1 },
+ { "CTpOutIpFifoPerr", 6, 1 },
+ { "CTpOutEthFifoPerr", 5, 1 },
+ { "CTpInCplFifoPerr", 4, 1 },
+ { "CTpInTcpOpFifoPerr", 3, 1 },
+ { "PduFbkFifoPerr", 2, 1 },
+ { "SrqTablePerr", 1, 1 },
+ { "DelInvFifoPerr", 0, 1 },
+ { "TP_INT_CAUSE", 0x7e74, 0 },
+ { "FlmTxFlstEmpty", 30, 1 },
+ { "RssLkpPerr", 29, 1 },
+ { "FlmPerrSet", 28, 1 },
+ { "ProtocolSramPerr", 27, 1 },
+ { "ArpLutPerr", 26, 1 },
+ { "CmRcfOpPerr", 25, 1 },
+ { "CmCachePerr", 24, 1 },
+ { "CmRcfDataPerr", 23, 1 },
+ { "DbL2tLutPerr", 22, 1 },
+ { "DbTxTidPerr", 21, 1 },
+ { "DbExtPerr", 20, 1 },
+ { "DbOpPerr", 19, 1 },
+ { "TmCachePerr", 18, 1 },
+ { "ETpOutCplFifoPerr", 17, 1 },
+ { "ETpOutTcpFifoPerr", 16, 1 },
+ { "ETpOutIpFifoPerr", 15, 1 },
+ { "ETpOutEthFifoPerr", 14, 1 },
+ { "ETpInCplFifoPerr", 13, 1 },
+ { "ETpInTcpOptFifoPerr", 12, 1 },
+ { "ETpInTcpFifoPerr", 11, 1 },
+ { "ETpInIpFifoPerr", 10, 1 },
+ { "ETpInEthFifoPerr", 9, 1 },
+ { "CTpOutCplFifoPerr", 8, 1 },
+ { "CTpOutPldFifoPerr", 7, 1 },
+ { "CTpOutIpFifoPerr", 6, 1 },
+ { "CTpOutEthFifoPerr", 5, 1 },
+ { "CTpInCplFifoPerr", 4, 1 },
+ { "CTpInTcpOpFifoPerr", 3, 1 },
+ { "PduFbkFifoPerr", 2, 1 },
+ { "SrqTablePerr", 1, 1 },
+ { "DelInvFifoPerr", 0, 1 },
+ { "TP_PER_ENABLE", 0x7e78, 0 },
+ { "FlmTxFlstEmpty", 30, 1 },
+ { "RssLkpPerr", 29, 1 },
+ { "FlmPerrSet", 28, 1 },
+ { "ProtocolSramPerr", 27, 1 },
+ { "ArpLutPerr", 26, 1 },
+ { "CmRcfOpPerr", 25, 1 },
+ { "CmCachePerr", 24, 1 },
+ { "CmRcfDataPerr", 23, 1 },
+ { "DbL2tLutPerr", 22, 1 },
+ { "DbTxTidPerr", 21, 1 },
+ { "DbExtPerr", 20, 1 },
+ { "DbOpPerr", 19, 1 },
+ { "TmCachePerr", 18, 1 },
+ { "ETpOutCplFifoPerr", 17, 1 },
+ { "ETpOutTcpFifoPerr", 16, 1 },
+ { "ETpOutIpFifoPerr", 15, 1 },
+ { "ETpOutEthFifoPerr", 14, 1 },
+ { "ETpInCplFifoPerr", 13, 1 },
+ { "ETpInTcpOptFifoPerr", 12, 1 },
+ { "ETpInTcpFifoPerr", 11, 1 },
+ { "ETpInIpFifoPerr", 10, 1 },
+ { "ETpInEthFifoPerr", 9, 1 },
+ { "CTpOutCplFifoPerr", 8, 1 },
+ { "CTpOutPldFifoPerr", 7, 1 },
+ { "CTpOutIpFifoPerr", 6, 1 },
+ { "CTpOutEthFifoPerr", 5, 1 },
+ { "CTpInCplFifoPerr", 4, 1 },
+ { "CTpInTcpOpFifoPerr", 3, 1 },
+ { "PduFbkFifoPerr", 2, 1 },
+ { "SrqTablePerr", 1, 1 },
+ { "DelInvFifoPerr", 0, 1 },
+ { "TP_FLM_FREE_PS_CNT", 0x7e80, 0 },
+ { "TP_FLM_FREE_RX_CNT", 0x7e84, 0 },
+ { "FreeRxPageChn", 28, 1 },
+ { "FreeRxPageCount", 0, 21 },
+ { "TP_FLM_FREE_TX_CNT", 0x7e88, 0 },
+ { "FreeTxPageChn", 28, 2 },
+ { "FreeTxPageCount", 0, 21 },
+ { "TP_TM_HEAP_PUSH_CNT", 0x7e8c, 0 },
+ { "TP_TM_HEAP_POP_CNT", 0x7e90, 0 },
+ { "TP_TM_DACK_PUSH_CNT", 0x7e94, 0 },
+ { "TP_TM_DACK_POP_CNT", 0x7e98, 0 },
+ { "TP_TM_MOD_PUSH_CNT", 0x7e9c, 0 },
+ { "TP_MOD_POP_CNT", 0x7ea0, 0 },
+ { "TP_TIMER_SEPARATOR", 0x7ea4, 0 },
+ { "TimerSeparator", 16, 16 },
+ { "DisableTimeFreeze", 0, 1 },
+ { "TP_STAMP_TIME", 0x7ea8, 0 },
+ { "TP_DEBUG_FLAGS", 0x7eac, 0 },
+ { "RxTimerCompBuffer", 27, 1 },
+ { "RxTimerDackFirst", 26, 1 },
+ { "RxTimerDack", 25, 1 },
+ { "RxTimerHeartbeat", 24, 1 },
+ { "RxPawsDrop", 23, 1 },
+ { "RxUrgDataDrop", 22, 1 },
+ { "RxFutureData", 21, 1 },
+ { "RxRcvRxmData", 20, 1 },
+ { "RxRcvOooDataFin", 19, 1 },
+ { "RxRcvOooData", 18, 1 },
+ { "RxRcvWndZero", 17, 1 },
+ { "RxRcvWndLtMss", 16, 1 },
+ { "TxDfrFast", 13, 1 },
+ { "TxRxmMisc", 12, 1 },
+ { "TxDupAckInc", 11, 1 },
+ { "TxRxmUrg", 10, 1 },
+ { "TxRxmFin", 9, 1 },
+ { "TxRxmSyn", 8, 1 },
+ { "TxRxmNewReno", 7, 1 },
+ { "TxRxmFast", 6, 1 },
+ { "TxRxmTimer", 5, 1 },
+ { "TxRxmTimerKeepalive", 4, 1 },
+ { "TxRxmTimerPersist", 3, 1 },
+ { "TxRcvAdvShrunk", 2, 1 },
+ { "TxRcvAdvZero", 1, 1 },
+ { "TxRcvAdvLtMss", 0, 1 },
+ { "TP_RX_SCHED", 0x7eb0, 0 },
+ { "CommitReset1", 31, 1 },
+ { "CommitReset0", 30, 1 },
+ { "ForceCong1", 29, 1 },
+ { "ForceCong0", 28, 1 },
+ { "EnableLpbkFull1", 26, 2 },
+ { "EnableLpbkFull0", 24, 2 },
+ { "EnableFifoFull1", 22, 2 },
+ { "EnablePcmdFull1", 20, 2 },
+ { "EnableHdrFull1", 18, 2 },
+ { "EnableFifoFull0", 16, 2 },
+ { "EnablePcmdFull0", 14, 2 },
+ { "EnableHdrFull0", 12, 2 },
+ { "TP_TX_SCHED", 0x7eb4, 0 },
+ { "CommitReset3", 31, 1 },
+ { "CommitReset2", 30, 1 },
+ { "CommitReset1", 29, 1 },
+ { "CommitReset0", 28, 1 },
+ { "ForceCong3", 27, 1 },
+ { "ForceCong2", 26, 1 },
+ { "ForceCong1", 25, 1 },
+ { "ForceCong0", 24, 1 },
+ { "CommitLimit3", 18, 6 },
+ { "CommitLimit2", 12, 6 },
+ { "CommitLimit1", 6, 6 },
+ { "CommitLimit0", 0, 6 },
+ { "TP_FX_SCHED", 0x7eb8, 0 },
+ { "TxChnXoff3", 19, 1 },
+ { "TxChnXoff2", 18, 1 },
+ { "TxChnXoff1", 17, 1 },
+ { "TxChnXoff0", 16, 1 },
+ { "TxModXoff7", 15, 1 },
+ { "TxModXoff6", 14, 1 },
+ { "TxModXoff5", 13, 1 },
+ { "TxModXoff4", 12, 1 },
+ { "TxModXoff3", 11, 1 },
+ { "TxModXoff2", 10, 1 },
+ { "TxModXoff1", 9, 1 },
+ { "TxModXoff0", 8, 1 },
+ { "RxChnXoff3", 7, 1 },
+ { "RxChnXoff2", 6, 1 },
+ { "RxChnXoff1", 5, 1 },
+ { "RxChnXoff0", 4, 1 },
+ { "RxModXoff1", 1, 1 },
+ { "RxModXoff0", 0, 1 },
+ { "TP_TX_ORATE", 0x7ebc, 0 },
+ { "OfdRate3", 24, 8 },
+ { "OfdRate2", 16, 8 },
+ { "OfdRate1", 8, 8 },
+ { "OfdRate0", 0, 8 },
+ { "TP_IX_SCHED0", 0x7ec0, 0 },
+ { "TP_IX_SCHED1", 0x7ec4, 0 },
+ { "TP_IX_SCHED2", 0x7ec8, 0 },
+ { "TP_IX_SCHED3", 0x7ecc, 0 },
+ { "TP_TX_TRATE", 0x7ed0, 0 },
+ { "TnlRate3", 24, 8 },
+ { "TnlRate2", 16, 8 },
+ { "TnlRate1", 8, 8 },
+ { "TnlRate0", 0, 8 },
+ { "TP_DBG_LA_CONFIG", 0x7ed4, 0 },
+ { "DbgLaOpcEnable", 24, 8 },
+ { "DbgLaWhlf", 23, 1 },
+ { "DbgLaWptr", 16, 7 },
+ { "DbgLaMode", 14, 2 },
+ { "DbgLaFatalFreeze", 13, 1 },
+ { "DbgLaEnable", 12, 1 },
+ { "DbgLaRptr", 0, 7 },
+ { "TP_DBG_LA_DATAL", 0x7ed8, 0 },
+ { "TP_DBG_LA_DATAH", 0x7edc, 0 },
+ { "TP_PROTOCOL_CNTRL", 0x7ee8, 0 },
+ { "WriteEnable", 31, 1 },
+ { "TcamEnable", 10, 1 },
+ { "BlockSelect", 8, 2 },
+ { "LineAddress", 1, 7 },
+ { "RequestDone", 0, 1 },
+ { "TP_PROTOCOL_DATA0", 0x7eec, 0 },
+ { "TP_PROTOCOL_DATA1", 0x7ef0, 0 },
+ { "TP_PROTOCOL_DATA2", 0x7ef4, 0 },
+ { "TP_PROTOCOL_DATA3", 0x7ef8, 0 },
+ { "TP_PROTOCOL_DATA4", 0x7efc, 0 },
+ { NULL }
+};
+
+struct reg_info t6_ulp_tx_regs[] = {
+ { "ULP_TX_CONFIG", 0x8dc0, 0 },
+ { "ULIMIT_EXCLUSIVE_FIX", 16, 1 },
+ { "ISO_A_FLAG_EN", 15, 1 },
+ { "IWARP_SEQ_FLIT_DIS", 14, 1 },
+ { "MR_SIZE_FIX_EN", 13, 1 },
+ { "T10_ISO_FIX_EN", 12, 1 },
+ { "CPL_FLAGS_UPDATE_EN", 11, 1 },
+ { "IWARP_SEQ_UPDATE_EN", 10, 1 },
+ { "SEQ_UPDATE_EN", 9, 1 },
+ { "ERR_ITT_EN", 8, 1 },
+ { "atomic_fix_dis", 7, 1 },
+ { "PHYS_ADDR_RESP_EN", 6, 1 },
+ { "ENDIANESS_CHANGE", 5, 1 },
+ { "ERR_RTAG_EN", 4, 1 },
+ { "TSO_ETHLEN_EN", 3, 1 },
+ { "emsg_more_info", 2, 1 },
+ { "LOSDR", 1, 1 },
+ { "extra_tag_insertion_enable", 0, 1 },
+ { "ULP_TX_PERR_INJECT", 0x8dc4, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "ULP_TX_INT_ENABLE", 0x8dc8, 0 },
+ { "Pbl_bound_err_ch3", 31, 1 },
+ { "Pbl_bound_err_ch2", 30, 1 },
+ { "Pbl_bound_err_ch1", 29, 1 },
+ { "Pbl_bound_err_ch0", 28, 1 },
+ { "sge2ulp_fifo_perr_set3", 27, 1 },
+ { "sge2ulp_fifo_perr_set2", 26, 1 },
+ { "sge2ulp_fifo_perr_set1", 25, 1 },
+ { "sge2ulp_fifo_perr_set0", 24, 1 },
+ { "cim2ulp_fifo_perr_set3", 23, 1 },
+ { "cim2ulp_fifo_perr_set2", 22, 1 },
+ { "cim2ulp_fifo_perr_set1", 21, 1 },
+ { "cim2ulp_fifo_perr_set0", 20, 1 },
+ { "CQE_fifo_perr_set3", 19, 1 },
+ { "CQE_fifo_perr_set2", 18, 1 },
+ { "CQE_fifo_perr_set1", 17, 1 },
+ { "CQE_fifo_perr_set0", 16, 1 },
+ { "pbl_fifo_perr_set3", 15, 1 },
+ { "pbl_fifo_perr_set2", 14, 1 },
+ { "pbl_fifo_perr_set1", 13, 1 },
+ { "pbl_fifo_perr_set0", 12, 1 },
+ { "cmd_fifo_perr_set3", 11, 1 },
+ { "cmd_fifo_perr_set2", 10, 1 },
+ { "cmd_fifo_perr_set1", 9, 1 },
+ { "cmd_fifo_perr_set0", 8, 1 },
+ { "lso_hdr_sram_perr_set3", 7, 1 },
+ { "lso_hdr_sram_perr_set2", 6, 1 },
+ { "lso_hdr_sram_perr_set1", 5, 1 },
+ { "lso_hdr_sram_perr_set0", 4, 1 },
+ { "ULP_TX_INT_CAUSE", 0x8dcc, 0 },
+ { "Pbl_bound_err_ch3", 31, 1 },
+ { "Pbl_bound_err_ch2", 30, 1 },
+ { "Pbl_bound_err_ch1", 29, 1 },
+ { "Pbl_bound_err_ch0", 28, 1 },
+ { "sge2ulp_fifo_perr_set3", 27, 1 },
+ { "sge2ulp_fifo_perr_set2", 26, 1 },
+ { "sge2ulp_fifo_perr_set1", 25, 1 },
+ { "sge2ulp_fifo_perr_set0", 24, 1 },
+ { "cim2ulp_fifo_perr_set3", 23, 1 },
+ { "cim2ulp_fifo_perr_set2", 22, 1 },
+ { "cim2ulp_fifo_perr_set1", 21, 1 },
+ { "cim2ulp_fifo_perr_set0", 20, 1 },
+ { "CQE_fifo_perr_set3", 19, 1 },
+ { "CQE_fifo_perr_set2", 18, 1 },
+ { "CQE_fifo_perr_set1", 17, 1 },
+ { "CQE_fifo_perr_set0", 16, 1 },
+ { "pbl_fifo_perr_set3", 15, 1 },
+ { "pbl_fifo_perr_set2", 14, 1 },
+ { "pbl_fifo_perr_set1", 13, 1 },
+ { "pbl_fifo_perr_set0", 12, 1 },
+ { "cmd_fifo_perr_set3", 11, 1 },
+ { "cmd_fifo_perr_set2", 10, 1 },
+ { "cmd_fifo_perr_set1", 9, 1 },
+ { "cmd_fifo_perr_set0", 8, 1 },
+ { "lso_hdr_sram_perr_set3", 7, 1 },
+ { "lso_hdr_sram_perr_set2", 6, 1 },
+ { "lso_hdr_sram_perr_set1", 5, 1 },
+ { "lso_hdr_sram_perr_set0", 4, 1 },
+ { "ULP_TX_PERR_ENABLE", 0x8dd0, 0 },
+ { "sge2ulp_fifo_perr_set3", 27, 1 },
+ { "sge2ulp_fifo_perr_set2", 26, 1 },
+ { "sge2ulp_fifo_perr_set1", 25, 1 },
+ { "sge2ulp_fifo_perr_set0", 24, 1 },
+ { "cim2ulp_fifo_perr_set3", 23, 1 },
+ { "cim2ulp_fifo_perr_set2", 22, 1 },
+ { "cim2ulp_fifo_perr_set1", 21, 1 },
+ { "cim2ulp_fifo_perr_set0", 20, 1 },
+ { "CQE_fifo_perr_set3", 19, 1 },
+ { "CQE_fifo_perr_set2", 18, 1 },
+ { "CQE_fifo_perr_set1", 17, 1 },
+ { "CQE_fifo_perr_set0", 16, 1 },
+ { "pbl_fifo_perr_set3", 15, 1 },
+ { "pbl_fifo_perr_set2", 14, 1 },
+ { "pbl_fifo_perr_set1", 13, 1 },
+ { "pbl_fifo_perr_set0", 12, 1 },
+ { "cmd_fifo_perr_set3", 11, 1 },
+ { "cmd_fifo_perr_set2", 10, 1 },
+ { "cmd_fifo_perr_set1", 9, 1 },
+ { "cmd_fifo_perr_set0", 8, 1 },
+ { "lso_hdr_sram_perr_set3", 7, 1 },
+ { "lso_hdr_sram_perr_set2", 6, 1 },
+ { "lso_hdr_sram_perr_set1", 5, 1 },
+ { "lso_hdr_sram_perr_set0", 4, 1 },
+ { "ULP_TX_TPT_LLIMIT", 0x8dd4, 0 },
+ { "ULP_TX_TPT_ULIMIT", 0x8dd8, 0 },
+ { "ULP_TX_PBL_LLIMIT", 0x8ddc, 0 },
+ { "ULP_TX_PBL_ULIMIT", 0x8de0, 0 },
+ { "ULP_TX_TLS_CTL", 0x8de4, 0 },
+ { "TlsPerrEn", 4, 1 },
+ { "TlsPathCtl", 3, 1 },
+ { "TlsDisableIFuse", 2, 1 },
+ { "TlsDisableCFuse", 1, 1 },
+ { "TlsDisable", 0, 1 },
+ { "ULP_TX_CPL_PACK_SIZE1", 0x8df8, 0 },
+ { "Ch3Size1", 24, 8 },
+ { "Ch2Size1", 16, 8 },
+ { "Ch1Size1", 8, 8 },
+ { "Ch0Size1", 0, 8 },
+ { "ULP_TX_CPL_PACK_SIZE2", 0x8dfc, 0 },
+ { "Ch3Size2", 24, 8 },
+ { "Ch2Size2", 16, 8 },
+ { "Ch1Size2", 8, 8 },
+ { "Ch0Size2", 0, 8 },
+ { "ULP_TX_ERR_MSG2CIM", 0x8e00, 0 },
+ { "ULP_TX_ERR_TABLE_BASE", 0x8e04, 0 },
+ { "ULP_TX_ERR_CNT_CH0", 0x8e10, 0 },
+ { "ULP_TX_ERR_CNT_CH1", 0x8e14, 0 },
+ { "ULP_TX_ERR_CNT_CH2", 0x8e18, 0 },
+ { "ULP_TX_ERR_CNT_CH3", 0x8e1c, 0 },
+ { "ULP_TX_FC_SOF", 0x8e20, 0 },
+ { "SOF_FS3", 24, 8 },
+ { "SOF_FS2", 16, 8 },
+ { "SOF_3", 8, 8 },
+ { "SOF_2", 0, 8 },
+ { "ULP_TX_FC_EOF", 0x8e24, 0 },
+ { "EOF_LS3", 24, 8 },
+ { "EOF_LS2", 16, 8 },
+ { "EOF_3", 8, 8 },
+ { "EOF_2", 0, 8 },
+ { "ULP_TX_CGEN_GLOBAL", 0x8e28, 0 },
+ { "ULP_TX_CGEN", 0x8e2c, 0 },
+ { "ULP_TX_CGEN_Storage", 8, 4 },
+ { "ULP_TX_CGEN_RDMA", 4, 4 },
+ { "ULP_TX_CGEN_Channel", 0, 4 },
+ { "ULP_TX_MEM_CFG", 0x8e30, 0 },
+ { "ULP_TX_PERR_INJECT_2", 0x8e34, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "ULP_TX_FPGA_CMD_CTRL", 0x8e38, 0 },
+ { "ULP_TX_FPGA_CMD_0", 0x8e3c, 0 },
+ { "ULP_TX_FPGA_CMD_1", 0x8e40, 0 },
+ { "ULP_TX_FPGA_CMD_2", 0x8e44, 0 },
+ { "ULP_TX_FPGA_CMD_3", 0x8e48, 0 },
+ { "ULP_TX_FPGA_CMD_4", 0x8e4c, 0 },
+ { "ULP_TX_FPGA_CMD_5", 0x8e50, 0 },
+ { "ULP_TX_FPGA_CMD_6", 0x8e54, 0 },
+ { "ULP_TX_FPGA_CMD_7", 0x8e58, 0 },
+ { "ULP_TX_FPGA_CMD_8", 0x8e5c, 0 },
+ { "ULP_TX_FPGA_CMD_9", 0x8e60, 0 },
+ { "ULP_TX_FPGA_CMD_10", 0x8e64, 0 },
+ { "ULP_TX_FPGA_CMD_11", 0x8e68, 0 },
+ { "ULP_TX_FPGA_CMD_12", 0x8e6c, 0 },
+ { "ULP_TX_FPGA_CMD_13", 0x8e70, 0 },
+ { "ULP_TX_FPGA_CMD_14", 0x8e74, 0 },
+ { "ULP_TX_FPGA_CMD_15", 0x8e78, 0 },
+ { "ULP_TX_INT_ENABLE_2", 0x8e7c, 0 },
+ { "edma_in_fifo_perr_set3", 31, 1 },
+ { "edma_in_fifo_perr_set2", 30, 1 },
+ { "edma_in_fifo_perr_set1", 29, 1 },
+ { "edma_in_fifo_perr_set0", 28, 1 },
+ { "align_ctl_fifo_perr_set3", 27, 1 },
+ { "align_ctl_fifo_perr_set2", 26, 1 },
+ { "align_ctl_fifo_perr_set1", 25, 1 },
+ { "align_ctl_fifo_perr_set0", 24, 1 },
+ { "sge_fifo_perr_set3", 23, 1 },
+ { "sge_fifo_perr_set2", 22, 1 },
+ { "sge_fifo_perr_set1", 21, 1 },
+ { "sge_fifo_perr_set0", 20, 1 },
+ { "stag_fifo_perr_set3", 19, 1 },
+ { "stag_fifo_perr_set2", 18, 1 },
+ { "stag_fifo_perr_set1", 17, 1 },
+ { "stag_fifo_perr_set0", 16, 1 },
+ { "map_fifo_perr_set3", 15, 1 },
+ { "map_fifo_perr_set2", 14, 1 },
+ { "map_fifo_perr_set1", 13, 1 },
+ { "map_fifo_perr_set0", 12, 1 },
+ { "dma_fifo_perr_set3", 11, 1 },
+ { "dma_fifo_perr_set2", 10, 1 },
+ { "dma_fifo_perr_set1", 9, 1 },
+ { "dma_fifo_perr_set0", 8, 1 },
+ { "fso_hdr_sram_perr_set3", 7, 1 },
+ { "fso_hdr_sram_perr_set2", 6, 1 },
+ { "fso_hdr_sram_perr_set1", 5, 1 },
+ { "fso_hdr_sram_perr_set0", 4, 1 },
+ { "t10_pi_sram_perr_set3", 3, 1 },
+ { "t10_pi_sram_perr_set2", 2, 1 },
+ { "t10_pi_sram_perr_set1", 1, 1 },
+ { "t10_pi_sram_perr_set0", 0, 1 },
+ { "ULP_TX_INT_CAUSE_2", 0x8e80, 0 },
+ { "edma_in_fifo_perr_set3", 31, 1 },
+ { "edma_in_fifo_perr_set2", 30, 1 },
+ { "edma_in_fifo_perr_set1", 29, 1 },
+ { "edma_in_fifo_perr_set0", 28, 1 },
+ { "align_ctl_fifo_perr_set3", 27, 1 },
+ { "align_ctl_fifo_perr_set2", 26, 1 },
+ { "align_ctl_fifo_perr_set1", 25, 1 },
+ { "align_ctl_fifo_perr_set0", 24, 1 },
+ { "sge_fifo_perr_set3", 23, 1 },
+ { "sge_fifo_perr_set2", 22, 1 },
+ { "sge_fifo_perr_set1", 21, 1 },
+ { "sge_fifo_perr_set0", 20, 1 },
+ { "stag_fifo_perr_set3", 19, 1 },
+ { "stag_fifo_perr_set2", 18, 1 },
+ { "stag_fifo_perr_set1", 17, 1 },
+ { "stag_fifo_perr_set0", 16, 1 },
+ { "map_fifo_perr_set3", 15, 1 },
+ { "map_fifo_perr_set2", 14, 1 },
+ { "map_fifo_perr_set1", 13, 1 },
+ { "map_fifo_perr_set0", 12, 1 },
+ { "dma_fifo_perr_set3", 11, 1 },
+ { "dma_fifo_perr_set2", 10, 1 },
+ { "dma_fifo_perr_set1", 9, 1 },
+ { "dma_fifo_perr_set0", 8, 1 },
+ { "fso_hdr_sram_perr_set3", 7, 1 },
+ { "fso_hdr_sram_perr_set2", 6, 1 },
+ { "fso_hdr_sram_perr_set1", 5, 1 },
+ { "fso_hdr_sram_perr_set0", 4, 1 },
+ { "t10_pi_sram_perr_set3", 3, 1 },
+ { "t10_pi_sram_perr_set2", 2, 1 },
+ { "t10_pi_sram_perr_set1", 1, 1 },
+ { "t10_pi_sram_perr_set0", 0, 1 },
+ { "ULP_TX_PERR_ENABLE_2", 0x8e84, 0 },
+ { "edma_in_fifo_perr_set3", 31, 1 },
+ { "edma_in_fifo_perr_set2", 30, 1 },
+ { "edma_in_fifo_perr_set1", 29, 1 },
+ { "edma_in_fifo_perr_set0", 28, 1 },
+ { "align_ctl_fifo_perr_set3", 27, 1 },
+ { "align_ctl_fifo_perr_set2", 26, 1 },
+ { "align_ctl_fifo_perr_set1", 25, 1 },
+ { "align_ctl_fifo_perr_set0", 24, 1 },
+ { "sge_fifo_perr_set3", 23, 1 },
+ { "sge_fifo_perr_set2", 22, 1 },
+ { "sge_fifo_perr_set1", 21, 1 },
+ { "sge_fifo_perr_set0", 20, 1 },
+ { "stag_fifo_perr_set3", 19, 1 },
+ { "stag_fifo_perr_set2", 18, 1 },
+ { "stag_fifo_perr_set1", 17, 1 },
+ { "stag_fifo_perr_set0", 16, 1 },
+ { "map_fifo_perr_set3", 15, 1 },
+ { "map_fifo_perr_set2", 14, 1 },
+ { "map_fifo_perr_set1", 13, 1 },
+ { "map_fifo_perr_set0", 12, 1 },
+ { "dma_fifo_perr_set3", 11, 1 },
+ { "dma_fifo_perr_set2", 10, 1 },
+ { "dma_fifo_perr_set1", 9, 1 },
+ { "dma_fifo_perr_set0", 8, 1 },
+ { "fso_hdr_sram_perr_set3", 7, 1 },
+ { "fso_hdr_sram_perr_set2", 6, 1 },
+ { "fso_hdr_sram_perr_set1", 5, 1 },
+ { "fso_hdr_sram_perr_set0", 4, 1 },
+ { "t10_pi_sram_perr_set3", 3, 1 },
+ { "t10_pi_sram_perr_set2", 2, 1 },
+ { "t10_pi_sram_perr_set1", 1, 1 },
+ { "t10_pi_sram_perr_set0", 0, 1 },
+ { "ULP_TX_SE_CNT_ERR", 0x8ea0, 0 },
+ { "ERR_CH3", 12, 4 },
+ { "ERR_CH2", 8, 4 },
+ { "ERR_CH1", 4, 4 },
+ { "ERR_CH0", 0, 4 },
+ { "ULP_TX_SE_CNT_CLR", 0x8ea4, 0 },
+ { "CLR_DROP", 16, 4 },
+ { "CLR_CH3", 12, 4 },
+ { "CLR_CH2", 8, 4 },
+ { "CLR_CH1", 4, 4 },
+ { "CLR_CH0", 0, 4 },
+ { "ULP_TX_SE_CNT_CH0", 0x8ea8, 0 },
+ { "SOP_CNT_ULP2TP", 28, 4 },
+ { "EOP_CNT_ULP2TP", 24, 4 },
+ { "SOP_CNT_LSO_IN", 20, 4 },
+ { "EOP_CNT_LSO_IN", 16, 4 },
+ { "SOP_CNT_ALG_IN", 12, 4 },
+ { "EOP_CNT_ALG_IN", 8, 4 },
+ { "SOP_CNT_CIM2ULP", 4, 4 },
+ { "EOP_CNT_CIM2ULP", 0, 4 },
+ { "ULP_TX_SE_CNT_CH1", 0x8eac, 0 },
+ { "SOP_CNT_ULP2TP", 28, 4 },
+ { "EOP_CNT_ULP2TP", 24, 4 },
+ { "SOP_CNT_LSO_IN", 20, 4 },
+ { "EOP_CNT_LSO_IN", 16, 4 },
+ { "SOP_CNT_ALG_IN", 12, 4 },
+ { "EOP_CNT_ALG_IN", 8, 4 },
+ { "SOP_CNT_CIM2ULP", 4, 4 },
+ { "EOP_CNT_CIM2ULP", 0, 4 },
+ { "ULP_TX_SE_CNT_CH2", 0x8eb0, 0 },
+ { "SOP_CNT_ULP2TP", 28, 4 },
+ { "EOP_CNT_ULP2TP", 24, 4 },
+ { "SOP_CNT_LSO_IN", 20, 4 },
+ { "EOP_CNT_LSO_IN", 16, 4 },
+ { "SOP_CNT_ALG_IN", 12, 4 },
+ { "EOP_CNT_ALG_IN", 8, 4 },
+ { "SOP_CNT_CIM2ULP", 4, 4 },
+ { "EOP_CNT_CIM2ULP", 0, 4 },
+ { "ULP_TX_SE_CNT_CH3", 0x8eb4, 0 },
+ { "SOP_CNT_ULP2TP", 28, 4 },
+ { "EOP_CNT_ULP2TP", 24, 4 },
+ { "SOP_CNT_LSO_IN", 20, 4 },
+ { "EOP_CNT_LSO_IN", 16, 4 },
+ { "SOP_CNT_ALG_IN", 12, 4 },
+ { "EOP_CNT_ALG_IN", 8, 4 },
+ { "SOP_CNT_CIM2ULP", 4, 4 },
+ { "EOP_CNT_CIM2ULP", 0, 4 },
+ { "ULP_TX_DROP_CNT", 0x8eb8, 0 },
+ { "DROP_INVLD_MC_CH3", 28, 4 },
+ { "DROP_INVLD_MC_CH2", 24, 4 },
+ { "DROP_INVLD_MC_CH1", 20, 4 },
+ { "DROP_INVLD_MC_CH0", 16, 4 },
+ { "DROP_CH3", 12, 4 },
+ { "DROP_CH2", 8, 4 },
+ { "DROP_CH1", 4, 4 },
+ { "DROP_CH0", 0, 4 },
+ { "ULP_TX_CSU_REVISION", 0x8ebc, 0 },
+ { "ULP_TX_LA_RDPTR_0", 0x8ec0, 0 },
+ { "ULP_TX_LA_RDDATA_0", 0x8ec4, 0 },
+ { "ULP_TX_LA_WRPTR_0", 0x8ec8, 0 },
+ { "ULP_TX_LA_RESERVED_0", 0x8ecc, 0 },
+ { "ULP_TX_LA_RDPTR_1", 0x8ed0, 0 },
+ { "ULP_TX_LA_RDDATA_1", 0x8ed4, 0 },
+ { "ULP_TX_LA_WRPTR_1", 0x8ed8, 0 },
+ { "ULP_TX_LA_RESERVED_1", 0x8edc, 0 },
+ { "ULP_TX_LA_RDPTR_2", 0x8ee0, 0 },
+ { "ULP_TX_LA_RDDATA_2", 0x8ee4, 0 },
+ { "ULP_TX_LA_WRPTR_2", 0x8ee8, 0 },
+ { "ULP_TX_LA_RESERVED_2", 0x8eec, 0 },
+ { "ULP_TX_LA_RDPTR_3", 0x8ef0, 0 },
+ { "ULP_TX_LA_RDDATA_3", 0x8ef4, 0 },
+ { "ULP_TX_LA_WRPTR_3", 0x8ef8, 0 },
+ { "ULP_TX_LA_RESERVED_3", 0x8efc, 0 },
+ { "ULP_TX_LA_RDPTR_4", 0x8f00, 0 },
+ { "ULP_TX_LA_RDDATA_4", 0x8f04, 0 },
+ { "ULP_TX_LA_WRPTR_4", 0x8f08, 0 },
+ { "ULP_TX_LA_RESERVED_4", 0x8f0c, 0 },
+ { "ULP_TX_LA_RDPTR_5", 0x8f10, 0 },
+ { "ULP_TX_LA_RDDATA_5", 0x8f14, 0 },
+ { "ULP_TX_LA_WRPTR_5", 0x8f18, 0 },
+ { "ULP_TX_LA_RESERVED_5", 0x8f1c, 0 },
+ { "ULP_TX_LA_RDPTR_6", 0x8f20, 0 },
+ { "ULP_TX_LA_RDDATA_6", 0x8f24, 0 },
+ { "ULP_TX_LA_WRPTR_6", 0x8f28, 0 },
+ { "ULP_TX_LA_RESERVED_6", 0x8f2c, 0 },
+ { "ULP_TX_LA_RDPTR_7", 0x8f30, 0 },
+ { "ULP_TX_LA_RDDATA_7", 0x8f34, 0 },
+ { "ULP_TX_LA_WRPTR_7", 0x8f38, 0 },
+ { "ULP_TX_LA_RESERVED_7", 0x8f3c, 0 },
+ { "ULP_TX_LA_RDPTR_8", 0x8f40, 0 },
+ { "ULP_TX_LA_RDDATA_8", 0x8f44, 0 },
+ { "ULP_TX_LA_WRPTR_8", 0x8f48, 0 },
+ { "ULP_TX_LA_RESERVED_8", 0x8f4c, 0 },
+ { "ULP_TX_LA_RDPTR_9", 0x8f50, 0 },
+ { "ULP_TX_LA_RDDATA_9", 0x8f54, 0 },
+ { "ULP_TX_LA_WRPTR_9", 0x8f58, 0 },
+ { "ULP_TX_LA_RESERVED_9", 0x8f5c, 0 },
+ { "ULP_TX_LA_RDPTR_10", 0x8f60, 0 },
+ { "ULP_TX_LA_RDDATA_10", 0x8f64, 0 },
+ { "ULP_TX_LA_WRPTR_10", 0x8f68, 0 },
+ { "ULP_TX_LA_RESERVED_10", 0x8f6c, 0 },
+ { "ULP_TX_ASIC_DEBUG_CTRL", 0x8f70, 0 },
+ { "ULP_TX_CPL_TX_DATA_FLAGS_MASK", 0x8f88, 0 },
+ { "bypass_first", 26, 1 },
+ { "bypass_middle", 25, 1 },
+ { "bypass_last", 24, 1 },
+ { "push_first", 22, 1 },
+ { "push_middle", 21, 1 },
+ { "push_last", 20, 1 },
+ { "save_first", 18, 1 },
+ { "save_middle", 17, 1 },
+ { "save_last", 16, 1 },
+ { "flush_first", 14, 1 },
+ { "flush_middle", 13, 1 },
+ { "flush_last", 12, 1 },
+ { "urgent_first", 10, 1 },
+ { "urgent_middle", 9, 1 },
+ { "urgent_last", 8, 1 },
+ { "more_first", 6, 1 },
+ { "more_middle", 5, 1 },
+ { "more_last", 4, 1 },
+ { "shove_first", 2, 1 },
+ { "shove_middle", 1, 1 },
+ { "shove_last", 0, 1 },
+ { "ULP_TX_TLS_IND_CMD", 0x8fb8, 0 },
+ { "ULP_TX_TLS_IND_DATA", 0x8fbc, 0 },
+ { "ULP_TX_ASIC_DEBUG_0", 0x8f74, 0 },
+ { "ULP_TX_ASIC_DEBUG_1", 0x8f78, 0 },
+ { "ULP_TX_ASIC_DEBUG_2", 0x8f7c, 0 },
+ { "ULP_TX_ASIC_DEBUG_3", 0x8f80, 0 },
+ { "ULP_TX_ASIC_DEBUG_4", 0x8f84, 0 },
+ { NULL }
+};
+
+struct reg_info t6_pm_rx_regs[] = {
+ { "PM_RX_CFG", 0x8fc0, 0 },
+ { "ch1_output", 27, 5 },
+ { "strobe1", 16, 1 },
+ { "ch1_input", 11, 5 },
+ { "ch2_input", 6, 5 },
+ { "ch3_input", 1, 5 },
+ { "strobe0", 0, 1 },
+ { "PM_RX_MODE", 0x8fc4, 0 },
+ { "use_bundle_len", 4, 1 },
+ { "stat_to_ch", 3, 1 },
+ { "stat_from_ch", 1, 2 },
+ { "prefetch_enable", 0, 1 },
+ { "PM_RX_STAT_CONFIG", 0x8fc8, 0 },
+ { "PM_RX_STAT_COUNT", 0x8fcc, 0 },
+ { "PM_RX_DBG_CTRL", 0x8fd0, 0 },
+ { "OspiWrBusy", 21, 2 },
+ { "IspiWrBusy", 17, 4 },
+ { "PMDbgAddr", 0, 17 },
+ { "PM_RX_DBG_DATA", 0x8fd4, 0 },
+ { "PM_RX_INT_ENABLE", 0x8fd8, 0 },
+ { "ospi_overflow1", 28, 1 },
+ { "ospi_overflow0", 27, 1 },
+ { "ma_intf_sdc_err", 26, 1 },
+ { "bundle_len_ParErr", 25, 1 },
+ { "bundle_len_ovfl", 24, 1 },
+ { "sdc_err", 23, 1 },
+ { "zero_e_cmd_error", 22, 1 },
+ { "iespi0_fifo2x_Rx_framing_error", 21, 1 },
+ { "iespi1_fifo2x_Rx_framing_error", 20, 1 },
+ { "iespi2_fifo2x_Rx_framing_error", 19, 1 },
+ { "iespi3_fifo2x_Rx_framing_error", 18, 1 },
+ { "iespi0_Rx_framing_error", 17, 1 },
+ { "iespi1_Rx_framing_error", 16, 1 },
+ { "iespi2_Rx_framing_error", 15, 1 },
+ { "iespi3_Rx_framing_error", 14, 1 },
+ { "iespi0_Tx_framing_error", 13, 1 },
+ { "iespi1_Tx_framing_error", 12, 1 },
+ { "iespi2_Tx_framing_error", 11, 1 },
+ { "iespi3_Tx_framing_error", 10, 1 },
+ { "ocspi0_Rx_framing_error", 9, 1 },
+ { "ocspi1_Rx_framing_error", 8, 1 },
+ { "ocspi0_Tx_framing_error", 7, 1 },
+ { "ocspi1_Tx_framing_error", 6, 1 },
+ { "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
+ { "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
+ { "ocspi_par_error", 3, 1 },
+ { "db_options_par_error", 2, 1 },
+ { "iespi_par_error", 1, 1 },
+ { "e_pcmd_par_error", 0, 1 },
+ { "PM_RX_INT_CAUSE", 0x8fdc, 0 },
+ { "ospi_overflow1", 28, 1 },
+ { "ospi_overflow0", 27, 1 },
+ { "ma_intf_sdc_err", 26, 1 },
+ { "bundle_len_ParErr", 25, 1 },
+ { "bundle_len_ovfl", 24, 1 },
+ { "sdc_err", 23, 1 },
+ { "zero_e_cmd_error", 22, 1 },
+ { "iespi0_fifo2x_Rx_framing_error", 21, 1 },
+ { "iespi1_fifo2x_Rx_framing_error", 20, 1 },
+ { "iespi2_fifo2x_Rx_framing_error", 19, 1 },
+ { "iespi3_fifo2x_Rx_framing_error", 18, 1 },
+ { "iespi0_Rx_framing_error", 17, 1 },
+ { "iespi1_Rx_framing_error", 16, 1 },
+ { "iespi2_Rx_framing_error", 15, 1 },
+ { "iespi3_Rx_framing_error", 14, 1 },
+ { "iespi0_Tx_framing_error", 13, 1 },
+ { "iespi1_Tx_framing_error", 12, 1 },
+ { "iespi2_Tx_framing_error", 11, 1 },
+ { "iespi3_Tx_framing_error", 10, 1 },
+ { "ocspi0_Rx_framing_error", 9, 1 },
+ { "ocspi1_Rx_framing_error", 8, 1 },
+ { "ocspi0_Tx_framing_error", 7, 1 },
+ { "ocspi1_Tx_framing_error", 6, 1 },
+ { "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
+ { "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
+ { "ocspi_par_error", 3, 1 },
+ { "db_options_par_error", 2, 1 },
+ { "iespi_par_error", 1, 1 },
+ { "e_pcmd_par_error", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t6_pm_tx_regs[] = {
+ { "PM_TX_CFG", 0x8fe0, 0 },
+ { "ch1_output", 27, 5 },
+ { "ch2_output", 22, 5 },
+ { "ch3_output", 17, 5 },
+ { "strobe1", 16, 1 },
+ { "ch1_input", 11, 5 },
+ { "ch2_input", 6, 5 },
+ { "ch3_input", 1, 5 },
+ { "strobe0", 0, 1 },
+ { "PM_TX_MODE", 0x8fe4, 0 },
+ { "cong_thresh3", 25, 7 },
+ { "cong_thresh2", 18, 7 },
+ { "cong_thresh1", 11, 7 },
+ { "cong_thresh0", 4, 7 },
+ { "use_bundle_len", 3, 1 },
+ { "stat_channel", 1, 2 },
+ { "prefetch_enable", 0, 1 },
+ { "PM_TX_STAT_CONFIG", 0x8fe8, 0 },
+ { "PM_TX_STAT_COUNT", 0x8fec, 0 },
+ { "PM_TX_DBG_CTRL", 0x8ff0, 0 },
+ { "OspiWrBusy", 21, 4 },
+ { "IspiWrBusy", 17, 4 },
+ { "PMDbgAddr", 0, 17 },
+ { "PM_TX_DBG_DATA", 0x8ff4, 0 },
+ { "PM_TX_INT_ENABLE", 0x8ff8, 0 },
+ { "pcmd_len_ovfl0", 31, 1 },
+ { "pcmd_len_ovfl1", 30, 1 },
+ { "pcmd_len_ovfl2", 29, 1 },
+ { "zero_c_cmd_error", 28, 1 },
+ { "icspi0_fifo2x_Rx_framing_error", 27, 1 },
+ { "icspi1_fifo2x_Rx_framing_error", 26, 1 },
+ { "icspi2_fifo2x_Rx_framing_error", 25, 1 },
+ { "icspi3_fifo2x_Rx_framing_error", 24, 1 },
+ { "icspi0_Rx_framing_error", 23, 1 },
+ { "icspi1_Rx_framing_error", 22, 1 },
+ { "icspi2_Rx_framing_error", 21, 1 },
+ { "icspi3_Rx_framing_error", 20, 1 },
+ { "icspi0_Tx_framing_error", 19, 1 },
+ { "icspi1_Tx_framing_error", 18, 1 },
+ { "icspi2_Tx_framing_error", 17, 1 },
+ { "icspi3_Tx_framing_error", 16, 1 },
+ { "oespi0_Rx_framing_error", 15, 1 },
+ { "oespi1_Rx_framing_error", 14, 1 },
+ { "oespi2_Rx_framing_error", 13, 1 },
+ { "oespi3_Rx_framing_error", 12, 1 },
+ { "oespi0_Tx_framing_error", 11, 1 },
+ { "oespi1_Tx_framing_error", 10, 1 },
+ { "oespi2_Tx_framing_error", 9, 1 },
+ { "oespi3_Tx_framing_error", 8, 1 },
+ { "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
+ { "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
+ { "oespi2_ofifo2x_Tx_framing_error", 5, 1 },
+ { "oespi3_ofifo2x_Tx_framing_error", 4, 1 },
+ { "oespi_par_error", 3, 1 },
+ { "db_options_par_error", 2, 1 },
+ { "icspi_par_error", 1, 1 },
+ { "c_pcmd_par_error", 0, 1 },
+ { "PM_TX_INT_CAUSE", 0x8ffc, 0 },
+ { "pcmd_len_ovfl0", 31, 1 },
+ { "pcmd_len_ovfl1", 30, 1 },
+ { "pcmd_len_ovfl2", 29, 1 },
+ { "zero_c_cmd_error", 28, 1 },
+ { "icspi0_fifo2x_Rx_framing_error", 27, 1 },
+ { "icspi1_fifo2x_Rx_framing_error", 26, 1 },
+ { "icspi2_fifo2x_Rx_framing_error", 25, 1 },
+ { "icspi3_fifo2x_Rx_framing_error", 24, 1 },
+ { "icspi0_Rx_framing_error", 23, 1 },
+ { "icspi1_Rx_framing_error", 22, 1 },
+ { "icspi2_Rx_framing_error", 21, 1 },
+ { "icspi3_Rx_framing_error", 20, 1 },
+ { "icspi0_Tx_framing_error", 19, 1 },
+ { "icspi1_Tx_framing_error", 18, 1 },
+ { "icspi2_Tx_framing_error", 17, 1 },
+ { "icspi3_Tx_framing_error", 16, 1 },
+ { "oespi0_Rx_framing_error", 15, 1 },
+ { "oespi1_Rx_framing_error", 14, 1 },
+ { "oespi2_Rx_framing_error", 13, 1 },
+ { "oespi3_Rx_framing_error", 12, 1 },
+ { "oespi0_Tx_framing_error", 11, 1 },
+ { "oespi1_Tx_framing_error", 10, 1 },
+ { "oespi2_Tx_framing_error", 9, 1 },
+ { "oespi3_Tx_framing_error", 8, 1 },
+ { "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
+ { "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
+ { "oespi2_ofifo2x_Tx_framing_error", 5, 1 },
+ { "oespi3_ofifo2x_Tx_framing_error", 4, 1 },
+ { "ospi_or_bundle_len_par_err", 3, 1 },
+ { "db_options_par_error", 2, 1 },
+ { "icspi_par_error", 1, 1 },
+ { "c_pcmd_par_error", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t6_mps_regs[] = {
+ { "MPS_CMN_CTL", 0x9000, 0 },
+ { "TX_PORT_STATS_MODE", 8, 1 },
+ { "T5Mode", 7, 1 },
+ { "SpeedMode", 5, 2 },
+ { "LpbkCrdtCtrl", 4, 1 },
+ { "Detect8023", 3, 1 },
+ { "VFDirectAccess", 2, 1 },
+ { "NumPorts", 0, 2 },
+ { "MPS_INT_ENABLE", 0x9004, 0 },
+ { "StatIntEnb", 5, 1 },
+ { "TxIntEnb", 4, 1 },
+ { "RxIntEnb", 3, 1 },
+ { "TrcIntEnb", 2, 1 },
+ { "ClsIntEnb", 1, 1 },
+ { "PLIntEnb", 0, 1 },
+ { "MPS_INT_CAUSE", 0x9008, 0 },
+ { "StatInt", 5, 1 },
+ { "TxInt", 4, 1 },
+ { "RxInt", 3, 1 },
+ { "TrcInt", 2, 1 },
+ { "ClsInt", 1, 1 },
+ { "PLInt", 0, 1 },
+ { "MPS_CGEN_GLOBAL", 0x900c, 0 },
+ { "MPS_VF_TX_CTL_31_0", 0x9010, 0 },
+ { "MPS_VF_TX_CTL_63_32", 0x9014, 0 },
+ { "MPS_VF_TX_CTL_95_64", 0x9018, 0 },
+ { "MPS_VF_TX_CTL_127_96", 0x901c, 0 },
+ { "MPS_VF_TX_CTL_159_128", 0x9100, 0 },
+ { "MPS_VF_TX_CTL_191_160", 0x9104, 0 },
+ { "MPS_VF_TX_CTL_223_192", 0x9108, 0 },
+ { "MPS_VF_TX_CTL_255_224", 0x910c, 0 },
+ { "MPS_VF_RX_CTL_31_0", 0x9020, 0 },
+ { "MPS_VF_RX_CTL_63_32", 0x9024, 0 },
+ { "MPS_VF_RX_CTL_95_64", 0x9028, 0 },
+ { "MPS_VF_RX_CTL_127_96", 0x902c, 0 },
+ { "MPS_VF_RX_CTL_159_128", 0x9110, 0 },
+ { "MPS_VF_RX_CTL_191_160", 0x9114, 0 },
+ { "MPS_VF_RX_CTL_223_192", 0x9118, 0 },
+ { "MPS_VF_RX_CTL_255_224", 0x911c, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP0", 0x9030, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP1", 0x9034, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP2", 0x9038, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP3", 0x903c, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP0", 0x9040, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP1", 0x9044, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP2", 0x9048, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP3", 0x904c, 0 },
+ { "MPS_TP_CSIDE_MUX_CTL_P0", 0x9050, 0 },
+ { "MPS_TP_CSIDE_MUX_CTL_P1", 0x9054, 0 },
+ { "MPS_WOL_CTL_MODE", 0x9058, 0 },
+ { "MPS_FPGA_DEBUG", 0x9060, 0 },
+ { "FPGA_PTP_PORT", 9, 2 },
+ { "LPBK_EN", 8, 1 },
+ { "CH_MAP1", 2, 2 },
+ { "CH_MAP0", 0, 2 },
+ { "MPS_DEBUG_CTL", 0x9068, 0 },
+ { "DbgModeCtl_H", 11, 1 },
+ { "DbgSel_H", 6, 5 },
+ { "DbgModeCtl_L", 5, 1 },
+ { "DbgSel_L", 0, 5 },
+ { "MPS_DEBUG_DATA_REG_L", 0x906c, 0 },
+ { "MPS_DEBUG_DATA_REG_H", 0x9070, 0 },
+ { "MPS_TOP_SPARE", 0x9074, 0 },
+ { "TopSpare", 8, 24 },
+ { "oVlanSelLpbk3", 7, 1 },
+ { "oVlanSelLpbk2", 6, 1 },
+ { "oVlanSelLpbk1", 5, 1 },
+ { "oVlanSelLpbk0", 4, 1 },
+ { "oVlanSelMac3", 3, 1 },
+ { "oVlanSelMac2", 2, 1 },
+ { "oVlanSelMac1", 1, 1 },
+ { "oVlanSelMac0", 0, 1 },
+ { "MPS_BUILD_REVISION", 0x9078, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH0", 0x907c, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH1", 0x9080, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH2", 0x9084, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH3", 0x9088, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH4", 0x908c, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH5", 0x9090, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH6", 0x9094, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH7", 0x9098, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH8", 0x909c, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH9", 0x90a0, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH10", 0x90a4, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH11", 0x90a8, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH12", 0x90ac, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH13", 0x90b0, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH14", 0x90b4, 0 },
+ { "MPS_TX_PAUSE_DURATION_BUF_GRP_TH15", 0x90b8, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0", 0x90bc, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1", 0x90c0, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2", 0x90c4, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3", 0x90c8, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4", 0x90cc, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5", 0x90d0, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6", 0x90d4, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7", 0x90d8, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8", 0x90dc, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9", 0x90e0, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10", 0x90e4, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11", 0x90e8, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12", 0x90ec, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13", 0x90f0, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14", 0x90f4, 0 },
+ { "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15", 0x90f8, 0 },
+ { "MPS_FPGA_BIST_CFG_P0", 0x9120, 0 },
+ { "AddrMask", 16, 16 },
+ { "BaseAddr", 0, 16 },
+ { "MPS_FPGA_BIST_CFG_P1", 0x9124, 0 },
+ { "AddrMask", 16, 16 },
+ { "BaseAddr", 0, 16 },
+ { "MPS_PORT_CTL", 0x30000, 0 },
+ { "LpbkEn", 31, 1 },
+ { "TxEn", 30, 1 },
+ { "RxEn", 29, 1 },
+ { "PPPEn", 28, 1 },
+ { "FCSStripEn", 27, 1 },
+ { "PPPAndPause", 26, 1 },
+ { "PrioPPPEnMap", 16, 8 },
+ { "MPS_PORT_PAUSE_CTL", 0x30004, 0 },
+ { "MPS_PORT_TX_PAUSE_CTL", 0x30008, 0 },
+ { "RegSendOff", 24, 8 },
+ { "RegSendOn", 16, 8 },
+ { "SgeSendEn", 8, 8 },
+ { "RxSendEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_CTL2", 0x3000c, 0 },
+ { "MPS_PORT_RX_PAUSE_CTL", 0x30010, 0 },
+ { "RegHaltOn", 8, 8 },
+ { "RxHaltEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_STATUS", 0x30014, 0 },
+ { "RegSending", 16, 8 },
+ { "SgeSending", 8, 8 },
+ { "RxSending", 0, 8 },
+ { "MPS_PORT_RX_PAUSE_STATUS", 0x30018, 0 },
+ { "RegHalted", 8, 8 },
+ { "RxHalted", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_DEST_L", 0x3001c, 0 },
+ { "MPS_PORT_TX_PAUSE_DEST_H", 0x30020, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_L", 0x30024, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_H", 0x30028, 0 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3002c, 0 },
+ { "Prty7", 14, 2 },
+ { "Prty6", 12, 2 },
+ { "Prty5", 10, 2 },
+ { "Prty4", 8, 2 },
+ { "Prty3", 6, 2 },
+ { "Prty2", 4, 2 },
+ { "Prty1", 2, 2 },
+ { "Prty0", 0, 2 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x30030, 0 },
+ { "Prty7", 28, 4 },
+ { "Prty6", 24, 4 },
+ { "Prty5", 20, 4 },
+ { "Prty4", 16, 4 },
+ { "Prty3", 12, 4 },
+ { "Prty2", 8, 4 },
+ { "Prty1", 4, 4 },
+ { "Prty0", 0, 4 },
+ { "MPS_PORT_CTL", 0x34000, 0 },
+ { "LpbkEn", 31, 1 },
+ { "TxEn", 30, 1 },
+ { "RxEn", 29, 1 },
+ { "PPPEn", 28, 1 },
+ { "FCSStripEn", 27, 1 },
+ { "PPPAndPause", 26, 1 },
+ { "PrioPPPEnMap", 16, 8 },
+ { "MPS_PORT_PAUSE_CTL", 0x34004, 0 },
+ { "MPS_PORT_TX_PAUSE_CTL", 0x34008, 0 },
+ { "RegSendOff", 24, 8 },
+ { "RegSendOn", 16, 8 },
+ { "SgeSendEn", 8, 8 },
+ { "RxSendEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_CTL2", 0x3400c, 0 },
+ { "MPS_PORT_RX_PAUSE_CTL", 0x34010, 0 },
+ { "RegHaltOn", 8, 8 },
+ { "RxHaltEn", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_STATUS", 0x34014, 0 },
+ { "RegSending", 16, 8 },
+ { "SgeSending", 8, 8 },
+ { "RxSending", 0, 8 },
+ { "MPS_PORT_RX_PAUSE_STATUS", 0x34018, 0 },
+ { "RegHalted", 8, 8 },
+ { "RxHalted", 0, 8 },
+ { "MPS_PORT_TX_PAUSE_DEST_L", 0x3401c, 0 },
+ { "MPS_PORT_TX_PAUSE_DEST_H", 0x34020, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_L", 0x34024, 0 },
+ { "MPS_PORT_TX_PAUSE_SOURCE_H", 0x34028, 0 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3402c, 0 },
+ { "Prty7", 14, 2 },
+ { "Prty6", 12, 2 },
+ { "Prty5", 10, 2 },
+ { "Prty4", 8, 2 },
+ { "Prty3", 6, 2 },
+ { "Prty2", 4, 2 },
+ { "Prty1", 2, 2 },
+ { "Prty0", 0, 2 },
+ { "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x34030, 0 },
+ { "Prty7", 28, 4 },
+ { "Prty6", 24, 4 },
+ { "Prty5", 20, 4 },
+ { "Prty4", 16, 4 },
+ { "Prty3", 12, 4 },
+ { "Prty2", 8, 4 },
+ { "Prty1", 4, 4 },
+ { "Prty0", 0, 4 },
+ { "MPS_PF_CTL", 0x1e2c0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1e6c0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1eac0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1eec0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1f2c0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1f6c0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1fac0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_PF_CTL", 0x1fec0, 0 },
+ { "TxEn", 1, 1 },
+ { "RxEn", 0, 1 },
+ { "MPS_RX_CTL", 0x11000, 0 },
+ { "FILT_VLAN_SEL", 17, 1 },
+ { "CBA_EN", 16, 1 },
+ { "BLK_SNDR", 12, 4 },
+ { "CMPRS", 8, 4 },
+ { "SNF", 0, 8 },
+ { "MPS_RX_PORT_MUX_CTL", 0x11004, 0 },
+ { "CTL_P1", 4, 4 },
+ { "CTL_P0", 0, 4 },
+ { "MPS_RX_FIFO_0_CTL", 0x11008, 0 },
+ { "MPS_RX_FIFO_1_CTL", 0x1100c, 0 },
+ { "MPS_RX_FIFO_2_CTL", 0x11010, 0 },
+ { "MPS_RX_FIFO_3_CTL", 0x11014, 0 },
+ { "MPS_RX_PG_HYST_BG0", 0x11048, 0 },
+ { "EN", 31, 1 },
+ { "TH", 0, 11 },
+ { "MPS_RX_PG_HYST_BG1", 0x1104c, 0 },
+ { "EN", 31, 1 },
+ { "TH", 0, 11 },
+ { "MPS_RX_PG_HYST_BG2", 0x11050, 0 },
+ { "EN", 31, 1 },
+ { "TH", 0, 11 },
+ { "MPS_RX_PG_HYST_BG3", 0x11054, 0 },
+ { "EN", 31, 1 },
+ { "TH", 0, 11 },
+ { "MPS_RX_OCH_CTL", 0x11058, 0 },
+ { "DROP_WT", 27, 5 },
+ { "TRUNC_WT", 22, 5 },
+ { "DRAIN", 13, 5 },
+ { "DROP", 8, 5 },
+ { "STOP", 0, 5 },
+ { "MPS_RX_LPBK_BP0", 0x1105c, 0 },
+ { "MPS_RX_LPBK_BP1", 0x11060, 0 },
+ { "MPS_RX_LPBK_BP2", 0x11064, 0 },
+ { "MPS_RX_LPBK_BP3", 0x11068, 0 },
+ { "MPS_RX_PORT_GAP", 0x1106c, 0 },
+ { "MPS_RX_PERR_INT_CAUSE", 0x11074, 0 },
+ { "INT_ERR_INT", 24, 1 },
+ { "FF", 23, 1 },
+ { "RPLC", 19, 1 },
+ { "ATRB", 18, 1 },
+ { "PPM1", 10, 1 },
+ { "PPM0", 9, 1 },
+ { "MPS_RX_PERR_INT_ENABLE", 0x11078, 0 },
+ { "INT_ERR_INT", 24, 1 },
+ { "FF", 23, 1 },
+ { "RPLC", 19, 1 },
+ { "ATRB", 18, 1 },
+ { "PPM1", 10, 1 },
+ { "PPM0", 9, 1 },
+ { "MPS_RX_PERR_ENABLE", 0x1107c, 0 },
+ { "INT_ERR_INT", 24, 1 },
+ { "FF", 23, 1 },
+ { "RPLC", 19, 1 },
+ { "ATRB", 18, 1 },
+ { "PPM1", 10, 1 },
+ { "PPM0", 9, 1 },
+ { "MPS_RX_PERR_INJECT", 0x11080, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "MPS_RX_FUNC_INT_CAUSE", 0x11084, 0 },
+ { "MTU_ERR_INT3", 19, 1 },
+ { "MTU_ERR_INT2", 18, 1 },
+ { "MTU_ERR_INT1", 17, 1 },
+ { "MTU_ERR_INT0", 16, 1 },
+ { "SE_CNT_ERR_INT", 15, 1 },
+ { "FRM_ERR_INT", 14, 1 },
+ { "LEN_ERR_INT", 13, 1 },
+ { "INT_ERR_INT", 8, 5 },
+ { "PG_TH_INT7", 7, 1 },
+ { "PG_TH_INT6", 6, 1 },
+ { "PG_TH_INT5", 5, 1 },
+ { "PG_TH_INT4", 4, 1 },
+ { "PG_TH_INT3", 3, 1 },
+ { "PG_TH_INT2", 2, 1 },
+ { "PG_TH_INT1", 1, 1 },
+ { "PG_TH_INT0", 0, 1 },
+ { "MPS_RX_FUNC_INT_ENABLE", 0x11088, 0 },
+ { "MTU_ERR_INT3", 19, 1 },
+ { "MTU_ERR_INT2", 18, 1 },
+ { "MTU_ERR_INT1", 17, 1 },
+ { "MTU_ERR_INT0", 16, 1 },
+ { "SE_CNT_ERR_INT", 15, 1 },
+ { "FRM_ERR_INT", 14, 1 },
+ { "LEN_ERR_INT", 13, 1 },
+ { "INT_ERR_INT", 8, 5 },
+ { "PG_TH_INT7", 7, 1 },
+ { "PG_TH_INT6", 6, 1 },
+ { "PG_TH_INT5", 5, 1 },
+ { "PG_TH_INT4", 4, 1 },
+ { "PG_TH_INT3", 3, 1 },
+ { "PG_TH_INT2", 2, 1 },
+ { "PG_TH_INT1", 1, 1 },
+ { "PG_TH_INT0", 0, 1 },
+ { "MPS_RX_REPL_CTL", 0x11098, 0 },
+ { "MPS_RX_PPP_ATRB", 0x1109c, 0 },
+ { "ETYPE", 16, 16 },
+ { "OPCODE", 0, 16 },
+ { "MPS_RX_QFC0_ATRB", 0x110a0, 0 },
+ { "ETYPE", 16, 16 },
+ { "DA", 0, 16 },
+ { "MPS_RX_QFC1_ATRB", 0x110a4, 0 },
+ { "MPS_RX_PT_ARB0", 0x110a8, 0 },
+ { "LPBK_WT", 16, 14 },
+ { "MAC_WT", 0, 14 },
+ { "MPS_RX_PT_ARB1", 0x110ac, 0 },
+ { "LPBK_WT", 16, 14 },
+ { "MAC_WT", 0, 14 },
+ { "MPS_RX_PT_ARB2", 0x110b0, 0 },
+ { "LPBK_WT", 16, 14 },
+ { "MAC_WT", 0, 14 },
+ { "MPS_PF_OUT_EN", 0x110b4, 0 },
+ { "MPS_BMC_MTU", 0x110b8, 0 },
+ { "MPS_BMC_PKT_CNT", 0x110bc, 0 },
+ { "MPS_BMC_BYTE_CNT", 0x110c0, 0 },
+ { "MPS_PFVF_ATRB_CTL", 0x110c4, 0 },
+ { "RD_WRN", 31, 1 },
+ { "PFVF", 0, 9 },
+ { "MPS_PFVF_ATRB", 0x110c8, 0 },
+ { "PF", 28, 3 },
+ { "OFF", 18, 1 },
+ { "NV_DROP", 17, 1 },
+ { "MODE", 16, 1 },
+ { "FULL_FRAME_MODE", 14, 1 },
+ { "MTU", 0, 14 },
+ { "MPS_PFVF_ATRB_FLTR0", 0x110cc, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR1", 0x110d0, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR2", 0x110d4, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR3", 0x110d8, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR4", 0x110dc, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR5", 0x110e0, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR6", 0x110e4, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR7", 0x110e8, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR8", 0x110ec, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR9", 0x110f0, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR10", 0x110f4, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR11", 0x110f8, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR12", 0x110fc, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR13", 0x11100, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR14", 0x11104, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PFVF_ATRB_FLTR15", 0x11108, 0 },
+ { "VLAN_EN", 16, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_RPLC_MAP_CTL", 0x1110c, 0 },
+ { "RD_WRN", 31, 1 },
+ { "ADDR", 0, 10 },
+ { "MPS_PF_RPLCT_MAP", 0x11110, 0 },
+ { "MPS_VF_RPLCT_MAP0", 0x11114, 0 },
+ { "MPS_VF_RPLCT_MAP1", 0x11118, 0 },
+ { "MPS_VF_RPLCT_MAP2", 0x1111c, 0 },
+ { "MPS_VF_RPLCT_MAP3", 0x11120, 0 },
+ { "MPS_VF_RPLCT_MAP4", 0x11300, 0 },
+ { "MPS_VF_RPLCT_MAP5", 0x11304, 0 },
+ { "MPS_VF_RPLCT_MAP6", 0x11308, 0 },
+ { "MPS_VF_RPLCT_MAP7", 0x1130c, 0 },
+ { "MPS_MEM_DBG_CTL", 0x1112c, 0 },
+ { "PKD", 17, 1 },
+ { "PGD", 16, 1 },
+ { "ADDR", 0, 16 },
+ { "MPS_PKD_MEM_DATA0", 0x11130, 0 },
+ { "MPS_PKD_MEM_DATA1", 0x11134, 0 },
+ { "MPS_PKD_MEM_DATA2", 0x11138, 0 },
+ { "MPS_PGD_MEM_DATA", 0x1113c, 0 },
+ { "MPS_RX_SE_CNT_ERR", 0x11140, 0 },
+ { "MPS_RX_SE_CNT_CLR", 0x11144, 0 },
+ { "MPS_RX_SE_CNT_IN0", 0x11148, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN1", 0x1114c, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN2", 0x11150, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN3", 0x11154, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN4", 0x11158, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN5", 0x1115c, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN6", 0x11160, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_IN7", 0x11164, 0 },
+ { "SOP_CNT_PM", 24, 8 },
+ { "EOP_CNT_PM", 16, 8 },
+ { "SOP_CNT_IN", 8, 8 },
+ { "EOP_CNT_IN", 0, 8 },
+ { "MPS_RX_SE_CNT_OUT01", 0x11168, 0 },
+ { "SOP_CNT_1", 24, 8 },
+ { "EOP_CNT_1", 16, 8 },
+ { "SOP_CNT_0", 8, 8 },
+ { "EOP_CNT_0", 0, 8 },
+ { "MPS_RX_SE_CNT_OUT23", 0x1116c, 0 },
+ { "SOP_CNT_3", 24, 8 },
+ { "EOP_CNT_3", 16, 8 },
+ { "SOP_CNT_2", 8, 8 },
+ { "EOP_CNT_2", 0, 8 },
+ { "MPS_RX_SPI_ERR", 0x11170, 0 },
+ { "LEN_ERR", 21, 4 },
+ { "ERR", 0, 21 },
+ { "MPS_RX_IN_BUS_STATE", 0x11174, 0 },
+ { "ST3", 24, 8 },
+ { "ST2", 16, 8 },
+ { "ST1", 8, 8 },
+ { "ST0", 0, 8 },
+ { "MPS_RX_OUT_BUS_STATE", 0x11178, 0 },
+ { "ST_NCSI", 23, 9 },
+ { "ST_TP", 0, 23 },
+ { "MPS_RX_DBG_CTL", 0x1117c, 0 },
+ { "OUT_DBG_CHNL", 8, 3 },
+ { "DBG_PKD_QSEL", 7, 1 },
+ { "DBG_CDS_INV", 6, 1 },
+ { "IN_DBG_PORT", 3, 3 },
+ { "IN_DBG_CHNL", 0, 3 },
+ { "MPS_RX_SPARE", 0x11190, 0 },
+ { "MPS_RX_PTP_ETYPE", 0x11194, 0 },
+ { "PETYPE2", 16, 16 },
+ { "PETYPE1", 0, 16 },
+ { "MPS_RX_PTP_TCP", 0x11198, 0 },
+ { "PTCPORT2", 16, 16 },
+ { "PTCPORT1", 0, 16 },
+ { "MPS_RX_PTP_UDP", 0x1119c, 0 },
+ { "PUDPORT2", 16, 16 },
+ { "PUDPORT1", 0, 16 },
+ { "MPS_RX_PTP_CTL", 0x111a0, 0 },
+ { "MIN_PTP_SPACE", 24, 7 },
+ { "PUDP2EN", 20, 4 },
+ { "PUDP1EN", 16, 4 },
+ { "PTCP2EN", 12, 4 },
+ { "PTCP1EN", 8, 4 },
+ { "PETYPE2EN", 4, 4 },
+ { "PETYPE1EN", 0, 4 },
+ { "MPS_RX_PAUSE_GEN_TH_0_0", 0x111a4, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_0_1", 0x111a8, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_0_2", 0x111ac, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_0_3", 0x111b0, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_1_0", 0x111b4, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_1_1", 0x111b8, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_1_2", 0x111bc, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_1_3", 0x111c0, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_2_0", 0x111c4, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_2_1", 0x111c8, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_2_2", 0x111cc, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_2_3", 0x111d0, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_3_0", 0x111d4, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_3_1", 0x111d8, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_3_2", 0x111dc, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_PAUSE_GEN_TH_3_3", 0x111e0, 0 },
+ { "TH_HIGH", 16, 16 },
+ { "TH_LOW", 0, 16 },
+ { "MPS_RX_MAC_CLS_DROP_CNT0", 0x111e4, 0 },
+ { "MPS_RX_MAC_CLS_DROP_CNT1", 0x111e8, 0 },
+ { "MPS_RX_MAC_CLS_DROP_CNT2", 0x111ec, 0 },
+ { "MPS_RX_MAC_CLS_DROP_CNT3", 0x111f0, 0 },
+ { "MPS_RX_LPBK_CLS_DROP_CNT0", 0x111f4, 0 },
+ { "MPS_RX_LPBK_CLS_DROP_CNT1", 0x111f8, 0 },
+ { "MPS_RX_LPBK_CLS_DROP_CNT2", 0x111fc, 0 },
+ { "MPS_RX_LPBK_CLS_DROP_CNT3", 0x11200, 0 },
+ { "MPS_RX_CGEN", 0x11204, 0 },
+ { "MPS_RX_CGEN_NCSI", 12, 1 },
+ { "MPS_RX_CGEN_OUT", 8, 4 },
+ { "MPS_RX_CGEN_LPBK_IN", 4, 4 },
+ { "MPS_RX_CGEN_MAC_IN", 0, 4 },
+ { "MPS_RX_MAC_BG_PG_CNT0", 0x11208, 0 },
+ { "MAC_USED", 16, 11 },
+ { "MAC_ALLOC", 0, 11 },
+ { "MPS_RX_MAC_BG_PG_CNT1", 0x1120c, 0 },
+ { "MAC_USED", 16, 11 },
+ { "MAC_ALLOC", 0, 11 },
+ { "MPS_RX_MAC_BG_PG_CNT2", 0x11210, 0 },
+ { "MAC_USED", 16, 11 },
+ { "MAC_ALLOC", 0, 11 },
+ { "MPS_RX_MAC_BG_PG_CNT3", 0x11214, 0 },
+ { "MAC_USED", 16, 11 },
+ { "MAC_ALLOC", 0, 11 },
+ { "MPS_RX_LPBK_BG_PG_CNT0", 0x11218, 0 },
+ { "LPBK_USED", 16, 11 },
+ { "LPBK_ALLOC", 0, 11 },
+ { "MPS_RX_LPBK_BG_PG_CNT1", 0x1121c, 0 },
+ { "LPBK_USED", 16, 11 },
+ { "LPBK_ALLOC", 0, 11 },
+ { "MPS_RX_CONGESTION_THRESHOLD_BG0", 0x11220, 0 },
+ { "CONG_EN", 31, 1 },
+ { "CONG_TH", 0, 20 },
+ { "MPS_RX_CONGESTION_THRESHOLD_BG1", 0x11224, 0 },
+ { "CONG_EN", 31, 1 },
+ { "CONG_TH", 0, 20 },
+ { "MPS_RX_CONGESTION_THRESHOLD_BG2", 0x11228, 0 },
+ { "CONG_EN", 31, 1 },
+ { "CONG_TH", 0, 20 },
+ { "MPS_RX_CONGESTION_THRESHOLD_BG3", 0x1122c, 0 },
+ { "CONG_EN", 31, 1 },
+ { "CONG_TH", 0, 20 },
+ { "MPS_RX_GRE_PROT_TYPE", 0x11230, 0 },
+ { "NVGRE_EN", 9, 1 },
+ { "GRE_EN", 8, 1 },
+ { "GRE", 0, 8 },
+ { "MPS_RX_VXLAN_TYPE", 0x11234, 0 },
+ { "VXLAN_EN", 16, 1 },
+ { "VXLAN", 0, 16 },
+ { "MPS_RX_GENEVE_TYPE", 0x11238, 0 },
+ { "GENEVE_EN", 16, 1 },
+ { "GENEVE", 0, 16 },
+ { "MPS_RX_INNER_HDR_IVLAN", 0x1123c, 0 },
+ { "IVLAN_EN", 16, 1 },
+ { "IVLAN_ETYPE", 0, 16 },
+ { "MPS_RX_ENCAP_NVGRE", 0x11240, 0 },
+ { "ETYPE_EN", 16, 1 },
+ { "ETYPE", 0, 16 },
+ { "MPS_RX_ENCAP_GENEVE", 0x11244, 0 },
+ { "ETYPE_EN", 16, 1 },
+ { "ETYPE", 0, 16 },
+ { "MPS_RX_TCP", 0x11248, 0 },
+ { "PROT_TYPE_EN", 8, 1 },
+ { "PROT_TYPE", 0, 8 },
+ { "MPS_RX_UDP", 0x1124c, 0 },
+ { "PROT_TYPE_EN", 8, 1 },
+ { "PROT_TYPE", 0, 8 },
+ { "MPS_RX_PAUSE", 0x11250, 0 },
+ { "MPS_RX_LENGTH", 0x11254, 0 },
+ { "SAP_VALUE", 16, 16 },
+ { "LENGTH_ETYPE", 0, 16 },
+ { "MPS_RX_CTL_ORG", 0x11258, 0 },
+ { "CTL_VALUE", 24, 8 },
+ { "ORG_VALUE", 0, 24 },
+ { "MPS_RX_IPV4", 0x1125c, 0 },
+ { "MPS_RX_IPV6", 0x11260, 0 },
+ { "MPS_RX_TTL", 0x11264, 0 },
+ { "TTL_IPV4", 10, 8 },
+ { "TTL_IPV6", 2, 8 },
+ { "TTL_CHK_EN_IPV4", 1, 1 },
+ { "TTL_CHK_EN_IPV6", 0, 1 },
+ { "MPS_RX_DEFAULT_VNI", 0x11268, 0 },
+ { "MPS_RX_PRS_CTL", 0x1126c, 0 },
+ { "CTL_CHK_EN", 28, 1 },
+ { "ORG_CHK_EN", 27, 1 },
+ { "SAP_CHK_EN", 26, 1 },
+ { "VXLAN_FLAG_CHK_EN", 25, 1 },
+ { "VXLAN_FLAG_MASK", 17, 8 },
+ { "VXLAN_FLAG", 9, 8 },
+ { "GRE_VER_CHK_EN", 8, 1 },
+ { "GRE_VER", 5, 3 },
+ { "GENEVE_VER_CHK_EN", 4, 1 },
+ { "GENEVE_VER", 2, 2 },
+ { "DIP_EN", 1, 1 },
+ { "MPS_RX_PRS_CTL_2", 0x11270, 0 },
+ { "EN_UDP_CSUM_CHK", 4, 1 },
+ { "EN_UDP_LEN_CHK", 3, 1 },
+ { "EN_IP_CSUM_CHK", 2, 1 },
+ { "EN_IP_PAYLOAD_LEN_CHK", 1, 1 },
+ { "IPV6_UDP_CSUM_COMPAT", 0, 1 },
+ { "MPS_RX_MPS2NCSI_CNT", 0x11274, 0 },
+ { "MPS_RX_MAX_TNL_HDR_LEN", 0x11278, 0 },
+ { "MPS_RX_PAUSE_DA_H", 0x1127c, 0 },
+ { "MPS_RX_PAUSE_DA_L", 0x11280, 0 },
+ { "MPS_RX_CNT_NVGRE_PKT_MAC0", 0x11284, 0 },
+ { "MPS_RX_CNT_VXLAN_PKT_MAC0", 0x11288, 0 },
+ { "MPS_RX_CNT_GENEVE_PKT_MAC0", 0x1128c, 0 },
+ { "MPS_RX_CNT_TNL_ERR_PKT_MAC0", 0x11290, 0 },
+ { "MPS_RX_CNT_NVGRE_PKT_MAC1", 0x11294, 0 },
+ { "MPS_RX_CNT_VXLAN_PKT_MAC1", 0x11298, 0 },
+ { "MPS_RX_CNT_GENEVE_PKT_MAC1", 0x1129c, 0 },
+ { "MPS_RX_CNT_TNL_ERR_PKT_MAC1", 0x112a0, 0 },
+ { "MPS_RX_CNT_NVGRE_PKT_LPBK0", 0x112a4, 0 },
+ { "MPS_RX_CNT_VXLAN_PKT_LPBK0", 0x112a8, 0 },
+ { "MPS_RX_CNT_GENEVE_PKT_LPBK0", 0x112ac, 0 },
+ { "MPS_RX_CNT_TNL_ERR_PKT_LPBK0", 0x112b0, 0 },
+ { "MPS_RX_CNT_NVGRE_PKT_LPBK1", 0x112b4, 0 },
+ { "MPS_RX_CNT_VXLAN_PKT_LPBK1", 0x112b8, 0 },
+ { "MPS_RX_CNT_GENEVE_PKT_LPBK1", 0x112bc, 0 },
+ { "MPS_RX_CNT_TNL_ERR_PKT_LPBK1", 0x112c0, 0 },
+ { "MPS_RX_CNT_NVGRE_PKT_TO_TP0", 0x112c4, 0 },
+ { "MPS_RX_CNT_VXLAN_PKT_TO_TP0", 0x112c8, 0 },
+ { "MPS_RX_CNT_GENEVE_PKT_TO_TP0", 0x112cc, 0 },
+ { "MPS_RX_CNT_TNL_ERR_PKT_TO_TP0", 0x112d0, 0 },
+ { "MPS_RX_CNT_NVGRE_PKT_TO_TP1", 0x112d4, 0 },
+ { "MPS_RX_CNT_VXLAN_PKT_TO_TP1", 0x112d8, 0 },
+ { "MPS_RX_CNT_GENEVE_PKT_TO_TP1", 0x112dc, 0 },
+ { "MPS_RX_CNT_TNL_ERR_PKT_TO_TP1", 0x112e0, 0 },
+ { "MPS_PORT_RX_CTL", 0x30100, 0 },
+ { "HASH_PRIO_SEL_LPBK", 25, 1 },
+ { "HASH_PRIO_SEL_MAC", 24, 1 },
+ { "HASH_EN_LPBK", 23, 1 },
+ { "HASH_EN_MAC", 22, 1 },
+ { "PTP_FWD_UP", 21, 1 },
+ { "NO_RPLCT_M", 20, 1 },
+ { "RPLCT_SEL_L", 18, 2 },
+ { "FLTR_VLAN_SEL", 17, 1 },
+ { "PRIO_VLAN_SEL", 16, 1 },
+ { "CHK_8023_LEN_M", 15, 1 },
+ { "CHK_8023_LEN_L", 14, 1 },
+ { "NIV_DROP", 13, 1 },
+ { "NOV_DROP", 12, 1 },
+ { "CLS_PRT", 11, 1 },
+ { "RX_QFC_EN", 10, 1 },
+ { "QFC_FWD_UP", 9, 1 },
+ { "PPP_FWD_UP", 8, 1 },
+ { "PAUSE_FWD_UP", 7, 1 },
+ { "LPBK_BP", 6, 1 },
+ { "PASS_NO_MATCH", 5, 1 },
+ { "IVLAN_EN", 4, 1 },
+ { "OVLAN_EN3", 3, 1 },
+ { "OVLAN_EN2", 2, 1 },
+ { "OVLAN_EN1", 1, 1 },
+ { "OVLAN_EN0", 0, 1 },
+ { "MPS_PORT_RX_MTU", 0x30104, 0 },
+ { "MPS_PORT_RX_PF_MAP", 0x30108, 0 },
+ { "MPS_PORT_RX_VF_MAP0", 0x3010c, 0 },
+ { "MPS_PORT_RX_VF_MAP1", 0x30110, 0 },
+ { "MPS_PORT_RX_VF_MAP2", 0x30114, 0 },
+ { "MPS_PORT_RX_VF_MAP3", 0x30118, 0 },
+ { "MPS_PORT_RX_VF_MAP4", 0x30150, 0 },
+ { "MPS_PORT_RX_VF_MAP5", 0x30154, 0 },
+ { "MPS_PORT_RX_VF_MAP6", 0x30158, 0 },
+ { "MPS_PORT_RX_VF_MAP7", 0x3015c, 0 },
+ { "MPS_PORT_RX_IVLAN", 0x3011c, 0 },
+ { "MPS_PORT_RX_OVLAN0", 0x30120, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN1", 0x30124, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN2", 0x30128, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN3", 0x3012c, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_RSS_HASH", 0x30130, 0 },
+ { "MPS_PORT_RX_RSS_CONTROL", 0x30134, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_CTL1", 0x30138, 0 },
+ { "FIXED_PFVF_MAC", 14, 1 },
+ { "FIXED_PFVF_LPBK", 13, 1 },
+ { "FIXED_PFVF_LPBK_OV", 12, 1 },
+ { "FIXED_PF", 9, 3 },
+ { "FIXED_VF_VLD", 8, 1 },
+ { "FIXED_VF", 0, 8 },
+ { "MPS_PORT_RX_SPARE", 0x3013c, 0 },
+ { "MPS_PORT_RX_PTP_RSS_HASH", 0x30140, 0 },
+ { "MPS_PORT_RX_PTP_RSS_CONTROL", 0x30144, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_TS_VLD", 0x30148, 0 },
+ { "MPS_PORT_RX_TNL_LKP_INNER_SEL", 0x3014c, 0 },
+ { "MPS_PORT_RX_PRS_DEBUG_FLAG_MAC", 0x30160, 0 },
+ { "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+ { "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+ { "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+ { "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+ { "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+ { "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+ { "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+ { "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+ { "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+ { "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+ { "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+ { "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+ { "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+ { "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+ { "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+ { "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+ { "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+ { "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+ { "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+ { "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+ { "Err_Tnl_Hdr_Len", 11, 1 },
+ { "non_runt_frame", 10, 1 },
+ { "Inner_VLAN_VLD", 9, 1 },
+ { "Err_IP_Payload_Len", 8, 1 },
+ { "Err_UDP_Payload_Len", 7, 1 },
+ { "MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK", 0x30164, 0 },
+ { "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+ { "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+ { "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+ { "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+ { "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+ { "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+ { "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+ { "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+ { "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+ { "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+ { "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+ { "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+ { "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+ { "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+ { "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+ { "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+ { "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+ { "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+ { "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+ { "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+ { "Err_Tnl_Hdr_Len", 11, 1 },
+ { "Inner_VLAN_VLD", 10, 1 },
+ { "Err_IP_Payload_Len", 9, 1 },
+ { "Err_UDP_Payload_Len", 8, 1 },
+ { "MPS_PORT_RX_REPL_VECT_SEL", 0x30168, 0 },
+ { "DIS_REPL_VECT_SEL", 4, 1 },
+ { "REPL_VECT_SEL", 0, 4 },
+ { "MPS_PORT_RX_CTL", 0x34100, 0 },
+ { "HASH_PRIO_SEL_LPBK", 25, 1 },
+ { "HASH_PRIO_SEL_MAC", 24, 1 },
+ { "HASH_EN_LPBK", 23, 1 },
+ { "HASH_EN_MAC", 22, 1 },
+ { "PTP_FWD_UP", 21, 1 },
+ { "NO_RPLCT_M", 20, 1 },
+ { "RPLCT_SEL_L", 18, 2 },
+ { "FLTR_VLAN_SEL", 17, 1 },
+ { "PRIO_VLAN_SEL", 16, 1 },
+ { "CHK_8023_LEN_M", 15, 1 },
+ { "CHK_8023_LEN_L", 14, 1 },
+ { "NIV_DROP", 13, 1 },
+ { "NOV_DROP", 12, 1 },
+ { "CLS_PRT", 11, 1 },
+ { "RX_QFC_EN", 10, 1 },
+ { "QFC_FWD_UP", 9, 1 },
+ { "PPP_FWD_UP", 8, 1 },
+ { "PAUSE_FWD_UP", 7, 1 },
+ { "LPBK_BP", 6, 1 },
+ { "PASS_NO_MATCH", 5, 1 },
+ { "IVLAN_EN", 4, 1 },
+ { "OVLAN_EN3", 3, 1 },
+ { "OVLAN_EN2", 2, 1 },
+ { "OVLAN_EN1", 1, 1 },
+ { "OVLAN_EN0", 0, 1 },
+ { "MPS_PORT_RX_MTU", 0x34104, 0 },
+ { "MPS_PORT_RX_PF_MAP", 0x34108, 0 },
+ { "MPS_PORT_RX_VF_MAP0", 0x3410c, 0 },
+ { "MPS_PORT_RX_VF_MAP1", 0x34110, 0 },
+ { "MPS_PORT_RX_VF_MAP2", 0x34114, 0 },
+ { "MPS_PORT_RX_VF_MAP3", 0x34118, 0 },
+ { "MPS_PORT_RX_VF_MAP4", 0x34150, 0 },
+ { "MPS_PORT_RX_VF_MAP5", 0x34154, 0 },
+ { "MPS_PORT_RX_VF_MAP6", 0x34158, 0 },
+ { "MPS_PORT_RX_VF_MAP7", 0x3415c, 0 },
+ { "MPS_PORT_RX_IVLAN", 0x3411c, 0 },
+ { "MPS_PORT_RX_OVLAN0", 0x34120, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN1", 0x34124, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN2", 0x34128, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_OVLAN3", 0x3412c, 0 },
+ { "OVLAN_MASK", 16, 16 },
+ { "OVLAN_ETYPE", 0, 16 },
+ { "MPS_PORT_RX_RSS_HASH", 0x34130, 0 },
+ { "MPS_PORT_RX_RSS_CONTROL", 0x34134, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_CTL1", 0x34138, 0 },
+ { "FIXED_PFVF_MAC", 14, 1 },
+ { "FIXED_PFVF_LPBK", 13, 1 },
+ { "FIXED_PFVF_LPBK_OV", 12, 1 },
+ { "FIXED_PF", 9, 3 },
+ { "FIXED_VF_VLD", 8, 1 },
+ { "FIXED_VF", 0, 8 },
+ { "MPS_PORT_RX_SPARE", 0x3413c, 0 },
+ { "MPS_PORT_RX_PTP_RSS_HASH", 0x34140, 0 },
+ { "MPS_PORT_RX_PTP_RSS_CONTROL", 0x34144, 0 },
+ { "RSS_CTRL", 16, 8 },
+ { "QUE_NUM", 0, 16 },
+ { "MPS_PORT_RX_TS_VLD", 0x34148, 0 },
+ { "MPS_PORT_RX_TNL_LKP_INNER_SEL", 0x3414c, 0 },
+ { "MPS_PORT_RX_PRS_DEBUG_FLAG_MAC", 0x34160, 0 },
+ { "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+ { "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+ { "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+ { "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+ { "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+ { "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+ { "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+ { "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+ { "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+ { "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+ { "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+ { "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+ { "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+ { "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+ { "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+ { "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+ { "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+ { "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+ { "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+ { "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+ { "Err_Tnl_Hdr_Len", 11, 1 },
+ { "non_runt_frame", 10, 1 },
+ { "Inner_VLAN_VLD", 9, 1 },
+ { "Err_IP_Payload_Len", 8, 1 },
+ { "Err_UDP_Payload_Len", 7, 1 },
+ { "MPS_PORT_RX_PRS_DEBUG_FLAG_LPBK", 0x34164, 0 },
+ { "Outer_IPv4_n_Inner_IPv4", 31, 1 },
+ { "Outer_IPv4_n_Inner_IPv6", 30, 1 },
+ { "Outer_IPv6_n_Inner_IPv4", 29, 1 },
+ { "Outer_IPv6_n_Inner_IPv6", 28, 1 },
+ { "Outer_IPv4_n_VLAN_NVGRE", 27, 1 },
+ { "Outer_IPv6_n_VLAN_NVGRE", 26, 1 },
+ { "Outer_IPv4_n_Double_VLAN_NVGRE", 25, 1 },
+ { "Outer_IPv6_n_Double_VLAN_NVGRE", 24, 1 },
+ { "Outer_IPv4_n_VLAN_GRE", 23, 1 },
+ { "Outer_IPv6_n_VLAN_GRE", 22, 1 },
+ { "Outer_IPv4_n_Double_VLAN_GRE", 21, 1 },
+ { "Outer_IPv6_n_Double_VLAN_GRE", 20, 1 },
+ { "Outer_IPv4_n_VLAN_VXLAN", 19, 1 },
+ { "Outer_IPv6_n_VLAN_VXLAN", 18, 1 },
+ { "Outer_IPv4_n_Double_VLAN_VXLAN", 17, 1 },
+ { "Outer_IPv6_n_Double_VLAN_VXLAN", 16, 1 },
+ { "Outer_IPv4_n_VLAN_GENEVE", 15, 1 },
+ { "Outer_IPv6_n_VLAN_GENEVE", 14, 1 },
+ { "Outer_IPv4_n_Double_VLAN_GENEVE", 13, 1 },
+ { "Outer_IPv6_n_Double_VLAN_GENEVE", 12, 1 },
+ { "Err_Tnl_Hdr_Len", 11, 1 },
+ { "Inner_VLAN_VLD", 10, 1 },
+ { "Err_IP_Payload_Len", 9, 1 },
+ { "Err_UDP_Payload_Len", 8, 1 },
+ { "MPS_PORT_RX_REPL_VECT_SEL", 0x34168, 0 },
+ { "DIS_REPL_VECT_SEL", 4, 1 },
+ { "REPL_VECT_SEL", 0, 4 },
+ { "MPS_TX_PRTY_SEL", 0x9400, 0 },
+ { "Ch2_Prty", 12, 3 },
+ { "Ch1_Prty", 8, 3 },
+ { "Ch0_Prty", 4, 3 },
+ { "TP_Source", 2, 2 },
+ { "NCSI_Source", 0, 2 },
+ { "MPS_TX_INT_ENABLE", 0x9404, 0 },
+ { "PortErr", 16, 1 },
+ { "FRMERR", 15, 1 },
+ { "SECNTERR", 14, 1 },
+ { "BUBBLE", 13, 1 },
+ { "TxDescFifo", 9, 4 },
+ { "TxDataFifo", 5, 4 },
+ { "Ncsi", 4, 1 },
+ { "TP", 0, 4 },
+ { "MPS_TX_INT_CAUSE", 0x9408, 0 },
+ { "PortErr", 16, 1 },
+ { "FRMERR", 15, 1 },
+ { "SECNTERR", 14, 1 },
+ { "BUBBLE", 13, 1 },
+ { "TxDescFifo", 9, 4 },
+ { "TxDataFifo", 5, 4 },
+ { "Ncsi", 4, 1 },
+ { "TP", 0, 4 },
+ { "MPS_TX_NCSI2MPS_CNT", 0x940c, 0 },
+ { "MPS_TX_PERR_ENABLE", 0x9410, 0 },
+ { "TxDescFifo", 9, 4 },
+ { "TxDataFifo", 5, 4 },
+ { "Ncsi", 4, 1 },
+ { "TP", 0, 4 },
+ { "MPS_TX_PERR_INJECT", 0x9414, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "MPS_TX_SE_CNT_TP01", 0x9418, 0 },
+ { "SOP_CNT_1", 24, 8 },
+ { "EOP_CNT_1", 16, 8 },
+ { "SOP_CNT_0", 8, 8 },
+ { "EOP_CNT_0", 0, 8 },
+ { "MPS_TX_SE_CNT_TP23", 0x941c, 0 },
+ { "SOP_CNT_3", 24, 8 },
+ { "EOP_CNT_3", 16, 8 },
+ { "SOP_CNT_2", 8, 8 },
+ { "EOP_CNT_2", 0, 8 },
+ { "MPS_TX_SE_CNT_MAC01", 0x9420, 0 },
+ { "SOP_CNT_1", 24, 8 },
+ { "EOP_CNT_1", 16, 8 },
+ { "SOP_CNT_0", 8, 8 },
+ { "EOP_CNT_0", 0, 8 },
+ { "MPS_TX_SE_CNT_MAC23", 0x9424, 0 },
+ { "SOP_CNT_3", 24, 8 },
+ { "EOP_CNT_3", 16, 8 },
+ { "SOP_CNT_2", 8, 8 },
+ { "EOP_CNT_2", 0, 8 },
+ { "MPS_TX_SECNT_SPI_BUBBLE_ERR", 0x9428, 0 },
+ { "Bubble", 16, 8 },
+ { "Spi", 8, 8 },
+ { "SeCnt", 0, 8 },
+ { "MPS_TX_SECNT_BUBBLE_CLR", 0x942c, 0 },
+ { "NcsiSeCnt", 20, 1 },
+ { "LpbkSeCnt", 16, 4 },
+ { "Bubble", 8, 8 },
+ { "SeCnt", 0, 8 },
+ { "MPS_TX_PORT_ERR", 0x9430, 0 },
+ { "Lpbkpt3", 7, 1 },
+ { "Lpbkpt2", 6, 1 },
+ { "Lpbkpt1", 5, 1 },
+ { "Lpbkpt0", 4, 1 },
+ { "pt3", 3, 1 },
+ { "pt2", 2, 1 },
+ { "pt1", 1, 1 },
+ { "pt0", 0, 1 },
+ { "MPS_TX_LPBK_DROP_BP_CTL_CH0", 0x9434, 0 },
+ { "BpEn", 1, 1 },
+ { "DropEn", 0, 1 },
+ { "MPS_TX_LPBK_DROP_BP_CTL_CH1", 0x9438, 0 },
+ { "BpEn", 1, 1 },
+ { "DropEn", 0, 1 },
+ { "MPS_TX_LPBK_DROP_BP_CTL_CH2", 0x943c, 0 },
+ { "BpEn", 1, 1 },
+ { "DropEn", 0, 1 },
+ { "MPS_TX_LPBK_DROP_BP_CTL_CH3", 0x9440, 0 },
+ { "BpEn", 1, 1 },
+ { "DropEn", 0, 1 },
+ { "MPS_TX_DEBUG_REG_TP2TX_10", 0x9444, 0 },
+ { "SOPCh1", 31, 1 },
+ { "EOPCh1", 30, 1 },
+ { "SizeCh1", 27, 3 },
+ { "ErrCh1", 26, 1 },
+ { "FullCh1", 25, 1 },
+ { "ValidCh1", 24, 1 },
+ { "DataCh1", 16, 8 },
+ { "SOPCh0", 15, 1 },
+ { "EOPCh0", 14, 1 },
+ { "SizeCh0", 11, 3 },
+ { "ErrCh0", 10, 1 },
+ { "FullCh0", 9, 1 },
+ { "ValidCh0", 8, 1 },
+ { "DataCh0", 0, 8 },
+ { "MPS_TX_DEBUG_REG_TP2TX_32", 0x9448, 0 },
+ { "SOPCh3", 31, 1 },
+ { "EOPCh3", 30, 1 },
+ { "SizeCh3", 27, 3 },
+ { "ErrCh3", 26, 1 },
+ { "FullCh3", 25, 1 },
+ { "ValidCh3", 24, 1 },
+ { "DataCh3", 16, 8 },
+ { "SOPCh2", 15, 1 },
+ { "EOPCh2", 14, 1 },
+ { "SizeCh2", 11, 3 },
+ { "ErrCh2", 10, 1 },
+ { "FullCh2", 9, 1 },
+ { "ValidCh2", 8, 1 },
+ { "DataCh2", 0, 8 },
+ { "MPS_TX_DEBUG_REG_TX2MAC_10", 0x944c, 0 },
+ { "SOPPt1", 31, 1 },
+ { "EOPPt1", 30, 1 },
+ { "SizePt1", 27, 3 },
+ { "ErrPt1", 26, 1 },
+ { "FullPt1", 25, 1 },
+ { "ValidPt1", 24, 1 },
+ { "DataPt1", 16, 8 },
+ { "SOPPt0", 15, 1 },
+ { "EOPPt0", 14, 1 },
+ { "SizePt0", 11, 3 },
+ { "ErrPt0", 10, 1 },
+ { "FullPt0", 9, 1 },
+ { "ValidPt0", 8, 1 },
+ { "DataPt0", 0, 8 },
+ { "MPS_TX_DEBUG_REG_TX2MAC_32", 0x9450, 0 },
+ { "SOPPt3", 31, 1 },
+ { "EOPPt3", 30, 1 },
+ { "SizePt3", 27, 3 },
+ { "ErrPt3", 26, 1 },
+ { "FullPt3", 25, 1 },
+ { "ValidPt3", 24, 1 },
+ { "DataPt3", 16, 8 },
+ { "SOPPt2", 15, 1 },
+ { "EOPPt2", 14, 1 },
+ { "SizePt2", 11, 3 },
+ { "ErrPt2", 10, 1 },
+ { "FullPt2", 9, 1 },
+ { "ValidPt2", 8, 1 },
+ { "DataPt2", 0, 8 },
+ { "MPS_TX_SGE_CH_PAUSE_IGNR", 0x9454, 0 },
+ { "MPS_TX_DEBUG_SUBPART_SEL", 0x9458, 0 },
+ { "SubPrtH", 11, 5 },
+ { "PortH", 8, 3 },
+ { "SubPrtL", 3, 5 },
+ { "PortL", 0, 3 },
+ { "MPS_TX_PAD_CTL", 0x945c, 0 },
+ { "LpbkPadEnPt3", 7, 1 },
+ { "LpbkPadEnPt2", 6, 1 },
+ { "LpbkPadEnPt1", 5, 1 },
+ { "LpbkPadEnPt0", 4, 1 },
+ { "MacPadEnPt3", 3, 1 },
+ { "MacPadEnPt2", 2, 1 },
+ { "MacPadEnPt1", 1, 1 },
+ { "MacPadEnPt0", 0, 1 },
+ { "MPS_TX_PFVF_PORT_DROP_TP", 0x9460, 0 },
+ { "TP2MPS_Ch1", 8, 8 },
+ { "TP2MPS_Ch0", 0, 8 },
+ { "MPS_TX_PFVF_PORT_DROP_NCSI", 0x9464, 0 },
+ { "MPS_TX_PFVF_PORT_DROP_CTL", 0x9468, 0 },
+ { "PFNOVFDROP", 5, 1 },
+ { "NCSI_Ch4_CLR", 4, 1 },
+ { "TP2MPS_Ch1_CLR", 1, 1 },
+ { "TP2MPS_Ch0_CLR", 0, 1 },
+ { "MPS_TX_CGEN", 0x946c, 0 },
+ { "TxOutLpbk3_CGEN", 31, 1 },
+ { "TxOutLpbk2_CGEN", 30, 1 },
+ { "TxOutLpbk1_CGEN", 29, 1 },
+ { "TxOutLpbk0_CGEN", 28, 1 },
+ { "TxOutMAC3_CGEN", 27, 1 },
+ { "TxOutMAC2_CGEN", 26, 1 },
+ { "TxOutMAC1_CGEN", 25, 1 },
+ { "TxOutMAC0_CGEN", 24, 1 },
+ { "TxSchLpbk3_CGEN", 23, 1 },
+ { "TxSchLpbk2_CGEN", 22, 1 },
+ { "TxSchLpbk1_CGEN", 21, 1 },
+ { "TxSchLpbk0_CGEN", 20, 1 },
+ { "TxSchMAC3_CGEN", 19, 1 },
+ { "TxSchMAC2_CGEN", 18, 1 },
+ { "TxSchMAC1_CGEN", 17, 1 },
+ { "TxSchMAC0_CGEN", 16, 1 },
+ { "TxInCh4_CGEN", 15, 1 },
+ { "TxInCh3_CGEN", 14, 1 },
+ { "TxInCh2_CGEN", 13, 1 },
+ { "TxInCh1_CGEN", 12, 1 },
+ { "TxInCh0_CGEN", 11, 1 },
+ { "MPS_TX_CGEN_DYNAMIC", 0x9470, 0 },
+ { "TxOutLpbk3_CGEN", 31, 1 },
+ { "TxOutLpbk2_CGEN", 30, 1 },
+ { "TxOutLpbk1_CGEN", 29, 1 },
+ { "TxOutLpbk0_CGEN", 28, 1 },
+ { "TxOutMAC3_CGEN", 27, 1 },
+ { "TxOutMAC2_CGEN", 26, 1 },
+ { "TxOutMAC1_CGEN", 25, 1 },
+ { "TxOutMAC0_CGEN", 24, 1 },
+ { "TxSchLpbk3_CGEN", 23, 1 },
+ { "TxSchLpbk2_CGEN", 22, 1 },
+ { "TxSchLpbk1_CGEN", 21, 1 },
+ { "TxSchLpbk0_CGEN", 20, 1 },
+ { "TxSchMAC3_CGEN", 19, 1 },
+ { "TxSchMAC2_CGEN", 18, 1 },
+ { "TxSchMAC1_CGEN", 17, 1 },
+ { "TxSchMAC0_CGEN", 16, 1 },
+ { "TxInCh4_CGEN", 15, 1 },
+ { "TxInCh3_CGEN", 14, 1 },
+ { "TxInCh2_CGEN", 13, 1 },
+ { "TxInCh1_CGEN", 12, 1 },
+ { "TxInCh0_CGEN", 11, 1 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1e2e0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1e6e0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1eae0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1eee0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1f2e0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1f6e0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1fae0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PF_TX_QINQ_VLAN", 0x1fee0, 0 },
+ { "ProtocolID", 16, 16 },
+ { "Priority", 13, 3 },
+ { "CFI", 12, 1 },
+ { "Tag", 0, 12 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH0", 0x30190, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH1", 0x30194, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH2", 0x30198, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3019c, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH4", 0x301a0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x301a8, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x301ac, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x301b0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x301b4, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x301b8, 0 },
+ { "MPS_PORT_TX_FIFO_CTL", 0x301c4, 0 },
+ { "OUT_TH", 22, 8 },
+ { "IN_TH", 14, 8 },
+ { "FifoTh", 5, 9 },
+ { "FifoEn", 4, 1 },
+ { "MaxPktCnt", 0, 4 },
+ { "MPS_PORT_FPGA_PAUSE_CTL", 0x301c8, 0 },
+ { "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x301d0, 0 },
+ { "off_pending", 8, 8 },
+ { "on_pending", 0, 8 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH0", 0x34190, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH1", 0x34194, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH2", 0x34198, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3419c, 0 },
+ { "MPS_PORT_TX_MAC_RELOAD_CH4", 0x341a0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x341a8, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x341ac, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x341b0, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x341b4, 0 },
+ { "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x341b8, 0 },
+ { "MPS_PORT_TX_FIFO_CTL", 0x341c4, 0 },
+ { "OUT_TH", 22, 8 },
+ { "IN_TH", 14, 8 },
+ { "FifoTh", 5, 9 },
+ { "FifoEn", 4, 1 },
+ { "MaxPktCnt", 0, 4 },
+ { "MPS_PORT_FPGA_PAUSE_CTL", 0x341c8, 0 },
+ { "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x341d0, 0 },
+ { "off_pending", 8, 8 },
+ { "on_pending", 0, 8 },
+ { "MPS_TRC_CFG", 0x9800, 0 },
+ { "TrcMultiRSSFilter", 5, 1 },
+ { "TrcFifoEmpty", 4, 1 },
+ { "TrcIgnoreDropInput", 3, 1 },
+ { "TrcKeepDuplicates", 2, 1 },
+ { "TrcEn", 1, 1 },
+ { "TrcMultiFilter", 0, 1 },
+ { "MPS_TRC_FILTER0_RSS_HASH", 0x9804, 0 },
+ { "MPS_TRC_FILTER0_RSS_CONTROL", 0x9808, 0 },
+ { "RssControl", 16, 8 },
+ { "QueueNumber", 0, 16 },
+ { "MPS_TRC_FILTER1_RSS_HASH", 0x9ff0, 0 },
+ { "MPS_TRC_FILTER1_RSS_CONTROL", 0x9ff4, 0 },
+ { "RssControl", 16, 8 },
+ { "QueueNumber", 0, 16 },
+ { "MPS_TRC_FILTER2_RSS_HASH", 0x9ff8, 0 },
+ { "MPS_TRC_FILTER2_RSS_CONTROL", 0x9ffc, 0 },
+ { "RssControl", 16, 8 },
+ { "QueueNumber", 0, 16 },
+ { "MPS_TRC_FILTER3_RSS_HASH", 0xa000, 0 },
+ { "MPS_TRC_FILTER3_RSS_CONTROL", 0xa004, 0 },
+ { "RssControl", 16, 8 },
+ { "QueueNumber", 0, 16 },
+ { "MPS_TRC_RSS_HASH", 0xa008, 0 },
+ { "MPS_TRC_RSS_CONTROL", 0xa00c, 0 },
+ { "RssControl", 16, 8 },
+ { "QueueNumber", 0, 16 },
+ { "MPS_TRC_VF_OFF_FILTER_0", 0xa010, 0 },
+ { "TrcMPS2TP_MacOnly", 22, 1 },
+ { "TrcAllMPS2TP", 21, 1 },
+ { "TrcAllTP2MPS", 20, 1 },
+ { "TrcAllVf", 19, 1 },
+ { "OffEn", 18, 1 },
+ { "VfFiltEn", 17, 1 },
+ { "VfFiltMask", 9, 8 },
+ { "VfFiltValid", 8, 1 },
+ { "VfFiltData", 0, 8 },
+ { "MPS_TRC_VF_OFF_FILTER_1", 0xa014, 0 },
+ { "TrcMPS2TP_MacOnly", 22, 1 },
+ { "TrcAllMPS2TP", 21, 1 },
+ { "TrcAllTP2MPS", 20, 1 },
+ { "TrcAllVf", 19, 1 },
+ { "OffEn", 18, 1 },
+ { "VfFiltEn", 17, 1 },
+ { "VfFiltMask", 9, 8 },
+ { "VfFiltValid", 8, 1 },
+ { "VfFiltData", 0, 8 },
+ { "MPS_TRC_VF_OFF_FILTER_2", 0xa018, 0 },
+ { "TrcMPS2TP_MacOnly", 22, 1 },
+ { "TrcAllMPS2TP", 21, 1 },
+ { "TrcAllTP2MPS", 20, 1 },
+ { "TrcAllVf", 19, 1 },
+ { "OffEn", 18, 1 },
+ { "VfFiltEn", 17, 1 },
+ { "VfFiltMask", 9, 8 },
+ { "VfFiltValid", 8, 1 },
+ { "VfFiltData", 0, 8 },
+ { "MPS_TRC_VF_OFF_FILTER_3", 0xa01c, 0 },
+ { "TrcMPS2TP_MacOnly", 22, 1 },
+ { "TrcAllMPS2TP", 21, 1 },
+ { "TrcAllTP2MPS", 20, 1 },
+ { "TrcAllVf", 19, 1 },
+ { "OffEn", 18, 1 },
+ { "VfFiltEn", 17, 1 },
+ { "VfFiltMask", 9, 8 },
+ { "VfFiltValid", 8, 1 },
+ { "VfFiltData", 0, 8 },
+ { "MPS_TRC_CGEN", 0xa020, 0 },
+ { "MPS_TRC_FILTER_MATCH_CTL_A", 0x9810, 0 },
+ { "TfInsertActLen", 27, 1 },
+ { "TfInsertTimer", 26, 1 },
+ { "TfInvertMatch", 25, 1 },
+ { "TfPktTooLarge", 24, 1 },
+ { "TfEn", 23, 1 },
+ { "TfPort", 18, 5 },
+ { "TfDrop", 17, 1 },
+ { "TfSopEopErr", 16, 1 },
+ { "TfLength", 8, 5 },
+ { "TfOffset", 0, 5 },
+ { "MPS_TRC_FILTER_MATCH_CTL_A", 0x9814, 0 },
+ { "TfInsertActLen", 27, 1 },
+ { "TfInsertTimer", 26, 1 },
+ { "TfInvertMatch", 25, 1 },
+ { "TfPktTooLarge", 24, 1 },
+ { "TfEn", 23, 1 },
+ { "TfPort", 18, 5 },
+ { "TfDrop", 17, 1 },
+ { "TfSopEopErr", 16, 1 },
+ { "TfLength", 8, 5 },
+ { "TfOffset", 0, 5 },
+ { "MPS_TRC_FILTER_MATCH_CTL_A", 0x9818, 0 },
+ { "TfInsertActLen", 27, 1 },
+ { "TfInsertTimer", 26, 1 },
+ { "TfInvertMatch", 25, 1 },
+ { "TfPktTooLarge", 24, 1 },
+ { "TfEn", 23, 1 },
+ { "TfPort", 18, 5 },
+ { "TfDrop", 17, 1 },
+ { "TfSopEopErr", 16, 1 },
+ { "TfLength", 8, 5 },
+ { "TfOffset", 0, 5 },
+ { "MPS_TRC_FILTER_MATCH_CTL_A", 0x981c, 0 },
+ { "TfInsertActLen", 27, 1 },
+ { "TfInsertTimer", 26, 1 },
+ { "TfInvertMatch", 25, 1 },
+ { "TfPktTooLarge", 24, 1 },
+ { "TfEn", 23, 1 },
+ { "TfPort", 18, 5 },
+ { "TfDrop", 17, 1 },
+ { "TfSopEopErr", 16, 1 },
+ { "TfLength", 8, 5 },
+ { "TfOffset", 0, 5 },
+ { "MPS_TRC_FILTER_MATCH_CTL_B", 0x9820, 0 },
+ { "TfMinPktSize", 16, 9 },
+ { "TfCaptureMax", 0, 14 },
+ { "MPS_TRC_FILTER_MATCH_CTL_B", 0x9824, 0 },
+ { "TfMinPktSize", 16, 9 },
+ { "TfCaptureMax", 0, 14 },
+ { "MPS_TRC_FILTER_MATCH_CTL_B", 0x9828, 0 },
+ { "TfMinPktSize", 16, 9 },
+ { "TfCaptureMax", 0, 14 },
+ { "MPS_TRC_FILTER_MATCH_CTL_B", 0x982c, 0 },
+ { "TfMinPktSize", 16, 9 },
+ { "TfCaptureMax", 0, 14 },
+ { "MPS_TRC_FILTER_RUNT_CTL", 0x9830, 0 },
+ { "MPS_TRC_FILTER_RUNT_CTL", 0x9834, 0 },
+ { "MPS_TRC_FILTER_RUNT_CTL", 0x9838, 0 },
+ { "MPS_TRC_FILTER_RUNT_CTL", 0x983c, 0 },
+ { "MPS_TRC_FILTER_DROP", 0x9840, 0 },
+ { "TfDropInpCount", 16, 16 },
+ { "TfDropBufferCount", 0, 16 },
+ { "MPS_TRC_FILTER_DROP", 0x9844, 0 },
+ { "TfDropInpCount", 16, 16 },
+ { "TfDropBufferCount", 0, 16 },
+ { "MPS_TRC_FILTER_DROP", 0x9848, 0 },
+ { "TfDropInpCount", 16, 16 },
+ { "TfDropBufferCount", 0, 16 },
+ { "MPS_TRC_FILTER_DROP", 0x984c, 0 },
+ { "TfDropInpCount", 16, 16 },
+ { "TfDropBufferCount", 0, 16 },
+ { "MPS_TRC_PERR_INJECT", 0x9850, 0 },
+ { "MemSel", 1, 4 },
+ { "InjectDataErr", 0, 1 },
+ { "MPS_TRC_PERR_ENABLE", 0x9854, 0 },
+ { "MiscPerr", 8, 1 },
+ { "PktFifo", 4, 4 },
+ { "FiltMem", 0, 4 },
+ { "MPS_TRC_INT_ENABLE", 0x9858, 0 },
+ { "PLErrEnb", 9, 1 },
+ { "MiscPerr", 8, 1 },
+ { "PktFifo", 4, 4 },
+ { "FiltMem", 0, 4 },
+ { "MPS_TRC_INT_CAUSE", 0x985c, 0 },
+ { "PLErrEnb", 9, 1 },
+ { "MiscPerr", 8, 1 },
+ { "PktFifo", 4, 4 },
+ { "FiltMem", 0, 4 },
+ { "MPS_TRC_TIMESTAMP_L", 0x9860, 0 },
+ { "MPS_TRC_TIMESTAMP_H", 0x9864, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c00, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c04, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c08, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c0c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c10, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c14, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c18, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c1c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c20, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c24, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c28, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c2c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c30, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c34, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c38, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c3c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c40, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c44, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c48, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c4c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c50, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c54, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c58, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c5c, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c60, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c64, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c68, 0 },
+ { "MPS_TRC_FILTER0_MATCH", 0x9c6c, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c80, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c84, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c88, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c8c, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c90, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c94, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c98, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9c9c, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ca0, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ca4, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ca8, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cac, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cb0, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cb4, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cb8, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cbc, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cc0, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cc4, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cc8, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ccc, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cd0, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cd4, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cd8, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cdc, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ce0, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ce4, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9ce8, 0 },
+ { "MPS_TRC_FILTER0_DONT_CARE", 0x9cec, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d00, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d04, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d08, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d0c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d10, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d14, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d18, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d1c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d20, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d24, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d28, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d2c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d30, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d34, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d38, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d3c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d40, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d44, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d48, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d4c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d50, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d54, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d58, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d5c, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d60, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d64, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d68, 0 },
+ { "MPS_TRC_FILTER1_MATCH", 0x9d6c, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d80, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d84, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d88, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d8c, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d90, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d94, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d98, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9d9c, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9da0, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9da4, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9da8, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dac, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9db0, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9db4, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9db8, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dbc, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dc0, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dc4, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dc8, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dcc, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dd0, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dd4, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dd8, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9ddc, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9de0, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9de4, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9de8, 0 },
+ { "MPS_TRC_FILTER1_DONT_CARE", 0x9dec, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e00, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e04, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e08, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e0c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e10, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e14, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e18, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e1c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e20, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e24, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e28, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e2c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e30, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e34, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e38, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e3c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e40, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e44, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e48, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e4c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e50, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e54, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e58, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e5c, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e60, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e64, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e68, 0 },
+ { "MPS_TRC_FILTER2_MATCH", 0x9e6c, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e80, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e84, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e88, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e8c, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e90, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e94, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e98, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9e9c, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ea0, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ea4, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ea8, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9eac, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9eb0, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9eb4, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9eb8, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ebc, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ec0, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ec4, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ec8, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ecc, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ed0, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ed4, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ed8, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9edc, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ee0, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ee4, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9ee8, 0 },
+ { "MPS_TRC_FILTER2_DONT_CARE", 0x9eec, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f00, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f04, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f08, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f0c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f10, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f14, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f18, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f1c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f20, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f24, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f28, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f2c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f30, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f34, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f38, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f3c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f40, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f44, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f48, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f4c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f50, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f54, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f58, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f5c, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f60, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f64, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f68, 0 },
+ { "MPS_TRC_FILTER3_MATCH", 0x9f6c, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f80, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f84, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f88, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f8c, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f90, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f94, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f98, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9f9c, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fa0, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fa4, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fa8, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fac, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fb0, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fb4, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fb8, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fbc, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fc0, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fc4, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fc8, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fcc, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fd0, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fd4, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fd8, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fdc, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fe0, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fe4, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fe8, 0 },
+ { "MPS_TRC_FILTER3_DONT_CARE", 0x9fec, 0 },
+ { "MPS_STAT_CTL", 0x9600, 0 },
+ { "StatStopCtrl", 10, 1 },
+ { "StopStat", 9, 1 },
+ { "StatWriteCtrl", 8, 1 },
+ { "CountLbPF", 7, 1 },
+ { "CountLbVF", 6, 1 },
+ { "CountPauseMCRx", 5, 1 },
+ { "CountPauseStatRx", 4, 1 },
+ { "CountPauseMCTx", 3, 1 },
+ { "CountPauseStatTx", 2, 1 },
+ { "CountVFinPF", 1, 1 },
+ { "LpbkErrStat", 0, 1 },
+ { "MPS_STAT_INT_ENABLE", 0x9608, 0 },
+ { "MPS_STAT_INT_CAUSE", 0x960c, 0 },
+ { "MPS_STAT_PERR_INT_ENABLE_SRAM", 0x9610, 0 },
+ { "Rxbg", 27, 2 },
+ { "Rxpf", 22, 5 },
+ { "Txpf", 18, 4 },
+ { "Rxport", 11, 7 },
+ { "Lbport", 6, 5 },
+ { "Txport", 0, 6 },
+ { "MPS_STAT_PERR_INT_CAUSE_SRAM", 0x9614, 0 },
+ { "Rxbg", 27, 2 },
+ { "Rxpf", 22, 5 },
+ { "Txpf", 18, 4 },
+ { "Rxport", 11, 7 },
+ { "Lbport", 6, 5 },
+ { "Txport", 0, 6 },
+ { "MPS_STAT_PERR_ENABLE_SRAM", 0x9618, 0 },
+ { "Rxbg", 27, 2 },
+ { "Rxpf", 22, 5 },
+ { "Txpf", 18, 4 },
+ { "Rxport", 11, 7 },
+ { "Lbport", 6, 5 },
+ { "Txport", 0, 6 },
+ { "MPS_STAT_PERR_INT_ENABLE_TX_FIFO", 0x961c, 0 },
+ { "TxCh", 20, 4 },
+ { "Tx", 12, 8 },
+ { "Pause", 8, 4 },
+ { "Drop", 0, 8 },
+ { "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 0x9620, 0 },
+ { "TxCh", 20, 4 },
+ { "Tx", 12, 8 },
+ { "Pause", 8, 4 },
+ { "Drop", 0, 8 },
+ { "MPS_STAT_PERR_ENABLE_TX_FIFO", 0x9624, 0 },
+ { "TxCh", 20, 4 },
+ { "Tx", 12, 8 },
+ { "Pause", 8, 4 },
+ { "Drop", 0, 8 },
+ { "MPS_STAT_PERR_INT_ENABLE_RX_FIFO", 0x9628, 0 },
+ { "Pause", 20, 4 },
+ { "Lpbk", 16, 4 },
+ { "Nq", 8, 8 },
+ { "PV", 4, 4 },
+ { "Mac", 0, 4 },
+ { "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 0x962c, 0 },
+ { "Pause", 20, 4 },
+ { "Lpbk", 16, 4 },
+ { "Nq", 8, 8 },
+ { "PV", 4, 4 },
+ { "Mac", 0, 4 },
+ { "MPS_STAT_PERR_ENABLE_RX_FIFO", 0x9630, 0 },
+ { "Pause", 20, 4 },
+ { "Lpbk", 16, 4 },
+ { "Nq", 8, 8 },
+ { "PV", 4, 4 },
+ { "Mac", 0, 4 },
+ { "MPS_STAT_PERR_INJECT", 0x9634, 0 },
+ { "MemSel", 1, 7 },
+ { "InjectDataErr", 0, 1 },
+ { "MPS_STAT_DEBUG_SUB_SEL", 0x9638, 0 },
+ { "SubPrtH", 5, 5 },
+ { "SubPrtL", 0, 5 },
+ { "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L", 0x9640, 0 },
+ { "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H", 0x9644, 0 },
+ { "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L", 0x9648, 0 },
+ { "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H", 0x964c, 0 },
+ { "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L", 0x9650, 0 },
+ { "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H", 0x9654, 0 },
+ { "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L", 0x9658, 0 },
+ { "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H", 0x965c, 0 },
+ { "MPS_STAT_RX_BG_0_LB_DROP_FRAME_L", 0x9660, 0 },
+ { "MPS_STAT_RX_BG_0_LB_DROP_FRAME_H", 0x9664, 0 },
+ { "MPS_STAT_RX_BG_1_LB_DROP_FRAME_L", 0x9668, 0 },
+ { "MPS_STAT_RX_BG_1_LB_DROP_FRAME_H", 0x966c, 0 },
+ { "MPS_STAT_RX_BG_2_LB_DROP_FRAME_L", 0x9670, 0 },
+ { "MPS_STAT_RX_BG_2_LB_DROP_FRAME_H", 0x9674, 0 },
+ { "MPS_STAT_RX_BG_3_LB_DROP_FRAME_L", 0x9678, 0 },
+ { "MPS_STAT_RX_BG_3_LB_DROP_FRAME_H", 0x967c, 0 },
+ { "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L", 0x9680, 0 },
+ { "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H", 0x9684, 0 },
+ { "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L", 0x9688, 0 },
+ { "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H", 0x968c, 0 },
+ { "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L", 0x9690, 0 },
+ { "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H", 0x9694, 0 },
+ { "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L", 0x9698, 0 },
+ { "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H", 0x969c, 0 },
+ { "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L", 0x96a0, 0 },
+ { "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H", 0x96a4, 0 },
+ { "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L", 0x96a8, 0 },
+ { "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H", 0x96ac, 0 },
+ { "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L", 0x96b0, 0 },
+ { "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H", 0x96b4, 0 },
+ { "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L", 0x96b8, 0 },
+ { "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H", 0x96bc, 0 },
+ { "MPS_STAT_PERR_INT_ENABLE_SRAM1", 0x96c0, 0 },
+ { "Rxvf", 5, 3 },
+ { "Txvf", 0, 5 },
+ { "MPS_STAT_PERR_INT_CAUSE_SRAM1", 0x96c4, 0 },
+ { "Rxvf", 5, 3 },
+ { "Txvf", 0, 5 },
+ { "MPS_STAT_PERR_ENABLE_SRAM1", 0x96c8, 0 },
+ { "Rxvf", 5, 3 },
+ { "Txvf", 0, 5 },
+ { "MPS_STAT_STOP_UPD_BG", 0x96cc, 0 },
+ { "MPS_STAT_STOP_UPD_PORT", 0x96d0, 0 },
+ { "PtLpbk", 8, 4 },
+ { "PtTx", 4, 4 },
+ { "PtRx", 0, 4 },
+ { "MPS_STAT_STOP_UPD_PF", 0x96d4, 0 },
+ { "PFTx", 8, 8 },
+ { "PFRx", 0, 8 },
+ { "MPS_STAT_STOP_UPD_TX_VF_0_31", 0x96d8, 0 },
+ { "MPS_STAT_STOP_UPD_TX_VF_32_63", 0x96dc, 0 },
+ { "MPS_STAT_STOP_UPD_TX_VF_64_95", 0x96e0, 0 },
+ { "MPS_STAT_STOP_UPD_TX_VF_96_127", 0x96e4, 0 },
+ { "MPS_STAT_STOP_UPD_TX_VF_128_159", 0x9710, 0 },
+ { "MPS_STAT_STOP_UPD_TX_VF_160_191", 0x9714, 0 },
+ { "MPS_STAT_STOP_UPD_TX_VF_192_223", 0x9718, 0 },
+ { "MPS_STAT_STOP_UPD_TX_VF_224_255", 0x971c, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_0_31", 0x96e8, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_32_63", 0x96ec, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_64_95", 0x96f0, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_96_127", 0x96f4, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_128_159", 0x96f8, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_160_191", 0x96fc, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_192_223", 0x9700, 0 },
+ { "MPS_STAT_STOP_UPD_RX_VF_224_255", 0x9704, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x30400, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x30404, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x30408, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3040c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x30410, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x30414, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x30418, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3041c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x30420, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x30424, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x30428, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3042c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_L", 0x30430, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_H", 0x30434, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x30438, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3043c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x30440, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x30444, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x30448, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3044c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x30450, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x30454, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x30458, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3045c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x30460, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x30464, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_L", 0x30468, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3046c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x30470, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x30474, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x30478, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3047c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x30480, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x30484, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x30488, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3048c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x30490, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x30494, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x30498, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3049c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x304a0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x304a4, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x304a8, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x304ac, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x304b0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x304b4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x304c0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x304c4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x304c8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x304cc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x304d0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x304d4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x304d8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x304dc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x304e0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x304e4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x304e8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x304ec, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_L", 0x304f0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_H", 0x304f4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x304f8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x304fc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x30500, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x30504, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x30508, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3050c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x30510, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x30514, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x30518, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3051c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x30520, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x30524, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x30528, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3052c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x30540, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x30544, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x30548, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3054c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x30550, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x30554, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x30558, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3055c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x30560, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x30564, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x30568, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3056c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x30570, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x30574, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x30578, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3057c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x30580, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x30584, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x30588, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3058c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_L", 0x30590, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_H", 0x30594, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x30598, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3059c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x305a0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x305a4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x305a8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x305ac, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x305b0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x305b4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x305b8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x305bc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x305c0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x305c4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x305c8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x305cc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x305d0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x305d4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x305d8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x305dc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x305e0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x305e4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x305e8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x305ec, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x305f0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x305f4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x305f8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x305fc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x30600, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x30604, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x30608, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3060c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x30610, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x30614, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x30618, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3061c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x34400, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x34404, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x34408, 0 },
+ { "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3440c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x34410, 0 },
+ { "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x34414, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x34418, 0 },
+ { "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3441c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x34420, 0 },
+ { "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x34424, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x34428, 0 },
+ { "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3442c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_L", 0x34430, 0 },
+ { "MPS_PORT_STAT_TX_PORT_64B_H", 0x34434, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x34438, 0 },
+ { "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3443c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x34440, 0 },
+ { "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x34444, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x34448, 0 },
+ { "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3444c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x34450, 0 },
+ { "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x34454, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x34458, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3445c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x34460, 0 },
+ { "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x34464, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_L", 0x34468, 0 },
+ { "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3446c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x34470, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x34474, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x34478, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3447c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x34480, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x34484, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x34488, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3448c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x34490, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x34494, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x34498, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3449c, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x344a0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x344a4, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x344a8, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x344ac, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x344b0, 0 },
+ { "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x344b4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x344c0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x344c4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x344c8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x344cc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x344d0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x344d4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x344d8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x344dc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x344e0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x344e4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x344e8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x344ec, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_L", 0x344f0, 0 },
+ { "MPS_PORT_STAT_LB_PORT_64B_H", 0x344f4, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x344f8, 0 },
+ { "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x344fc, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x34500, 0 },
+ { "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x34504, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x34508, 0 },
+ { "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3450c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x34510, 0 },
+ { "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x34514, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x34518, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3451c, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x34520, 0 },
+ { "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x34524, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x34528, 0 },
+ { "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3452c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x34540, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x34544, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x34548, 0 },
+ { "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3454c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x34550, 0 },
+ { "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x34554, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x34558, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3455c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x34560, 0 },
+ { "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x34564, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x34568, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3456c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x34570, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x34574, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x34578, 0 },
+ { "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3457c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x34580, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x34584, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x34588, 0 },
+ { "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3458c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_L", 0x34590, 0 },
+ { "MPS_PORT_STAT_RX_PORT_64B_H", 0x34594, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x34598, 0 },
+ { "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3459c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x345a0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x345a4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x345a8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x345ac, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x345b0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x345b4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x345b8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x345bc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x345c0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x345c4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x345c8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x345cc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x345d0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x345d4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x345d8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x345dc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x345e0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x345e4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x345e8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x345ec, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x345f0, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x345f4, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x345f8, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x345fc, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x34600, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x34604, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x34608, 0 },
+ { "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3460c, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x34610, 0 },
+ { "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x34614, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x34618, 0 },
+ { "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3461c, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e300, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e304, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e308, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e30c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e310, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e314, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e318, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e31c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e320, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e324, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e328, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e32c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e330, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e334, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e338, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e33c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e340, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e344, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e348, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e34c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e350, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e354, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e358, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e35c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e360, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e364, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e368, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e36c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e370, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e374, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e378, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e37c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e380, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e384, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e700, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e704, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e708, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e70c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e710, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e714, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e718, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e71c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e720, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e724, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e728, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e72c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e730, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e734, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e738, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e73c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e740, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e744, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e748, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e74c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e750, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e754, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e758, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e75c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e760, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e764, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e768, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e76c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e770, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e774, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e778, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e77c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e780, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e784, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1eb00, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1eb04, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1eb08, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1eb0c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1eb10, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1eb14, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1eb18, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1eb1c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1eb20, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1eb24, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1eb28, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1eb2c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1eb30, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1eb34, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1eb38, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1eb3c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1eb40, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1eb44, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1eb48, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1eb4c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1eb50, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1eb54, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1eb58, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1eb5c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1eb60, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1eb64, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1eb68, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1eb6c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1eb70, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1eb74, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1eb78, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1eb7c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1eb80, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1eb84, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ef00, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ef04, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ef08, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ef0c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ef10, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ef14, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ef18, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ef1c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ef20, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ef24, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ef28, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ef2c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ef30, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ef34, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ef38, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ef3c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ef40, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ef44, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ef48, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ef4c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ef50, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ef54, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ef58, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ef5c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ef60, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ef64, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ef68, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ef6c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ef70, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ef74, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ef78, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ef7c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ef80, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ef84, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f300, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f304, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f308, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f30c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f310, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f314, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f318, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f31c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f320, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f324, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f328, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f32c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f330, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f334, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f338, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f33c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f340, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f344, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f348, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f34c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f350, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f354, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f358, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f35c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f360, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f364, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f368, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f36c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f370, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f374, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f378, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f37c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f380, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f384, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f700, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f704, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f708, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f70c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f710, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f714, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f718, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f71c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f720, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f724, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f728, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f72c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f730, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f734, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f738, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f73c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f740, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f744, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f748, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f74c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f750, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f754, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f758, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f75c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f760, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f764, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f768, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f76c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f770, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f774, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f778, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f77c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f780, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f784, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1fb00, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1fb04, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1fb08, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1fb0c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1fb10, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1fb14, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1fb18, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1fb1c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1fb20, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1fb24, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1fb28, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1fb2c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1fb30, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1fb34, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1fb38, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1fb3c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1fb40, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1fb44, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1fb48, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1fb4c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1fb50, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1fb54, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1fb58, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1fb5c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1fb60, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1fb64, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1fb68, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1fb6c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1fb70, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1fb74, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1fb78, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1fb7c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1fb80, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1fb84, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ff00, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ff04, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ff08, 0 },
+ { "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ff0c, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ff10, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ff14, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ff18, 0 },
+ { "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ff1c, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ff20, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ff24, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ff28, 0 },
+ { "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ff2c, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ff30, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ff34, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ff38, 0 },
+ { "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ff3c, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ff40, 0 },
+ { "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ff44, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ff48, 0 },
+ { "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ff4c, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ff50, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ff54, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ff58, 0 },
+ { "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ff5c, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ff60, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ff64, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ff68, 0 },
+ { "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ff6c, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ff70, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ff74, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ff78, 0 },
+ { "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ff7c, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ff80, 0 },
+ { "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ff84, 0 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30200, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30204, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30208, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3020c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30210, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30214, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30218, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3021c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30220, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30224, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30228, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3022c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30230, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30234, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30238, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3023c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30240, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30244, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30248, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3024c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30250, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30254, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30258, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3025c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30260, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30264, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30268, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3026c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30270, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30274, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30278, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3027c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30280, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30284, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x30288, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3028c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
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+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34264, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34268, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3426c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34270, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34274, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34278, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3427c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34280, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34284, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34288, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3428c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34290, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34294, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34298, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x3429c, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342a0, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342a4, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342a8, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342ac, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342b0, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342b4, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342b8, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342bc, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342c0, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342c4, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342c8, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342cc, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342d0, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342d4, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342d8, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342dc, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342e0, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342e4, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342e8, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342ec, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342f0, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342f4, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342f8, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x342fc, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_SRAM", 0x34300, 0 },
+ { "DisEncapOuterRplct", 23, 1 },
+ { "DisEncap", 22, 1 },
+ { "Valid", 21, 1 },
+ { "PortMap", 17, 4 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_HASH_CTL", 0x30304, 0 },
+ { "UnicastEnable", 31, 1 },
+ { "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x30308, 0 },
+ { "Enable", 31, 1 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3030c, 0 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x30310, 0 },
+ { "MatchAll", 18, 1 },
+ { "MatchBoth", 17, 1 },
+ { "Valid", 16, 1 },
+ { "DA", 0, 16 },
+ { "MPS_PORT_CLS_BMC_VLAN", 0x30314, 0 },
+ { "BMC_VLAN_SEL", 13, 1 },
+ { "Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PORT_CLS_CTL", 0x30318, 0 },
+ { "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
+ { "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
+ { "LPBK_TCAM_PRIORITY", 12, 1 },
+ { "LPBK_SMAC_TCAM_SEL", 10, 2 },
+ { "LPBK_DMAC_TCAM_SEL", 8, 2 },
+ { "TCAM1_HIT_PRIORITY", 7, 1 },
+ { "TCAM0_HIT_PRIORITY", 6, 1 },
+ { "TCAM_PRIORITY", 5, 1 },
+ { "SMAC_TCAM_SEL", 3, 2 },
+ { "DMAC_TCAM_SEL", 1, 2 },
+ { "PF_VLAN_SEL", 0, 1 },
+ { "MPS_PORT_CLS_NCSI_ETH_TYPE", 0x3031c, 0 },
+ { "EthType1", 16, 16 },
+ { "EthType2", 0, 16 },
+ { "MPS_PORT_CLS_NCSI_ETH_TYPE_EN", 0x30320, 0 },
+ { "EN1", 1, 1 },
+ { "EN2", 0, 1 },
+ { "MPS_PORT_CLS_HASH_CTL", 0x34304, 0 },
+ { "UnicastEnable", 31, 1 },
+ { "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x34308, 0 },
+ { "Enable", 31, 1 },
+ { "MultiListen", 16, 1 },
+ { "Priority", 13, 3 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3430c, 0 },
+ { "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x34310, 0 },
+ { "MatchAll", 18, 1 },
+ { "MatchBoth", 17, 1 },
+ { "Valid", 16, 1 },
+ { "DA", 0, 16 },
+ { "MPS_PORT_CLS_BMC_VLAN", 0x34314, 0 },
+ { "BMC_VLAN_SEL", 13, 1 },
+ { "Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_PORT_CLS_CTL", 0x34318, 0 },
+ { "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
+ { "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
+ { "LPBK_TCAM_PRIORITY", 12, 1 },
+ { "LPBK_SMAC_TCAM_SEL", 10, 2 },
+ { "LPBK_DMAC_TCAM_SEL", 8, 2 },
+ { "TCAM1_HIT_PRIORITY", 7, 1 },
+ { "TCAM0_HIT_PRIORITY", 6, 1 },
+ { "TCAM_PRIORITY", 5, 1 },
+ { "SMAC_TCAM_SEL", 3, 2 },
+ { "DMAC_TCAM_SEL", 1, 2 },
+ { "PF_VLAN_SEL", 0, 1 },
+ { "MPS_PORT_CLS_NCSI_ETH_TYPE", 0x3431c, 0 },
+ { "EthType1", 16, 16 },
+ { "EthType2", 0, 16 },
+ { "MPS_PORT_CLS_NCSI_ETH_TYPE_EN", 0x34320, 0 },
+ { "EN1", 1, 1 },
+ { "EN2", 0, 1 },
+ { "MPS_CLS_CTL", 0xd000, 0 },
+ { "VlanClsEn_in", 7, 1 },
+ { "DisTcamParChk", 6, 1 },
+ { "VlanLkpEn", 5, 1 },
+ { "MemWriteFault", 4, 1 },
+ { "MemWriteWaiting", 3, 1 },
+ { "CimNoPromiscuous", 2, 1 },
+ { "HypervisorOnly", 1, 1 },
+ { "VlanClsEn", 0, 1 },
+ { "MPS_CLS_ARB_WEIGHT", 0xd004, 0 },
+ { "PlWeight", 16, 5 },
+ { "CimWeight", 8, 5 },
+ { "LpbkWeight", 0, 5 },
+ { "MPS_CLS_NCSI_ETH_TYPE", 0xd008, 0 },
+ { "EthType1", 16, 16 },
+ { "EthType2", 0, 16 },
+ { "MPS_CLS_NCSI_ETH_TYPE_EN", 0xd00c, 0 },
+ { "EN1", 1, 1 },
+ { "EN2", 0, 1 },
+ { "MPS_CLS_BMC_MAC_ADDR_L", 0xd010, 0 },
+ { "MPS_CLS_BMC_MAC_ADDR_H", 0xd014, 0 },
+ { "MatchAll", 18, 1 },
+ { "MatchBoth", 17, 1 },
+ { "Valid", 16, 1 },
+ { "DA", 0, 16 },
+ { "MPS_CLS_BMC_VLAN", 0xd018, 0 },
+ { "Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_PERR_INJECT", 0xd01c, 0 },
+ { "MemSel", 1, 2 },
+ { "InjectDataErr", 0, 1 },
+ { "MPS_CLS_PERR_ENABLE", 0xd020, 0 },
+ { "HashSRAM", 2, 1 },
+ { "MatchTCAM", 1, 1 },
+ { "MatchSRAM", 0, 1 },
+ { "MPS_CLS_INT_ENABLE", 0xd024, 0 },
+ { "PLErrEnb", 3, 1 },
+ { "HashSRAM", 2, 1 },
+ { "MatchTCAM", 1, 1 },
+ { "MatchSRAM", 0, 1 },
+ { "MPS_CLS_INT_CAUSE", 0xd028, 0 },
+ { "PLErrEnb", 3, 1 },
+ { "HashSRAM", 2, 1 },
+ { "MatchTCAM", 1, 1 },
+ { "MatchSRAM", 0, 1 },
+ { "MPS_CLS_PL_TEST_DATA_L", 0xd02c, 0 },
+ { "MPS_CLS_PL_TEST_DATA_H", 0xd030, 0 },
+ { "MPS_CLS_PL_TEST_RES_DATA", 0xd034, 0 },
+ { "Cls_Spare", 28, 4 },
+ { "Cls_Priority", 25, 3 },
+ { "Cls_Replicate", 24, 1 },
+ { "Cls_Index", 15, 9 },
+ { "Cls_VF", 7, 8 },
+ { "Cls_VF_Vld", 6, 1 },
+ { "Cls_PF", 3, 3 },
+ { "Cls_Match", 0, 3 },
+ { "MPS_CLS_PL_TEST_CTL", 0xd038, 0 },
+ { "MPS_CLS_PORT_BMC_CTL", 0xd03c, 0 },
+ { "MPS_CLS_MATCH_CNT_TCAM", 0xd100, 0 },
+ { "MPS_CLS_MATCH_CNT_HASH", 0xd104, 0 },
+ { "MPS_CLS_MATCH_CNT_BCAST", 0xd108, 0 },
+ { "MPS_CLS_MATCH_CNT_BMC", 0xd10c, 0 },
+ { "MPS_CLS_MATCH_CNT_PROM", 0xd110, 0 },
+ { "MPS_CLS_MATCH_CNT_HPROM", 0xd114, 0 },
+ { "MPS_CLS_MISS_CNT", 0xd118, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd200, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd220, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd240, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd260, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd280, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2a0, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2c0, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_L", 0xd2e0, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd204, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd224, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd244, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd264, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd284, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2a4, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2c4, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_DA_H", 0xd2e4, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd208, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd228, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd248, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd268, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd288, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2a8, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2c8, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_L", 0xd2e8, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd20c, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd22c, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd24c, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd26c, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd28c, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2ac, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2cc, 0 },
+ { "MPS_CLS_REQUEST_TRACE_MAC_SA_H", 0xd2ec, 0 },
+ { "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd210, 0 },
+ { "ClsTrcVlanVld", 31, 1 },
+ { "ClsTrcVlanId", 16, 12 },
+ { "ClsTrcReqPort", 0, 4 },
+ { "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd230, 0 },
+ { "ClsTrcVlanVld", 31, 1 },
+ { "ClsTrcVlanId", 16, 12 },
+ { "ClsTrcReqPort", 0, 4 },
+ { "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd250, 0 },
+ { "ClsTrcVlanVld", 31, 1 },
+ { "ClsTrcVlanId", 16, 12 },
+ { "ClsTrcReqPort", 0, 4 },
+ { "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd270, 0 },
+ { "ClsTrcVlanVld", 31, 1 },
+ { "ClsTrcVlanId", 16, 12 },
+ { "ClsTrcReqPort", 0, 4 },
+ { "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd290, 0 },
+ { "ClsTrcVlanVld", 31, 1 },
+ { "ClsTrcVlanId", 16, 12 },
+ { "ClsTrcReqPort", 0, 4 },
+ { "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2b0, 0 },
+ { "ClsTrcVlanVld", 31, 1 },
+ { "ClsTrcVlanId", 16, 12 },
+ { "ClsTrcReqPort", 0, 4 },
+ { "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2d0, 0 },
+ { "ClsTrcVlanVld", 31, 1 },
+ { "ClsTrcVlanId", 16, 12 },
+ { "ClsTrcReqPort", 0, 4 },
+ { "MPS_CLS_REQUEST_TRACE_PORT_VLAN", 0xd2f0, 0 },
+ { "ClsTrcVlanVld", 31, 1 },
+ { "ClsTrcVlanId", 16, 12 },
+ { "ClsTrcReqPort", 0, 4 },
+ { "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd214, 0 },
+ { "ClsTrcLkpType", 31, 1 },
+ { "ClsTrcDIPHit", 30, 1 },
+ { "ClsTrcVNI", 0, 24 },
+ { "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd234, 0 },
+ { "ClsTrcLkpType", 31, 1 },
+ { "ClsTrcDIPHit", 30, 1 },
+ { "ClsTrcVNI", 0, 24 },
+ { "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd254, 0 },
+ { "ClsTrcLkpType", 31, 1 },
+ { "ClsTrcDIPHit", 30, 1 },
+ { "ClsTrcVNI", 0, 24 },
+ { "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd274, 0 },
+ { "ClsTrcLkpType", 31, 1 },
+ { "ClsTrcDIPHit", 30, 1 },
+ { "ClsTrcVNI", 0, 24 },
+ { "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd294, 0 },
+ { "ClsTrcLkpType", 31, 1 },
+ { "ClsTrcDIPHit", 30, 1 },
+ { "ClsTrcVNI", 0, 24 },
+ { "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2b4, 0 },
+ { "ClsTrcLkpType", 31, 1 },
+ { "ClsTrcDIPHit", 30, 1 },
+ { "ClsTrcVNI", 0, 24 },
+ { "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2d4, 0 },
+ { "ClsTrcLkpType", 31, 1 },
+ { "ClsTrcDIPHit", 30, 1 },
+ { "ClsTrcVNI", 0, 24 },
+ { "MPS_CLS_REQUEST_TRACE_ENCAP", 0xd2f4, 0 },
+ { "ClsTrcLkpType", 31, 1 },
+ { "ClsTrcDIPHit", 30, 1 },
+ { "ClsTrcVNI", 0, 24 },
+ { "MPS_CLS_RESULT_TRACE", 0xd300, 0 },
+ { "ClsTrcPortNum", 31, 1 },
+ { "ClsTrcPriority", 28, 3 },
+ { "ClsTrcMultiListen", 27, 1 },
+ { "ClsTrcReplicate", 26, 1 },
+ { "ClsTrcPortMap", 24, 2 },
+ { "ClsTrcMatch", 21, 3 },
+ { "ClsTrcIndex", 12, 9 },
+ { "ClsTrcVF_Vld", 11, 1 },
+ { "ClsTrcPF", 3, 8 },
+ { "ClsTrcVF", 0, 3 },
+ { "MPS_CLS_RESULT_TRACE", 0xd304, 0 },
+ { "ClsTrcPortNum", 31, 1 },
+ { "ClsTrcPriority", 28, 3 },
+ { "ClsTrcMultiListen", 27, 1 },
+ { "ClsTrcReplicate", 26, 1 },
+ { "ClsTrcPortMap", 24, 2 },
+ { "ClsTrcMatch", 21, 3 },
+ { "ClsTrcIndex", 12, 9 },
+ { "ClsTrcVF_Vld", 11, 1 },
+ { "ClsTrcPF", 3, 8 },
+ { "ClsTrcVF", 0, 3 },
+ { "MPS_CLS_RESULT_TRACE", 0xd308, 0 },
+ { "ClsTrcPortNum", 31, 1 },
+ { "ClsTrcPriority", 28, 3 },
+ { "ClsTrcMultiListen", 27, 1 },
+ { "ClsTrcReplicate", 26, 1 },
+ { "ClsTrcPortMap", 24, 2 },
+ { "ClsTrcMatch", 21, 3 },
+ { "ClsTrcIndex", 12, 9 },
+ { "ClsTrcVF_Vld", 11, 1 },
+ { "ClsTrcPF", 3, 8 },
+ { "ClsTrcVF", 0, 3 },
+ { "MPS_CLS_RESULT_TRACE", 0xd30c, 0 },
+ { "ClsTrcPortNum", 31, 1 },
+ { "ClsTrcPriority", 28, 3 },
+ { "ClsTrcMultiListen", 27, 1 },
+ { "ClsTrcReplicate", 26, 1 },
+ { "ClsTrcPortMap", 24, 2 },
+ { "ClsTrcMatch", 21, 3 },
+ { "ClsTrcIndex", 12, 9 },
+ { "ClsTrcVF_Vld", 11, 1 },
+ { "ClsTrcPF", 3, 8 },
+ { "ClsTrcVF", 0, 3 },
+ { "MPS_CLS_RESULT_TRACE", 0xd310, 0 },
+ { "ClsTrcPortNum", 31, 1 },
+ { "ClsTrcPriority", 28, 3 },
+ { "ClsTrcMultiListen", 27, 1 },
+ { "ClsTrcReplicate", 26, 1 },
+ { "ClsTrcPortMap", 24, 2 },
+ { "ClsTrcMatch", 21, 3 },
+ { "ClsTrcIndex", 12, 9 },
+ { "ClsTrcVF_Vld", 11, 1 },
+ { "ClsTrcPF", 3, 8 },
+ { "ClsTrcVF", 0, 3 },
+ { "MPS_CLS_RESULT_TRACE", 0xd314, 0 },
+ { "ClsTrcPortNum", 31, 1 },
+ { "ClsTrcPriority", 28, 3 },
+ { "ClsTrcMultiListen", 27, 1 },
+ { "ClsTrcReplicate", 26, 1 },
+ { "ClsTrcPortMap", 24, 2 },
+ { "ClsTrcMatch", 21, 3 },
+ { "ClsTrcIndex", 12, 9 },
+ { "ClsTrcVF_Vld", 11, 1 },
+ { "ClsTrcPF", 3, 8 },
+ { "ClsTrcVF", 0, 3 },
+ { "MPS_CLS_RESULT_TRACE", 0xd318, 0 },
+ { "ClsTrcPortNum", 31, 1 },
+ { "ClsTrcPriority", 28, 3 },
+ { "ClsTrcMultiListen", 27, 1 },
+ { "ClsTrcReplicate", 26, 1 },
+ { "ClsTrcPortMap", 24, 2 },
+ { "ClsTrcMatch", 21, 3 },
+ { "ClsTrcIndex", 12, 9 },
+ { "ClsTrcVF_Vld", 11, 1 },
+ { "ClsTrcPF", 3, 8 },
+ { "ClsTrcVF", 0, 3 },
+ { "MPS_CLS_RESULT_TRACE", 0xd31c, 0 },
+ { "ClsTrcPortNum", 31, 1 },
+ { "ClsTrcPriority", 28, 3 },
+ { "ClsTrcMultiListen", 27, 1 },
+ { "ClsTrcReplicate", 26, 1 },
+ { "ClsTrcPortMap", 24, 2 },
+ { "ClsTrcMatch", 21, 3 },
+ { "ClsTrcIndex", 12, 9 },
+ { "ClsTrcVF_Vld", 11, 1 },
+ { "ClsTrcPF", 3, 8 },
+ { "ClsTrcVF", 0, 3 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfc0, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfc4, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfc8, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfcc, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfd0, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfd4, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfd8, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfdc, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_VLAN_TABLE", 0xdfe0, 0 },
+ { "VLAN_Mask", 16, 12 },
+ { "PF", 13, 3 },
+ { "VLAN_Valid", 12, 1 },
+ { "VLAN_ID", 0, 12 },
+ { "MPS_CLS_DIPIPV4_ID_TABLE", 0x12000, 0 },
+ { "MPS_CLS_DIPIPV4_ID_TABLE", 0x12008, 0 },
+ { "MPS_CLS_DIPIPV4_ID_TABLE", 0x12010, 0 },
+ { "MPS_CLS_DIPIPV4_ID_TABLE", 0x12018, 0 },
+ { "MPS_CLS_DIPIPV4_MASK_TABLE", 0x12004, 0 },
+ { "MPS_CLS_DIPIPV4_MASK_TABLE", 0x1200c, 0 },
+ { "MPS_CLS_DIPIPV4_MASK_TABLE", 0x12014, 0 },
+ { "MPS_CLS_DIPIPV4_MASK_TABLE", 0x1201c, 0 },
+ { "MPS_CLS_DIPIPV6ID_0_TABLE", 0x12020, 0 },
+ { "MPS_CLS_DIPIPV6ID_0_TABLE", 0x12040, 0 },
+ { "MPS_CLS_DIPIPV6ID_1_TABLE", 0x12024, 0 },
+ { "MPS_CLS_DIPIPV6ID_1_TABLE", 0x12044, 0 },
+ { "MPS_CLS_DIPIPV6ID_2_TABLE", 0x12028, 0 },
+ { "MPS_CLS_DIPIPV6ID_2_TABLE", 0x12048, 0 },
+ { "MPS_CLS_DIPIPV6ID_3_TABLE", 0x1202c, 0 },
+ { "MPS_CLS_DIPIPV6ID_3_TABLE", 0x1204c, 0 },
+ { "MPS_CLS_DIPIPV6MASK_0_TABLE", 0x12030, 0 },
+ { "MPS_CLS_DIPIPV6MASK_0_TABLE", 0x12050, 0 },
+ { "MPS_CLS_DIPIPV6MASK_1_TABLE", 0x12034, 0 },
+ { "MPS_CLS_DIPIPV6MASK_1_TABLE", 0x12054, 0 },
+ { "MPS_CLS_DIPIPV6MASK_2_TABLE", 0x12038, 0 },
+ { "MPS_CLS_DIPIPV6MASK_2_TABLE", 0x12058, 0 },
+ { "MPS_CLS_DIPIPV6MASK_3_TABLE", 0x1203c, 0 },
+ { "MPS_CLS_DIPIPV6MASK_3_TABLE", 0x1205c, 0 },
+ { "MPS_RX_HASH_LKP_TABLE", 0x12060, 0 },
+ { "MPS_RX_HASH_LKP_TABLE", 0x12064, 0 },
+ { "MPS_RX_HASH_LKP_TABLE", 0x12068, 0 },
+ { "MPS_RX_HASH_LKP_TABLE", 0x1206c, 0 },
+ { "MPS_CLS_SRAM_L", 0xe000, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe008, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe010, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe018, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe020, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe028, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe030, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe038, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe040, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe048, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe050, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe058, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe060, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
+ { "MultiListen0", 26, 1 },
+ { "Priority3", 23, 3 },
+ { "Priority2", 20, 3 },
+ { "Priority1", 17, 3 },
+ { "Priority0", 14, 3 },
+ { "Valid", 13, 1 },
+ { "Replicate", 12, 1 },
+ { "PF", 9, 3 },
+ { "VF_Valid", 8, 1 },
+ { "VF", 0, 8 },
+ { "MPS_CLS_SRAM_L", 0xe068, 0 },
+ { "DisEncapOuterRplct", 31, 1 },
+ { "DisEncap", 30, 1 },
+ { "MultiListen3", 29, 1 },
+ { "MultiListen2", 28, 1 },
+ { "MultiListen1", 27, 1 },
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+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xedfc, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee04, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee0c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee14, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee1c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee24, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee2c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee34, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee3c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee44, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee4c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee54, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee5c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee64, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee6c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee74, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee7c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee84, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee8c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee94, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xee9c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeea4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeeac, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeeb4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeebc, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeec4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeecc, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeed4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeedc, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeee4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeeec, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeef4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeefc, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef04, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef0c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef14, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef1c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef24, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef2c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef34, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef3c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef44, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef4c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef54, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef5c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef64, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef6c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef74, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef7c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef84, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef8c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef94, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xef9c, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefa4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefac, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefb4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefbc, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefc4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefcc, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefd4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefdc, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefe4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xefec, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeff4, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_SRAM_H", 0xeffc, 0 },
+ { "MacParity2", 10, 1 },
+ { "MacParity1", 9, 1 },
+ { "MacParity0", 8, 1 },
+ { "MacParityMaskSize", 4, 4 },
+ { "PortMap", 0, 4 },
+ { "MPS_CLS_TCAM_DATA0", 0xf000, 0 },
+ { "MPS_CLS_TCAM_DATA1", 0xf004, 0 },
+ { "VIDL", 16, 16 },
+ { "DMACH", 0, 16 },
+ { "MPS_CLS_TCAM_DATA2_CTL", 0xf008, 0 },
+ { "CtlCmdType", 31, 1 },
+ { "CtlReqID", 30, 1 },
+ { "CtlTcamSel", 25, 1 },
+ { "CtlTcamIndex", 17, 8 },
+ { "CtlXYBitSel", 16, 1 },
+ { "DataPortNum", 12, 4 },
+ { "DataLkpType", 10, 2 },
+ { "DataDipHit", 8, 1 },
+ { "DataVIDH2", 7, 1 },
+ { "DataVIDH1", 0, 7 },
+ { "MPS_CLS_TCAM_RDATA0_REQ_ID0", 0xf010, 0 },
+ { "MPS_CLS_TCAM_RDATA1_REQ_ID0", 0xf014, 0 },
+ { "VIDL", 16, 16 },
+ { "DMACH", 0, 16 },
+ { "MPS_CLS_TCAM_RDATA2_REQ_ID0", 0xf018, 0 },
+ { "DataPortNum", 12, 4 },
+ { "DataLkpType", 10, 2 },
+ { "DataDipHit", 8, 1 },
+ { "DataVIDH2", 7, 1 },
+ { "DataVIDH1", 0, 7 },
+ { "MPS_CLS_TCAM_RDATA0_REQ_ID1", 0xf020, 0 },
+ { "MPS_CLS_TCAM_RDATA1_REQ_ID1", 0xf024, 0 },
+ { "VIDL", 16, 16 },
+ { "DMACH", 0, 16 },
+ { "MPS_CLS_TCAM_RDATA2_REQ_ID1", 0xf028, 0 },
+ { "DataPortNum", 12, 4 },
+ { "DataLkpType", 10, 2 },
+ { "DataDipHit", 8, 1 },
+ { "DataVIDH2", 7, 1 },
+ { "DataVIDH1", 0, 7 },
+ { NULL }
+};
+
+struct reg_info t6_cpl_switch_regs[] = {
+ { "CPL_SWITCH_CNTRL", 0x19040, 0 },
+ { "cpl_pkt_tid", 8, 24 },
+ { "cim_split_enable", 6, 1 },
+ { "cim_truncate_enable", 5, 1 },
+ { "cim_to_up_full_size", 4, 1 },
+ { "cpu_no_enable", 3, 1 },
+ { "switch_table_enable", 2, 1 },
+ { "sge_enable", 1, 1 },
+ { "cim_enable", 0, 1 },
+ { "CPL_SWITCH_TBL_IDX", 0x19044, 0 },
+ { "CPL_SWITCH_TBL_DATA", 0x19048, 0 },
+ { "CPL_SWITCH_ZERO_ERROR", 0x1904c, 0 },
+ { "zero_cmd_ch1", 8, 8 },
+ { "zero_cmd_ch0", 0, 8 },
+ { "CPL_INTR_ENABLE", 0x19050, 0 },
+ { "perr_cpl_128to128_1", 7, 1 },
+ { "perr_cpl_128to128_0", 6, 1 },
+ { "cim_op_map_perr", 5, 1 },
+ { "cim_ovfl_error", 4, 1 },
+ { "tp_framing_error", 3, 1 },
+ { "sge_framing_error", 2, 1 },
+ { "cim_framing_error", 1, 1 },
+ { "zero_switch_error", 0, 1 },
+ { "CPL_INTR_CAUSE", 0x19054, 0 },
+ { "perr_cpl_128to128_1", 7, 1 },
+ { "perr_cpl_128to128_0", 6, 1 },
+ { "cim_op_map_perr", 5, 1 },
+ { "cim_ovfl_error", 4, 1 },
+ { "tp_framing_error", 3, 1 },
+ { "sge_framing_error", 2, 1 },
+ { "cim_framing_error", 1, 1 },
+ { "zero_switch_error", 0, 1 },
+ { "CPL_MAP_TBL_IDX", 0x19058, 0 },
+ { "cim_split_opcode_program", 8, 1 },
+ { "cpl_map_tbl_idx", 0, 8 },
+ { "CPL_MAP_TBL_DATA", 0x1905c, 0 },
+ { NULL }
+};
+
+struct reg_info t6_smb_regs[] = {
+ { "SMB_GLOBAL_TIME_CFG", 0x19060, 0 },
+ { "MacroCntCfg", 8, 5 },
+ { "MicroCntCfg", 0, 8 },
+ { "SMB_MST_TIMEOUT_CFG", 0x19064, 0 },
+ { "SMB_MST_CTL_CFG", 0x19068, 0 },
+ { "MstFifoDbg", 31, 1 },
+ { "MstFifoDbgClr", 30, 1 },
+ { "MstRxByteCfg", 12, 6 },
+ { "MstTxByteCfg", 6, 6 },
+ { "MstReset", 1, 1 },
+ { "MstCtlEn", 0, 1 },
+ { "SMB_MST_CTL_STS", 0x1906c, 0 },
+ { "MstRxByteCnt", 12, 6 },
+ { "MstTxByteCnt", 6, 6 },
+ { "MstBusySts", 0, 1 },
+ { "SMB_MST_TX_FIFO_RDWR", 0x19070, 0 },
+ { "SMB_MST_RX_FIFO_RDWR", 0x19074, 0 },
+ { "SMB_SLV_TIMEOUT_CFG", 0x19078, 0 },
+ { "SMB_SLV_CTL_CFG", 0x1907c, 0 },
+ { "SlvFifoDbg", 31, 1 },
+ { "SlvFifoDbgClr", 30, 1 },
+ { "SlvCrcOutBitInv", 21, 1 },
+ { "SlvCrcOutBitRev", 20, 1 },
+ { "SlvCrcInBitRev", 19, 1 },
+ { "SlvCrcPreset", 11, 8 },
+ { "SlvAddrCfg", 4, 7 },
+ { "SlvAlrtSet", 2, 1 },
+ { "SlvReset", 1, 1 },
+ { "SlvCtlEn", 0, 1 },
+ { "SMB_SLV_CTL_STS", 0x19080, 0 },
+ { "SlvFifoTxCnt", 12, 6 },
+ { "SlvFifoCnt", 6, 6 },
+ { "SlvAlrtSts", 2, 1 },
+ { "SlvBusySts", 0, 1 },
+ { "SMB_SLV_FIFO_RDWR", 0x19084, 0 },
+ { "SMB_INT_ENABLE", 0x1908c, 0 },
+ { "MstTxFifoParEn", 21, 1 },
+ { "MstRxFifoParEn", 20, 1 },
+ { "SlvFifoParEn", 19, 1 },
+ { "SlvUnExpBusStopEn", 18, 1 },
+ { "SlvUnExpBusStartEn", 17, 1 },
+ { "SlvCommandCodeInvEn", 16, 1 },
+ { "SlvByteCntErrEn", 15, 1 },
+ { "SlvUnExpAckMstEn", 14, 1 },
+ { "SlvUnExpNackMstEn", 13, 1 },
+ { "SlvNoBusStopEn", 12, 1 },
+ { "SlvNoRepStartEn", 11, 1 },
+ { "SlvRxAddrIntEn", 10, 1 },
+ { "SlvRxPecErrIntEn", 9, 1 },
+ { "SlvPrepToArpIntEn", 8, 1 },
+ { "SlvTimeOutIntEn", 7, 1 },
+ { "SlvErrIntEn", 6, 1 },
+ { "SlvDoneIntEn", 5, 1 },
+ { "SlvRxRdyIntEn", 4, 1 },
+ { "MstTimeOutIntEn", 3, 1 },
+ { "MstNAckIntEn", 2, 1 },
+ { "MstLostArbIntEn", 1, 1 },
+ { "MstDoneIntEn", 0, 1 },
+ { "SMB_INT_CAUSE", 0x19090, 0 },
+ { "MstTxFifoParInt", 21, 1 },
+ { "MstRxFifoParInt", 20, 1 },
+ { "SlvFifoParInt", 19, 1 },
+ { "SlvUnExpBusStopInt", 18, 1 },
+ { "SlvUnExpBusStartInt", 17, 1 },
+ { "SlvCommandCodeInvInt", 16, 1 },
+ { "SlvByteCntErrInt", 15, 1 },
+ { "SlvUnExpAckMstInt", 14, 1 },
+ { "SlvUnExpNackMstInt", 13, 1 },
+ { "SlvNoBusStopInt", 12, 1 },
+ { "SlvNoRepStartInt", 11, 1 },
+ { "SlvRxAddrInt", 10, 1 },
+ { "SlvRxPecErrInt", 9, 1 },
+ { "SlvPrepToArpInt", 8, 1 },
+ { "SlvTimeOutInt", 7, 1 },
+ { "SlvErrInt", 6, 1 },
+ { "SlvDoneInt", 5, 1 },
+ { "SlvRxRdyInt", 4, 1 },
+ { "MstTimeOutInt", 3, 1 },
+ { "MstNAckInt", 2, 1 },
+ { "MstLostArbInt", 1, 1 },
+ { "MstDoneInt", 0, 1 },
+ { "SMB_DEBUG_DATA", 0x19094, 0 },
+ { "DebugDataH", 16, 16 },
+ { "DebugDataL", 0, 16 },
+ { "SMB_PERR_EN", 0x19098, 0 },
+ { "MstTxFifo", 21, 1 },
+ { "MstRxFifo", 19, 1 },
+ { "SlvFifo", 18, 1 },
+ { "MstTxFifoPerrEn", 2, 1 },
+ { "MstRxFifoPerrEn", 1, 1 },
+ { "SlvFifoPerrEn", 0, 1 },
+ { "SMB_PERR_INJ", 0x1909c, 0 },
+ { "MstTxInjDataErr", 3, 1 },
+ { "MstRxInjDataErr", 2, 1 },
+ { "SlvInjDataErr", 1, 1 },
+ { "FifoInjDataErrEn", 0, 1 },
+ { "SMB_SLV_ARP_CTL", 0x190a0, 0 },
+ { "ArpCommandCode", 2, 8 },
+ { "ArpAddrRes", 1, 1 },
+ { "ArpAddrVal", 0, 1 },
+ { "SMB_ARP_UDID0", 0x190a4, 0 },
+ { "SMB_ARP_UDID1", 0x190a8, 0 },
+ { "SubsystemVendorID", 16, 16 },
+ { "SubsystemDeviceID", 0, 16 },
+ { "SMB_ARP_UDID2", 0x190ac, 0 },
+ { "DeviceID", 16, 16 },
+ { "Interface", 0, 16 },
+ { "SMB_ARP_UDID3", 0x190b0, 0 },
+ { "DeviceCap", 24, 8 },
+ { "VersionID", 16, 8 },
+ { "VendorID", 0, 16 },
+ { "SMB_SLV_AUX_ADDR0", 0x190b4, 0 },
+ { "AuxAddr0Val", 6, 1 },
+ { "AuxAddr0", 0, 6 },
+ { "SMB_SLV_AUX_ADDR1", 0x190b8, 0 },
+ { "AuxAddr1Val", 6, 1 },
+ { "AuxAddr1", 0, 6 },
+ { "SMB_SLV_AUX_ADDR2", 0x190bc, 0 },
+ { "AuxAddr2Val", 6, 1 },
+ { "AuxAddr2", 0, 6 },
+ { "SMB_SLV_AUX_ADDR3", 0x190c0, 0 },
+ { "AuxAddr3Val", 6, 1 },
+ { "AuxAddr3", 0, 6 },
+ { "SMB_COMMAND_CODE0", 0x190c4, 0 },
+ { "SMB_COMMAND_CODE1", 0x190c8, 0 },
+ { "SMB_COMMAND_CODE2", 0x190cc, 0 },
+ { "SMB_COMMAND_CODE3", 0x190d0, 0 },
+ { "SMB_COMMAND_CODE4", 0x190d4, 0 },
+ { "SMB_COMMAND_CODE5", 0x190d8, 0 },
+ { "SMB_COMMAND_CODE6", 0x190dc, 0 },
+ { "SMB_COMMAND_CODE7", 0x190e0, 0 },
+ { "SMB_MICRO_CNT_CLK_CFG", 0x190e4, 0 },
+ { "MacroCntClkCfg", 8, 5 },
+ { "MicroCntClkCfg", 0, 8 },
+ { "SMB_CTL_STATUS", 0x190e8, 0 },
+ { "MstBusBusy", 2, 1 },
+ { "SlvBusBusy", 1, 1 },
+ { "BusBusy", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t6_i2cm_regs[] = {
+ { "I2CM_CFG", 0x190f0, 0 },
+ { "I2CM_DATA", 0x190f4, 0 },
+ { "I2CM_OP", 0x190f8, 0 },
+ { "Busy", 31, 1 },
+ { "Ack", 30, 1 },
+ { "Cont", 1, 1 },
+ { "Op", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t6_mi_regs[] = {
+ { "MI_CFG", 0x19100, 0 },
+ { "T4_St", 14, 1 },
+ { "ClkDiv", 5, 8 },
+ { "St", 3, 2 },
+ { "PreEn", 2, 1 },
+ { "MDIInv", 1, 1 },
+ { "MDIO_1P2V_Sel", 0, 1 },
+ { "MI_ADDR", 0x19104, 0 },
+ { "PhyAddr", 5, 5 },
+ { "RegAddr", 0, 5 },
+ { "MI_DATA", 0x19108, 0 },
+ { "MI_OP", 0x1910c, 0 },
+ { "Busy", 31, 1 },
+ { "St", 3, 2 },
+ { "Inc", 2, 1 },
+ { "Op", 0, 2 },
+ { NULL }
+};
+
+struct reg_info t6_uart_regs[] = {
+ { "UART_CONFIG", 0x19110, 0 },
+ { "StopBits", 22, 2 },
+ { "Parity", 20, 2 },
+ { "DataBits", 16, 4 },
+ { "ClkDiv", 0, 12 },
+ { NULL }
+};
+
+struct reg_info t6_pmu_regs[] = {
+ { "PMU_PART_CG_PWRMODE", 0x19120, 0 },
+ { "PL_DIS_PRTY_CHK", 20, 1 },
+ { "SGE_Part_CGEn", 19, 1 },
+ { "PDP_Part_CGEn", 18, 1 },
+ { "TP_Part_CGEn", 17, 1 },
+ { "EDC0_Part_CGEn", 16, 1 },
+ { "EDC1_Part_CGEn", 15, 1 },
+ { "LE_Part_CGEn", 14, 1 },
+ { "MA_Part_CGEn", 13, 1 },
+ { "PCIE_Part_CGEn", 10, 1 },
+ { "InitPowerMode", 0, 2 },
+ { "PMU_SLEEPMODE_WAKEUP", 0x19124, 0 },
+ { "GlobalDeepSleepEn", 6, 1 },
+ { "HWWakeUpEn", 5, 1 },
+ { "Port3SleepMode", 4, 1 },
+ { "Port2SleepMode", 3, 1 },
+ { "Port1SleepMode", 2, 1 },
+ { "Port0SleepMode", 1, 1 },
+ { "WakeUp", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t6_ulp_rx_regs[] = {
+ { "ULP_RX_CTL", 0x19150, 0 },
+ { "PCMD1Threshold", 24, 8 },
+ { "PCMD0Threshold", 16, 8 },
+ { "disable_0B_STAG_ERR", 14, 1 },
+ { "RDMA_0b_wr_opcode", 10, 4 },
+ { "RDMA_0b_wr_pass", 9, 1 },
+ { "STAG_RQE", 8, 1 },
+ { "RDMA_State_En", 7, 1 },
+ { "Crc1_En", 6, 1 },
+ { "RDMA_0b_wr_cqe", 5, 1 },
+ { "PCIE_Atrb_En", 4, 1 },
+ { "RDMA_permissive_mode", 3, 1 },
+ { "PagePodME", 2, 1 },
+ { "IscsiTagTcb", 1, 1 },
+ { "TddpTagTcb", 0, 1 },
+ { "ULP_RX_INT_ENABLE", 0x19154, 0 },
+ { "SE_CNT_MISMATCH_1", 26, 1 },
+ { "SE_CNT_MISMATCH_0", 25, 1 },
+ { "ENABLE_CTX_1", 24, 1 },
+ { "ENABLE_CTX_0", 23, 1 },
+ { "ENABLE_FF", 22, 1 },
+ { "ENABLE_APF_1", 21, 1 },
+ { "ENABLE_APF_0", 20, 1 },
+ { "ENABLE_AF_1", 19, 1 },
+ { "ENABLE_AF_0", 18, 1 },
+ { "ENABLE_DDPDF_1", 17, 1 },
+ { "ENABLE_DDPMF_1", 16, 1 },
+ { "ENABLE_MEMRF_1", 15, 1 },
+ { "ENABLE_PRSDF_1", 14, 1 },
+ { "ENABLE_DDPDF_0", 13, 1 },
+ { "ENABLE_DDPMF_0", 12, 1 },
+ { "ENABLE_MEMRF_0", 11, 1 },
+ { "ENABLE_PRSDF_0", 10, 1 },
+ { "ENABLE_PCMDF_1", 9, 1 },
+ { "ENABLE_TPTCF_1", 8, 1 },
+ { "ENABLE_DDPCF_1", 7, 1 },
+ { "ENABLE_MPARF_1", 6, 1 },
+ { "ENABLE_MPARC_1", 5, 1 },
+ { "ENABLE_PCMDF_0", 4, 1 },
+ { "ENABLE_TPTCF_0", 3, 1 },
+ { "ENABLE_DDPCF_0", 2, 1 },
+ { "ENABLE_MPARF_0", 1, 1 },
+ { "ENABLE_MPARC_0", 0, 1 },
+ { "ULP_RX_INT_CAUSE", 0x19158, 0 },
+ { "SE_CNT_MISMATCH_1", 26, 1 },
+ { "SE_CNT_MISMATCH_0", 25, 1 },
+ { "CAUSE_CTX_1", 24, 1 },
+ { "CAUSE_CTX_0", 23, 1 },
+ { "CAUSE_FF", 22, 1 },
+ { "CAUSE_APF_1", 21, 1 },
+ { "CAUSE_APF_0", 20, 1 },
+ { "CAUSE_AF_1", 19, 1 },
+ { "CAUSE_AF_0", 18, 1 },
+ { "CAUSE_DDPDF_1", 17, 1 },
+ { "CAUSE_DDPMF_1", 16, 1 },
+ { "CAUSE_MEMRF_1", 15, 1 },
+ { "CAUSE_PRSDF_1", 14, 1 },
+ { "CAUSE_DDPDF_0", 13, 1 },
+ { "CAUSE_DDPMF_0", 12, 1 },
+ { "CAUSE_MEMRF_0", 11, 1 },
+ { "CAUSE_PRSDF_0", 10, 1 },
+ { "CAUSE_PCMDF_1", 9, 1 },
+ { "CAUSE_TPTCF_1", 8, 1 },
+ { "CAUSE_DDPCF_1", 7, 1 },
+ { "CAUSE_MPARF_1", 6, 1 },
+ { "CAUSE_MPARC_1", 5, 1 },
+ { "CAUSE_PCMDF_0", 4, 1 },
+ { "CAUSE_TPTCF_0", 3, 1 },
+ { "CAUSE_DDPCF_0", 2, 1 },
+ { "CAUSE_MPARF_0", 1, 1 },
+ { "CAUSE_MPARC_0", 0, 1 },
+ { "ULP_RX_ISCSI_LLIMIT", 0x1915c, 0 },
+ { "IscsiLlimit", 6, 26 },
+ { "ULP_RX_ISCSI_ULIMIT", 0x19160, 0 },
+ { "IscsiUlimit", 6, 26 },
+ { "ULP_RX_ISCSI_TAGMASK", 0x19164, 0 },
+ { "IscsiTagMask", 6, 26 },
+ { "ULP_RX_ISCSI_PSZ", 0x19168, 0 },
+ { "Hpz3", 24, 4 },
+ { "Hpz2", 16, 4 },
+ { "Hpz1", 8, 4 },
+ { "Hpz0", 0, 4 },
+ { "ULP_RX_TDDP_LLIMIT", 0x1916c, 0 },
+ { "TddpLlimit", 6, 26 },
+ { "ULP_RX_TDDP_ULIMIT", 0x19170, 0 },
+ { "TddpUlimit", 6, 26 },
+ { "ULP_RX_TDDP_TAGMASK", 0x19174, 0 },
+ { "TddpTagMask", 6, 26 },
+ { "ULP_RX_TDDP_PSZ", 0x19178, 0 },
+ { "Hpz3", 24, 4 },
+ { "Hpz2", 16, 4 },
+ { "Hpz1", 8, 4 },
+ { "Hpz0", 0, 4 },
+ { "ULP_RX_STAG_LLIMIT", 0x1917c, 0 },
+ { "ULP_RX_STAG_ULIMIT", 0x19180, 0 },
+ { "ULP_RX_RQ_LLIMIT", 0x19184, 0 },
+ { "ULP_RX_RQ_ULIMIT", 0x19188, 0 },
+ { "ULP_RX_PBL_LLIMIT", 0x1918c, 0 },
+ { "ULP_RX_PBL_ULIMIT", 0x19190, 0 },
+ { "ULP_RX_CTX_BASE", 0x19194, 0 },
+ { "ULP_RX_PERR_ENABLE", 0x1919c, 0 },
+ { "PERR_SE_CNT_MISMATCH_1", 26, 1 },
+ { "PERR_SE_CNT_MISMATCH_0", 25, 1 },
+ { "PERR_ENABLE_CTX_1", 24, 1 },
+ { "PERR_ENABLE_CTX_0", 23, 1 },
+ { "PERR_ENABLE_FF", 22, 1 },
+ { "PERR_ENABLE_APF_1", 21, 1 },
+ { "PERR_ENABLE_APF_0", 20, 1 },
+ { "PERR_ENABLE_AF_1", 19, 1 },
+ { "PERR_ENABLE_AF_0", 18, 1 },
+ { "PERR_ENABLE_DDPDF_1", 17, 1 },
+ { "PERR_ENABLE_DDPMF_1", 16, 1 },
+ { "PERR_ENABLE_MEMRF_1", 15, 1 },
+ { "PERR_ENABLE_PRSDF_1", 14, 1 },
+ { "PERR_ENABLE_DDPDF_0", 13, 1 },
+ { "PERR_ENABLE_DDPMF_0", 12, 1 },
+ { "PERR_ENABLE_MEMRF_0", 11, 1 },
+ { "PERR_ENABLE_PRSDF_0", 10, 1 },
+ { "PERR_ENABLE_PCMDF_1", 9, 1 },
+ { "PERR_ENABLE_TPTCF_1", 8, 1 },
+ { "PERR_ENABLE_DDPCF_1", 7, 1 },
+ { "PERR_ENABLE_MPARF_1", 6, 1 },
+ { "PERR_ENABLE_MPARC_1", 5, 1 },
+ { "PERR_ENABLE_PCMDF_0", 4, 1 },
+ { "PERR_ENABLE_TPTCF_0", 3, 1 },
+ { "PERR_ENABLE_DDPCF_0", 2, 1 },
+ { "PERR_ENABLE_MPARF_0", 1, 1 },
+ { "PERR_ENABLE_MPARC_0", 0, 1 },
+ { "ULP_RX_PERR_INJECT", 0x191a0, 0 },
+ { "MemSel", 1, 5 },
+ { "InjectDataErr", 0, 1 },
+ { "ULP_RX_RQUDP_LLIMIT", 0x191a4, 0 },
+ { "ULP_RX_RQUDP_ULIMIT", 0x191a8, 0 },
+ { "ULP_RX_CTX_ACC_CH0", 0x191ac, 0 },
+ { "REQ", 21, 1 },
+ { "WB", 20, 1 },
+ { "TID", 0, 20 },
+ { "ULP_RX_CTX_ACC_CH1", 0x191b0, 0 },
+ { "REQ", 21, 1 },
+ { "WB", 20, 1 },
+ { "TID", 0, 20 },
+ { "ULP_RX_SE_CNT_ERR", 0x191d0, 0 },
+ { "ERR_CH1", 4, 4 },
+ { "ERR_CH0", 0, 4 },
+ { "ULP_RX_SE_CNT_CLR", 0x191d4, 0 },
+ { "CLR_CH0", 4, 4 },
+ { "CLR_CH1", 0, 4 },
+ { "ULP_RX_SE_CNT_CH0", 0x191d8, 0 },
+ { "SOP_CNT_OUT0", 28, 4 },
+ { "EOP_CNT_OUT0", 24, 4 },
+ { "SOP_CNT_AL0", 20, 4 },
+ { "EOP_CNT_AL0", 16, 4 },
+ { "SOP_CNT_MR0", 12, 4 },
+ { "EOP_CNT_MR0", 8, 4 },
+ { "SOP_CNT_IN0", 4, 4 },
+ { "EOP_CNT_IN0", 0, 4 },
+ { "ULP_RX_SE_CNT_CH1", 0x191dc, 0 },
+ { "SOP_CNT_OUT1", 28, 4 },
+ { "EOP_CNT_OUT1", 24, 4 },
+ { "SOP_CNT_AL1", 20, 4 },
+ { "EOP_CNT_AL1", 16, 4 },
+ { "SOP_CNT_MR1", 12, 4 },
+ { "EOP_CNT_MR1", 8, 4 },
+ { "SOP_CNT_IN1", 4, 4 },
+ { "EOP_CNT_IN1", 0, 4 },
+ { "ULP_RX_DBG_CTL", 0x191e0, 0 },
+ { "EN_DBG_H", 17, 1 },
+ { "EN_DBG_L", 16, 1 },
+ { "SEL_H", 8, 8 },
+ { "SEL_L", 0, 8 },
+ { "ULP_RX_DBG_DATAH", 0x191e4, 0 },
+ { "ULP_RX_DBG_DATAL", 0x191e8, 0 },
+ { "ULP_RX_LA_CHNL", 0x19238, 0 },
+ { "ULP_RX_LA_CTL", 0x1923c, 0 },
+ { "ULP_RX_LA_RDPTR", 0x19240, 0 },
+ { "ULP_RX_LA_RDDATA", 0x19244, 0 },
+ { "ULP_RX_LA_WRPTR", 0x19248, 0 },
+ { "ULP_RX_LA_RESERVED", 0x1924c, 0 },
+ { "ULP_RX_CQE_GEN_EN", 0x19250, 0 },
+ { "Termimate_msg", 1, 1 },
+ { "Terminate_with_err", 0, 1 },
+ { "ULP_RX_ATOMIC_OPCODES", 0x19254, 0 },
+ { "atomic_req_qno", 22, 2 },
+ { "atomic_rsp_qno", 20, 2 },
+ { "immediate_qno", 18, 2 },
+ { "immediate_with_se_qno", 16, 2 },
+ { "atomic_wr_opcode", 12, 4 },
+ { "atomic_rd_opcode", 8, 4 },
+ { "immediate_opcode", 4, 4 },
+ { "immediate_with_se_opcode", 0, 4 },
+ { "ULP_RX_T10_CRC_ENDIAN_SWITCHING", 0x19258, 0 },
+ { "ULP_RX_MISC_FEATURE_ENABLE", 0x1925c, 0 },
+ { "iscsi_dcrc_error_cmp_en", 25, 1 },
+ { "IscsiTagPI", 24, 1 },
+ { "ddp_version_1", 22, 2 },
+ { "ddp_version_0", 20, 2 },
+ { "rdma_version_1", 18, 2 },
+ { "rdma_version_0", 16, 2 },
+ { "pbl_bound_check_w_pglen", 15, 1 },
+ { "zbyte_fix_disable", 14, 1 },
+ { "t10_offset_update_en", 13, 1 },
+ { "ulp_insert_pi", 12, 1 },
+ { "pdu_dpi", 11, 1 },
+ { "iscsi_eff_offset_en", 10, 1 },
+ { "iscsi_all_cmp_mode", 9, 1 },
+ { "iscsi_enable_hdr_cmd", 8, 1 },
+ { "iscsi_force_cmp_mode", 7, 1 },
+ { "iscsi_enable_cmp_mode", 6, 1 },
+ { "pio_rdma_send_rqe", 5, 1 },
+ { "terminate_status_en", 4, 1 },
+ { "multiple_pref_enable", 3, 1 },
+ { "umudp_pbl_pref_enable", 2, 1 },
+ { "rdma_pbl_pref_en", 1, 1 },
+ { "sdc_crc_prot_en", 0, 1 },
+ { "ULP_RX_CH0_CGEN", 0x19260, 0 },
+ { "BYPASS_CGEN", 7, 1 },
+ { "TDDP_CGEN", 6, 1 },
+ { "ISCSI_CGEN", 5, 1 },
+ { "RDMA_CGEN", 4, 1 },
+ { "CHANNEL_CGEN", 3, 1 },
+ { "All_DataPath_CGEN", 2, 1 },
+ { "T10Diff_DataPath_CGEN", 1, 1 },
+ { "Rdma_DataPath_CGEN", 0, 1 },
+ { "ULP_RX_CH1_CGEN", 0x19264, 0 },
+ { "BYPASS_CGEN", 7, 1 },
+ { "TDDP_CGEN", 6, 1 },
+ { "ISCSI_CGEN", 5, 1 },
+ { "RDMA_CGEN", 4, 1 },
+ { "CHANNEL_CGEN", 3, 1 },
+ { "All_DataPath_CGEN", 2, 1 },
+ { "T10Diff_DataPath_CGEN", 1, 1 },
+ { "Rdma_DataPath_CGEN", 0, 1 },
+ { "ULP_RX_RFE_DISABLE", 0x19268, 0 },
+ { "ULP_RX_INT_ENABLE_2", 0x1926c, 0 },
+ { "ULPRX2MA_IntfPerr", 8, 1 },
+ { "ALN_SDC_ERR_1", 7, 1 },
+ { "ALN_SDC_ERR_0", 6, 1 },
+ { "PF_UNTAGGED_TPT_1", 5, 1 },
+ { "PF_UNTAGGED_TPT_0", 4, 1 },
+ { "PF_PBL_1", 3, 1 },
+ { "PF_PBL_0", 2, 1 },
+ { "DDP_HINT_1", 1, 1 },
+ { "DDP_HINT_0", 0, 1 },
+ { "ULP_RX_INT_CAUSE_2", 0x19270, 0 },
+ { "ULPRX2MA_IntfPerr", 8, 1 },
+ { "ALN_SDC_ERR_1", 7, 1 },
+ { "ALN_SDC_ERR_0", 6, 1 },
+ { "PF_UNTAGGED_TPT_1", 5, 1 },
+ { "PF_UNTAGGED_TPT_0", 4, 1 },
+ { "PF_PBL_1", 3, 1 },
+ { "PF_PBL_0", 2, 1 },
+ { "DDP_HINT_1", 1, 1 },
+ { "DDP_HINT_0", 0, 1 },
+ { "ULP_RX_PERR_ENABLE_2", 0x19274, 0 },
+ { "ENABLE_ULPRX2MA_IntfPerr", 8, 1 },
+ { "ENABLE_ALN_SDC_ERR_1", 7, 1 },
+ { "ENABLE_ALN_SDC_ERR_0", 6, 1 },
+ { "ENABLE_PF_UNTAGGED_TPT_1", 5, 1 },
+ { "ENABLE_PF_UNTAGGED_TPT_0", 4, 1 },
+ { "ENABLE_PF_PBL_1", 3, 1 },
+ { "ENABLE_PF_PBL_0", 2, 1 },
+ { "ENABLE_DDP_HINT_1", 1, 1 },
+ { "ENABLE_DDP_HINT_0", 0, 1 },
+ { "ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT", 0x19278, 0 },
+ { "ULP_RX_ATOMIC_LEN", 0x1927c, 0 },
+ { "atomic_rpl_len", 16, 8 },
+ { "atomic_req_len", 8, 8 },
+ { "atomic_immediate_len", 0, 8 },
+ { "ULP_RX_CGEN_GLOBAL", 0x19280, 0 },
+ { "ULP_RX_CTX_SKIP_MA_REQ", 0x19284, 0 },
+ { "clear_ctx_err_cnt1", 3, 1 },
+ { "clear_ctx_err_cnt0", 2, 1 },
+ { "skip_ma_req_en1", 1, 1 },
+ { "skip_ma_req_en0", 0, 1 },
+ { "ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID", 0x19288, 0 },
+ { "ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID", 0x1928c, 0 },
+ { "ULP_RX_MSN_CHECK_ENABLE", 0x19290, 0 },
+ { "Rd_or_Term_msn_check_enable", 2, 1 },
+ { "atomic_op_msn_check_enable", 1, 1 },
+ { "send_msn_check_enable", 0, 1 },
+ { "ULP_RX_TLS_PP_LLIMIT", 0x192a4, 0 },
+ { "TlsPpLlimit", 6, 26 },
+ { "ULP_RX_TLS_PP_ULIMIT", 0x192a8, 0 },
+ { "TlsPpUlimit", 6, 26 },
+ { "ULP_RX_TLS_KEY_LLIMIT", 0x192ac, 0 },
+ { "TlsKeyLlimit", 8, 24 },
+ { "ULP_RX_TLS_KEY_ULIMIT", 0x192b0, 0 },
+ { "TlsKeyUlimit", 8, 24 },
+ { "ULP_RX_TLS_CTL", 0x192bc, 0 },
+ { "TlsPerrEn", 4, 1 },
+ { "TlsDisableIFuse", 2, 1 },
+ { "TlsDisableCFuse", 1, 1 },
+ { "TlsDisable", 0, 1 },
+ { "ULP_RX_TLS_IND_CMD", 0x19348, 0 },
+ { "ULP_RX_TLS_IND_DATA", 0x1934c, 0 },
+ { NULL }
+};
+
+struct reg_info t6_sf_regs[] = {
+ { "SF_DATA", 0x193f8, 0 },
+ { "SF_OP", 0x193fc, 0 },
+ { "Busy", 31, 1 },
+ { "Lock", 4, 1 },
+ { "Cont", 3, 1 },
+ { "ByteCnt", 1, 2 },
+ { "Op", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t6_pl_regs[] = {
+ { "PL_PF_INT_CAUSE", 0x1e3c0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1e3c4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1e3c8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1e7c0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1e7c4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1e7c8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1ebc0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1ebc4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1ebc8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1efc0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1efc4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1efc8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1f3c0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1f3c4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1f3c8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1f7c0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1f7c4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1f7c8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1fbc0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1fbc4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1fbc8, 0 },
+ { "PL_PF_INT_CAUSE", 0x1ffc0, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_INT_ENABLE", 0x1ffc4, 0 },
+ { "SW", 3, 1 },
+ { "CIM", 1, 1 },
+ { "MPS", 0, 1 },
+ { "PL_PF_CTL", 0x1ffc8, 0 },
+ { "PL_WHOAMI", 0x19400, 0 },
+ { "PortxMap", 24, 3 },
+ { "SourceBus", 16, 2 },
+ { "SourcePF", 9, 3 },
+ { "IsVF", 8, 1 },
+ { "VFID", 0, 8 },
+ { "PL_PERR_CAUSE", 0x19404, 0 },
+ { "UART", 28, 1 },
+ { "ULP_TX", 27, 1 },
+ { "SGE", 26, 1 },
+ { "HMA", 25, 1 },
+ { "CPL_SWITCH", 24, 1 },
+ { "ULP_RX", 23, 1 },
+ { "PM_RX", 22, 1 },
+ { "PM_TX", 21, 1 },
+ { "MA", 20, 1 },
+ { "TP", 19, 1 },
+ { "LE", 18, 1 },
+ { "EDC1", 17, 1 },
+ { "EDC0", 16, 1 },
+ { "MC0", 15, 1 },
+ { "PCIE", 14, 1 },
+ { "PMU", 13, 1 },
+ { "MAC", 9, 1 },
+ { "SMB", 8, 1 },
+ { "SF", 7, 1 },
+ { "PL", 6, 1 },
+ { "NCSI", 5, 1 },
+ { "MPS", 4, 1 },
+ { "MI", 3, 1 },
+ { "DBG", 2, 1 },
+ { "I2CM", 1, 1 },
+ { "CIM", 0, 1 },
+ { "PL_PERR_ENABLE", 0x19408, 0 },
+ { "UART", 28, 1 },
+ { "ULP_TX", 27, 1 },
+ { "SGE", 26, 1 },
+ { "HMA", 25, 1 },
+ { "CPL_SWITCH", 24, 1 },
+ { "ULP_RX", 23, 1 },
+ { "PM_RX", 22, 1 },
+ { "PM_TX", 21, 1 },
+ { "MA", 20, 1 },
+ { "TP", 19, 1 },
+ { "LE", 18, 1 },
+ { "EDC1", 17, 1 },
+ { "EDC0", 16, 1 },
+ { "MC0", 15, 1 },
+ { "PCIE", 14, 1 },
+ { "PMU", 13, 1 },
+ { "MAC", 9, 1 },
+ { "SMB", 8, 1 },
+ { "SF", 7, 1 },
+ { "PL", 6, 1 },
+ { "NCSI", 5, 1 },
+ { "MPS", 4, 1 },
+ { "MI", 3, 1 },
+ { "DBG", 2, 1 },
+ { "I2CM", 1, 1 },
+ { "CIM", 0, 1 },
+ { "PL_INT_CAUSE", 0x1940c, 0 },
+ { "FLR", 30, 1 },
+ { "SW_CIM", 29, 1 },
+ { "UART", 28, 1 },
+ { "ULP_TX", 27, 1 },
+ { "SGE", 26, 1 },
+ { "HMA", 25, 1 },
+ { "CPL_SWITCH", 24, 1 },
+ { "ULP_RX", 23, 1 },
+ { "PM_RX", 22, 1 },
+ { "PM_TX", 21, 1 },
+ { "MA", 20, 1 },
+ { "TP", 19, 1 },
+ { "LE", 18, 1 },
+ { "EDC1", 17, 1 },
+ { "EDC0", 16, 1 },
+ { "MC0", 15, 1 },
+ { "PCIE", 14, 1 },
+ { "PMU", 13, 1 },
+ { "MAC1", 10, 1 },
+ { "MAC0", 9, 1 },
+ { "SMB", 8, 1 },
+ { "SF", 7, 1 },
+ { "PL", 6, 1 },
+ { "NCSI", 5, 1 },
+ { "MPS", 4, 1 },
+ { "MI", 3, 1 },
+ { "DBG", 2, 1 },
+ { "I2CM", 1, 1 },
+ { "CIM", 0, 1 },
+ { "PL_INT_ENABLE", 0x19410, 0 },
+ { "FLR", 30, 1 },
+ { "SW_CIM", 29, 1 },
+ { "UART", 28, 1 },
+ { "ULP_TX", 27, 1 },
+ { "SGE", 26, 1 },
+ { "HMA", 25, 1 },
+ { "CPL_SWITCH", 24, 1 },
+ { "ULP_RX", 23, 1 },
+ { "PM_RX", 22, 1 },
+ { "PM_TX", 21, 1 },
+ { "MA", 20, 1 },
+ { "TP", 19, 1 },
+ { "LE", 18, 1 },
+ { "EDC1", 17, 1 },
+ { "EDC0", 16, 1 },
+ { "MC0", 15, 1 },
+ { "PCIE", 14, 1 },
+ { "PMU", 13, 1 },
+ { "MAC1", 10, 1 },
+ { "MAC0", 9, 1 },
+ { "SMB", 8, 1 },
+ { "SF", 7, 1 },
+ { "PL", 6, 1 },
+ { "NCSI", 5, 1 },
+ { "MPS", 4, 1 },
+ { "MI", 3, 1 },
+ { "DBG", 2, 1 },
+ { "I2CM", 1, 1 },
+ { "CIM", 0, 1 },
+ { "PL_INT_MAP0", 0x19414, 0 },
+ { "MapNCSI", 16, 9 },
+ { "MapDefault", 0, 9 },
+ { "PL_INT_MAP1", 0x19418, 0 },
+ { "MapMAC1", 16, 9 },
+ { "MapMAC0", 0, 9 },
+ { "PL_INT_MAP3", 0x19420, 0 },
+ { "MapMI", 16, 9 },
+ { "MapSMB", 0, 9 },
+ { "PL_INT_MAP4", 0x19424, 0 },
+ { "MapDBG", 16, 9 },
+ { "MapI2CM", 0, 9 },
+ { "PL_RST", 0x19428, 0 },
+ { "AutoPciePause", 4, 1 },
+ { "FatalPerrEn", 3, 1 },
+ { "SWIntCIM", 2, 1 },
+ { "PIORst", 1, 1 },
+ { "PIORstMode", 0, 1 },
+ { "PL_PL_INT_CAUSE", 0x19430, 0 },
+ { "PL_BusPerr", 6, 1 },
+ { "FatalPerr", 4, 1 },
+ { "InvalidAccess", 3, 1 },
+ { "Timeout", 2, 1 },
+ { "PLErr", 1, 1 },
+ { "PL_PL_INT_ENABLE", 0x19434, 0 },
+ { "PL_BusPerr", 6, 1 },
+ { "FatalPerr", 4, 1 },
+ { "InvalidAccess", 3, 1 },
+ { "Timeout", 2, 1 },
+ { "PLErr", 1, 1 },
+ { "PL_PL_PERR_ENABLE", 0x19438, 0 },
+ { "PL_BusPerr", 6, 1 },
+ { "PL_REV", 0x1943c, 0 },
+ { "ChipID", 4, 4 },
+ { "Rev", 0, 4 },
+ { "PL_PCIE_LINK", 0x19440, 0 },
+ { "LN0_AESTAT", 27, 3 },
+ { "LN0_AECMD", 24, 3 },
+ { "StateCfgInitF", 16, 8 },
+ { "StateCfgInit", 12, 4 },
+ { "PHY_STATUS", 10, 1 },
+ { "SPEED", 8, 2 },
+ { "PERstTimeout", 7, 1 },
+ { "LTSSMEnable", 6, 1 },
+ { "LTSSM", 0, 6 },
+ { "PL_PCIE_CTL_STAT", 0x19444, 0 },
+ { "Status", 16, 16 },
+ { "Control", 0, 16 },
+ { "PL_SEMAPHORE_CTL", 0x1944c, 0 },
+ { "LockStatus", 16, 8 },
+ { "OwnerOverride", 8, 1 },
+ { "EnablePF", 0, 8 },
+ { "PL_SEMAPHORE_LOCK", 0x19450, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x19454, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x19458, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x1945c, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x19460, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x19464, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x19468, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_SEMAPHORE_LOCK", 0x1946c, 0 },
+ { "Lock", 31, 1 },
+ { "SourceBus", 3, 2 },
+ { "SourcePF", 0, 3 },
+ { "PL_PORTX_MAP", 0x19474, 0 },
+ { "MAP7", 28, 3 },
+ { "MAP6", 24, 3 },
+ { "MAP5", 20, 3 },
+ { "MAP4", 16, 3 },
+ { "MAP3", 12, 3 },
+ { "MAP2", 8, 3 },
+ { "MAP1", 4, 3 },
+ { "MAP0", 0, 3 },
+ { "PL_VF_SLICE_L", 0x19490, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x19498, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194a0, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194a8, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194b0, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194b8, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194c0, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_L", 0x194c8, 0 },
+ { "LimitAddr", 16, 10 },
+ { "BaseAddr", 0, 10 },
+ { "PL_VF_SLICE_H", 0x19494, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x1949c, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194a4, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194ac, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194b4, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194bc, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194c4, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_VF_SLICE_H", 0x194cc, 0 },
+ { "ModIndx", 16, 3 },
+ { "ModOffset", 0, 10 },
+ { "PL_TIMEOUT_CTL", 0x194f0, 0 },
+ { "PerrCapture", 16, 1 },
+ { "Timeout", 0, 16 },
+ { "PL_TIMEOUT_STATUS0", 0x194f4, 0 },
+ { "Addr", 2, 28 },
+ { "PL_TIMEOUT_STATUS1", 0x194f8, 0 },
+ { "Valid", 31, 1 },
+ { "ValidPerr", 30, 1 },
+ { "Write", 22, 1 },
+ { "Bus", 20, 2 },
+ { "PF", 16, 3 },
+ { "VFID", 0, 9 },
+ { NULL }
+};
+
+struct reg_info t6_le_regs[] = {
+ { "LE_DB_ID", 0x19c00, 0 },
+ { "LE_DB_CONFIG", 0x19c04, 0 },
+ { "CHK_FUL_TUP_ZERO", 27, 1 },
+ { "PRI_HASH", 26, 1 },
+ { "EXTN_HASH_IPV4", 25, 1 },
+ { "PROTOCOLMASKEN", 24, 1 },
+ { "SRVRSRAMEN", 22, 1 },
+ { "HASHEN", 20, 1 },
+ { "ASLIPCOMPEN_IPV4", 18, 1 },
+ { "BUILD", 16, 1 },
+ { "IGNR_TUP_ZERO", 9, 1 },
+ { "IGNR_LIP_ZERO", 8, 1 },
+ { "CLCAM_INIT_BUSY", 7, 1 },
+ { "CLCAM_INIT", 6, 1 },
+ { "MTCAM_INIT_BUSY", 5, 1 },
+ { "MTCAM_INIT", 4, 1 },
+ { "REGION_EN", 0, 4 },
+ { "LE_DB_EXEC_CTRL", 0x19c08, 0 },
+ { "TPDB_IF_PAUSE_ACK", 10, 1 },
+ { "TPDB_IF_PAUSE_REQ", 9, 1 },
+ { "ERRSTOP_EN", 8, 1 },
+ { "CMDLIMIT", 0, 8 },
+ { "LE_DB_PS_CTRL", 0x19c0c, 0 },
+ { "SRAMDEEPSLEEP_STAT", 11, 1 },
+ { "CLTCAMDEEPSLEEP_STAT", 10, 1 },
+ { "TCAMDEEPSLEEP_STAT", 9, 1 },
+ { "SRAMDEEPSLEEP", 8, 1 },
+ { "CLTCAMDEEPSLEEP", 7, 1 },
+ { "TCAMDEEPSLEEP", 6, 1 },
+ { "SRVRAMCLKOFF", 5, 1 },
+ { "HASHCLKOFF", 4, 1 },
+ { "LE_DB_ACTIVE_TABLE_START_INDEX", 0x19c10, 0 },
+ { "LE_DB_NORM_FILT_TABLE_START_INDEX", 0x19c14, 0 },
+ { "LE_DB_SRVR_START_INDEX", 0x19c18, 0 },
+ { "LE_DB_HPRI_FILT_TABLE_START_INDEX", 0x19c1c, 0 },
+ { "LE_DB_ACT_CNT_IPV4", 0x19c20, 0 },
+ { "LE_DB_ACT_CNT_IPV6", 0x19c24, 0 },
+ { "LE_DB_ACT_CNT_IPV4_TCAM", 0x19c94, 0 },
+ { "LE_DB_ACT_CNT_IPV6_TCAM", 0x19c98, 0 },
+ { "LE_DB_REQ_RSP_CNT", 0x19ce4, 0 },
+ { "RspCnt", 16, 16 },
+ { "ReqCnt", 0, 16 },
+ { "LE_HASH_COLLISION", 0x19fc4, 0 },
+ { "LE_GLOBAL_COLLISION", 0x19fc8, 0 },
+ { "LE_DB_HASH_CONFIG", 0x19c28, 0 },
+ { "NUMHASHBKT", 20, 5 },
+ { "HASHTBLSIZE", 3, 17 },
+ { "LE_DB_MIN_NUM_ACTV_TCAM_ENTRIES", 0x19c2c, 0 },
+ { "LE_DB_MAX_NUM_HASH_ENTRIES", 0x19c70, 0 },
+ { "LE_DB_RSP_CODE_0", 0x19c74, 0 },
+ { "SUCCESS", 25, 5 },
+ { "TCAM_ACTV_SUCC", 20, 5 },
+ { "HASH_ACTV_SUCC", 15, 5 },
+ { "TCAM_SRVR_HIT", 10, 5 },
+ { "SRAM_SRVR_HIT", 5, 5 },
+ { "TCAM_ACTV_HIT", 0, 5 },
+ { "LE_DB_RSP_CODE_1", 0x19c78, 0 },
+ { "HASH_ACTV_HIT", 25, 5 },
+ { "MISS", 20, 5 },
+ { "NORM_FILT_HIT", 15, 5 },
+ { "HPRI_FILT_HIT", 10, 5 },
+ { "ACTV_OPEN_ERR", 5, 5 },
+ { "ACTV_FULL_ERR", 0, 5 },
+ { "LE_DB_RSP_CODE_2", 0x19c7c, 0 },
+ { "SRCH_RGN_HIT", 25, 5 },
+ { "CLIP_FAIL", 20, 5 },
+ { "LIP_ZERO_ERR", 15, 5 },
+ { "UNKNOWN_CMD", 10, 5 },
+ { "CMD_TID_ERR", 5, 5 },
+ { "INTERNAL_ERR", 0, 5 },
+ { "LE_DB_RSP_CODE_3", 0x19c80, 0 },
+ { "SRAM_SRVR_HIT_ACTF", 25, 5 },
+ { "TCAM_SRVR_HIT_ACTF", 20, 5 },
+ { "INVLDRD", 15, 5 },
+ { "TUPLZERO", 10, 5 },
+ { "LE_DB_HASH_TBL_BASE_ADDR", 0x19c30, 0 },
+ { "HASHTBLADDR", 4, 28 },
+ { "LE_TCAM_SIZE", 0x19c34, 0 },
+ { "LE_DB_INT_ENABLE", 0x19c38, 0 },
+ { "ClipSubErr", 29, 1 },
+ { "ClCamFifoerr", 28, 1 },
+ { "HashTblMemCrcErr", 27, 1 },
+ { "CTcamInvldEnt", 26, 1 },
+ { "TcamInvldEnt", 25, 1 },
+ { "TotCntErr", 24, 1 },
+ { "CmdPrsrIntErr", 23, 1 },
+ { "CmdTidErr", 22, 1 },
+ { "ActRgnFull", 21, 1 },
+ { "ActCntIPv6Tzero", 20, 1 },
+ { "ActCntIPv4Tzero", 19, 1 },
+ { "ActCntIPv6zero", 18, 1 },
+ { "ActCntIPv4zero", 17, 1 },
+ { "MaifwrIntPerr", 16, 1 },
+ { "HashTblMemAccErr", 15, 1 },
+ { "TcamCrcErr", 14, 1 },
+ { "TcamIntPerr", 13, 1 },
+ { "VfSramPerr", 12, 1 },
+ { "SrvSramPerr", 11, 1 },
+ { "SsramIntPerr", 10, 1 },
+ { "ClCamIntPerr", 9, 1 },
+ { "ClCamCrcParErr", 8, 1 },
+ { "HashTblAccFail", 7, 1 },
+ { "TcamAccFail", 6, 1 },
+ { "SrvSramAccFail", 5, 1 },
+ { "ClipTcamAccFail", 4, 1 },
+ { "UnknownCmd", 3, 1 },
+ { "LIP0", 2, 1 },
+ { "LIPMiss", 1, 1 },
+ { "PipelineErr", 0, 1 },
+ { "LE_DB_INT_CAUSE", 0x19c3c, 0 },
+ { "ClipSubErr", 29, 1 },
+ { "ClCamFifoerr", 28, 1 },
+ { "HashTblMemCrcErr", 27, 1 },
+ { "CTcamInvldEnt", 26, 1 },
+ { "TcamInvldEnt", 25, 1 },
+ { "TotCntErr", 24, 1 },
+ { "CmdPrsrIntErr", 23, 1 },
+ { "CmdTidErr", 22, 1 },
+ { "ActRgnFull", 21, 1 },
+ { "ActCntIPv6Tzero", 20, 1 },
+ { "ActCntIPv4Tzero", 19, 1 },
+ { "ActCntIPv6zero", 18, 1 },
+ { "ActCntIPv4zero", 17, 1 },
+ { "MaifwrIntPerr", 16, 1 },
+ { "HashTblMemAccErr", 15, 1 },
+ { "TcamCrcErr", 14, 1 },
+ { "TcamIntPerr", 13, 1 },
+ { "VfSramPerr", 12, 1 },
+ { "SrvSramPerr", 11, 1 },
+ { "SsramIntPerr", 10, 1 },
+ { "ClCamIntPerr", 9, 1 },
+ { "ClCamCrcParErr", 8, 1 },
+ { "HashTblAccFail", 7, 1 },
+ { "TcamAccFail", 6, 1 },
+ { "SrvSramAccFail", 5, 1 },
+ { "ClipTcamAccFail", 4, 1 },
+ { "UnknownCmd", 3, 1 },
+ { "LIP0", 2, 1 },
+ { "LIPMiss", 1, 1 },
+ { "PipelineErr", 0, 1 },
+ { "LE_PERR_ENABLE", 0x19cf8, 0 },
+ { "BkChkPeriod", 22, 10 },
+ { "TcamBkChkEn", 21, 1 },
+ { "MaifwrIntPerr", 16, 1 },
+ { "HashTblMemAccErr", 15, 1 },
+ { "TcamCrcErr", 14, 1 },
+ { "TcamIntPerr", 13, 1 },
+ { "VfSramPerr", 12, 1 },
+ { "SrvSramPerr", 11, 1 },
+ { "SsramIntPerr", 10, 1 },
+ { "ClCamIntPerr", 9, 1 },
+ { "ClCamCrcParErr", 8, 1 },
+ { "HashTblAccFail", 7, 1 },
+ { "TcamAccFail", 6, 1 },
+ { "SrvSramAccFail", 5, 1 },
+ { "ClipTcamAccFail", 4, 1 },
+ { "ClCamFifoerr", 2, 1 },
+ { "HashTblMemCrcErr", 1, 1 },
+ { "PipelineErr", 0, 1 },
+ { "LE_DB_ERR_CMD_TID", 0x19c48, 0 },
+ { "ERR_CID", 22, 8 },
+ { "ERR_PROT", 20, 2 },
+ { "ERR_TID", 0, 20 },
+ { "LE_DB_DBG_MATCH_DATA_MASK", 0x19c50, 0 },
+ { "LE_DB_DBG_MATCH_DATA_MASK", 0x19c54, 0 },
+ { "LE_DB_DBG_MATCH_DATA_MASK", 0x19c58, 0 },
+ { "LE_DB_DBG_MATCH_DATA_MASK", 0x19c5c, 0 },
+ { "LE_DB_DBG_MATCH_DATA_MASK", 0x19c60, 0 },
+ { "LE_DB_DBG_MATCH_DATA_MASK", 0x19c64, 0 },
+ { "LE_DB_DBG_MATCH_DATA_MASK", 0x19c68, 0 },
+ { "LE_DB_DBG_MATCH_DATA_MASK", 0x19c6c, 0 },
+ { "LE_DB_DBG_MATCH_DATA", 0x19ca0, 0 },
+ { "LE_DB_DBG_MATCH_DATA", 0x19ca4, 0 },
+ { "LE_DB_DBG_MATCH_DATA", 0x19ca8, 0 },
+ { "LE_DB_DBG_MATCH_DATA", 0x19cac, 0 },
+ { "LE_DB_DBG_MATCH_DATA", 0x19cb0, 0 },
+ { "LE_DB_DBG_MATCH_DATA", 0x19cb4, 0 },
+ { "LE_DB_DBG_MATCH_DATA", 0x19cb8, 0 },
+ { "LE_DB_DBG_MATCH_DATA", 0x19cbc, 0 },
+ { "LE_DB_DBG_MATCH_CMD_IDX_MASK", 0x19c40, 0 },
+ { "CMD_CMP_MASK", 20, 5 },
+ { "TID_CMP_MASK", 0, 20 },
+ { "LE_DB_DBG_MATCH_CMD_IDX_DATA", 0x19c44, 0 },
+ { "CMD_CMP", 20, 5 },
+ { "TID_CMP", 0, 20 },
+ { "LE_DB_DBGI_CONFIG", 0x19cf0, 0 },
+ { "DBGICMDRANGE", 22, 3 },
+ { "DBGICMDMSKREAD", 21, 1 },
+ { "DBGICMDSEARCH", 20, 1 },
+ { "DBGICMDREAD", 19, 1 },
+ { "DBGICMDLEARN", 18, 1 },
+ { "DBGICMDWRITE", 17, 1 },
+ { "DBGICMDIPv6", 16, 1 },
+ { "DBGICMDBUSY", 3, 1 },
+ { "DBGICMDSTRT", 2, 1 },
+ { "DBGICMDMODE", 0, 2 },
+ { "LE_DB_DBGI_REQ_CMD", 0x19cf4, 0 },
+ { "DBGICMD", 20, 4 },
+ { "DBGITID", 0, 20 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d00, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d04, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d08, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d0c, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d10, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d14, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d18, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d1c, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d20, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d24, 0 },
+ { "LE_DB_DBGI_REQ_DATA", 0x19d28, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d50, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d54, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d58, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d5c, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d60, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d64, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d68, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d6c, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d70, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d74, 0 },
+ { "LE_DB_DBGI_REQ_MASK", 0x19d78, 0 },
+ { "LE_DB_DBGI_RSP_STATUS", 0x19d94, 0 },
+ { "DBGIRspTid", 12, 20 },
+ { "DBGIRspMsg", 8, 4 },
+ { "DBGIRspLearn", 2, 1 },
+ { "DBGIRspHit", 1, 1 },
+ { "DBGIRspValid", 0, 1 },
+ { "LE_DBG_SEL", 0x19d98, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19da0, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19da4, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19da8, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dac, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19db0, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19db4, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19db8, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dbc, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dc0, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dc4, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dc8, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dcc, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dd0, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dd4, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19dd8, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19ddc, 0 },
+ { "LE_DB_DBGI_RSP_DATA", 0x19de0, 0 },
+ { "LE_DB_TCAM_TID_BASE", 0x19df0, 0 },
+ { "LE_DB_CLCAM_TID_BASE", 0x19df4, 0 },
+ { "LE_DB_HASH_TID_BASE", 0x19df8, 0 },
+ { "LE_DB_SSRAM_TID_BASE", 0x19dfc, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV4", 0x19e00, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV4", 0x19e04, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV4", 0x19e08, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV4", 0x19e0c, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV4", 0x19e10, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e50, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e54, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e58, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e5c, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e60, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e64, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e68, 0 },
+ { "LE_DB_ACTIVE_MASK_IPV6", 0x19e6c, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea0, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea4, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV4", 0x19ea8, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV4", 0x19eac, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb0, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb4, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV4", 0x19eb8, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV4", 0x19ebc, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV6", 0x19ec4, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV6", 0x19ec8, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV6", 0x19ecc, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed0, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed4, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV6", 0x19ed8, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV6", 0x19edc, 0 },
+ { "LE_DB_HASH_MASK_GEN_IPV6", 0x19ee0, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19ee4, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19ee8, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV4", 0x19eec, 0 },
+ { "LE_DB_PSV_FILTER_MASK_FLT_IPV4", 0x19ef0, 0 },
+ { "LE_DB_PSV_FILTER_MASK_FLT_IPV4", 0x19ef4, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f04, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f08, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f0c, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f10, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f14, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f18, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f1c, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f20, 0 },
+ { "LE_DB_PSV_FILTER_MASK_TUP_IPV6", 0x19f24, 0 },
+ { "LE_DB_PSV_FILTER_MASK_FLT_IPV6", 0x19f28, 0 },
+ { "LE_DB_PSV_FILTER_MASK_FLT_IPV6", 0x19f2c, 0 },
+ { "LE_DB_SRVR_SRAM_CONFIG", 0x19f34, 0 },
+ { "PRI_HFILT", 4, 1 },
+ { "PRI_SRVR", 3, 1 },
+ { "PRI_FILT", 2, 1 },
+ { "SRVRINITBUSY", 1, 1 },
+ { "SRVRINIT", 0, 1 },
+ { "LE_DB_SRVR_VF_SRCH_TABLE_CTRL", 0x19f38, 0 },
+ { "VFLUTBUSY", 10, 1 },
+ { "VFLUTSTART", 9, 1 },
+ { "RDWR", 8, 1 },
+ { "VFINDEX", 0, 8 },
+ { "LE_DB_SRVR_VF_SRCH_TABLE_DATA", 0x19f3c, 0 },
+ { "SRCHHADDR", 12, 12 },
+ { "SRCHLADDR", 0, 12 },
+ { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f40, 0 },
+ { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f44, 0 },
+ { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f48, 0 },
+ { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f4c, 0 },
+ { "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f50, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f90, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f94, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f98, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f9c, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa0, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa4, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa8, 0 },
+ { "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fac, 0 },
+ { "LE_DEBUG_LA_CONFIG", 0x19fd0, 0 },
+ { "LE_REQ_DEBUG_LA_DATA", 0x19fd4, 0 },
+ { "LE_REQ_DEBUG_LA_WRPTR", 0x19fd8, 0 },
+ { "LE_RSP_DEBUG_LA_DATA", 0x19fdc, 0 },
+ { "LE_RSP_DEBUG_LA_WRPTR", 0x19fe0, 0 },
+ { "LE_DEBUG_LA_SEL_DATA", 0x19fe4, 0 },
+ { NULL }
+};
+
+struct reg_info t6_ncsi_regs[] = {
+ { "NCSI_PORT_CFGREG", 0x1a000, 0 },
+ { "WireEn", 28, 4 },
+ { "strp_crc", 24, 4 },
+ { "rx_halt", 22, 1 },
+ { "flush_rx_fifo", 21, 1 },
+ { "hw_arb_en", 20, 1 },
+ { "soft_pkg_sel", 19, 1 },
+ { "err_discard_en", 18, 1 },
+ { "max_pkt_size", 4, 14 },
+ { "rx_byte_swap", 3, 1 },
+ { "tx_byte_swap", 2, 1 },
+ { "NCSI_RST_CTRL", 0x1a004, 0 },
+ { "mac_ref_rst", 2, 1 },
+ { "mac_rx_rst", 1, 1 },
+ { "mac_tx_rst", 0, 1 },
+ { "NCSI_CH0_SADDR_LOW", 0x1a010, 0 },
+ { "NCSI_CH0_SADDR_HIGH", 0x1a014, 0 },
+ { "CHO_SADDR_EN", 31, 1 },
+ { "CH0_SADDR_HIGH", 0, 16 },
+ { "NCSI_CH1_SADDR_LOW", 0x1a018, 0 },
+ { "NCSI_CH1_SADDR_HIGH", 0x1a01c, 0 },
+ { "CH1_SADDR_EN", 31, 1 },
+ { "CH1_SADDR_HIGH", 0, 16 },
+ { "NCSI_CH2_SADDR_LOW", 0x1a020, 0 },
+ { "NCSI_CH2_SADDR_HIGH", 0x1a024, 0 },
+ { "CH2_SADDR_EN", 31, 1 },
+ { "CH2_SADDR_HIGH", 0, 16 },
+ { "NCSI_CH3_SADDR_LOW", 0x1a028, 0 },
+ { "NCSI_CH3_SADDR_HIGH", 0x1a02c, 0 },
+ { "CH3_SADDR_EN", 31, 1 },
+ { "CH3_SADDR_HIGH", 0, 16 },
+ { "NCSI_WORK_REQHDR_0", 0x1a030, 0 },
+ { "NCSI_WORK_REQHDR_1", 0x1a034, 0 },
+ { "NCSI_WORK_REQHDR_2", 0x1a038, 0 },
+ { "NCSI_WORK_REQHDR_3", 0x1a03c, 0 },
+ { "NCSI_MPS_HDR_LO", 0x1a040, 0 },
+ { "NCSI_MPS_HDR_HI", 0x1a044, 0 },
+ { "NCSI_CTL", 0x1a048, 0 },
+ { "STRIP_OVLAN", 3, 1 },
+ { "bmc_drop_non_bc", 2, 1 },
+ { "bmc_rx_fwd_all", 1, 1 },
+ { "FWD_BMC", 0, 1 },
+ { "NCSI_NCSI_ETYPE", 0x1a04c, 0 },
+ { "NCSI_RX_FIFO_CNT", 0x1a050, 0 },
+ { "NCSI_RX_ERR_CNT", 0x1a054, 0 },
+ { "NCSI_RX_OF_CNT", 0x1a058, 0 },
+ { "NCSI_RX_MS_CNT", 0x1a05c, 0 },
+ { "NCSI_RX_IE_CNT", 0x1a060, 0 },
+ { "NCSI_MPS_DEMUX_CNT", 0x1a064, 0 },
+ { "MPS2CIM_CNT", 16, 9 },
+ { "MPS2BMC_CNT", 0, 9 },
+ { "NCSI_CIM_DEMUX_CNT", 0x1a068, 0 },
+ { "CIM2MPS_CNT", 16, 9 },
+ { "CIM2BMC_CNT", 0, 9 },
+ { "NCSI_TX_FIFO_CNT", 0x1a06c, 0 },
+ { "NCSI_SE_CNT_CTL", 0x1a0b0, 0 },
+ { "NCSI_SE_CNT_MPS", 0x1a0b4, 0 },
+ { "NCSI_SE_CNT_CIM", 0x1a0b8, 0 },
+ { "NCSI_BUS_DEBUG", 0x1a0bc, 0 },
+ { "NCSI_LA_RDPTR", 0x1a0c0, 0 },
+ { "NCSI_LA_RDDATA", 0x1a0c4, 0 },
+ { "NCSI_LA_WRPTR", 0x1a0c8, 0 },
+ { "NCSI_LA_RESERVED", 0x1a0cc, 0 },
+ { "NCSI_LA_CTL", 0x1a0d0, 0 },
+ { "NCSI_INT_ENABLE", 0x1a0d4, 0 },
+ { "CIM_DM_prty_err", 8, 1 },
+ { "MPS_DM_prty_err", 7, 1 },
+ { "token", 6, 1 },
+ { "arb_done", 5, 1 },
+ { "arb_started", 4, 1 },
+ { "WOL", 3, 1 },
+ { "MACInt", 2, 1 },
+ { "TXFIFO_prty_err", 1, 1 },
+ { "RXFIFO_prty_err", 0, 1 },
+ { "NCSI_INT_CAUSE", 0x1a0d8, 0 },
+ { "CIM_DM_prty_err", 8, 1 },
+ { "MPS_DM_prty_err", 7, 1 },
+ { "token", 6, 1 },
+ { "arb_done", 5, 1 },
+ { "arb_started", 4, 1 },
+ { "WOL", 3, 1 },
+ { "MACInt", 2, 1 },
+ { "TXFIFO_prty_err", 1, 1 },
+ { "RXFIFO_prty_err", 0, 1 },
+ { "NCSI_STATUS", 0x1a0dc, 0 },
+ { "Master", 1, 1 },
+ { "arb_status", 0, 1 },
+ { "NCSI_PAUSE_CTRL", 0x1a0e0, 0 },
+ { "NCSI_PAUSE_TIMEOUT", 0x1a0e4, 0 },
+ { "NCSI_PAUSE_WM", 0x1a0ec, 0 },
+ { "PauseHWM", 16, 11 },
+ { "PauseLWM", 0, 11 },
+ { "NCSI_DEBUG", 0x1a0f0, 0 },
+ { "TxFIFO_empty", 4, 1 },
+ { "TxFIFO_full", 3, 1 },
+ { "PKG_ID", 0, 3 },
+ { "NCSI_PERR_INJECT", 0x1a0f4, 0 },
+ { "MemSel", 1, 1 },
+ { "InjectDataErr", 0, 1 },
+ { "NCSI_PERR_ENABLE", 0x1a0f8, 0 },
+ { "CIM_DM_prty_err", 8, 1 },
+ { "MPS_DM_prty_err", 7, 1 },
+ { "TXFIFO_prty_err", 1, 1 },
+ { "RXFIFO_prty_err", 0, 1 },
+ { "NCSI_MACB_NETWORK_CTRL", 0x1a100, 0 },
+ { "TxSndZeroPause", 12, 1 },
+ { "TxSndPause", 11, 1 },
+ { "TxStop", 10, 1 },
+ { "TxStart", 9, 1 },
+ { "BackPress", 8, 1 },
+ { "StatWrEn", 7, 1 },
+ { "IncrStat", 6, 1 },
+ { "ClearStat", 5, 1 },
+ { "EnMgmtPort", 4, 1 },
+ { "TxEn", 3, 1 },
+ { "RxEn", 2, 1 },
+ { "LoopLocal", 1, 1 },
+ { "LoopPHY", 0, 1 },
+ { "NCSI_MACB_NETWORK_CFG", 0x1a104, 0 },
+ { "PClkDiv128", 22, 1 },
+ { "CopyPause", 21, 1 },
+ { "NonStdPreOK", 20, 1 },
+ { "NoFCS", 19, 1 },
+ { "RxEnHalfDup", 18, 1 },
+ { "NoCopyFCS", 17, 1 },
+ { "LenChkEn", 16, 1 },
+ { "RxBufOffset", 14, 2 },
+ { "PauseEn", 13, 1 },
+ { "RetryTest", 12, 1 },
+ { "PClkDiv", 10, 2 },
+ { "ExtClass", 9, 1 },
+ { "En1536Frame", 8, 1 },
+ { "UCastHashEn", 7, 1 },
+ { "MCastHashEn", 6, 1 },
+ { "RxBCastDis", 5, 1 },
+ { "CopyAllFrames", 4, 1 },
+ { "JumboEn", 3, 1 },
+ { "SerEn", 2, 1 },
+ { "FullDuplex", 1, 1 },
+ { "Speed", 0, 1 },
+ { "NCSI_MACB_NETWORK_STATUS", 0x1a108, 0 },
+ { "PHYMgmtStatus", 2, 1 },
+ { "MDIStatus", 1, 1 },
+ { "LinkStatus", 0, 1 },
+ { "NCSI_MACB_TX_STATUS", 0x1a114, 0 },
+ { "UnderrunErr", 6, 1 },
+ { "TxComplete", 5, 1 },
+ { "BufferExhausted", 4, 1 },
+ { "TxProgress", 3, 1 },
+ { "RetryLimit", 2, 1 },
+ { "ColEvent", 1, 1 },
+ { "UsedBitRead", 0, 1 },
+ { "NCSI_MACB_RX_BUF_QPTR", 0x1a118, 0 },
+ { "RxBufQPtr", 2, 30 },
+ { "NCSI_MACB_TX_BUF_QPTR", 0x1a11c, 0 },
+ { "TxBufQPtr", 2, 30 },
+ { "NCSI_MACB_RX_STATUS", 0x1a120, 0 },
+ { "RxOverrunErr", 2, 1 },
+ { "FrameRcvd", 1, 1 },
+ { "NoRxBuf", 0, 1 },
+ { "NCSI_MACB_INT_STATUS", 0x1a124, 0 },
+ { "PauseTimeZero", 13, 1 },
+ { "PauseRcvd", 12, 1 },
+ { "HRespNotOK", 11, 1 },
+ { "RxOverrun", 10, 1 },
+ { "LinkChange", 9, 1 },
+ { "TxComplete", 7, 1 },
+ { "TxBufErr", 6, 1 },
+ { "RetryLimitErr", 5, 1 },
+ { "TxBufUnderrun", 4, 1 },
+ { "TxUsedBitRead", 3, 1 },
+ { "RxUsedBitRead", 2, 1 },
+ { "RxComplete", 1, 1 },
+ { "MgmtFrameSent", 0, 1 },
+ { "NCSI_MACB_INT_EN", 0x1a128, 0 },
+ { "PauseTimeZero", 13, 1 },
+ { "PauseRcvd", 12, 1 },
+ { "HRespNotOK", 11, 1 },
+ { "RxOverrun", 10, 1 },
+ { "LinkChange", 9, 1 },
+ { "TxComplete", 7, 1 },
+ { "TxBufErr", 6, 1 },
+ { "RetryLimitErr", 5, 1 },
+ { "TxBufUnderrun", 4, 1 },
+ { "TxUsedBitRead", 3, 1 },
+ { "RxUsedBitRead", 2, 1 },
+ { "RxComplete", 1, 1 },
+ { "MgmtFrameSent", 0, 1 },
+ { "NCSI_MACB_INT_DIS", 0x1a12c, 0 },
+ { "PauseTimeZero", 13, 1 },
+ { "PauseRcvd", 12, 1 },
+ { "HRespNotOK", 11, 1 },
+ { "RxOverrun", 10, 1 },
+ { "LinkChange", 9, 1 },
+ { "TxComplete", 7, 1 },
+ { "TxBufErr", 6, 1 },
+ { "RetryLimitErr", 5, 1 },
+ { "TxBufUnderrun", 4, 1 },
+ { "TxUsedBitRead", 3, 1 },
+ { "RxUsedBitRead", 2, 1 },
+ { "RxComplete", 1, 1 },
+ { "MgmtFrameSent", 0, 1 },
+ { "NCSI_MACB_INT_MASK", 0x1a130, 0 },
+ { "PauseTimeZero", 13, 1 },
+ { "PauseRcvd", 12, 1 },
+ { "HRespNotOK", 11, 1 },
+ { "RxOverrun", 10, 1 },
+ { "LinkChange", 9, 1 },
+ { "TxComplete", 7, 1 },
+ { "TxBufErr", 6, 1 },
+ { "RetryLimitErr", 5, 1 },
+ { "TxBufUnderrun", 4, 1 },
+ { "TxUsedBitRead", 3, 1 },
+ { "RxUsedBitRead", 2, 1 },
+ { "RxComplete", 1, 1 },
+ { "MgmtFrameSent", 0, 1 },
+ { "NCSI_MACB_PAUSE_TIME", 0x1a138, 0 },
+ { "NCSI_MACB_PAUSE_FRAMES_RCVD", 0x1a13c, 0 },
+ { "NCSI_MACB_TX_FRAMES_OK", 0x1a140, 0 },
+ { "NCSI_MACB_SINGLE_COL_FRAMES", 0x1a144, 0 },
+ { "NCSI_MACB_MUL_COL_FRAMES", 0x1a148, 0 },
+ { "NCSI_MACB_RX_FRAMES_OK", 0x1a14c, 0 },
+ { "NCSI_MACB_FCS_ERR", 0x1a150, 0 },
+ { "NCSI_MACB_ALIGN_ERR", 0x1a154, 0 },
+ { "NCSI_MACB_DEF_TX_FRAMES", 0x1a158, 0 },
+ { "NCSI_MACB_LATE_COL", 0x1a15c, 0 },
+ { "NCSI_MACB_EXCESSIVE_COL", 0x1a160, 0 },
+ { "NCSI_MACB_TX_UNDERRUN_ERR", 0x1a164, 0 },
+ { "NCSI_MACB_CARRIER_SENSE_ERR", 0x1a168, 0 },
+ { "NCSI_MACB_RX_RESOURCE_ERR", 0x1a16c, 0 },
+ { "NCSI_MACB_RX_OVERRUN_ERR", 0x1a170, 0 },
+ { "NCSI_MACB_RX_SYMBOL_ERR", 0x1a174, 0 },
+ { "NCSI_MACB_RX_OVERSIZE_FRAME", 0x1a178, 0 },
+ { "NCSI_MACB_RX_JABBER_ERR", 0x1a17c, 0 },
+ { "NCSI_MACB_RX_UNDERSIZE_FRAME", 0x1a180, 0 },
+ { "NCSI_MACB_SQE_TEST_ERR", 0x1a184, 0 },
+ { "NCSI_MACB_LENGTH_ERR", 0x1a188, 0 },
+ { "NCSI_MACB_TX_PAUSE_FRAMES", 0x1a18c, 0 },
+ { "NCSI_MACB_HASH_LOW", 0x1a190, 0 },
+ { "NCSI_MACB_HASH_HIGH", 0x1a194, 0 },
+ { "NCSI_MACB_SPECIFIC_1_LOW", 0x1a198, 0 },
+ { "NCSI_MACB_SPECIFIC_1_HIGH", 0x1a19c, 0 },
+ { "NCSI_MACB_SPECIFIC_2_LOW", 0x1a1a0, 0 },
+ { "NCSI_MACB_SPECIFIC_2_HIGH", 0x1a1a4, 0 },
+ { "NCSI_MACB_SPECIFIC_3_LOW", 0x1a1a8, 0 },
+ { "NCSI_MACB_SPECIFIC_3_HIGH", 0x1a1ac, 0 },
+ { "NCSI_MACB_SPECIFIC_4_LOW", 0x1a1b0, 0 },
+ { "NCSI_MACB_SPECIFIC_4_HIGH", 0x1a1b4, 0 },
+ { "NCSI_MACB_TYPE_ID", 0x1a1b8, 0 },
+ { "NCSI_MACB_TX_PAUSE_QUANTUM", 0x1a1bc, 0 },
+ { "NCSI_MACB_USER_IO", 0x1a1c0, 0 },
+ { "UserProgInput", 16, 16 },
+ { "UserProgOutput", 0, 16 },
+ { "NCSI_MACB_WOL_CFG", 0x1a1c4, 0 },
+ { "MCHashEn", 19, 1 },
+ { "Specific1En", 18, 1 },
+ { "ARPEn", 17, 1 },
+ { "MagicPktEn", 16, 1 },
+ { "ARPIPAddr", 0, 16 },
+ { "NCSI_MACB_REV_STATUS", 0x1a1fc, 0 },
+ { "PartRef", 16, 16 },
+ { "DesRev", 0, 16 },
+ { NULL }
+};
+
+struct reg_info t6_mac_regs[] = {
+ { "MAC_PORT_CFG", 0x30800, 0 },
+ { "MAC_Clk_Sel", 29, 3 },
+ { "Ena_err_rsp", 28, 1 },
+ { "SinkTx", 27, 1 },
+ { "SinkTxOnLinkDown", 26, 1 },
+ { "debug_clr", 25, 1 },
+ { "LoopNoFwd", 24, 1 },
+ { "pll_sel", 23, 1 },
+ { "port_map", 20, 3 },
+ { "Smux_Rx_Loop", 19, 1 },
+ { "Rx_Lane_Swap", 18, 1 },
+ { "Tx_Lane_Swap", 17, 1 },
+ { "Aec_pat_data", 15, 1 },
+ { "Signal_Det", 14, 1 },
+ { "macclk_sel", 13, 1 },
+ { "xgmii_sel", 12, 1 },
+ { "debug_port_sel", 10, 2 },
+ { "SmuxTxSel", 9, 1 },
+ { "SmuxRxSel", 8, 1 },
+ { "Enable_25G", 7, 1 },
+ { "Enable_50G", 6, 1 },
+ { "PortSpeed", 4, 2 },
+ { "Rx_Byte_Swap", 3, 1 },
+ { "Tx_Byte_Swap", 2, 1 },
+ { "debug_tx_rx_sel", 1, 1 },
+ { "Port_Sel", 0, 1 },
+ { "MAC_PORT_RESET_CTRL", 0x30804, 0 },
+ { "TWGDSK_HSSC16B", 31, 1 },
+ { "EEE_RESET", 30, 1 },
+ { "PTP_TIMER", 29, 1 },
+ { "MtipRefReset", 28, 1 },
+ { "MAC100G40G_RESET", 27, 1 },
+ { "MAC10G1G_RESET", 26, 1 },
+ { "MtipRegReset", 25, 1 },
+ { "PCS1G_RESET", 24, 1 },
+ { "AEC3Reset", 23, 1 },
+ { "AEC2Reset", 22, 1 },
+ { "AEC1Reset", 21, 1 },
+ { "AEC0Reset", 20, 1 },
+ { "AET3Reset", 19, 1 },
+ { "AET2Reset", 18, 1 },
+ { "AET1Reset", 17, 1 },
+ { "AET0Reset", 16, 1 },
+ { "PCS10G_RESET", 15, 1 },
+ { "PCS40G_RESET", 14, 1 },
+ { "PCS100G_RESET", 13, 1 },
+ { "TXIF_Reset", 12, 1 },
+ { "RXIF_Reset", 11, 1 },
+ { "AuxExt_Reset", 10, 1 },
+ { "MtipSd3TxRst", 9, 1 },
+ { "MtipSd2TxRst", 8, 1 },
+ { "MtipSd1TxRst", 7, 1 },
+ { "MtipSd0TxRst", 6, 1 },
+ { "MtipSd3RxRst", 5, 1 },
+ { "MtipSd2RxRst", 4, 1 },
+ { "MtipSd1RxRst", 3, 1 },
+ { "WOL_Reset", 2, 1 },
+ { "MtipSd0RxRst", 1, 1 },
+ { "HSS_Reset", 0, 1 },
+ { "MAC_PORT_LED_CFG", 0x30808, 0 },
+ { "Led1_Cfg1", 14, 2 },
+ { "Led0_Cfg1", 12, 2 },
+ { "Led1_tlo", 11, 1 },
+ { "Led1_thi", 10, 1 },
+ { "Led0_tlo", 9, 1 },
+ { "Led0_thi", 8, 1 },
+ { "Led1_Cfg", 5, 3 },
+ { "Led1_Polarity_Inv", 4, 1 },
+ { "Led0_Cfg", 1, 3 },
+ { "Led0_Polarity_Inv", 0, 1 },
+ { "MAC_PORT_LED_COUNTHI", 0x3080c, 0 },
+ { "MAC_PORT_LED_COUNTLO", 0x30810, 0 },
+ { "MAC_PORT_CFG3", 0x30814, 0 },
+ { "REF_Clk_Sel", 30, 2 },
+ { "sgmii_sd_sig_det", 29, 1 },
+ { "sgmii_sgpcs_ena", 28, 1 },
+ { "FPGA_PTP_PORT", 26, 2 },
+ { "FCSDisCtrl", 25, 1 },
+ { "SigDetCtrl", 24, 1 },
+ { "tx_lane", 23, 1 },
+ { "rx_lane", 22, 1 },
+ { "se_clr", 21, 1 },
+ { "an_ena", 17, 4 },
+ { "sd_rx_clk_ena", 13, 4 },
+ { "sd_tx_clk_ena", 9, 4 },
+ { "SGMIISEL", 8, 1 },
+ { "HSSPLLSEL", 4, 4 },
+ { "HSSC16C20SEL", 0, 4 },
+ { "MAC_PORT_CFG2", 0x30818, 0 },
+ { "Rx_Polarity_Inv", 28, 4 },
+ { "Tx_Polarity_Inv", 24, 4 },
+ { "InstanceNum", 22, 2 },
+ { "StopOnPerr", 21, 1 },
+ { "an_data_ctl", 19, 1 },
+ { "PatEn", 18, 1 },
+ { "MagicEn", 17, 1 },
+ { "T5_AEC_PMA_TX_READY", 4, 4 },
+ { "T5_AEC_PMA_RX_READY", 0, 4 },
+ { "MAC_PORT_PKT_COUNT", 0x3081c, 0 },
+ { "tx_sop_count", 24, 8 },
+ { "tx_eop_count", 16, 8 },
+ { "rx_sop_count", 8, 8 },
+ { "rx_eop_count", 0, 8 },
+ { "MAC_PORT_CFG4", 0x30820, 0 },
+ { "AEC3_RX_WIDTH", 14, 2 },
+ { "AEC2_RX_WIDTH", 12, 2 },
+ { "AEC1_RX_WIDTH", 10, 2 },
+ { "AEC0_RX_WIDTH", 8, 2 },
+ { "AEC3_TX_WIDTH", 6, 2 },
+ { "AEC2_TX_WIDTH", 4, 2 },
+ { "AEC1_TX_WIDTH", 2, 2 },
+ { "AEC0_TX_WIDTH", 0, 2 },
+ { "MAC_PORT_MAGIC_MACID_LO", 0x30824, 0 },
+ { "MAC_PORT_MAGIC_MACID_HI", 0x30828, 0 },
+ { "MAC_PORT_MTIP_RESET_CTRL", 0x3082c, 0 },
+ { "an_reset_sd_tx_clk", 31, 1 },
+ { "an_reset_sd_rx_clk", 30, 1 },
+ { "sgmii_reset_tx_clk", 29, 1 },
+ { "sgmii_reset_rx_clk", 28, 1 },
+ { "sgmii_reset_ref_clk", 27, 1 },
+ { "pcs10g_reset_xfi_rxclk", 26, 1 },
+ { "pcs10g_reset_xfi_txclk", 25, 1 },
+ { "pcs10g_reset_sd_tx_clk", 24, 1 },
+ { "pcs10g_reset_sd_rx_clk", 23, 1 },
+ { "pcs40g_reset_rxclk", 22, 1 },
+ { "pcs40g_reset_sd_tx_clk", 21, 1 },
+ { "pcs40g_reset_sd0_rx_clk", 20, 1 },
+ { "pcs40g_reset_sd1_rx_clk", 19, 1 },
+ { "pcs40g_reset_sd2_rx_clk", 18, 1 },
+ { "pcs40g_reset_sd3_rx_clk", 17, 1 },
+ { "pcs100g_reset_cgmii_rxclk", 16, 1 },
+ { "pcs100g_reset_cgmii_txclk", 15, 1 },
+ { "pcs100g_reset_tx_clk", 14, 1 },
+ { "pcs100g_reset_sd0_rx_clk", 13, 1 },
+ { "pcs100g_reset_sd1_rx_clk", 12, 1 },
+ { "pcs100g_reset_sd2_rx_clk", 11, 1 },
+ { "pcs100g_reset_sd3_rx_clk", 10, 1 },
+ { "mac40g100g_reset_txclk", 9, 1 },
+ { "mac40g100g_reset_rxclk", 8, 1 },
+ { "mac40g100g_reset_ff_tx_clk", 7, 1 },
+ { "mac40g100g_reset_ff_rx_clk", 6, 1 },
+ { "mac40g100g_reset_ts_clk", 5, 1 },
+ { "mac1g10g_reset_rxclk", 4, 1 },
+ { "mac1g10g_reset_txclk", 3, 1 },
+ { "mac1g10g_reset_ff_rx_clk", 2, 1 },
+ { "mac1g10g_reset_ff_tx_clk", 1, 1 },
+ { "xgmii_clk_reset", 0, 1 },
+ { "MAC_PORT_MTIP_GATE_CTRL", 0x30830, 0 },
+ { "an_gate_sd_tx_clk", 31, 1 },
+ { "an_gate_sd_rx_clk", 30, 1 },
+ { "sgmii_gate_tx_clk", 29, 1 },
+ { "sgmii_gate_rx_clk", 28, 1 },
+ { "sgmii_gate_ref_clk", 27, 1 },
+ { "pcs10g_gate_xfi_rxclk", 26, 1 },
+ { "pcs10g_gate_xfi_txclk", 25, 1 },
+ { "pcs10g_gate_sd_tx_clk", 24, 1 },
+ { "pcs10g_gate_sd_rx_clk", 23, 1 },
+ { "pcs40g_gate_rxclk", 22, 1 },
+ { "pcs40g_gate_sd_tx_clk", 21, 1 },
+ { "pcs40g_gate_sd_rx_clk", 20, 1 },
+ { "pcs100g_gate_cgmii_rxclk", 19, 1 },
+ { "pcs100g_gate_cgmii_txclk", 18, 1 },
+ { "pcs100g_gate_tx_clk", 17, 1 },
+ { "pcs100g_gate_sd_rx_clk", 16, 1 },
+ { "mac40g100g_gate_txclk", 15, 1 },
+ { "mac40g100g_gate_rxclk", 14, 1 },
+ { "mac40g100g_gate_ff_tx_clk", 13, 1 },
+ { "mac40g100g_gate_ff_rx_clk", 12, 1 },
+ { "mac40g100g_ts_clk", 11, 1 },
+ { "mac1g10g_gate_rxclk", 10, 1 },
+ { "mac1g10g_gate_txclk", 9, 1 },
+ { "mac1g10g_gate_ff_rx_clk", 8, 1 },
+ { "mac1g10g_gate_ff_tx_clk", 7, 1 },
+ { "aec_rx", 6, 1 },
+ { "aec_tx", 5, 1 },
+ { "pcs100g_clk_enable", 4, 1 },
+ { "pcs40g_clk_enable", 3, 1 },
+ { "pcs10g_clk_enable", 2, 1 },
+ { "pcs1g_clk_enable", 1, 1 },
+ { "an_clk_enable", 0, 1 },
+ { "MAC_PORT_LINK_STATUS", 0x30834, 0 },
+ { "hi_ber", 7, 1 },
+ { "an_done", 6, 1 },
+ { "align_done", 5, 1 },
+ { "block_lock", 4, 1 },
+ { "remflt", 3, 1 },
+ { "locflt", 2, 1 },
+ { "linkup", 1, 1 },
+ { "linkdn", 0, 1 },
+ { "MAC_PORT_AEC_ADD_CTL_STAT_0", 0x30838, 0 },
+ { "AEC_SYS_LANE_TYPE_3", 11, 1 },
+ { "AEC_SYS_LANE_TYPE_2", 10, 1 },
+ { "AEC_SYS_LANE_TYPE_1", 9, 1 },
+ { "AEC_SYS_LANE_TYPE_0", 8, 1 },
+ { "AEC_SYS_LANE_SELECT_3", 6, 2 },
+ { "AEC_SYS_LANE_SELECT_2", 4, 2 },
+ { "AEC_SYS_LANE_SELECT_1", 2, 2 },
+ { "AEC_SYS_LANE_SELECT_O", 0, 2 },
+ { "MAC_PORT_AEC_ADD_CTL_STAT_1", 0x3083c, 0 },
+ { "AEC_RX_UNKNOWN_LANE_3", 11, 1 },
+ { "AEC_RX_UNKNOWN_LANE_2", 10, 1 },
+ { "AEC_RX_UNKNOWN_LANE_1", 9, 1 },
+ { "AEC_RX_UNKNOWN_LANE_0", 8, 1 },
+ { "AEC_RX_LANE_ID_3", 6, 2 },
+ { "AEC_RX_LANE_ID_2", 4, 2 },
+ { "AEC_RX_LANE_ID_1", 2, 2 },
+ { "AEC_RX_LANE_ID_O", 0, 2 },
+ { "MAC_PORT_AEC_XGMII_TIMER_LO_40G", 0x30840, 0 },
+ { "MAC_PORT_AEC_XGMII_TIMER_HI_40G", 0x30844, 0 },
+ { "MAC_PORT_AEC_XGMII_TIMER_LO_100G", 0x30848, 0 },
+ { "MAC_PORT_AEC_XGMII_TIMER_HI_100G", 0x3084c, 0 },
+ { "MAC_PORT_AEC_DEBUG_LO_0", 0x30850, 0 },
+ { "CTL_FSM_CUR_STATE", 28, 3 },
+ { "CIN_FSM_CUR_STATE", 26, 2 },
+ { "CRI_FSM_CUR_STATE", 23, 3 },
+ { "CU_C3_ACK_VALUE", 21, 2 },
+ { "CU_C2_ACK_VALUE", 19, 2 },
+ { "CU_C1_ACK_VALUE", 17, 2 },
+ { "CU_C0_ACK_VALUE", 15, 2 },
+ { "CX_INIT", 13, 1 },
+ { "CX_PRESET", 12, 1 },
+ { "CUF_C3_UPDATE", 9, 2 },
+ { "CUF_C2_UPDATE", 7, 2 },
+ { "CUF_C1_UPDATE", 5, 2 },
+ { "CUF_C0_UPDATE", 3, 2 },
+ { "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
+ { "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
+ { "REG_MAN_DEC_REQ", 0, 1 },
+ { "MAC_PORT_AEC_DEBUG_HI_0", 0x30854, 0 },
+ { "FC_LSNA_", 12, 1 },
+ { "CUF_C0_FSM_DEBUG", 9, 3 },
+ { "CUF_C1_FSM_DEBUG", 6, 3 },
+ { "CUF_C2_FSM_DEBUG", 3, 3 },
+ { "LCK_FSM_CUR_STATE", 0, 3 },
+ { "MAC_PORT_AEC_DEBUG_LO_1", 0x30858, 0 },
+ { "CTL_FSM_CUR_STATE", 28, 3 },
+ { "CIN_FSM_CUR_STATE", 26, 2 },
+ { "CRI_FSM_CUR_STATE", 23, 3 },
+ { "CU_C3_ACK_VALUE", 21, 2 },
+ { "CU_C2_ACK_VALUE", 19, 2 },
+ { "CU_C1_ACK_VALUE", 17, 2 },
+ { "CU_C0_ACK_VALUE", 15, 2 },
+ { "CX_INIT", 13, 1 },
+ { "CX_PRESET", 12, 1 },
+ { "CUF_C3_UPDATE", 9, 2 },
+ { "CUF_C2_UPDATE", 7, 2 },
+ { "CUF_C1_UPDATE", 5, 2 },
+ { "CUF_C0_UPDATE", 3, 2 },
+ { "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
+ { "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
+ { "REG_MAN_DEC_REQ", 0, 1 },
+ { "MAC_PORT_AEC_DEBUG_HI_1", 0x3085c, 0 },
+ { "FC_LSNA_", 12, 1 },
+ { "CUF_C0_FSM_DEBUG", 9, 3 },
+ { "CUF_C1_FSM_DEBUG", 6, 3 },
+ { "CUF_C2_FSM_DEBUG", 3, 3 },
+ { "LCK_FSM_CUR_STATE", 0, 3 },
+ { "MAC_PORT_AEC_DEBUG_LO_2", 0x30860, 0 },
+ { "CTL_FSM_CUR_STATE", 28, 3 },
+ { "CIN_FSM_CUR_STATE", 26, 2 },
+ { "CRI_FSM_CUR_STATE", 23, 3 },
+ { "CU_C3_ACK_VALUE", 21, 2 },
+ { "CU_C2_ACK_VALUE", 19, 2 },
+ { "CU_C1_ACK_VALUE", 17, 2 },
+ { "CU_C0_ACK_VALUE", 15, 2 },
+ { "CX_INIT", 13, 1 },
+ { "CX_PRESET", 12, 1 },
+ { "CUF_C3_UPDATE", 9, 2 },
+ { "CUF_C2_UPDATE", 7, 2 },
+ { "CUF_C1_UPDATE", 5, 2 },
+ { "CUF_C0_UPDATE", 3, 2 },
+ { "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
+ { "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
+ { "REG_MAN_DEC_REQ", 0, 1 },
+ { "MAC_PORT_AEC_DEBUG_HI_2", 0x30864, 0 },
+ { "FC_LSNA_", 12, 1 },
+ { "CUF_C0_FSM_DEBUG", 9, 3 },
+ { "CUF_C1_FSM_DEBUG", 6, 3 },
+ { "CUF_C2_FSM_DEBUG", 3, 3 },
+ { "LCK_FSM_CUR_STATE", 0, 3 },
+ { "MAC_PORT_AEC_DEBUG_LO_3", 0x30868, 0 },
+ { "CTL_FSM_CUR_STATE", 28, 3 },
+ { "CIN_FSM_CUR_STATE", 26, 2 },
+ { "CRI_FSM_CUR_STATE", 23, 3 },
+ { "CU_C3_ACK_VALUE", 21, 2 },
+ { "CU_C2_ACK_VALUE", 19, 2 },
+ { "CU_C1_ACK_VALUE", 17, 2 },
+ { "CU_C0_ACK_VALUE", 15, 2 },
+ { "CX_INIT", 13, 1 },
+ { "CX_PRESET", 12, 1 },
+ { "CUF_C3_UPDATE", 9, 2 },
+ { "CUF_C2_UPDATE", 7, 2 },
+ { "CUF_C1_UPDATE", 5, 2 },
+ { "CUF_C0_UPDATE", 3, 2 },
+ { "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
+ { "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
+ { "REG_MAN_DEC_REQ", 0, 1 },
+ { "MAC_PORT_AEC_DEBUG_HI_3", 0x3086c, 0 },
+ { "FC_LSNA_", 12, 1 },
+ { "CUF_C0_FSM_DEBUG", 9, 3 },
+ { "CUF_C1_FSM_DEBUG", 6, 3 },
+ { "CUF_C2_FSM_DEBUG", 3, 3 },
+ { "LCK_FSM_CUR_STATE", 0, 3 },
+ { "MAC_PORT_MAC_DEBUG_RO", 0x30870, 0 },
+ { "mac40g100g_tx_underflow", 13, 1 },
+ { "mac1g10g_magic_ind", 12, 1 },
+ { "mac1g10g_ff_rx_empty", 11, 1 },
+ { "mac1g10g_ff_tx_ovr_err", 10, 1 },
+ { "mac1g10g_if_mode_ena", 8, 2 },
+ { "mac1g10g_mii_ena_10", 7, 1 },
+ { "mac1g10g_pause_on", 6, 1 },
+ { "mac1g10g_pfc_mode", 5, 1 },
+ { "mac1g10g_rx_sfd_o", 4, 1 },
+ { "mac1g10g_tx_empty", 3, 1 },
+ { "mac1g10g_tx_sfd_o", 2, 1 },
+ { "mac1g10g_tx_ts_frm_out", 1, 1 },
+ { "mac1g10g_tx_underflow", 0, 1 },
+ { "MAC_PORT_MAC_CTRL_RW", 0x30874, 0 },
+ { "mac40g100g_ff_tx_pfc_xoff", 17, 8 },
+ { "mac40g100g_tx_loc_fault", 16, 1 },
+ { "mac40g100g_tx_rem_fault", 15, 1 },
+ { "mac40g_loop_bck", 14, 1 },
+ { "mac1g10g_magic_ena", 13, 1 },
+ { "mac1g10g_if_mode_set", 11, 2 },
+ { "mac1g10g_tx_loc_fault", 10, 1 },
+ { "mac1g10g_tx_rem_fault", 9, 1 },
+ { "mac1g10g_xoff_gen", 1, 8 },
+ { "mac1g_loop_bck", 0, 1 },
+ { "MAC_PORT_PCS_DEBUG0_RO", 0x30878, 0 },
+ { "fpga_lock", 26, 4 },
+ { "an_done", 25, 1 },
+ { "an_int", 24, 1 },
+ { "an_pcs_rx_clk_ena", 23, 1 },
+ { "an_pcs_tx_clk_ena", 22, 1 },
+ { "an_select", 17, 5 },
+ { "an_prog", 16, 1 },
+ { "pcs40g_block_lock", 12, 4 },
+ { "pcs40g_ber_timer_done", 11, 1 },
+ { "pcs10g_fec_locked", 10, 1 },
+ { "pcs10g_block_lock", 9, 1 },
+ { "sgmii_gmii_col", 8, 1 },
+ { "sgmii_gmii_crs", 7, 1 },
+ { "sgmii_sd_loopback", 6, 1 },
+ { "sgmii_sg_an_done", 5, 1 },
+ { "sgmii_sg_hd", 4, 1 },
+ { "sgmii_sg_page_rx", 3, 1 },
+ { "sgmii_sg_rx_sync", 2, 1 },
+ { "sgmii_sg_speed", 0, 2 },
+ { "MAC_PORT_PCS_CTRL_RW", 0x3087c, 0 },
+ { "tx_li_fault", 31, 1 },
+ { "pad", 30, 1 },
+ { "blk_stb_val", 22, 8 },
+ { "debug_sel", 18, 4 },
+ { "sgmii_loop", 15, 3 },
+ { "an_dis_timer", 14, 1 },
+ { "pcs100g_ber_timer_short", 13, 1 },
+ { "pcs100g_tx_lane_thresh", 9, 4 },
+ { "pcs100g_vl_intvl", 8, 1 },
+ { "sgmii_tx_lane_ckmult", 4, 3 },
+ { "sgmii_tx_lane_thresh", 0, 4 },
+ { "MAC_PORT_PCS_DEBUG1_RO", 0x30880, 0 },
+ { "pcs100g_align_lock", 21, 1 },
+ { "pcs100g_ber_timer_done", 20, 1 },
+ { "pcs100g_block_lock", 0, 20 },
+ { "MAC_PORT_PERR_INT_EN_100G", 0x30884, 0 },
+ { "Perr_rx_fec100g_dly", 29, 1 },
+ { "Perr_rx_fec100g", 28, 1 },
+ { "Perr_rx3_fec100g_dk", 27, 1 },
+ { "Perr_rx2_fec100g_dk", 26, 1 },
+ { "Perr_rx1_fec100g_dk", 25, 1 },
+ { "Perr_rx0_fec100g_dk", 24, 1 },
+ { "Perr_tx3_pcs100g", 23, 1 },
+ { "Perr_tx2_pcs100g", 22, 1 },
+ { "Perr_tx1_pcs100g", 21, 1 },
+ { "Perr_tx0_pcs100g", 20, 1 },
+ { "Perr_rx19_pcs100g", 19, 1 },
+ { "Perr_rx18_pcs100g", 18, 1 },
+ { "Perr_rx17_pcs100g", 17, 1 },
+ { "Perr_rx16_pcs100g", 16, 1 },
+ { "Perr_rx15_pcs100g", 15, 1 },
+ { "Perr_rx14_pcs100g", 14, 1 },
+ { "Perr_rx13_pcs100g", 13, 1 },
+ { "Perr_rx12_pcs100g", 12, 1 },
+ { "Perr_rx11_pcs100g", 11, 1 },
+ { "Perr_rx10_pcs100g", 10, 1 },
+ { "Perr_rx9_pcs100g", 9, 1 },
+ { "Perr_rx8_pcs100g", 8, 1 },
+ { "Perr_rx7_pcs100g", 7, 1 },
+ { "Perr_rx6_pcs100g", 6, 1 },
+ { "Perr_rx5_pcs100g", 5, 1 },
+ { "Perr_rx4_pcs100g", 4, 1 },
+ { "Perr_rx3_pcs100g", 3, 1 },
+ { "Perr_rx2_pcs100g", 2, 1 },
+ { "Perr_rx1_pcs100g", 1, 1 },
+ { "Perr_rx0_pcs100g", 0, 1 },
+ { "MAC_PORT_PERR_INT_CAUSE_100G", 0x30888, 0 },
+ { "Perr_rx_fec100g_dly", 29, 1 },
+ { "Perr_rx_fec100g", 28, 1 },
+ { "Perr_rx3_fec100g_dk", 27, 1 },
+ { "Perr_rx2_fec100g_dk", 26, 1 },
+ { "Perr_rx1_fec100g_dk", 25, 1 },
+ { "Perr_rx0_fec100g_dk", 24, 1 },
+ { "Perr_tx3_pcs100g", 23, 1 },
+ { "Perr_tx2_pcs100g", 22, 1 },
+ { "Perr_tx1_pcs100g", 21, 1 },
+ { "Perr_tx0_pcs100g", 20, 1 },
+ { "Perr_rx19_pcs100g", 19, 1 },
+ { "Perr_rx18_pcs100g", 18, 1 },
+ { "Perr_rx17_pcs100g", 17, 1 },
+ { "Perr_rx16_pcs100g", 16, 1 },
+ { "Perr_rx15_pcs100g", 15, 1 },
+ { "Perr_rx14_pcs100g", 14, 1 },
+ { "Perr_rx13_pcs100g", 13, 1 },
+ { "Perr_rx12_pcs100g", 12, 1 },
+ { "Perr_rx11_pcs100g", 11, 1 },
+ { "Perr_rx10_pcs100g", 10, 1 },
+ { "Perr_rx9_pcs100g", 9, 1 },
+ { "Perr_rx8_pcs100g", 8, 1 },
+ { "Perr_rx7_pcs100g", 7, 1 },
+ { "Perr_rx6_pcs100g", 6, 1 },
+ { "Perr_rx5_pcs100g", 5, 1 },
+ { "Perr_rx4_pcs100g", 4, 1 },
+ { "Perr_rx3_pcs100g", 3, 1 },
+ { "Perr_rx2_pcs100g", 2, 1 },
+ { "Perr_rx1_pcs100g", 1, 1 },
+ { "Perr_rx0_pcs100g", 0, 1 },
+ { "MAC_PORT_PERR_ENABLE_100G", 0x3088c, 0 },
+ { "Perr_rx_fec100g_dly", 29, 1 },
+ { "Perr_rx_fec100g", 28, 1 },
+ { "Perr_rx3_fec100g_dk", 27, 1 },
+ { "Perr_rx2_fec100g_dk", 26, 1 },
+ { "Perr_rx1_fec100g_dk", 25, 1 },
+ { "Perr_rx0_fec100g_dk", 24, 1 },
+ { "Perr_tx3_pcs100g", 23, 1 },
+ { "Perr_tx2_pcs100g", 22, 1 },
+ { "Perr_tx1_pcs100g", 21, 1 },
+ { "Perr_tx0_pcs100g", 20, 1 },
+ { "Perr_rx19_pcs100g", 19, 1 },
+ { "Perr_rx18_pcs100g", 18, 1 },
+ { "Perr_rx17_pcs100g", 17, 1 },
+ { "Perr_rx16_pcs100g", 16, 1 },
+ { "Perr_rx15_pcs100g", 15, 1 },
+ { "Perr_rx14_pcs100g", 14, 1 },
+ { "Perr_rx13_pcs100g", 13, 1 },
+ { "Perr_rx12_pcs100g", 12, 1 },
+ { "Perr_rx11_pcs100g", 11, 1 },
+ { "Perr_rx10_pcs100g", 10, 1 },
+ { "Perr_rx9_pcs100g", 9, 1 },
+ { "Perr_rx8_pcs100g", 8, 1 },
+ { "Perr_rx7_pcs100g", 7, 1 },
+ { "Perr_rx6_pcs100g", 6, 1 },
+ { "Perr_rx5_pcs100g", 5, 1 },
+ { "Perr_rx4_pcs100g", 4, 1 },
+ { "Perr_rx3_pcs100g", 3, 1 },
+ { "Perr_rx2_pcs100g", 2, 1 },
+ { "Perr_rx1_pcs100g", 1, 1 },
+ { "Perr_rx0_pcs100g", 0, 1 },
+ { "MAC_PORT_MAC_STAT_DEBUG", 0x30890, 0 },
+ { "MAC_PORT_MAC_25G_50G_AM0", 0x30894, 0 },
+ { "MAC_PORT_MAC_25G_50G_AM1", 0x30898, 0 },
+ { "MAC_PORT_MAC_25G_50G_AM2", 0x3089c, 0 },
+ { "MAC_PORT_MAC_25G_50G_AM3", 0x308a0, 0 },
+ { "MAC_PORT_MAC_AN_STATE_STATUS", 0x308a4, 0 },
+ { "MAC_PORT_EPIO_DATA0", 0x308c0, 0 },
+ { "MAC_PORT_EPIO_DATA1", 0x308c4, 0 },
+ { "MAC_PORT_EPIO_DATA2", 0x308c8, 0 },
+ { "MAC_PORT_EPIO_DATA3", 0x308cc, 0 },
+ { "MAC_PORT_EPIO_OP", 0x308d0, 0 },
+ { "Busy", 31, 1 },
+ { "Write", 8, 1 },
+ { "Address", 0, 8 },
+ { "MAC_PORT_WOL_STATUS", 0x308d4, 0 },
+ { "MagicDetected", 31, 1 },
+ { "PatDetected", 30, 1 },
+ { "ClearMagic", 4, 1 },
+ { "ClearMatch", 3, 1 },
+ { "MatchedFilter", 0, 3 },
+ { "MAC_PORT_INT_EN", 0x308d8, 0 },
+ { "pps", 30, 1 },
+ { "tx_ts_avail", 29, 1 },
+ { "single_alarm", 28, 1 },
+ { "periodic_alarm", 27, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_INT_CAUSE", 0x308dc, 0 },
+ { "pps", 30, 1 },
+ { "tx_ts_avail", 29, 1 },
+ { "single_alarm", 28, 1 },
+ { "periodic_alarm", 27, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_PERR_INT_EN", 0x308e0, 0 },
+ { "Perr_pkt_ram", 31, 1 },
+ { "Perr_mask_ram", 30, 1 },
+ { "Perr_crc_ram", 29, 1 },
+ { "rx_mac40g", 28, 1 },
+ { "tx_mac40g", 27, 1 },
+ { "rx_st_mac40g", 26, 1 },
+ { "tx_st_mac40g", 25, 1 },
+ { "tx_mac1g10g", 24, 1 },
+ { "rx_mac1g10g", 23, 1 },
+ { "rx_status_mac1g10g", 22, 1 },
+ { "rx_st_mac1g10g", 21, 1 },
+ { "tx_st_mac1g10g", 20, 1 },
+ { "Perr_tx0_pcs40g", 19, 1 },
+ { "Perr_tx1_pcs40g", 18, 1 },
+ { "Perr_tx2_pcs40g", 17, 1 },
+ { "Perr_tx3_pcs40g", 16, 1 },
+ { "Perr_tx0_fec40g", 15, 1 },
+ { "Perr_tx1_fec40g", 14, 1 },
+ { "Perr_tx2_fec40g", 13, 1 },
+ { "Perr_tx3_fec40g", 12, 1 },
+ { "Perr_rx0_pcs40g", 11, 1 },
+ { "Perr_rx1_pcs40g", 10, 1 },
+ { "Perr_rx2_pcs40g", 9, 1 },
+ { "Perr_rx3_pcs40g", 8, 1 },
+ { "Perr_rx0_fec40g", 7, 1 },
+ { "Perr_rx1_fec40g", 6, 1 },
+ { "Perr_rx2_fec40g", 5, 1 },
+ { "Perr_rx3_fec40g", 4, 1 },
+ { "Perr_rx_pcs10g_lpbk", 3, 1 },
+ { "Perr_rx_pcs10g", 2, 1 },
+ { "Perr_rx_pcs1g", 1, 1 },
+ { "Perr_tx_pcs1g", 0, 1 },
+ { "MAC_PORT_PERR_INT_CAUSE", 0x308e4, 0 },
+ { "Perr_pkt_ram", 31, 1 },
+ { "Perr_mask_ram", 30, 1 },
+ { "Perr_crc_ram", 29, 1 },
+ { "rx_mac40g", 28, 1 },
+ { "tx_mac40g", 27, 1 },
+ { "rx_st_mac40g", 26, 1 },
+ { "tx_st_mac40g", 25, 1 },
+ { "tx_mac1g10g", 24, 1 },
+ { "rx_mac1g10g", 23, 1 },
+ { "rx_status_mac1g10g", 22, 1 },
+ { "rx_st_mac1g10g", 21, 1 },
+ { "tx_st_mac1g10g", 20, 1 },
+ { "Perr_tx0_pcs40g", 19, 1 },
+ { "Perr_tx1_pcs40g", 18, 1 },
+ { "Perr_tx2_pcs40g", 17, 1 },
+ { "Perr_tx3_pcs40g", 16, 1 },
+ { "Perr_tx0_fec40g", 15, 1 },
+ { "Perr_tx1_fec40g", 14, 1 },
+ { "Perr_tx2_fec40g", 13, 1 },
+ { "Perr_tx3_fec40g", 12, 1 },
+ { "Perr_rx0_pcs40g", 11, 1 },
+ { "Perr_rx1_pcs40g", 10, 1 },
+ { "Perr_rx2_pcs40g", 9, 1 },
+ { "Perr_rx3_pcs40g", 8, 1 },
+ { "Perr_rx0_fec40g", 7, 1 },
+ { "Perr_rx1_fec40g", 6, 1 },
+ { "Perr_rx2_fec40g", 5, 1 },
+ { "Perr_rx3_fec40g", 4, 1 },
+ { "Perr_rx_pcs10g_lpbk", 3, 1 },
+ { "Perr_rx_pcs10g", 2, 1 },
+ { "Perr_rx_pcs1g", 1, 1 },
+ { "Perr_tx_pcs1g", 0, 1 },
+ { "MAC_PORT_PERR_ENABLE", 0x308e8, 0 },
+ { "Perr_pkt_ram", 31, 1 },
+ { "Perr_mask_ram", 30, 1 },
+ { "Perr_crc_ram", 29, 1 },
+ { "rx_mac40g", 28, 1 },
+ { "tx_mac40g", 27, 1 },
+ { "rx_st_mac40g", 26, 1 },
+ { "tx_st_mac40g", 25, 1 },
+ { "tx_mac1g10g", 24, 1 },
+ { "rx_mac1g10g", 23, 1 },
+ { "rx_status_mac1g10g", 22, 1 },
+ { "rx_st_mac1g10g", 21, 1 },
+ { "tx_st_mac1g10g", 20, 1 },
+ { "Perr_tx0_pcs40g", 19, 1 },
+ { "Perr_tx1_pcs40g", 18, 1 },
+ { "Perr_tx2_pcs40g", 17, 1 },
+ { "Perr_tx3_pcs40g", 16, 1 },
+ { "Perr_tx0_fec40g", 15, 1 },
+ { "Perr_tx1_fec40g", 14, 1 },
+ { "Perr_tx2_fec40g", 13, 1 },
+ { "Perr_tx3_fec40g", 12, 1 },
+ { "Perr_rx0_pcs40g", 11, 1 },
+ { "Perr_rx1_pcs40g", 10, 1 },
+ { "Perr_rx2_pcs40g", 9, 1 },
+ { "Perr_rx3_pcs40g", 8, 1 },
+ { "Perr_rx0_fec40g", 7, 1 },
+ { "Perr_rx1_fec40g", 6, 1 },
+ { "Perr_rx2_fec40g", 5, 1 },
+ { "Perr_rx3_fec40g", 4, 1 },
+ { "Perr_rx_pcs10g_lpbk", 3, 1 },
+ { "Perr_rx_pcs10g", 2, 1 },
+ { "Perr_rx_pcs1g", 1, 1 },
+ { "Perr_tx_pcs1g", 0, 1 },
+ { "MAC_PORT_PERR_INJECT", 0x308ec, 0 },
+ { "MemSel", 1, 6 },
+ { "InjectDataErr", 0, 1 },
+ { "MAC_PORT_HSS_CFG0", 0x308f0, 0 },
+ { "TXDTS", 31, 1 },
+ { "TXCTS", 30, 1 },
+ { "TXBTS", 29, 1 },
+ { "TXATS", 28, 1 },
+ { "TXDOBS", 27, 1 },
+ { "TXCOBS", 26, 1 },
+ { "TXBOBS", 25, 1 },
+ { "TXAOBS", 24, 1 },
+ { "HSSREFCLKVALIDA", 20, 1 },
+ { "HSSREFCLKVALIDB", 19, 1 },
+ { "HSSRESYNCA", 18, 1 },
+ { "HSSAVDHI", 17, 1 },
+ { "HSSRESYNCB", 16, 1 },
+ { "HSSRECCALA", 15, 1 },
+ { "HSSRXACMODE", 14, 1 },
+ { "HSSRECCALB", 13, 1 },
+ { "HSSPLLBYPA", 12, 1 },
+ { "HSSPLLBYPB", 11, 1 },
+ { "HSSPDWNPLLA", 10, 1 },
+ { "HSSPDWNPLLB", 9, 1 },
+ { "HSSVCOSELA", 8, 1 },
+ { "HSSVCOSELB", 7, 1 },
+ { "HSSCALCOMP", 6, 1 },
+ { "HSSCALENAB", 5, 1 },
+ { "HSSEXTC16SEL", 4, 1 },
+ { "MAC_PORT_HSS_CFG1", 0x308f4, 0 },
+ { "RXACONFIGSEL", 30, 2 },
+ { "RXAQUIET", 29, 1 },
+ { "RXAREFRESH", 28, 1 },
+ { "RXBCONFIGSEL", 26, 2 },
+ { "RXBQUIET", 25, 1 },
+ { "RXBREFRESH", 24, 1 },
+ { "RXCCONFIGSEL", 22, 2 },
+ { "RXCQUIET", 21, 1 },
+ { "RXCREFRESH", 20, 1 },
+ { "RXDCONFIGSEL", 18, 2 },
+ { "RXDQUIET", 17, 1 },
+ { "RXDREFRESH", 16, 1 },
+ { "TXACONFIGSEL", 14, 2 },
+ { "TXAQUIET", 13, 1 },
+ { "TXAREFRESH", 12, 1 },
+ { "TXBCONFIGSEL", 10, 2 },
+ { "TXBQUIET", 9, 1 },
+ { "TXBREFRESH", 8, 1 },
+ { "TXCCONFIGSEL", 6, 2 },
+ { "TXCQUIET", 5, 1 },
+ { "TXCREFRESH", 4, 1 },
+ { "TXDCONFIGSEL", 2, 2 },
+ { "TXDQUIET", 1, 1 },
+ { "TXDREFRESH", 0, 1 },
+ { "MAC_PORT_HSS_CFG2", 0x308f8, 0 },
+ { "RXAASSTCLK", 31, 1 },
+ { "T5RXAPRBSRST", 30, 1 },
+ { "RXBASSTCLK", 29, 1 },
+ { "T5RXBPRBSRST", 28, 1 },
+ { "RXCASSTCLK", 27, 1 },
+ { "T5RXCPRBSRST", 26, 1 },
+ { "RXDASSTCLK", 25, 1 },
+ { "T5RXDPRBSRST", 24, 1 },
+ { "RXDDATASYNC", 23, 1 },
+ { "RXCDATASYNC", 22, 1 },
+ { "RXBDATASYNC", 21, 1 },
+ { "RXADATASYNC", 20, 1 },
+ { "RXDEARLYIN", 19, 1 },
+ { "RXDLATEIN", 18, 1 },
+ { "RXDPHSLOCK", 17, 1 },
+ { "RXDPHSDNIN", 16, 1 },
+ { "RXDPHSUPIN", 15, 1 },
+ { "RXCEARLYIN", 14, 1 },
+ { "RXCLATEIN", 13, 1 },
+ { "RXCPHSLOCK", 12, 1 },
+ { "RXCPHSDNIN", 11, 1 },
+ { "RXCPHSUPIN", 10, 1 },
+ { "RXBEARLYIN", 9, 1 },
+ { "RXBLATEIN", 8, 1 },
+ { "RXBPHSLOCK", 7, 1 },
+ { "RXBPHSDNIN", 6, 1 },
+ { "RXBPHSUPIN", 5, 1 },
+ { "RXAEARLYIN", 4, 1 },
+ { "RXALATEIN", 3, 1 },
+ { "RXAPHSLOCK", 2, 1 },
+ { "RXAPHSDNIN", 1, 1 },
+ { "RXAPHSUPIN", 0, 1 },
+ { "MAC_PORT_HSS_CFG3", 0x308fc, 0 },
+ { "HSSCALSSTN", 22, 6 },
+ { "HSSCALSSTP", 16, 6 },
+ { "HSSPLLCONFIGB", 8, 8 },
+ { "HSSPLLCONFIGA", 0, 8 },
+ { "MAC_PORT_HSS_CFG4", 0x30900, 0 },
+ { "HSSREFDIVA", 24, 4 },
+ { "HSSREFDIVB", 20, 4 },
+ { "HSSPLLDIV2B", 19, 1 },
+ { "HSSPLLDIV2A", 18, 1 },
+ { "HSSDIVSELA", 9, 9 },
+ { "HSSDIVSELB", 0, 9 },
+ { "MAC_PORT_HSS_STATUS", 0x30904, 0 },
+ { "RXDERROFLOW", 19, 1 },
+ { "RXCERROFLOW", 18, 1 },
+ { "RXBERROFLOW", 17, 1 },
+ { "RXAERROFLOW", 16, 1 },
+ { "RXDPRBSSYNC", 15, 1 },
+ { "RXCPRBSSYNC", 14, 1 },
+ { "RXBPRBSSYNC", 13, 1 },
+ { "RXAPRBSSYNC", 12, 1 },
+ { "RXDPRBSERR", 11, 1 },
+ { "RXCPRBSERR", 10, 1 },
+ { "RXBPRBSERR", 9, 1 },
+ { "RXAPRBSERR", 8, 1 },
+ { "RXDSIGDET", 7, 1 },
+ { "RXCSIGDET", 6, 1 },
+ { "RXBSIGDET", 5, 1 },
+ { "RXASIGDET", 4, 1 },
+ { "HSSPLLLOCKB", 3, 1 },
+ { "HSSPLLLOCKA", 2, 1 },
+ { "HSSPRTREADYB", 1, 1 },
+ { "HSSPRTREADYA", 0, 1 },
+ { "MAC_PORT_HSS_EEE_STATUS", 0x30908, 0 },
+ { "RXAQUIET_STATUS", 15, 1 },
+ { "RXAREFRESH_STATUS", 14, 1 },
+ { "RXBQUIET_STATUS", 13, 1 },
+ { "RXBREFRESH_STATUS", 12, 1 },
+ { "RXCQUIET_STATUS", 11, 1 },
+ { "RXCREFRESH_STATUS", 10, 1 },
+ { "RXDQUIET_STATUS", 9, 1 },
+ { "RXDREFRESH_STATUS", 8, 1 },
+ { "TXAQUIET_STATUS", 7, 1 },
+ { "TXAREFRESH_STATUS", 6, 1 },
+ { "TXBQUIET_STATUS", 5, 1 },
+ { "TXBREFRESH_STATUS", 4, 1 },
+ { "TXCQUIET_STATUS", 3, 1 },
+ { "TXCREFRESH_STATUS", 2, 1 },
+ { "TXDQUIET_STATUS", 1, 1 },
+ { "TXDREFRESH_STATUS", 0, 1 },
+ { "MAC_PORT_HSS_SIGDET_STATUS", 0x3090c, 0 },
+ { "MAC_PORT_HSS_PL_CTL", 0x30910, 0 },
+ { "TOV", 16, 8 },
+ { "TSU", 8, 8 },
+ { "IPW", 0, 8 },
+ { "MAC_PORT_RUNT_FRAME", 0x30914, 0 },
+ { "runtclear", 16, 1 },
+ { "runt", 0, 16 },
+ { "MAC_PORT_EEE_STATUS", 0x30918, 0 },
+ { "eee_tx_10g_state", 10, 2 },
+ { "eee_rx_10g_state", 8, 2 },
+ { "eee_tx_1g_state", 6, 2 },
+ { "eee_rx_1g_state", 4, 2 },
+ { "pma_rx_refresh", 3, 1 },
+ { "pma_rx_quiet", 2, 1 },
+ { "pma_tx_refresh", 1, 1 },
+ { "pma_tx_quiet", 0, 1 },
+ { "MAC_PORT_CGEN", 0x3091c, 0 },
+ { "CGEN", 8, 1 },
+ { "sd7_CGEN", 7, 1 },
+ { "sd6_CGEN", 6, 1 },
+ { "sd5_CGEN", 5, 1 },
+ { "sd4_CGEN", 4, 1 },
+ { "sd3_CGEN", 3, 1 },
+ { "sd2_CGEN", 2, 1 },
+ { "sd1_CGEN", 1, 1 },
+ { "sd0_CGEN", 0, 1 },
+ { "MAC_PORT_CGEN_MTIP", 0x30920, 0 },
+ { "MACSEG5_CGEN", 11, 1 },
+ { "PCSSEG5_CGEN", 10, 1 },
+ { "MACSEG4_CGEN", 9, 1 },
+ { "PCSSEG4_CGEN", 8, 1 },
+ { "MACSEG3_CGEN", 7, 1 },
+ { "PCSSEG3_CGEN", 6, 1 },
+ { "MACSEG2_CGEN", 5, 1 },
+ { "PCSSEG2_CGEN", 4, 1 },
+ { "MACSEG1_CGEN", 3, 1 },
+ { "PCSSEG1_CGEN", 2, 1 },
+ { "MACSEG0_CGEN", 1, 1 },
+ { "PCSSEG0_CGEN", 0, 1 },
+ { "MAC_PORT_TX_TS_ID", 0x30924, 0 },
+ { "MAC_PORT_TX_TS_VAL_LO", 0x30928, 0 },
+ { "MAC_PORT_TX_TS_VAL_HI", 0x3092c, 0 },
+ { "MAC_PORT_EEE_CTL", 0x30930, 0 },
+ { "EEE_CTRL", 2, 30 },
+ { "TICK_START", 1, 1 },
+ { "En", 0, 1 },
+ { "MAC_PORT_EEE_TX_CTL", 0x30934, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_ACTIVE", 3, 1 },
+ { "LPI_TXHOLD", 2, 1 },
+ { "LPI_REQ", 1, 1 },
+ { "EEE_TX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_RX_CTL", 0x30938, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_IND", 1, 1 },
+ { "EEE_RX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3093c, 0 },
+ { "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x30940, 0 },
+ { "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x30944, 0 },
+ { "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x30948, 0 },
+ { "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3094c, 0 },
+ { "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x30950, 0 },
+ { "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x30954, 0 },
+ { "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x30958, 0 },
+ { "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3095c, 0 },
+ { "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x30960, 0 },
+ { "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x30964, 0 },
+ { "MAC_PORT_EEE_WF_COUNT", 0x30968, 0 },
+ { "wake_cnt_clr", 16, 1 },
+ { "wake_cnt", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_RD0_LO", 0x3096c, 0 },
+ { "MAC_PORT_PTP_TIMER_RD0_HI", 0x30970, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_LO", 0x30974, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_HI", 0x30978, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_LO", 0x3097c, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_HI", 0x30980, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_0", 0x30984, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_1", 0x30988, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3098c, 0 },
+ { "MAC_PORT_PTP_SUM_LO", 0x30990, 0 },
+ { "MAC_PORT_PTP_SUM_HI", 0x30994, 0 },
+ { "MAC_PORT_PTP_TIMER_INCR0", 0x30998, 0 },
+ { "Y", 16, 16 },
+ { "X", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_INCR1", 0x3099c, 0 },
+ { "Y_TICK", 16, 16 },
+ { "X_TICK", 0, 16 },
+ { "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x309a0, 0 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x309a4, 0 },
+ { "B", 16, 16 },
+ { "A", 0, 16 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x309a8, 0 },
+ { "MAC_PORT_PTP_CFG", 0x309ac, 0 },
+ { "ALARM_EN", 21, 1 },
+ { "ALARM_START", 20, 1 },
+ { "PPS_EN", 19, 1 },
+ { "FRZ", 18, 1 },
+ { "OFFSER_ADJUST_SIGN", 17, 1 },
+ { "ADD_OFFSET", 16, 1 },
+ { "CYCLE1", 8, 8 },
+ { "Q", 0, 8 },
+ { "MAC_PORT_PTP_PPS", 0x309b0, 0 },
+ { "MAC_PORT_PTP_SINGLE_ALARM", 0x309b4, 0 },
+ { "MAC_PORT_PTP_PERIODIC_ALARM", 0x309b8, 0 },
+ { "MAC_PORT_PTP_STATUS", 0x309bc, 0 },
+ { "MAC_PORT_MTIP_REVISION", 0x30a00, 0 },
+ { "CUSTREV", 16, 16 },
+ { "VER", 8, 8 },
+ { "REV", 0, 8 },
+ { "MAC_PORT_MTIP_SCRATCH", 0x30a04, 0 },
+ { "MAC_PORT_MTIP_COMMAND_CONFIG", 0x30a08, 0 },
+ { "TX_FLUSH", 22, 1 },
+ { "RX_SFD_ANY", 21, 1 },
+ { "PAUSE_PFC_COMP", 20, 1 },
+ { "PFC_MODE", 19, 1 },
+ { "RS_COL_CNT_EXT", 18, 1 },
+ { "NO_LGTH_CHECK", 17, 1 },
+ { "SEND_IDLE", 16, 1 },
+ { "PHY_TXENA", 15, 1 },
+ { "RX_ERR_DISC", 14, 1 },
+ { "CMD_FRAME_ENA", 13, 1 },
+ { "SW_RESET", 12, 1 },
+ { "TX_PAD_EN", 11, 1 },
+ { "LOOPBACK_EN", 10, 1 },
+ { "TX_ADDR_INS", 9, 1 },
+ { "PAUSE_IGNORE", 8, 1 },
+ { "PAUSE_FWD", 7, 1 },
+ { "CRC_FWD", 6, 1 },
+ { "PAD_EN", 5, 1 },
+ { "PROMIS_EN", 4, 1 },
+ { "WAN_MODE", 3, 1 },
+ { "RX_ENA", 1, 1 },
+ { "TX_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_MAC_ADDR_0", 0x30a0c, 0 },
+ { "MAC_PORT_MTIP_MAC_ADDR_1", 0x30a10, 0 },
+ { "MAC_PORT_MTIP_FRM_LENGTH", 0x30a14, 0 },
+ { "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x30a1c, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x30a20, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x30a24, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x30a28, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x30a2c, 0 },
+ { "ENABLE", 8, 1 },
+ { "ADDR", 0, 6 },
+ { "MAC_PORT_MTIP_MAC_STATUS", 0x30a40, 0 },
+ { "TS_AVAIL", 3, 1 },
+ { "PHY_LOS", 2, 1 },
+ { "RX_REM_FAULT", 1, 1 },
+ { "RX_LOC_FAULT", 0, 1 },
+ { "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x30a44, 0 },
+ { "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x30a48, 0 },
+ { "MAC_PORT_MTIP_INIT_CREDIT", 0x30a4c, 0 },
+ { "MAC_PORT_MTIP_CURRENT_CREDIT", 0x30a50, 0 },
+ { "MAC_PORT_RX_PAUSE_STATUS", 0x30a74, 0 },
+ { "MAC_PORT_MTIP_TS_TIMESTAMP", 0x30a7c, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x30a80, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x30a84, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOK", 0x30a88, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x30a8c, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x30a90, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x30a94, 0 },
+ { "MAC_PORT_AALIGNMENTERRORS", 0x30a98, 0 },
+ { "MAC_PORT_AALIGNMENTERRORSHI", 0x30a9c, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x30aa0, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x30aa4, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x30aa8, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x30aac, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORS", 0x30ab0, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x30ab4, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORS", 0x30ab8, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORSHI", 0x30abc, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOK", 0x30ac0, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOKHI", 0x30ac4, 0 },
+ { "MAC_PORT_VLANRECEIVEDOK", 0x30ac8, 0 },
+ { "MAC_PORT_VLANRECEIVEDOKHI", 0x30acc, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x30ad0, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x30ad4, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOK", 0x30ad8, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x30adc, 0 },
+ { "MAC_PORT_IFINUCASTPKTS", 0x30ae0, 0 },
+ { "MAC_PORT_IFINUCASTPKTSHI", 0x30ae4, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTS", 0x30ae8, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTSHI", 0x30aec, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTS", 0x30af0, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTSHI", 0x30af4, 0 },
+ { "MAC_PORT_IFOUTERRORS", 0x30af8, 0 },
+ { "MAC_PORT_IFOUTERRORSHI", 0x30afc, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTS", 0x30b08, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTSHI", 0x30b0c, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTS", 0x30b10, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x30b14, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTS", 0x30b18, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x30b1c, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTS", 0x30b20, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x30b24, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETS", 0x30b28, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETSHI", 0x30b2c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS", 0x30b30, 0 },
+ { "MAC_PORT_ETHERSTATSPKTSHI", 0x30b34, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x30b38, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x30b3c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x30b40, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x30b44, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x30b48, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x30b4c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x30b50, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x30b54, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x30b58, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x30b5c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x30b60, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30b64, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x30b68, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30b6c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x30b70, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x30b74, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x30b78, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x30b7c, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERS", 0x30b80, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERSHI", 0x30b84, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTS", 0x30b88, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x30b8c, 0 },
+ { "MAC_PORT_IFINERRORS", 0x30b90, 0 },
+ { "MAC_PORT_IFINERRORSHI", 0x30b94, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x30b98, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x30b9c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x30ba0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x30ba4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x30ba8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x30bac, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x30bb0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x30bb4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x30bb8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x30bbc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x30bc0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x30bc4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x30bc8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x30bcc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x30bd0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x30bd4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x30bd8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x30bdc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x30be0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x30be4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x30be8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x30bec, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x30bf0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x30bf4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x30bf8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x30bfc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x30c00, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x30c04, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x30c08, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x30c0c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x30c10, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x30c14, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x30c18, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x30c1c, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x30c20, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x30c24, 0 },
+ { "MAC_PORT_MTIP_1G10G_REVISION", 0x30d00, 0 },
+ { "CUSTREV", 16, 16 },
+ { "VER", 8, 8 },
+ { "REV", 0, 8 },
+ { "MAC_PORT_MTIP_1G10G_SCRATCH", 0x30d04, 0 },
+ { "MAC_PORT_MTIP_1G10G_COMMAND_CONFIG", 0x30d08, 0 },
+ { "SHORT_DISCARD", 25, 1 },
+ { "REG_LOWP_RXEMPTY", 24, 1 },
+ { "TX_LOWP_ENA", 23, 1 },
+ { "TX_FLUSH", 22, 1 },
+ { "SFD_ANY", 21, 1 },
+ { "PAUSE_PFC_COMP", 20, 1 },
+ { "PFC_MODE", 19, 1 },
+ { "COL_CNT_ExT", 18, 1 },
+ { "NO_LGTH_CHECK", 17, 1 },
+ { "FORCE_SEND_IDLE", 16, 1 },
+ { "PHY_TXENA", 15, 1 },
+ { "RX_ERR_DISC", 14, 1 },
+ { "CNTL_FRM_ENA", 13, 1 },
+ { "SW_RESET", 12, 1 },
+ { "TX_PAD_EN", 11, 1 },
+ { "LOOP_ENA", 10, 1 },
+ { "TX_ADDR_INS", 9, 1 },
+ { "PAUSE_IGNORE", 8, 1 },
+ { "PAUSE_FWD", 7, 1 },
+ { "CRC_FWD", 6, 1 },
+ { "PAD_EN", 5, 1 },
+ { "PROMIS_EN", 4, 1 },
+ { "WAN_MODE", 3, 1 },
+ { "RX_ENAMAC", 1, 1 },
+ { "TX_ENAMAC", 0, 1 },
+ { "MAC_PORT_MTIP_1G10G_MAC_ADDR_0", 0x30d0c, 0 },
+ { "MAC_PORT_MTIP_1G10G_MAC_ADDR_1", 0x30d10, 0 },
+ { "MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU", 0x30d14, 0 },
+ { "SET_LEN", 16, 16 },
+ { "FRM_LEN_SET", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS", 0x30d1c, 0 },
+ { "EMPTY", 16, 16 },
+ { "AVAIL", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS", 0x30d20, 0 },
+ { "EMPTY", 16, 16 },
+ { "AVAIL", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E", 0x30d24, 0 },
+ { "AlmostFull", 16, 16 },
+ { "AlmostEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E", 0x30d28, 0 },
+ { "AlmostFull", 16, 16 },
+ { "AlmostEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD", 0x30d2c, 0 },
+ { "MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS", 0x30d30, 0 },
+ { "Clk_divisor", 7, 9 },
+ { "ENA_CLAUSE", 6, 1 },
+ { "PREAMBLE_DISABLE", 5, 1 },
+ { "Hold_time_setting", 2, 3 },
+ { "MDIO_read_error", 1, 1 },
+ { "MDIO_Busy", 0, 1 },
+ { "MAC_PORT_MTIP_1G10G_MDIO_COMMAND", 0x30d34, 0 },
+ { "READ_MODE", 15, 1 },
+ { "POST_INCR_READ", 14, 1 },
+ { "Port_PHY_Addr", 5, 5 },
+ { "Device_Reg_Addr", 0, 5 },
+ { "MAC_PORT_MTIP_1G10G_MDIO_DATA", 0x30d38, 0 },
+ { "MAC_PORT_MTIP_1G10G_MDIO_REGADDR", 0x30d3c, 0 },
+ { "MAC_PORT_MTIP_1G10G_STATUS", 0x30d40, 0 },
+ { "RX_LINT_FAULT", 7, 1 },
+ { "RX_EMPTY", 6, 1 },
+ { "TX_EMPTY", 5, 1 },
+ { "RX_LOWP", 4, 1 },
+ { "TS_AVAIL", 3, 1 },
+ { "PHY_LOS", 2, 1 },
+ { "RX_REM_FAULT", 1, 1 },
+ { "RX_LOC_FAULT", 0, 1 },
+ { "MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH", 0x30d44, 0 },
+ { "MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER", 0x30d48, 0 },
+ { "MAC_PORT_MTIP_1G10G_INIT_CREDIT", 0x30d4c, 0 },
+ { "MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA", 0x30d54, 0 },
+ { "CL1_PAUSE_QUANTA", 16, 16 },
+ { "CL0_PAUSE_QUANTA", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA", 0x30d58, 0 },
+ { "CL3_PAUSE_QUANTA", 16, 16 },
+ { "CL2_PAUSE_QUANTA", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA", 0x30d5c, 0 },
+ { "CL5_PAUSE_QUANTA", 16, 16 },
+ { "CL4_PAUSE_QUANTA", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA", 0x30d60, 0 },
+ { "CL7_PAUSE_QUANTA", 16, 16 },
+ { "CL6_PAUSE_QUANTA", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH", 0x30d64, 0 },
+ { "CL1_QUANTA_THRESH", 16, 16 },
+ { "CL0_QUANTA_THRESH", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH", 0x30d68, 0 },
+ { "CL3_QUANTA_THRESH", 16, 16 },
+ { "CL2_QUANTA_THRESH", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH", 0x30d6c, 0 },
+ { "CL5_QUANTA_THRESH", 16, 16 },
+ { "CL4_QUANTA_THRESH", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH", 0x30d70, 0 },
+ { "CL7_QUANTA_THRESH", 16, 16 },
+ { "CL6_QUANTA_THRESH", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS", 0x30d74, 0 },
+ { "MAC_PORT_MTIP_1G10G_TS_TIMESTAMP", 0x30d7c, 0 },
+ { "MAC_PORT_MTIP_1G10G_STATN_CONFIG", 0x30de0, 0 },
+ { "CLEAR", 2, 1 },
+ { "CLEAR_ON_READ", 1, 1 },
+ { "SATURATE", 0, 1 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS", 0x30e00, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI", 0x30e04, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_OCTETSOK", 0x30e08, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI", 0x30e0c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS", 0x30e10, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI", 0x30e14, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES", 0x30e18, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI", 0x30e1c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_FRAMESOK", 0x30e20, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI", 0x30e24, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_CRCERRORS", 0x30e28, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI", 0x30e2c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_VLANOK", 0x30e30, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_VLANOKHI", 0x30e34, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINERRORS", 0x30e38, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI", 0x30e3c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS", 0x30e40, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI", 0x30e44, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS", 0x30e48, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI", 0x30e4c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS", 0x30e50, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI", 0x30e54, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS", 0x30e58, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI", 0x30e5c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS", 0x30e60, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI", 0x30e64, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS", 0x30e68, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI", 0x30e6c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS", 0x30e70, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI", 0x30e74, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS", 0x30e78, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI", 0x30e7c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS", 0x30e80, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI", 0x30e84, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS", 0x30e88, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI", 0x30e8c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS", 0x30e90, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30e94, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS", 0x30e98, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30e9c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX", 0x30ea0, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI", 0x30ea4, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS", 0x30ea8, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI", 0x30eac, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS", 0x30eb0, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI", 0x30eb4, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS", 0x30eb8, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI", 0x30ebc, 0 },
+ { "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED", 0x30ec0, 0 },
+ { "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI", 0x30ec4, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG", 0x30ec8, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI", 0x30ecc, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS", 0x30ed0, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI", 0x30ed4, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS", 0x30f00, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI", 0x30f04, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_OCTETSOK", 0x30f08, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI", 0x30f0c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS", 0x30f10, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI", 0x30f14, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES", 0x30f18, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI", 0x30f1c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_FRAMESOK", 0x30f20, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI", 0x30f24, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_CRCERRORS", 0x30f28, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI", 0x30f2c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_VLANOK", 0x30f30, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_VLANOKHI", 0x30f34, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS", 0x30f38, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI", 0x30f3c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS", 0x30f40, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI", 0x30f44, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS", 0x30f48, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI", 0x30f4c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS", 0x30f50, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI", 0x30f54, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS", 0x30f58, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI", 0x30f5c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS", 0x30f60, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI", 0x30f64, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS", 0x30f68, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI", 0x30f6c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS", 0x30f70, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI", 0x30f74, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS", 0x30f78, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI", 0x30f7c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS", 0x30f80, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI", 0x30f84, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS", 0x30f88, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI", 0x30f8c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS", 0x30f90, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30f94, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS", 0x30f98, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30f9c, 0 },
+ { "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU", 0x30fa0, 0 },
+ { "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI", 0x30fa4, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES", 0x30fc0, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI", 0x30fc4, 0 },
+ { "MAC_PORT_MTIP_1G10G_IF_MODE", 0x31000, 0 },
+ { "MII_ENA_10", 4, 1 },
+ { "IF_MODE", 0, 2 },
+ { "MAC_PORT_MTIP_1G10G_IF_STATUS", 0x31004, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0", 0x31080, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI", 0x31084, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1", 0x31088, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI", 0x3108c, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2", 0x31090, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI", 0x31094, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3", 0x31098, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI", 0x3109c, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4", 0x310a0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI", 0x310a4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5", 0x310a8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI", 0x310ac, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6", 0x310b0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI", 0x310b4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7", 0x310b8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI", 0x310bc, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0", 0x310c0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI", 0x310c4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1", 0x310c8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI", 0x310cc, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2", 0x310d0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI", 0x310d4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3", 0x310d8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI", 0x310dc, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4", 0x310e0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI", 0x310e4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5", 0x310e8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI", 0x310ec, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6", 0x310f0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI", 0x310f4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7", 0x310f8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI", 0x310fc, 0 },
+ { "MAC_PORT_MTIP_SGMII_CONTROL", 0x31200, 0 },
+ { "Reset", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "Speed_Sel", 13, 1 },
+ { "AN_EN", 12, 1 },
+ { "PWR_DWN", 11, 1 },
+ { "Isolate", 10, 1 },
+ { "AN_RESTART", 9, 1 },
+ { "DUPLEx_MODE", 8, 1 },
+ { "Collision_Test", 7, 1 },
+ { "Speed_Sel1", 6, 1 },
+ { "MAC_PORT_MTIP_SGMII_STATUS", 0x31204, 0 },
+ { "100BaseT4", 15, 1 },
+ { "100BasexFullDplx", 14, 1 },
+ { "100BasexHalfDplx", 13, 1 },
+ { "10MbpsFullDplx", 12, 1 },
+ { "10MbpsHalfDplx", 11, 1 },
+ { "100BaseT2FullDplx", 10, 1 },
+ { "100BaseT2HalfDplx", 9, 1 },
+ { "ExtdStatus", 8, 1 },
+ { "AN_Complete", 5, 1 },
+ { "REM_FAULT", 4, 1 },
+ { "AN_Ability", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "JabberDetect", 1, 1 },
+ { "ExtdCapability", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x31208, 0 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x3120c, 0 },
+ { "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x31210, 0 },
+ { "NP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "RF2", 13, 1 },
+ { "RF1", 12, 1 },
+ { "PS2", 8, 1 },
+ { "PS1", 7, 1 },
+ { "HD", 6, 1 },
+ { "FD", 5, 1 },
+ { "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x31214, 0 },
+ { "CuLinkStatus", 15, 1 },
+ { "ACK", 14, 1 },
+ { "CuDplxStatus", 12, 1 },
+ { "CuSpeed", 10, 2 },
+ { "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x31218, 0 },
+ { "Next_Page_Able", 2, 1 },
+ { "PAGE_RECEIVE", 1, 1 },
+ { "MAC_PORT_MTIP_SGMII_NP_TX", 0x3121c, 0 },
+ { "MAC_PORT_MTIP_SGMII_LP_NP_RX", 0x31220, 0 },
+ { "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x3123c, 0 },
+ { "MAC_PORT_MTIP_SGMII_SCRATCH", 0x31240, 0 },
+ { "MAC_PORT_MTIP_SGMII_REV", 0x31244, 0 },
+ { "CUSTREV", 16, 16 },
+ { "VER", 8, 8 },
+ { "REV", 0, 8 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x31248, 0 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x3124c, 0 },
+ { "MAC_PORT_MTIP_SGMII_IF_MODE", 0x31250, 0 },
+ { "SGMII_DUPLEx", 4, 1 },
+ { "SGMII_SPEED", 2, 2 },
+ { "USE_SGMII_AN", 1, 1 },
+ { "SGMII_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_DECODE_ERROR", 0x31254, 0 },
+ { "MAC_PORT_MTIP_KR_PCS_CONTROL_1", 0x31300, 0 },
+ { "Reset", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "Speed_SEL", 13, 1 },
+ { "Low_Power", 11, 1 },
+ { "Speed_SEL1", 6, 1 },
+ { "Speed_SEL2", 2, 4 },
+ { "MAC_PORT_MTIP_KR_PCS_STATUS_1", 0x31304, 0 },
+ { "TX_LPI", 11, 1 },
+ { "RX_LPI", 10, 1 },
+ { "TX_LPI_ACTIVE", 9, 1 },
+ { "RX_LPI_ACTIVE", 8, 1 },
+ { "Fault", 7, 1 },
+ { "PCS_RX_Link_STAT", 2, 1 },
+ { "Low_power_Ability", 1, 1 },
+ { "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1", 0x31308, 0 },
+ { "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2", 0x3130c, 0 },
+ { "MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY", 0x31310, 0 },
+ { "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO", 0x31314, 0 },
+ { "Auto_Negotiation_Present", 7, 1 },
+ { "DTE_xS_present", 5, 1 },
+ { "PHY_xS_present", 4, 1 },
+ { "PCS_present", 3, 1 },
+ { "WIS_present", 2, 1 },
+ { "PMD_PMA_Present", 1, 1 },
+ { "Clause_22_Reg_Present", 0, 1 },
+ { "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI", 0x31318, 0 },
+ { "Auto_Negotiation_Present", 7, 1 },
+ { "DTE_xS_present", 5, 1 },
+ { "PHY_xS_present", 4, 1 },
+ { "PCS_present", 3, 1 },
+ { "WIS_present", 2, 1 },
+ { "PMD_PMA_Present", 1, 1 },
+ { "Clause_22_Reg_Present", 0, 1 },
+ { "MAC_PORT_MTIP_KR_PCS_CONTROL_2", 0x3131c, 0 },
+ { "MAC_PORT_MTIP_KR_PCS_STATUS_2", 0x31320, 0 },
+ { "Device_Present", 14, 2 },
+ { "Transmit_Fault", 11, 1 },
+ { "Receive_Fault", 10, 1 },
+ { "10GBASE_W_Capable", 2, 1 },
+ { "10GBASE_x_Capable", 1, 1 },
+ { "10GBASE_R_Capable", 0, 1 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO", 0x31338, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI", 0x3133c, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1", 0x31380, 0 },
+ { "10GBASE_R_RX_Link_Status", 12, 1 },
+ { "PRBS9_Pttrn_Tstng_Ability", 3, 1 },
+ { "PRBS31_Pttrn_Tstng_Ability", 2, 1 },
+ { "10GBASE_R_PCS_High_BER", 1, 1 },
+ { "10GBASE_R_PCS_Block_Lock", 0, 1 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2", 0x31384, 0 },
+ { "Latched_Block_Lock", 15, 1 },
+ { "Latched_High_BER", 14, 1 },
+ { "BERBER_Counter", 8, 6 },
+ { "ErrBlkCnt", 0, 8 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0", 0x31388, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1", 0x3138c, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2", 0x31390, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3", 0x31394, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0", 0x31398, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1", 0x3139c, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2", 0x313a0, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3", 0x313a4, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL", 0x313a8, 0 },
+ { "PRBS9_TX_Tst_Pttrn_En", 6, 1 },
+ { "PRBS31_RX_Tst_Pttrn_En", 5, 1 },
+ { "PRBS31_TX_Tst_Pttrn_En", 4, 1 },
+ { "TX_Test_Pattern_En", 3, 1 },
+ { "RX_Test_Pattern_En", 2, 1 },
+ { "Test_Pattern_Select", 1, 1 },
+ { "Data_Pattern_Select", 0, 1 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER", 0x313ac, 0 },
+ { "MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS", 0x313b4, 0 },
+ { "Transmit_FIFO_Fault", 1, 1 },
+ { "Receive_FIFO_Fault", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_CONTROL_1", 0x31400, 0 },
+ { "RESET", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "Speed_selection", 13, 1 },
+ { "Low_power", 11, 1 },
+ { "Speed_selection1", 6, 1 },
+ { "Speed_selection2", 2, 4 },
+ { "MAC_PORT_MTIP_KR4_STATUS_1", 0x31404, 0 },
+ { "Fault", 7, 1 },
+ { "Receive_link_STAT", 2, 1 },
+ { "Low_power_ability", 1, 1 },
+ { "MAC_PORT_MTIP_KR4_DEVICE_ID0", 0x31408, 0 },
+ { "MAC_PORT_MTIP_KR4_DEVICE_ID1", 0x3140c, 0 },
+ { "DEVICE_ID1", 16, 16 },
+ { "MAC_PORT_MTIP_KR4_SPEED_ABILITY", 0x31410, 0 },
+ { "100G_capable", 3, 1 },
+ { "40G_capable", 2, 1 },
+ { "10PASS_TS_2Base_TL_capable", 1, 1 },
+ { "10G_capable", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1", 0x31414, 0 },
+ { "TC_present", 6, 1 },
+ { "DTE_xS_present", 5, 1 },
+ { "PHY_xS_present", 4, 1 },
+ { "PCS_present", 3, 1 },
+ { "WIS_present", 2, 1 },
+ { "PMD_PMA_present", 1, 1 },
+ { "Clause_22_reg", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2", 0x31418, 0 },
+ { "Vendor_specific_device", 15, 1 },
+ { "Vendor_specific_device1", 14, 1 },
+ { "Clause_22_ExT", 13, 1 },
+ { "MAC_PORT_MTIP_KR4_CONTROL_2", 0x3141c, 0 },
+ { "MAC_PORT_MTIP_KR4_STATUS_2", 0x31420, 0 },
+ { "Device_present", 14, 2 },
+ { "Transmit_fault", 11, 1 },
+ { "Receive_fault", 10, 1 },
+ { "100GBase_R_capable", 5, 1 },
+ { "40GBase_R_capable", 4, 1 },
+ { "10GBase_T_capable", 3, 1 },
+ { "10GBase_W_capable", 2, 1 },
+ { "10GBase_x_capable", 1, 1 },
+ { "10GBase_R_capable", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_PKG_ID0", 0x31438, 0 },
+ { "MAC_PORT_MTIP_KR4_PKG_ID1", 0x3143c, 0 },
+ { "MAC_PORT_MTIP_KR4_BASE_R_STATUS_1", 0x31480, 0 },
+ { "RX_link_status", 12, 1 },
+ { "High_BER", 1, 1 },
+ { "Block_lock", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_BASE_R_STATUS_2", 0x31484, 0 },
+ { "Latched_bl_lk", 15, 1 },
+ { "Latched_hg_br", 14, 1 },
+ { "Ber_cnt", 8, 6 },
+ { "Err_bl_cnt", 0, 8 },
+ { "MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL", 0x314a8, 0 },
+ { "TX_TP_EN", 3, 1 },
+ { "RX_TP_EN", 2, 1 },
+ { "MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT", 0x314ac, 0 },
+ { "MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT", 0x314b0, 0 },
+ { "MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT", 0x314b4, 0 },
+ { "HI_ORDER_CNT_EN", 15, 1 },
+ { "ERR_BLK_CNTR", 0, 14 },
+ { "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1", 0x314c8, 0 },
+ { "LANE_ALIGN_STATUS", 12, 1 },
+ { "LANE_3_BLK_LCK", 3, 1 },
+ { "LANE_2_BLK_LC32_6431K", 2, 1 },
+ { "LANE_1_BLK_LCK", 1, 1 },
+ { "LANE_0_BLK_LCK", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2", 0x314cc, 0 },
+ { "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3", 0x314d0, 0 },
+ { "LANE_3_ALIGN_MRKR_LCK", 3, 1 },
+ { "LANE_2_ALIGN_MRKR_LCK", 2, 1 },
+ { "LANE_1_ALIGN_MRKR_LCK", 1, 1 },
+ { "LANE_0_ALIGN_MRKR_LCK", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4", 0x314d4, 0 },
+ { "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0", 0x31720, 0 },
+ { "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1", 0x31724, 0 },
+ { "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2", 0x31728, 0 },
+ { "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3", 0x3172c, 0 },
+ { "MAC_PORT_MTIP_KR4_LANE_0_MAPPING", 0x31a40, 0 },
+ { "MAC_PORT_MTIP_KR4_LANE_1_MAPPING", 0x31a44, 0 },
+ { "MAC_PORT_MTIP_KR4_LANE_2_MAPPING", 0x31a48, 0 },
+ { "MAC_PORT_MTIP_KR4_LANE_3_MAPPING", 0x31a4c, 0 },
+ { "MAC_PORT_MTIP_KR4_SCRATCH", 0x31af0, 0 },
+ { "MAC_PORT_MTIP_KR4_CORE_REVISION", 0x31af4, 0 },
+ { "MAC_PORT_MTIP_KR4_VL_INTVL", 0x31af8, 0 },
+ { "MAC_PORT_MTIP_KR4_TX_LANE_THRESH", 0x31afc, 0 },
+ { "MAC_PORT_MTIP_CR4_CONTROL_1", 0x31b00, 0 },
+ { "Reset", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "Speed_selection", 13, 1 },
+ { "Low_power", 11, 1 },
+ { "Speed_selection1", 6, 1 },
+ { "Speed_selection2", 2, 4 },
+ { "MAC_PORT_MTIP_CR4_STATUS_1", 0x31b04, 0 },
+ { "Fault", 7, 1 },
+ { "RX_Link_Status", 2, 1 },
+ { "Low_power_ability", 1, 1 },
+ { "MAC_PORT_MTIP_CR4_DEVICE_ID0", 0x31b08, 0 },
+ { "MAC_PORT_MTIP_CR4_DEVICE_ID1", 0x31b0c, 0 },
+ { "MAC_PORT_MTIP_CR4_SPEED_ABILITY", 0x31b10, 0 },
+ { "100G_capable", 8, 1 },
+ { "40G_capable", 7, 1 },
+ { "10PASS_TS_2Base_TL_capable", 1, 1 },
+ { "10G_capable", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1", 0x31b14, 0 },
+ { "TC_present", 6, 1 },
+ { "DTE_xS_present", 5, 1 },
+ { "PHY_xS_present", 4, 1 },
+ { "PCS_present", 3, 1 },
+ { "WIS_present", 2, 1 },
+ { "PMD_PMA_present", 1, 1 },
+ { "Clause22reg_present", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2", 0x31b18, 0 },
+ { "VSD_2_PRESENT", 15, 1 },
+ { "VSD_1_PRESENT", 14, 1 },
+ { "Clause22_ExT_Present", 13, 1 },
+ { "MAC_PORT_MTIP_CR4_CONTROL_2", 0x31b1c, 0 },
+ { "MAC_PORT_MTIP_CR4_STATUS_2", 0x31b20, 0 },
+ { "Device_present", 14, 2 },
+ { "Transmit_fault", 11, 1 },
+ { "Receive_fault", 10, 1 },
+ { "100GBase_R_capable", 5, 1 },
+ { "40GBase_R_capable", 4, 1 },
+ { "10GBase_T_capable", 3, 1 },
+ { "10GBase_W_capable", 2, 1 },
+ { "10GBase_x_capable", 1, 1 },
+ { "10GBase_R_capable", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_PKG_ID0", 0x31b38, 0 },
+ { "MAC_PORT_MTIP_CR4_PKG_ID1", 0x31b3c, 0 },
+ { "MAC_PORT_MTIP_CR4_BASE_R_STATUS_1", 0x31b80, 0 },
+ { "RX_Link_STAT", 12, 1 },
+ { "High_BER", 1, 1 },
+ { "Block_Lock", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_BASE_R_STATUS_2", 0x31b84, 0 },
+ { "Latched_block_lock", 15, 1 },
+ { "Latched_high_BER", 14, 1 },
+ { "BER_counter", 8, 6 },
+ { "Errored_blocks_cntr", 0, 8 },
+ { "MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL", 0x31ba8, 0 },
+ { "Scrambled_ID_TP_EN", 7, 1 },
+ { "MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT", 0x31bac, 0 },
+ { "MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT", 0x31bb0, 0 },
+ { "MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT", 0x31bb4, 0 },
+ { "Hi_ORDER_CNT_Present", 15, 1 },
+ { "ERR_BLKS_CNTR", 0, 14 },
+ { "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1", 0x31bc8, 0 },
+ { "LANE_ALIGN_STAT", 12, 1 },
+ { "Lane_7_blck_lck", 7, 1 },
+ { "Lane_6_blck_lck", 6, 1 },
+ { "Lane_5_blck_lck", 5, 1 },
+ { "Lane_4_blck_lck", 4, 1 },
+ { "Lane_3_blck_lck", 3, 1 },
+ { "Lane_2_blck_lck", 2, 1 },
+ { "Lane_1_blck_lck", 1, 1 },
+ { "Lane_0_blck_lck", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2", 0x31bcc, 0 },
+ { "Lane_19_blck_lck", 11, 1 },
+ { "Lane_18_blck_lck", 10, 1 },
+ { "Lane_17_blck_lck", 9, 1 },
+ { "Lane_16_blck_lck", 8, 1 },
+ { "Lane_15_blck_lck", 7, 1 },
+ { "Lane_14_blck_lck", 6, 1 },
+ { "Lane_13_blck_lck", 5, 1 },
+ { "Lane_12_blck_lck", 4, 1 },
+ { "Lane_11_blck_lck", 3, 1 },
+ { "Lane_10_blck_lck", 2, 1 },
+ { "Lane_9_blck_lck", 1, 1 },
+ { "Lane_8_blck_lck", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3", 0x31bd0, 0 },
+ { "Lane7_algn_mrkr_lck", 7, 1 },
+ { "Lane6_algn_mrkr_lck", 6, 1 },
+ { "Lane5_algn_mrkr_lck", 5, 1 },
+ { "Lane4_algn_mrkr_lck", 4, 1 },
+ { "Lane3_algn_mrkr_lck", 3, 1 },
+ { "Lane2_algn_mrkr_lck", 2, 1 },
+ { "Lane1_algn_mrkr_lck", 1, 1 },
+ { "Lane0_algn_mrkr_lck", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4", 0x31bd4, 0 },
+ { "Lane19_algn_mrkr_lck", 11, 1 },
+ { "Lane18_algn_mrkr_lck", 10, 1 },
+ { "Lane17_algn_mrkr_lck", 9, 1 },
+ { "Lane16_algn_mrkr_lck", 8, 1 },
+ { "Lane15_algn_mrkr_lck", 7, 1 },
+ { "Lane14_algn_mrkr_lck", 6, 1 },
+ { "Lane13_algn_mrkr_lck", 5, 1 },
+ { "Lane12_algn_mrkr_lck", 4, 1 },
+ { "Lane11_algn_mrkr_lck", 3, 1 },
+ { "Lane10_algn_mrkr_lck", 2, 1 },
+ { "Lane9_algn_mrkr_lck", 1, 1 },
+ { "Lane8_algn_mrkr_lck", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0", 0x31e20, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1", 0x31e24, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2", 0x31e28, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3", 0x31e2c, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4", 0x31e30, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5", 0x31e34, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6", 0x31e38, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7", 0x31e3c, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8", 0x31e40, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9", 0x31e44, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10", 0x31e48, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11", 0x31e4c, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12", 0x31e50, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13", 0x31e54, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14", 0x31e58, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15", 0x31e5c, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16", 0x31e60, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17", 0x31e64, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18", 0x31e68, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19", 0x31e6c, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_0_MAPPING", 0x32140, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_1_MAPPING", 0x32144, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_2_MAPPING", 0x32148, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_3_MAPPING", 0x3214c, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_4_MAPPING", 0x32150, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_5_MAPPING", 0x32154, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_6_MAPPING", 0x32158, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_7_MAPPING", 0x3215c, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_8_MAPPING", 0x32160, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_9_MAPPING", 0x32164, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_10_MAPPING", 0x32168, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_11_MAPPING", 0x3216c, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_12_MAPPING", 0x32170, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_13_MAPPING", 0x32174, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_14_MAPPING", 0x32178, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_15_MAPPING", 0x3217c, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_16_MAPPING", 0x32180, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_17_MAPPING", 0x32184, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_18_MAPPING", 0x32188, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_19_MAPPING", 0x3218c, 0 },
+ { "MAC_PORT_MTIP_CR4_SCRATCH", 0x321f0, 0 },
+ { "MAC_PORT_MTIP_CR4_CORE_REVISION", 0x321f4, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_CONTROL", 0x32200, 0 },
+ { "RS_FEC_Bypass_Error_Indication", 1, 1 },
+ { "RS_FEC_Bypass_Correction", 0, 1 },
+ { "MAC_PORT_MTIP_RS_FEC_STATUS", 0x32204, 0 },
+ { "RS_FEC_PCS_align_status", 15, 1 },
+ { "fec_align_status", 14, 1 },
+ { "RS_FEC_high_SER", 2, 1 },
+ { "RS_FEC_bypass_error_indication_ability", 1, 1 },
+ { "RS_FEC_bypass_correction_ability", 0, 1 },
+ { "MAC_PORT_MTIP_RS_FEC_CCW_LO", 0x32208, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_CCW_HI", 0x3220c, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_NCCW_LO", 0x32210, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_NCCW_HI", 0x32214, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI", 0x32218, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO", 0x32228, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI", 0x3222c, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO", 0x32230, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI", 0x32234, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO", 0x32238, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI", 0x3223c, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO", 0x32240, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI", 0x32244, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL", 0x32400, 0 },
+ { "RS_FEC_enabled_status", 15, 1 },
+ { "RS_FEC_Enable", 2, 1 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1", 0x32404, 0 },
+ { "deskew_empty", 12, 4 },
+ { "fec_align_status_lh", 10, 1 },
+ { "tx_dp_overflow", 9, 1 },
+ { "rx_dp_overflow", 8, 1 },
+ { "tx_datapath_restart", 7, 1 },
+ { "rx_datapath_restart", 6, 1 },
+ { "marker_check_restart", 5, 1 },
+ { "fec_align_status_ll", 4, 1 },
+ { "amps_lock", 0, 4 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2", 0x32408, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION", 0x3240c, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY", 0x32410, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS", 0x32414, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN", 0x32418, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER", 0x3241c, 0 },
+ { "MAC_PORT_MTIP_FEC_ABILITY", 0x32618, 0 },
+ { "BASE_R_FEC_Error_Indication_Ability", 1, 1 },
+ { "BASE_R_FEC_Ability", 0, 1 },
+ { "MAC_PORT_FEC_CONTROL", 0x3261c, 0 },
+ { "fec_en_err_ind", 1, 1 },
+ { "fec_en", 0, 1 },
+ { "MAC_PORT_FEC_STATUS", 0x32620, 0 },
+ { "FEC_LOCKED0", 1, 4 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_MTIP_FEC0_CERR_CNT_0", 0x32624, 0 },
+ { "MAC_PORT_MTIP_FEC0_CERR_CNT_1", 0x32628, 0 },
+ { "MAC_PORT_MTIP_FEC0_NCERR_CNT_0", 0x3262c, 0 },
+ { "MAC_PORT_MTIP_FEC0_NCERR_CNT_1", 0x32630, 0 },
+ { "MAC_PORT_MTIP_FEC_STATUS1", 0x32664, 0 },
+ { "FEC_LOCKED0", 1, 4 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_MTIP_FEC1_CERR_CNT_0", 0x32668, 0 },
+ { "MAC_PORT_MTIP_FEC1_CERR_CNT_1", 0x3266c, 0 },
+ { "MAC_PORT_MTIP_FEC1_NCERR_CNT_0", 0x32670, 0 },
+ { "MAC_PORT_MTIP_FEC1_NCERR_CNT_1", 0x32674, 0 },
+ { "MAC_PORT_MTIP_FEC_STATUS2", 0x326a8, 0 },
+ { "FEC_LOCKED0", 1, 4 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_MTIP_FEC2_CERR_CNT_0", 0x326ac, 0 },
+ { "MAC_PORT_MTIP_FEC2_CERR_CNT_1", 0x326b0, 0 },
+ { "MAC_PORT_MTIP_FEC2_NCERR_CNT_0", 0x326b4, 0 },
+ { "MAC_PORT_MTIP_FEC2_NCERR_CNT_1", 0x326b8, 0 },
+ { "MAC_PORT_MTIP_FEC_STATUS3", 0x326ec, 0 },
+ { "FEC_LOCKED0", 1, 4 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_MTIP_FEC3_CERR_CNT_0", 0x326f0, 0 },
+ { "MAC_PORT_MTIP_FEC3_CERR_CNT_1", 0x326f4, 0 },
+ { "MAC_PORT_MTIP_FEC3_NCERR_CNT_0", 0x326f8, 0 },
+ { "MAC_PORT_MTIP_FEC3_NCERR_CNT_1", 0x326fc, 0 },
+ { "MAC_PORT_BEAN_CTL", 0x32c00, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS", 0x32c04, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0", 0x32c08, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1", 0x32c0c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2", 0x32c10, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0", 0x32c14, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1", 0x32c18, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2", 0x32c1c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT", 0x32c20, 0 },
+ { "MAC_PORT_BEAN_XNP_0", 0x32c24, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1", 0x32c28, 0 },
+ { "MAC_PORT_BEAN_XNP_2", 0x32c2c, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0", 0x32c30, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1", 0x32c34, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2", 0x32c38, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS", 0x32c3c, 0 },
+ { "100GCR4", 11, 1 },
+ { "100GKR4", 10, 1 },
+ { "100GKP4", 9, 1 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_AE_RX_COEF_REQ", 0x32a00, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C3", 6, 2 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT", 0x32a04, 0 },
+ { "T5_AE0_RXSTAT_RDY", 15, 1 },
+ { "T5_AE0_RXSTAT_LSNA", 14, 1 },
+ { "T5_AE0_RXSTAT_FEC", 13, 1 },
+ { "T5_AE0_RXSTAT_TF", 12, 1 },
+ { "T5_AE0_RXSTAT_C3", 6, 2 },
+ { "T5_AE0_RXSTAT_C2", 4, 2 },
+ { "T5_AE0_RXSTAT_C1", 2, 2 },
+ { "T5_AE0_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ", 0x32a08, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "TXREQ_FEC", 11, 1 },
+ { "T5_TXREQ_C3", 6, 2 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT", 0x32a0c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C3", 6, 2 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE", 0x32a10, 0 },
+ { "SET_WAIT_TIMER", 13, 2 },
+ { "C2_C3_STATE_SEL", 12, 1 },
+ { "FFE4_EN", 11, 1 },
+ { "FEC_REQUEST", 10, 1 },
+ { "FEC_SUPPORTED", 9, 1 },
+ { "TX_FIXED", 8, 1 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL", 0x32a14, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL", 0x32a18, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE", 0x32a1c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_1", 0x32a20, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C3", 6, 2 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_1", 0x32a24, 0 },
+ { "T5_AE1_RXSTAT_RDY", 15, 1 },
+ { "T5_AE1_RXSTAT_LSNA", 14, 1 },
+ { "T5_AE1_RXSTAT_FEC", 13, 1 },
+ { "T5_AE1_RXSTAT_TF", 12, 1 },
+ { "T5_AE1_RXSTAT_C3", 6, 2 },
+ { "T5_AE1_RXSTAT_C2", 4, 2 },
+ { "T5_AE1_RXSTAT_C1", 2, 2 },
+ { "T5_AE1_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_1", 0x32a28, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "TXREQ_FEC", 11, 1 },
+ { "T5_TXREQ_C3", 6, 2 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_1", 0x32a2c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C3", 6, 2 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_1", 0x32a30, 0 },
+ { "SET_WAIT_TIMER", 13, 2 },
+ { "C2_C3_STATE_SEL", 12, 1 },
+ { "FFE4_EN", 11, 1 },
+ { "FEC_REQUEST", 10, 1 },
+ { "FEC_SUPPORTED", 9, 1 },
+ { "TX_FIXED", 8, 1 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_1", 0x32a34, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_1", 0x32a38, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_1", 0x32a3c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_2", 0x32a40, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C3", 6, 2 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_2", 0x32a44, 0 },
+ { "T5_AE2_RXSTAT_RDY", 15, 1 },
+ { "T5_AE2_RXSTAT_LSNA", 14, 1 },
+ { "T5_AE2_RXSTAT_FEC", 13, 1 },
+ { "T5_AE2_RXSTAT_TF", 12, 1 },
+ { "T5_AE2_RXSTAT_C3", 6, 2 },
+ { "T5_AE2_RXSTAT_C2", 4, 2 },
+ { "T5_AE2_RXSTAT_C1", 2, 2 },
+ { "T5_AE2_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_2", 0x32a48, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "TXREQ_FEC", 11, 1 },
+ { "T5_TXREQ_C3", 6, 2 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_2", 0x32a4c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C3", 6, 2 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_2", 0x32a50, 0 },
+ { "SET_WAIT_TIMER", 13, 2 },
+ { "C2_C3_STATE_SEL", 12, 1 },
+ { "FFE4_EN", 11, 1 },
+ { "FEC_REQUEST", 10, 1 },
+ { "FEC_SUPPORTED", 9, 1 },
+ { "TX_FIXED", 8, 1 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_2", 0x32a54, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_2", 0x32a58, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_2", 0x32a5c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_3", 0x32a60, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C3", 6, 2 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_3", 0x32a64, 0 },
+ { "T5_AE3_RXSTAT_RDY", 15, 1 },
+ { "T5_AE3_RXSTAT_LSNA", 14, 1 },
+ { "T5_AE3_RXSTAT_FEC", 13, 1 },
+ { "T5_AE3_RXSTAT_TF", 12, 1 },
+ { "T5_AE3_RXSTAT_C3", 6, 2 },
+ { "T5_AE3_RXSTAT_C2", 4, 2 },
+ { "T5_AE3_RXSTAT_C1", 2, 2 },
+ { "T5_AE3_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_3", 0x32a68, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "TXREQ_FEC", 11, 1 },
+ { "T5_TXREQ_C3", 6, 2 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_3", 0x32a6c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C3", 6, 2 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_3", 0x32a70, 0 },
+ { "SET_WAIT_TIMER", 13, 2 },
+ { "C2_C3_STATE_SEL", 12, 1 },
+ { "FFE4_EN", 11, 1 },
+ { "FEC_REQUEST", 10, 1 },
+ { "FEC_SUPPORTED", 9, 1 },
+ { "TX_FIXED", 8, 1 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_3", 0x32a74, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_3", 0x32a78, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_3", 0x32a7c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_TX_DIS", 0x32a80, 0 },
+ { "MAC_PORT_AE_KR_CTRL", 0x32a84, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET", 0x32a88, 0 },
+ { "MAC_PORT_AE_KR_STATUS", 0x32a8c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_1", 0x32a90, 0 },
+ { "MAC_PORT_AE_KR_CTRL_1", 0x32a94, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_1", 0x32a98, 0 },
+ { "MAC_PORT_AE_KR_STATUS_1", 0x32a9c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_2", 0x32aa0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_2", 0x32aa4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_2", 0x32aa8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_2", 0x32aac, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_3", 0x32ab0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_3", 0x32ab4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_3", 0x32ab8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_3", 0x32abc, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x32b00, 0 },
+ { "INIT_METH", 12, 4 },
+ { "INIT_CNT", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_N0", 5, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x32b04, 0 },
+ { "FEC_CNV", 15, 1 },
+ { "EN_RETRY", 14, 1 },
+ { "DPC_METH", 12, 2 },
+ { "EN_P2", 11, 1 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_0", 0x32b08, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x32b0c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT5", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_0", 0x32b10, 0 },
+ { "CTRL_STAT", 8, 5 },
+ { "NEU_STATE", 4, 4 },
+ { "CTRL_STATE", 0, 4 },
+ { "MAC_PORT_AET_STATUS_20", 0x32b14, 0 },
+ { "MAC_PORT_AET_LIMITS0", 0x32b18, 0 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x32b20, 0 },
+ { "INIT_METH", 12, 4 },
+ { "INIT_CNT", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_N0", 5, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x32b24, 0 },
+ { "FEC_CNV", 15, 1 },
+ { "EN_RETRY", 14, 1 },
+ { "DPC_METH", 12, 2 },
+ { "EN_P2", 11, 1 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_1", 0x32b28, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x32b2c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT5", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_1", 0x32b30, 0 },
+ { "CTRL_STAT", 8, 5 },
+ { "NEU_STATE", 4, 4 },
+ { "CTRL_STATE", 0, 4 },
+ { "MAC_PORT_AET_STATUS_21", 0x32b34, 0 },
+ { "MAC_PORT_AET_LIMITS1", 0x32b38, 0 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x32b40, 0 },
+ { "INIT_METH", 12, 4 },
+ { "INIT_CNT", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_N0", 5, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x32b44, 0 },
+ { "FEC_CNV", 15, 1 },
+ { "EN_RETRY", 14, 1 },
+ { "DPC_METH", 12, 2 },
+ { "EN_P2", 11, 1 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_2", 0x32b48, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x32b4c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT5", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_2", 0x32b50, 0 },
+ { "CTRL_STAT", 8, 5 },
+ { "NEU_STATE", 4, 4 },
+ { "CTRL_STATE", 0, 4 },
+ { "MAC_PORT_AET_STATUS_22", 0x32b54, 0 },
+ { "MAC_PORT_AET_LIMITS2", 0x32b58, 0 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x32b60, 0 },
+ { "INIT_METH", 12, 4 },
+ { "INIT_CNT", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_N0", 5, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x32b64, 0 },
+ { "FEC_CNV", 15, 1 },
+ { "EN_RETRY", 14, 1 },
+ { "DPC_METH", 12, 2 },
+ { "EN_P2", 11, 1 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_3", 0x32b68, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x32b6c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT5", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_3", 0x32b70, 0 },
+ { "CTRL_STAT", 8, 5 },
+ { "NEU_STATE", 4, 4 },
+ { "CTRL_STATE", 0, 4 },
+ { "MAC_PORT_AET_STATUS_23", 0x32b74, 0 },
+ { "MAC_PORT_AET_LIMITS3", 0x32b78, 0 },
+ { "MAC_PORT_ANALOG_TEST_MUX", 0x33814, 0 },
+ { "MAC_PORT_PLLREFSEL_CONTROL", 0x33854, 0 },
+ { "MAC_PORT_REFISINK_CONTROL", 0x33858, 0 },
+ { "MAC_PORT_REFISRC_CONTROL", 0x3385c, 0 },
+ { "MAC_PORT_REFVREG_CONTROL", 0x33860, 0 },
+ { "MAC_PORT_VBGENDOC_CONTROL", 0x33864, 0 },
+ { "BGCLKSEL", 2, 1 },
+ { "VBGENDOC", 0, 2 },
+ { "MAC_PORT_VREFTUNE_CONTROL", 0x33868, 0 },
+ { "MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL", 0x33880, 0 },
+ { "FRCCAL_COMP", 6, 1 },
+ { "FRCERR", 5, 1 },
+ { "CAL_BISTENAB", 4, 1 },
+ { "RCAL_RESET", 0, 1 },
+ { "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1", 0x33884, 0 },
+ { "RCALBENAB", 3, 1 },
+ { "RCALBUSY", 2, 1 },
+ { "RCALERR", 1, 1 },
+ { "RCALCOMP", 0, 1 },
+ { "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2", 0x33888, 0 },
+ { "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3", 0x3388c, 0 },
+ { "MAC_PORT_INEQUALITY_CONTROL_AND_RESULT", 0x338c0, 0 },
+ { "ISGT", 7, 1 },
+ { "ISLT", 6, 1 },
+ { "ISEQ", 5, 1 },
+ { "ISVAL", 3, 2 },
+ { "GTORLT", 1, 2 },
+ { "INEQ", 0, 1 },
+ { "MAC_PORT_INEQUALITY_LOW_LIMIT", 0x338c4, 0 },
+ { "MAC_PORT_INEQUALITY_LOW_LIMIT_MASK", 0x338c8, 0 },
+ { "MAC_PORT_INEQUALITY_HIGH_LIMIT", 0x338cc, 0 },
+ { "MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK", 0x338d0, 0 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_6", 0x338e8, 0 },
+ { "JTAGMD", 3, 1 },
+ { "RXACMODE", 2, 1 },
+ { "HSSACJPC", 1, 1 },
+ { "HSSACJAC", 0, 1 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_5", 0x338ec, 0 },
+ { "REFVALIDD", 6, 1 },
+ { "REFVALIDC", 5, 1 },
+ { "REFVALIDB", 4, 1 },
+ { "REFVALIDA", 3, 1 },
+ { "REFSELRESET", 2, 1 },
+ { "SOFTRESET", 1, 1 },
+ { "MACROTEST", 0, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x33b00, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x33b04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x33b08, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x33b0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x33b10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLA_POWER_CONTROL", 0x33b24, 0 },
+ { "SPWRENA", 1, 1 },
+ { "NPWRENA", 0, 1 },
+ { "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x33b28, 0 },
+ { "MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL", 0x33b38, 0 },
+ { "MAC_PORT_PLLA_PCLK_CONTROL", 0x33b3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x33b40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x33b44, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x33b48, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x33b4c, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x33b50, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x33bf0, 0 },
+ { "PLLDIVA", 4, 1 },
+ { "REFDIV", 0, 4 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x33bf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x33bf8, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x33bfc, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x33c00, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x33c04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x33c08, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x33c0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x33c10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLB_POWER_CONTROL", 0x33c24, 0 },
+ { "SPWRENA", 1, 1 },
+ { "NPWRENA", 0, 1 },
+ { "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x33c28, 0 },
+ { "MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL", 0x33c38, 0 },
+ { "MAC_PORT_PLLB_PCLK_CONTROL", 0x33c3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x33c40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x33c44, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x33c48, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x33c4c, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x33c50, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x33cf0, 0 },
+ { "PLLDIVA", 4, 1 },
+ { "REFDIV", 0, 4 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x33cf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x33cf8, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x33cfc, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x33000, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_RXLOOP", 5, 1 },
+ { "T5_TX_ENFFE4", 4, 1 },
+ { "T5_TX_BWSEL", 2, 2 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x33004, 0 },
+ { "SPSEL", 11, 3 },
+ { "FRCERR", 10, 1 },
+ { "ERROR", 9, 1 },
+ { "SYNC", 8, 1 },
+ { "P7CHK", 5, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x33008, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "SASMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3300c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33010, 0 },
+ { "T5DCCEN", 4, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33014, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33018, 0 },
+ { "CALSSTN", 8, 6 },
+ { "CALSSTP", 0, 6 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3301c, 0 },
+ { "DRTOL", 2, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x33020, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x33024, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x33028, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT", 0x3302c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x33034, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33038, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "SASCMD", 10, 2 },
+ { "C0UPDT", 6, 2 },
+ { "C3UPDT", 4, 2 },
+ { "C2UPDT", 2, 2 },
+ { "C1UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3303c, 0 },
+ { "C0STAT", 6, 2 },
+ { "C3STAT", 4, 2 },
+ { "C2STAT", 2, 2 },
+ { "C1STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33040, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33044, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33048, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3304c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33050, 0 },
+ { "ATUNEN", 8, 8 },
+ { "ATUNEP", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33058, 0 },
+ { "DCCCOMPINV", 8, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED", 0x33060, 0 },
+ { "AS4X7", 14, 2 },
+ { "AS4X6", 12, 2 },
+ { "AS4X5", 10, 2 },
+ { "AS4X4", 8, 2 },
+ { "AS4X3", 6, 2 },
+ { "AS4X2", 4, 2 },
+ { "AS4X1", 2, 2 },
+ { "AS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED", 0x33064, 0 },
+ { "AS2X3", 6, 2 },
+ { "AS2X2", 4, 2 },
+ { "AS2X1", 2, 2 },
+ { "AS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED", 0x33068, 0 },
+ { "AS1X7", 14, 2 },
+ { "AS1X6", 12, 2 },
+ { "AS1X5", 10, 2 },
+ { "AS1X4", 8, 2 },
+ { "AS1X3", 6, 2 },
+ { "AS1X2", 4, 2 },
+ { "AS1X1", 2, 2 },
+ { "AS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3306c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33070, 0 },
+ { "AT2X", 8, 4 },
+ { "AT4X", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33074, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33078, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3307c, 0 },
+ { "XADDR", 1, 5 },
+ { "XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33080, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33084, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33088, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3308c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3309c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x330a0, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 13, 2 },
+ { "DCCLOCK", 11, 2 },
+ { "DCCOFFSET", 8, 3 },
+ { "DCCSTEP", 6, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x330a4, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x330a8, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x330ac, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE", 0x330c0, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x330c8, 0 },
+ { "OS4X7", 14, 2 },
+ { "OS4X6", 12, 2 },
+ { "OS4X5", 10, 2 },
+ { "OS4X4", 8, 2 },
+ { "OS4X3", 6, 2 },
+ { "OS4X2", 4, 2 },
+ { "OS4X1", 2, 2 },
+ { "OS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x330cc, 0 },
+ { "OS2X3", 6, 2 },
+ { "OS2X2", 4, 2 },
+ { "OS2X1", 2, 2 },
+ { "OS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x330d0, 0 },
+ { "OS1X7", 14, 2 },
+ { "OS1X6", 12, 2 },
+ { "OS1X5", 10, 2 },
+ { "OS1X4", 8, 2 },
+ { "OS1X3", 6, 2 },
+ { "OS1X2", 4, 2 },
+ { "OS1X1", 2, 2 },
+ { "OS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x330d8, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x330dc, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x330e0, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5", 0x330ec, 0 },
+ { "ERRORP", 15, 1 },
+ { "ERRORN", 14, 1 },
+ { "TESTENA", 13, 1 },
+ { "TUNEBIT", 10, 3 },
+ { "DATAPOS", 8, 2 },
+ { "SEGSEL", 3, 5 },
+ { "TAPSEL", 1, 2 },
+ { "DATASIGN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x330f0, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x330f4, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x330f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x330fc, 0 },
+ { "SDOVRDEN", 15, 1 },
+ { "BSOUTN", 7, 1 },
+ { "BSOUTP", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x33100, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_RXLOOP", 5, 1 },
+ { "T5_TX_ENFFE4", 4, 1 },
+ { "T5_TX_BWSEL", 2, 2 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x33104, 0 },
+ { "SPSEL", 11, 3 },
+ { "FRCERR", 10, 1 },
+ { "ERROR", 9, 1 },
+ { "SYNC", 8, 1 },
+ { "P7CHK", 5, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x33108, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "SASMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3310c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33110, 0 },
+ { "T5DCCEN", 4, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33114, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33118, 0 },
+ { "CALSSTN", 8, 6 },
+ { "CALSSTP", 0, 6 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3311c, 0 },
+ { "DRTOL", 2, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x33120, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x33124, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x33128, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT", 0x3312c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x33134, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33138, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "SASCMD", 10, 2 },
+ { "C0UPDT", 6, 2 },
+ { "C3UPDT", 4, 2 },
+ { "C2UPDT", 2, 2 },
+ { "C1UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3313c, 0 },
+ { "C0STAT", 6, 2 },
+ { "C3STAT", 4, 2 },
+ { "C2STAT", 2, 2 },
+ { "C1STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33140, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33144, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33148, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3314c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33150, 0 },
+ { "ATUNEN", 8, 8 },
+ { "ATUNEP", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33158, 0 },
+ { "DCCCOMPINV", 8, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED", 0x33160, 0 },
+ { "AS4X7", 14, 2 },
+ { "AS4X6", 12, 2 },
+ { "AS4X5", 10, 2 },
+ { "AS4X4", 8, 2 },
+ { "AS4X3", 6, 2 },
+ { "AS4X2", 4, 2 },
+ { "AS4X1", 2, 2 },
+ { "AS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED", 0x33164, 0 },
+ { "AS2X3", 6, 2 },
+ { "AS2X2", 4, 2 },
+ { "AS2X1", 2, 2 },
+ { "AS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED", 0x33168, 0 },
+ { "AS1X7", 14, 2 },
+ { "AS1X6", 12, 2 },
+ { "AS1X5", 10, 2 },
+ { "AS1X4", 8, 2 },
+ { "AS1X3", 6, 2 },
+ { "AS1X2", 4, 2 },
+ { "AS1X1", 2, 2 },
+ { "AS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3316c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33170, 0 },
+ { "AT2X", 8, 4 },
+ { "AT4X", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33174, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33178, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3317c, 0 },
+ { "XADDR", 1, 5 },
+ { "XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33180, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33184, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33188, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3318c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3319c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x331a0, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 13, 2 },
+ { "DCCLOCK", 11, 2 },
+ { "DCCOFFSET", 8, 3 },
+ { "DCCSTEP", 6, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x331a4, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x331a8, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x331ac, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE", 0x331c0, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x331c8, 0 },
+ { "OS4X7", 14, 2 },
+ { "OS4X6", 12, 2 },
+ { "OS4X5", 10, 2 },
+ { "OS4X4", 8, 2 },
+ { "OS4X3", 6, 2 },
+ { "OS4X2", 4, 2 },
+ { "OS4X1", 2, 2 },
+ { "OS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x331cc, 0 },
+ { "OS2X3", 6, 2 },
+ { "OS2X2", 4, 2 },
+ { "OS2X1", 2, 2 },
+ { "OS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x331d0, 0 },
+ { "OS1X7", 14, 2 },
+ { "OS1X6", 12, 2 },
+ { "OS1X5", 10, 2 },
+ { "OS1X4", 8, 2 },
+ { "OS1X3", 6, 2 },
+ { "OS1X2", 4, 2 },
+ { "OS1X1", 2, 2 },
+ { "OS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x331d8, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x331dc, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x331e0, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5", 0x331ec, 0 },
+ { "ERRORP", 15, 1 },
+ { "ERRORN", 14, 1 },
+ { "TESTENA", 13, 1 },
+ { "TUNEBIT", 10, 3 },
+ { "DATAPOS", 8, 2 },
+ { "SEGSEL", 3, 5 },
+ { "TAPSEL", 1, 2 },
+ { "DATASIGN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x331f0, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x331f4, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x331f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x331fc, 0 },
+ { "SDOVRDEN", 15, 1 },
+ { "BSOUTN", 7, 1 },
+ { "BSOUTP", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x33400, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_RXLOOP", 5, 1 },
+ { "T5_TX_ENFFE4", 4, 1 },
+ { "T5_TX_BWSEL", 2, 2 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x33404, 0 },
+ { "SPSEL", 11, 3 },
+ { "FRCERR", 10, 1 },
+ { "ERROR", 9, 1 },
+ { "SYNC", 8, 1 },
+ { "P7CHK", 5, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x33408, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "SASMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3340c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33410, 0 },
+ { "T5DCCEN", 4, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33414, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33418, 0 },
+ { "CALSSTN", 8, 6 },
+ { "CALSSTP", 0, 6 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3341c, 0 },
+ { "DRTOL", 2, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x33420, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x33424, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x33428, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT", 0x3342c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x33434, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33438, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "SASCMD", 10, 2 },
+ { "C0UPDT", 6, 2 },
+ { "C3UPDT", 4, 2 },
+ { "C2UPDT", 2, 2 },
+ { "C1UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3343c, 0 },
+ { "C0STAT", 6, 2 },
+ { "C3STAT", 4, 2 },
+ { "C2STAT", 2, 2 },
+ { "C1STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33440, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33444, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33448, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3344c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33450, 0 },
+ { "ATUNEN", 8, 8 },
+ { "ATUNEP", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33458, 0 },
+ { "DCCCOMPINV", 8, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED", 0x33460, 0 },
+ { "AS4X7", 14, 2 },
+ { "AS4X6", 12, 2 },
+ { "AS4X5", 10, 2 },
+ { "AS4X4", 8, 2 },
+ { "AS4X3", 6, 2 },
+ { "AS4X2", 4, 2 },
+ { "AS4X1", 2, 2 },
+ { "AS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED", 0x33464, 0 },
+ { "AS2X3", 6, 2 },
+ { "AS2X2", 4, 2 },
+ { "AS2X1", 2, 2 },
+ { "AS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED", 0x33468, 0 },
+ { "AS1X7", 14, 2 },
+ { "AS1X6", 12, 2 },
+ { "AS1X5", 10, 2 },
+ { "AS1X4", 8, 2 },
+ { "AS1X3", 6, 2 },
+ { "AS1X2", 4, 2 },
+ { "AS1X1", 2, 2 },
+ { "AS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3346c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33470, 0 },
+ { "AT2X", 8, 4 },
+ { "AT4X", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33474, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33478, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3347c, 0 },
+ { "XADDR", 1, 5 },
+ { "XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33480, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33484, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33488, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3348c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3349c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x334a0, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 13, 2 },
+ { "DCCLOCK", 11, 2 },
+ { "DCCOFFSET", 8, 3 },
+ { "DCCSTEP", 6, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x334a4, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x334a8, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x334ac, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE", 0x334c0, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x334c8, 0 },
+ { "OS4X7", 14, 2 },
+ { "OS4X6", 12, 2 },
+ { "OS4X5", 10, 2 },
+ { "OS4X4", 8, 2 },
+ { "OS4X3", 6, 2 },
+ { "OS4X2", 4, 2 },
+ { "OS4X1", 2, 2 },
+ { "OS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x334cc, 0 },
+ { "OS2X3", 6, 2 },
+ { "OS2X2", 4, 2 },
+ { "OS2X1", 2, 2 },
+ { "OS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x334d0, 0 },
+ { "OS1X7", 14, 2 },
+ { "OS1X6", 12, 2 },
+ { "OS1X5", 10, 2 },
+ { "OS1X4", 8, 2 },
+ { "OS1X3", 6, 2 },
+ { "OS1X2", 4, 2 },
+ { "OS1X1", 2, 2 },
+ { "OS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x334d8, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x334dc, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x334e0, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5", 0x334ec, 0 },
+ { "ERRORP", 15, 1 },
+ { "ERRORN", 14, 1 },
+ { "TESTENA", 13, 1 },
+ { "TUNEBIT", 10, 3 },
+ { "DATAPOS", 8, 2 },
+ { "SEGSEL", 3, 5 },
+ { "TAPSEL", 1, 2 },
+ { "DATASIGN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x334f0, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x334f4, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x334f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x334fc, 0 },
+ { "SDOVRDEN", 15, 1 },
+ { "BSOUTN", 7, 1 },
+ { "BSOUTP", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x33500, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_RXLOOP", 5, 1 },
+ { "T5_TX_ENFFE4", 4, 1 },
+ { "T5_TX_BWSEL", 2, 2 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x33504, 0 },
+ { "SPSEL", 11, 3 },
+ { "FRCERR", 10, 1 },
+ { "ERROR", 9, 1 },
+ { "SYNC", 8, 1 },
+ { "P7CHK", 5, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x33508, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "SASMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3350c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33510, 0 },
+ { "T5DCCEN", 4, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33514, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33518, 0 },
+ { "CALSSTN", 8, 6 },
+ { "CALSSTP", 0, 6 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3351c, 0 },
+ { "DRTOL", 2, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x33520, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x33524, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x33528, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT", 0x3352c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x33534, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33538, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "SASCMD", 10, 2 },
+ { "C0UPDT", 6, 2 },
+ { "C3UPDT", 4, 2 },
+ { "C2UPDT", 2, 2 },
+ { "C1UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3353c, 0 },
+ { "C0STAT", 6, 2 },
+ { "C3STAT", 4, 2 },
+ { "C2STAT", 2, 2 },
+ { "C1STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33540, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33544, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33548, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3354c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33550, 0 },
+ { "ATUNEN", 8, 8 },
+ { "ATUNEP", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33558, 0 },
+ { "DCCCOMPINV", 8, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED", 0x33560, 0 },
+ { "AS4X7", 14, 2 },
+ { "AS4X6", 12, 2 },
+ { "AS4X5", 10, 2 },
+ { "AS4X4", 8, 2 },
+ { "AS4X3", 6, 2 },
+ { "AS4X2", 4, 2 },
+ { "AS4X1", 2, 2 },
+ { "AS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED", 0x33564, 0 },
+ { "AS2X3", 6, 2 },
+ { "AS2X2", 4, 2 },
+ { "AS2X1", 2, 2 },
+ { "AS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED", 0x33568, 0 },
+ { "AS1X7", 14, 2 },
+ { "AS1X6", 12, 2 },
+ { "AS1X5", 10, 2 },
+ { "AS1X4", 8, 2 },
+ { "AS1X3", 6, 2 },
+ { "AS1X2", 4, 2 },
+ { "AS1X1", 2, 2 },
+ { "AS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3356c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33570, 0 },
+ { "AT2X", 8, 4 },
+ { "AT4X", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33574, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33578, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3357c, 0 },
+ { "XADDR", 1, 5 },
+ { "XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33580, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33584, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33588, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3358c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3359c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x335a0, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 13, 2 },
+ { "DCCLOCK", 11, 2 },
+ { "DCCOFFSET", 8, 3 },
+ { "DCCSTEP", 6, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x335a4, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x335a8, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x335ac, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE", 0x335c0, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x335c8, 0 },
+ { "OS4X7", 14, 2 },
+ { "OS4X6", 12, 2 },
+ { "OS4X5", 10, 2 },
+ { "OS4X4", 8, 2 },
+ { "OS4X3", 6, 2 },
+ { "OS4X2", 4, 2 },
+ { "OS4X1", 2, 2 },
+ { "OS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x335cc, 0 },
+ { "OS2X3", 6, 2 },
+ { "OS2X2", 4, 2 },
+ { "OS2X1", 2, 2 },
+ { "OS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x335d0, 0 },
+ { "OS1X7", 14, 2 },
+ { "OS1X6", 12, 2 },
+ { "OS1X5", 10, 2 },
+ { "OS1X4", 8, 2 },
+ { "OS1X3", 6, 2 },
+ { "OS1X2", 4, 2 },
+ { "OS1X1", 2, 2 },
+ { "OS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x335d8, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x335dc, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x335e0, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5", 0x335ec, 0 },
+ { "ERRORP", 15, 1 },
+ { "ERRORN", 14, 1 },
+ { "TESTENA", 13, 1 },
+ { "TUNEBIT", 10, 3 },
+ { "DATAPOS", 8, 2 },
+ { "SEGSEL", 3, 5 },
+ { "TAPSEL", 1, 2 },
+ { "DATASIGN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x335f0, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x335f4, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x335f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x335fc, 0 },
+ { "SDOVRDEN", 15, 1 },
+ { "BSOUTN", 7, 1 },
+ { "BSOUTP", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x33900, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_RXLOOP", 5, 1 },
+ { "T5_TX_ENFFE4", 4, 1 },
+ { "T5_TX_BWSEL", 2, 2 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x33904, 0 },
+ { "SPSEL", 11, 3 },
+ { "FRCERR", 10, 1 },
+ { "ERROR", 9, 1 },
+ { "SYNC", 8, 1 },
+ { "P7CHK", 5, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x33908, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "SASMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3390c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33910, 0 },
+ { "T5DCCEN", 4, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33914, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33918, 0 },
+ { "CALSSTN", 8, 6 },
+ { "CALSSTP", 0, 6 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3391c, 0 },
+ { "DRTOL", 2, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x33920, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x33924, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x33928, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT", 0x3392c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x33934, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33938, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "SASCMD", 10, 2 },
+ { "C0UPDT", 6, 2 },
+ { "C3UPDT", 4, 2 },
+ { "C2UPDT", 2, 2 },
+ { "C1UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3393c, 0 },
+ { "C0STAT", 6, 2 },
+ { "C3STAT", 4, 2 },
+ { "C2STAT", 2, 2 },
+ { "C1STAT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x33940, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x33944, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x33948, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3394c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER", 0x33950, 0 },
+ { "ATUNEN", 8, 8 },
+ { "ATUNEP", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x33958, 0 },
+ { "DCCCOMPINV", 8, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED", 0x33960, 0 },
+ { "AS4X7", 14, 2 },
+ { "AS4X6", 12, 2 },
+ { "AS4X5", 10, 2 },
+ { "AS4X4", 8, 2 },
+ { "AS4X3", 6, 2 },
+ { "AS4X2", 4, 2 },
+ { "AS4X1", 2, 2 },
+ { "AS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED", 0x33964, 0 },
+ { "AS2X3", 6, 2 },
+ { "AS2X2", 4, 2 },
+ { "AS2X1", 2, 2 },
+ { "AS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED", 0x33968, 0 },
+ { "AS1X7", 14, 2 },
+ { "AS1X6", 12, 2 },
+ { "AS1X5", 10, 2 },
+ { "AS1X4", 8, 2 },
+ { "AS1X3", 6, 2 },
+ { "AS1X2", 4, 2 },
+ { "AS1X1", 2, 2 },
+ { "AS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3396c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x33970, 0 },
+ { "AT2X", 8, 4 },
+ { "AT4X", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x33974, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33978, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3397c, 0 },
+ { "XADDR", 1, 5 },
+ { "XWR", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33980, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33984, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x33988, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3398c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3399c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x339a0, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 13, 2 },
+ { "DCCLOCK", 11, 2 },
+ { "DCCOFFSET", 8, 3 },
+ { "DCCSTEP", 6, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x339a4, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x339a8, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x339ac, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE", 0x339c0, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x339c8, 0 },
+ { "OS4X7", 14, 2 },
+ { "OS4X6", 12, 2 },
+ { "OS4X5", 10, 2 },
+ { "OS4X4", 8, 2 },
+ { "OS4X3", 6, 2 },
+ { "OS4X2", 4, 2 },
+ { "OS4X1", 2, 2 },
+ { "OS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x339cc, 0 },
+ { "OS2X3", 6, 2 },
+ { "OS2X2", 4, 2 },
+ { "OS2X1", 2, 2 },
+ { "OS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x339d0, 0 },
+ { "OS1X7", 14, 2 },
+ { "OS1X6", 12, 2 },
+ { "OS1X5", 10, 2 },
+ { "OS1X4", 8, 2 },
+ { "OS1X3", 6, 2 },
+ { "OS1X2", 4, 2 },
+ { "OS1X1", 2, 2 },
+ { "OS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x339d8, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x339dc, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x339e0, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5", 0x339ec, 0 },
+ { "ERRORP", 15, 1 },
+ { "ERRORN", 14, 1 },
+ { "TESTENA", 13, 1 },
+ { "TUNEBIT", 10, 3 },
+ { "DATAPOS", 8, 2 },
+ { "SEGSEL", 3, 5 },
+ { "TAPSEL", 1, 2 },
+ { "DATASIGN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x339f0, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x339f4, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x339f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x339fc, 0 },
+ { "SDOVRDEN", 15, 1 },
+ { "BSOUTN", 7, 1 },
+ { "BSOUTP", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x33200, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_MODE8023AZ", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x33204, 0 },
+ { "APLYDCD", 15, 1 },
+ { "PPOL", 13, 2 },
+ { "PCLKSEL", 11, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x33208, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3320c, 0 },
+ { "H1ANOFST", 12, 4 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "TMSCAL", 8, 2 },
+ { "APADJ", 7, 1 },
+ { "RSEL", 6, 1 },
+ { "PHOFFS", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x33210, 0 },
+ { "ROTA", 8, 6 },
+ { "ROTD", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x33214, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROTE", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33218, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOFFF", 8, 4 },
+ { "RAOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3321c, 0 },
+ { "RCALER", 15, 1 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x33220, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 8, 4 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x33224, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x33228, 0 },
+ { "REQWOV", 15, 1 },
+ { "RASEL", 11, 3 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3322c, 0 },
+ { "WRAPSEL", 15, 1 },
+ { "ACTL", 14, 1 },
+ { "PEAK", 9, 5 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x33230, 0 },
+ { "FVOFFSKP", 15, 1 },
+ { "FGAINCHK", 14, 1 },
+ { "FH1ACAL", 13, 1 },
+ { "FH1AFLTR", 11, 2 },
+ { "T5SHORTV", 10, 1 },
+ { "WGAIN", 8, 2 },
+ { "GAIN_STAT", 7, 1 },
+ { "T5VGAIN", 0, 7 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x33234, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33238, 0 },
+ { "PMCFG", 6, 2 },
+ { "PMOFFTIME", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1", 0x3323c, 0 },
+ { "SELI", 9, 1 },
+ { "SERVREF", 5, 3 },
+ { "IQAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2", 0x33240, 0 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33244, 0 },
+ { "SAVEADAC", 8, 1 },
+ { "LOAD2", 7, 1 },
+ { "LOAD1", 6, 1 },
+ { "WRTACC2", 5, 1 },
+ { "WRTACC1", 4, 1 },
+ { "SELAPAN", 3, 1 },
+ { "DASEL", 0, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x33248, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN", 0x3324c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x33250, 0 },
+ { "ADAC2", 8, 8 },
+ { "ADAC1", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL", 0x33254, 0 },
+ { "FACCPLDYN", 13, 1 },
+ { "ACCPLGAIN", 10, 3 },
+ { "ACCPLREF", 8, 2 },
+ { "ACCPLSTEP", 6, 2 },
+ { "ACCPLASTEP", 1, 5 },
+ { "FACCPL", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE", 0x33258, 0 },
+ { "ACCPLMEANS", 15, 1 },
+ { "CDROVREN", 8, 1 },
+ { "ACCPLBIAS", 0, 8 },
+ { "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET", 0x3325c, 0 },
+ { "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33260, 0 },
+ { "H1OX", 8, 6 },
+ { "H1EX", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR", 0x33264, 0 },
+ { "PILOCK", 10, 1 },
+ { "UNPKPKA", 2, 6 },
+ { "UNPKVGA", 0, 2 },
+ { "MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH", 0x33268, 0 },
+ { "OVRAC", 15, 1 },
+ { "OVRPK", 14, 1 },
+ { "OVRTAILS", 12, 2 },
+ { "OVRTAILV", 9, 3 },
+ { "OVRCAP", 8, 1 },
+ { "OVRDCDPRE", 7, 1 },
+ { "OVRDCDPST", 6, 1 },
+ { "DCVSCTMODE", 2, 1 },
+ { "CDRANLGSW", 0, 2 },
+ { "MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3326c, 0 },
+ { "PFLAG", 5, 2 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33270, 0 },
+ { "DACCLIP", 15, 1 },
+ { "DPCFRZ", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCLKNQ", 11, 1 },
+ { "DPCWDFE", 10, 1 },
+ { "DPCWPK", 9, 1 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x33274, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "VIEWSCAN", 4, 1 },
+ { "ODEC", 0, 4 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x33278, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "ACCCMP", 11, 1 },
+ { "DCCCMP", 10, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5IQCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3327c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x33280, 0 },
+ { "H25SPC", 15, 1 },
+ { "FDCCAL", 14, 1 },
+ { "FROTCAL", 13, 1 },
+ { "FIQAMP", 12, 1 },
+ { "FRPTCALF", 11, 1 },
+ { "FINTCALGS", 10, 1 },
+ { "FDCC", 9, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FDCD", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FINTRCALDYN", 1, 1 },
+ { "FQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL", 0x33284, 0 },
+ { "QCCIND", 13, 1 },
+ { "DCDIND", 10, 3 },
+ { "DCCIND", 8, 2 },
+ { "CFSEL", 5, 1 },
+ { "LOFCH", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE", 0x33288, 0 },
+ { "LOFU", 8, 7 },
+ { "LOFL", 0, 7 },
+ { "MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST", 0x3328c, 0 },
+ { "HBISTMAN", 12, 1 },
+ { "HBISTRES", 11, 1 },
+ { "HBISTSP", 8, 3 },
+ { "HBISTEN", 7, 1 },
+ { "HBISTRST", 6, 1 },
+ { "HCOMP", 5, 1 },
+ { "HPASS", 4, 1 },
+ { "HSEL", 0, 4 },
+ { "MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST", 0x33290, 0 },
+ { "ACCCMP", 13, 1 },
+ { "ACCEN", 12, 1 },
+ { "ACCRST", 11, 1 },
+ { "ACCIND", 8, 3 },
+ { "ACCRD", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER", 0x33298, 0 },
+ { "LFREG", 15, 1 },
+ { "LFRC", 14, 1 },
+ { "LGIDLE", 13, 1 },
+ { "LFTGT", 8, 5 },
+ { "LGTGT", 7, 1 },
+ { "LRDY", 6, 1 },
+ { "LIDLE", 5, 1 },
+ { "LCURR", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3329c, 0 },
+ { "OFFSN", 13, 2 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x332a0, 0 },
+ { "RX_OVRSUMPD", 15, 1 },
+ { "RX_OVRKBPD", 14, 1 },
+ { "RX_OVRDIVPD", 13, 1 },
+ { "RX_OFFVGADIS", 12, 1 },
+ { "RX_OFFACDIS", 11, 1 },
+ { "RX_VTERM", 10, 1 },
+ { "RX_DISSPY2D", 8, 1 },
+ { "RX_OBSOVEN", 7, 1 },
+ { "RX_LINKANLGSW", 0, 7 },
+ { "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x332a4, 0 },
+ { "INTDACEGS", 13, 3 },
+ { "INTDACE", 8, 5 },
+ { "INTDACGS", 6, 2 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x332a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x332ac, 0 },
+ { "SMQM", 13, 3 },
+ { "SMQ", 5, 8 },
+ { "EMMD", 3, 2 },
+ { "EMBRDY", 2, 1 },
+ { "EMBUMP", 1, 1 },
+ { "EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x332b0, 0 },
+ { "EMSF", 13, 1 },
+ { "EMDATA59", 12, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x332b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x332b8, 0 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3", 0x332bc, 0 },
+ { "FTIMEOUT", 15, 1 },
+ { "FROTCAL4", 14, 1 },
+ { "FDCD2", 13, 1 },
+ { "FPRBSPOLTOG", 12, 1 },
+ { "FPRBSOFF2", 11, 1 },
+ { "FDDCAL2", 10, 1 },
+ { "FDDCFLTR", 9, 1 },
+ { "FDAC6", 8, 1 },
+ { "FDDC5", 7, 1 },
+ { "FDDC3456", 6, 1 },
+ { "FSPY2DATA", 5, 1 },
+ { "FPHSLOCK", 4, 1 },
+ { "FCLKALGN", 3, 1 },
+ { "FCLKALDYN", 2, 1 },
+ { "FDFE", 1, 1 },
+ { "FPRBSOFF", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_TAP_CONTROL", 0x332c0, 0 },
+ { "MAC_PORT_RX_LINKA_DFE_TAP", 0x332c4, 0 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2", 0x332e4, 0 },
+ { "STNDBYSTAT", 15, 1 },
+ { "CALSDONE", 14, 1 },
+ { "ACISRCCMP", 5, 1 },
+ { "PRBSOFFCMP", 4, 1 },
+ { "CLKALGNCMP", 3, 1 },
+ { "ROTFCMP", 2, 1 },
+ { "DCDCMP", 1, 1 },
+ { "QCCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x332e8, 0 },
+ { "FCSADJ", 6, 1 },
+ { "CSIND", 3, 2 },
+ { "CSVAL", 0, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL", 0x332ec, 0 },
+ { "DCDTMDOUT", 15, 1 },
+ { "DCDTOEN", 14, 1 },
+ { "DCDLOCK", 13, 1 },
+ { "DCDSTEP", 11, 2 },
+ { "DCDALTWPDIS", 10, 1 },
+ { "DCDOVRDEN", 9, 1 },
+ { "DCCAOVRDEN", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL", 0x332f0, 0 },
+ { "PRBSMODE", 14, 2 },
+ { "DCCSTEP", 10, 2 },
+ { "DCCOVRDEN", 9, 1 },
+ { "DCCLOCK", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL", 0x332f4, 0 },
+ { "DCCQCCMODE", 15, 1 },
+ { "DCCQCCDYN", 14, 1 },
+ { "DCCQCCHOLD", 13, 1 },
+ { "QCCSTEP", 10, 2 },
+ { "QCCOVRDEN", 9, 1 },
+ { "QCCLOCK", 8, 1 },
+ { "QCCSIGN", 6, 2 },
+ { "QCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x332f8, 0 },
+ { "TSTCMP", 15, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x332fc, 0 },
+ { "CALMODEEDGE", 14, 1 },
+ { "TESTCAP", 13, 1 },
+ { "SNAPEN", 12, 1 },
+ { "ASYNCDIR", 11, 1 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x33300, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_MODE8023AZ", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x33304, 0 },
+ { "APLYDCD", 15, 1 },
+ { "PPOL", 13, 2 },
+ { "PCLKSEL", 11, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x33308, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3330c, 0 },
+ { "H1ANOFST", 12, 4 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "TMSCAL", 8, 2 },
+ { "APADJ", 7, 1 },
+ { "RSEL", 6, 1 },
+ { "PHOFFS", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x33310, 0 },
+ { "ROTA", 8, 6 },
+ { "ROTD", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x33314, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROTE", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33318, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOFFF", 8, 4 },
+ { "RAOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3331c, 0 },
+ { "RCALER", 15, 1 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x33320, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 8, 4 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x33324, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x33328, 0 },
+ { "REQWOV", 15, 1 },
+ { "RASEL", 11, 3 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3332c, 0 },
+ { "WRAPSEL", 15, 1 },
+ { "ACTL", 14, 1 },
+ { "PEAK", 9, 5 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x33330, 0 },
+ { "FVOFFSKP", 15, 1 },
+ { "FGAINCHK", 14, 1 },
+ { "FH1ACAL", 13, 1 },
+ { "FH1AFLTR", 11, 2 },
+ { "T5SHORTV", 10, 1 },
+ { "WGAIN", 8, 2 },
+ { "GAIN_STAT", 7, 1 },
+ { "T5VGAIN", 0, 7 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x33334, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33338, 0 },
+ { "PMCFG", 6, 2 },
+ { "PMOFFTIME", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1", 0x3333c, 0 },
+ { "SELI", 9, 1 },
+ { "SERVREF", 5, 3 },
+ { "IQAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2", 0x33340, 0 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33344, 0 },
+ { "SAVEADAC", 8, 1 },
+ { "LOAD2", 7, 1 },
+ { "LOAD1", 6, 1 },
+ { "WRTACC2", 5, 1 },
+ { "WRTACC1", 4, 1 },
+ { "SELAPAN", 3, 1 },
+ { "DASEL", 0, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x33348, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN", 0x3334c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x33350, 0 },
+ { "ADAC2", 8, 8 },
+ { "ADAC1", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL", 0x33354, 0 },
+ { "FACCPLDYN", 13, 1 },
+ { "ACCPLGAIN", 10, 3 },
+ { "ACCPLREF", 8, 2 },
+ { "ACCPLSTEP", 6, 2 },
+ { "ACCPLASTEP", 1, 5 },
+ { "FACCPL", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE", 0x33358, 0 },
+ { "ACCPLMEANS", 15, 1 },
+ { "CDROVREN", 8, 1 },
+ { "ACCPLBIAS", 0, 8 },
+ { "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET", 0x3335c, 0 },
+ { "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33360, 0 },
+ { "H1OX", 8, 6 },
+ { "H1EX", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR", 0x33364, 0 },
+ { "PILOCK", 10, 1 },
+ { "UNPKPKA", 2, 6 },
+ { "UNPKVGA", 0, 2 },
+ { "MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH", 0x33368, 0 },
+ { "OVRAC", 15, 1 },
+ { "OVRPK", 14, 1 },
+ { "OVRTAILS", 12, 2 },
+ { "OVRTAILV", 9, 3 },
+ { "OVRCAP", 8, 1 },
+ { "OVRDCDPRE", 7, 1 },
+ { "OVRDCDPST", 6, 1 },
+ { "DCVSCTMODE", 2, 1 },
+ { "CDRANLGSW", 0, 2 },
+ { "MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3336c, 0 },
+ { "PFLAG", 5, 2 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33370, 0 },
+ { "DACCLIP", 15, 1 },
+ { "DPCFRZ", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCLKNQ", 11, 1 },
+ { "DPCWDFE", 10, 1 },
+ { "DPCWPK", 9, 1 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x33374, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "VIEWSCAN", 4, 1 },
+ { "ODEC", 0, 4 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x33378, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "ACCCMP", 11, 1 },
+ { "DCCCMP", 10, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5IQCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3337c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x33380, 0 },
+ { "H25SPC", 15, 1 },
+ { "FDCCAL", 14, 1 },
+ { "FROTCAL", 13, 1 },
+ { "FIQAMP", 12, 1 },
+ { "FRPTCALF", 11, 1 },
+ { "FINTCALGS", 10, 1 },
+ { "FDCC", 9, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FDCD", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FINTRCALDYN", 1, 1 },
+ { "FQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL", 0x33384, 0 },
+ { "QCCIND", 13, 1 },
+ { "DCDIND", 10, 3 },
+ { "DCCIND", 8, 2 },
+ { "CFSEL", 5, 1 },
+ { "LOFCH", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE", 0x33388, 0 },
+ { "LOFU", 8, 7 },
+ { "LOFL", 0, 7 },
+ { "MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST", 0x3338c, 0 },
+ { "HBISTMAN", 12, 1 },
+ { "HBISTRES", 11, 1 },
+ { "HBISTSP", 8, 3 },
+ { "HBISTEN", 7, 1 },
+ { "HBISTRST", 6, 1 },
+ { "HCOMP", 5, 1 },
+ { "HPASS", 4, 1 },
+ { "HSEL", 0, 4 },
+ { "MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST", 0x33390, 0 },
+ { "ACCCMP", 13, 1 },
+ { "ACCEN", 12, 1 },
+ { "ACCRST", 11, 1 },
+ { "ACCIND", 8, 3 },
+ { "ACCRD", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER", 0x33398, 0 },
+ { "LFREG", 15, 1 },
+ { "LFRC", 14, 1 },
+ { "LGIDLE", 13, 1 },
+ { "LFTGT", 8, 5 },
+ { "LGTGT", 7, 1 },
+ { "LRDY", 6, 1 },
+ { "LIDLE", 5, 1 },
+ { "LCURR", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3339c, 0 },
+ { "OFFSN", 13, 2 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x333a0, 0 },
+ { "RX_OVRSUMPD", 15, 1 },
+ { "RX_OVRKBPD", 14, 1 },
+ { "RX_OVRDIVPD", 13, 1 },
+ { "RX_OFFVGADIS", 12, 1 },
+ { "RX_OFFACDIS", 11, 1 },
+ { "RX_VTERM", 10, 1 },
+ { "RX_DISSPY2D", 8, 1 },
+ { "RX_OBSOVEN", 7, 1 },
+ { "RX_LINKANLGSW", 0, 7 },
+ { "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x333a4, 0 },
+ { "INTDACEGS", 13, 3 },
+ { "INTDACE", 8, 5 },
+ { "INTDACGS", 6, 2 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x333a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x333ac, 0 },
+ { "SMQM", 13, 3 },
+ { "SMQ", 5, 8 },
+ { "EMMD", 3, 2 },
+ { "EMBRDY", 2, 1 },
+ { "EMBUMP", 1, 1 },
+ { "EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x333b0, 0 },
+ { "EMSF", 13, 1 },
+ { "EMDATA59", 12, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x333b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x333b8, 0 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3", 0x333bc, 0 },
+ { "FTIMEOUT", 15, 1 },
+ { "FROTCAL4", 14, 1 },
+ { "FDCD2", 13, 1 },
+ { "FPRBSPOLTOG", 12, 1 },
+ { "FPRBSOFF2", 11, 1 },
+ { "FDDCAL2", 10, 1 },
+ { "FDDCFLTR", 9, 1 },
+ { "FDAC6", 8, 1 },
+ { "FDDC5", 7, 1 },
+ { "FDDC3456", 6, 1 },
+ { "FSPY2DATA", 5, 1 },
+ { "FPHSLOCK", 4, 1 },
+ { "FCLKALGN", 3, 1 },
+ { "FCLKALDYN", 2, 1 },
+ { "FDFE", 1, 1 },
+ { "FPRBSOFF", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_TAP_CONTROL", 0x333c0, 0 },
+ { "MAC_PORT_RX_LINKB_DFE_TAP", 0x333c4, 0 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2", 0x333e4, 0 },
+ { "STNDBYSTAT", 15, 1 },
+ { "CALSDONE", 14, 1 },
+ { "ACISRCCMP", 5, 1 },
+ { "PRBSOFFCMP", 4, 1 },
+ { "CLKALGNCMP", 3, 1 },
+ { "ROTFCMP", 2, 1 },
+ { "DCDCMP", 1, 1 },
+ { "QCCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x333e8, 0 },
+ { "FCSADJ", 6, 1 },
+ { "CSIND", 3, 2 },
+ { "CSVAL", 0, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL", 0x333ec, 0 },
+ { "DCDTMDOUT", 15, 1 },
+ { "DCDTOEN", 14, 1 },
+ { "DCDLOCK", 13, 1 },
+ { "DCDSTEP", 11, 2 },
+ { "DCDALTWPDIS", 10, 1 },
+ { "DCDOVRDEN", 9, 1 },
+ { "DCCAOVRDEN", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL", 0x333f0, 0 },
+ { "PRBSMODE", 14, 2 },
+ { "DCCSTEP", 10, 2 },
+ { "DCCOVRDEN", 9, 1 },
+ { "DCCLOCK", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL", 0x333f4, 0 },
+ { "DCCQCCMODE", 15, 1 },
+ { "DCCQCCDYN", 14, 1 },
+ { "DCCQCCHOLD", 13, 1 },
+ { "QCCSTEP", 10, 2 },
+ { "QCCOVRDEN", 9, 1 },
+ { "QCCLOCK", 8, 1 },
+ { "QCCSIGN", 6, 2 },
+ { "QCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x333f8, 0 },
+ { "TSTCMP", 15, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x333fc, 0 },
+ { "CALMODEEDGE", 14, 1 },
+ { "TESTCAP", 13, 1 },
+ { "SNAPEN", 12, 1 },
+ { "ASYNCDIR", 11, 1 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x33600, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_MODE8023AZ", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x33604, 0 },
+ { "APLYDCD", 15, 1 },
+ { "PPOL", 13, 2 },
+ { "PCLKSEL", 11, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x33608, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3360c, 0 },
+ { "H1ANOFST", 12, 4 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "TMSCAL", 8, 2 },
+ { "APADJ", 7, 1 },
+ { "RSEL", 6, 1 },
+ { "PHOFFS", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x33610, 0 },
+ { "ROTA", 8, 6 },
+ { "ROTD", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x33614, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROTE", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33618, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOFFF", 8, 4 },
+ { "RAOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3361c, 0 },
+ { "RCALER", 15, 1 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x33620, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 8, 4 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x33624, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x33628, 0 },
+ { "REQWOV", 15, 1 },
+ { "RASEL", 11, 3 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3362c, 0 },
+ { "WRAPSEL", 15, 1 },
+ { "ACTL", 14, 1 },
+ { "PEAK", 9, 5 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x33630, 0 },
+ { "FVOFFSKP", 15, 1 },
+ { "FGAINCHK", 14, 1 },
+ { "FH1ACAL", 13, 1 },
+ { "FH1AFLTR", 11, 2 },
+ { "T5SHORTV", 10, 1 },
+ { "WGAIN", 8, 2 },
+ { "GAIN_STAT", 7, 1 },
+ { "T5VGAIN", 0, 7 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x33634, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33638, 0 },
+ { "PMCFG", 6, 2 },
+ { "PMOFFTIME", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1", 0x3363c, 0 },
+ { "SELI", 9, 1 },
+ { "SERVREF", 5, 3 },
+ { "IQAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2", 0x33640, 0 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33644, 0 },
+ { "SAVEADAC", 8, 1 },
+ { "LOAD2", 7, 1 },
+ { "LOAD1", 6, 1 },
+ { "WRTACC2", 5, 1 },
+ { "WRTACC1", 4, 1 },
+ { "SELAPAN", 3, 1 },
+ { "DASEL", 0, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x33648, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN", 0x3364c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x33650, 0 },
+ { "ADAC2", 8, 8 },
+ { "ADAC1", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL", 0x33654, 0 },
+ { "FACCPLDYN", 13, 1 },
+ { "ACCPLGAIN", 10, 3 },
+ { "ACCPLREF", 8, 2 },
+ { "ACCPLSTEP", 6, 2 },
+ { "ACCPLASTEP", 1, 5 },
+ { "FACCPL", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE", 0x33658, 0 },
+ { "ACCPLMEANS", 15, 1 },
+ { "CDROVREN", 8, 1 },
+ { "ACCPLBIAS", 0, 8 },
+ { "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET", 0x3365c, 0 },
+ { "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33660, 0 },
+ { "H1OX", 8, 6 },
+ { "H1EX", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR", 0x33664, 0 },
+ { "PILOCK", 10, 1 },
+ { "UNPKPKA", 2, 6 },
+ { "UNPKVGA", 0, 2 },
+ { "MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH", 0x33668, 0 },
+ { "OVRAC", 15, 1 },
+ { "OVRPK", 14, 1 },
+ { "OVRTAILS", 12, 2 },
+ { "OVRTAILV", 9, 3 },
+ { "OVRCAP", 8, 1 },
+ { "OVRDCDPRE", 7, 1 },
+ { "OVRDCDPST", 6, 1 },
+ { "DCVSCTMODE", 2, 1 },
+ { "CDRANLGSW", 0, 2 },
+ { "MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3366c, 0 },
+ { "PFLAG", 5, 2 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33670, 0 },
+ { "DACCLIP", 15, 1 },
+ { "DPCFRZ", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCLKNQ", 11, 1 },
+ { "DPCWDFE", 10, 1 },
+ { "DPCWPK", 9, 1 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x33674, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "VIEWSCAN", 4, 1 },
+ { "ODEC", 0, 4 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x33678, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "ACCCMP", 11, 1 },
+ { "DCCCMP", 10, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5IQCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3367c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x33680, 0 },
+ { "H25SPC", 15, 1 },
+ { "FDCCAL", 14, 1 },
+ { "FROTCAL", 13, 1 },
+ { "FIQAMP", 12, 1 },
+ { "FRPTCALF", 11, 1 },
+ { "FINTCALGS", 10, 1 },
+ { "FDCC", 9, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FDCD", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FINTRCALDYN", 1, 1 },
+ { "FQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL", 0x33684, 0 },
+ { "QCCIND", 13, 1 },
+ { "DCDIND", 10, 3 },
+ { "DCCIND", 8, 2 },
+ { "CFSEL", 5, 1 },
+ { "LOFCH", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE", 0x33688, 0 },
+ { "LOFU", 8, 7 },
+ { "LOFL", 0, 7 },
+ { "MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST", 0x3368c, 0 },
+ { "HBISTMAN", 12, 1 },
+ { "HBISTRES", 11, 1 },
+ { "HBISTSP", 8, 3 },
+ { "HBISTEN", 7, 1 },
+ { "HBISTRST", 6, 1 },
+ { "HCOMP", 5, 1 },
+ { "HPASS", 4, 1 },
+ { "HSEL", 0, 4 },
+ { "MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST", 0x33690, 0 },
+ { "ACCCMP", 13, 1 },
+ { "ACCEN", 12, 1 },
+ { "ACCRST", 11, 1 },
+ { "ACCIND", 8, 3 },
+ { "ACCRD", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER", 0x33698, 0 },
+ { "LFREG", 15, 1 },
+ { "LFRC", 14, 1 },
+ { "LGIDLE", 13, 1 },
+ { "LFTGT", 8, 5 },
+ { "LGTGT", 7, 1 },
+ { "LRDY", 6, 1 },
+ { "LIDLE", 5, 1 },
+ { "LCURR", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3369c, 0 },
+ { "OFFSN", 13, 2 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x336a0, 0 },
+ { "RX_OVRSUMPD", 15, 1 },
+ { "RX_OVRKBPD", 14, 1 },
+ { "RX_OVRDIVPD", 13, 1 },
+ { "RX_OFFVGADIS", 12, 1 },
+ { "RX_OFFACDIS", 11, 1 },
+ { "RX_VTERM", 10, 1 },
+ { "RX_DISSPY2D", 8, 1 },
+ { "RX_OBSOVEN", 7, 1 },
+ { "RX_LINKANLGSW", 0, 7 },
+ { "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x336a4, 0 },
+ { "INTDACEGS", 13, 3 },
+ { "INTDACE", 8, 5 },
+ { "INTDACGS", 6, 2 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x336a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x336ac, 0 },
+ { "SMQM", 13, 3 },
+ { "SMQ", 5, 8 },
+ { "EMMD", 3, 2 },
+ { "EMBRDY", 2, 1 },
+ { "EMBUMP", 1, 1 },
+ { "EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x336b0, 0 },
+ { "EMSF", 13, 1 },
+ { "EMDATA59", 12, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x336b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x336b8, 0 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3", 0x336bc, 0 },
+ { "FTIMEOUT", 15, 1 },
+ { "FROTCAL4", 14, 1 },
+ { "FDCD2", 13, 1 },
+ { "FPRBSPOLTOG", 12, 1 },
+ { "FPRBSOFF2", 11, 1 },
+ { "FDDCAL2", 10, 1 },
+ { "FDDCFLTR", 9, 1 },
+ { "FDAC6", 8, 1 },
+ { "FDDC5", 7, 1 },
+ { "FDDC3456", 6, 1 },
+ { "FSPY2DATA", 5, 1 },
+ { "FPHSLOCK", 4, 1 },
+ { "FCLKALGN", 3, 1 },
+ { "FCLKALDYN", 2, 1 },
+ { "FDFE", 1, 1 },
+ { "FPRBSOFF", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_TAP_CONTROL", 0x336c0, 0 },
+ { "MAC_PORT_RX_LINKC_DFE_TAP", 0x336c4, 0 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2", 0x336e4, 0 },
+ { "STNDBYSTAT", 15, 1 },
+ { "CALSDONE", 14, 1 },
+ { "ACISRCCMP", 5, 1 },
+ { "PRBSOFFCMP", 4, 1 },
+ { "CLKALGNCMP", 3, 1 },
+ { "ROTFCMP", 2, 1 },
+ { "DCDCMP", 1, 1 },
+ { "QCCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x336e8, 0 },
+ { "FCSADJ", 6, 1 },
+ { "CSIND", 3, 2 },
+ { "CSVAL", 0, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL", 0x336ec, 0 },
+ { "DCDTMDOUT", 15, 1 },
+ { "DCDTOEN", 14, 1 },
+ { "DCDLOCK", 13, 1 },
+ { "DCDSTEP", 11, 2 },
+ { "DCDALTWPDIS", 10, 1 },
+ { "DCDOVRDEN", 9, 1 },
+ { "DCCAOVRDEN", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL", 0x336f0, 0 },
+ { "PRBSMODE", 14, 2 },
+ { "DCCSTEP", 10, 2 },
+ { "DCCOVRDEN", 9, 1 },
+ { "DCCLOCK", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL", 0x336f4, 0 },
+ { "DCCQCCMODE", 15, 1 },
+ { "DCCQCCDYN", 14, 1 },
+ { "DCCQCCHOLD", 13, 1 },
+ { "QCCSTEP", 10, 2 },
+ { "QCCOVRDEN", 9, 1 },
+ { "QCCLOCK", 8, 1 },
+ { "QCCSIGN", 6, 2 },
+ { "QCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x336f8, 0 },
+ { "TSTCMP", 15, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x336fc, 0 },
+ { "CALMODEEDGE", 14, 1 },
+ { "TESTCAP", 13, 1 },
+ { "SNAPEN", 12, 1 },
+ { "ASYNCDIR", 11, 1 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x33700, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_MODE8023AZ", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x33704, 0 },
+ { "APLYDCD", 15, 1 },
+ { "PPOL", 13, 2 },
+ { "PCLKSEL", 11, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x33708, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3370c, 0 },
+ { "H1ANOFST", 12, 4 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "TMSCAL", 8, 2 },
+ { "APADJ", 7, 1 },
+ { "RSEL", 6, 1 },
+ { "PHOFFS", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x33710, 0 },
+ { "ROTA", 8, 6 },
+ { "ROTD", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x33714, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROTE", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33718, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOFFF", 8, 4 },
+ { "RAOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3371c, 0 },
+ { "RCALER", 15, 1 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x33720, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 8, 4 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x33724, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x33728, 0 },
+ { "REQWOV", 15, 1 },
+ { "RASEL", 11, 3 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3372c, 0 },
+ { "WRAPSEL", 15, 1 },
+ { "ACTL", 14, 1 },
+ { "PEAK", 9, 5 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x33730, 0 },
+ { "FVOFFSKP", 15, 1 },
+ { "FGAINCHK", 14, 1 },
+ { "FH1ACAL", 13, 1 },
+ { "FH1AFLTR", 11, 2 },
+ { "T5SHORTV", 10, 1 },
+ { "WGAIN", 8, 2 },
+ { "GAIN_STAT", 7, 1 },
+ { "T5VGAIN", 0, 7 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x33734, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33738, 0 },
+ { "PMCFG", 6, 2 },
+ { "PMOFFTIME", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1", 0x3373c, 0 },
+ { "SELI", 9, 1 },
+ { "SERVREF", 5, 3 },
+ { "IQAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2", 0x33740, 0 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33744, 0 },
+ { "SAVEADAC", 8, 1 },
+ { "LOAD2", 7, 1 },
+ { "LOAD1", 6, 1 },
+ { "WRTACC2", 5, 1 },
+ { "WRTACC1", 4, 1 },
+ { "SELAPAN", 3, 1 },
+ { "DASEL", 0, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x33748, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN", 0x3374c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x33750, 0 },
+ { "ADAC2", 8, 8 },
+ { "ADAC1", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL", 0x33754, 0 },
+ { "FACCPLDYN", 13, 1 },
+ { "ACCPLGAIN", 10, 3 },
+ { "ACCPLREF", 8, 2 },
+ { "ACCPLSTEP", 6, 2 },
+ { "ACCPLASTEP", 1, 5 },
+ { "FACCPL", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE", 0x33758, 0 },
+ { "ACCPLMEANS", 15, 1 },
+ { "CDROVREN", 8, 1 },
+ { "ACCPLBIAS", 0, 8 },
+ { "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET", 0x3375c, 0 },
+ { "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33760, 0 },
+ { "H1OX", 8, 6 },
+ { "H1EX", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR", 0x33764, 0 },
+ { "PILOCK", 10, 1 },
+ { "UNPKPKA", 2, 6 },
+ { "UNPKVGA", 0, 2 },
+ { "MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH", 0x33768, 0 },
+ { "OVRAC", 15, 1 },
+ { "OVRPK", 14, 1 },
+ { "OVRTAILS", 12, 2 },
+ { "OVRTAILV", 9, 3 },
+ { "OVRCAP", 8, 1 },
+ { "OVRDCDPRE", 7, 1 },
+ { "OVRDCDPST", 6, 1 },
+ { "DCVSCTMODE", 2, 1 },
+ { "CDRANLGSW", 0, 2 },
+ { "MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3376c, 0 },
+ { "PFLAG", 5, 2 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33770, 0 },
+ { "DACCLIP", 15, 1 },
+ { "DPCFRZ", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCLKNQ", 11, 1 },
+ { "DPCWDFE", 10, 1 },
+ { "DPCWPK", 9, 1 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x33774, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "VIEWSCAN", 4, 1 },
+ { "ODEC", 0, 4 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x33778, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "ACCCMP", 11, 1 },
+ { "DCCCMP", 10, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5IQCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3377c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x33780, 0 },
+ { "H25SPC", 15, 1 },
+ { "FDCCAL", 14, 1 },
+ { "FROTCAL", 13, 1 },
+ { "FIQAMP", 12, 1 },
+ { "FRPTCALF", 11, 1 },
+ { "FINTCALGS", 10, 1 },
+ { "FDCC", 9, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FDCD", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FINTRCALDYN", 1, 1 },
+ { "FQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL", 0x33784, 0 },
+ { "QCCIND", 13, 1 },
+ { "DCDIND", 10, 3 },
+ { "DCCIND", 8, 2 },
+ { "CFSEL", 5, 1 },
+ { "LOFCH", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE", 0x33788, 0 },
+ { "LOFU", 8, 7 },
+ { "LOFL", 0, 7 },
+ { "MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST", 0x3378c, 0 },
+ { "HBISTMAN", 12, 1 },
+ { "HBISTRES", 11, 1 },
+ { "HBISTSP", 8, 3 },
+ { "HBISTEN", 7, 1 },
+ { "HBISTRST", 6, 1 },
+ { "HCOMP", 5, 1 },
+ { "HPASS", 4, 1 },
+ { "HSEL", 0, 4 },
+ { "MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST", 0x33790, 0 },
+ { "ACCCMP", 13, 1 },
+ { "ACCEN", 12, 1 },
+ { "ACCRST", 11, 1 },
+ { "ACCIND", 8, 3 },
+ { "ACCRD", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER", 0x33798, 0 },
+ { "LFREG", 15, 1 },
+ { "LFRC", 14, 1 },
+ { "LGIDLE", 13, 1 },
+ { "LFTGT", 8, 5 },
+ { "LGTGT", 7, 1 },
+ { "LRDY", 6, 1 },
+ { "LIDLE", 5, 1 },
+ { "LCURR", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3379c, 0 },
+ { "OFFSN", 13, 2 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x337a0, 0 },
+ { "RX_OVRSUMPD", 15, 1 },
+ { "RX_OVRKBPD", 14, 1 },
+ { "RX_OVRDIVPD", 13, 1 },
+ { "RX_OFFVGADIS", 12, 1 },
+ { "RX_OFFACDIS", 11, 1 },
+ { "RX_VTERM", 10, 1 },
+ { "RX_DISSPY2D", 8, 1 },
+ { "RX_OBSOVEN", 7, 1 },
+ { "RX_LINKANLGSW", 0, 7 },
+ { "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x337a4, 0 },
+ { "INTDACEGS", 13, 3 },
+ { "INTDACE", 8, 5 },
+ { "INTDACGS", 6, 2 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x337a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x337ac, 0 },
+ { "SMQM", 13, 3 },
+ { "SMQ", 5, 8 },
+ { "EMMD", 3, 2 },
+ { "EMBRDY", 2, 1 },
+ { "EMBUMP", 1, 1 },
+ { "EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x337b0, 0 },
+ { "EMSF", 13, 1 },
+ { "EMDATA59", 12, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x337b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x337b8, 0 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3", 0x337bc, 0 },
+ { "FTIMEOUT", 15, 1 },
+ { "FROTCAL4", 14, 1 },
+ { "FDCD2", 13, 1 },
+ { "FPRBSPOLTOG", 12, 1 },
+ { "FPRBSOFF2", 11, 1 },
+ { "FDDCAL2", 10, 1 },
+ { "FDDCFLTR", 9, 1 },
+ { "FDAC6", 8, 1 },
+ { "FDDC5", 7, 1 },
+ { "FDDC3456", 6, 1 },
+ { "FSPY2DATA", 5, 1 },
+ { "FPHSLOCK", 4, 1 },
+ { "FCLKALGN", 3, 1 },
+ { "FCLKALDYN", 2, 1 },
+ { "FDFE", 1, 1 },
+ { "FPRBSOFF", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_TAP_CONTROL", 0x337c0, 0 },
+ { "MAC_PORT_RX_LINKD_DFE_TAP", 0x337c4, 0 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2", 0x337e4, 0 },
+ { "STNDBYSTAT", 15, 1 },
+ { "CALSDONE", 14, 1 },
+ { "ACISRCCMP", 5, 1 },
+ { "PRBSOFFCMP", 4, 1 },
+ { "CLKALGNCMP", 3, 1 },
+ { "ROTFCMP", 2, 1 },
+ { "DCDCMP", 1, 1 },
+ { "QCCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x337e8, 0 },
+ { "FCSADJ", 6, 1 },
+ { "CSIND", 3, 2 },
+ { "CSVAL", 0, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL", 0x337ec, 0 },
+ { "DCDTMDOUT", 15, 1 },
+ { "DCDTOEN", 14, 1 },
+ { "DCDLOCK", 13, 1 },
+ { "DCDSTEP", 11, 2 },
+ { "DCDALTWPDIS", 10, 1 },
+ { "DCDOVRDEN", 9, 1 },
+ { "DCCAOVRDEN", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL", 0x337f0, 0 },
+ { "PRBSMODE", 14, 2 },
+ { "DCCSTEP", 10, 2 },
+ { "DCCOVRDEN", 9, 1 },
+ { "DCCLOCK", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL", 0x337f4, 0 },
+ { "DCCQCCMODE", 15, 1 },
+ { "DCCQCCDYN", 14, 1 },
+ { "DCCQCCHOLD", 13, 1 },
+ { "QCCSTEP", 10, 2 },
+ { "QCCOVRDEN", 9, 1 },
+ { "QCCLOCK", 8, 1 },
+ { "QCCSIGN", 6, 2 },
+ { "QCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x337f8, 0 },
+ { "TSTCMP", 15, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x337fc, 0 },
+ { "CALMODEEDGE", 14, 1 },
+ { "TESTCAP", 13, 1 },
+ { "SNAPEN", 12, 1 },
+ { "ASYNCDIR", 11, 1 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x33a00, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_MODE8023AZ", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x33a04, 0 },
+ { "APLYDCD", 15, 1 },
+ { "PPOL", 13, 2 },
+ { "PCLKSEL", 11, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x33a08, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x33a0c, 0 },
+ { "H1ANOFST", 12, 4 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "TMSCAL", 8, 2 },
+ { "APADJ", 7, 1 },
+ { "RSEL", 6, 1 },
+ { "PHOFFS", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x33a10, 0 },
+ { "ROTA", 8, 6 },
+ { "ROTD", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x33a14, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROTE", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33a18, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOFFF", 8, 4 },
+ { "RAOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x33a1c, 0 },
+ { "RCALER", 15, 1 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x33a20, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 8, 4 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x33a24, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x33a28, 0 },
+ { "REQWOV", 15, 1 },
+ { "RASEL", 11, 3 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x33a2c, 0 },
+ { "WRAPSEL", 15, 1 },
+ { "ACTL", 14, 1 },
+ { "PEAK", 9, 5 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x33a30, 0 },
+ { "FVOFFSKP", 15, 1 },
+ { "FGAINCHK", 14, 1 },
+ { "FH1ACAL", 13, 1 },
+ { "FH1AFLTR", 11, 2 },
+ { "T5SHORTV", 10, 1 },
+ { "WGAIN", 8, 2 },
+ { "GAIN_STAT", 7, 1 },
+ { "T5VGAIN", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x33a34, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x33a38, 0 },
+ { "PMCFG", 6, 2 },
+ { "PMOFFTIME", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1", 0x33a3c, 0 },
+ { "SELI", 9, 1 },
+ { "SERVREF", 5, 3 },
+ { "IQAMP", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2", 0x33a40, 0 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x33a44, 0 },
+ { "SAVEADAC", 8, 1 },
+ { "LOAD2", 7, 1 },
+ { "LOAD1", 6, 1 },
+ { "WRTACC2", 5, 1 },
+ { "WRTACC1", 4, 1 },
+ { "SELAPAN", 3, 1 },
+ { "DASEL", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x33a48, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN", 0x33a4c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x33a50, 0 },
+ { "ADAC2", 8, 8 },
+ { "ADAC1", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL", 0x33a54, 0 },
+ { "FACCPLDYN", 13, 1 },
+ { "ACCPLGAIN", 10, 3 },
+ { "ACCPLREF", 8, 2 },
+ { "ACCPLSTEP", 6, 2 },
+ { "ACCPLASTEP", 1, 5 },
+ { "FACCPL", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE", 0x33a58, 0 },
+ { "ACCPLMEANS", 15, 1 },
+ { "CDROVREN", 8, 1 },
+ { "ACCPLBIAS", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET", 0x33a5c, 0 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x33a60, 0 },
+ { "H1OX", 8, 6 },
+ { "H1EX", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR", 0x33a64, 0 },
+ { "PILOCK", 10, 1 },
+ { "UNPKPKA", 2, 6 },
+ { "UNPKVGA", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH", 0x33a68, 0 },
+ { "OVRAC", 15, 1 },
+ { "OVRPK", 14, 1 },
+ { "OVRTAILS", 12, 2 },
+ { "OVRTAILV", 9, 3 },
+ { "OVRCAP", 8, 1 },
+ { "OVRDCDPRE", 7, 1 },
+ { "OVRDCDPST", 6, 1 },
+ { "DCVSCTMODE", 2, 1 },
+ { "CDRANLGSW", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x33a6c, 0 },
+ { "PFLAG", 5, 2 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33a70, 0 },
+ { "DACCLIP", 15, 1 },
+ { "DPCFRZ", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCLKNQ", 11, 1 },
+ { "DPCWDFE", 10, 1 },
+ { "DPCWPK", 9, 1 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x33a74, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "VIEWSCAN", 4, 1 },
+ { "ODEC", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x33a78, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "ACCCMP", 11, 1 },
+ { "DCCCMP", 10, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5IQCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x33a7c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x33a80, 0 },
+ { "H25SPC", 15, 1 },
+ { "FDCCAL", 14, 1 },
+ { "FROTCAL", 13, 1 },
+ { "FIQAMP", 12, 1 },
+ { "FRPTCALF", 11, 1 },
+ { "FINTCALGS", 10, 1 },
+ { "FDCC", 9, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FDCD", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FINTRCALDYN", 1, 1 },
+ { "FQCC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL", 0x33a84, 0 },
+ { "QCCIND", 13, 1 },
+ { "DCDIND", 10, 3 },
+ { "DCCIND", 8, 2 },
+ { "CFSEL", 5, 1 },
+ { "LOFCH", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE", 0x33a88, 0 },
+ { "LOFU", 8, 7 },
+ { "LOFL", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST", 0x33a8c, 0 },
+ { "HBISTMAN", 12, 1 },
+ { "HBISTRES", 11, 1 },
+ { "HBISTSP", 8, 3 },
+ { "HBISTEN", 7, 1 },
+ { "HBISTRST", 6, 1 },
+ { "HCOMP", 5, 1 },
+ { "HPASS", 4, 1 },
+ { "HSEL", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST", 0x33a90, 0 },
+ { "ACCCMP", 13, 1 },
+ { "ACCEN", 12, 1 },
+ { "ACCRST", 11, 1 },
+ { "ACCIND", 8, 3 },
+ { "ACCRD", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER", 0x33a98, 0 },
+ { "LFREG", 15, 1 },
+ { "LFRC", 14, 1 },
+ { "LGIDLE", 13, 1 },
+ { "LFTGT", 8, 5 },
+ { "LGTGT", 7, 1 },
+ { "LRDY", 6, 1 },
+ { "LIDLE", 5, 1 },
+ { "LCURR", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x33a9c, 0 },
+ { "OFFSN", 13, 2 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x33aa0, 0 },
+ { "RX_OVRSUMPD", 15, 1 },
+ { "RX_OVRKBPD", 14, 1 },
+ { "RX_OVRDIVPD", 13, 1 },
+ { "RX_OFFVGADIS", 12, 1 },
+ { "RX_OFFACDIS", 11, 1 },
+ { "RX_VTERM", 10, 1 },
+ { "RX_DISSPY2D", 8, 1 },
+ { "RX_OBSOVEN", 7, 1 },
+ { "RX_LINKANLGSW", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x33aa4, 0 },
+ { "INTDACEGS", 13, 3 },
+ { "INTDACE", 8, 5 },
+ { "INTDACGS", 6, 2 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x33aa8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x33aac, 0 },
+ { "SMQM", 13, 3 },
+ { "SMQ", 5, 8 },
+ { "EMMD", 3, 2 },
+ { "EMBRDY", 2, 1 },
+ { "EMBUMP", 1, 1 },
+ { "EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x33ab0, 0 },
+ { "EMSF", 13, 1 },
+ { "EMDATA59", 12, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x33ab4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x33ab8, 0 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3", 0x33abc, 0 },
+ { "FTIMEOUT", 15, 1 },
+ { "FROTCAL4", 14, 1 },
+ { "FDCD2", 13, 1 },
+ { "FPRBSPOLTOG", 12, 1 },
+ { "FPRBSOFF2", 11, 1 },
+ { "FDDCAL2", 10, 1 },
+ { "FDDCFLTR", 9, 1 },
+ { "FDAC6", 8, 1 },
+ { "FDDC5", 7, 1 },
+ { "FDDC3456", 6, 1 },
+ { "FSPY2DATA", 5, 1 },
+ { "FPHSLOCK", 4, 1 },
+ { "FCLKALGN", 3, 1 },
+ { "FCLKALDYN", 2, 1 },
+ { "FDFE", 1, 1 },
+ { "FPRBSOFF", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL", 0x33ac0, 0 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_TAP", 0x33ac4, 0 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2", 0x33ae4, 0 },
+ { "STNDBYSTAT", 15, 1 },
+ { "CALSDONE", 14, 1 },
+ { "ACISRCCMP", 5, 1 },
+ { "PRBSOFFCMP", 4, 1 },
+ { "CLKALGNCMP", 3, 1 },
+ { "ROTFCMP", 2, 1 },
+ { "DCDCMP", 1, 1 },
+ { "QCCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x33ae8, 0 },
+ { "FCSADJ", 6, 1 },
+ { "CSIND", 3, 2 },
+ { "CSVAL", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL", 0x33aec, 0 },
+ { "DCDTMDOUT", 15, 1 },
+ { "DCDTOEN", 14, 1 },
+ { "DCDLOCK", 13, 1 },
+ { "DCDSTEP", 11, 2 },
+ { "DCDALTWPDIS", 10, 1 },
+ { "DCDOVRDEN", 9, 1 },
+ { "DCCAOVRDEN", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL", 0x33af0, 0 },
+ { "PRBSMODE", 14, 2 },
+ { "DCCSTEP", 10, 2 },
+ { "DCCOVRDEN", 9, 1 },
+ { "DCCLOCK", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL", 0x33af4, 0 },
+ { "DCCQCCMODE", 15, 1 },
+ { "DCCQCCDYN", 14, 1 },
+ { "DCCQCCHOLD", 13, 1 },
+ { "QCCSTEP", 10, 2 },
+ { "QCCOVRDEN", 9, 1 },
+ { "QCCLOCK", 8, 1 },
+ { "QCCSIGN", 6, 2 },
+ { "QCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x33af8, 0 },
+ { "TSTCMP", 15, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x33afc, 0 },
+ { "CALMODEEDGE", 14, 1 },
+ { "TESTCAP", 13, 1 },
+ { "SNAPEN", 12, 1 },
+ { "ASYNCDIR", 11, 1 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_CFG", 0x34800, 0 },
+ { "MAC_Clk_Sel", 29, 3 },
+ { "Ena_err_rsp", 28, 1 },
+ { "SinkTx", 27, 1 },
+ { "SinkTxOnLinkDown", 26, 1 },
+ { "debug_clr", 25, 1 },
+ { "LoopNoFwd", 24, 1 },
+ { "pll_sel", 23, 1 },
+ { "port_map", 20, 3 },
+ { "Smux_Rx_Loop", 19, 1 },
+ { "Rx_Lane_Swap", 18, 1 },
+ { "Tx_Lane_Swap", 17, 1 },
+ { "Aec_pat_data", 15, 1 },
+ { "Signal_Det", 14, 1 },
+ { "macclk_sel", 13, 1 },
+ { "xgmii_sel", 12, 1 },
+ { "debug_port_sel", 10, 2 },
+ { "SmuxTxSel", 9, 1 },
+ { "SmuxRxSel", 8, 1 },
+ { "Enable_25G", 7, 1 },
+ { "Enable_50G", 6, 1 },
+ { "PortSpeed", 4, 2 },
+ { "Rx_Byte_Swap", 3, 1 },
+ { "Tx_Byte_Swap", 2, 1 },
+ { "debug_tx_rx_sel", 1, 1 },
+ { "Port_Sel", 0, 1 },
+ { "MAC_PORT_RESET_CTRL", 0x34804, 0 },
+ { "TWGDSK_HSSC16B", 31, 1 },
+ { "EEE_RESET", 30, 1 },
+ { "PTP_TIMER", 29, 1 },
+ { "MtipRefReset", 28, 1 },
+ { "MAC100G40G_RESET", 27, 1 },
+ { "MAC10G1G_RESET", 26, 1 },
+ { "MtipRegReset", 25, 1 },
+ { "PCS1G_RESET", 24, 1 },
+ { "AEC3Reset", 23, 1 },
+ { "AEC2Reset", 22, 1 },
+ { "AEC1Reset", 21, 1 },
+ { "AEC0Reset", 20, 1 },
+ { "AET3Reset", 19, 1 },
+ { "AET2Reset", 18, 1 },
+ { "AET1Reset", 17, 1 },
+ { "AET0Reset", 16, 1 },
+ { "PCS10G_RESET", 15, 1 },
+ { "PCS40G_RESET", 14, 1 },
+ { "PCS100G_RESET", 13, 1 },
+ { "TXIF_Reset", 12, 1 },
+ { "RXIF_Reset", 11, 1 },
+ { "AuxExt_Reset", 10, 1 },
+ { "MtipSd3TxRst", 9, 1 },
+ { "MtipSd2TxRst", 8, 1 },
+ { "MtipSd1TxRst", 7, 1 },
+ { "MtipSd0TxRst", 6, 1 },
+ { "MtipSd3RxRst", 5, 1 },
+ { "MtipSd2RxRst", 4, 1 },
+ { "MtipSd1RxRst", 3, 1 },
+ { "WOL_Reset", 2, 1 },
+ { "MtipSd0RxRst", 1, 1 },
+ { "HSS_Reset", 0, 1 },
+ { "MAC_PORT_LED_CFG", 0x34808, 0 },
+ { "Led1_Cfg1", 14, 2 },
+ { "Led0_Cfg1", 12, 2 },
+ { "Led1_tlo", 11, 1 },
+ { "Led1_thi", 10, 1 },
+ { "Led0_tlo", 9, 1 },
+ { "Led0_thi", 8, 1 },
+ { "Led1_Cfg", 5, 3 },
+ { "Led1_Polarity_Inv", 4, 1 },
+ { "Led0_Cfg", 1, 3 },
+ { "Led0_Polarity_Inv", 0, 1 },
+ { "MAC_PORT_LED_COUNTHI", 0x3480c, 0 },
+ { "MAC_PORT_LED_COUNTLO", 0x34810, 0 },
+ { "MAC_PORT_CFG3", 0x34814, 0 },
+ { "REF_Clk_Sel", 30, 2 },
+ { "sgmii_sd_sig_det", 29, 1 },
+ { "sgmii_sgpcs_ena", 28, 1 },
+ { "FPGA_PTP_PORT", 26, 2 },
+ { "FCSDisCtrl", 25, 1 },
+ { "SigDetCtrl", 24, 1 },
+ { "tx_lane", 23, 1 },
+ { "rx_lane", 22, 1 },
+ { "se_clr", 21, 1 },
+ { "an_ena", 17, 4 },
+ { "sd_rx_clk_ena", 13, 4 },
+ { "sd_tx_clk_ena", 9, 4 },
+ { "SGMIISEL", 8, 1 },
+ { "HSSPLLSEL", 4, 4 },
+ { "HSSC16C20SEL", 0, 4 },
+ { "MAC_PORT_CFG2", 0x34818, 0 },
+ { "Rx_Polarity_Inv", 28, 4 },
+ { "Tx_Polarity_Inv", 24, 4 },
+ { "InstanceNum", 22, 2 },
+ { "StopOnPerr", 21, 1 },
+ { "an_data_ctl", 19, 1 },
+ { "PatEn", 18, 1 },
+ { "MagicEn", 17, 1 },
+ { "T5_AEC_PMA_TX_READY", 4, 4 },
+ { "T5_AEC_PMA_RX_READY", 0, 4 },
+ { "MAC_PORT_PKT_COUNT", 0x3481c, 0 },
+ { "tx_sop_count", 24, 8 },
+ { "tx_eop_count", 16, 8 },
+ { "rx_sop_count", 8, 8 },
+ { "rx_eop_count", 0, 8 },
+ { "MAC_PORT_CFG4", 0x34820, 0 },
+ { "AEC3_RX_WIDTH", 14, 2 },
+ { "AEC2_RX_WIDTH", 12, 2 },
+ { "AEC1_RX_WIDTH", 10, 2 },
+ { "AEC0_RX_WIDTH", 8, 2 },
+ { "AEC3_TX_WIDTH", 6, 2 },
+ { "AEC2_TX_WIDTH", 4, 2 },
+ { "AEC1_TX_WIDTH", 2, 2 },
+ { "AEC0_TX_WIDTH", 0, 2 },
+ { "MAC_PORT_MAGIC_MACID_LO", 0x34824, 0 },
+ { "MAC_PORT_MAGIC_MACID_HI", 0x34828, 0 },
+ { "MAC_PORT_MTIP_RESET_CTRL", 0x3482c, 0 },
+ { "an_reset_sd_tx_clk", 31, 1 },
+ { "an_reset_sd_rx_clk", 30, 1 },
+ { "sgmii_reset_tx_clk", 29, 1 },
+ { "sgmii_reset_rx_clk", 28, 1 },
+ { "sgmii_reset_ref_clk", 27, 1 },
+ { "pcs10g_reset_xfi_rxclk", 26, 1 },
+ { "pcs10g_reset_xfi_txclk", 25, 1 },
+ { "pcs10g_reset_sd_tx_clk", 24, 1 },
+ { "pcs10g_reset_sd_rx_clk", 23, 1 },
+ { "pcs40g_reset_rxclk", 22, 1 },
+ { "pcs40g_reset_sd_tx_clk", 21, 1 },
+ { "pcs40g_reset_sd0_rx_clk", 20, 1 },
+ { "pcs40g_reset_sd1_rx_clk", 19, 1 },
+ { "pcs40g_reset_sd2_rx_clk", 18, 1 },
+ { "pcs40g_reset_sd3_rx_clk", 17, 1 },
+ { "pcs100g_reset_cgmii_rxclk", 16, 1 },
+ { "pcs100g_reset_cgmii_txclk", 15, 1 },
+ { "pcs100g_reset_tx_clk", 14, 1 },
+ { "pcs100g_reset_sd0_rx_clk", 13, 1 },
+ { "pcs100g_reset_sd1_rx_clk", 12, 1 },
+ { "pcs100g_reset_sd2_rx_clk", 11, 1 },
+ { "pcs100g_reset_sd3_rx_clk", 10, 1 },
+ { "mac40g100g_reset_txclk", 9, 1 },
+ { "mac40g100g_reset_rxclk", 8, 1 },
+ { "mac40g100g_reset_ff_tx_clk", 7, 1 },
+ { "mac40g100g_reset_ff_rx_clk", 6, 1 },
+ { "mac40g100g_reset_ts_clk", 5, 1 },
+ { "mac1g10g_reset_rxclk", 4, 1 },
+ { "mac1g10g_reset_txclk", 3, 1 },
+ { "mac1g10g_reset_ff_rx_clk", 2, 1 },
+ { "mac1g10g_reset_ff_tx_clk", 1, 1 },
+ { "xgmii_clk_reset", 0, 1 },
+ { "MAC_PORT_MTIP_GATE_CTRL", 0x34830, 0 },
+ { "an_gate_sd_tx_clk", 31, 1 },
+ { "an_gate_sd_rx_clk", 30, 1 },
+ { "sgmii_gate_tx_clk", 29, 1 },
+ { "sgmii_gate_rx_clk", 28, 1 },
+ { "sgmii_gate_ref_clk", 27, 1 },
+ { "pcs10g_gate_xfi_rxclk", 26, 1 },
+ { "pcs10g_gate_xfi_txclk", 25, 1 },
+ { "pcs10g_gate_sd_tx_clk", 24, 1 },
+ { "pcs10g_gate_sd_rx_clk", 23, 1 },
+ { "pcs40g_gate_rxclk", 22, 1 },
+ { "pcs40g_gate_sd_tx_clk", 21, 1 },
+ { "pcs40g_gate_sd_rx_clk", 20, 1 },
+ { "pcs100g_gate_cgmii_rxclk", 19, 1 },
+ { "pcs100g_gate_cgmii_txclk", 18, 1 },
+ { "pcs100g_gate_tx_clk", 17, 1 },
+ { "pcs100g_gate_sd_rx_clk", 16, 1 },
+ { "mac40g100g_gate_txclk", 15, 1 },
+ { "mac40g100g_gate_rxclk", 14, 1 },
+ { "mac40g100g_gate_ff_tx_clk", 13, 1 },
+ { "mac40g100g_gate_ff_rx_clk", 12, 1 },
+ { "mac40g100g_ts_clk", 11, 1 },
+ { "mac1g10g_gate_rxclk", 10, 1 },
+ { "mac1g10g_gate_txclk", 9, 1 },
+ { "mac1g10g_gate_ff_rx_clk", 8, 1 },
+ { "mac1g10g_gate_ff_tx_clk", 7, 1 },
+ { "aec_rx", 6, 1 },
+ { "aec_tx", 5, 1 },
+ { "pcs100g_clk_enable", 4, 1 },
+ { "pcs40g_clk_enable", 3, 1 },
+ { "pcs10g_clk_enable", 2, 1 },
+ { "pcs1g_clk_enable", 1, 1 },
+ { "an_clk_enable", 0, 1 },
+ { "MAC_PORT_LINK_STATUS", 0x34834, 0 },
+ { "hi_ber", 7, 1 },
+ { "an_done", 6, 1 },
+ { "align_done", 5, 1 },
+ { "block_lock", 4, 1 },
+ { "remflt", 3, 1 },
+ { "locflt", 2, 1 },
+ { "linkup", 1, 1 },
+ { "linkdn", 0, 1 },
+ { "MAC_PORT_AEC_ADD_CTL_STAT_0", 0x34838, 0 },
+ { "AEC_SYS_LANE_TYPE_3", 11, 1 },
+ { "AEC_SYS_LANE_TYPE_2", 10, 1 },
+ { "AEC_SYS_LANE_TYPE_1", 9, 1 },
+ { "AEC_SYS_LANE_TYPE_0", 8, 1 },
+ { "AEC_SYS_LANE_SELECT_3", 6, 2 },
+ { "AEC_SYS_LANE_SELECT_2", 4, 2 },
+ { "AEC_SYS_LANE_SELECT_1", 2, 2 },
+ { "AEC_SYS_LANE_SELECT_O", 0, 2 },
+ { "MAC_PORT_AEC_ADD_CTL_STAT_1", 0x3483c, 0 },
+ { "AEC_RX_UNKNOWN_LANE_3", 11, 1 },
+ { "AEC_RX_UNKNOWN_LANE_2", 10, 1 },
+ { "AEC_RX_UNKNOWN_LANE_1", 9, 1 },
+ { "AEC_RX_UNKNOWN_LANE_0", 8, 1 },
+ { "AEC_RX_LANE_ID_3", 6, 2 },
+ { "AEC_RX_LANE_ID_2", 4, 2 },
+ { "AEC_RX_LANE_ID_1", 2, 2 },
+ { "AEC_RX_LANE_ID_O", 0, 2 },
+ { "MAC_PORT_AEC_XGMII_TIMER_LO_40G", 0x34840, 0 },
+ { "MAC_PORT_AEC_XGMII_TIMER_HI_40G", 0x34844, 0 },
+ { "MAC_PORT_AEC_XGMII_TIMER_LO_100G", 0x34848, 0 },
+ { "MAC_PORT_AEC_XGMII_TIMER_HI_100G", 0x3484c, 0 },
+ { "MAC_PORT_AEC_DEBUG_LO_0", 0x34850, 0 },
+ { "CTL_FSM_CUR_STATE", 28, 3 },
+ { "CIN_FSM_CUR_STATE", 26, 2 },
+ { "CRI_FSM_CUR_STATE", 23, 3 },
+ { "CU_C3_ACK_VALUE", 21, 2 },
+ { "CU_C2_ACK_VALUE", 19, 2 },
+ { "CU_C1_ACK_VALUE", 17, 2 },
+ { "CU_C0_ACK_VALUE", 15, 2 },
+ { "CX_INIT", 13, 1 },
+ { "CX_PRESET", 12, 1 },
+ { "CUF_C3_UPDATE", 9, 2 },
+ { "CUF_C2_UPDATE", 7, 2 },
+ { "CUF_C1_UPDATE", 5, 2 },
+ { "CUF_C0_UPDATE", 3, 2 },
+ { "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
+ { "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
+ { "REG_MAN_DEC_REQ", 0, 1 },
+ { "MAC_PORT_AEC_DEBUG_HI_0", 0x34854, 0 },
+ { "FC_LSNA_", 12, 1 },
+ { "CUF_C0_FSM_DEBUG", 9, 3 },
+ { "CUF_C1_FSM_DEBUG", 6, 3 },
+ { "CUF_C2_FSM_DEBUG", 3, 3 },
+ { "LCK_FSM_CUR_STATE", 0, 3 },
+ { "MAC_PORT_AEC_DEBUG_LO_1", 0x34858, 0 },
+ { "CTL_FSM_CUR_STATE", 28, 3 },
+ { "CIN_FSM_CUR_STATE", 26, 2 },
+ { "CRI_FSM_CUR_STATE", 23, 3 },
+ { "CU_C3_ACK_VALUE", 21, 2 },
+ { "CU_C2_ACK_VALUE", 19, 2 },
+ { "CU_C1_ACK_VALUE", 17, 2 },
+ { "CU_C0_ACK_VALUE", 15, 2 },
+ { "CX_INIT", 13, 1 },
+ { "CX_PRESET", 12, 1 },
+ { "CUF_C3_UPDATE", 9, 2 },
+ { "CUF_C2_UPDATE", 7, 2 },
+ { "CUF_C1_UPDATE", 5, 2 },
+ { "CUF_C0_UPDATE", 3, 2 },
+ { "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
+ { "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
+ { "REG_MAN_DEC_REQ", 0, 1 },
+ { "MAC_PORT_AEC_DEBUG_HI_1", 0x3485c, 0 },
+ { "FC_LSNA_", 12, 1 },
+ { "CUF_C0_FSM_DEBUG", 9, 3 },
+ { "CUF_C1_FSM_DEBUG", 6, 3 },
+ { "CUF_C2_FSM_DEBUG", 3, 3 },
+ { "LCK_FSM_CUR_STATE", 0, 3 },
+ { "MAC_PORT_AEC_DEBUG_LO_2", 0x34860, 0 },
+ { "CTL_FSM_CUR_STATE", 28, 3 },
+ { "CIN_FSM_CUR_STATE", 26, 2 },
+ { "CRI_FSM_CUR_STATE", 23, 3 },
+ { "CU_C3_ACK_VALUE", 21, 2 },
+ { "CU_C2_ACK_VALUE", 19, 2 },
+ { "CU_C1_ACK_VALUE", 17, 2 },
+ { "CU_C0_ACK_VALUE", 15, 2 },
+ { "CX_INIT", 13, 1 },
+ { "CX_PRESET", 12, 1 },
+ { "CUF_C3_UPDATE", 9, 2 },
+ { "CUF_C2_UPDATE", 7, 2 },
+ { "CUF_C1_UPDATE", 5, 2 },
+ { "CUF_C0_UPDATE", 3, 2 },
+ { "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
+ { "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
+ { "REG_MAN_DEC_REQ", 0, 1 },
+ { "MAC_PORT_AEC_DEBUG_HI_2", 0x34864, 0 },
+ { "FC_LSNA_", 12, 1 },
+ { "CUF_C0_FSM_DEBUG", 9, 3 },
+ { "CUF_C1_FSM_DEBUG", 6, 3 },
+ { "CUF_C2_FSM_DEBUG", 3, 3 },
+ { "LCK_FSM_CUR_STATE", 0, 3 },
+ { "MAC_PORT_AEC_DEBUG_LO_3", 0x34868, 0 },
+ { "CTL_FSM_CUR_STATE", 28, 3 },
+ { "CIN_FSM_CUR_STATE", 26, 2 },
+ { "CRI_FSM_CUR_STATE", 23, 3 },
+ { "CU_C3_ACK_VALUE", 21, 2 },
+ { "CU_C2_ACK_VALUE", 19, 2 },
+ { "CU_C1_ACK_VALUE", 17, 2 },
+ { "CU_C0_ACK_VALUE", 15, 2 },
+ { "CX_INIT", 13, 1 },
+ { "CX_PRESET", 12, 1 },
+ { "CUF_C3_UPDATE", 9, 2 },
+ { "CUF_C2_UPDATE", 7, 2 },
+ { "CUF_C1_UPDATE", 5, 2 },
+ { "CUF_C0_UPDATE", 3, 2 },
+ { "REG_FPH_ATTR_TXUPDAT_VALID", 2, 1 },
+ { "REG_FPH_ATTR_TXSTAT_VALID", 1, 1 },
+ { "REG_MAN_DEC_REQ", 0, 1 },
+ { "MAC_PORT_AEC_DEBUG_HI_3", 0x3486c, 0 },
+ { "FC_LSNA_", 12, 1 },
+ { "CUF_C0_FSM_DEBUG", 9, 3 },
+ { "CUF_C1_FSM_DEBUG", 6, 3 },
+ { "CUF_C2_FSM_DEBUG", 3, 3 },
+ { "LCK_FSM_CUR_STATE", 0, 3 },
+ { "MAC_PORT_MAC_DEBUG_RO", 0x34870, 0 },
+ { "mac40g100g_tx_underflow", 13, 1 },
+ { "mac1g10g_magic_ind", 12, 1 },
+ { "mac1g10g_ff_rx_empty", 11, 1 },
+ { "mac1g10g_ff_tx_ovr_err", 10, 1 },
+ { "mac1g10g_if_mode_ena", 8, 2 },
+ { "mac1g10g_mii_ena_10", 7, 1 },
+ { "mac1g10g_pause_on", 6, 1 },
+ { "mac1g10g_pfc_mode", 5, 1 },
+ { "mac1g10g_rx_sfd_o", 4, 1 },
+ { "mac1g10g_tx_empty", 3, 1 },
+ { "mac1g10g_tx_sfd_o", 2, 1 },
+ { "mac1g10g_tx_ts_frm_out", 1, 1 },
+ { "mac1g10g_tx_underflow", 0, 1 },
+ { "MAC_PORT_MAC_CTRL_RW", 0x34874, 0 },
+ { "mac40g100g_ff_tx_pfc_xoff", 17, 8 },
+ { "mac40g100g_tx_loc_fault", 16, 1 },
+ { "mac40g100g_tx_rem_fault", 15, 1 },
+ { "mac40g_loop_bck", 14, 1 },
+ { "mac1g10g_magic_ena", 13, 1 },
+ { "mac1g10g_if_mode_set", 11, 2 },
+ { "mac1g10g_tx_loc_fault", 10, 1 },
+ { "mac1g10g_tx_rem_fault", 9, 1 },
+ { "mac1g10g_xoff_gen", 1, 8 },
+ { "mac1g_loop_bck", 0, 1 },
+ { "MAC_PORT_PCS_DEBUG0_RO", 0x34878, 0 },
+ { "fpga_lock", 26, 4 },
+ { "an_done", 25, 1 },
+ { "an_int", 24, 1 },
+ { "an_pcs_rx_clk_ena", 23, 1 },
+ { "an_pcs_tx_clk_ena", 22, 1 },
+ { "an_select", 17, 5 },
+ { "an_prog", 16, 1 },
+ { "pcs40g_block_lock", 12, 4 },
+ { "pcs40g_ber_timer_done", 11, 1 },
+ { "pcs10g_fec_locked", 10, 1 },
+ { "pcs10g_block_lock", 9, 1 },
+ { "sgmii_gmii_col", 8, 1 },
+ { "sgmii_gmii_crs", 7, 1 },
+ { "sgmii_sd_loopback", 6, 1 },
+ { "sgmii_sg_an_done", 5, 1 },
+ { "sgmii_sg_hd", 4, 1 },
+ { "sgmii_sg_page_rx", 3, 1 },
+ { "sgmii_sg_rx_sync", 2, 1 },
+ { "sgmii_sg_speed", 0, 2 },
+ { "MAC_PORT_PCS_CTRL_RW", 0x3487c, 0 },
+ { "tx_li_fault", 31, 1 },
+ { "pad", 30, 1 },
+ { "blk_stb_val", 22, 8 },
+ { "debug_sel", 18, 4 },
+ { "sgmii_loop", 15, 3 },
+ { "an_dis_timer", 14, 1 },
+ { "pcs100g_ber_timer_short", 13, 1 },
+ { "pcs100g_tx_lane_thresh", 9, 4 },
+ { "pcs100g_vl_intvl", 8, 1 },
+ { "sgmii_tx_lane_ckmult", 4, 3 },
+ { "sgmii_tx_lane_thresh", 0, 4 },
+ { "MAC_PORT_PCS_DEBUG1_RO", 0x34880, 0 },
+ { "pcs100g_align_lock", 21, 1 },
+ { "pcs100g_ber_timer_done", 20, 1 },
+ { "pcs100g_block_lock", 0, 20 },
+ { "MAC_PORT_PERR_INT_EN_100G", 0x34884, 0 },
+ { "Perr_rx_fec100g_dly", 29, 1 },
+ { "Perr_rx_fec100g", 28, 1 },
+ { "Perr_rx3_fec100g_dk", 27, 1 },
+ { "Perr_rx2_fec100g_dk", 26, 1 },
+ { "Perr_rx1_fec100g_dk", 25, 1 },
+ { "Perr_rx0_fec100g_dk", 24, 1 },
+ { "Perr_tx3_pcs100g", 23, 1 },
+ { "Perr_tx2_pcs100g", 22, 1 },
+ { "Perr_tx1_pcs100g", 21, 1 },
+ { "Perr_tx0_pcs100g", 20, 1 },
+ { "Perr_rx19_pcs100g", 19, 1 },
+ { "Perr_rx18_pcs100g", 18, 1 },
+ { "Perr_rx17_pcs100g", 17, 1 },
+ { "Perr_rx16_pcs100g", 16, 1 },
+ { "Perr_rx15_pcs100g", 15, 1 },
+ { "Perr_rx14_pcs100g", 14, 1 },
+ { "Perr_rx13_pcs100g", 13, 1 },
+ { "Perr_rx12_pcs100g", 12, 1 },
+ { "Perr_rx11_pcs100g", 11, 1 },
+ { "Perr_rx10_pcs100g", 10, 1 },
+ { "Perr_rx9_pcs100g", 9, 1 },
+ { "Perr_rx8_pcs100g", 8, 1 },
+ { "Perr_rx7_pcs100g", 7, 1 },
+ { "Perr_rx6_pcs100g", 6, 1 },
+ { "Perr_rx5_pcs100g", 5, 1 },
+ { "Perr_rx4_pcs100g", 4, 1 },
+ { "Perr_rx3_pcs100g", 3, 1 },
+ { "Perr_rx2_pcs100g", 2, 1 },
+ { "Perr_rx1_pcs100g", 1, 1 },
+ { "Perr_rx0_pcs100g", 0, 1 },
+ { "MAC_PORT_PERR_INT_CAUSE_100G", 0x34888, 0 },
+ { "Perr_rx_fec100g_dly", 29, 1 },
+ { "Perr_rx_fec100g", 28, 1 },
+ { "Perr_rx3_fec100g_dk", 27, 1 },
+ { "Perr_rx2_fec100g_dk", 26, 1 },
+ { "Perr_rx1_fec100g_dk", 25, 1 },
+ { "Perr_rx0_fec100g_dk", 24, 1 },
+ { "Perr_tx3_pcs100g", 23, 1 },
+ { "Perr_tx2_pcs100g", 22, 1 },
+ { "Perr_tx1_pcs100g", 21, 1 },
+ { "Perr_tx0_pcs100g", 20, 1 },
+ { "Perr_rx19_pcs100g", 19, 1 },
+ { "Perr_rx18_pcs100g", 18, 1 },
+ { "Perr_rx17_pcs100g", 17, 1 },
+ { "Perr_rx16_pcs100g", 16, 1 },
+ { "Perr_rx15_pcs100g", 15, 1 },
+ { "Perr_rx14_pcs100g", 14, 1 },
+ { "Perr_rx13_pcs100g", 13, 1 },
+ { "Perr_rx12_pcs100g", 12, 1 },
+ { "Perr_rx11_pcs100g", 11, 1 },
+ { "Perr_rx10_pcs100g", 10, 1 },
+ { "Perr_rx9_pcs100g", 9, 1 },
+ { "Perr_rx8_pcs100g", 8, 1 },
+ { "Perr_rx7_pcs100g", 7, 1 },
+ { "Perr_rx6_pcs100g", 6, 1 },
+ { "Perr_rx5_pcs100g", 5, 1 },
+ { "Perr_rx4_pcs100g", 4, 1 },
+ { "Perr_rx3_pcs100g", 3, 1 },
+ { "Perr_rx2_pcs100g", 2, 1 },
+ { "Perr_rx1_pcs100g", 1, 1 },
+ { "Perr_rx0_pcs100g", 0, 1 },
+ { "MAC_PORT_PERR_ENABLE_100G", 0x3488c, 0 },
+ { "Perr_rx_fec100g_dly", 29, 1 },
+ { "Perr_rx_fec100g", 28, 1 },
+ { "Perr_rx3_fec100g_dk", 27, 1 },
+ { "Perr_rx2_fec100g_dk", 26, 1 },
+ { "Perr_rx1_fec100g_dk", 25, 1 },
+ { "Perr_rx0_fec100g_dk", 24, 1 },
+ { "Perr_tx3_pcs100g", 23, 1 },
+ { "Perr_tx2_pcs100g", 22, 1 },
+ { "Perr_tx1_pcs100g", 21, 1 },
+ { "Perr_tx0_pcs100g", 20, 1 },
+ { "Perr_rx19_pcs100g", 19, 1 },
+ { "Perr_rx18_pcs100g", 18, 1 },
+ { "Perr_rx17_pcs100g", 17, 1 },
+ { "Perr_rx16_pcs100g", 16, 1 },
+ { "Perr_rx15_pcs100g", 15, 1 },
+ { "Perr_rx14_pcs100g", 14, 1 },
+ { "Perr_rx13_pcs100g", 13, 1 },
+ { "Perr_rx12_pcs100g", 12, 1 },
+ { "Perr_rx11_pcs100g", 11, 1 },
+ { "Perr_rx10_pcs100g", 10, 1 },
+ { "Perr_rx9_pcs100g", 9, 1 },
+ { "Perr_rx8_pcs100g", 8, 1 },
+ { "Perr_rx7_pcs100g", 7, 1 },
+ { "Perr_rx6_pcs100g", 6, 1 },
+ { "Perr_rx5_pcs100g", 5, 1 },
+ { "Perr_rx4_pcs100g", 4, 1 },
+ { "Perr_rx3_pcs100g", 3, 1 },
+ { "Perr_rx2_pcs100g", 2, 1 },
+ { "Perr_rx1_pcs100g", 1, 1 },
+ { "Perr_rx0_pcs100g", 0, 1 },
+ { "MAC_PORT_MAC_STAT_DEBUG", 0x34890, 0 },
+ { "MAC_PORT_MAC_25G_50G_AM0", 0x34894, 0 },
+ { "MAC_PORT_MAC_25G_50G_AM1", 0x34898, 0 },
+ { "MAC_PORT_MAC_25G_50G_AM2", 0x3489c, 0 },
+ { "MAC_PORT_MAC_25G_50G_AM3", 0x348a0, 0 },
+ { "MAC_PORT_MAC_AN_STATE_STATUS", 0x348a4, 0 },
+ { "MAC_PORT_EPIO_DATA0", 0x348c0, 0 },
+ { "MAC_PORT_EPIO_DATA1", 0x348c4, 0 },
+ { "MAC_PORT_EPIO_DATA2", 0x348c8, 0 },
+ { "MAC_PORT_EPIO_DATA3", 0x348cc, 0 },
+ { "MAC_PORT_EPIO_OP", 0x348d0, 0 },
+ { "Busy", 31, 1 },
+ { "Write", 8, 1 },
+ { "Address", 0, 8 },
+ { "MAC_PORT_WOL_STATUS", 0x348d4, 0 },
+ { "MagicDetected", 31, 1 },
+ { "PatDetected", 30, 1 },
+ { "ClearMagic", 4, 1 },
+ { "ClearMatch", 3, 1 },
+ { "MatchedFilter", 0, 3 },
+ { "MAC_PORT_INT_EN", 0x348d8, 0 },
+ { "pps", 30, 1 },
+ { "tx_ts_avail", 29, 1 },
+ { "single_alarm", 28, 1 },
+ { "periodic_alarm", 27, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_INT_CAUSE", 0x348dc, 0 },
+ { "pps", 30, 1 },
+ { "tx_ts_avail", 29, 1 },
+ { "single_alarm", 28, 1 },
+ { "periodic_alarm", 27, 1 },
+ { "PatDetWake", 26, 1 },
+ { "MagicWake", 25, 1 },
+ { "SigDetChg", 24, 1 },
+ { "AE_Train_Local", 22, 1 },
+ { "HSSPLL_LOCK", 21, 1 },
+ { "HSSPRT_READY", 20, 1 },
+ { "AutoNeg_Done", 19, 1 },
+ { "PCS_Link_Good", 12, 1 },
+ { "PCS_Link_Fail", 11, 1 },
+ { "RxFifoOverFlow", 10, 1 },
+ { "HSSPRBSErr", 9, 1 },
+ { "HSSEyeQual", 8, 1 },
+ { "RemoteFault", 7, 1 },
+ { "LocalFault", 6, 1 },
+ { "MAC_Link_Down", 5, 1 },
+ { "MAC_Link_Up", 4, 1 },
+ { "an_page_rcvd", 2, 1 },
+ { "TxFifo_prty_err", 1, 1 },
+ { "RxFifo_prty_err", 0, 1 },
+ { "MAC_PORT_PERR_INT_EN", 0x348e0, 0 },
+ { "Perr_pkt_ram", 31, 1 },
+ { "Perr_mask_ram", 30, 1 },
+ { "Perr_crc_ram", 29, 1 },
+ { "rx_mac40g", 28, 1 },
+ { "tx_mac40g", 27, 1 },
+ { "rx_st_mac40g", 26, 1 },
+ { "tx_st_mac40g", 25, 1 },
+ { "tx_mac1g10g", 24, 1 },
+ { "rx_mac1g10g", 23, 1 },
+ { "rx_status_mac1g10g", 22, 1 },
+ { "rx_st_mac1g10g", 21, 1 },
+ { "tx_st_mac1g10g", 20, 1 },
+ { "Perr_tx0_pcs40g", 19, 1 },
+ { "Perr_tx1_pcs40g", 18, 1 },
+ { "Perr_tx2_pcs40g", 17, 1 },
+ { "Perr_tx3_pcs40g", 16, 1 },
+ { "Perr_tx0_fec40g", 15, 1 },
+ { "Perr_tx1_fec40g", 14, 1 },
+ { "Perr_tx2_fec40g", 13, 1 },
+ { "Perr_tx3_fec40g", 12, 1 },
+ { "Perr_rx0_pcs40g", 11, 1 },
+ { "Perr_rx1_pcs40g", 10, 1 },
+ { "Perr_rx2_pcs40g", 9, 1 },
+ { "Perr_rx3_pcs40g", 8, 1 },
+ { "Perr_rx0_fec40g", 7, 1 },
+ { "Perr_rx1_fec40g", 6, 1 },
+ { "Perr_rx2_fec40g", 5, 1 },
+ { "Perr_rx3_fec40g", 4, 1 },
+ { "Perr_rx_pcs10g_lpbk", 3, 1 },
+ { "Perr_rx_pcs10g", 2, 1 },
+ { "Perr_rx_pcs1g", 1, 1 },
+ { "Perr_tx_pcs1g", 0, 1 },
+ { "MAC_PORT_PERR_INT_CAUSE", 0x348e4, 0 },
+ { "Perr_pkt_ram", 31, 1 },
+ { "Perr_mask_ram", 30, 1 },
+ { "Perr_crc_ram", 29, 1 },
+ { "rx_mac40g", 28, 1 },
+ { "tx_mac40g", 27, 1 },
+ { "rx_st_mac40g", 26, 1 },
+ { "tx_st_mac40g", 25, 1 },
+ { "tx_mac1g10g", 24, 1 },
+ { "rx_mac1g10g", 23, 1 },
+ { "rx_status_mac1g10g", 22, 1 },
+ { "rx_st_mac1g10g", 21, 1 },
+ { "tx_st_mac1g10g", 20, 1 },
+ { "Perr_tx0_pcs40g", 19, 1 },
+ { "Perr_tx1_pcs40g", 18, 1 },
+ { "Perr_tx2_pcs40g", 17, 1 },
+ { "Perr_tx3_pcs40g", 16, 1 },
+ { "Perr_tx0_fec40g", 15, 1 },
+ { "Perr_tx1_fec40g", 14, 1 },
+ { "Perr_tx2_fec40g", 13, 1 },
+ { "Perr_tx3_fec40g", 12, 1 },
+ { "Perr_rx0_pcs40g", 11, 1 },
+ { "Perr_rx1_pcs40g", 10, 1 },
+ { "Perr_rx2_pcs40g", 9, 1 },
+ { "Perr_rx3_pcs40g", 8, 1 },
+ { "Perr_rx0_fec40g", 7, 1 },
+ { "Perr_rx1_fec40g", 6, 1 },
+ { "Perr_rx2_fec40g", 5, 1 },
+ { "Perr_rx3_fec40g", 4, 1 },
+ { "Perr_rx_pcs10g_lpbk", 3, 1 },
+ { "Perr_rx_pcs10g", 2, 1 },
+ { "Perr_rx_pcs1g", 1, 1 },
+ { "Perr_tx_pcs1g", 0, 1 },
+ { "MAC_PORT_PERR_ENABLE", 0x348e8, 0 },
+ { "Perr_pkt_ram", 31, 1 },
+ { "Perr_mask_ram", 30, 1 },
+ { "Perr_crc_ram", 29, 1 },
+ { "rx_mac40g", 28, 1 },
+ { "tx_mac40g", 27, 1 },
+ { "rx_st_mac40g", 26, 1 },
+ { "tx_st_mac40g", 25, 1 },
+ { "tx_mac1g10g", 24, 1 },
+ { "rx_mac1g10g", 23, 1 },
+ { "rx_status_mac1g10g", 22, 1 },
+ { "rx_st_mac1g10g", 21, 1 },
+ { "tx_st_mac1g10g", 20, 1 },
+ { "Perr_tx0_pcs40g", 19, 1 },
+ { "Perr_tx1_pcs40g", 18, 1 },
+ { "Perr_tx2_pcs40g", 17, 1 },
+ { "Perr_tx3_pcs40g", 16, 1 },
+ { "Perr_tx0_fec40g", 15, 1 },
+ { "Perr_tx1_fec40g", 14, 1 },
+ { "Perr_tx2_fec40g", 13, 1 },
+ { "Perr_tx3_fec40g", 12, 1 },
+ { "Perr_rx0_pcs40g", 11, 1 },
+ { "Perr_rx1_pcs40g", 10, 1 },
+ { "Perr_rx2_pcs40g", 9, 1 },
+ { "Perr_rx3_pcs40g", 8, 1 },
+ { "Perr_rx0_fec40g", 7, 1 },
+ { "Perr_rx1_fec40g", 6, 1 },
+ { "Perr_rx2_fec40g", 5, 1 },
+ { "Perr_rx3_fec40g", 4, 1 },
+ { "Perr_rx_pcs10g_lpbk", 3, 1 },
+ { "Perr_rx_pcs10g", 2, 1 },
+ { "Perr_rx_pcs1g", 1, 1 },
+ { "Perr_tx_pcs1g", 0, 1 },
+ { "MAC_PORT_PERR_INJECT", 0x348ec, 0 },
+ { "MemSel", 1, 6 },
+ { "InjectDataErr", 0, 1 },
+ { "MAC_PORT_HSS_CFG0", 0x348f0, 0 },
+ { "TXDTS", 31, 1 },
+ { "TXCTS", 30, 1 },
+ { "TXBTS", 29, 1 },
+ { "TXATS", 28, 1 },
+ { "TXDOBS", 27, 1 },
+ { "TXCOBS", 26, 1 },
+ { "TXBOBS", 25, 1 },
+ { "TXAOBS", 24, 1 },
+ { "HSSREFCLKVALIDA", 20, 1 },
+ { "HSSREFCLKVALIDB", 19, 1 },
+ { "HSSRESYNCA", 18, 1 },
+ { "HSSAVDHI", 17, 1 },
+ { "HSSRESYNCB", 16, 1 },
+ { "HSSRECCALA", 15, 1 },
+ { "HSSRXACMODE", 14, 1 },
+ { "HSSRECCALB", 13, 1 },
+ { "HSSPLLBYPA", 12, 1 },
+ { "HSSPLLBYPB", 11, 1 },
+ { "HSSPDWNPLLA", 10, 1 },
+ { "HSSPDWNPLLB", 9, 1 },
+ { "HSSVCOSELA", 8, 1 },
+ { "HSSVCOSELB", 7, 1 },
+ { "HSSCALCOMP", 6, 1 },
+ { "HSSCALENAB", 5, 1 },
+ { "HSSEXTC16SEL", 4, 1 },
+ { "MAC_PORT_HSS_CFG1", 0x348f4, 0 },
+ { "RXACONFIGSEL", 30, 2 },
+ { "RXAQUIET", 29, 1 },
+ { "RXAREFRESH", 28, 1 },
+ { "RXBCONFIGSEL", 26, 2 },
+ { "RXBQUIET", 25, 1 },
+ { "RXBREFRESH", 24, 1 },
+ { "RXCCONFIGSEL", 22, 2 },
+ { "RXCQUIET", 21, 1 },
+ { "RXCREFRESH", 20, 1 },
+ { "RXDCONFIGSEL", 18, 2 },
+ { "RXDQUIET", 17, 1 },
+ { "RXDREFRESH", 16, 1 },
+ { "TXACONFIGSEL", 14, 2 },
+ { "TXAQUIET", 13, 1 },
+ { "TXAREFRESH", 12, 1 },
+ { "TXBCONFIGSEL", 10, 2 },
+ { "TXBQUIET", 9, 1 },
+ { "TXBREFRESH", 8, 1 },
+ { "TXCCONFIGSEL", 6, 2 },
+ { "TXCQUIET", 5, 1 },
+ { "TXCREFRESH", 4, 1 },
+ { "TXDCONFIGSEL", 2, 2 },
+ { "TXDQUIET", 1, 1 },
+ { "TXDREFRESH", 0, 1 },
+ { "MAC_PORT_HSS_CFG2", 0x348f8, 0 },
+ { "RXAASSTCLK", 31, 1 },
+ { "T5RXAPRBSRST", 30, 1 },
+ { "RXBASSTCLK", 29, 1 },
+ { "T5RXBPRBSRST", 28, 1 },
+ { "RXCASSTCLK", 27, 1 },
+ { "T5RXCPRBSRST", 26, 1 },
+ { "RXDASSTCLK", 25, 1 },
+ { "T5RXDPRBSRST", 24, 1 },
+ { "RXDDATASYNC", 23, 1 },
+ { "RXCDATASYNC", 22, 1 },
+ { "RXBDATASYNC", 21, 1 },
+ { "RXADATASYNC", 20, 1 },
+ { "RXDEARLYIN", 19, 1 },
+ { "RXDLATEIN", 18, 1 },
+ { "RXDPHSLOCK", 17, 1 },
+ { "RXDPHSDNIN", 16, 1 },
+ { "RXDPHSUPIN", 15, 1 },
+ { "RXCEARLYIN", 14, 1 },
+ { "RXCLATEIN", 13, 1 },
+ { "RXCPHSLOCK", 12, 1 },
+ { "RXCPHSDNIN", 11, 1 },
+ { "RXCPHSUPIN", 10, 1 },
+ { "RXBEARLYIN", 9, 1 },
+ { "RXBLATEIN", 8, 1 },
+ { "RXBPHSLOCK", 7, 1 },
+ { "RXBPHSDNIN", 6, 1 },
+ { "RXBPHSUPIN", 5, 1 },
+ { "RXAEARLYIN", 4, 1 },
+ { "RXALATEIN", 3, 1 },
+ { "RXAPHSLOCK", 2, 1 },
+ { "RXAPHSDNIN", 1, 1 },
+ { "RXAPHSUPIN", 0, 1 },
+ { "MAC_PORT_HSS_CFG3", 0x348fc, 0 },
+ { "HSSCALSSTN", 22, 6 },
+ { "HSSCALSSTP", 16, 6 },
+ { "HSSPLLCONFIGB", 8, 8 },
+ { "HSSPLLCONFIGA", 0, 8 },
+ { "MAC_PORT_HSS_CFG4", 0x34900, 0 },
+ { "HSSREFDIVA", 24, 4 },
+ { "HSSREFDIVB", 20, 4 },
+ { "HSSPLLDIV2B", 19, 1 },
+ { "HSSPLLDIV2A", 18, 1 },
+ { "HSSDIVSELA", 9, 9 },
+ { "HSSDIVSELB", 0, 9 },
+ { "MAC_PORT_HSS_STATUS", 0x34904, 0 },
+ { "RXDERROFLOW", 19, 1 },
+ { "RXCERROFLOW", 18, 1 },
+ { "RXBERROFLOW", 17, 1 },
+ { "RXAERROFLOW", 16, 1 },
+ { "RXDPRBSSYNC", 15, 1 },
+ { "RXCPRBSSYNC", 14, 1 },
+ { "RXBPRBSSYNC", 13, 1 },
+ { "RXAPRBSSYNC", 12, 1 },
+ { "RXDPRBSERR", 11, 1 },
+ { "RXCPRBSERR", 10, 1 },
+ { "RXBPRBSERR", 9, 1 },
+ { "RXAPRBSERR", 8, 1 },
+ { "RXDSIGDET", 7, 1 },
+ { "RXCSIGDET", 6, 1 },
+ { "RXBSIGDET", 5, 1 },
+ { "RXASIGDET", 4, 1 },
+ { "HSSPLLLOCKB", 3, 1 },
+ { "HSSPLLLOCKA", 2, 1 },
+ { "HSSPRTREADYB", 1, 1 },
+ { "HSSPRTREADYA", 0, 1 },
+ { "MAC_PORT_HSS_EEE_STATUS", 0x34908, 0 },
+ { "RXAQUIET_STATUS", 15, 1 },
+ { "RXAREFRESH_STATUS", 14, 1 },
+ { "RXBQUIET_STATUS", 13, 1 },
+ { "RXBREFRESH_STATUS", 12, 1 },
+ { "RXCQUIET_STATUS", 11, 1 },
+ { "RXCREFRESH_STATUS", 10, 1 },
+ { "RXDQUIET_STATUS", 9, 1 },
+ { "RXDREFRESH_STATUS", 8, 1 },
+ { "TXAQUIET_STATUS", 7, 1 },
+ { "TXAREFRESH_STATUS", 6, 1 },
+ { "TXBQUIET_STATUS", 5, 1 },
+ { "TXBREFRESH_STATUS", 4, 1 },
+ { "TXCQUIET_STATUS", 3, 1 },
+ { "TXCREFRESH_STATUS", 2, 1 },
+ { "TXDQUIET_STATUS", 1, 1 },
+ { "TXDREFRESH_STATUS", 0, 1 },
+ { "MAC_PORT_HSS_SIGDET_STATUS", 0x3490c, 0 },
+ { "MAC_PORT_HSS_PL_CTL", 0x34910, 0 },
+ { "TOV", 16, 8 },
+ { "TSU", 8, 8 },
+ { "IPW", 0, 8 },
+ { "MAC_PORT_RUNT_FRAME", 0x34914, 0 },
+ { "runtclear", 16, 1 },
+ { "runt", 0, 16 },
+ { "MAC_PORT_EEE_STATUS", 0x34918, 0 },
+ { "eee_tx_10g_state", 10, 2 },
+ { "eee_rx_10g_state", 8, 2 },
+ { "eee_tx_1g_state", 6, 2 },
+ { "eee_rx_1g_state", 4, 2 },
+ { "pma_rx_refresh", 3, 1 },
+ { "pma_rx_quiet", 2, 1 },
+ { "pma_tx_refresh", 1, 1 },
+ { "pma_tx_quiet", 0, 1 },
+ { "MAC_PORT_CGEN", 0x3491c, 0 },
+ { "CGEN", 8, 1 },
+ { "sd7_CGEN", 7, 1 },
+ { "sd6_CGEN", 6, 1 },
+ { "sd5_CGEN", 5, 1 },
+ { "sd4_CGEN", 4, 1 },
+ { "sd3_CGEN", 3, 1 },
+ { "sd2_CGEN", 2, 1 },
+ { "sd1_CGEN", 1, 1 },
+ { "sd0_CGEN", 0, 1 },
+ { "MAC_PORT_CGEN_MTIP", 0x34920, 0 },
+ { "MACSEG5_CGEN", 11, 1 },
+ { "PCSSEG5_CGEN", 10, 1 },
+ { "MACSEG4_CGEN", 9, 1 },
+ { "PCSSEG4_CGEN", 8, 1 },
+ { "MACSEG3_CGEN", 7, 1 },
+ { "PCSSEG3_CGEN", 6, 1 },
+ { "MACSEG2_CGEN", 5, 1 },
+ { "PCSSEG2_CGEN", 4, 1 },
+ { "MACSEG1_CGEN", 3, 1 },
+ { "PCSSEG1_CGEN", 2, 1 },
+ { "MACSEG0_CGEN", 1, 1 },
+ { "PCSSEG0_CGEN", 0, 1 },
+ { "MAC_PORT_TX_TS_ID", 0x34924, 0 },
+ { "MAC_PORT_TX_TS_VAL_LO", 0x34928, 0 },
+ { "MAC_PORT_TX_TS_VAL_HI", 0x3492c, 0 },
+ { "MAC_PORT_EEE_CTL", 0x34930, 0 },
+ { "EEE_CTRL", 2, 30 },
+ { "TICK_START", 1, 1 },
+ { "En", 0, 1 },
+ { "MAC_PORT_EEE_TX_CTL", 0x34934, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_ACTIVE", 3, 1 },
+ { "LPI_TXHOLD", 2, 1 },
+ { "LPI_REQ", 1, 1 },
+ { "EEE_TX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_RX_CTL", 0x34938, 0 },
+ { "WAKE_TIMER", 16, 16 },
+ { "HSS_TIMER", 5, 4 },
+ { "HSS_CTL", 4, 1 },
+ { "LPI_IND", 1, 1 },
+ { "EEE_RX_RESET", 0, 1 },
+ { "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3493c, 0 },
+ { "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x34940, 0 },
+ { "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x34944, 0 },
+ { "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x34948, 0 },
+ { "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3494c, 0 },
+ { "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x34950, 0 },
+ { "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x34954, 0 },
+ { "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x34958, 0 },
+ { "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3495c, 0 },
+ { "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x34960, 0 },
+ { "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x34964, 0 },
+ { "MAC_PORT_EEE_WF_COUNT", 0x34968, 0 },
+ { "wake_cnt_clr", 16, 1 },
+ { "wake_cnt", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_RD0_LO", 0x3496c, 0 },
+ { "MAC_PORT_PTP_TIMER_RD0_HI", 0x34970, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_LO", 0x34974, 0 },
+ { "MAC_PORT_PTP_TIMER_RD1_HI", 0x34978, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_LO", 0x3497c, 0 },
+ { "MAC_PORT_PTP_TIMER_WR_HI", 0x34980, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_0", 0x34984, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_1", 0x34988, 0 },
+ { "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3498c, 0 },
+ { "MAC_PORT_PTP_SUM_LO", 0x34990, 0 },
+ { "MAC_PORT_PTP_SUM_HI", 0x34994, 0 },
+ { "MAC_PORT_PTP_TIMER_INCR0", 0x34998, 0 },
+ { "Y", 16, 16 },
+ { "X", 0, 16 },
+ { "MAC_PORT_PTP_TIMER_INCR1", 0x3499c, 0 },
+ { "Y_TICK", 16, 16 },
+ { "X_TICK", 0, 16 },
+ { "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x349a0, 0 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x349a4, 0 },
+ { "B", 16, 16 },
+ { "A", 0, 16 },
+ { "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x349a8, 0 },
+ { "MAC_PORT_PTP_CFG", 0x349ac, 0 },
+ { "ALARM_EN", 21, 1 },
+ { "ALARM_START", 20, 1 },
+ { "PPS_EN", 19, 1 },
+ { "FRZ", 18, 1 },
+ { "OFFSER_ADJUST_SIGN", 17, 1 },
+ { "ADD_OFFSET", 16, 1 },
+ { "CYCLE1", 8, 8 },
+ { "Q", 0, 8 },
+ { "MAC_PORT_PTP_PPS", 0x349b0, 0 },
+ { "MAC_PORT_PTP_SINGLE_ALARM", 0x349b4, 0 },
+ { "MAC_PORT_PTP_PERIODIC_ALARM", 0x349b8, 0 },
+ { "MAC_PORT_PTP_STATUS", 0x349bc, 0 },
+ { "MAC_PORT_MTIP_REVISION", 0x34a00, 0 },
+ { "CUSTREV", 16, 16 },
+ { "VER", 8, 8 },
+ { "REV", 0, 8 },
+ { "MAC_PORT_MTIP_SCRATCH", 0x34a04, 0 },
+ { "MAC_PORT_MTIP_COMMAND_CONFIG", 0x34a08, 0 },
+ { "TX_FLUSH", 22, 1 },
+ { "RX_SFD_ANY", 21, 1 },
+ { "PAUSE_PFC_COMP", 20, 1 },
+ { "PFC_MODE", 19, 1 },
+ { "RS_COL_CNT_EXT", 18, 1 },
+ { "NO_LGTH_CHECK", 17, 1 },
+ { "SEND_IDLE", 16, 1 },
+ { "PHY_TXENA", 15, 1 },
+ { "RX_ERR_DISC", 14, 1 },
+ { "CMD_FRAME_ENA", 13, 1 },
+ { "SW_RESET", 12, 1 },
+ { "TX_PAD_EN", 11, 1 },
+ { "LOOPBACK_EN", 10, 1 },
+ { "TX_ADDR_INS", 9, 1 },
+ { "PAUSE_IGNORE", 8, 1 },
+ { "PAUSE_FWD", 7, 1 },
+ { "CRC_FWD", 6, 1 },
+ { "PAD_EN", 5, 1 },
+ { "PROMIS_EN", 4, 1 },
+ { "WAN_MODE", 3, 1 },
+ { "RX_ENA", 1, 1 },
+ { "TX_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_MAC_ADDR_0", 0x34a0c, 0 },
+ { "MAC_PORT_MTIP_MAC_ADDR_1", 0x34a10, 0 },
+ { "MAC_PORT_MTIP_FRM_LENGTH", 0x34a14, 0 },
+ { "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x34a1c, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x34a20, 0 },
+ { "AVAIL", 16, 16 },
+ { "EMPTY", 0, 16 },
+ { "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x34a24, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x34a28, 0 },
+ { "AlmstFull", 16, 16 },
+ { "AlmstEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x34a2c, 0 },
+ { "ENABLE", 8, 1 },
+ { "ADDR", 0, 6 },
+ { "MAC_PORT_MTIP_MAC_STATUS", 0x34a40, 0 },
+ { "TS_AVAIL", 3, 1 },
+ { "PHY_LOS", 2, 1 },
+ { "RX_REM_FAULT", 1, 1 },
+ { "RX_LOC_FAULT", 0, 1 },
+ { "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x34a44, 0 },
+ { "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x34a48, 0 },
+ { "MAC_PORT_MTIP_INIT_CREDIT", 0x34a4c, 0 },
+ { "MAC_PORT_MTIP_CURRENT_CREDIT", 0x34a50, 0 },
+ { "MAC_PORT_RX_PAUSE_STATUS", 0x34a74, 0 },
+ { "MAC_PORT_MTIP_TS_TIMESTAMP", 0x34a7c, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x34a80, 0 },
+ { "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x34a84, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOK", 0x34a88, 0 },
+ { "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x34a8c, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x34a90, 0 },
+ { "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x34a94, 0 },
+ { "MAC_PORT_AALIGNMENTERRORS", 0x34a98, 0 },
+ { "MAC_PORT_AALIGNMENTERRORSHI", 0x34a9c, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x34aa0, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x34aa4, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x34aa8, 0 },
+ { "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x34aac, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORS", 0x34ab0, 0 },
+ { "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x34ab4, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORS", 0x34ab8, 0 },
+ { "MAC_PORT_AINRANGELENGTHERRORSHI", 0x34abc, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOK", 0x34ac0, 0 },
+ { "MAC_PORT_VLANTRANSMITTEDOKHI", 0x34ac4, 0 },
+ { "MAC_PORT_VLANRECEIVEDOK", 0x34ac8, 0 },
+ { "MAC_PORT_VLANRECEIVEDOKHI", 0x34acc, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x34ad0, 0 },
+ { "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x34ad4, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOK", 0x34ad8, 0 },
+ { "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x34adc, 0 },
+ { "MAC_PORT_IFINUCASTPKTS", 0x34ae0, 0 },
+ { "MAC_PORT_IFINUCASTPKTSHI", 0x34ae4, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTS", 0x34ae8, 0 },
+ { "MAC_PORT_IFINMULTICASTPKTSHI", 0x34aec, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTS", 0x34af0, 0 },
+ { "MAC_PORT_IFINBROADCASTPKTSHI", 0x34af4, 0 },
+ { "MAC_PORT_IFOUTERRORS", 0x34af8, 0 },
+ { "MAC_PORT_IFOUTERRORSHI", 0x34afc, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTS", 0x34b08, 0 },
+ { "MAC_PORT_IFOUTUCASTPKTSHI", 0x34b0c, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTS", 0x34b10, 0 },
+ { "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x34b14, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTS", 0x34b18, 0 },
+ { "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x34b1c, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTS", 0x34b20, 0 },
+ { "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x34b24, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETS", 0x34b28, 0 },
+ { "MAC_PORT_ETHERSTATSOCTETSHI", 0x34b2c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS", 0x34b30, 0 },
+ { "MAC_PORT_ETHERSTATSPKTSHI", 0x34b34, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x34b38, 0 },
+ { "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x34b3c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x34b40, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x34b44, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x34b48, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x34b4c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x34b50, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x34b54, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x34b58, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x34b5c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x34b60, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34b64, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x34b68, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34b6c, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x34b70, 0 },
+ { "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x34b74, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x34b78, 0 },
+ { "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x34b7c, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERS", 0x34b80, 0 },
+ { "MAC_PORT_ETHERSTATSJABBERSHI", 0x34b84, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTS", 0x34b88, 0 },
+ { "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x34b8c, 0 },
+ { "MAC_PORT_IFINERRORS", 0x34b90, 0 },
+ { "MAC_PORT_IFINERRORSHI", 0x34b94, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x34b98, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x34b9c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x34ba0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x34ba4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x34ba8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x34bac, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x34bb0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x34bb4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x34bb8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x34bbc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x34bc0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x34bc4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x34bc8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x34bcc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x34bd0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x34bd4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x34bd8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x34bdc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x34be0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x34be4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x34be8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x34bec, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x34bf0, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x34bf4, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x34bf8, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x34bfc, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x34c00, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x34c04, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x34c08, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x34c0c, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x34c10, 0 },
+ { "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x34c14, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x34c18, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x34c1c, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x34c20, 0 },
+ { "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x34c24, 0 },
+ { "MAC_PORT_MTIP_1G10G_REVISION", 0x34d00, 0 },
+ { "CUSTREV", 16, 16 },
+ { "VER", 8, 8 },
+ { "REV", 0, 8 },
+ { "MAC_PORT_MTIP_1G10G_SCRATCH", 0x34d04, 0 },
+ { "MAC_PORT_MTIP_1G10G_COMMAND_CONFIG", 0x34d08, 0 },
+ { "SHORT_DISCARD", 25, 1 },
+ { "REG_LOWP_RXEMPTY", 24, 1 },
+ { "TX_LOWP_ENA", 23, 1 },
+ { "TX_FLUSH", 22, 1 },
+ { "SFD_ANY", 21, 1 },
+ { "PAUSE_PFC_COMP", 20, 1 },
+ { "PFC_MODE", 19, 1 },
+ { "COL_CNT_ExT", 18, 1 },
+ { "NO_LGTH_CHECK", 17, 1 },
+ { "FORCE_SEND_IDLE", 16, 1 },
+ { "PHY_TXENA", 15, 1 },
+ { "RX_ERR_DISC", 14, 1 },
+ { "CNTL_FRM_ENA", 13, 1 },
+ { "SW_RESET", 12, 1 },
+ { "TX_PAD_EN", 11, 1 },
+ { "LOOP_ENA", 10, 1 },
+ { "TX_ADDR_INS", 9, 1 },
+ { "PAUSE_IGNORE", 8, 1 },
+ { "PAUSE_FWD", 7, 1 },
+ { "CRC_FWD", 6, 1 },
+ { "PAD_EN", 5, 1 },
+ { "PROMIS_EN", 4, 1 },
+ { "WAN_MODE", 3, 1 },
+ { "RX_ENAMAC", 1, 1 },
+ { "TX_ENAMAC", 0, 1 },
+ { "MAC_PORT_MTIP_1G10G_MAC_ADDR_0", 0x34d0c, 0 },
+ { "MAC_PORT_MTIP_1G10G_MAC_ADDR_1", 0x34d10, 0 },
+ { "MAC_PORT_MTIP_1G10G_FRM_LENGTH_TX_MTU", 0x34d14, 0 },
+ { "SET_LEN", 16, 16 },
+ { "FRM_LEN_SET", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_RX_FIFO_SECTIONS", 0x34d1c, 0 },
+ { "EMPTY", 16, 16 },
+ { "AVAIL", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_TX_FIFO_SECTIONS", 0x34d20, 0 },
+ { "EMPTY", 16, 16 },
+ { "AVAIL", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_RX_FIFO_ALMOST_F_E", 0x34d24, 0 },
+ { "AlmostFull", 16, 16 },
+ { "AlmostEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_TX_FIFO_ALMOST_F_E", 0x34d28, 0 },
+ { "AlmostFull", 16, 16 },
+ { "AlmostEmpty", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_HASHTABLE_LOAD", 0x34d2c, 0 },
+ { "MAC_PORT_MTIP_1G10G_MDIO_CFG_STATUS", 0x34d30, 0 },
+ { "Clk_divisor", 7, 9 },
+ { "ENA_CLAUSE", 6, 1 },
+ { "PREAMBLE_DISABLE", 5, 1 },
+ { "Hold_time_setting", 2, 3 },
+ { "MDIO_read_error", 1, 1 },
+ { "MDIO_Busy", 0, 1 },
+ { "MAC_PORT_MTIP_1G10G_MDIO_COMMAND", 0x34d34, 0 },
+ { "READ_MODE", 15, 1 },
+ { "POST_INCR_READ", 14, 1 },
+ { "Port_PHY_Addr", 5, 5 },
+ { "Device_Reg_Addr", 0, 5 },
+ { "MAC_PORT_MTIP_1G10G_MDIO_DATA", 0x34d38, 0 },
+ { "MAC_PORT_MTIP_1G10G_MDIO_REGADDR", 0x34d3c, 0 },
+ { "MAC_PORT_MTIP_1G10G_STATUS", 0x34d40, 0 },
+ { "RX_LINT_FAULT", 7, 1 },
+ { "RX_EMPTY", 6, 1 },
+ { "TX_EMPTY", 5, 1 },
+ { "RX_LOWP", 4, 1 },
+ { "TS_AVAIL", 3, 1 },
+ { "PHY_LOS", 2, 1 },
+ { "RX_REM_FAULT", 1, 1 },
+ { "RX_LOC_FAULT", 0, 1 },
+ { "MAC_PORT_MTIP_1G10G_TX_IPG_LENGTH", 0x34d44, 0 },
+ { "MAC_PORT_MTIP_1G10G_CREDIT_TRIGGER", 0x34d48, 0 },
+ { "MAC_PORT_MTIP_1G10G_INIT_CREDIT", 0x34d4c, 0 },
+ { "MAC_PORT_MTIP_1G10G_CL01_PAUSE_QUANTA", 0x34d54, 0 },
+ { "CL1_PAUSE_QUANTA", 16, 16 },
+ { "CL0_PAUSE_QUANTA", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL23_PAUSE_QUANTA", 0x34d58, 0 },
+ { "CL3_PAUSE_QUANTA", 16, 16 },
+ { "CL2_PAUSE_QUANTA", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL45_PAUSE_QUANTA", 0x34d5c, 0 },
+ { "CL5_PAUSE_QUANTA", 16, 16 },
+ { "CL4_PAUSE_QUANTA", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL67_PAUSE_QUANTA", 0x34d60, 0 },
+ { "CL7_PAUSE_QUANTA", 16, 16 },
+ { "CL6_PAUSE_QUANTA", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL01_QUANTA_THRESH", 0x34d64, 0 },
+ { "CL1_QUANTA_THRESH", 16, 16 },
+ { "CL0_QUANTA_THRESH", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL23_QUANTA_THRESH", 0x34d68, 0 },
+ { "CL3_QUANTA_THRESH", 16, 16 },
+ { "CL2_QUANTA_THRESH", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL45_QUANTA_THRESH", 0x34d6c, 0 },
+ { "CL5_QUANTA_THRESH", 16, 16 },
+ { "CL4_QUANTA_THRESH", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_CL67_QUANTA_THRESH", 0x34d70, 0 },
+ { "CL7_QUANTA_THRESH", 16, 16 },
+ { "CL6_QUANTA_THRESH", 0, 16 },
+ { "MAC_PORT_MTIP_1G10G_RX_PAUSE_STATUS", 0x34d74, 0 },
+ { "MAC_PORT_MTIP_1G10G_TS_TIMESTAMP", 0x34d7c, 0 },
+ { "MAC_PORT_MTIP_1G10G_STATN_CONFIG", 0x34de0, 0 },
+ { "CLEAR", 2, 1 },
+ { "CLEAR_ON_READ", 1, 1 },
+ { "SATURATE", 0, 1 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETS", 0x34e00, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOCTETSHI", 0x34e04, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_OCTETSOK", 0x34e08, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_OCTETSOKHI", 0x34e0c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORS", 0x34e10, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AALIGNMENTERRORSHI", 0x34e14, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMES", 0x34e18, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_APAUSEMACCTRLFRAMESHI", 0x34e1c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_FRAMESOK", 0x34e20, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_FRAMESOKHI", 0x34e24, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_CRCERRORS", 0x34e28, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_CRCERRORSHI", 0x34e2c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_VLANOK", 0x34e30, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_VLANOKHI", 0x34e34, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINERRORS", 0x34e38, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINERRORSHI", 0x34e3c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTS", 0x34e40, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINUCASTPKTSHI", 0x34e44, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTS", 0x34e48, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINMULTICASTPKTSHI", 0x34e4c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTS", 0x34e50, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_IFINBROADCASTPKTSHI", 0x34e54, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTS", 0x34e58, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSDROPEVENTSHI", 0x34e5c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS", 0x34e60, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTSHI", 0x34e64, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTS", 0x34e68, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSUNDERSIZEPKTSHI", 0x34e6c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETS", 0x34e70, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS64OCTETSHI", 0x34e74, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETS", 0x34e78, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS65TO127OCTETSHI", 0x34e7c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETS", 0x34e80, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS128TO255OCTETSHI", 0x34e84, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETS", 0x34e88, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS256TO511OCTETSHI", 0x34e8c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETS", 0x34e90, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34e94, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETS", 0x34e98, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34e9c, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAX", 0x34ea0, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSPKTS1519TOMAXHI", 0x34ea4, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTS", 0x34ea8, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSOVERSIZEPKTSHI", 0x34eac, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERS", 0x34eb0, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSJABBERSHI", 0x34eb4, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTS", 0x34eb8, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_ETHERSTATSFRAGMENTSHI", 0x34ebc, 0 },
+ { "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVED", 0x34ec0, 0 },
+ { "MAC_PORT_MTIP_1G10G_AMACCONTROLFRAMESRECEIVEDHI", 0x34ec4, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONG", 0x34ec8, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AFRAMETOOLONGHI", 0x34ecc, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORS", 0x34ed0, 0 },
+ { "MAC_PORT_MTIP_1G10G_RX_AINRANGELENGTHERRORSHI", 0x34ed4, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETS", 0x34f00, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSOCTETSHI", 0x34f04, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_OCTETSOK", 0x34f08, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_OCTETSOKHI", 0x34f0c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORS", 0x34f10, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_AALIGNMENTERRORSHI", 0x34f14, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMES", 0x34f18, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_APAUSEMACCTRLFRAMESHI", 0x34f1c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_FRAMESOK", 0x34f20, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_FRAMESOKHI", 0x34f24, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_CRCERRORS", 0x34f28, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_CRCERRORSHI", 0x34f2c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_VLANOK", 0x34f30, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_VLANOKHI", 0x34f34, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORS", 0x34f38, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFOUTERRORSHI", 0x34f3c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTS", 0x34f40, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFUCASTPKTSHI", 0x34f44, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTS", 0x34f48, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFMULTICASTPKTSHI", 0x34f4c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTS", 0x34f50, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_IFBROADCASTPKTSHI", 0x34f54, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTS", 0x34f58, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSDROPEVENTSHI", 0x34f5c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS", 0x34f60, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTSHI", 0x34f64, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTS", 0x34f68, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSUNDERSIZEPKTSHI", 0x34f6c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETS", 0x34f70, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS64OCTETSHI", 0x34f74, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETS", 0x34f78, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS65TO127OCTETSHI", 0x34f7c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETS", 0x34f80, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS128TO255OCTETSHI", 0x34f84, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETS", 0x34f88, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS256TO511OCTETSHI", 0x34f8c, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETS", 0x34f90, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34f94, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETS", 0x34f98, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34f9c, 0 },
+ { "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTU", 0x34fa0, 0 },
+ { "MAC_PORT_MTIP_1G10G_ETHERSTATSPKTS1519TOTX_MTUHI", 0x34fa4, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMES", 0x34fc0, 0 },
+ { "MAC_PORT_MTIP_1G10G_TX_AMACCONTROLFRAMESHI", 0x34fc4, 0 },
+ { "MAC_PORT_MTIP_1G10G_IF_MODE", 0x35000, 0 },
+ { "MII_ENA_10", 4, 1 },
+ { "IF_MODE", 0, 2 },
+ { "MAC_PORT_MTIP_1G10G_IF_STATUS", 0x35004, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0", 0x35080, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_0HI", 0x35084, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1", 0x35088, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_1HI", 0x3508c, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2", 0x35090, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_2HI", 0x35094, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3", 0x35098, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_3HI", 0x3509c, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4", 0x350a0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_4HI", 0x350a4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5", 0x350a8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_5HI", 0x350ac, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6", 0x350b0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_6HI", 0x350b4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7", 0x350b8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESRECEIVED_7HI", 0x350bc, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0", 0x350c0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_0HI", 0x350c4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1", 0x350c8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_1HI", 0x350cc, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2", 0x350d0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_2HI", 0x350d4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3", 0x350d8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_3HI", 0x350dc, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4", 0x350e0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_4HI", 0x350e4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5", 0x350e8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_5HI", 0x350ec, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6", 0x350f0, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_6HI", 0x350f4, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7", 0x350f8, 0 },
+ { "MAC_PORT_MTIP_1G10G_PFCFRAMESTRANSMITTED_7HI", 0x350fc, 0 },
+ { "MAC_PORT_MTIP_SGMII_CONTROL", 0x35200, 0 },
+ { "Reset", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "Speed_Sel", 13, 1 },
+ { "AN_EN", 12, 1 },
+ { "PWR_DWN", 11, 1 },
+ { "Isolate", 10, 1 },
+ { "AN_RESTART", 9, 1 },
+ { "DUPLEx_MODE", 8, 1 },
+ { "Collision_Test", 7, 1 },
+ { "Speed_Sel1", 6, 1 },
+ { "MAC_PORT_MTIP_SGMII_STATUS", 0x35204, 0 },
+ { "100BaseT4", 15, 1 },
+ { "100BasexFullDplx", 14, 1 },
+ { "100BasexHalfDplx", 13, 1 },
+ { "10MbpsFullDplx", 12, 1 },
+ { "10MbpsHalfDplx", 11, 1 },
+ { "100BaseT2FullDplx", 10, 1 },
+ { "100BaseT2HalfDplx", 9, 1 },
+ { "ExtdStatus", 8, 1 },
+ { "AN_Complete", 5, 1 },
+ { "REM_FAULT", 4, 1 },
+ { "AN_Ability", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "JabberDetect", 1, 1 },
+ { "ExtdCapability", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x35208, 0 },
+ { "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x3520c, 0 },
+ { "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x35210, 0 },
+ { "NP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "RF2", 13, 1 },
+ { "RF1", 12, 1 },
+ { "PS2", 8, 1 },
+ { "PS1", 7, 1 },
+ { "HD", 6, 1 },
+ { "FD", 5, 1 },
+ { "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x35214, 0 },
+ { "CuLinkStatus", 15, 1 },
+ { "ACK", 14, 1 },
+ { "CuDplxStatus", 12, 1 },
+ { "CuSpeed", 10, 2 },
+ { "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x35218, 0 },
+ { "Next_Page_Able", 2, 1 },
+ { "PAGE_RECEIVE", 1, 1 },
+ { "MAC_PORT_MTIP_SGMII_NP_TX", 0x3521c, 0 },
+ { "MAC_PORT_MTIP_SGMII_LP_NP_RX", 0x35220, 0 },
+ { "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x3523c, 0 },
+ { "MAC_PORT_MTIP_SGMII_SCRATCH", 0x35240, 0 },
+ { "MAC_PORT_MTIP_SGMII_REV", 0x35244, 0 },
+ { "CUSTREV", 16, 16 },
+ { "VER", 8, 8 },
+ { "REV", 0, 8 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x35248, 0 },
+ { "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x3524c, 0 },
+ { "MAC_PORT_MTIP_SGMII_IF_MODE", 0x35250, 0 },
+ { "SGMII_DUPLEx", 4, 1 },
+ { "SGMII_SPEED", 2, 2 },
+ { "USE_SGMII_AN", 1, 1 },
+ { "SGMII_ENA", 0, 1 },
+ { "MAC_PORT_MTIP_SGMII_DECODE_ERROR", 0x35254, 0 },
+ { "MAC_PORT_MTIP_KR_PCS_CONTROL_1", 0x35300, 0 },
+ { "Reset", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "Speed_SEL", 13, 1 },
+ { "Low_Power", 11, 1 },
+ { "Speed_SEL1", 6, 1 },
+ { "Speed_SEL2", 2, 4 },
+ { "MAC_PORT_MTIP_KR_PCS_STATUS_1", 0x35304, 0 },
+ { "TX_LPI", 11, 1 },
+ { "RX_LPI", 10, 1 },
+ { "TX_LPI_ACTIVE", 9, 1 },
+ { "RX_LPI_ACTIVE", 8, 1 },
+ { "Fault", 7, 1 },
+ { "PCS_RX_Link_STAT", 2, 1 },
+ { "Low_power_Ability", 1, 1 },
+ { "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_1", 0x35308, 0 },
+ { "MAC_PORT_MTIP_KR_PCS_DEVICE_IDENTIFIER_2", 0x3530c, 0 },
+ { "MAC_PORT_MTIP_KR_PCS_SPEED_ABILITY", 0x35310, 0 },
+ { "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGELO", 0x35314, 0 },
+ { "Auto_Negotiation_Present", 7, 1 },
+ { "DTE_xS_present", 5, 1 },
+ { "PHY_xS_present", 4, 1 },
+ { "PCS_present", 3, 1 },
+ { "WIS_present", 2, 1 },
+ { "PMD_PMA_Present", 1, 1 },
+ { "Clause_22_Reg_Present", 0, 1 },
+ { "MAC_PORT_MTIP_KR_PCS_DEVICES_IN_PACKAGEHI", 0x35318, 0 },
+ { "Auto_Negotiation_Present", 7, 1 },
+ { "DTE_xS_present", 5, 1 },
+ { "PHY_xS_present", 4, 1 },
+ { "PCS_present", 3, 1 },
+ { "WIS_present", 2, 1 },
+ { "PMD_PMA_Present", 1, 1 },
+ { "Clause_22_Reg_Present", 0, 1 },
+ { "MAC_PORT_MTIP_KR_PCS_CONTROL_2", 0x3531c, 0 },
+ { "MAC_PORT_MTIP_KR_PCS_STATUS_2", 0x35320, 0 },
+ { "Device_Present", 14, 2 },
+ { "Transmit_Fault", 11, 1 },
+ { "Receive_Fault", 10, 1 },
+ { "10GBASE_W_Capable", 2, 1 },
+ { "10GBASE_x_Capable", 1, 1 },
+ { "10GBASE_R_Capable", 0, 1 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_LO", 0x35338, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_PACKAGE_IDENTIFIER_HI", 0x3533c, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_1", 0x35380, 0 },
+ { "10GBASE_R_RX_Link_Status", 12, 1 },
+ { "PRBS9_Pttrn_Tstng_Ability", 3, 1 },
+ { "PRBS31_Pttrn_Tstng_Ability", 2, 1 },
+ { "10GBASE_R_PCS_High_BER", 1, 1 },
+ { "10GBASE_R_PCS_Block_Lock", 0, 1 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_STATUS_2", 0x35384, 0 },
+ { "Latched_Block_Lock", 15, 1 },
+ { "Latched_High_BER", 14, 1 },
+ { "BERBER_Counter", 8, 6 },
+ { "ErrBlkCnt", 0, 8 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_0", 0x35388, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_1", 0x3538c, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_2", 0x35390, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_A_3", 0x35394, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_0", 0x35398, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_1", 0x3539c, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_2", 0x353a0, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_SEED_B_3", 0x353a4, 0 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_CONTROL", 0x353a8, 0 },
+ { "PRBS9_TX_Tst_Pttrn_En", 6, 1 },
+ { "PRBS31_RX_Tst_Pttrn_En", 5, 1 },
+ { "PRBS31_TX_Tst_Pttrn_En", 4, 1 },
+ { "TX_Test_Pattern_En", 3, 1 },
+ { "RX_Test_Pattern_En", 2, 1 },
+ { "Test_Pattern_Select", 1, 1 },
+ { "Data_Pattern_Select", 0, 1 },
+ { "MAC_PORT_MTIP_KR_10GBASE_R_PCS_TEST_PATTERN_ERROR_COUNTER", 0x353ac, 0 },
+ { "MAC_PORT_MTIP_KR_VENDOR_SPECIFIC_PCS_STATUS", 0x353b4, 0 },
+ { "Transmit_FIFO_Fault", 1, 1 },
+ { "Receive_FIFO_Fault", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_CONTROL_1", 0x35400, 0 },
+ { "RESET", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "Speed_selection", 13, 1 },
+ { "Low_power", 11, 1 },
+ { "Speed_selection1", 6, 1 },
+ { "Speed_selection2", 2, 4 },
+ { "MAC_PORT_MTIP_KR4_STATUS_1", 0x35404, 0 },
+ { "Fault", 7, 1 },
+ { "Receive_link_STAT", 2, 1 },
+ { "Low_power_ability", 1, 1 },
+ { "MAC_PORT_MTIP_KR4_DEVICE_ID0", 0x35408, 0 },
+ { "MAC_PORT_MTIP_KR4_DEVICE_ID1", 0x3540c, 0 },
+ { "DEVICE_ID1", 16, 16 },
+ { "MAC_PORT_MTIP_KR4_SPEED_ABILITY", 0x35410, 0 },
+ { "100G_capable", 3, 1 },
+ { "40G_capable", 2, 1 },
+ { "10PASS_TS_2Base_TL_capable", 1, 1 },
+ { "10G_capable", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG1", 0x35414, 0 },
+ { "TC_present", 6, 1 },
+ { "DTE_xS_present", 5, 1 },
+ { "PHY_xS_present", 4, 1 },
+ { "PCS_present", 3, 1 },
+ { "WIS_present", 2, 1 },
+ { "PMD_PMA_present", 1, 1 },
+ { "Clause_22_reg", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_DEVICES_IN_PKG2", 0x35418, 0 },
+ { "Vendor_specific_device", 15, 1 },
+ { "Vendor_specific_device1", 14, 1 },
+ { "Clause_22_ExT", 13, 1 },
+ { "MAC_PORT_MTIP_KR4_CONTROL_2", 0x3541c, 0 },
+ { "MAC_PORT_MTIP_KR4_STATUS_2", 0x35420, 0 },
+ { "Device_present", 14, 2 },
+ { "Transmit_fault", 11, 1 },
+ { "Receive_fault", 10, 1 },
+ { "100GBase_R_capable", 5, 1 },
+ { "40GBase_R_capable", 4, 1 },
+ { "10GBase_T_capable", 3, 1 },
+ { "10GBase_W_capable", 2, 1 },
+ { "10GBase_x_capable", 1, 1 },
+ { "10GBase_R_capable", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_PKG_ID0", 0x35438, 0 },
+ { "MAC_PORT_MTIP_KR4_PKG_ID1", 0x3543c, 0 },
+ { "MAC_PORT_MTIP_KR4_BASE_R_STATUS_1", 0x35480, 0 },
+ { "RX_link_status", 12, 1 },
+ { "High_BER", 1, 1 },
+ { "Block_lock", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_BASE_R_STATUS_2", 0x35484, 0 },
+ { "Latched_bl_lk", 15, 1 },
+ { "Latched_hg_br", 14, 1 },
+ { "Ber_cnt", 8, 6 },
+ { "Err_bl_cnt", 0, 8 },
+ { "MAC_PORT_MTIP_KR4_BASE_R_TEST_CONTROL", 0x354a8, 0 },
+ { "TX_TP_EN", 3, 1 },
+ { "RX_TP_EN", 2, 1 },
+ { "MAC_PORT_MTIP_KR4_BASE_R_TEST_ERR_CNT", 0x354ac, 0 },
+ { "MAC_PORT_MTIP_KR4_BER_HIGH_ORDER_CNT", 0x354b0, 0 },
+ { "MAC_PORT_MTIP_KR4_ERR_BLK_HIGH_ORDER_CNT", 0x354b4, 0 },
+ { "HI_ORDER_CNT_EN", 15, 1 },
+ { "ERR_BLK_CNTR", 0, 14 },
+ { "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_1", 0x354c8, 0 },
+ { "LANE_ALIGN_STATUS", 12, 1 },
+ { "LANE_3_BLK_LCK", 3, 1 },
+ { "LANE_2_BLK_LC32_6431K", 2, 1 },
+ { "LANE_1_BLK_LCK", 1, 1 },
+ { "LANE_0_BLK_LCK", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_2", 0x354cc, 0 },
+ { "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_3", 0x354d0, 0 },
+ { "LANE_3_ALIGN_MRKR_LCK", 3, 1 },
+ { "LANE_2_ALIGN_MRKR_LCK", 2, 1 },
+ { "LANE_1_ALIGN_MRKR_LCK", 1, 1 },
+ { "LANE_0_ALIGN_MRKR_LCK", 0, 1 },
+ { "MAC_PORT_MTIP_KR4_MULTI_LANE_ALIGN_STATUS_4", 0x354d4, 0 },
+ { "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_0", 0x35720, 0 },
+ { "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_1", 0x35724, 0 },
+ { "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_2", 0x35728, 0 },
+ { "MAC_PORT_MTIP_KR4_BIP_ERR_CNT_LANE_3", 0x3572c, 0 },
+ { "MAC_PORT_MTIP_KR4_LANE_0_MAPPING", 0x35a40, 0 },
+ { "MAC_PORT_MTIP_KR4_LANE_1_MAPPING", 0x35a44, 0 },
+ { "MAC_PORT_MTIP_KR4_LANE_2_MAPPING", 0x35a48, 0 },
+ { "MAC_PORT_MTIP_KR4_LANE_3_MAPPING", 0x35a4c, 0 },
+ { "MAC_PORT_MTIP_KR4_SCRATCH", 0x35af0, 0 },
+ { "MAC_PORT_MTIP_KR4_CORE_REVISION", 0x35af4, 0 },
+ { "MAC_PORT_MTIP_KR4_VL_INTVL", 0x35af8, 0 },
+ { "MAC_PORT_MTIP_KR4_TX_LANE_THRESH", 0x35afc, 0 },
+ { "MAC_PORT_MTIP_CR4_CONTROL_1", 0x35b00, 0 },
+ { "Reset", 15, 1 },
+ { "Loopback", 14, 1 },
+ { "Speed_selection", 13, 1 },
+ { "Low_power", 11, 1 },
+ { "Speed_selection1", 6, 1 },
+ { "Speed_selection2", 2, 4 },
+ { "MAC_PORT_MTIP_CR4_STATUS_1", 0x35b04, 0 },
+ { "Fault", 7, 1 },
+ { "RX_Link_Status", 2, 1 },
+ { "Low_power_ability", 1, 1 },
+ { "MAC_PORT_MTIP_CR4_DEVICE_ID0", 0x35b08, 0 },
+ { "MAC_PORT_MTIP_CR4_DEVICE_ID1", 0x35b0c, 0 },
+ { "MAC_PORT_MTIP_CR4_SPEED_ABILITY", 0x35b10, 0 },
+ { "100G_capable", 8, 1 },
+ { "40G_capable", 7, 1 },
+ { "10PASS_TS_2Base_TL_capable", 1, 1 },
+ { "10G_capable", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG1", 0x35b14, 0 },
+ { "TC_present", 6, 1 },
+ { "DTE_xS_present", 5, 1 },
+ { "PHY_xS_present", 4, 1 },
+ { "PCS_present", 3, 1 },
+ { "WIS_present", 2, 1 },
+ { "PMD_PMA_present", 1, 1 },
+ { "Clause22reg_present", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_DEVICES_IN_PKG2", 0x35b18, 0 },
+ { "VSD_2_PRESENT", 15, 1 },
+ { "VSD_1_PRESENT", 14, 1 },
+ { "Clause22_ExT_Present", 13, 1 },
+ { "MAC_PORT_MTIP_CR4_CONTROL_2", 0x35b1c, 0 },
+ { "MAC_PORT_MTIP_CR4_STATUS_2", 0x35b20, 0 },
+ { "Device_present", 14, 2 },
+ { "Transmit_fault", 11, 1 },
+ { "Receive_fault", 10, 1 },
+ { "100GBase_R_capable", 5, 1 },
+ { "40GBase_R_capable", 4, 1 },
+ { "10GBase_T_capable", 3, 1 },
+ { "10GBase_W_capable", 2, 1 },
+ { "10GBase_x_capable", 1, 1 },
+ { "10GBase_R_capable", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_PKG_ID0", 0x35b38, 0 },
+ { "MAC_PORT_MTIP_CR4_PKG_ID1", 0x35b3c, 0 },
+ { "MAC_PORT_MTIP_CR4_BASE_R_STATUS_1", 0x35b80, 0 },
+ { "RX_Link_STAT", 12, 1 },
+ { "High_BER", 1, 1 },
+ { "Block_Lock", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_BASE_R_STATUS_2", 0x35b84, 0 },
+ { "Latched_block_lock", 15, 1 },
+ { "Latched_high_BER", 14, 1 },
+ { "BER_counter", 8, 6 },
+ { "Errored_blocks_cntr", 0, 8 },
+ { "MAC_PORT_MTIP_CR4_BASE_R_TEST_CONTROL", 0x35ba8, 0 },
+ { "Scrambled_ID_TP_EN", 7, 1 },
+ { "MAC_PORT_MTIP_CR4_BASE_R_TEST_ERR_CNT", 0x35bac, 0 },
+ { "MAC_PORT_MTIP_CR4_BER_HIGH_ORDER_CNT", 0x35bb0, 0 },
+ { "MAC_PORT_MTIP_CR4_ERR_BLK_HIGH_ORDER_CNT", 0x35bb4, 0 },
+ { "Hi_ORDER_CNT_Present", 15, 1 },
+ { "ERR_BLKS_CNTR", 0, 14 },
+ { "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_1", 0x35bc8, 0 },
+ { "LANE_ALIGN_STAT", 12, 1 },
+ { "Lane_7_blck_lck", 7, 1 },
+ { "Lane_6_blck_lck", 6, 1 },
+ { "Lane_5_blck_lck", 5, 1 },
+ { "Lane_4_blck_lck", 4, 1 },
+ { "Lane_3_blck_lck", 3, 1 },
+ { "Lane_2_blck_lck", 2, 1 },
+ { "Lane_1_blck_lck", 1, 1 },
+ { "Lane_0_blck_lck", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_2", 0x35bcc, 0 },
+ { "Lane_19_blck_lck", 11, 1 },
+ { "Lane_18_blck_lck", 10, 1 },
+ { "Lane_17_blck_lck", 9, 1 },
+ { "Lane_16_blck_lck", 8, 1 },
+ { "Lane_15_blck_lck", 7, 1 },
+ { "Lane_14_blck_lck", 6, 1 },
+ { "Lane_13_blck_lck", 5, 1 },
+ { "Lane_12_blck_lck", 4, 1 },
+ { "Lane_11_blck_lck", 3, 1 },
+ { "Lane_10_blck_lck", 2, 1 },
+ { "Lane_9_blck_lck", 1, 1 },
+ { "Lane_8_blck_lck", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_3", 0x35bd0, 0 },
+ { "Lane7_algn_mrkr_lck", 7, 1 },
+ { "Lane6_algn_mrkr_lck", 6, 1 },
+ { "Lane5_algn_mrkr_lck", 5, 1 },
+ { "Lane4_algn_mrkr_lck", 4, 1 },
+ { "Lane3_algn_mrkr_lck", 3, 1 },
+ { "Lane2_algn_mrkr_lck", 2, 1 },
+ { "Lane1_algn_mrkr_lck", 1, 1 },
+ { "Lane0_algn_mrkr_lck", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_MULTI_LANE_ALIGN_STATUS_4", 0x35bd4, 0 },
+ { "Lane19_algn_mrkr_lck", 11, 1 },
+ { "Lane18_algn_mrkr_lck", 10, 1 },
+ { "Lane17_algn_mrkr_lck", 9, 1 },
+ { "Lane16_algn_mrkr_lck", 8, 1 },
+ { "Lane15_algn_mrkr_lck", 7, 1 },
+ { "Lane14_algn_mrkr_lck", 6, 1 },
+ { "Lane13_algn_mrkr_lck", 5, 1 },
+ { "Lane12_algn_mrkr_lck", 4, 1 },
+ { "Lane11_algn_mrkr_lck", 3, 1 },
+ { "Lane10_algn_mrkr_lck", 2, 1 },
+ { "Lane9_algn_mrkr_lck", 1, 1 },
+ { "Lane8_algn_mrkr_lck", 0, 1 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_0", 0x35e20, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_1", 0x35e24, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_2", 0x35e28, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_3", 0x35e2c, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_4", 0x35e30, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_5", 0x35e34, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_6", 0x35e38, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_7", 0x35e3c, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_8", 0x35e40, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_9", 0x35e44, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_10", 0x35e48, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_11", 0x35e4c, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_12", 0x35e50, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_13", 0x35e54, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_14", 0x35e58, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_15", 0x35e5c, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_16", 0x35e60, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_17", 0x35e64, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_18", 0x35e68, 0 },
+ { "MAC_PORT_MTIP_CR4_BIP_ERR_CNTLANE_19", 0x35e6c, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_0_MAPPING", 0x36140, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_1_MAPPING", 0x36144, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_2_MAPPING", 0x36148, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_3_MAPPING", 0x3614c, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_4_MAPPING", 0x36150, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_5_MAPPING", 0x36154, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_6_MAPPING", 0x36158, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_7_MAPPING", 0x3615c, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_8_MAPPING", 0x36160, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_9_MAPPING", 0x36164, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_10_MAPPING", 0x36168, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_11_MAPPING", 0x3616c, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_12_MAPPING", 0x36170, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_13_MAPPING", 0x36174, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_14_MAPPING", 0x36178, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_15_MAPPING", 0x3617c, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_16_MAPPING", 0x36180, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_17_MAPPING", 0x36184, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_18_MAPPING", 0x36188, 0 },
+ { "MAC_PORT_MTIP_CR4_LANE_19_MAPPING", 0x3618c, 0 },
+ { "MAC_PORT_MTIP_CR4_SCRATCH", 0x361f0, 0 },
+ { "MAC_PORT_MTIP_CR4_CORE_REVISION", 0x361f4, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_CONTROL", 0x36200, 0 },
+ { "RS_FEC_Bypass_Error_Indication", 1, 1 },
+ { "RS_FEC_Bypass_Correction", 0, 1 },
+ { "MAC_PORT_MTIP_RS_FEC_STATUS", 0x36204, 0 },
+ { "RS_FEC_PCS_align_status", 15, 1 },
+ { "fec_align_status", 14, 1 },
+ { "RS_FEC_high_SER", 2, 1 },
+ { "RS_FEC_bypass_error_indication_ability", 1, 1 },
+ { "RS_FEC_bypass_correction_ability", 0, 1 },
+ { "MAC_PORT_MTIP_RS_FEC_CCW_LO", 0x36208, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_CCW_HI", 0x3620c, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_NCCW_LO", 0x36210, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_NCCW_HI", 0x36214, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_LANEMAPRS_FEC_NCCW_HI", 0x36218, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_LO", 0x36228, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR0_HI", 0x3622c, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_LO", 0x36230, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR1_HI", 0x36234, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_LO", 0x36238, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR2_HI", 0x3623c, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_LO", 0x36240, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_SYMBLERR3_HI", 0x36244, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_CONTROL", 0x36400, 0 },
+ { "RS_FEC_enabled_status", 15, 1 },
+ { "RS_FEC_Enable", 2, 1 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_1", 0x36404, 0 },
+ { "deskew_empty", 12, 4 },
+ { "fec_align_status_lh", 10, 1 },
+ { "tx_dp_overflow", 9, 1 },
+ { "rx_dp_overflow", 8, 1 },
+ { "tx_datapath_restart", 7, 1 },
+ { "rx_datapath_restart", 6, 1 },
+ { "marker_check_restart", 5, 1 },
+ { "fec_align_status_ll", 4, 1 },
+ { "amps_lock", 0, 4 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_INFO_2", 0x36408, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_REVISION", 0x3640c, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_KEY", 0x36410, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_SYMBOLS", 0x36414, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_PATTERN", 0x36418, 0 },
+ { "MAC_PORT_MTIP_RS_FEC_VENDOR_TX_TEST_TRIGGER", 0x3641c, 0 },
+ { "MAC_PORT_MTIP_FEC_ABILITY", 0x36618, 0 },
+ { "BASE_R_FEC_Error_Indication_Ability", 1, 1 },
+ { "BASE_R_FEC_Ability", 0, 1 },
+ { "MAC_PORT_FEC_CONTROL", 0x3661c, 0 },
+ { "fec_en_err_ind", 1, 1 },
+ { "fec_en", 0, 1 },
+ { "MAC_PORT_FEC_STATUS", 0x36620, 0 },
+ { "FEC_LOCKED0", 1, 4 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_MTIP_FEC0_CERR_CNT_0", 0x36624, 0 },
+ { "MAC_PORT_MTIP_FEC0_CERR_CNT_1", 0x36628, 0 },
+ { "MAC_PORT_MTIP_FEC0_NCERR_CNT_0", 0x3662c, 0 },
+ { "MAC_PORT_MTIP_FEC0_NCERR_CNT_1", 0x36630, 0 },
+ { "MAC_PORT_MTIP_FEC_STATUS1", 0x36664, 0 },
+ { "FEC_LOCKED0", 1, 4 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_MTIP_FEC1_CERR_CNT_0", 0x36668, 0 },
+ { "MAC_PORT_MTIP_FEC1_CERR_CNT_1", 0x3666c, 0 },
+ { "MAC_PORT_MTIP_FEC1_NCERR_CNT_0", 0x36670, 0 },
+ { "MAC_PORT_MTIP_FEC1_NCERR_CNT_1", 0x36674, 0 },
+ { "MAC_PORT_MTIP_FEC_STATUS2", 0x366a8, 0 },
+ { "FEC_LOCKED0", 1, 4 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_MTIP_FEC2_CERR_CNT_0", 0x366ac, 0 },
+ { "MAC_PORT_MTIP_FEC2_CERR_CNT_1", 0x366b0, 0 },
+ { "MAC_PORT_MTIP_FEC2_NCERR_CNT_0", 0x366b4, 0 },
+ { "MAC_PORT_MTIP_FEC2_NCERR_CNT_1", 0x366b8, 0 },
+ { "MAC_PORT_MTIP_FEC_STATUS3", 0x366ec, 0 },
+ { "FEC_LOCKED0", 1, 4 },
+ { "FEC_LOCKED", 0, 1 },
+ { "MAC_PORT_MTIP_FEC3_CERR_CNT_0", 0x366f0, 0 },
+ { "MAC_PORT_MTIP_FEC3_CERR_CNT_1", 0x366f4, 0 },
+ { "MAC_PORT_MTIP_FEC3_NCERR_CNT_0", 0x366f8, 0 },
+ { "MAC_PORT_MTIP_FEC3_NCERR_CNT_1", 0x366fc, 0 },
+ { "MAC_PORT_BEAN_CTL", 0x36c00, 0 },
+ { "AN_RESET", 15, 1 },
+ { "EXT_NXP_CTRL", 13, 1 },
+ { "BEAN_EN", 12, 1 },
+ { "RESTART_BEAN", 9, 1 },
+ { "MAC_PORT_BEAN_STATUS", 0x36c04, 0 },
+ { "PDF", 9, 1 },
+ { "EXT_NXP_STATUS", 7, 1 },
+ { "PAGE_RCVD", 6, 1 },
+ { "BEAN_COMPLETE", 5, 1 },
+ { "REM_FAULT_STATUS", 4, 1 },
+ { "BEAN_ABILITY", 3, 1 },
+ { "LINK_STATUS", 2, 1 },
+ { "LP_BEAN_ABILITY", 0, 1 },
+ { "MAC_PORT_BEAN_ABILITY_0", 0x36c08, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_1", 0x36c0c, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_ABILITY_2", 0x36c10, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_REM_ABILITY_0", 0x36c14, 0 },
+ { "NXP", 15, 1 },
+ { "ACK", 14, 1 },
+ { "REM_FAULT", 13, 1 },
+ { "PAUSE_ABILITY", 10, 3 },
+ { "ECHO_NONCE", 5, 5 },
+ { "SELECTOR", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_1", 0x36c18, 0 },
+ { "TECH_ABILITY_1", 5, 11 },
+ { "TX_NONCE", 0, 5 },
+ { "MAC_PORT_BEAN_REM_ABILITY_2", 0x36c1c, 0 },
+ { "T5_FEC_ABILITY", 14, 2 },
+ { "TECH_ABILITY_2", 0, 14 },
+ { "MAC_PORT_BEAN_MS_COUNT", 0x36c20, 0 },
+ { "MAC_PORT_BEAN_XNP_0", 0x36c24, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_BEAN_XNP_1", 0x36c28, 0 },
+ { "MAC_PORT_BEAN_XNP_2", 0x36c2c, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_0", 0x36c30, 0 },
+ { "XNP", 15, 1 },
+ { "ACKNOWLEDGE", 14, 1 },
+ { "MP", 13, 1 },
+ { "ACK2", 12, 1 },
+ { "TOGGLE", 11, 1 },
+ { "MU", 0, 11 },
+ { "MAC_PORT_LP_BEAN_XNP_1", 0x36c34, 0 },
+ { "MAC_PORT_LP_BEAN_XNP_2", 0x36c38, 0 },
+ { "MAC_PORT_BEAN_ETH_STATUS", 0x36c3c, 0 },
+ { "100GCR4", 11, 1 },
+ { "100GKR4", 10, 1 },
+ { "100GKP4", 9, 1 },
+ { "100GCR10", 8, 1 },
+ { "40GCR4", 6, 1 },
+ { "40GKR4", 5, 1 },
+ { "FEC", 4, 1 },
+ { "10GKR", 3, 1 },
+ { "10GKX4", 2, 1 },
+ { "1GKX", 1, 1 },
+ { "MAC_PORT_AE_RX_COEF_REQ", 0x36a00, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C3", 6, 2 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT", 0x36a04, 0 },
+ { "T5_AE0_RXSTAT_RDY", 15, 1 },
+ { "T5_AE0_RXSTAT_LSNA", 14, 1 },
+ { "T5_AE0_RXSTAT_FEC", 13, 1 },
+ { "T5_AE0_RXSTAT_TF", 12, 1 },
+ { "T5_AE0_RXSTAT_C3", 6, 2 },
+ { "T5_AE0_RXSTAT_C2", 4, 2 },
+ { "T5_AE0_RXSTAT_C1", 2, 2 },
+ { "T5_AE0_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ", 0x36a08, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "TXREQ_FEC", 11, 1 },
+ { "T5_TXREQ_C3", 6, 2 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT", 0x36a0c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C3", 6, 2 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE", 0x36a10, 0 },
+ { "SET_WAIT_TIMER", 13, 2 },
+ { "C2_C3_STATE_SEL", 12, 1 },
+ { "FFE4_EN", 11, 1 },
+ { "FEC_REQUEST", 10, 1 },
+ { "FEC_SUPPORTED", 9, 1 },
+ { "TX_FIXED", 8, 1 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL", 0x36a14, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL", 0x36a18, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE", 0x36a1c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_1", 0x36a20, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C3", 6, 2 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_1", 0x36a24, 0 },
+ { "T5_AE1_RXSTAT_RDY", 15, 1 },
+ { "T5_AE1_RXSTAT_LSNA", 14, 1 },
+ { "T5_AE1_RXSTAT_FEC", 13, 1 },
+ { "T5_AE1_RXSTAT_TF", 12, 1 },
+ { "T5_AE1_RXSTAT_C3", 6, 2 },
+ { "T5_AE1_RXSTAT_C2", 4, 2 },
+ { "T5_AE1_RXSTAT_C1", 2, 2 },
+ { "T5_AE1_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_1", 0x36a28, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "TXREQ_FEC", 11, 1 },
+ { "T5_TXREQ_C3", 6, 2 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_1", 0x36a2c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C3", 6, 2 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_1", 0x36a30, 0 },
+ { "SET_WAIT_TIMER", 13, 2 },
+ { "C2_C3_STATE_SEL", 12, 1 },
+ { "FFE4_EN", 11, 1 },
+ { "FEC_REQUEST", 10, 1 },
+ { "FEC_SUPPORTED", 9, 1 },
+ { "TX_FIXED", 8, 1 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_1", 0x36a34, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_1", 0x36a38, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_1", 0x36a3c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_2", 0x36a40, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C3", 6, 2 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_2", 0x36a44, 0 },
+ { "T5_AE2_RXSTAT_RDY", 15, 1 },
+ { "T5_AE2_RXSTAT_LSNA", 14, 1 },
+ { "T5_AE2_RXSTAT_FEC", 13, 1 },
+ { "T5_AE2_RXSTAT_TF", 12, 1 },
+ { "T5_AE2_RXSTAT_C3", 6, 2 },
+ { "T5_AE2_RXSTAT_C2", 4, 2 },
+ { "T5_AE2_RXSTAT_C1", 2, 2 },
+ { "T5_AE2_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_2", 0x36a48, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "TXREQ_FEC", 11, 1 },
+ { "T5_TXREQ_C3", 6, 2 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_2", 0x36a4c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C3", 6, 2 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_2", 0x36a50, 0 },
+ { "SET_WAIT_TIMER", 13, 2 },
+ { "C2_C3_STATE_SEL", 12, 1 },
+ { "FFE4_EN", 11, 1 },
+ { "FEC_REQUEST", 10, 1 },
+ { "FEC_SUPPORTED", 9, 1 },
+ { "TX_FIXED", 8, 1 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_2", 0x36a54, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_2", 0x36a58, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_2", 0x36a5c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_RX_COEF_REQ_3", 0x36a60, 0 },
+ { "RXREQ_CPRE", 13, 1 },
+ { "RXREQ_CINIT", 12, 1 },
+ { "T5_RXREQ_C3", 6, 2 },
+ { "T5_RXREQ_C2", 4, 2 },
+ { "T5_RXREQ_C1", 2, 2 },
+ { "T5_RXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_RX_COEF_STAT_3", 0x36a64, 0 },
+ { "T5_AE3_RXSTAT_RDY", 15, 1 },
+ { "T5_AE3_RXSTAT_LSNA", 14, 1 },
+ { "T5_AE3_RXSTAT_FEC", 13, 1 },
+ { "T5_AE3_RXSTAT_TF", 12, 1 },
+ { "T5_AE3_RXSTAT_C3", 6, 2 },
+ { "T5_AE3_RXSTAT_C2", 4, 2 },
+ { "T5_AE3_RXSTAT_C1", 2, 2 },
+ { "T5_AE3_RXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_REQ_3", 0x36a68, 0 },
+ { "TXREQ_CPRE", 13, 1 },
+ { "TXREQ_CINIT", 12, 1 },
+ { "TXREQ_FEC", 11, 1 },
+ { "T5_TXREQ_C3", 6, 2 },
+ { "T5_TXREQ_C2", 4, 2 },
+ { "T5_TXREQ_C1", 2, 2 },
+ { "T5_TXREQ_C0", 0, 2 },
+ { "MAC_PORT_AE_TX_COEF_STAT_3", 0x36a6c, 0 },
+ { "TXSTAT_RDY", 15, 1 },
+ { "T5_TXSTAT_C3", 6, 2 },
+ { "T5_TXSTAT_C2", 4, 2 },
+ { "T5_TXSTAT_C1", 2, 2 },
+ { "T5_TXSTAT_C0", 0, 2 },
+ { "MAC_PORT_AE_REG_MODE_3", 0x36a70, 0 },
+ { "SET_WAIT_TIMER", 13, 2 },
+ { "C2_C3_STATE_SEL", 12, 1 },
+ { "FFE4_EN", 11, 1 },
+ { "FEC_REQUEST", 10, 1 },
+ { "FEC_SUPPORTED", 9, 1 },
+ { "TX_FIXED", 8, 1 },
+ { "AET_RSVD", 7, 1 },
+ { "AET_ENABLE", 6, 1 },
+ { "MAN_DEC", 4, 2 },
+ { "MANUAL_RDY", 3, 1 },
+ { "MWT_DISABLE", 2, 1 },
+ { "MDIO_OVR", 1, 1 },
+ { "STICKY_MODE", 0, 1 },
+ { "MAC_PORT_AE_PRBS_CTL_3", 0x36a74, 0 },
+ { "PRBS_CHK_ERRCNT", 8, 8 },
+ { "PRBS_SYNCCNT", 5, 3 },
+ { "PRBS_CHK_SYNC", 4, 1 },
+ { "PRBS_CHK_RST", 3, 1 },
+ { "PRBS_CHK_OFF", 2, 1 },
+ { "PRBS_GEN_FRCERR", 1, 1 },
+ { "PRBS_GEN_OFF", 0, 1 },
+ { "MAC_PORT_AE_FSM_CTL_3", 0x36a78, 0 },
+ { "CIN_ENABLE", 15, 1 },
+ { "FSM_TR_LCL", 14, 1 },
+ { "FSM_GDMRK", 11, 3 },
+ { "FSM_BADMRK", 8, 3 },
+ { "FSM_TR_FAIL", 7, 1 },
+ { "FSM_TR_ACT", 6, 1 },
+ { "FSM_FRM_LCK", 5, 1 },
+ { "FSM_TR_COMP", 4, 1 },
+ { "MC_RX_RDY", 3, 1 },
+ { "FSM_CU_DIS", 2, 1 },
+ { "FSM_TR_RST", 1, 1 },
+ { "FSM_TR_EN", 0, 1 },
+ { "MAC_PORT_AE_FSM_STATE_3", 0x36a7c, 0 },
+ { "CC2FSM_STATE", 13, 3 },
+ { "CC1FSM_STATE", 10, 3 },
+ { "CC0FSM_STATE", 7, 3 },
+ { "FLFSM_STATE", 4, 3 },
+ { "TFSM_STATE", 0, 3 },
+ { "MAC_PORT_AE_TX_DIS", 0x36a80, 0 },
+ { "MAC_PORT_AE_KR_CTRL", 0x36a84, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET", 0x36a88, 0 },
+ { "MAC_PORT_AE_KR_STATUS", 0x36a8c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_1", 0x36a90, 0 },
+ { "MAC_PORT_AE_KR_CTRL_1", 0x36a94, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_1", 0x36a98, 0 },
+ { "MAC_PORT_AE_KR_STATUS_1", 0x36a9c, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_2", 0x36aa0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_2", 0x36aa4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_2", 0x36aa8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_2", 0x36aac, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AE_TX_DIS_3", 0x36ab0, 0 },
+ { "MAC_PORT_AE_KR_CTRL_3", 0x36ab4, 0 },
+ { "Training_Enable", 1, 1 },
+ { "Restart_Training", 0, 1 },
+ { "MAC_PORT_AE_RX_SIGDET_3", 0x36ab8, 0 },
+ { "MAC_PORT_AE_KR_STATUS_3", 0x36abc, 0 },
+ { "Training_Failure", 3, 1 },
+ { "Training", 2, 1 },
+ { "Frame_Lock", 1, 1 },
+ { "RX_Trained", 0, 1 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x36b00, 0 },
+ { "INIT_METH", 12, 4 },
+ { "INIT_CNT", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_N0", 5, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x36b04, 0 },
+ { "FEC_CNV", 15, 1 },
+ { "EN_RETRY", 14, 1 },
+ { "DPC_METH", 12, 2 },
+ { "EN_P2", 11, 1 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_0", 0x36b08, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x36b0c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT5", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_0", 0x36b10, 0 },
+ { "CTRL_STAT", 8, 5 },
+ { "NEU_STATE", 4, 4 },
+ { "CTRL_STATE", 0, 4 },
+ { "MAC_PORT_AET_STATUS_20", 0x36b14, 0 },
+ { "MAC_PORT_AET_LIMITS0", 0x36b18, 0 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x36b20, 0 },
+ { "INIT_METH", 12, 4 },
+ { "INIT_CNT", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_N0", 5, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x36b24, 0 },
+ { "FEC_CNV", 15, 1 },
+ { "EN_RETRY", 14, 1 },
+ { "DPC_METH", 12, 2 },
+ { "EN_P2", 11, 1 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_1", 0x36b28, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x36b2c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT5", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_1", 0x36b30, 0 },
+ { "CTRL_STAT", 8, 5 },
+ { "NEU_STATE", 4, 4 },
+ { "CTRL_STATE", 0, 4 },
+ { "MAC_PORT_AET_STATUS_21", 0x36b34, 0 },
+ { "MAC_PORT_AET_LIMITS1", 0x36b38, 0 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x36b40, 0 },
+ { "INIT_METH", 12, 4 },
+ { "INIT_CNT", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_N0", 5, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x36b44, 0 },
+ { "FEC_CNV", 15, 1 },
+ { "EN_RETRY", 14, 1 },
+ { "DPC_METH", 12, 2 },
+ { "EN_P2", 11, 1 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_2", 0x36b48, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x36b4c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT5", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_2", 0x36b50, 0 },
+ { "CTRL_STAT", 8, 5 },
+ { "NEU_STATE", 4, 4 },
+ { "CTRL_STATE", 0, 4 },
+ { "MAC_PORT_AET_STATUS_22", 0x36b54, 0 },
+ { "MAC_PORT_AET_LIMITS2", 0x36b58, 0 },
+ { "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x36b60, 0 },
+ { "INIT_METH", 12, 4 },
+ { "INIT_CNT", 8, 4 },
+ { "EN_ZFE", 7, 1 },
+ { "EN_GAIN_TOG", 6, 1 },
+ { "EN_AI_N0", 5, 1 },
+ { "EN_H1T_EQ", 3, 1 },
+ { "H1TEQ_GOAL", 0, 3 },
+ { "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x36b64, 0 },
+ { "FEC_CNV", 15, 1 },
+ { "EN_RETRY", 14, 1 },
+ { "DPC_METH", 12, 2 },
+ { "EN_P2", 11, 1 },
+ { "GAIN_TH", 6, 5 },
+ { "EN_SD_TH", 5, 1 },
+ { "EN_AMIN_TH", 4, 1 },
+ { "AMIN_TH", 0, 4 },
+ { "MAC_PORT_AET_ZFE_LIMITS_3", 0x36b68, 0 },
+ { "ACC_LIM", 8, 4 },
+ { "CNV_LIM", 4, 4 },
+ { "TOG_LIM", 0, 4 },
+ { "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x36b6c, 0 },
+ { "BOOT_LUT7", 12, 4 },
+ { "BOOT_LUT5", 8, 4 },
+ { "BOOT_LUT45", 4, 4 },
+ { "BOOT_LUT0123", 2, 2 },
+ { "BOOT_DEC_C0", 1, 1 },
+ { "MAC_PORT_AET_STATUS_3", 0x36b70, 0 },
+ { "CTRL_STAT", 8, 5 },
+ { "NEU_STATE", 4, 4 },
+ { "CTRL_STATE", 0, 4 },
+ { "MAC_PORT_AET_STATUS_23", 0x36b74, 0 },
+ { "MAC_PORT_AET_LIMITS3", 0x36b78, 0 },
+ { "MAC_PORT_ANALOG_TEST_MUX", 0x37814, 0 },
+ { "MAC_PORT_PLLREFSEL_CONTROL", 0x37854, 0 },
+ { "MAC_PORT_REFISINK_CONTROL", 0x37858, 0 },
+ { "MAC_PORT_REFISRC_CONTROL", 0x3785c, 0 },
+ { "MAC_PORT_REFVREG_CONTROL", 0x37860, 0 },
+ { "MAC_PORT_VBGENDOC_CONTROL", 0x37864, 0 },
+ { "BGCLKSEL", 2, 1 },
+ { "VBGENDOC", 0, 2 },
+ { "MAC_PORT_VREFTUNE_CONTROL", 0x37868, 0 },
+ { "MAC_PORT_IMPEDENCE_CALIBRATION_CONTROL", 0x37880, 0 },
+ { "FRCCAL_COMP", 6, 1 },
+ { "FRCERR", 5, 1 },
+ { "CAL_BISTENAB", 4, 1 },
+ { "RCAL_RESET", 0, 1 },
+ { "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_1", 0x37884, 0 },
+ { "RCALBENAB", 3, 1 },
+ { "RCALBUSY", 2, 1 },
+ { "RCALERR", 1, 1 },
+ { "RCALCOMP", 0, 1 },
+ { "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_2", 0x37888, 0 },
+ { "MAC_PORT_IMPEDENCE_CALIBRATION_STATUS_3", 0x3788c, 0 },
+ { "MAC_PORT_INEQUALITY_CONTROL_AND_RESULT", 0x378c0, 0 },
+ { "ISGT", 7, 1 },
+ { "ISLT", 6, 1 },
+ { "ISEQ", 5, 1 },
+ { "ISVAL", 3, 2 },
+ { "GTORLT", 1, 2 },
+ { "INEQ", 0, 1 },
+ { "MAC_PORT_INEQUALITY_LOW_LIMIT", 0x378c4, 0 },
+ { "MAC_PORT_INEQUALITY_LOW_LIMIT_MASK", 0x378c8, 0 },
+ { "MAC_PORT_INEQUALITY_HIGH_LIMIT", 0x378cc, 0 },
+ { "MAC_PORT_INEQUALITY_HIGH_LIMIT_MASK", 0x378d0, 0 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_6", 0x378e8, 0 },
+ { "JTAGMD", 3, 1 },
+ { "RXACMODE", 2, 1 },
+ { "HSSACJPC", 1, 1 },
+ { "HSSACJAC", 0, 1 },
+ { "MAC_PORT_MACRO_TEST_CONTROL_5", 0x378ec, 0 },
+ { "REFVALIDD", 6, 1 },
+ { "REFVALIDC", 5, 1 },
+ { "REFVALIDB", 4, 1 },
+ { "REFVALIDA", 3, 1 },
+ { "REFSELRESET", 2, 1 },
+ { "SOFTRESET", 1, 1 },
+ { "MACROTEST", 0, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x37b00, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x37b04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x37b08, 0 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x37b0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x37b10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLA_POWER_CONTROL", 0x37b24, 0 },
+ { "SPWRENA", 1, 1 },
+ { "NPWRENA", 0, 1 },
+ { "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x37b28, 0 },
+ { "MAC_PORT_PLLA_PLL_MICELLANEOUS_CONTROL", 0x37b38, 0 },
+ { "MAC_PORT_PLLA_PCLK_CONTROL", 0x37b3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x37b40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x37b44, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x37b48, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x37b4c, 0 },
+ { "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x37b50, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x37bf0, 0 },
+ { "PLLDIVA", 4, 1 },
+ { "REFDIV", 0, 4 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x37bf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x37bf8, 0 },
+ { "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x37bfc, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x37c00, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x37c04, 0 },
+ { "LDET", 4, 1 },
+ { "CCERR", 3, 1 },
+ { "CCCMP", 2, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x37c08, 0 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x37c0c, 0 },
+ { "FMIN", 3, 1 },
+ { "FMAX", 2, 1 },
+ { "CVHOLD", 1, 1 },
+ { "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x37c10, 0 },
+ { "CMETH", 2, 1 },
+ { "RECAL", 1, 1 },
+ { "CCLD", 0, 1 },
+ { "MAC_PORT_PLLB_POWER_CONTROL", 0x37c24, 0 },
+ { "SPWRENA", 1, 1 },
+ { "NPWRENA", 0, 1 },
+ { "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x37c28, 0 },
+ { "MAC_PORT_PLLB_PLL_MICELLANEOUS_CONTROL", 0x37c38, 0 },
+ { "MAC_PORT_PLLB_PCLK_CONTROL", 0x37c3c, 0 },
+ { "SPEDIV", 3, 5 },
+ { "PCKSEL", 0, 3 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x37c40, 0 },
+ { "EMIL", 2, 1 },
+ { "EMID", 1, 1 },
+ { "EMIS", 0, 1 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x37c44, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x37c48, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x37c4c, 0 },
+ { "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x37c50, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x37cf0, 0 },
+ { "PLLDIVA", 4, 1 },
+ { "REFDIV", 0, 4 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x37cf4, 0 },
+ { "RESYNC", 6, 1 },
+ { "RXCLKSEL", 5, 1 },
+ { "FRCBAND", 4, 1 },
+ { "PLLBYP", 3, 1 },
+ { "VCOSEL", 1, 1 },
+ { "DIVSEL8", 0, 1 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x37cf8, 0 },
+ { "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x37cfc, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x37000, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_RXLOOP", 5, 1 },
+ { "T5_TX_ENFFE4", 4, 1 },
+ { "T5_TX_BWSEL", 2, 2 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x37004, 0 },
+ { "SPSEL", 11, 3 },
+ { "FRCERR", 10, 1 },
+ { "ERROR", 9, 1 },
+ { "SYNC", 8, 1 },
+ { "P7CHK", 5, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x37008, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "SASMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3700c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37010, 0 },
+ { "T5DCCEN", 4, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37014, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37018, 0 },
+ { "CALSSTN", 8, 6 },
+ { "CALSSTP", 0, 6 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3701c, 0 },
+ { "DRTOL", 2, 3 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x37020, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x37024, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x37028, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_3_COEFFICIENT", 0x3702c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x37034, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37038, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "SASCMD", 10, 2 },
+ { "C0UPDT", 6, 2 },
+ { "C3UPDT", 4, 2 },
+ { "C2UPDT", 2, 2 },
+ { "C1UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3703c, 0 },
+ { "C0STAT", 6, 2 },
+ { "C3STAT", 4, 2 },
+ { "C2STAT", 2, 2 },
+ { "C1STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37040, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37044, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37048, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3704c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37050, 0 },
+ { "ATUNEN", 8, 8 },
+ { "ATUNEP", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37058, 0 },
+ { "DCCCOMPINV", 8, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_4X_SEGMENT_APPLIED", 0x37060, 0 },
+ { "AS4X7", 14, 2 },
+ { "AS4X6", 12, 2 },
+ { "AS4X5", 10, 2 },
+ { "AS4X4", 8, 2 },
+ { "AS4X3", 6, 2 },
+ { "AS4X2", 4, 2 },
+ { "AS4X1", 2, 2 },
+ { "AS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_2X_SEGMENT_APPLIED", 0x37064, 0 },
+ { "AS2X3", 6, 2 },
+ { "AS2X2", 4, 2 },
+ { "AS2X1", 2, 2 },
+ { "AS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_1X_SEGMENT_APPLIED", 0x37068, 0 },
+ { "AS1X7", 14, 2 },
+ { "AS1X6", 12, 2 },
+ { "AS1X5", 10, 2 },
+ { "AS1X4", 8, 2 },
+ { "AS1X3", 6, 2 },
+ { "AS1X2", 4, 2 },
+ { "AS1X1", 2, 2 },
+ { "AS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3706c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37070, 0 },
+ { "AT2X", 8, 4 },
+ { "AT4X", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37074, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37078, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3707c, 0 },
+ { "XADDR", 1, 5 },
+ { "XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37080, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37084, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37088, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3708c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3709c, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x370a0, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 13, 2 },
+ { "DCCLOCK", 11, 2 },
+ { "DCCOFFSET", 8, 3 },
+ { "DCCSTEP", 6, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x370a4, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x370a8, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x370ac, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SIGN_OVERRIDE", 0x370c0, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x370c8, 0 },
+ { "OS4X7", 14, 2 },
+ { "OS4X6", 12, 2 },
+ { "OS4X5", 10, 2 },
+ { "OS4X4", 8, 2 },
+ { "OS4X3", 6, 2 },
+ { "OS4X2", 4, 2 },
+ { "OS4X1", 2, 2 },
+ { "OS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x370cc, 0 },
+ { "OS2X3", 6, 2 },
+ { "OS2X2", 4, 2 },
+ { "OS2X1", 2, 2 },
+ { "OS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x370d0, 0 },
+ { "OS1X7", 14, 2 },
+ { "OS1X6", 12, 2 },
+ { "OS1X5", 10, 2 },
+ { "OS1X4", 8, 2 },
+ { "OS1X3", 6, 2 },
+ { "OS1X2", 4, 2 },
+ { "OS1X1", 2, 2 },
+ { "OS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x370d8, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x370dc, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x370e0, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_5", 0x370ec, 0 },
+ { "ERRORP", 15, 1 },
+ { "ERRORN", 14, 1 },
+ { "TESTENA", 13, 1 },
+ { "TUNEBIT", 10, 3 },
+ { "DATAPOS", 8, 2 },
+ { "SEGSEL", 3, 5 },
+ { "TAPSEL", 1, 2 },
+ { "DATASIGN", 0, 1 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x370f0, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x370f4, 0 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x370f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x370fc, 0 },
+ { "SDOVRDEN", 15, 1 },
+ { "BSOUTN", 7, 1 },
+ { "BSOUTP", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x37100, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_RXLOOP", 5, 1 },
+ { "T5_TX_ENFFE4", 4, 1 },
+ { "T5_TX_BWSEL", 2, 2 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x37104, 0 },
+ { "SPSEL", 11, 3 },
+ { "FRCERR", 10, 1 },
+ { "ERROR", 9, 1 },
+ { "SYNC", 8, 1 },
+ { "P7CHK", 5, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x37108, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "SASMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3710c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37110, 0 },
+ { "T5DCCEN", 4, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37114, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37118, 0 },
+ { "CALSSTN", 8, 6 },
+ { "CALSSTP", 0, 6 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3711c, 0 },
+ { "DRTOL", 2, 3 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x37120, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x37124, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x37128, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_3_COEFFICIENT", 0x3712c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x37134, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37138, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "SASCMD", 10, 2 },
+ { "C0UPDT", 6, 2 },
+ { "C3UPDT", 4, 2 },
+ { "C2UPDT", 2, 2 },
+ { "C1UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3713c, 0 },
+ { "C0STAT", 6, 2 },
+ { "C3STAT", 4, 2 },
+ { "C2STAT", 2, 2 },
+ { "C1STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37140, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37144, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37148, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3714c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37150, 0 },
+ { "ATUNEN", 8, 8 },
+ { "ATUNEP", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37158, 0 },
+ { "DCCCOMPINV", 8, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_4X_SEGMENT_APPLIED", 0x37160, 0 },
+ { "AS4X7", 14, 2 },
+ { "AS4X6", 12, 2 },
+ { "AS4X5", 10, 2 },
+ { "AS4X4", 8, 2 },
+ { "AS4X3", 6, 2 },
+ { "AS4X2", 4, 2 },
+ { "AS4X1", 2, 2 },
+ { "AS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_2X_SEGMENT_APPLIED", 0x37164, 0 },
+ { "AS2X3", 6, 2 },
+ { "AS2X2", 4, 2 },
+ { "AS2X1", 2, 2 },
+ { "AS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_1X_SEGMENT_APPLIED", 0x37168, 0 },
+ { "AS1X7", 14, 2 },
+ { "AS1X6", 12, 2 },
+ { "AS1X5", 10, 2 },
+ { "AS1X4", 8, 2 },
+ { "AS1X3", 6, 2 },
+ { "AS1X2", 4, 2 },
+ { "AS1X1", 2, 2 },
+ { "AS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3716c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37170, 0 },
+ { "AT2X", 8, 4 },
+ { "AT4X", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37174, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37178, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3717c, 0 },
+ { "XADDR", 1, 5 },
+ { "XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37180, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37184, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37188, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3718c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3719c, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x371a0, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 13, 2 },
+ { "DCCLOCK", 11, 2 },
+ { "DCCOFFSET", 8, 3 },
+ { "DCCSTEP", 6, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x371a4, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x371a8, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x371ac, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SIGN_OVERRIDE", 0x371c0, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x371c8, 0 },
+ { "OS4X7", 14, 2 },
+ { "OS4X6", 12, 2 },
+ { "OS4X5", 10, 2 },
+ { "OS4X4", 8, 2 },
+ { "OS4X3", 6, 2 },
+ { "OS4X2", 4, 2 },
+ { "OS4X1", 2, 2 },
+ { "OS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x371cc, 0 },
+ { "OS2X3", 6, 2 },
+ { "OS2X2", 4, 2 },
+ { "OS2X1", 2, 2 },
+ { "OS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x371d0, 0 },
+ { "OS1X7", 14, 2 },
+ { "OS1X6", 12, 2 },
+ { "OS1X5", 10, 2 },
+ { "OS1X4", 8, 2 },
+ { "OS1X3", 6, 2 },
+ { "OS1X2", 4, 2 },
+ { "OS1X1", 2, 2 },
+ { "OS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x371d8, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x371dc, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x371e0, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_5", 0x371ec, 0 },
+ { "ERRORP", 15, 1 },
+ { "ERRORN", 14, 1 },
+ { "TESTENA", 13, 1 },
+ { "TUNEBIT", 10, 3 },
+ { "DATAPOS", 8, 2 },
+ { "SEGSEL", 3, 5 },
+ { "TAPSEL", 1, 2 },
+ { "DATASIGN", 0, 1 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x371f0, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x371f4, 0 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x371f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x371fc, 0 },
+ { "SDOVRDEN", 15, 1 },
+ { "BSOUTN", 7, 1 },
+ { "BSOUTP", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x37400, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_RXLOOP", 5, 1 },
+ { "T5_TX_ENFFE4", 4, 1 },
+ { "T5_TX_BWSEL", 2, 2 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x37404, 0 },
+ { "SPSEL", 11, 3 },
+ { "FRCERR", 10, 1 },
+ { "ERROR", 9, 1 },
+ { "SYNC", 8, 1 },
+ { "P7CHK", 5, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x37408, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "SASMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3740c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37410, 0 },
+ { "T5DCCEN", 4, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37414, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37418, 0 },
+ { "CALSSTN", 8, 6 },
+ { "CALSSTP", 0, 6 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3741c, 0 },
+ { "DRTOL", 2, 3 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x37420, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x37424, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x37428, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_3_COEFFICIENT", 0x3742c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x37434, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37438, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "SASCMD", 10, 2 },
+ { "C0UPDT", 6, 2 },
+ { "C3UPDT", 4, 2 },
+ { "C2UPDT", 2, 2 },
+ { "C1UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3743c, 0 },
+ { "C0STAT", 6, 2 },
+ { "C3STAT", 4, 2 },
+ { "C2STAT", 2, 2 },
+ { "C1STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37440, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37444, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37448, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3744c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37450, 0 },
+ { "ATUNEN", 8, 8 },
+ { "ATUNEP", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37458, 0 },
+ { "DCCCOMPINV", 8, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_4X_SEGMENT_APPLIED", 0x37460, 0 },
+ { "AS4X7", 14, 2 },
+ { "AS4X6", 12, 2 },
+ { "AS4X5", 10, 2 },
+ { "AS4X4", 8, 2 },
+ { "AS4X3", 6, 2 },
+ { "AS4X2", 4, 2 },
+ { "AS4X1", 2, 2 },
+ { "AS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_2X_SEGMENT_APPLIED", 0x37464, 0 },
+ { "AS2X3", 6, 2 },
+ { "AS2X2", 4, 2 },
+ { "AS2X1", 2, 2 },
+ { "AS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_1X_SEGMENT_APPLIED", 0x37468, 0 },
+ { "AS1X7", 14, 2 },
+ { "AS1X6", 12, 2 },
+ { "AS1X5", 10, 2 },
+ { "AS1X4", 8, 2 },
+ { "AS1X3", 6, 2 },
+ { "AS1X2", 4, 2 },
+ { "AS1X1", 2, 2 },
+ { "AS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3746c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37470, 0 },
+ { "AT2X", 8, 4 },
+ { "AT4X", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37474, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37478, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3747c, 0 },
+ { "XADDR", 1, 5 },
+ { "XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37480, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37484, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37488, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3748c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3749c, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x374a0, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 13, 2 },
+ { "DCCLOCK", 11, 2 },
+ { "DCCOFFSET", 8, 3 },
+ { "DCCSTEP", 6, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x374a4, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x374a8, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x374ac, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SIGN_OVERRIDE", 0x374c0, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x374c8, 0 },
+ { "OS4X7", 14, 2 },
+ { "OS4X6", 12, 2 },
+ { "OS4X5", 10, 2 },
+ { "OS4X4", 8, 2 },
+ { "OS4X3", 6, 2 },
+ { "OS4X2", 4, 2 },
+ { "OS4X1", 2, 2 },
+ { "OS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x374cc, 0 },
+ { "OS2X3", 6, 2 },
+ { "OS2X2", 4, 2 },
+ { "OS2X1", 2, 2 },
+ { "OS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x374d0, 0 },
+ { "OS1X7", 14, 2 },
+ { "OS1X6", 12, 2 },
+ { "OS1X5", 10, 2 },
+ { "OS1X4", 8, 2 },
+ { "OS1X3", 6, 2 },
+ { "OS1X2", 4, 2 },
+ { "OS1X1", 2, 2 },
+ { "OS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x374d8, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x374dc, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x374e0, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_5", 0x374ec, 0 },
+ { "ERRORP", 15, 1 },
+ { "ERRORN", 14, 1 },
+ { "TESTENA", 13, 1 },
+ { "TUNEBIT", 10, 3 },
+ { "DATAPOS", 8, 2 },
+ { "SEGSEL", 3, 5 },
+ { "TAPSEL", 1, 2 },
+ { "DATASIGN", 0, 1 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x374f0, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x374f4, 0 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x374f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x374fc, 0 },
+ { "SDOVRDEN", 15, 1 },
+ { "BSOUTN", 7, 1 },
+ { "BSOUTP", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x37500, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_RXLOOP", 5, 1 },
+ { "T5_TX_ENFFE4", 4, 1 },
+ { "T5_TX_BWSEL", 2, 2 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x37504, 0 },
+ { "SPSEL", 11, 3 },
+ { "FRCERR", 10, 1 },
+ { "ERROR", 9, 1 },
+ { "SYNC", 8, 1 },
+ { "P7CHK", 5, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x37508, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "SASMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3750c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37510, 0 },
+ { "T5DCCEN", 4, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37514, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37518, 0 },
+ { "CALSSTN", 8, 6 },
+ { "CALSSTP", 0, 6 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3751c, 0 },
+ { "DRTOL", 2, 3 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x37520, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x37524, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x37528, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_3_COEFFICIENT", 0x3752c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x37534, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37538, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "SASCMD", 10, 2 },
+ { "C0UPDT", 6, 2 },
+ { "C3UPDT", 4, 2 },
+ { "C2UPDT", 2, 2 },
+ { "C1UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3753c, 0 },
+ { "C0STAT", 6, 2 },
+ { "C3STAT", 4, 2 },
+ { "C2STAT", 2, 2 },
+ { "C1STAT", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37540, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37544, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37548, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3754c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37550, 0 },
+ { "ATUNEN", 8, 8 },
+ { "ATUNEP", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37558, 0 },
+ { "DCCCOMPINV", 8, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_4X_SEGMENT_APPLIED", 0x37560, 0 },
+ { "AS4X7", 14, 2 },
+ { "AS4X6", 12, 2 },
+ { "AS4X5", 10, 2 },
+ { "AS4X4", 8, 2 },
+ { "AS4X3", 6, 2 },
+ { "AS4X2", 4, 2 },
+ { "AS4X1", 2, 2 },
+ { "AS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_2X_SEGMENT_APPLIED", 0x37564, 0 },
+ { "AS2X3", 6, 2 },
+ { "AS2X2", 4, 2 },
+ { "AS2X1", 2, 2 },
+ { "AS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_1X_SEGMENT_APPLIED", 0x37568, 0 },
+ { "AS1X7", 14, 2 },
+ { "AS1X6", 12, 2 },
+ { "AS1X5", 10, 2 },
+ { "AS1X4", 8, 2 },
+ { "AS1X3", 6, 2 },
+ { "AS1X2", 4, 2 },
+ { "AS1X1", 2, 2 },
+ { "AS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3756c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37570, 0 },
+ { "AT2X", 8, 4 },
+ { "AT4X", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37574, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37578, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3757c, 0 },
+ { "XADDR", 1, 5 },
+ { "XWR", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37580, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37584, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37588, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3758c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3759c, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x375a0, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 13, 2 },
+ { "DCCLOCK", 11, 2 },
+ { "DCCOFFSET", 8, 3 },
+ { "DCCSTEP", 6, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x375a4, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x375a8, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x375ac, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SIGN_OVERRIDE", 0x375c0, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x375c8, 0 },
+ { "OS4X7", 14, 2 },
+ { "OS4X6", 12, 2 },
+ { "OS4X5", 10, 2 },
+ { "OS4X4", 8, 2 },
+ { "OS4X3", 6, 2 },
+ { "OS4X2", 4, 2 },
+ { "OS4X1", 2, 2 },
+ { "OS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x375cc, 0 },
+ { "OS2X3", 6, 2 },
+ { "OS2X2", 4, 2 },
+ { "OS2X1", 2, 2 },
+ { "OS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x375d0, 0 },
+ { "OS1X7", 14, 2 },
+ { "OS1X6", 12, 2 },
+ { "OS1X5", 10, 2 },
+ { "OS1X4", 8, 2 },
+ { "OS1X3", 6, 2 },
+ { "OS1X2", 4, 2 },
+ { "OS1X1", 2, 2 },
+ { "OS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x375d8, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x375dc, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x375e0, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_5", 0x375ec, 0 },
+ { "ERRORP", 15, 1 },
+ { "ERRORN", 14, 1 },
+ { "TESTENA", 13, 1 },
+ { "TUNEBIT", 10, 3 },
+ { "DATAPOS", 8, 2 },
+ { "SEGSEL", 3, 5 },
+ { "TAPSEL", 1, 2 },
+ { "DATASIGN", 0, 1 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x375f0, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x375f4, 0 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x375f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x375fc, 0 },
+ { "SDOVRDEN", 15, 1 },
+ { "BSOUTN", 7, 1 },
+ { "BSOUTP", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x37900, 0 },
+ { "T5_TX_LINKEN", 15, 1 },
+ { "T5_TX_LINKRST", 14, 1 },
+ { "T5_TX_CFGWRT", 13, 1 },
+ { "T5_TX_CFGPTR", 11, 2 },
+ { "T5_TX_CFGEXT", 10, 1 },
+ { "T5_TX_CFGACT", 9, 1 },
+ { "T5_TX_RSYNCC", 8, 1 },
+ { "T5_TX_PLLSEL", 6, 2 },
+ { "T5_TX_RXLOOP", 5, 1 },
+ { "T5_TX_ENFFE4", 4, 1 },
+ { "T5_TX_BWSEL", 2, 2 },
+ { "T5_TX_RTSEL", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x37904, 0 },
+ { "SPSEL", 11, 3 },
+ { "FRCERR", 10, 1 },
+ { "ERROR", 9, 1 },
+ { "SYNC", 8, 1 },
+ { "P7CHK", 5, 1 },
+ { "PRST", 4, 1 },
+ { "TPGMD", 3, 1 },
+ { "TPSEL", 0, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x37908, 0 },
+ { "ZCALOVRD", 8, 1 },
+ { "SASMODE", 7, 1 },
+ { "AEPOL", 6, 1 },
+ { "AESRC", 5, 1 },
+ { "EQMODE", 4, 1 },
+ { "OCOEF", 3, 1 },
+ { "COEFRST", 2, 1 },
+ { "ALOAD", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3790c, 0 },
+ { "T5DRVHIZ", 5, 1 },
+ { "T5SLEW", 2, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37910, 0 },
+ { "T5DCCEN", 4, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37914, 0 },
+ { "RSTEP", 15, 1 },
+ { "RLOCK", 14, 1 },
+ { "RPOS", 8, 6 },
+ { "DCLKSAM", 7, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37918, 0 },
+ { "CALSSTN", 8, 6 },
+ { "CALSSTP", 0, 6 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3791c, 0 },
+ { "DRTOL", 2, 3 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x37920, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x37924, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x37928, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_3_COEFFICIENT", 0x3792c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x37934, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37938, 0 },
+ { "CPREST", 13, 1 },
+ { "CINIT", 12, 1 },
+ { "SASCMD", 10, 2 },
+ { "C0UPDT", 6, 2 },
+ { "C3UPDT", 4, 2 },
+ { "C2UPDT", 2, 2 },
+ { "C1UPDT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3793c, 0 },
+ { "C0STAT", 6, 2 },
+ { "C3STAT", 4, 2 },
+ { "C2STAT", 2, 2 },
+ { "C1STAT", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_0_COEFFICIENT_OVERRIDE", 0x37940, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_1_COEFFICIENT_OVERRIDE", 0x37944, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_2_COEFFICIENT_OVERRIDE", 0x37948, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_AE_TAP_3_COEFFICIENT_OVERRIDE", 0x3794c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_APPLIED_TUNE_REGISTER", 0x37950, 0 },
+ { "ATUNEN", 8, 8 },
+ { "ATUNEP", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_ANALOG_DIAGNOSTICS_REGISTER", 0x37958, 0 },
+ { "DCCCOMPINV", 8, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_4X_SEGMENT_APPLIED", 0x37960, 0 },
+ { "AS4X7", 14, 2 },
+ { "AS4X6", 12, 2 },
+ { "AS4X5", 10, 2 },
+ { "AS4X4", 8, 2 },
+ { "AS4X3", 6, 2 },
+ { "AS4X2", 4, 2 },
+ { "AS4X1", 2, 2 },
+ { "AS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_2X_SEGMENT_APPLIED", 0x37964, 0 },
+ { "AS2X3", 6, 2 },
+ { "AS2X2", 4, 2 },
+ { "AS2X1", 2, 2 },
+ { "AS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_1X_SEGMENT_APPLIED", 0x37968, 0 },
+ { "AS1X7", 14, 2 },
+ { "AS1X6", 12, 2 },
+ { "AS1X5", 10, 2 },
+ { "AS1X4", 8, 2 },
+ { "AS1X3", 6, 2 },
+ { "AS1X2", 4, 2 },
+ { "AS1X1", 2, 2 },
+ { "AS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_TERMINATION_APPLIED", 0x3796c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X1X_TERMINATION_APPLIED", 0x37970, 0 },
+ { "AT2X", 8, 4 },
+ { "AT4X", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_APPLIED_REGISTER", 0x37974, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37978, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3797c, 0 },
+ { "XADDR", 1, 5 },
+ { "XWR", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37980, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37984, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_5_4", 0x37988, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_7_6", 0x3798c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3799c, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x379a0, 0 },
+ { "DCCTIMEDOUT", 15, 1 },
+ { "DCCTIMEEN", 13, 2 },
+ { "DCCLOCK", 11, 2 },
+ { "DCCOFFSET", 8, 3 },
+ { "DCCSTEP", 6, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x379a4, 0 },
+ { "DCCOUT", 12, 1 },
+ { "DCCCLK", 11, 1 },
+ { "DCCHOLD", 10, 1 },
+ { "DCCSIGN", 8, 2 },
+ { "DCCAMP", 1, 7 },
+ { "DCCOEN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x379a8, 0 },
+ { "DCCASIGN", 7, 2 },
+ { "DCCAAMP", 0, 7 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x379ac, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SIGN_OVERRIDE", 0x379c0, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_4X_OVERRIDE", 0x379c8, 0 },
+ { "OS4X7", 14, 2 },
+ { "OS4X6", 12, 2 },
+ { "OS4X5", 10, 2 },
+ { "OS4X4", 8, 2 },
+ { "OS4X3", 6, 2 },
+ { "OS4X2", 4, 2 },
+ { "OS4X1", 2, 2 },
+ { "OS4X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_2X_OVERRIDE", 0x379cc, 0 },
+ { "OS2X3", 6, 2 },
+ { "OS2X2", 4, 2 },
+ { "OS2X1", 2, 2 },
+ { "OS2X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_1X_OVERRIDE", 0x379d0, 0 },
+ { "OS1X7", 14, 2 },
+ { "OS1X6", 12, 2 },
+ { "OS1X5", 10, 2 },
+ { "OS1X4", 8, 2 },
+ { "OS1X3", 6, 2 },
+ { "OS1X2", 4, 2 },
+ { "OS1X1", 2, 2 },
+ { "OS1X0", 0, 2 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_4X_TERMINATION_OVERRIDE", 0x379d8, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_2X_TERMINATION_OVERRIDE", 0x379dc, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_SEGMENT_1X_TERMINATION_OVERRIDE", 0x379e0, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_5", 0x379ec, 0 },
+ { "ERRORP", 15, 1 },
+ { "ERRORN", 14, 1 },
+ { "TESTENA", 13, 1 },
+ { "TUNEBIT", 10, 3 },
+ { "DATAPOS", 8, 2 },
+ { "SEGSEL", 3, 5 },
+ { "TAPSEL", 1, 2 },
+ { "DATASIGN", 0, 1 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x379f0, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x379f4, 0 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x379f8, 0 },
+ { "AECMDVAL", 14, 1 },
+ { "AECMD1312", 12, 2 },
+ { "AECMD70", 0, 8 },
+ { "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x379fc, 0 },
+ { "SDOVRDEN", 15, 1 },
+ { "BSOUTN", 7, 1 },
+ { "BSOUTP", 6, 1 },
+ { "BSIN", 5, 1 },
+ { "JTAGAMPL", 3, 2 },
+ { "JTAGTS", 2, 1 },
+ { "TS", 1, 1 },
+ { "OBS", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x37200, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_MODE8023AZ", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x37204, 0 },
+ { "APLYDCD", 15, 1 },
+ { "PPOL", 13, 2 },
+ { "PCLKSEL", 11, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x37208, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3720c, 0 },
+ { "H1ANOFST", 12, 4 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "TMSCAL", 8, 2 },
+ { "APADJ", 7, 1 },
+ { "RSEL", 6, 1 },
+ { "PHOFFS", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x37210, 0 },
+ { "ROTA", 8, 6 },
+ { "ROTD", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x37214, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROTE", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37218, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOFFF", 8, 4 },
+ { "RAOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3721c, 0 },
+ { "RCALER", 15, 1 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x37220, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 8, 4 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x37224, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x37228, 0 },
+ { "REQWOV", 15, 1 },
+ { "RASEL", 11, 3 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3722c, 0 },
+ { "WRAPSEL", 15, 1 },
+ { "ACTL", 14, 1 },
+ { "PEAK", 9, 5 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x37230, 0 },
+ { "FVOFFSKP", 15, 1 },
+ { "FGAINCHK", 14, 1 },
+ { "FH1ACAL", 13, 1 },
+ { "FH1AFLTR", 11, 2 },
+ { "T5SHORTV", 10, 1 },
+ { "WGAIN", 8, 2 },
+ { "GAIN_STAT", 7, 1 },
+ { "T5VGAIN", 0, 7 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x37234, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37238, 0 },
+ { "PMCFG", 6, 2 },
+ { "PMOFFTIME", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_1", 0x3723c, 0 },
+ { "SELI", 9, 1 },
+ { "SERVREF", 5, 3 },
+ { "IQAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_IQAMP_CONTROL_2", 0x37240, 0 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37244, 0 },
+ { "SAVEADAC", 8, 1 },
+ { "LOAD2", 7, 1 },
+ { "LOAD1", 6, 1 },
+ { "WRTACC2", 5, 1 },
+ { "WRTACC1", 4, 1 },
+ { "SELAPAN", 3, 1 },
+ { "DASEL", 0, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x37248, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN", 0x3724c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x37250, 0 },
+ { "ADAC2", 8, 8 },
+ { "ADAC1", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_CONTROL", 0x37254, 0 },
+ { "FACCPLDYN", 13, 1 },
+ { "ACCPLGAIN", 10, 3 },
+ { "ACCPLREF", 8, 2 },
+ { "ACCPLSTEP", 6, 2 },
+ { "ACCPLASTEP", 1, 5 },
+ { "FACCPL", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_AC_COUPLING_VALUE", 0x37258, 0 },
+ { "ACCPLMEANS", 15, 1 },
+ { "CDROVREN", 8, 1 },
+ { "ACCPLBIAS", 0, 8 },
+ { "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET", 0x3725c, 0 },
+ { "MAC_PORT_RX_LINKA_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37260, 0 },
+ { "H1OX", 8, 6 },
+ { "H1EX", 0, 6 },
+ { "MAC_PORT_RX_LINKA_PEAKED_INTEGRATOR", 0x37264, 0 },
+ { "PILOCK", 10, 1 },
+ { "UNPKPKA", 2, 6 },
+ { "UNPKVGA", 0, 2 },
+ { "MAC_PORT_RX_LINKA_CDR_ANALOG_SWITCH", 0x37268, 0 },
+ { "OVRAC", 15, 1 },
+ { "OVRPK", 14, 1 },
+ { "OVRTAILS", 12, 2 },
+ { "OVRTAILV", 9, 3 },
+ { "OVRCAP", 8, 1 },
+ { "OVRDCDPRE", 7, 1 },
+ { "OVRDCDPST", 6, 1 },
+ { "DCVSCTMODE", 2, 1 },
+ { "CDRANLGSW", 0, 2 },
+ { "MAC_PORT_RX_LINKA_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3726c, 0 },
+ { "PFLAG", 5, 2 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37270, 0 },
+ { "DACCLIP", 15, 1 },
+ { "DPCFRZ", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCLKNQ", 11, 1 },
+ { "DPCWDFE", 10, 1 },
+ { "DPCWPK", 9, 1 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x37274, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "VIEWSCAN", 4, 1 },
+ { "ODEC", 0, 4 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x37278, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "ACCCMP", 11, 1 },
+ { "DCCCMP", 10, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5IQCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3727c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x37280, 0 },
+ { "H25SPC", 15, 1 },
+ { "FDCCAL", 14, 1 },
+ { "FROTCAL", 13, 1 },
+ { "FIQAMP", 12, 1 },
+ { "FRPTCALF", 11, 1 },
+ { "FINTCALGS", 10, 1 },
+ { "FDCC", 9, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FDCD", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FINTRCALDYN", 1, 1 },
+ { "FQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_CHANNEL", 0x37284, 0 },
+ { "QCCIND", 13, 1 },
+ { "DCDIND", 10, 3 },
+ { "DCCIND", 8, 2 },
+ { "CFSEL", 5, 1 },
+ { "LOFCH", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DFE_OFFSET_VALUE", 0x37288, 0 },
+ { "LOFU", 8, 7 },
+ { "LOFL", 0, 7 },
+ { "MAC_PORT_RX_LINKA_H_COEFFICIENBT_BIST", 0x3728c, 0 },
+ { "HBISTMAN", 12, 1 },
+ { "HBISTRES", 11, 1 },
+ { "HBISTSP", 8, 3 },
+ { "HBISTEN", 7, 1 },
+ { "HBISTRST", 6, 1 },
+ { "HCOMP", 5, 1 },
+ { "HPASS", 4, 1 },
+ { "HSEL", 0, 4 },
+ { "MAC_PORT_RX_LINKA_AC_CAPACITOR_BIST", 0x37290, 0 },
+ { "ACCCMP", 13, 1 },
+ { "ACCEN", 12, 1 },
+ { "ACCRST", 11, 1 },
+ { "ACCIND", 8, 3 },
+ { "ACCRD", 0, 8 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL_REGISTER", 0x37298, 0 },
+ { "LFREG", 15, 1 },
+ { "LFRC", 14, 1 },
+ { "LGIDLE", 13, 1 },
+ { "LFTGT", 8, 5 },
+ { "LGTGT", 7, 1 },
+ { "LRDY", 6, 1 },
+ { "LIDLE", 5, 1 },
+ { "LCURR", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3729c, 0 },
+ { "OFFSN", 13, 2 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x372a0, 0 },
+ { "RX_OVRSUMPD", 15, 1 },
+ { "RX_OVRKBPD", 14, 1 },
+ { "RX_OVRDIVPD", 13, 1 },
+ { "RX_OFFVGADIS", 12, 1 },
+ { "RX_OFFACDIS", 11, 1 },
+ { "RX_VTERM", 10, 1 },
+ { "RX_DISSPY2D", 8, 1 },
+ { "RX_OBSOVEN", 7, 1 },
+ { "RX_LINKANLGSW", 0, 7 },
+ { "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x372a4, 0 },
+ { "INTDACEGS", 13, 3 },
+ { "INTDACE", 8, 5 },
+ { "INTDACGS", 6, 2 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x372a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x372ac, 0 },
+ { "SMQM", 13, 3 },
+ { "SMQ", 5, 8 },
+ { "EMMD", 3, 2 },
+ { "EMBRDY", 2, 1 },
+ { "EMBUMP", 1, 1 },
+ { "EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x372b0, 0 },
+ { "EMSF", 13, 1 },
+ { "EMDATA59", 12, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x372b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x372b8, 0 },
+ { "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_3", 0x372bc, 0 },
+ { "FTIMEOUT", 15, 1 },
+ { "FROTCAL4", 14, 1 },
+ { "FDCD2", 13, 1 },
+ { "FPRBSPOLTOG", 12, 1 },
+ { "FPRBSOFF2", 11, 1 },
+ { "FDDCAL2", 10, 1 },
+ { "FDDCFLTR", 9, 1 },
+ { "FDAC6", 8, 1 },
+ { "FDDC5", 7, 1 },
+ { "FDDC3456", 6, 1 },
+ { "FSPY2DATA", 5, 1 },
+ { "FPHSLOCK", 4, 1 },
+ { "FCLKALGN", 3, 1 },
+ { "FCLKALDYN", 2, 1 },
+ { "FDFE", 1, 1 },
+ { "FPRBSOFF", 0, 1 },
+ { "MAC_PORT_RX_LINKA_DFE_TAP_CONTROL", 0x372c0, 0 },
+ { "MAC_PORT_RX_LINKA_DFE_TAP", 0x372c4, 0 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS_2", 0x372e4, 0 },
+ { "STNDBYSTAT", 15, 1 },
+ { "CALSDONE", 14, 1 },
+ { "ACISRCCMP", 5, 1 },
+ { "PRBSOFFCMP", 4, 1 },
+ { "CLKALGNCMP", 3, 1 },
+ { "ROTFCMP", 2, 1 },
+ { "DCDCMP", 1, 1 },
+ { "QCCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKA_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x372e8, 0 },
+ { "FCSADJ", 6, 1 },
+ { "CSIND", 3, 2 },
+ { "CSVAL", 0, 3 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DCD_CONTROL", 0x372ec, 0 },
+ { "DCDTMDOUT", 15, 1 },
+ { "DCDTOEN", 14, 1 },
+ { "DCDLOCK", 13, 1 },
+ { "DCDSTEP", 11, 2 },
+ { "DCDALTWPDIS", 10, 1 },
+ { "DCDOVRDEN", 9, 1 },
+ { "DCCAOVRDEN", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_DCC_CONTROL", 0x372f0, 0 },
+ { "PRBSMODE", 14, 2 },
+ { "DCCSTEP", 10, 2 },
+ { "DCCOVRDEN", 9, 1 },
+ { "DCCLOCK", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_QCC_CONTROL", 0x372f4, 0 },
+ { "DCCQCCMODE", 15, 1 },
+ { "DCCQCCDYN", 14, 1 },
+ { "DCCQCCHOLD", 13, 1 },
+ { "QCCSTEP", 10, 2 },
+ { "QCCOVRDEN", 9, 1 },
+ { "QCCLOCK", 8, 1 },
+ { "QCCSIGN", 6, 2 },
+ { "QCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x372f8, 0 },
+ { "TSTCMP", 15, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x372fc, 0 },
+ { "CALMODEEDGE", 14, 1 },
+ { "TESTCAP", 13, 1 },
+ { "SNAPEN", 12, 1 },
+ { "ASYNCDIR", 11, 1 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x37300, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_MODE8023AZ", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x37304, 0 },
+ { "APLYDCD", 15, 1 },
+ { "PPOL", 13, 2 },
+ { "PCLKSEL", 11, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x37308, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3730c, 0 },
+ { "H1ANOFST", 12, 4 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "TMSCAL", 8, 2 },
+ { "APADJ", 7, 1 },
+ { "RSEL", 6, 1 },
+ { "PHOFFS", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x37310, 0 },
+ { "ROTA", 8, 6 },
+ { "ROTD", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x37314, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROTE", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37318, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOFFF", 8, 4 },
+ { "RAOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3731c, 0 },
+ { "RCALER", 15, 1 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x37320, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 8, 4 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x37324, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x37328, 0 },
+ { "REQWOV", 15, 1 },
+ { "RASEL", 11, 3 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3732c, 0 },
+ { "WRAPSEL", 15, 1 },
+ { "ACTL", 14, 1 },
+ { "PEAK", 9, 5 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x37330, 0 },
+ { "FVOFFSKP", 15, 1 },
+ { "FGAINCHK", 14, 1 },
+ { "FH1ACAL", 13, 1 },
+ { "FH1AFLTR", 11, 2 },
+ { "T5SHORTV", 10, 1 },
+ { "WGAIN", 8, 2 },
+ { "GAIN_STAT", 7, 1 },
+ { "T5VGAIN", 0, 7 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x37334, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37338, 0 },
+ { "PMCFG", 6, 2 },
+ { "PMOFFTIME", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_1", 0x3733c, 0 },
+ { "SELI", 9, 1 },
+ { "SERVREF", 5, 3 },
+ { "IQAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_IQAMP_CONTROL_2", 0x37340, 0 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37344, 0 },
+ { "SAVEADAC", 8, 1 },
+ { "LOAD2", 7, 1 },
+ { "LOAD1", 6, 1 },
+ { "WRTACC2", 5, 1 },
+ { "WRTACC1", 4, 1 },
+ { "SELAPAN", 3, 1 },
+ { "DASEL", 0, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x37348, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN", 0x3734c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x37350, 0 },
+ { "ADAC2", 8, 8 },
+ { "ADAC1", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_CONTROL", 0x37354, 0 },
+ { "FACCPLDYN", 13, 1 },
+ { "ACCPLGAIN", 10, 3 },
+ { "ACCPLREF", 8, 2 },
+ { "ACCPLSTEP", 6, 2 },
+ { "ACCPLASTEP", 1, 5 },
+ { "FACCPL", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_AC_COUPLING_VALUE", 0x37358, 0 },
+ { "ACCPLMEANS", 15, 1 },
+ { "CDROVREN", 8, 1 },
+ { "ACCPLBIAS", 0, 8 },
+ { "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET", 0x3735c, 0 },
+ { "MAC_PORT_RX_LINKB_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37360, 0 },
+ { "H1OX", 8, 6 },
+ { "H1EX", 0, 6 },
+ { "MAC_PORT_RX_LINKB_PEAKED_INTEGRATOR", 0x37364, 0 },
+ { "PILOCK", 10, 1 },
+ { "UNPKPKA", 2, 6 },
+ { "UNPKVGA", 0, 2 },
+ { "MAC_PORT_RX_LINKB_CDR_ANALOG_SWITCH", 0x37368, 0 },
+ { "OVRAC", 15, 1 },
+ { "OVRPK", 14, 1 },
+ { "OVRTAILS", 12, 2 },
+ { "OVRTAILV", 9, 3 },
+ { "OVRCAP", 8, 1 },
+ { "OVRDCDPRE", 7, 1 },
+ { "OVRDCDPST", 6, 1 },
+ { "DCVSCTMODE", 2, 1 },
+ { "CDRANLGSW", 0, 2 },
+ { "MAC_PORT_RX_LINKB_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3736c, 0 },
+ { "PFLAG", 5, 2 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37370, 0 },
+ { "DACCLIP", 15, 1 },
+ { "DPCFRZ", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCLKNQ", 11, 1 },
+ { "DPCWDFE", 10, 1 },
+ { "DPCWPK", 9, 1 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x37374, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "VIEWSCAN", 4, 1 },
+ { "ODEC", 0, 4 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x37378, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "ACCCMP", 11, 1 },
+ { "DCCCMP", 10, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5IQCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3737c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x37380, 0 },
+ { "H25SPC", 15, 1 },
+ { "FDCCAL", 14, 1 },
+ { "FROTCAL", 13, 1 },
+ { "FIQAMP", 12, 1 },
+ { "FRPTCALF", 11, 1 },
+ { "FINTCALGS", 10, 1 },
+ { "FDCC", 9, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FDCD", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FINTRCALDYN", 1, 1 },
+ { "FQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_CHANNEL", 0x37384, 0 },
+ { "QCCIND", 13, 1 },
+ { "DCDIND", 10, 3 },
+ { "DCCIND", 8, 2 },
+ { "CFSEL", 5, 1 },
+ { "LOFCH", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DFE_OFFSET_VALUE", 0x37388, 0 },
+ { "LOFU", 8, 7 },
+ { "LOFL", 0, 7 },
+ { "MAC_PORT_RX_LINKB_H_COEFFICIENBT_BIST", 0x3738c, 0 },
+ { "HBISTMAN", 12, 1 },
+ { "HBISTRES", 11, 1 },
+ { "HBISTSP", 8, 3 },
+ { "HBISTEN", 7, 1 },
+ { "HBISTRST", 6, 1 },
+ { "HCOMP", 5, 1 },
+ { "HPASS", 4, 1 },
+ { "HSEL", 0, 4 },
+ { "MAC_PORT_RX_LINKB_AC_CAPACITOR_BIST", 0x37390, 0 },
+ { "ACCCMP", 13, 1 },
+ { "ACCEN", 12, 1 },
+ { "ACCRST", 11, 1 },
+ { "ACCIND", 8, 3 },
+ { "ACCRD", 0, 8 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL_REGISTER", 0x37398, 0 },
+ { "LFREG", 15, 1 },
+ { "LFRC", 14, 1 },
+ { "LGIDLE", 13, 1 },
+ { "LFTGT", 8, 5 },
+ { "LGTGT", 7, 1 },
+ { "LRDY", 6, 1 },
+ { "LIDLE", 5, 1 },
+ { "LCURR", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3739c, 0 },
+ { "OFFSN", 13, 2 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x373a0, 0 },
+ { "RX_OVRSUMPD", 15, 1 },
+ { "RX_OVRKBPD", 14, 1 },
+ { "RX_OVRDIVPD", 13, 1 },
+ { "RX_OFFVGADIS", 12, 1 },
+ { "RX_OFFACDIS", 11, 1 },
+ { "RX_VTERM", 10, 1 },
+ { "RX_DISSPY2D", 8, 1 },
+ { "RX_OBSOVEN", 7, 1 },
+ { "RX_LINKANLGSW", 0, 7 },
+ { "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x373a4, 0 },
+ { "INTDACEGS", 13, 3 },
+ { "INTDACE", 8, 5 },
+ { "INTDACGS", 6, 2 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x373a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x373ac, 0 },
+ { "SMQM", 13, 3 },
+ { "SMQ", 5, 8 },
+ { "EMMD", 3, 2 },
+ { "EMBRDY", 2, 1 },
+ { "EMBUMP", 1, 1 },
+ { "EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x373b0, 0 },
+ { "EMSF", 13, 1 },
+ { "EMDATA59", 12, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x373b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x373b8, 0 },
+ { "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_3", 0x373bc, 0 },
+ { "FTIMEOUT", 15, 1 },
+ { "FROTCAL4", 14, 1 },
+ { "FDCD2", 13, 1 },
+ { "FPRBSPOLTOG", 12, 1 },
+ { "FPRBSOFF2", 11, 1 },
+ { "FDDCAL2", 10, 1 },
+ { "FDDCFLTR", 9, 1 },
+ { "FDAC6", 8, 1 },
+ { "FDDC5", 7, 1 },
+ { "FDDC3456", 6, 1 },
+ { "FSPY2DATA", 5, 1 },
+ { "FPHSLOCK", 4, 1 },
+ { "FCLKALGN", 3, 1 },
+ { "FCLKALDYN", 2, 1 },
+ { "FDFE", 1, 1 },
+ { "FPRBSOFF", 0, 1 },
+ { "MAC_PORT_RX_LINKB_DFE_TAP_CONTROL", 0x373c0, 0 },
+ { "MAC_PORT_RX_LINKB_DFE_TAP", 0x373c4, 0 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS_2", 0x373e4, 0 },
+ { "STNDBYSTAT", 15, 1 },
+ { "CALSDONE", 14, 1 },
+ { "ACISRCCMP", 5, 1 },
+ { "PRBSOFFCMP", 4, 1 },
+ { "CLKALGNCMP", 3, 1 },
+ { "ROTFCMP", 2, 1 },
+ { "DCDCMP", 1, 1 },
+ { "QCCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKB_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x373e8, 0 },
+ { "FCSADJ", 6, 1 },
+ { "CSIND", 3, 2 },
+ { "CSVAL", 0, 3 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DCD_CONTROL", 0x373ec, 0 },
+ { "DCDTMDOUT", 15, 1 },
+ { "DCDTOEN", 14, 1 },
+ { "DCDLOCK", 13, 1 },
+ { "DCDSTEP", 11, 2 },
+ { "DCDALTWPDIS", 10, 1 },
+ { "DCDOVRDEN", 9, 1 },
+ { "DCCAOVRDEN", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_DCC_CONTROL", 0x373f0, 0 },
+ { "PRBSMODE", 14, 2 },
+ { "DCCSTEP", 10, 2 },
+ { "DCCOVRDEN", 9, 1 },
+ { "DCCLOCK", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_QCC_CONTROL", 0x373f4, 0 },
+ { "DCCQCCMODE", 15, 1 },
+ { "DCCQCCDYN", 14, 1 },
+ { "DCCQCCHOLD", 13, 1 },
+ { "QCCSTEP", 10, 2 },
+ { "QCCOVRDEN", 9, 1 },
+ { "QCCLOCK", 8, 1 },
+ { "QCCSIGN", 6, 2 },
+ { "QCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x373f8, 0 },
+ { "TSTCMP", 15, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x373fc, 0 },
+ { "CALMODEEDGE", 14, 1 },
+ { "TESTCAP", 13, 1 },
+ { "SNAPEN", 12, 1 },
+ { "ASYNCDIR", 11, 1 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x37600, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_MODE8023AZ", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x37604, 0 },
+ { "APLYDCD", 15, 1 },
+ { "PPOL", 13, 2 },
+ { "PCLKSEL", 11, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x37608, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3760c, 0 },
+ { "H1ANOFST", 12, 4 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "TMSCAL", 8, 2 },
+ { "APADJ", 7, 1 },
+ { "RSEL", 6, 1 },
+ { "PHOFFS", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x37610, 0 },
+ { "ROTA", 8, 6 },
+ { "ROTD", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x37614, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROTE", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37618, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOFFF", 8, 4 },
+ { "RAOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3761c, 0 },
+ { "RCALER", 15, 1 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x37620, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 8, 4 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x37624, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x37628, 0 },
+ { "REQWOV", 15, 1 },
+ { "RASEL", 11, 3 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3762c, 0 },
+ { "WRAPSEL", 15, 1 },
+ { "ACTL", 14, 1 },
+ { "PEAK", 9, 5 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x37630, 0 },
+ { "FVOFFSKP", 15, 1 },
+ { "FGAINCHK", 14, 1 },
+ { "FH1ACAL", 13, 1 },
+ { "FH1AFLTR", 11, 2 },
+ { "T5SHORTV", 10, 1 },
+ { "WGAIN", 8, 2 },
+ { "GAIN_STAT", 7, 1 },
+ { "T5VGAIN", 0, 7 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x37634, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37638, 0 },
+ { "PMCFG", 6, 2 },
+ { "PMOFFTIME", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_1", 0x3763c, 0 },
+ { "SELI", 9, 1 },
+ { "SERVREF", 5, 3 },
+ { "IQAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_IQAMP_CONTROL_2", 0x37640, 0 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37644, 0 },
+ { "SAVEADAC", 8, 1 },
+ { "LOAD2", 7, 1 },
+ { "LOAD1", 6, 1 },
+ { "WRTACC2", 5, 1 },
+ { "WRTACC1", 4, 1 },
+ { "SELAPAN", 3, 1 },
+ { "DASEL", 0, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x37648, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN", 0x3764c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x37650, 0 },
+ { "ADAC2", 8, 8 },
+ { "ADAC1", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_CONTROL", 0x37654, 0 },
+ { "FACCPLDYN", 13, 1 },
+ { "ACCPLGAIN", 10, 3 },
+ { "ACCPLREF", 8, 2 },
+ { "ACCPLSTEP", 6, 2 },
+ { "ACCPLASTEP", 1, 5 },
+ { "FACCPL", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_AC_COUPLING_VALUE", 0x37658, 0 },
+ { "ACCPLMEANS", 15, 1 },
+ { "CDROVREN", 8, 1 },
+ { "ACCPLBIAS", 0, 8 },
+ { "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET", 0x3765c, 0 },
+ { "MAC_PORT_RX_LINKC_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37660, 0 },
+ { "H1OX", 8, 6 },
+ { "H1EX", 0, 6 },
+ { "MAC_PORT_RX_LINKC_PEAKED_INTEGRATOR", 0x37664, 0 },
+ { "PILOCK", 10, 1 },
+ { "UNPKPKA", 2, 6 },
+ { "UNPKVGA", 0, 2 },
+ { "MAC_PORT_RX_LINKC_CDR_ANALOG_SWITCH", 0x37668, 0 },
+ { "OVRAC", 15, 1 },
+ { "OVRPK", 14, 1 },
+ { "OVRTAILS", 12, 2 },
+ { "OVRTAILV", 9, 3 },
+ { "OVRCAP", 8, 1 },
+ { "OVRDCDPRE", 7, 1 },
+ { "OVRDCDPST", 6, 1 },
+ { "DCVSCTMODE", 2, 1 },
+ { "CDRANLGSW", 0, 2 },
+ { "MAC_PORT_RX_LINKC_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3766c, 0 },
+ { "PFLAG", 5, 2 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37670, 0 },
+ { "DACCLIP", 15, 1 },
+ { "DPCFRZ", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCLKNQ", 11, 1 },
+ { "DPCWDFE", 10, 1 },
+ { "DPCWPK", 9, 1 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x37674, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "VIEWSCAN", 4, 1 },
+ { "ODEC", 0, 4 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x37678, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "ACCCMP", 11, 1 },
+ { "DCCCMP", 10, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5IQCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3767c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x37680, 0 },
+ { "H25SPC", 15, 1 },
+ { "FDCCAL", 14, 1 },
+ { "FROTCAL", 13, 1 },
+ { "FIQAMP", 12, 1 },
+ { "FRPTCALF", 11, 1 },
+ { "FINTCALGS", 10, 1 },
+ { "FDCC", 9, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FDCD", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FINTRCALDYN", 1, 1 },
+ { "FQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_CHANNEL", 0x37684, 0 },
+ { "QCCIND", 13, 1 },
+ { "DCDIND", 10, 3 },
+ { "DCCIND", 8, 2 },
+ { "CFSEL", 5, 1 },
+ { "LOFCH", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DFE_OFFSET_VALUE", 0x37688, 0 },
+ { "LOFU", 8, 7 },
+ { "LOFL", 0, 7 },
+ { "MAC_PORT_RX_LINKC_H_COEFFICIENBT_BIST", 0x3768c, 0 },
+ { "HBISTMAN", 12, 1 },
+ { "HBISTRES", 11, 1 },
+ { "HBISTSP", 8, 3 },
+ { "HBISTEN", 7, 1 },
+ { "HBISTRST", 6, 1 },
+ { "HCOMP", 5, 1 },
+ { "HPASS", 4, 1 },
+ { "HSEL", 0, 4 },
+ { "MAC_PORT_RX_LINKC_AC_CAPACITOR_BIST", 0x37690, 0 },
+ { "ACCCMP", 13, 1 },
+ { "ACCEN", 12, 1 },
+ { "ACCRST", 11, 1 },
+ { "ACCIND", 8, 3 },
+ { "ACCRD", 0, 8 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL_REGISTER", 0x37698, 0 },
+ { "LFREG", 15, 1 },
+ { "LFRC", 14, 1 },
+ { "LGIDLE", 13, 1 },
+ { "LFTGT", 8, 5 },
+ { "LGTGT", 7, 1 },
+ { "LRDY", 6, 1 },
+ { "LIDLE", 5, 1 },
+ { "LCURR", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3769c, 0 },
+ { "OFFSN", 13, 2 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x376a0, 0 },
+ { "RX_OVRSUMPD", 15, 1 },
+ { "RX_OVRKBPD", 14, 1 },
+ { "RX_OVRDIVPD", 13, 1 },
+ { "RX_OFFVGADIS", 12, 1 },
+ { "RX_OFFACDIS", 11, 1 },
+ { "RX_VTERM", 10, 1 },
+ { "RX_DISSPY2D", 8, 1 },
+ { "RX_OBSOVEN", 7, 1 },
+ { "RX_LINKANLGSW", 0, 7 },
+ { "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x376a4, 0 },
+ { "INTDACEGS", 13, 3 },
+ { "INTDACE", 8, 5 },
+ { "INTDACGS", 6, 2 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x376a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x376ac, 0 },
+ { "SMQM", 13, 3 },
+ { "SMQ", 5, 8 },
+ { "EMMD", 3, 2 },
+ { "EMBRDY", 2, 1 },
+ { "EMBUMP", 1, 1 },
+ { "EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x376b0, 0 },
+ { "EMSF", 13, 1 },
+ { "EMDATA59", 12, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x376b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x376b8, 0 },
+ { "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_3", 0x376bc, 0 },
+ { "FTIMEOUT", 15, 1 },
+ { "FROTCAL4", 14, 1 },
+ { "FDCD2", 13, 1 },
+ { "FPRBSPOLTOG", 12, 1 },
+ { "FPRBSOFF2", 11, 1 },
+ { "FDDCAL2", 10, 1 },
+ { "FDDCFLTR", 9, 1 },
+ { "FDAC6", 8, 1 },
+ { "FDDC5", 7, 1 },
+ { "FDDC3456", 6, 1 },
+ { "FSPY2DATA", 5, 1 },
+ { "FPHSLOCK", 4, 1 },
+ { "FCLKALGN", 3, 1 },
+ { "FCLKALDYN", 2, 1 },
+ { "FDFE", 1, 1 },
+ { "FPRBSOFF", 0, 1 },
+ { "MAC_PORT_RX_LINKC_DFE_TAP_CONTROL", 0x376c0, 0 },
+ { "MAC_PORT_RX_LINKC_DFE_TAP", 0x376c4, 0 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS_2", 0x376e4, 0 },
+ { "STNDBYSTAT", 15, 1 },
+ { "CALSDONE", 14, 1 },
+ { "ACISRCCMP", 5, 1 },
+ { "PRBSOFFCMP", 4, 1 },
+ { "CLKALGNCMP", 3, 1 },
+ { "ROTFCMP", 2, 1 },
+ { "DCDCMP", 1, 1 },
+ { "QCCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKC_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x376e8, 0 },
+ { "FCSADJ", 6, 1 },
+ { "CSIND", 3, 2 },
+ { "CSVAL", 0, 3 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DCD_CONTROL", 0x376ec, 0 },
+ { "DCDTMDOUT", 15, 1 },
+ { "DCDTOEN", 14, 1 },
+ { "DCDLOCK", 13, 1 },
+ { "DCDSTEP", 11, 2 },
+ { "DCDALTWPDIS", 10, 1 },
+ { "DCDOVRDEN", 9, 1 },
+ { "DCCAOVRDEN", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_DCC_CONTROL", 0x376f0, 0 },
+ { "PRBSMODE", 14, 2 },
+ { "DCCSTEP", 10, 2 },
+ { "DCCOVRDEN", 9, 1 },
+ { "DCCLOCK", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_QCC_CONTROL", 0x376f4, 0 },
+ { "DCCQCCMODE", 15, 1 },
+ { "DCCQCCDYN", 14, 1 },
+ { "DCCQCCHOLD", 13, 1 },
+ { "QCCSTEP", 10, 2 },
+ { "QCCOVRDEN", 9, 1 },
+ { "QCCLOCK", 8, 1 },
+ { "QCCSIGN", 6, 2 },
+ { "QCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x376f8, 0 },
+ { "TSTCMP", 15, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x376fc, 0 },
+ { "CALMODEEDGE", 14, 1 },
+ { "TESTCAP", 13, 1 },
+ { "SNAPEN", 12, 1 },
+ { "ASYNCDIR", 11, 1 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x37700, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_MODE8023AZ", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x37704, 0 },
+ { "APLYDCD", 15, 1 },
+ { "PPOL", 13, 2 },
+ { "PCLKSEL", 11, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x37708, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3770c, 0 },
+ { "H1ANOFST", 12, 4 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "TMSCAL", 8, 2 },
+ { "APADJ", 7, 1 },
+ { "RSEL", 6, 1 },
+ { "PHOFFS", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x37710, 0 },
+ { "ROTA", 8, 6 },
+ { "ROTD", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x37714, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROTE", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37718, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOFFF", 8, 4 },
+ { "RAOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3771c, 0 },
+ { "RCALER", 15, 1 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x37720, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 8, 4 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x37724, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x37728, 0 },
+ { "REQWOV", 15, 1 },
+ { "RASEL", 11, 3 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3772c, 0 },
+ { "WRAPSEL", 15, 1 },
+ { "ACTL", 14, 1 },
+ { "PEAK", 9, 5 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x37730, 0 },
+ { "FVOFFSKP", 15, 1 },
+ { "FGAINCHK", 14, 1 },
+ { "FH1ACAL", 13, 1 },
+ { "FH1AFLTR", 11, 2 },
+ { "T5SHORTV", 10, 1 },
+ { "WGAIN", 8, 2 },
+ { "GAIN_STAT", 7, 1 },
+ { "T5VGAIN", 0, 7 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x37734, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37738, 0 },
+ { "PMCFG", 6, 2 },
+ { "PMOFFTIME", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_1", 0x3773c, 0 },
+ { "SELI", 9, 1 },
+ { "SERVREF", 5, 3 },
+ { "IQAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_IQAMP_CONTROL_2", 0x37740, 0 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37744, 0 },
+ { "SAVEADAC", 8, 1 },
+ { "LOAD2", 7, 1 },
+ { "LOAD1", 6, 1 },
+ { "WRTACC2", 5, 1 },
+ { "WRTACC1", 4, 1 },
+ { "SELAPAN", 3, 1 },
+ { "DASEL", 0, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x37748, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN", 0x3774c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x37750, 0 },
+ { "ADAC2", 8, 8 },
+ { "ADAC1", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_CONTROL", 0x37754, 0 },
+ { "FACCPLDYN", 13, 1 },
+ { "ACCPLGAIN", 10, 3 },
+ { "ACCPLREF", 8, 2 },
+ { "ACCPLSTEP", 6, 2 },
+ { "ACCPLASTEP", 1, 5 },
+ { "FACCPL", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_AC_COUPLING_VALUE", 0x37758, 0 },
+ { "ACCPLMEANS", 15, 1 },
+ { "CDROVREN", 8, 1 },
+ { "ACCPLBIAS", 0, 8 },
+ { "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET", 0x3775c, 0 },
+ { "MAC_PORT_RX_LINKD_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37760, 0 },
+ { "H1OX", 8, 6 },
+ { "H1EX", 0, 6 },
+ { "MAC_PORT_RX_LINKD_PEAKED_INTEGRATOR", 0x37764, 0 },
+ { "PILOCK", 10, 1 },
+ { "UNPKPKA", 2, 6 },
+ { "UNPKVGA", 0, 2 },
+ { "MAC_PORT_RX_LINKD_CDR_ANALOG_SWITCH", 0x37768, 0 },
+ { "OVRAC", 15, 1 },
+ { "OVRPK", 14, 1 },
+ { "OVRTAILS", 12, 2 },
+ { "OVRTAILV", 9, 3 },
+ { "OVRCAP", 8, 1 },
+ { "OVRDCDPRE", 7, 1 },
+ { "OVRDCDPST", 6, 1 },
+ { "DCVSCTMODE", 2, 1 },
+ { "CDRANLGSW", 0, 2 },
+ { "MAC_PORT_RX_LINKD_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x3776c, 0 },
+ { "PFLAG", 5, 2 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37770, 0 },
+ { "DACCLIP", 15, 1 },
+ { "DPCFRZ", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCLKNQ", 11, 1 },
+ { "DPCWDFE", 10, 1 },
+ { "DPCWPK", 9, 1 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x37774, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "VIEWSCAN", 4, 1 },
+ { "ODEC", 0, 4 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x37778, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "ACCCMP", 11, 1 },
+ { "DCCCMP", 10, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5IQCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3777c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x37780, 0 },
+ { "H25SPC", 15, 1 },
+ { "FDCCAL", 14, 1 },
+ { "FROTCAL", 13, 1 },
+ { "FIQAMP", 12, 1 },
+ { "FRPTCALF", 11, 1 },
+ { "FINTCALGS", 10, 1 },
+ { "FDCC", 9, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FDCD", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FINTRCALDYN", 1, 1 },
+ { "FQCC", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_CHANNEL", 0x37784, 0 },
+ { "QCCIND", 13, 1 },
+ { "DCDIND", 10, 3 },
+ { "DCCIND", 8, 2 },
+ { "CFSEL", 5, 1 },
+ { "LOFCH", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DFE_OFFSET_VALUE", 0x37788, 0 },
+ { "LOFU", 8, 7 },
+ { "LOFL", 0, 7 },
+ { "MAC_PORT_RX_LINKD_H_COEFFICIENBT_BIST", 0x3778c, 0 },
+ { "HBISTMAN", 12, 1 },
+ { "HBISTRES", 11, 1 },
+ { "HBISTSP", 8, 3 },
+ { "HBISTEN", 7, 1 },
+ { "HBISTRST", 6, 1 },
+ { "HCOMP", 5, 1 },
+ { "HPASS", 4, 1 },
+ { "HSEL", 0, 4 },
+ { "MAC_PORT_RX_LINKD_AC_CAPACITOR_BIST", 0x37790, 0 },
+ { "ACCCMP", 13, 1 },
+ { "ACCEN", 12, 1 },
+ { "ACCRST", 11, 1 },
+ { "ACCIND", 8, 3 },
+ { "ACCRD", 0, 8 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL_REGISTER", 0x37798, 0 },
+ { "LFREG", 15, 1 },
+ { "LFRC", 14, 1 },
+ { "LGIDLE", 13, 1 },
+ { "LFTGT", 8, 5 },
+ { "LGTGT", 7, 1 },
+ { "LRDY", 6, 1 },
+ { "LIDLE", 5, 1 },
+ { "LCURR", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3779c, 0 },
+ { "OFFSN", 13, 2 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x377a0, 0 },
+ { "RX_OVRSUMPD", 15, 1 },
+ { "RX_OVRKBPD", 14, 1 },
+ { "RX_OVRDIVPD", 13, 1 },
+ { "RX_OFFVGADIS", 12, 1 },
+ { "RX_OFFACDIS", 11, 1 },
+ { "RX_VTERM", 10, 1 },
+ { "RX_DISSPY2D", 8, 1 },
+ { "RX_OBSOVEN", 7, 1 },
+ { "RX_LINKANLGSW", 0, 7 },
+ { "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x377a4, 0 },
+ { "INTDACEGS", 13, 3 },
+ { "INTDACE", 8, 5 },
+ { "INTDACGS", 6, 2 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x377a8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x377ac, 0 },
+ { "SMQM", 13, 3 },
+ { "SMQ", 5, 8 },
+ { "EMMD", 3, 2 },
+ { "EMBRDY", 2, 1 },
+ { "EMBUMP", 1, 1 },
+ { "EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x377b0, 0 },
+ { "EMSF", 13, 1 },
+ { "EMDATA59", 12, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x377b4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x377b8, 0 },
+ { "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_3", 0x377bc, 0 },
+ { "FTIMEOUT", 15, 1 },
+ { "FROTCAL4", 14, 1 },
+ { "FDCD2", 13, 1 },
+ { "FPRBSPOLTOG", 12, 1 },
+ { "FPRBSOFF2", 11, 1 },
+ { "FDDCAL2", 10, 1 },
+ { "FDDCFLTR", 9, 1 },
+ { "FDAC6", 8, 1 },
+ { "FDDC5", 7, 1 },
+ { "FDDC3456", 6, 1 },
+ { "FSPY2DATA", 5, 1 },
+ { "FPHSLOCK", 4, 1 },
+ { "FCLKALGN", 3, 1 },
+ { "FCLKALDYN", 2, 1 },
+ { "FDFE", 1, 1 },
+ { "FPRBSOFF", 0, 1 },
+ { "MAC_PORT_RX_LINKD_DFE_TAP_CONTROL", 0x377c0, 0 },
+ { "MAC_PORT_RX_LINKD_DFE_TAP", 0x377c4, 0 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS_2", 0x377e4, 0 },
+ { "STNDBYSTAT", 15, 1 },
+ { "CALSDONE", 14, 1 },
+ { "ACISRCCMP", 5, 1 },
+ { "PRBSOFFCMP", 4, 1 },
+ { "CLKALGNCMP", 3, 1 },
+ { "ROTFCMP", 2, 1 },
+ { "DCDCMP", 1, 1 },
+ { "QCCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINKD_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x377e8, 0 },
+ { "FCSADJ", 6, 1 },
+ { "CSIND", 3, 2 },
+ { "CSVAL", 0, 3 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DCD_CONTROL", 0x377ec, 0 },
+ { "DCDTMDOUT", 15, 1 },
+ { "DCDTOEN", 14, 1 },
+ { "DCDLOCK", 13, 1 },
+ { "DCDSTEP", 11, 2 },
+ { "DCDALTWPDIS", 10, 1 },
+ { "DCDOVRDEN", 9, 1 },
+ { "DCCAOVRDEN", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_DCC_CONTROL", 0x377f0, 0 },
+ { "PRBSMODE", 14, 2 },
+ { "DCCSTEP", 10, 2 },
+ { "DCCOVRDEN", 9, 1 },
+ { "DCCLOCK", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_QCC_CONTROL", 0x377f4, 0 },
+ { "DCCQCCMODE", 15, 1 },
+ { "DCCQCCDYN", 14, 1 },
+ { "DCCQCCHOLD", 13, 1 },
+ { "QCCSTEP", 10, 2 },
+ { "QCCOVRDEN", 9, 1 },
+ { "QCCLOCK", 8, 1 },
+ { "QCCSIGN", 6, 2 },
+ { "QCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x377f8, 0 },
+ { "TSTCMP", 15, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x377fc, 0 },
+ { "CALMODEEDGE", 14, 1 },
+ { "TESTCAP", 13, 1 },
+ { "SNAPEN", 12, 1 },
+ { "ASYNCDIR", 11, 1 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x37a00, 0 },
+ { "T5_RX_LINKEN", 15, 1 },
+ { "T5_RX_LINKRST", 14, 1 },
+ { "T5_RX_CFGWRT", 13, 1 },
+ { "T5_RX_CFGPTR", 11, 2 },
+ { "T5_RX_CFGEXT", 10, 1 },
+ { "T5_RX_CFGACT", 9, 1 },
+ { "T5_RX_MODE8023AZ", 8, 1 },
+ { "T5_RX_PLLSEL", 6, 2 },
+ { "T5_RX_DMSEL", 4, 2 },
+ { "T5_RX_BWSEL", 2, 2 },
+ { "T5_RX_RTSEL", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x37a04, 0 },
+ { "APLYDCD", 15, 1 },
+ { "PPOL", 13, 2 },
+ { "PCLKSEL", 11, 2 },
+ { "FERRST", 10, 1 },
+ { "ERRST", 9, 1 },
+ { "SYNCST", 8, 1 },
+ { "WRPSM", 7, 1 },
+ { "WPLPEN", 6, 1 },
+ { "WRPMD", 5, 1 },
+ { "PRST", 4, 1 },
+ { "PCHKEN", 3, 1 },
+ { "PATSEL", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x37a08, 0 },
+ { "FTHROT", 12, 4 },
+ { "RTHROT", 11, 1 },
+ { "FILTCTL", 7, 4 },
+ { "RSRVO", 5, 2 },
+ { "EXTEL", 4, 1 },
+ { "RSTUCK", 3, 1 },
+ { "FRZFW", 2, 1 },
+ { "RSTFW", 1, 1 },
+ { "SSCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x37a0c, 0 },
+ { "H1ANOFST", 12, 4 },
+ { "RSNP", 11, 1 },
+ { "TSOEN", 10, 1 },
+ { "TMSCAL", 8, 2 },
+ { "APADJ", 7, 1 },
+ { "RSEL", 6, 1 },
+ { "PHOFFS", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x37a10, 0 },
+ { "ROTA", 8, 6 },
+ { "ROTD", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x37a14, 0 },
+ { "FREQFW", 8, 8 },
+ { "FWSNAP", 7, 1 },
+ { "ROTE", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37a18, 0 },
+ { "RCALER", 15, 1 },
+ { "RAOFFF", 8, 4 },
+ { "RAOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x37a1c, 0 },
+ { "RCALER", 15, 1 },
+ { "RDOFF", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x37a20, 0 },
+ { "REQCMP", 15, 1 },
+ { "DFEREQ", 14, 1 },
+ { "SPCEN", 13, 1 },
+ { "GATEEN", 12, 1 },
+ { "SPIFMT", 8, 4 },
+ { "STNDBY", 5, 1 },
+ { "FRCH", 4, 1 },
+ { "NONRND", 3, 1 },
+ { "NONRNF", 2, 1 },
+ { "FSTLCK", 1, 1 },
+ { "DFERST", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x37a24, 0 },
+ { "T5BYTE1", 8, 8 },
+ { "T5BYTE0", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x37a28, 0 },
+ { "REQWOV", 15, 1 },
+ { "RASEL", 11, 3 },
+ { "T5_RX_SMODE", 8, 3 },
+ { "T5_RX_ADCORR", 7, 1 },
+ { "T5_RX_TRAINEN", 6, 1 },
+ { "T5_RX_ASAMPQ", 3, 3 },
+ { "T5_RX_ASAMP", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x37a2c, 0 },
+ { "WRAPSEL", 15, 1 },
+ { "ACTL", 14, 1 },
+ { "PEAK", 9, 5 },
+ { "VOFFA", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x37a30, 0 },
+ { "FVOFFSKP", 15, 1 },
+ { "FGAINCHK", 14, 1 },
+ { "FH1ACAL", 13, 1 },
+ { "FH1AFLTR", 11, 2 },
+ { "T5SHORTV", 10, 1 },
+ { "WGAIN", 8, 2 },
+ { "GAIN_STAT", 7, 1 },
+ { "T5VGAIN", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x37a34, 0 },
+ { "HBND1", 10, 1 },
+ { "HBND0", 9, 1 },
+ { "VLCKD", 8, 1 },
+ { "VLCKDF", 7, 1 },
+ { "AMAXT", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_POWER_MANAGEMENT_CONTROL", 0x37a38, 0 },
+ { "PMCFG", 6, 2 },
+ { "PMOFFTIME", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_1", 0x37a3c, 0 },
+ { "SELI", 9, 1 },
+ { "SERVREF", 5, 3 },
+ { "IQAMP", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_IQAMP_CONTROL_2", 0x37a40, 0 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN_SELECTION", 0x37a44, 0 },
+ { "SAVEADAC", 8, 1 },
+ { "LOAD2", 7, 1 },
+ { "LOAD1", 6, 1 },
+ { "WRTACC2", 5, 1 },
+ { "WRTACC1", 4, 1 },
+ { "SELAPAN", 3, 1 },
+ { "DASEL", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x37a48, 0 },
+ { "DACAN", 8, 8 },
+ { "DACAP", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN", 0x37a4c, 0 },
+ { "DACAZ", 8, 8 },
+ { "DACAM", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x37a50, 0 },
+ { "ADAC2", 8, 8 },
+ { "ADAC1", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_CONTROL", 0x37a54, 0 },
+ { "FACCPLDYN", 13, 1 },
+ { "ACCPLGAIN", 10, 3 },
+ { "ACCPLREF", 8, 2 },
+ { "ACCPLSTEP", 6, 2 },
+ { "ACCPLASTEP", 1, 5 },
+ { "FACCPL", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_AC_COUPLING_VALUE", 0x37a58, 0 },
+ { "ACCPLMEANS", 15, 1 },
+ { "CDROVREN", 8, 1 },
+ { "ACCPLBIAS", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET", 0x37a5c, 0 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_H1H2H3_LOCAL_OFFSET_VALUE", 0x37a60, 0 },
+ { "H1OX", 8, 6 },
+ { "H1EX", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_PEAKED_INTEGRATOR", 0x37a64, 0 },
+ { "PILOCK", 10, 1 },
+ { "UNPKPKA", 2, 6 },
+ { "UNPKVGA", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_CDR_ANALOG_SWITCH", 0x37a68, 0 },
+ { "OVRAC", 15, 1 },
+ { "OVRPK", 14, 1 },
+ { "OVRTAILS", 12, 2 },
+ { "OVRTAILV", 9, 3 },
+ { "OVRCAP", 8, 1 },
+ { "OVRDCDPRE", 7, 1 },
+ { "OVRDCDPST", 6, 1 },
+ { "DCVSCTMODE", 2, 1 },
+ { "CDRANLGSW", 0, 2 },
+ { "MAC_PORT_RX_LINK_BCST_PEAKING_AMPLIFIER_INTIALIZATION_CONTROL", 0x37a6c, 0 },
+ { "PFLAG", 5, 2 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37a70, 0 },
+ { "DACCLIP", 15, 1 },
+ { "DPCFRZ", 14, 1 },
+ { "DPCCVG", 13, 1 },
+ { "DACCVG", 12, 1 },
+ { "DPCLKNQ", 11, 1 },
+ { "DPCWDFE", 10, 1 },
+ { "DPCWPK", 9, 1 },
+ { "BLKH1T", 8, 1 },
+ { "BLKOAE", 7, 1 },
+ { "H1TGT", 4, 3 },
+ { "OAE", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x37a74, 0 },
+ { "OLS", 11, 5 },
+ { "OES", 6, 5 },
+ { "BLKODEC", 5, 1 },
+ { "VIEWSCAN", 4, 1 },
+ { "ODEC", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x37a78, 0 },
+ { "T5BER6VAL", 15, 1 },
+ { "T5BER6", 14, 1 },
+ { "T5BER3VAL", 13, 1 },
+ { "T5TOOFAST", 12, 1 },
+ { "ACCCMP", 11, 1 },
+ { "DCCCMP", 10, 1 },
+ { "T5DPCCMP", 9, 1 },
+ { "T5DACCMP", 8, 1 },
+ { "T5DDCCMP", 7, 1 },
+ { "T5AERRFLG", 6, 1 },
+ { "T5WERRFLG", 5, 1 },
+ { "T5TRCMP", 4, 1 },
+ { "T5VLCKF", 3, 1 },
+ { "T5ROCCMP", 2, 1 },
+ { "T5IQCMP", 1, 1 },
+ { "T5OCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x37a7c, 0 },
+ { "FDPC", 15, 1 },
+ { "FDAC", 14, 1 },
+ { "FDDC", 13, 1 },
+ { "FNRND", 12, 1 },
+ { "FVGAIN", 11, 1 },
+ { "FVOFF", 10, 1 },
+ { "FSDET", 9, 1 },
+ { "FBER6", 8, 1 },
+ { "FROTO", 7, 1 },
+ { "FH4H5", 6, 1 },
+ { "FH2H3", 5, 1 },
+ { "FH1", 4, 1 },
+ { "FH1SN", 3, 1 },
+ { "FNRDF", 2, 1 },
+ { "FLOFF", 1, 1 },
+ { "FADAC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x37a80, 0 },
+ { "H25SPC", 15, 1 },
+ { "FDCCAL", 14, 1 },
+ { "FROTCAL", 13, 1 },
+ { "FIQAMP", 12, 1 },
+ { "FRPTCALF", 11, 1 },
+ { "FINTCALGS", 10, 1 },
+ { "FDCC", 9, 1 },
+ { "FTOOFAST", 8, 1 },
+ { "FDCD", 7, 1 },
+ { "FDINV", 6, 1 },
+ { "FHGS", 5, 1 },
+ { "FH6H12", 4, 1 },
+ { "FH1CAL", 3, 1 },
+ { "FINTCAL", 2, 1 },
+ { "FINTRCALDYN", 1, 1 },
+ { "FQCC", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_CHANNEL", 0x37a84, 0 },
+ { "QCCIND", 13, 1 },
+ { "DCDIND", 10, 3 },
+ { "DCCIND", 8, 2 },
+ { "CFSEL", 5, 1 },
+ { "LOFCH", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_VALUE", 0x37a88, 0 },
+ { "LOFU", 8, 7 },
+ { "LOFL", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_H_COEFFICIENBT_BIST", 0x37a8c, 0 },
+ { "HBISTMAN", 12, 1 },
+ { "HBISTRES", 11, 1 },
+ { "HBISTSP", 8, 3 },
+ { "HBISTEN", 7, 1 },
+ { "HBISTRST", 6, 1 },
+ { "HCOMP", 5, 1 },
+ { "HPASS", 4, 1 },
+ { "HSEL", 0, 4 },
+ { "MAC_PORT_RX_LINK_BCST_AC_CAPACITOR_BIST", 0x37a90, 0 },
+ { "ACCCMP", 13, 1 },
+ { "ACCEN", 12, 1 },
+ { "ACCRST", 11, 1 },
+ { "ACCIND", 8, 3 },
+ { "ACCRD", 0, 8 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL_REGISTER", 0x37a98, 0 },
+ { "LFREG", 15, 1 },
+ { "LFRC", 14, 1 },
+ { "LGIDLE", 13, 1 },
+ { "LFTGT", 8, 5 },
+ { "LGTGT", 7, 1 },
+ { "LRDY", 6, 1 },
+ { "LIDLE", 5, 1 },
+ { "LCURR", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x37a9c, 0 },
+ { "OFFSN", 13, 2 },
+ { "OFFAMP", 8, 5 },
+ { "SDACDC", 7, 1 },
+ { "SDPDN", 6, 1 },
+ { "SIGDET", 5, 1 },
+ { "SDLVL", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x37aa0, 0 },
+ { "RX_OVRSUMPD", 15, 1 },
+ { "RX_OVRKBPD", 14, 1 },
+ { "RX_OVRDIVPD", 13, 1 },
+ { "RX_OFFVGADIS", 12, 1 },
+ { "RX_OFFACDIS", 11, 1 },
+ { "RX_VTERM", 10, 1 },
+ { "RX_DISSPY2D", 8, 1 },
+ { "RX_OBSOVEN", 7, 1 },
+ { "RX_LINKANLGSW", 0, 7 },
+ { "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x37aa4, 0 },
+ { "INTDACEGS", 13, 3 },
+ { "INTDACE", 8, 5 },
+ { "INTDACGS", 6, 2 },
+ { "INTDAC", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x37aa8, 0 },
+ { "BLKAZ", 15, 1 },
+ { "WIDTH", 10, 5 },
+ { "MINWDTH", 5, 5 },
+ { "MINAMP", 0, 5 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x37aac, 0 },
+ { "SMQM", 13, 3 },
+ { "SMQ", 5, 8 },
+ { "EMMD", 3, 2 },
+ { "EMBRDY", 2, 1 },
+ { "EMBUMP", 1, 1 },
+ { "EMEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x37ab0, 0 },
+ { "EMSF", 13, 1 },
+ { "EMDATA59", 12, 1 },
+ { "EMCNT", 4, 8 },
+ { "EMOFLO", 2, 1 },
+ { "EMCRST", 1, 1 },
+ { "EMCEN", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x37ab4, 0 },
+ { "SM2RDY", 15, 1 },
+ { "SM2RST", 14, 1 },
+ { "APDF", 0, 12 },
+ { "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x37ab8, 0 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_3", 0x37abc, 0 },
+ { "FTIMEOUT", 15, 1 },
+ { "FROTCAL4", 14, 1 },
+ { "FDCD2", 13, 1 },
+ { "FPRBSPOLTOG", 12, 1 },
+ { "FPRBSOFF2", 11, 1 },
+ { "FDDCAL2", 10, 1 },
+ { "FDDCFLTR", 9, 1 },
+ { "FDAC6", 8, 1 },
+ { "FDDC5", 7, 1 },
+ { "FDDC3456", 6, 1 },
+ { "FSPY2DATA", 5, 1 },
+ { "FPHSLOCK", 4, 1 },
+ { "FCLKALGN", 3, 1 },
+ { "FCLKALDYN", 2, 1 },
+ { "FDFE", 1, 1 },
+ { "FPRBSOFF", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_TAP_CONTROL", 0x37ac0, 0 },
+ { "MAC_PORT_RX_LINK_BCST_DFE_TAP", 0x37ac4, 0 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS_2", 0x37ae4, 0 },
+ { "STNDBYSTAT", 15, 1 },
+ { "CALSDONE", 14, 1 },
+ { "ACISRCCMP", 5, 1 },
+ { "PRBSOFFCMP", 4, 1 },
+ { "CLKALGNCMP", 3, 1 },
+ { "ROTFCMP", 2, 1 },
+ { "DCDCMP", 1, 1 },
+ { "QCCCMP", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_AC_COUPLING_CURRENT_SOURCE_ADJUST", 0x37ae8, 0 },
+ { "FCSADJ", 6, 1 },
+ { "CSIND", 3, 2 },
+ { "CSVAL", 0, 3 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DCD_CONTROL", 0x37aec, 0 },
+ { "DCDTMDOUT", 15, 1 },
+ { "DCDTOEN", 14, 1 },
+ { "DCDLOCK", 13, 1 },
+ { "DCDSTEP", 11, 2 },
+ { "DCDALTWPDIS", 10, 1 },
+ { "DCDOVRDEN", 9, 1 },
+ { "DCCAOVRDEN", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_DCC_CONTROL", 0x37af0, 0 },
+ { "PRBSMODE", 14, 2 },
+ { "DCCSTEP", 10, 2 },
+ { "DCCOVRDEN", 9, 1 },
+ { "DCCLOCK", 8, 1 },
+ { "DCDSIGN", 6, 2 },
+ { "DCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_QCC_CONTROL", 0x37af4, 0 },
+ { "DCCQCCMODE", 15, 1 },
+ { "DCCQCCDYN", 14, 1 },
+ { "DCCQCCHOLD", 13, 1 },
+ { "QCCSTEP", 10, 2 },
+ { "QCCOVRDEN", 9, 1 },
+ { "QCCLOCK", 8, 1 },
+ { "QCCSIGN", 6, 2 },
+ { "QCDAMP", 0, 6 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_REGISTER_2", 0x37af8, 0 },
+ { "TSTCMP", 15, 1 },
+ { "SDLSSD", 5, 1 },
+ { "DFEOBSBIAS", 4, 1 },
+ { "GBOFSTLSSD", 3, 1 },
+ { "RXDOBS", 2, 1 },
+ { "ACJZPT", 1, 1 },
+ { "ACJZNT", 0, 1 },
+ { "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x37afc, 0 },
+ { "CALMODEEDGE", 14, 1 },
+ { "TESTCAP", 13, 1 },
+ { "SNAPEN", 12, 1 },
+ { "ASYNCDIR", 11, 1 },
+ { "PHSLOCK", 10, 1 },
+ { "TESTMODE", 9, 1 },
+ { "CALMODE", 8, 1 },
+ { "ACJPDP", 3, 1 },
+ { "ACJPDN", 2, 1 },
+ { "LSSDT", 1, 1 },
+ { "MTHOLD", 0, 1 },
+ { NULL }
+};
+
+struct reg_info t6_mc_0_regs[] = {
+ { "MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS", 0x47000, 0 },
+ { "DP18_PLL_LOCK", 1, 15 },
+ { "MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS", 0x47004, 0 },
+ { "AD32S_PLL_LOCK", 14, 2 },
+ { "MC_DDRPHY_PC_RANK_PAIR0", 0x47008, 0 },
+ { "RANK_PAIR0_PRI", 13, 3 },
+ { "RANK_PAIR0_PRI_V", 12, 1 },
+ { "RANK_PAIR0_SEC", 9, 3 },
+ { "RANK_PAIR0_SEC_V", 8, 1 },
+ { "RANK_PAIR1_PRI", 5, 3 },
+ { "RANK_PAIR1_PRI_V", 4, 1 },
+ { "RANK_PAIR1_SEC", 1, 3 },
+ { "RANK_PAIR1_SEC_V", 0, 1 },
+ { "MC_DDRPHY_PC_RANK_PAIR1", 0x4700c, 0 },
+ { "RANK_PAIR2_PRI", 13, 3 },
+ { "RANK_PAIR2_PRI_V", 12, 1 },
+ { "RANK_PAIR2_SEC", 9, 3 },
+ { "RANK_PAIR2_SEC_V", 8, 1 },
+ { "RANK_PAIR3_PRI", 5, 3 },
+ { "RANK_PAIR3_PRI_V", 4, 1 },
+ { "RANK_PAIR3_SEC", 1, 3 },
+ { "RANK_PAIR3_SEC_V", 0, 1 },
+ { "MC_DDRPHY_PC_BASE_CNTR0", 0x47010, 0 },
+ { "MC_DDRPHY_PC_RELOAD_VALUE0", 0x47014, 0 },
+ { "PERIODIC_CAL_REQ_EN", 15, 1 },
+ { "PERIODIC_RELOAD_VALUE0", 0, 15 },
+ { "MC_DDRPHY_PC_BASE_CNTR1", 0x47018, 0 },
+ { "MC_DDRPHY_PC_CAL_TIMER", 0x4701c, 0 },
+ { "MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE", 0x47020, 0 },
+ { "MC_DDRPHY_PC_ZCAL_TIMER", 0x47024, 0 },
+ { "MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE", 0x47028, 0 },
+ { "MC_DDRPHY_PC_PER_CAL_CONFIG", 0x4702c, 0 },
+ { "PER_ENA_RANK_PAIR", 12, 4 },
+ { "PER_ENA_ZCAL", 11, 1 },
+ { "PER_ENA_SYSCLK_ALIGN", 10, 1 },
+ { "ENA_PER_RD_CTR", 9, 1 },
+ { "ENA_PER_RDCLK_ALIGN", 8, 1 },
+ { "ENA_PER_DQS_ALIGN", 7, 1 },
+ { "PER_NEXT_RANK_PAIR", 5, 2 },
+ { "FAST_SIM_PER_CNTR", 4, 1 },
+ { "START_INIT_CAL", 3, 1 },
+ { "START_PER_CAL", 2, 1 },
+ { "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4703c, 0 },
+ { "PER_ZCAL_ENA_RANK", 8, 8 },
+ { "PER_ZCAL_NEXT_RANK", 5, 3 },
+ { "START_PER_ZCAL", 4, 1 },
+ { "MC_DDRPHY_PC_CONFIG0", 0x47030, 0 },
+ { "DDRPHY_PROTOCOL", 12, 4 },
+ { "DATA_MUX4_1MODE", 11, 1 },
+ { "SPAM_EN", 10, 1 },
+ { "DDR4_CMD_SIG_REDUCTION", 9, 1 },
+ { "SYSCLK_2X_MEMINTCLKO", 8, 1 },
+ { "LOW_LATENCY", 3, 1 },
+ { "DDR4_IPW_LOOP_DIS", 2, 1 },
+ { "DDR4_VLEVEL_BANK_GROUP", 1, 1 },
+ { "MC_DDRPHY_PC_CONFIG1", 0x47034, 0 },
+ { "WRITE_LATENCY_OFFSET", 12, 4 },
+ { "READ_LATENCY_OFFSET", 8, 4 },
+ { "MEMCTL_CIC_FAST", 7, 1 },
+ { "MEMCTL_CIS_IGNORE", 6, 1 },
+ { "DISABLE_MEMCTL_CAL", 5, 1 },
+ { "MEMORY_TYPE", 2, 3 },
+ { "DDR4_PDA_MODE", 1, 1 },
+ { "MC_DDRPHY_PC_RESETS", 0x47038, 0 },
+ { "PLL_RESET", 15, 1 },
+ { "SYSCLK_RESET", 14, 1 },
+ { "MC_DDRPHY_PC_ERROR_STATUS0", 0x47048, 0 },
+ { "RC_ERROR", 15, 1 },
+ { "WC_ERROR", 14, 1 },
+ { "SEQ_ERROR", 13, 1 },
+ { "CC_ERROR", 12, 1 },
+ { "APB_ERROR", 11, 1 },
+ { "PC_ERROR", 10, 1 },
+ { "MC_DDRPHY_PC_ERROR_MASK0", 0x4704c, 0 },
+ { "RC_ERROR_MASK", 15, 1 },
+ { "WC_ERROR_MASK", 14, 1 },
+ { "SEQ_ERROR_MASK", 13, 1 },
+ { "CC_ERROR_MASK", 12, 1 },
+ { "APB_ERROR_MASK", 11, 1 },
+ { "PC_ERROR_MASK", 10, 1 },
+ { "MC_DDRPHY_PC_IO_PVT_FET_CONTROL", 0x47050, 0 },
+ { "PVTP", 11, 5 },
+ { "PVTN", 6, 5 },
+ { "PVT_OVERRIDE", 5, 1 },
+ { "ENABLE_ZCAL", 4, 1 },
+ { "MC_DDRPHY_PC_VREF_DRV_CONTROL", 0x47054, 0 },
+ { "VREFDQ0DSGN", 15, 1 },
+ { "VREFDQ0D", 11, 4 },
+ { "VREFDQ1DSGN", 10, 1 },
+ { "VREFDQ1D", 6, 4 },
+ { "EN_ANALOG_PD", 3, 1 },
+ { "ANALOG_PD_DLY", 2, 1 },
+ { "ANALOG_PD_DIV", 0, 2 },
+ { "MC_DDRPHY_PC_INIT_CAL_CONFIG0", 0x47058, 0 },
+ { "ENA_WR_LEVEL", 15, 1 },
+ { "ENA_INITIAL_PAT_WR", 14, 1 },
+ { "ENA_DQS_ALIGN", 13, 1 },
+ { "ENA_RDCLK_ALIGN", 12, 1 },
+ { "ENA_READ_CTR", 11, 1 },
+ { "ENA_WRITE_CTR", 10, 1 },
+ { "ENA_INITIAL_COARSE_WR", 9, 1 },
+ { "ENA_COARSE_RD", 8, 1 },
+ { "ENA_CUSTOM_RD", 7, 1 },
+ { "ENA_CUSTOM_WR", 6, 1 },
+ { "ABORT_ON_CAL_ERROR", 5, 1 },
+ { "ENA_DIGITAL_EYE", 4, 1 },
+ { "ENA_RANK_PAIR", 0, 4 },
+ { "MC_DDRPHY_PC_INIT_CAL_CONFIG1", 0x4705c, 0 },
+ { "REFRESH_COUNT", 12, 4 },
+ { "REFRESH_CONTROL", 10, 2 },
+ { "REFRESH_ALL_RANKS", 9, 1 },
+ { "REFRESH_INTERVAL", 0, 7 },
+ { "MC_DDRPHY_PC_INIT_CAL_ERROR", 0x47060, 0 },
+ { "ERROR_WR_LEVEL", 15, 1 },
+ { "ERROR_INITIAL_PAT_WRITE", 14, 1 },
+ { "ERROR_DQS_ALIGN", 13, 1 },
+ { "ERROR_RDCLK_ALIGN", 12, 1 },
+ { "ERROR_READ_CTR", 11, 1 },
+ { "ERROR_WRITE_CTR", 10, 1 },
+ { "ERROR_INITIAL_COARSE_WR", 9, 1 },
+ { "ERROR_COARSE_RD", 8, 1 },
+ { "ERROR_CUSTOM_RD", 7, 1 },
+ { "ERROR_CUSTOM_WR", 6, 1 },
+ { "ERROR_DIGITAL_EYE", 5, 1 },
+ { "ERROR_RANK_PAIR", 0, 4 },
+ { "MC_DDRPHY_PC_INIT_CAL_MASK", 0x47068, 0 },
+ { "ERROR_WR_LEVEL_MASK", 15, 1 },
+ { "ERROR_INITIAL_PAT_WRITE_MASK", 14, 1 },
+ { "ERROR_DQS_ALIGN_MASK", 13, 1 },
+ { "ERROR_RDCLK_ALIGN_MASK", 12, 1 },
+ { "ERROR_READ_CTR_MASK", 11, 1 },
+ { "ERROR_WRITE_CTR_MASK", 10, 1 },
+ { "ERROR_INITIAL_COARSE_WR_MASK", 9, 1 },
+ { "ERROR_COARSE_RD_MASK", 8, 1 },
+ { "ERROR_CUSTOM_RD_MASK", 7, 1 },
+ { "ERROR_CUSTOM_WR_MASK", 6, 1 },
+ { "ERROR_DIGITAL_EYE_MASK", 5, 1 },
+ { "MC_DDRPHY_PC_INIT_CAL_STATUS", 0x47064, 0 },
+ { "INIT_CAL_COMPLETE", 12, 4 },
+ { "PER_CAL_ABORT", 6, 1 },
+ { "MC_DDRPHY_PC_IO_PVT_FET_STATUS", 0x4706c, 0 },
+ { "PVTP", 11, 5 },
+ { "PVTN", 6, 5 },
+ { "MC_DDRPHY_PC_MR0_PRI_RP", 0x47070, 0 },
+ { "MC_DDRPHY_PC_MR1_PRI_RP", 0x47074, 0 },
+ { "MC_DDRPHY_PC_MR2_PRI_RP", 0x47078, 0 },
+ { "MC_DDRPHY_PC_MR3_PRI_RP", 0x4707c, 0 },
+ { "MC_DDRPHY_PC_MR0_SEC_RP", 0x47080, 0 },
+ { "MC_DDRPHY_PC_MR1_SEC_RP", 0x47084, 0 },
+ { "MC_DDRPHY_PC_MR2_SEC_RP", 0x47088, 0 },
+ { "MC_DDRPHY_PC_MR3_SEC_RP", 0x4708c, 0 },
+ { "MC_DDRPHY_PC_RANK_GROUP", 0x47044, 0 },
+ { "ADDR_MIRROR_RP0_PRI", 15, 1 },
+ { "ADDR_MIRROR_RP0_SEC", 14, 1 },
+ { "ADDR_MIRROR_RP1_PRI", 13, 1 },
+ { "ADDR_MIRROR_RP1_SEC", 12, 1 },
+ { "ADDR_MIRROR_RP2_PRI", 11, 1 },
+ { "ADDR_MIRROR_RP2_SEC", 10, 1 },
+ { "ADDR_MIRROR_RP3_PRI", 9, 1 },
+ { "ADDR_MIRROR_RP3_SEC", 8, 1 },
+ { "RANK_GROUPING", 6, 2 },
+ { "ADDR_MIRROR_A3_A4", 5, 1 },
+ { "ADDR_MIRROR_A5_A6", 4, 1 },
+ { "ADDR_MIRROR_A7_A8", 3, 1 },
+ { "ADDR_MIRROR_A11_A13", 2, 1 },
+ { "ADDR_MIRROR_BA0_BA1", 1, 1 },
+ { "ADDR_MIRROR_BG0_BG1", 0, 1 },
+ { "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45800, 0 },
+ { "BIT_ENABLE_0_11", 4, 12 },
+ { "BIT_ENABLE_12_15", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45804, 0 },
+ { "DI_ADR0_ADR1", 15, 1 },
+ { "DI_ADR2_ADR3", 14, 1 },
+ { "DI_ADR4_ADR5", 13, 1 },
+ { "DI_ADR6_ADR7", 12, 1 },
+ { "DI_ADR8_ADR9", 11, 1 },
+ { "DI_ADR10_ADR11", 10, 1 },
+ { "DI_ADR12_ADR13", 9, 1 },
+ { "DI_ADR14_ADR15", 8, 1 },
+ { "MC_ADR_DDRPHY_ADR_DELAY0", 0x45810, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY1", 0x45814, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY2", 0x45818, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY3", 0x4581c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY4", 0x45820, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY5", 0x45824, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY6", 0x45828, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY7", 0x4582c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45830, 0 },
+ { "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
+ { "ADR_TEST_DATA_EN", 7, 1 },
+ { "ADR_TEST_MODE", 5, 2 },
+ { "ADR_TEST_4TO1_MODE", 4, 1 },
+ { "ADR_TEST_RESET", 3, 1 },
+ { "ADR_TEST_GEN_EN", 2, 1 },
+ { "ADR_TEST_CLEAR_ERROR", 1, 1 },
+ { "ADR_TEST_CHECK_EN", 0, 1 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45840, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45844, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45848, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4584c, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45850, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45854, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45858, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4585c, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45880, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45884, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45860, 0 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x458a0, 0 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x458a4, 0 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45868, 0 },
+ { "SLEW_CTL0", 12, 4 },
+ { "SLEW_CTL1", 8, 4 },
+ { "SLEW_CTL2", 4, 4 },
+ { "SLEW_CTL3", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x458a8, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x458ac, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x458b0, 0 },
+ { "ADR_LANE_0_11_PD", 4, 12 },
+ { "ADR_LANE_12_15_PD", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45a00, 0 },
+ { "BIT_ENABLE_0_11", 4, 12 },
+ { "BIT_ENABLE_12_15", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45a04, 0 },
+ { "DI_ADR0_ADR1", 15, 1 },
+ { "DI_ADR2_ADR3", 14, 1 },
+ { "DI_ADR4_ADR5", 13, 1 },
+ { "DI_ADR6_ADR7", 12, 1 },
+ { "DI_ADR8_ADR9", 11, 1 },
+ { "DI_ADR10_ADR11", 10, 1 },
+ { "DI_ADR12_ADR13", 9, 1 },
+ { "DI_ADR14_ADR15", 8, 1 },
+ { "MC_ADR_DDRPHY_ADR_DELAY0", 0x45a10, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY1", 0x45a14, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY2", 0x45a18, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY3", 0x45a1c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY4", 0x45a20, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY5", 0x45a24, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY6", 0x45a28, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DELAY7", 0x45a2c, 0 },
+ { "ADR_DELAY_BITS1_7", 8, 7 },
+ { "ADR_DELAY_BITS9_15", 0, 7 },
+ { "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45a30, 0 },
+ { "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
+ { "ADR_TEST_DATA_EN", 7, 1 },
+ { "ADR_TEST_MODE", 5, 2 },
+ { "ADR_TEST_4TO1_MODE", 4, 1 },
+ { "ADR_TEST_RESET", 3, 1 },
+ { "ADR_TEST_GEN_EN", 2, 1 },
+ { "ADR_TEST_CLEAR_ERROR", 1, 1 },
+ { "ADR_TEST_CHECK_EN", 0, 1 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45a40, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45a44, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45a48, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x45a4c, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45a50, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45a54, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45a58, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x45a5c, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45a80, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45a84, 0 },
+ { "SLICE_SEL_REG_BITS0_1", 14, 2 },
+ { "SLICE_SEL_REG_BITS2_3", 12, 2 },
+ { "SLICE_SEL_REG_BITS4_5", 10, 2 },
+ { "SLICE_SEL_REG_BITS6_7", 8, 2 },
+ { "SLICE_SEL_REG_BITS8_9", 6, 2 },
+ { "SLICE_SEL_REG_BITS10_11", 4, 2 },
+ { "SLICE_SEL_REG_BITS12_13", 2, 2 },
+ { "SLICE_SEL_REG_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45a60, 0 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x45aa0, 0 },
+ { "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x45aa4, 0 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45a68, 0 },
+ { "SLEW_CTL0", 12, 4 },
+ { "SLEW_CTL1", 8, 4 },
+ { "SLEW_CTL2", 4, 4 },
+ { "SLEW_CTL3", 0, 4 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x45aa8, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x45aac, 0 },
+ { "SLEW_CTL_SEL_BITS0_1", 14, 2 },
+ { "SLEW_CTL_SEL_BITS2_3", 12, 2 },
+ { "SLEW_CTL_SEL_BITS4_5", 10, 2 },
+ { "SLEW_CTL_SEL_BITS6_7", 8, 2 },
+ { "SLEW_CTL_SEL_BITS8_9", 6, 2 },
+ { "SLEW_CTL_SEL_BITS10_11", 4, 2 },
+ { "SLEW_CTL_SEL_BITS12_13", 2, 2 },
+ { "SLEW_CTL_SEL_BITS14_15", 0, 2 },
+ { "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x45ab0, 0 },
+ { "ADR_LANE_0_11_PD", 4, 12 },
+ { "ADR_LANE_12_15_PD", 0, 4 },
+ { "MC_DDRPHY_AD32S_PLL_VREG_CONFIG_0", 0x460c0, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_AD32S_PLL_VREG_CONFIG_1", 0x460c4, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "VREG_VREGSPARE", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "INTERP_SIG_SLEW_0_3", 1, 4 },
+ { "ANALOG_WRAPON", 0, 1 },
+ { "MC_DDRPHY_AD32S_SYSCLK_CNTL_PR", 0x460c8, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESE", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "CE0DLTVCC", 0, 2 },
+ { "MC_DDRPHY_AD32S_MCCLK_WRCLK_PR_STATIC_OFFSET", 0x460cc, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_AD32S_SYSCLK_PR_VALUE_RO", 0x460d0, 0 },
+ { "SLEW_LATE_SAMPLE", 15, 1 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "SLEW_EARLY_SAMPLE", 6, 1 },
+ { "SLEW_DONE_STATUS", 4, 2 },
+ { "SLEW_CNTL", 0, 4 },
+ { "MC_DDRPHY_AD32S_OUTPUT_FORCE_ATEST_CNTL", 0x460d4, 0 },
+ { "FLUSH", 15, 1 },
+ { "FORCE_EN", 14, 1 },
+ { "AD32S_HS_PROBE_A_SEL", 8, 4 },
+ { "AD32S_HS_PROBE_B_SEL", 4, 4 },
+ { "ATEST1CTL0", 3, 1 },
+ { "ATEST1CTL1", 2, 1 },
+ { "ATEST1CTL2", 1, 1 },
+ { "ATEST1CTL3", 0, 1 },
+ { "MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE0", 0x460d8, 0 },
+ { "MC_DDRPHY_AD32S_OUTPUT_DRIVER_FORCE_VALUE1", 0x460dc, 0 },
+ { "MC_DDRPHY_AD32S_POWERDOWN_1", 0x460e0, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "ADR_RX_PD", 4, 1 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "DVCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_AD32S_SLEW_CAL_CNTL", 0x460e4, 0 },
+ { "SLEW_CAL_ENABLE", 15, 1 },
+ { "SLEW_CAL_START", 14, 1 },
+ { "SLEW_CAL_OVERRIDE_EN", 12, 1 },
+ { "SLEW_CAL_OVERRIDE", 8, 4 },
+ { "SLEW_TARGET_PR_OFFSET", 0, 5 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44000, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44004, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "DP18_WRAPSEL", 5, 1 },
+ { "HW_VALUE", 4, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x441f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x441f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44008, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4400c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44010, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44014, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x441f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44018, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4401c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x441cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4417c, 0 },
+ { "FAIL_PASS_VALUE", 8, 7 },
+ { "PASS_FAIL_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44178, 0 },
+ { "WRCLK_CALIB_DONE", 15, 1 },
+ { "VALUE_UPDATED", 14, 1 },
+ { "FAIL_PASS_V", 13, 1 },
+ { "PASS_FAIL_V", 12, 1 },
+ { "FP_PF_EDGE_NF", 11, 1 },
+ { "NON_SYMETRIC", 10, 1 },
+ { "FULL_RANGE", 8, 1 },
+ { "QUAD3_EDGES", 7, 1 },
+ { "QUAD2_EDGES", 6, 1 },
+ { "QUAD1_EDGES", 5, 1 },
+ { "QUAD0_EDGES", 4, 1 },
+ { "QUAD3_CAVEAT", 3, 1 },
+ { "QUAD2_CAVEAT", 2, 1 },
+ { "QUAD1_CAVEAT", 1, 1 },
+ { "QUAD0_CAVEAT", 0, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44058, 0 },
+ { "PRBS_WAIT", 14, 2 },
+ { "PRBS_SYNC_EARLY", 13, 1 },
+ { "RD_DELAY_EARLY", 12, 1 },
+ { "SS_QUAD_CAL", 10, 1 },
+ { "SS_QUAD", 8, 2 },
+ { "SS_RD_DELAY", 7, 1 },
+ { "FORCE_HI_Z", 6, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4407c, 0 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x441d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x440c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x440c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44024, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44170, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44174, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x440e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x440e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x440e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x440ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x440f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x440f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x440f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x440fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44100, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44104, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44108, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4410c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44110, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44114, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44118, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4411c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44120, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44124, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44128, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4412c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44130, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44134, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44138, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4413c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44140, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44144, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44148, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4414c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44150, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44154, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44158, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4415c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44160, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44164, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44168, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4416c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44030, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44034, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x441c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x441c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x441c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44180, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44184, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44188, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4418c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44190, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44194, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44198, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4419c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x441a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x441a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x441a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x441ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44028, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44038, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4403c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44040, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44044, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4404c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44050, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44054, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4405c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "WR_LVL_DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44060, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "WR_CNTR_DONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44064, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44068, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4406c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44070, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "DQS_REC_LOW_POWER", 11, 1 },
+ { "DQ_REC_LOW_POWER", 10, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "ADVANCE_PR_VALUE", 0, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x441d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x441dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x441e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x441e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x441e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x441ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x441d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44074, 0 },
+ { "CHECKER_ENABLE", 15, 1 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "DP18_DFT_ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44020, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x440c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x440cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x440d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44078, 0 },
+ { "SYSCLK_DQSCLK_OFFSET", 8, 7 },
+ { "SYSCLK_RDCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x440d4, 0 },
+ { "DQS_ALIGN_SM", 11, 5 },
+ { "DQS_ALIGN_CNTR", 7, 4 },
+ { "ITERATION_CNTR", 6, 1 },
+ { "DQS_ALIGN_ITER_CNTR", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x440d8, 0 },
+ { "CALIBRATE_BIT", 13, 3 },
+ { "DQS_ALIGN_QUAD", 11, 2 },
+ { "DQS_QUAD_CONFIG", 8, 3 },
+ { "OPERATE_MODE", 4, 4 },
+ { "EN_DQS_OFFSET", 3, 1 },
+ { "DQS_ALIGN_JITTER", 2, 1 },
+ { "DIS_CLK_GATE", 1, 1 },
+ { "MAX_DQS_ITER", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x441b4, 0 },
+ { "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
+ { "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x441b8, 0 },
+ { "APPROACH_ALIGNMENT", 15, 1 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x440dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4402c, 0 },
+ { "DP18_HS_PROBE_A_SEL", 11, 5 },
+ { "DP18_HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x441fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "VCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44048, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DQS_ALIGN_BY_QUAD", 4, 1 },
+ { "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x441bc, 0 },
+ { "QUAD0_PWR_CTL", 12, 4 },
+ { "QUAD1_PWR_CTL", 8, 4 },
+ { "QUAD2_PWR_CTL", 4, 4 },
+ { "QUAD3_PWR_CTL", 0, 4 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44200, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44204, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "DP18_WRAPSEL", 5, 1 },
+ { "HW_VALUE", 4, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x443f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x443f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44208, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4420c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44210, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44214, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x443f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44218, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4421c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x443cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4437c, 0 },
+ { "FAIL_PASS_VALUE", 8, 7 },
+ { "PASS_FAIL_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44378, 0 },
+ { "WRCLK_CALIB_DONE", 15, 1 },
+ { "VALUE_UPDATED", 14, 1 },
+ { "FAIL_PASS_V", 13, 1 },
+ { "PASS_FAIL_V", 12, 1 },
+ { "FP_PF_EDGE_NF", 11, 1 },
+ { "NON_SYMETRIC", 10, 1 },
+ { "FULL_RANGE", 8, 1 },
+ { "QUAD3_EDGES", 7, 1 },
+ { "QUAD2_EDGES", 6, 1 },
+ { "QUAD1_EDGES", 5, 1 },
+ { "QUAD0_EDGES", 4, 1 },
+ { "QUAD3_CAVEAT", 3, 1 },
+ { "QUAD2_CAVEAT", 2, 1 },
+ { "QUAD1_CAVEAT", 1, 1 },
+ { "QUAD0_CAVEAT", 0, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44258, 0 },
+ { "PRBS_WAIT", 14, 2 },
+ { "PRBS_SYNC_EARLY", 13, 1 },
+ { "RD_DELAY_EARLY", 12, 1 },
+ { "SS_QUAD_CAL", 10, 1 },
+ { "SS_QUAD", 8, 2 },
+ { "SS_RD_DELAY", 7, 1 },
+ { "FORCE_HI_Z", 6, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4427c, 0 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x443d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x442c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x442c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44224, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44370, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44374, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x442e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x442e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x442e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x442ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x442f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x442f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x442f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x442fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44300, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44304, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44308, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4430c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44310, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44314, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44318, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4431c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44320, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44324, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44328, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4432c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44330, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44334, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44338, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4433c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44340, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44344, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44348, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4434c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44350, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44354, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44358, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4435c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44360, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44364, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44368, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4436c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44230, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44234, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x443c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x443c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x443c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44380, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44384, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44388, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4438c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44390, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44394, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44398, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4439c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x443a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x443a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x443a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x443ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44228, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44238, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4423c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44240, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44244, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4424c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44250, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44254, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4425c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "WR_LVL_DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44260, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "WR_CNTR_DONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44264, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44268, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4426c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44270, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "DQS_REC_LOW_POWER", 11, 1 },
+ { "DQ_REC_LOW_POWER", 10, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "ADVANCE_PR_VALUE", 0, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x443d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x443dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x443e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x443e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x443e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x443ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x443d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44274, 0 },
+ { "CHECKER_ENABLE", 15, 1 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "DP18_DFT_ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44220, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x442c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x442cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x442d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44278, 0 },
+ { "SYSCLK_DQSCLK_OFFSET", 8, 7 },
+ { "SYSCLK_RDCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x442d4, 0 },
+ { "DQS_ALIGN_SM", 11, 5 },
+ { "DQS_ALIGN_CNTR", 7, 4 },
+ { "ITERATION_CNTR", 6, 1 },
+ { "DQS_ALIGN_ITER_CNTR", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x442d8, 0 },
+ { "CALIBRATE_BIT", 13, 3 },
+ { "DQS_ALIGN_QUAD", 11, 2 },
+ { "DQS_QUAD_CONFIG", 8, 3 },
+ { "OPERATE_MODE", 4, 4 },
+ { "EN_DQS_OFFSET", 3, 1 },
+ { "DQS_ALIGN_JITTER", 2, 1 },
+ { "DIS_CLK_GATE", 1, 1 },
+ { "MAX_DQS_ITER", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x443b4, 0 },
+ { "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
+ { "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x443b8, 0 },
+ { "APPROACH_ALIGNMENT", 15, 1 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x442dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4422c, 0 },
+ { "DP18_HS_PROBE_A_SEL", 11, 5 },
+ { "DP18_HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x443fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "VCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44248, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DQS_ALIGN_BY_QUAD", 4, 1 },
+ { "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x443bc, 0 },
+ { "QUAD0_PWR_CTL", 12, 4 },
+ { "QUAD1_PWR_CTL", 8, 4 },
+ { "QUAD2_PWR_CTL", 4, 4 },
+ { "QUAD3_PWR_CTL", 0, 4 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44400, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44404, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "DP18_WRAPSEL", 5, 1 },
+ { "HW_VALUE", 4, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x445f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x445f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44408, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4440c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44410, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44414, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x445f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44418, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4441c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x445cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4457c, 0 },
+ { "FAIL_PASS_VALUE", 8, 7 },
+ { "PASS_FAIL_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44578, 0 },
+ { "WRCLK_CALIB_DONE", 15, 1 },
+ { "VALUE_UPDATED", 14, 1 },
+ { "FAIL_PASS_V", 13, 1 },
+ { "PASS_FAIL_V", 12, 1 },
+ { "FP_PF_EDGE_NF", 11, 1 },
+ { "NON_SYMETRIC", 10, 1 },
+ { "FULL_RANGE", 8, 1 },
+ { "QUAD3_EDGES", 7, 1 },
+ { "QUAD2_EDGES", 6, 1 },
+ { "QUAD1_EDGES", 5, 1 },
+ { "QUAD0_EDGES", 4, 1 },
+ { "QUAD3_CAVEAT", 3, 1 },
+ { "QUAD2_CAVEAT", 2, 1 },
+ { "QUAD1_CAVEAT", 1, 1 },
+ { "QUAD0_CAVEAT", 0, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44458, 0 },
+ { "PRBS_WAIT", 14, 2 },
+ { "PRBS_SYNC_EARLY", 13, 1 },
+ { "RD_DELAY_EARLY", 12, 1 },
+ { "SS_QUAD_CAL", 10, 1 },
+ { "SS_QUAD", 8, 2 },
+ { "SS_RD_DELAY", 7, 1 },
+ { "FORCE_HI_Z", 6, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4447c, 0 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x445d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x444c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x444c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44424, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44570, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44574, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x444e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x444e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x444e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x444ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x444f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x444f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x444f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x444fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44500, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44504, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44508, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4450c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44510, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44514, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44518, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4451c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44520, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44524, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44528, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4452c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44530, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44534, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44538, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4453c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44540, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44544, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44548, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4454c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44550, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44554, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44558, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4455c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44560, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44564, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44568, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4456c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44430, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44434, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x445c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x445c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x445c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44580, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44584, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44588, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4458c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44590, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44594, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44598, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4459c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x445a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x445a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x445a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x445ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44428, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44438, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4443c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44440, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44444, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4444c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44450, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44454, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4445c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "WR_LVL_DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44460, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "WR_CNTR_DONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44464, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44468, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4446c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44470, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "DQS_REC_LOW_POWER", 11, 1 },
+ { "DQ_REC_LOW_POWER", 10, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "ADVANCE_PR_VALUE", 0, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x445d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x445dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x445e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x445e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x445e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x445ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x445d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44474, 0 },
+ { "CHECKER_ENABLE", 15, 1 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "DP18_DFT_ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44420, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x444c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x444cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x444d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44478, 0 },
+ { "SYSCLK_DQSCLK_OFFSET", 8, 7 },
+ { "SYSCLK_RDCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x444d4, 0 },
+ { "DQS_ALIGN_SM", 11, 5 },
+ { "DQS_ALIGN_CNTR", 7, 4 },
+ { "ITERATION_CNTR", 6, 1 },
+ { "DQS_ALIGN_ITER_CNTR", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x444d8, 0 },
+ { "CALIBRATE_BIT", 13, 3 },
+ { "DQS_ALIGN_QUAD", 11, 2 },
+ { "DQS_QUAD_CONFIG", 8, 3 },
+ { "OPERATE_MODE", 4, 4 },
+ { "EN_DQS_OFFSET", 3, 1 },
+ { "DQS_ALIGN_JITTER", 2, 1 },
+ { "DIS_CLK_GATE", 1, 1 },
+ { "MAX_DQS_ITER", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x445b4, 0 },
+ { "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
+ { "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x445b8, 0 },
+ { "APPROACH_ALIGNMENT", 15, 1 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x444dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4442c, 0 },
+ { "DP18_HS_PROBE_A_SEL", 11, 5 },
+ { "DP18_HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x445fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "VCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44448, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DQS_ALIGN_BY_QUAD", 4, 1 },
+ { "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x445bc, 0 },
+ { "QUAD0_PWR_CTL", 12, 4 },
+ { "QUAD1_PWR_CTL", 8, 4 },
+ { "QUAD2_PWR_CTL", 4, 4 },
+ { "QUAD3_PWR_CTL", 0, 4 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44600, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44604, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "DP18_WRAPSEL", 5, 1 },
+ { "HW_VALUE", 4, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x447f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x447f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44608, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4460c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44610, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44614, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x447f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44618, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4461c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x447cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4477c, 0 },
+ { "FAIL_PASS_VALUE", 8, 7 },
+ { "PASS_FAIL_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44778, 0 },
+ { "WRCLK_CALIB_DONE", 15, 1 },
+ { "VALUE_UPDATED", 14, 1 },
+ { "FAIL_PASS_V", 13, 1 },
+ { "PASS_FAIL_V", 12, 1 },
+ { "FP_PF_EDGE_NF", 11, 1 },
+ { "NON_SYMETRIC", 10, 1 },
+ { "FULL_RANGE", 8, 1 },
+ { "QUAD3_EDGES", 7, 1 },
+ { "QUAD2_EDGES", 6, 1 },
+ { "QUAD1_EDGES", 5, 1 },
+ { "QUAD0_EDGES", 4, 1 },
+ { "QUAD3_CAVEAT", 3, 1 },
+ { "QUAD2_CAVEAT", 2, 1 },
+ { "QUAD1_CAVEAT", 1, 1 },
+ { "QUAD0_CAVEAT", 0, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44658, 0 },
+ { "PRBS_WAIT", 14, 2 },
+ { "PRBS_SYNC_EARLY", 13, 1 },
+ { "RD_DELAY_EARLY", 12, 1 },
+ { "SS_QUAD_CAL", 10, 1 },
+ { "SS_QUAD", 8, 2 },
+ { "SS_RD_DELAY", 7, 1 },
+ { "FORCE_HI_Z", 6, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4467c, 0 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x447d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x446c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x446c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44624, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44770, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44774, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x446e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x446e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x446e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x446ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x446f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x446f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x446f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x446fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44700, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44704, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44708, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4470c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44710, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44714, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44718, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4471c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44720, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44724, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44728, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4472c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44730, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44734, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44738, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4473c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44740, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44744, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44748, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4474c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44750, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44754, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44758, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4475c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44760, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44764, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44768, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4476c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44630, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44634, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x447c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x447c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x447c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44780, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44784, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44788, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4478c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44790, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44794, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44798, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4479c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x447a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x447a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x447a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x447ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44628, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44638, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4463c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44640, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44644, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4464c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44650, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44654, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4465c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "WR_LVL_DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44660, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "WR_CNTR_DONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44664, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44668, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4466c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44670, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "DQS_REC_LOW_POWER", 11, 1 },
+ { "DQ_REC_LOW_POWER", 10, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "ADVANCE_PR_VALUE", 0, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x447d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x447dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x447e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x447e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x447e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x447ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x447d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44674, 0 },
+ { "CHECKER_ENABLE", 15, 1 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "DP18_DFT_ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44620, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x446c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x446cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x446d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44678, 0 },
+ { "SYSCLK_DQSCLK_OFFSET", 8, 7 },
+ { "SYSCLK_RDCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x446d4, 0 },
+ { "DQS_ALIGN_SM", 11, 5 },
+ { "DQS_ALIGN_CNTR", 7, 4 },
+ { "ITERATION_CNTR", 6, 1 },
+ { "DQS_ALIGN_ITER_CNTR", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x446d8, 0 },
+ { "CALIBRATE_BIT", 13, 3 },
+ { "DQS_ALIGN_QUAD", 11, 2 },
+ { "DQS_QUAD_CONFIG", 8, 3 },
+ { "OPERATE_MODE", 4, 4 },
+ { "EN_DQS_OFFSET", 3, 1 },
+ { "DQS_ALIGN_JITTER", 2, 1 },
+ { "DIS_CLK_GATE", 1, 1 },
+ { "MAX_DQS_ITER", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x447b4, 0 },
+ { "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
+ { "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x447b8, 0 },
+ { "APPROACH_ALIGNMENT", 15, 1 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x446dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4462c, 0 },
+ { "DP18_HS_PROBE_A_SEL", 11, 5 },
+ { "DP18_HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x447fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "VCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44648, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DQS_ALIGN_BY_QUAD", 4, 1 },
+ { "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x447bc, 0 },
+ { "QUAD0_PWR_CTL", 12, 4 },
+ { "QUAD1_PWR_CTL", 8, 4 },
+ { "QUAD2_PWR_CTL", 4, 4 },
+ { "QUAD3_PWR_CTL", 0, 4 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44800, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44804, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "DP18_WRAPSEL", 5, 1 },
+ { "HW_VALUE", 4, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x449f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x449f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44808, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4480c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44810, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44814, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x449f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44818, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4481c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x449cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4497c, 0 },
+ { "FAIL_PASS_VALUE", 8, 7 },
+ { "PASS_FAIL_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44978, 0 },
+ { "WRCLK_CALIB_DONE", 15, 1 },
+ { "VALUE_UPDATED", 14, 1 },
+ { "FAIL_PASS_V", 13, 1 },
+ { "PASS_FAIL_V", 12, 1 },
+ { "FP_PF_EDGE_NF", 11, 1 },
+ { "NON_SYMETRIC", 10, 1 },
+ { "FULL_RANGE", 8, 1 },
+ { "QUAD3_EDGES", 7, 1 },
+ { "QUAD2_EDGES", 6, 1 },
+ { "QUAD1_EDGES", 5, 1 },
+ { "QUAD0_EDGES", 4, 1 },
+ { "QUAD3_CAVEAT", 3, 1 },
+ { "QUAD2_CAVEAT", 2, 1 },
+ { "QUAD1_CAVEAT", 1, 1 },
+ { "QUAD0_CAVEAT", 0, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44858, 0 },
+ { "PRBS_WAIT", 14, 2 },
+ { "PRBS_SYNC_EARLY", 13, 1 },
+ { "RD_DELAY_EARLY", 12, 1 },
+ { "SS_QUAD_CAL", 10, 1 },
+ { "SS_QUAD", 8, 2 },
+ { "SS_RD_DELAY", 7, 1 },
+ { "FORCE_HI_Z", 6, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4487c, 0 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x449d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x448c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x448c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44824, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44970, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44974, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x448e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x448e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x448e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x448ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x448f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x448f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x448f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x448fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44900, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44904, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44908, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4490c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44910, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44914, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44918, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4491c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44920, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44924, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44928, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4492c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44930, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44934, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44938, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4493c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44940, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44944, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44948, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4494c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44950, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44954, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44958, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4495c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44960, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44964, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44968, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4496c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44830, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44834, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x449c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x449c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x449c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44980, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44984, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44988, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4498c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44990, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44994, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44998, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4499c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x449a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x449a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x449a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x449ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44828, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44838, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4483c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44840, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44844, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4484c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44850, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44854, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4485c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "WR_LVL_DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44860, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "WR_CNTR_DONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44864, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44868, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4486c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44870, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "DQS_REC_LOW_POWER", 11, 1 },
+ { "DQ_REC_LOW_POWER", 10, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "ADVANCE_PR_VALUE", 0, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x449d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x449dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x449e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x449e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x449e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x449ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x449d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44874, 0 },
+ { "CHECKER_ENABLE", 15, 1 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "DP18_DFT_ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44820, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x448c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x448cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x448d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44878, 0 },
+ { "SYSCLK_DQSCLK_OFFSET", 8, 7 },
+ { "SYSCLK_RDCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x448d4, 0 },
+ { "DQS_ALIGN_SM", 11, 5 },
+ { "DQS_ALIGN_CNTR", 7, 4 },
+ { "ITERATION_CNTR", 6, 1 },
+ { "DQS_ALIGN_ITER_CNTR", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x448d8, 0 },
+ { "CALIBRATE_BIT", 13, 3 },
+ { "DQS_ALIGN_QUAD", 11, 2 },
+ { "DQS_QUAD_CONFIG", 8, 3 },
+ { "OPERATE_MODE", 4, 4 },
+ { "EN_DQS_OFFSET", 3, 1 },
+ { "DQS_ALIGN_JITTER", 2, 1 },
+ { "DIS_CLK_GATE", 1, 1 },
+ { "MAX_DQS_ITER", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x449b4, 0 },
+ { "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
+ { "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x449b8, 0 },
+ { "APPROACH_ALIGNMENT", 15, 1 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x448dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4482c, 0 },
+ { "DP18_HS_PROBE_A_SEL", 11, 5 },
+ { "DP18_HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x449fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "VCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44848, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DQS_ALIGN_BY_QUAD", 4, 1 },
+ { "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x449bc, 0 },
+ { "QUAD0_PWR_CTL", 12, 4 },
+ { "QUAD1_PWR_CTL", 8, 4 },
+ { "QUAD2_PWR_CTL", 4, 4 },
+ { "QUAD3_PWR_CTL", 0, 4 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44a00, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44a04, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "DP18_WRAPSEL", 5, 1 },
+ { "HW_VALUE", 4, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x44bf0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x44bf4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44a08, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x44a0c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44a10, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44a14, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x44bf8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44a18, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x44a1c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x44bcc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EDGE", 0x44b7c, 0 },
+ { "FAIL_PASS_VALUE", 8, 7 },
+ { "PASS_FAIL_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44b78, 0 },
+ { "WRCLK_CALIB_DONE", 15, 1 },
+ { "VALUE_UPDATED", 14, 1 },
+ { "FAIL_PASS_V", 13, 1 },
+ { "PASS_FAIL_V", 12, 1 },
+ { "FP_PF_EDGE_NF", 11, 1 },
+ { "NON_SYMETRIC", 10, 1 },
+ { "FULL_RANGE", 8, 1 },
+ { "QUAD3_EDGES", 7, 1 },
+ { "QUAD2_EDGES", 6, 1 },
+ { "QUAD1_EDGES", 5, 1 },
+ { "QUAD0_EDGES", 4, 1 },
+ { "QUAD3_CAVEAT", 3, 1 },
+ { "QUAD2_CAVEAT", 2, 1 },
+ { "QUAD1_CAVEAT", 1, 1 },
+ { "QUAD0_CAVEAT", 0, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44a58, 0 },
+ { "PRBS_WAIT", 14, 2 },
+ { "PRBS_SYNC_EARLY", 13, 1 },
+ { "RD_DELAY_EARLY", 12, 1 },
+ { "SS_QUAD_CAL", 10, 1 },
+ { "SS_QUAD", 8, 2 },
+ { "SS_RD_DELAY", 7, 1 },
+ { "FORCE_HI_Z", 6, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x44a7c, 0 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x44bd0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x44ac0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x44ac4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44a24, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44b70, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44b74, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x44ae0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x44ae4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x44ae8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x44aec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x44af0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x44af4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x44af8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x44afc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44b00, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44b04, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44b08, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x44b0c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44b10, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44b14, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44b18, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x44b1c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44b20, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44b24, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44b28, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x44b2c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44b30, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44b34, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44b38, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x44b3c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44b40, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44b44, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44b48, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x44b4c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44b50, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44b54, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44b58, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x44b5c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44b60, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44b64, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44b68, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x44b6c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44a30, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44a34, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x44bc0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x44bc4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x44bc8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44b80, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44b84, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44b88, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x44b8c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44b90, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44b94, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44b98, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x44b9c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x44ba0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x44ba4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x44ba8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x44bac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44a28, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44a38, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x44a3c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44a40, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44a44, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x44a4c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44a50, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44a54, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x44a5c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "WR_LVL_DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44a60, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "WR_CNTR_DONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44a64, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44a68, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x44a6c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44a70, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "DQS_REC_LOW_POWER", 11, 1 },
+ { "DQ_REC_LOW_POWER", 10, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "ADVANCE_PR_VALUE", 0, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x44bd8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x44bdc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x44be0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x44be8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x44be4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x44bec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x44bd4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44a74, 0 },
+ { "CHECKER_ENABLE", 15, 1 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "DP18_DFT_ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44a20, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x44ac8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x44acc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x44ad0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44a78, 0 },
+ { "SYSCLK_DQSCLK_OFFSET", 8, 7 },
+ { "SYSCLK_RDCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x44ad4, 0 },
+ { "DQS_ALIGN_SM", 11, 5 },
+ { "DQS_ALIGN_CNTR", 7, 4 },
+ { "ITERATION_CNTR", 6, 1 },
+ { "DQS_ALIGN_ITER_CNTR", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x44ad8, 0 },
+ { "CALIBRATE_BIT", 13, 3 },
+ { "DQS_ALIGN_QUAD", 11, 2 },
+ { "DQS_QUAD_CONFIG", 8, 3 },
+ { "OPERATE_MODE", 4, 4 },
+ { "EN_DQS_OFFSET", 3, 1 },
+ { "DQS_ALIGN_JITTER", 2, 1 },
+ { "DIS_CLK_GATE", 1, 1 },
+ { "MAX_DQS_ITER", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x44bb4, 0 },
+ { "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
+ { "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x44bb8, 0 },
+ { "APPROACH_ALIGNMENT", 15, 1 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x44adc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x44a2c, 0 },
+ { "DP18_HS_PROBE_A_SEL", 11, 5 },
+ { "DP18_HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x44bfc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "VCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44a48, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DQS_ALIGN_BY_QUAD", 4, 1 },
+ { "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x44bbc, 0 },
+ { "QUAD0_PWR_CTL", 12, 4 },
+ { "QUAD1_PWR_CTL", 8, 4 },
+ { "QUAD2_PWR_CTL", 4, 4 },
+ { "QUAD3_PWR_CTL", 0, 4 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44c00, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44c04, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "DP18_WRAPSEL", 5, 1 },
+ { "HW_VALUE", 4, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x44df0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x44df4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44c08, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x44c0c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44c10, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44c14, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x44df8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44c18, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x44c1c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x44dcc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EDGE", 0x44d7c, 0 },
+ { "FAIL_PASS_VALUE", 8, 7 },
+ { "PASS_FAIL_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44d78, 0 },
+ { "WRCLK_CALIB_DONE", 15, 1 },
+ { "VALUE_UPDATED", 14, 1 },
+ { "FAIL_PASS_V", 13, 1 },
+ { "PASS_FAIL_V", 12, 1 },
+ { "FP_PF_EDGE_NF", 11, 1 },
+ { "NON_SYMETRIC", 10, 1 },
+ { "FULL_RANGE", 8, 1 },
+ { "QUAD3_EDGES", 7, 1 },
+ { "QUAD2_EDGES", 6, 1 },
+ { "QUAD1_EDGES", 5, 1 },
+ { "QUAD0_EDGES", 4, 1 },
+ { "QUAD3_CAVEAT", 3, 1 },
+ { "QUAD2_CAVEAT", 2, 1 },
+ { "QUAD1_CAVEAT", 1, 1 },
+ { "QUAD0_CAVEAT", 0, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44c58, 0 },
+ { "PRBS_WAIT", 14, 2 },
+ { "PRBS_SYNC_EARLY", 13, 1 },
+ { "RD_DELAY_EARLY", 12, 1 },
+ { "SS_QUAD_CAL", 10, 1 },
+ { "SS_QUAD", 8, 2 },
+ { "SS_RD_DELAY", 7, 1 },
+ { "FORCE_HI_Z", 6, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x44c7c, 0 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x44dd0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x44cc0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x44cc4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44c24, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44d70, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44d74, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x44ce0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x44ce4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x44ce8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x44cec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x44cf0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x44cf4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x44cf8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x44cfc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44d00, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44d04, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44d08, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x44d0c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44d10, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44d14, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44d18, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x44d1c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44d20, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44d24, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44d28, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x44d2c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44d30, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44d34, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44d38, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x44d3c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44d40, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44d44, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44d48, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x44d4c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44d50, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44d54, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44d58, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x44d5c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44d60, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44d64, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44d68, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x44d6c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44c30, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44c34, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x44dc0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x44dc4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x44dc8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44d80, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44d84, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44d88, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x44d8c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44d90, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44d94, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44d98, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x44d9c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x44da0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x44da4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x44da8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x44dac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44c28, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44c38, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x44c3c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44c40, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44c44, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x44c4c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44c50, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44c54, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x44c5c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "WR_LVL_DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44c60, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "WR_CNTR_DONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44c64, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44c68, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x44c6c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44c70, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "DQS_REC_LOW_POWER", 11, 1 },
+ { "DQ_REC_LOW_POWER", 10, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "ADVANCE_PR_VALUE", 0, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x44dd8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x44ddc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x44de0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x44de8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x44de4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x44dec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x44dd4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44c74, 0 },
+ { "CHECKER_ENABLE", 15, 1 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "DP18_DFT_ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44c20, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x44cc8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x44ccc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x44cd0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44c78, 0 },
+ { "SYSCLK_DQSCLK_OFFSET", 8, 7 },
+ { "SYSCLK_RDCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x44cd4, 0 },
+ { "DQS_ALIGN_SM", 11, 5 },
+ { "DQS_ALIGN_CNTR", 7, 4 },
+ { "ITERATION_CNTR", 6, 1 },
+ { "DQS_ALIGN_ITER_CNTR", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x44cd8, 0 },
+ { "CALIBRATE_BIT", 13, 3 },
+ { "DQS_ALIGN_QUAD", 11, 2 },
+ { "DQS_QUAD_CONFIG", 8, 3 },
+ { "OPERATE_MODE", 4, 4 },
+ { "EN_DQS_OFFSET", 3, 1 },
+ { "DQS_ALIGN_JITTER", 2, 1 },
+ { "DIS_CLK_GATE", 1, 1 },
+ { "MAX_DQS_ITER", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x44db4, 0 },
+ { "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
+ { "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x44db8, 0 },
+ { "APPROACH_ALIGNMENT", 15, 1 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x44cdc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x44c2c, 0 },
+ { "DP18_HS_PROBE_A_SEL", 11, 5 },
+ { "DP18_HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x44dfc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "VCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44c48, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DQS_ALIGN_BY_QUAD", 4, 1 },
+ { "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x44dbc, 0 },
+ { "QUAD0_PWR_CTL", 12, 4 },
+ { "QUAD1_PWR_CTL", 8, 4 },
+ { "QUAD2_PWR_CTL", 4, 4 },
+ { "QUAD3_PWR_CTL", 0, 4 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44e00, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44e04, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "DP18_WRAPSEL", 5, 1 },
+ { "HW_VALUE", 4, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x44ff0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x44ff4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44e08, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x44e0c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44e10, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44e14, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x44ff8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44e18, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x44e1c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x44fcc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EDGE", 0x44f7c, 0 },
+ { "FAIL_PASS_VALUE", 8, 7 },
+ { "PASS_FAIL_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_WRCLK_STATUS", 0x44f78, 0 },
+ { "WRCLK_CALIB_DONE", 15, 1 },
+ { "VALUE_UPDATED", 14, 1 },
+ { "FAIL_PASS_V", 13, 1 },
+ { "PASS_FAIL_V", 12, 1 },
+ { "FP_PF_EDGE_NF", 11, 1 },
+ { "NON_SYMETRIC", 10, 1 },
+ { "FULL_RANGE", 8, 1 },
+ { "QUAD3_EDGES", 7, 1 },
+ { "QUAD2_EDGES", 6, 1 },
+ { "QUAD1_EDGES", 5, 1 },
+ { "QUAD0_EDGES", 4, 1 },
+ { "QUAD3_CAVEAT", 3, 1 },
+ { "QUAD2_CAVEAT", 2, 1 },
+ { "QUAD1_CAVEAT", 1, 1 },
+ { "QUAD0_CAVEAT", 0, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_CNTL", 0x44e58, 0 },
+ { "PRBS_WAIT", 14, 2 },
+ { "PRBS_SYNC_EARLY", 13, 1 },
+ { "RD_DELAY_EARLY", 12, 1 },
+ { "SS_QUAD_CAL", 10, 1 },
+ { "SS_QUAD", 8, 2 },
+ { "SS_RD_DELAY", 7, 1 },
+ { "FORCE_HI_Z", 6, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x44e7c, 0 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x44fd0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x44ec0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x44ec4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44e24, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44f70, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44f74, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x44ee0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x44ee4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x44ee8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x44eec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x44ef0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x44ef4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x44ef8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x44efc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44f00, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44f04, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44f08, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x44f0c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44f10, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44f14, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44f18, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x44f1c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44f20, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44f24, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44f28, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x44f2c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44f30, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44f34, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44f38, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x44f3c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44f40, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44f44, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44f48, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x44f4c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44f50, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44f54, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44f58, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x44f5c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44f60, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44f64, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44f68, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x44f6c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44e30, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44e34, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x44fc0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x44fc4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x44fc8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44f80, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44f84, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44f88, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x44f8c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44f90, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44f94, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44f98, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x44f9c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x44fa0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x44fa4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x44fa8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x44fac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44e28, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44e38, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x44e3c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44e40, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44e44, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x44e4c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x44e50, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44e54, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x44e5c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "WR_LVL_DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44e60, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "WR_CNTR_DONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44e64, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44e68, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x44e6c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44e70, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "DQS_REC_LOW_POWER", 11, 1 },
+ { "DQ_REC_LOW_POWER", 10, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "ADVANCE_PR_VALUE", 0, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x44fd8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x44fdc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x44fe0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x44fe8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x44fe4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x44fec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x44fd4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44e74, 0 },
+ { "CHECKER_ENABLE", 15, 1 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "DP18_DFT_ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44e20, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x44ec8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x44ecc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x44ed0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44e78, 0 },
+ { "SYSCLK_DQSCLK_OFFSET", 8, 7 },
+ { "SYSCLK_RDCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x44ed4, 0 },
+ { "DQS_ALIGN_SM", 11, 5 },
+ { "DQS_ALIGN_CNTR", 7, 4 },
+ { "ITERATION_CNTR", 6, 1 },
+ { "DQS_ALIGN_ITER_CNTR", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x44ed8, 0 },
+ { "CALIBRATE_BIT", 13, 3 },
+ { "DQS_ALIGN_QUAD", 11, 2 },
+ { "DQS_QUAD_CONFIG", 8, 3 },
+ { "OPERATE_MODE", 4, 4 },
+ { "EN_DQS_OFFSET", 3, 1 },
+ { "DQS_ALIGN_JITTER", 2, 1 },
+ { "DIS_CLK_GATE", 1, 1 },
+ { "MAX_DQS_ITER", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x44fb4, 0 },
+ { "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
+ { "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x44fb8, 0 },
+ { "APPROACH_ALIGNMENT", 15, 1 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x44edc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x44e2c, 0 },
+ { "DP18_HS_PROBE_A_SEL", 11, 5 },
+ { "DP18_HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x44ffc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "VCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44e48, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DQS_ALIGN_BY_QUAD", 4, 1 },
+ { "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x44fbc, 0 },
+ { "QUAD0_PWR_CTL", 12, 4 },
+ { "QUAD1_PWR_CTL", 8, 4 },
+ { "QUAD2_PWR_CTL", 4, 4 },
+ { "QUAD3_PWR_CTL", 0, 4 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x45000, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x45004, 0 },
+ { "DATA_BIT_ENABLE_16_23", 8, 8 },
+ { "DFT_FORCE_OUTPUTS", 7, 1 },
+ { "DFT_PRBS7_GEN_EN", 6, 1 },
+ { "DP18_WRAPSEL", 5, 1 },
+ { "HW_VALUE", 4, 1 },
+ { "MRS_CMD_DATA_N0", 3, 1 },
+ { "MRS_CMD_DATA_N1", 2, 1 },
+ { "MRS_CMD_DATA_N2", 1, 1 },
+ { "MRS_CMD_DATA_N3", 0, 1 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x451f0, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x451f4, 0 },
+ { "DATA_BIT_DISABLE_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x45008, 0 },
+ { "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4500c, 0 },
+ { "DATA_BIT_DIR_16_23", 8, 8 },
+ { "WL_ADVANCE_DISABLE", 7, 1 },
+ { "DISABLE_PING_PONG", 6, 1 },
+ { "DELAY_PING_PONG_HALF", 5, 1 },
+ { "ADVANCE_PING_PONG", 4, 1 },
+ { "ATEST_MUX_CTL0", 3, 1 },
+ { "ATEST_MUX_CTL1", 2, 1 },
+ { "ATEST_MUX_CTL2", 1, 1 },
+ { "ATEST_MUX_CTL3", 0, 1 },
+ { "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x45010, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x45014, 0 },
+ { "QUAD0_CLK16_BIT0", 15, 1 },
+ { "QUAD1_CLK16_BIT1", 14, 1 },
+ { "QUAD2_CLK16_BIT2", 13, 1 },
+ { "QUAD3_CLK16_BIT3", 12, 1 },
+ { "QUAD0_CLK18_BIT4", 11, 1 },
+ { "QUAD1_CLK18_BIT5", 10, 1 },
+ { "QUAD2_CLK20_BIT6", 9, 1 },
+ { "QUAD3_CLK20_BIT7", 8, 1 },
+ { "QUAD2_CLK22_BIT8", 7, 1 },
+ { "QUAD3_CLK22_BIT9", 6, 1 },
+ { "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
+ { "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
+ { "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
+ { "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
+ { "QUAD2_CLK18_BIT14", 1, 1 },
+ { "QUAD3_CLK18_BIT15", 0, 1 },
+ { "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x451f8, 0 },
+ { "DQ_WR_OFFSET_N0", 12, 4 },
+ { "DQ_WR_OFFSET_N1", 8, 4 },
+ { "DQ_WR_OFFSET_N2", 4, 4 },
+ { "DQ_WR_OFFSET_N3", 0, 4 },
+ { "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x45018, 0 },
+ { "PEAK_AMP_CTL_SIDE0", 13, 3 },
+ { "PEAK_AMP_CTL_SIDE1", 9, 3 },
+ { "SxMCVREF_0_3", 4, 4 },
+ { "SxPODVREF", 3, 1 },
+ { "DISABLE_TERMINATION", 2, 1 },
+ { "READ_CENTERING_MODE", 0, 2 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR", 0x4501c, 0 },
+ { "SYSCLK_ENABLE", 15, 1 },
+ { "SYSCLK_ROT_OVERRIDE", 8, 7 },
+ { "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
+ { "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
+ { "SYSCLK_PHASE_CNTL_EN", 5, 1 },
+ { "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
+ { "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
+ { "CONTINUOUS_UPDATE", 2, 1 },
+ { "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x451cc, 0 },
+ { "SYSCLK_ROT", 8, 7 },
+ { "BB_LOCK", 7, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_EDGE", 0x4517c, 0 },
+ { "FAIL_PASS_VALUE", 8, 7 },
+ { "PASS_FAIL_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_WRCLK_STATUS", 0x45178, 0 },
+ { "WRCLK_CALIB_DONE", 15, 1 },
+ { "VALUE_UPDATED", 14, 1 },
+ { "FAIL_PASS_V", 13, 1 },
+ { "PASS_FAIL_V", 12, 1 },
+ { "FP_PF_EDGE_NF", 11, 1 },
+ { "NON_SYMETRIC", 10, 1 },
+ { "FULL_RANGE", 8, 1 },
+ { "QUAD3_EDGES", 7, 1 },
+ { "QUAD2_EDGES", 6, 1 },
+ { "QUAD1_EDGES", 5, 1 },
+ { "QUAD0_EDGES", 4, 1 },
+ { "QUAD3_CAVEAT", 3, 1 },
+ { "QUAD2_CAVEAT", 2, 1 },
+ { "QUAD1_CAVEAT", 1, 1 },
+ { "QUAD0_CAVEAT", 0, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_CNTL", 0x45058, 0 },
+ { "PRBS_WAIT", 14, 2 },
+ { "PRBS_SYNC_EARLY", 13, 1 },
+ { "RD_DELAY_EARLY", 12, 1 },
+ { "SS_QUAD_CAL", 10, 1 },
+ { "SS_QUAD", 8, 2 },
+ { "SS_RD_DELAY", 7, 1 },
+ { "FORCE_HI_Z", 6, 1 },
+ { "MC_DDRPHY_DP18_WRCLK_AUX_CNTL", 0x4507c, 0 },
+ { "MC_DDRPHY_DP18_WRCLK_PR", 0x451d0, 0 },
+ { "TSYS_WRCLK", 8, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x450c0, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x450c4, 0 },
+ { "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
+ { "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x45024, 0 },
+ { "DQSCLK_SELECT0", 14, 2 },
+ { "RDCLK_SELECT0", 12, 2 },
+ { "DQSCLK_SELECT1", 10, 2 },
+ { "RDCLK_SELECT1", 8, 2 },
+ { "DQSCLK_SELECT2", 6, 2 },
+ { "RDCLK_SELECT2", 4, 2 },
+ { "DQSCLK_SELECT3", 2, 2 },
+ { "RDCLK_SELECT3", 0, 2 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x45170, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x45174, 0 },
+ { "INITIAL_DQS_ROT_N0_N2", 8, 7 },
+ { "INITIAL_DQS_ROT_N1_N3", 0, 7 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x450e0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x450e4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x450e8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x450ec, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x450f0, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x450f4, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x450f8, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x450fc, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x45100, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x45104, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x45108, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4510c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x45110, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x45114, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x45118, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4511c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x45120, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x45124, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x45128, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4512c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x45130, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x45134, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x45138, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4513c, 0 },
+ { "WR_DELAY", 6, 10 },
+ { "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x45140, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x45144, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x45148, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4514c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x45150, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x45154, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x45158, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4515c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x45160, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x45164, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x45168, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4516c, 0 },
+ { "RD_DELAY_BITS0_6", 9, 7 },
+ { "RD_DELAY_BITS8_14", 1, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x45030, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x45034, 0 },
+ { "OFFSET_BITS1_7", 8, 7 },
+ { "OFFSET_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x451c0, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x451c4, 0 },
+ { "REFERENCE_BITS1_7", 8, 7 },
+ { "REFERENCE_BITS9_15", 0, 7 },
+ { "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x451c8, 0 },
+ { "REFERENCE", 8, 7 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x45180, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x45184, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x45188, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4518c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x45190, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x45194, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x45198, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4519c, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x451a0, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x451a4, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x451a8, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x451ac, 0 },
+ { "RD_EYE_SIZE_BITS2_7", 8, 6 },
+ { "RD_EYE_SIZE_BITS10_15", 0, 6 },
+ { "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x45028, 0 },
+ { "MIN_RD_EYE_SIZE", 8, 6 },
+ { "MAX_DQS_DRIFT", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x45038, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4503c, 0 },
+ { "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x45040, 0 },
+ { "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x45044, 0 },
+ { "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
+ { "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4504c, 0 },
+ { "DQS_GATE_DELAY_N0", 12, 3 },
+ { "DQS_GATE_DELAY_N1", 8, 3 },
+ { "DQS_GATE_DELAY_N2", 4, 3 },
+ { "DQS_GATE_DELAY_N3", 0, 3 },
+ { "MC_DDRPHY_DP18_RD_STATUS0", 0x45050, 0 },
+ { "NO_EYE_DETECTED", 15, 1 },
+ { "LEADING_EDGE_FOUND", 14, 1 },
+ { "TRAILING_EDGE_FOUND", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3", 5, 1 },
+ { "EYE_CLIPPING", 4, 1 },
+ { "NO_DQS", 3, 1 },
+ { "NO_LOCK", 2, 1 },
+ { "DRIFT_ERROR", 1, 1 },
+ { "MIN_EYE", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x45054, 0 },
+ { "NO_EYE_DETECTED_MASK", 15, 1 },
+ { "LEADING_EDGE_FOUND_MASK", 14, 1 },
+ { "TRAILING_EDGE_FOUND_MASK", 13, 1 },
+ { "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
+ { "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
+ { "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
+ { "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
+ { "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
+ { "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
+ { "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
+ { "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
+ { "EYE_CLIPPING_MASK", 4, 1 },
+ { "NO_DQS_MASK", 3, 1 },
+ { "NO_LOCK_MASK", 2, 1 },
+ { "DRIFT_ERROR_MASK", 1, 1 },
+ { "MIN_EYE_MASK", 0, 1 },
+ { "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4505c, 0 },
+ { "CLK_LEVEL", 14, 2 },
+ { "FINE_STEPPING", 13, 1 },
+ { "WR_LVL_DONE", 12, 1 },
+ { "WL_ERR_CLK16_ST", 11, 1 },
+ { "WL_ERR_CLK18_ST", 10, 1 },
+ { "WL_ERR_CLK20_ST", 9, 1 },
+ { "WL_ERR_CLK22_ST", 8, 1 },
+ { "ZERO_DETECTED", 7, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x45060, 0 },
+ { "BIT_CENTERED", 11, 5 },
+ { "SMALL_STEP_LEFT", 10, 1 },
+ { "BIG_STEP_RIGHT", 9, 1 },
+ { "MATCH_STEP_RIGHT", 8, 1 },
+ { "JUMP_BACK_RIGHT", 7, 1 },
+ { "SMALL_STEP_RIGHT", 6, 1 },
+ { "WR_CNTR_DONE", 5, 1 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x45064, 0 },
+ { "FW_LEFT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x45068, 0 },
+ { "FW_RIGHT_SIDE", 5, 11 },
+ { "MC_DDRPHY_DP18_WR_ERROR0", 0x4506c, 0 },
+ { "WL_ERR_CLK16", 15, 1 },
+ { "WL_ERR_CLK18", 14, 1 },
+ { "WL_ERR_CLK20", 13, 1 },
+ { "WL_ERR_CLK22", 12, 1 },
+ { "VALID_NS_BIG_L", 7, 1 },
+ { "INVALID_NS_SMALL_L", 6, 1 },
+ { "VALID_NS_BIG_R", 5, 1 },
+ { "INVALID_NS_BIG_R", 4, 1 },
+ { "VALID_NS_JUMP_BACK", 3, 1 },
+ { "INVALID_NS_SMALL_R", 2, 1 },
+ { "OFFSET_ERR", 1, 1 },
+ { "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x45070, 0 },
+ { "WL_ERR_CLK16_MASK", 15, 1 },
+ { "WL_ERR_CLK18_MASK", 14, 1 },
+ { "WL_ERR_CLK20_MASK", 13, 1 },
+ { "WR_ERR_CLK22_MASK", 12, 1 },
+ { "DQS_REC_LOW_POWER", 11, 1 },
+ { "DQ_REC_LOW_POWER", 10, 1 },
+ { "VALID_NS_BIG_L_MASK", 7, 1 },
+ { "INVALID_NS_SMALL_L_MASK", 6, 1 },
+ { "VALID_NS_BIG_R_MASK", 5, 1 },
+ { "INVALID_NS_BIG_R_MASK", 4, 1 },
+ { "VALID_NS_JUMP_BACK_MASK", 3, 1 },
+ { "INVALID_NS_SMALL_R_MASK", 2, 1 },
+ { "OFFSET_ERR_MASK", 1, 1 },
+ { "ADVANCE_PR_VALUE", 0, 1 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG0", 0x451d8, 0 },
+ { "PLL_TUNE_0_2", 13, 3 },
+ { "PLL_TUNECP_0_2", 10, 3 },
+ { "PLL_TUNEF_0_5", 4, 6 },
+ { "PLL_TUNEVCO_0_1", 2, 2 },
+ { "PLL_PLLXTR_0_1", 0, 2 },
+ { "MC_DDRPHY_DP18_PLL_CONFIG1", 0x451dc, 0 },
+ { "PLL_TUNETDIV_0_2", 13, 3 },
+ { "PLL_TUNEMDIV_0_1", 11, 2 },
+ { "PLL_TUNEATST", 10, 1 },
+ { "VREG_RANGE_0_1", 8, 2 },
+ { "CE0DLTVCCA", 7, 1 },
+ { "VREG_VCCTUNE_0_1", 5, 2 },
+ { "CE0DLTVCCD1", 4, 1 },
+ { "CE0DLTVCCD2", 3, 1 },
+ { "S0INSDLYTAP", 2, 1 },
+ { "S1INSDLYTAP", 1, 1 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x451e0, 0 },
+ { "EN_SLICE_N_WR", 8, 8 },
+ { "EN_SLICE_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x451e8, 0 },
+ { "EN_TERM_N_WR", 8, 8 },
+ { "EN_TERM_N_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x451e4, 0 },
+ { "EN_SLICE_P_WR", 8, 8 },
+ { "EN_SLICE_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x451ec, 0 },
+ { "EN_TERM_P_WR", 8, 8 },
+ { "EN_TERM_P_WR_FFE", 4, 4 },
+ { "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x451d4, 0 },
+ { "INTERP_SIG_SLEW", 12, 4 },
+ { "POST_CURSOR", 8, 4 },
+ { "SLEW_CTL", 4, 4 },
+ { "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x45074, 0 },
+ { "CHECKER_ENABLE", 15, 1 },
+ { "CHECKER_RESET", 14, 1 },
+ { "SYNC", 6, 6 },
+ { "DP18_DFT_ERROR", 0, 6 },
+ { "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x45020, 0 },
+ { "DIGITAL_EYE_EN", 15, 1 },
+ { "BUMP", 14, 1 },
+ { "TRIG_PERIOD", 13, 1 },
+ { "CNTL_POL", 12, 1 },
+ { "CNTL_SRC", 8, 1 },
+ { "DIGITAL_EYE_VALUE", 0, 8 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_0", 0x450c8, 0 },
+ { "MEMINTD00_POS", 14, 2 },
+ { "MEMINTD01_PO", 12, 2 },
+ { "MEMINTD02_POS", 10, 2 },
+ { "MEMINTD03_POS", 8, 2 },
+ { "MEMINTD04_POS", 6, 2 },
+ { "MEMINTD05_POS", 4, 2 },
+ { "MEMINTD06_POS", 2, 2 },
+ { "MEMINTD07_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_1", 0x450cc, 0 },
+ { "MEMINTD08_POS", 14, 2 },
+ { "MEMINTD09_POS", 12, 2 },
+ { "MEMINTD10_POS", 10, 2 },
+ { "MEMINTD11_POS", 8, 2 },
+ { "MEMINTD12_POS", 6, 2 },
+ { "MEMINTD13_POS", 4, 2 },
+ { "MEMINTD14_POS", 2, 2 },
+ { "MEMINTD15_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_PATTERN_POS_2", 0x450d0, 0 },
+ { "MEMINTD16_POS", 14, 2 },
+ { "MEMINTD17_POS", 12, 2 },
+ { "MEMINTD18_POS", 10, 2 },
+ { "MEMINTD19_POS", 8, 2 },
+ { "MEMINTD20_POS", 6, 2 },
+ { "MEMINTD21_POS", 4, 2 },
+ { "MEMINTD22_POS", 2, 2 },
+ { "MEMINTD23_POS", 0, 2 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x45078, 0 },
+ { "SYSCLK_DQSCLK_OFFSET", 8, 7 },
+ { "SYSCLK_RDCLK_OFFSET", 0, 7 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x450d4, 0 },
+ { "DQS_ALIGN_SM", 11, 5 },
+ { "DQS_ALIGN_CNTR", 7, 4 },
+ { "ITERATION_CNTR", 6, 1 },
+ { "DQS_ALIGN_ITER_CNTR", 0, 6 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x450d8, 0 },
+ { "CALIBRATE_BIT", 13, 3 },
+ { "DQS_ALIGN_QUAD", 11, 2 },
+ { "DQS_QUAD_CONFIG", 8, 3 },
+ { "OPERATE_MODE", 4, 4 },
+ { "EN_DQS_OFFSET", 3, 1 },
+ { "DQS_ALIGN_JITTER", 2, 1 },
+ { "DIS_CLK_GATE", 1, 1 },
+ { "MAX_DQS_ITER", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x451b4, 0 },
+ { "DESIRED_EDGE_CNTR_TARGET_HIGH", 8, 8 },
+ { "DESIRED_EDGE_CNTR_TARGET_LOW", 0, 8 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x451b8, 0 },
+ { "APPROACH_ALIGNMENT", 15, 1 },
+ { "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x450dc, 0 },
+ { "DQS_OFFSET", 8, 7 },
+ { "MC_DDRPHY_DP18_DEBUG_SEL", 0x4502c, 0 },
+ { "DP18_HS_PROBE_A_SEL", 11, 5 },
+ { "DP18_HS_PROBE_B_SEL", 6, 5 },
+ { "RD_DEBUG_SEL", 3, 3 },
+ { "WR_DEBUG_SEL", 0, 3 },
+ { "MC_DDRPHY_DP18_POWERDOWN_1", 0x451fc, 0 },
+ { "MASTER_PD_CNTL", 15, 1 },
+ { "ANALOG_INPUT_STAB2", 14, 1 },
+ { "EYEDAC_PD", 13, 1 },
+ { "ANALOG_OUTPUT_STAB", 9, 1 },
+ { "ANALOG_INPUT_STAB1", 8, 1 },
+ { "SYSCLK_CLK_GATE", 6, 2 },
+ { "WR_FIFO_STAB", 5, 1 },
+ { "DELAY_LINE_CTL_OVERRIDE", 4, 1 },
+ { "DP18_RX_PD", 2, 2 },
+ { "TX_TRISTATE_CNTL", 1, 1 },
+ { "VCC_REG_PD", 0, 1 },
+ { "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x45048, 0 },
+ { "DYN_POWER_CNTL_EN", 15, 1 },
+ { "DQS_ALIGN_BY_QUAD", 4, 1 },
+ { "MC_DDRPHY_DP18_DELAY_LINE_PWR_CTL", 0x451bc, 0 },
+ { "QUAD0_PWR_CTL", 12, 4 },
+ { "QUAD1_PWR_CTL", 8, 4 },
+ { "QUAD2_PWR_CTL", 4, 4 },
+ { "QUAD3_PWR_CTL", 0, 4 },
+ { "MC_DDRPHY_SEQ_RD_WR_DATA0", 0x47200, 0 },
+ { "MC_DDRPHY_SEQ_RD_WR_DATA1", 0x47204, 0 },
+ { "MC_DDRPHY_SEQ_CONFIG0", 0x47208, 0 },
+ { "MPR_PATTERN_BIT", 15, 1 },
+ { "TWO_CYCLE_ADDR_EN", 14, 1 },
+ { "MR_MASK_EN", 10, 4 },
+ { "PARITY_DLY", 9, 1 },
+ { "FORCE_RESERVED", 7, 1 },
+ { "HALT_ROTATION", 6, 1 },
+ { "FORCE_MPR", 5, 1 },
+ { "IPW_SIDEAB_SEL", 2, 1 },
+ { "PARITY_A17_MASK", 1, 1 },
+ { "X16_DEVICE", 0, 1 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR0", 0x4720c, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR1", 0x47210, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR2", 0x47214, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR3", 0x47218, 0 },
+ { "MC_DDRPHY_SEQ_RESERVED_ADDR4", 0x4721c, 0 },
+ { "MC_DDRPHY_SEQ_ERROR_STATUS0", 0x47220, 0 },
+ { "MULTIPLE_REQ_ERROR", 15, 1 },
+ { "INVALID_REQTYPE_ERRO", 14, 1 },
+ { "EARLY_REQ_ERROR", 13, 1 },
+ { "MULTIPLE_REQ_SOURCE", 10, 3 },
+ { "INVALID_REQTYPE", 6, 4 },
+ { "INVALID_REQ_SOURCE", 3, 3 },
+ { "EARLY_REQ_SOURCE", 0, 3 },
+ { "MC_DDRPHY_SEQ_ERROR_MASK0", 0x47224, 0 },
+ { "MULT_REQ_ERR_MASK", 15, 1 },
+ { "INVALID_REQTYPE_ERR_MASK", 14, 1 },
+ { "EARLY_REQ_ERR_MASK", 13, 1 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG0", 0x47228, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG1", 0x4722c, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG2", 0x47230, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_WR_CONFIG3", 0x47234, 0 },
+ { "ODT_WR_VALUES_BITS0_7", 8, 8 },
+ { "ODT_WR_VALUES_BITS8_15", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG0", 0x47238, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG1", 0x4723c, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG2", 0x47240, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_ODT_RD_CONFIG3", 0x47244, 0 },
+ { "ODT_RD_VALUES_x2", 8, 8 },
+ { "ODT_RD_VALUES_x2plus1", 0, 8 },
+ { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM0", 0x47248, 0 },
+ { "TMOD_CYCLES", 12, 4 },
+ { "TRCD_CYCLES", 8, 4 },
+ { "TRP_CYCLES", 4, 4 },
+ { "TRFC_CYCLES", 0, 4 },
+ { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM1", 0x4724c, 0 },
+ { "TZQINIT_CYCLES", 12, 4 },
+ { "TZQCS_CYCLES", 8, 4 },
+ { "TWLDQSEN_CYCLES", 4, 4 },
+ { "TWRMRD_CYCLES", 0, 4 },
+ { "MC_DDRPHY_SEQ_MEM_TIMING_PARAM2", 0x47250, 0 },
+ { "TODTLON_OFF_CYCLES", 12, 4 },
+ { "TRC_CYCLES", 8, 4 },
+ { "TMRSC_CYCLES", 4, 4 },
+ { "MRS_CMD_SPACE", 0, 4 },
+ { "MC_DDRPHY_WC_CONFIG0", 0x47600, 0 },
+ { "TWLO_TWLOE", 8, 8 },
+ { "WL_ONE_DQS_PULSE", 7, 1 },
+ { "FW_WR_RD", 1, 6 },
+ { "CUSTOM_INIT_WRITE", 0, 1 },
+ { "MC_DDRPHY_WC_CONFIG1", 0x47604, 0 },
+ { "BIG_STEP", 12, 4 },
+ { "SMALL_STEP", 9, 3 },
+ { "WR_PRE_DLY", 3, 6 },
+ { "MC_DDRPHY_WC_CONFIG2", 0x47608, 0 },
+ { "NUM_VALID_SAMPLES", 12, 4 },
+ { "FW_RD_WR", 6, 6 },
+ { "TWR_MPR", 2, 4 },
+ { "EN_RESET_WR_DELAY_WL", 0, 1 },
+ { "MC_DDRPHY_WC_CONFIG3", 0x47614, 0 },
+ { "DDR4_MRS_CMD_DQ_EN", 15, 1 },
+ { "MRS_CMD_DQ_ON", 9, 6 },
+ { "MRS_CMD_DQ_OFF", 3, 6 },
+ { "MC_DDRPHY_WC_WRCLK_CNTL", 0x47618, 0 },
+ { "WRCLK_CAL_START", 15, 1 },
+ { "WRCLK_CAL_DONE", 14, 1 },
+ { "MC_DDRPHY_WC_ERROR_STATUS0", 0x4760c, 0 },
+ { "WR_CNTL_ERROR", 15, 1 },
+ { "MC_DDRPHY_WC_ERROR_MASK0", 0x47610, 0 },
+ { "WR_CNTL_ERROR_MASK", 15, 1 },
+ { "MC_DDRPHY_RC_CONFIG0", 0x47400, 0 },
+ { "GLOBAL_PHY_OFFSET", 12, 4 },
+ { "ADVANCE_RD_VALID", 11, 1 },
+ { "ERS_MODE", 10, 1 },
+ { "SINGLE_BIT_MPR_RP0", 6, 1 },
+ { "SINGLE_BIT_MPR_RP1", 5, 1 },
+ { "SINGLE_BIT_MPR_RP2", 4, 1 },
+ { "SINGLE_BIT_MPR_RP3", 3, 1 },
+ { "ALIGN_ON_EVEN_CYCLES", 2, 1 },
+ { "PERFORM_RDCLK_ALIGN", 1, 1 },
+ { "STAGGERED_PATTERN", 0, 1 },
+ { "MC_DDRPHY_RC_CONFIG1", 0x47404, 0 },
+ { "OUTER_LOOP_CNT", 2, 14 },
+ { "MC_DDRPHY_RC_CONFIG2", 0x47408, 0 },
+ { "CONSEQ_PASS", 11, 5 },
+ { "BURST_WINDOW", 5, 2 },
+ { "ALLOW_RD_FIFO_AUTO_R_ESET", 4, 1 },
+ { "DIS_LOW_PWR_PER_CAL", 3, 1 },
+ { "MC_DDRPHY_RC_CONFIG3", 0x4741c, 0 },
+ { "FINE_CAL_STEP_SIZE", 13, 3 },
+ { "COARSE_CAL_STEP_SIZE", 9, 4 },
+ { "DQ_SEL_QUAD", 7, 2 },
+ { "DQ_SEL_LANE", 4, 3 },
+ { "MC_DDRPHY_RC_PERIODIC", 0x47420, 0 },
+ { "MC_DDRPHY_RC_ERROR_STATUS0", 0x47414, 0 },
+ { "RD_CNTL_ERROR", 15, 1 },
+ { "MC_DDRPHY_RC_ERROR_MASK0", 0x47418, 0 },
+ { "RD_CNTL_ERROR_MASK", 15, 1 },
+ { "MC_DDRPHY_APB_CONFIG0", 0x47800, 0 },
+ { "DISABLE_PARITY_CHECKER", 15, 1 },
+ { "GENERATE_EVEN_PARITY", 14, 1 },
+ { "FORCE_ON_CLK_GATE", 13, 1 },
+ { "DEBUG_BUS_SEL_LO", 12, 1 },
+ { "DEBUG_BUS_SEL_HI", 8, 4 },
+ { "MC_DDRPHY_APB_ERROR_STATUS0", 0x47804, 0 },
+ { "INVALID_ADDRESS", 15, 1 },
+ { "WR_PAR_ERR", 14, 1 },
+ { "MC_DDRPHY_APB_ERROR_MASK0", 0x47808, 0 },
+ { "INVALID_ADDRESS_MASK", 15, 1 },
+ { "WR_PAR_ERR_MASK", 14, 1 },
+ { "MC_DDRPHY_APB_DP18_POPULATION", 0x4780c, 0 },
+ { "DP18_0_Populated", 15, 1 },
+ { "DP18_1_Populated", 14, 1 },
+ { "DP18_2_Populated", 13, 1 },
+ { "DP18_3_Populated", 12, 1 },
+ { "DP18_4_Populated", 11, 1 },
+ { "DP18_5_Populated", 10, 1 },
+ { "DP18_6_Populated", 9, 1 },
+ { "DP18_7_Populated", 8, 1 },
+ { "DP18_8_Populated", 7, 1 },
+ { "DP18_9_Populated", 6, 1 },
+ { "DP18_10_Populated", 5, 1 },
+ { "DP18_11_Populated", 4, 1 },
+ { "DP18_12_Populated", 3, 1 },
+ { "DP18_13_Populated", 2, 1 },
+ { "DP18_14_Populated", 1, 1 },
+ { "MC_DDRPHY_APB_ADR_POPULATION", 0x47810, 0 },
+ { "ADR16_0_Populated", 15, 1 },
+ { "ADR16_1_Populated", 14, 1 },
+ { "ADR16_2_Populated", 13, 1 },
+ { "ADR16_3_Populated", 12, 1 },
+ { "ADR12_0_Populated", 7, 1 },
+ { "ADR12_1_Populated", 6, 1 },
+ { "ADR12_2_Populated", 5, 1 },
+ { "ADR12_3_Populated", 4, 1 },
+ { "MC_DDRPHY_APB_ATEST_MUX_SEL", 0x47814, 0 },
+ { "ATEST_CNTL", 10, 6 },
+ { "MC_DDRPHY_APB_MTCTL_REG0", 0x47820, 0 },
+ { "MT_DATA_MUX4_1MODE", 15, 1 },
+ { "MT_PLL_RESET", 14, 1 },
+ { "MT_SYSCLK_RESET", 13, 1 },
+ { "MT_GLOBAL_PHY_OFFSET", 9, 4 },
+ { "MT_DQ_SEL_QUAD", 7, 2 },
+ { "MT_PERFORM_RDCLK_ALIGN", 6, 1 },
+ { "MT_ALIGN_ON_EVEN_CYCLES", 5, 1 },
+ { "MT_WRCLK_CAL_START", 4, 1 },
+ { "MC_DDRPHY_APB_MTCTL_REG1", 0x47824, 0 },
+ { "MT_WPRD_ENABLE", 15, 1 },
+ { "MT_PVTP", 10, 5 },
+ { "MT_PVTN", 5, 5 },
+ { "MC_DDRPHY_APB_MTSTAT_REG0", 0x47828, 0 },
+ { "MC_DDRPHY_APB_MTSTAT_REG1", 0x4782c, 0 },
+ { "MT_ADR32_PLL_LOCK_SUM", 1, 1 },
+ { "MT_DP18_PLL_LOCK_SUM", 0, 1 },
+ { "MC_LMC_MCSTAT", 0x40040, 0 },
+ { "INIT_COMPLETE", 31, 1 },
+ { "SELF_REF_MODE", 30, 1 },
+ { "IDLE", 29, 1 },
+ { "DFI_INIT_COMPLETE", 28, 1 },
+ { "PREFILL_COMPLETE", 27, 1 },
+ { "MC_LMC_MCOPT1", 0x40080, 0 },
+ { "MC_PROTOCOL", 31, 1 },
+ { "DM_ENABLE", 30, 1 },
+ { "ECC_EN", 29, 1 },
+ { "ECC_COR", 28, 1 },
+ { "RDIMM", 27, 1 },
+ { "PMUM", 25, 2 },
+ { "WIDTH0", 24, 1 },
+ { "PORT_ID_CHK_EN", 23, 1 },
+ { "UIOS", 22, 1 },
+ { "QUADCS_RDIMM", 21, 1 },
+ { "ZQCL_EN", 20, 1 },
+ { "WIDTH1", 19, 1 },
+ { "WD_DLY", 18, 1 },
+ { "QDEPTH", 16, 2 },
+ { "RWOO", 15, 1 },
+ { "WOOO", 14, 1 },
+ { "DCOO", 13, 1 },
+ { "DEF_REF", 12, 1 },
+ { "DEV_TYPE", 11, 1 },
+ { "CA_PTY_DLY", 10, 1 },
+ { "ECC_MUX", 8, 2 },
+ { "CE_THRESHOLD", 0, 8 },
+ { "MC_LMC_MCOPT2", 0x40084, 0 },
+ { "SELF_REF_EN", 31, 1 },
+ { "XSR_PREVENT", 30, 1 },
+ { "INIT_START", 29, 1 },
+ { "MC_ENABLE", 28, 1 },
+ { "CLK_DISABLE", 24, 4 },
+ { "RESET_RANK", 20, 4 },
+ { "MCIF_COMP_PTY_EN", 19, 1 },
+ { "CKE_OE", 17, 1 },
+ { "RESET_OE", 16, 1 },
+ { "DFI_PHYUD_CNTL", 14, 1 },
+ { "DFI_PHYUD_ACK", 13, 1 },
+ { "DFI_INIT_START", 12, 1 },
+ { "PM_ENABLE", 8, 4 },
+ { "RD_DEFREF_CNT", 4, 4 },
+ { "MC_LMC_CFGR0", 0x40100, 0 },
+ { "ROW_WIDTH", 12, 3 },
+ { "ADDR_MODE", 8, 4 },
+ { "MIRROR", 4, 1 },
+ { "RANK_ENABLE", 0, 1 },
+ { "MC_LMC_INITSEQ0", 0x40140, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD0", 0x40144, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ1", 0x40148, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD1", 0x4014c, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ2", 0x40150, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD2", 0x40154, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ3", 0x40158, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD3", 0x4015c, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ4", 0x40160, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD4", 0x40164, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ5", 0x40168, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD5", 0x4016c, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ6", 0x40170, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD6", 0x40174, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ7", 0x40178, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD7", 0x4017c, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ8", 0x40180, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD8", 0x40184, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ9", 0x40188, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD9", 0x4018c, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ10", 0x40190, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD10", 0x40194, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ11", 0x40198, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD11", 0x4019c, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ12", 0x401a0, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD12", 0x401a4, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ13", 0x401a8, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD13", 0x401ac, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ14", 0x401b0, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD14", 0x401b4, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_INITSEQ15", 0x401b8, 0 },
+ { "INIT_ENABLE", 31, 1 },
+ { "WAIT", 16, 12 },
+ { "EN_MULTI_RANK_SEL", 4, 1 },
+ { "RANK", 0, 4 },
+ { "MC_LMC_CMD15", 0x401bc, 0 },
+ { "CMD", 29, 3 },
+ { "CMD_ACTN", 28, 1 },
+ { "BG1", 23, 1 },
+ { "BANK", 20, 3 },
+ { "ADDR", 0, 16 },
+ { "MC_LMC_SDTR0", 0x40200, 0 },
+ { "REFI", 16, 16 },
+ { "T_RFC_XPR", 0, 12 },
+ { "MC_LMC_SDTR1", 0x40204, 0 },
+ { "T_LEADOFF", 31, 1 },
+ { "ODT_DELAY", 30, 1 },
+ { "ODT_WIDTH", 29, 1 },
+ { "T_WTRO", 24, 4 },
+ { "T_RTWO", 16, 4 },
+ { "T_RTW_ADJ", 12, 4 },
+ { "T_WTWO", 8, 4 },
+ { "T_RTRO", 0, 4 },
+ { "MC_LMC_SDTR2", 0x40208, 0 },
+ { "T_CWL", 28, 4 },
+ { "T_RCD0", 24, 4 },
+ { "T_PL", 20, 4 },
+ { "T_RP0", 16, 4 },
+ { "T_RP1", 15, 1 },
+ { "T_RCD1", 14, 1 },
+ { "T_RC", 8, 6 },
+ { "T_RAS", 0, 6 },
+ { "MC_LMC_SDTR3", 0x4020c, 0 },
+ { "T_WTR_S", 28, 4 },
+ { "T_WTR", 24, 4 },
+ { "FAW_ADJ", 20, 2 },
+ { "T_RTP", 16, 4 },
+ { "T_RRD_L", 12, 4 },
+ { "T_RRD", 8, 4 },
+ { "T_XSDLL", 0, 8 },
+ { "MC_LMC_SDTR4", 0x40210, 0 },
+ { "T_RDDATA_EN", 24, 7 },
+ { "T_SYS_RDLAT", 16, 6 },
+ { "T_CCD_L", 12, 4 },
+ { "T_CCD", 8, 3 },
+ { "T_CPDED", 5, 3 },
+ { "T_MOD", 0, 5 },
+ { "MC_LMC_SDTR5", 0x40214, 0 },
+ { "T_PHY_WRDATA", 24, 3 },
+ { "T_PHY_WRLAT", 16, 5 },
+ { "MC_LMC_DBG0", 0x40228, 0 },
+ { "T_SYS_RDLAT_DBG", 16, 5 },
+ { "MC_LMC_SMR0", 0x40240, 0 },
+ { "SMR0_RFU0", 13, 3 },
+ { "PPD", 12, 1 },
+ { "WR_RTP", 9, 3 },
+ { "SMR0_DLL", 8, 1 },
+ { "TM", 7, 1 },
+ { "CL31", 4, 3 },
+ { "RBT", 3, 1 },
+ { "CL0", 2, 1 },
+ { "BL", 0, 2 },
+ { "MC_LMC_SMR1", 0x40244, 0 },
+ { "QOFF", 12, 1 },
+ { "TDQS", 11, 1 },
+ { "SMR1_RFU0", 10, 1 },
+ { "RTT_NOM0", 9, 1 },
+ { "SMR1_RFU1", 8, 1 },
+ { "WR_LEVEL", 7, 1 },
+ { "RTT_NOM1", 6, 1 },
+ { "DIC0", 5, 1 },
+ { "AL", 3, 2 },
+ { "RTT_NOM2", 2, 1 },
+ { "DIC1", 1, 1 },
+ { "SMR1_DLL", 0, 1 },
+ { "MC_LMC_SMR2", 0x40248, 0 },
+ { "WR_CRC", 12, 1 },
+ { "RD_CRC", 11, 1 },
+ { "RTT_WR", 9, 2 },
+ { "SMR2_RFU0", 8, 1 },
+ { "SRT_ASR1", 7, 1 },
+ { "ASR0", 6, 1 },
+ { "CWL", 3, 3 },
+ { "PASR", 0, 3 },
+ { "MC_LMC_SMR3", 0x4024c, 0 },
+ { "MPR_RD_FMT", 11, 2 },
+ { "SMR3_RFU0", 9, 2 },
+ { "FGR_MODE", 6, 3 },
+ { "MRS_RDO", 5, 1 },
+ { "DRAM_ADR", 4, 1 },
+ { "GD_MODE", 3, 1 },
+ { "MPR", 2, 1 },
+ { "MPR_SEL", 0, 2 },
+ { "MC_LMC_SMR4", 0x40250, 0 },
+ { "WR_PRE", 12, 1 },
+ { "RD_PRE", 11, 1 },
+ { "RPT_MODE", 10, 1 },
+ { "FESR_MODE", 9, 1 },
+ { "CS_LAT_MODE", 6, 3 },
+ { "ALERT_STAT", 5, 1 },
+ { "IVM_MODE", 4, 1 },
+ { "TCR_MODE", 3, 1 },
+ { "TCR_RANGE", 2, 1 },
+ { "MPD_MODE", 1, 1 },
+ { "SMR4_RFU", 0, 1 },
+ { "MC_LMC_SMR5", 0x40254, 0 },
+ { "RD_DBI", 11, 1 },
+ { "WR_DBI", 10, 1 },
+ { "DM_MODE", 9, 1 },
+ { "RTT_PARK", 6, 3 },
+ { "SMR5_RFU", 5, 1 },
+ { "PAR_ERR_STAT", 4, 1 },
+ { "CRC_CLEAR", 3, 1 },
+ { "PAR_LAT_MODE", 0, 3 },
+ { "MC_LMC_SMR6", 0x40258, 0 },
+ { "TCCD_L", 10, 3 },
+ { "SRM6_RFU", 7, 3 },
+ { "VREF_DQ_RANGE", 6, 1 },
+ { "VREF_DQ_VALUE", 0, 6 },
+ { "MC_LMC_ODTR0", 0x40280, 0 },
+ { "RK0W", 25, 1 },
+ { "RK0R", 24, 1 },
+ { "MC_LMC_CALSTAT", 0x40304, 0 },
+ { "PHYUPD_ERR", 28, 4 },
+ { "PHYUPD_BUSY", 27, 1 },
+ { "MC_LMC_T_PHYUPD0", 0x40330, 0 },
+ { "MC_LMC_T_PHYUPD1", 0x40334, 0 },
+ { "MC_LMC_T_PHYUPD2", 0x40338, 0 },
+ { "MC_LMC_T_PHYUPD3", 0x4033c, 0 },
+ { "MC_P_DDRPHY_RST_CTRL", 0x41300, 0 },
+ { "PHY_CAL_REQ", 21, 1 },
+ { "PHY_DRAM_WL", 17, 4 },
+ { "PHY_CALIB_DONE", 5, 1 },
+ { "CTL_CAL_REQ", 4, 1 },
+ { "CTL_CKE", 3, 1 },
+ { "CTL_RST_N", 2, 1 },
+ { "DDRIO_ENABLE", 1, 1 },
+ { "PHY_RST_N", 0, 1 },
+ { "MC_P_PERFORMANCE_CTRL", 0x41304, 0 },
+ { "BUF_USE_TH", 12, 3 },
+ { "MC_IDLE_TH", 8, 4 },
+ { "RMW_DEFER_EN", 7, 1 },
+ { "DDR3_BRBC_MODE", 6, 1 },
+ { "RMW_DWRITE_EN", 5, 1 },
+ { "RMW_MERGE_EN", 4, 1 },
+ { "SYNC_PAB_EN", 3, 1 },
+ { "STALL_CHK_BIT", 2, 1 },
+ { "DDR3_BRC_MODE", 1, 1 },
+ { "RMW_PERF_CTRL", 0, 1 },
+ { "MC_P_ECC_CTRL", 0x41308, 0 },
+ { "ECC_BYPASS_BIST", 1, 1 },
+ { "ECC_DISABLE", 0, 1 },
+ { "MC_P_PAR_ENABLE", 0x4130c, 0 },
+ { "ECC_UE_PAR_ENABLE", 3, 1 },
+ { "ECC_CE_PAR_ENABLE", 2, 1 },
+ { "PERR_REG_INT_ENABLE", 1, 1 },
+ { "PERR_BLK_INT_ENABLE", 0, 1 },
+ { "MC_P_PAR_CAUSE", 0x41310, 0 },
+ { "ECC_UE_PAR_CAUSE", 3, 1 },
+ { "ECC_CE_PAR_CAUSE", 2, 1 },
+ { "FIFOR_PAR_CAUSE", 1, 1 },
+ { "RDATA_FIFOR_PAR_CAUSE", 0, 1 },
+ { "MC_P_INT_ENABLE", 0x41314, 0 },
+ { "ECC_UE_INT_ENABLE", 2, 1 },
+ { "ECC_CE_INT_ENABLE", 1, 1 },
+ { "PERR_INT_ENABLE", 0, 1 },
+ { "MC_P_INT_CAUSE", 0x41318, 0 },
+ { "ECC_UE_INT_CAUSE", 2, 1 },
+ { "ECC_CE_INT_CAUSE", 1, 1 },
+ { "PERR_INT_CAUSE", 0, 1 },
+ { "MC_P_ECC_STATUS", 0x4131c, 0 },
+ { "ECC_CECNT", 16, 16 },
+ { "ECC_UECNT", 0, 16 },
+ { "MC_P_PHY_CTRL", 0x41320, 0 },
+ { "MC_P_STATIC_CFG_STATUS", 0x41324, 0 },
+ { "STATIC_PP64", 26, 1 },
+ { "STATIC_PPEN", 25, 1 },
+ { "STATIC_OOOEN", 24, 1 },
+ { "STATIC_AWEN", 23, 1 },
+ { "STATIC_SWLAT", 18, 5 },
+ { "STATIC_WLAT", 17, 1 },
+ { "STATIC_ALIGN", 16, 1 },
+ { "STATIC_SLAT", 11, 5 },
+ { "STATIC_LAT", 10, 1 },
+ { "STATIC_MODE", 9, 1 },
+ { "STATIC_DEN", 6, 3 },
+ { "STATIC_ORG", 5, 1 },
+ { "STATIC_RKS", 4, 1 },
+ { "STATIC_WIDTH", 1, 3 },
+ { "STATIC_SLOW", 0, 1 },
+ { "MC_P_CORE_PCTL_STAT", 0x41328, 0 },
+ { "MC_P_DEBUG_CNT", 0x4132c, 0 },
+ { "WDATA_OCNT", 8, 5 },
+ { "RDATA_OCNT", 0, 5 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41330, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41334, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41338, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x4133c, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41340, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41344, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41348, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x4134c, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41350, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41354, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41358, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x4135c, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41360, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41364, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x41368, 0 },
+ { "MC_CE_ERR_DATA_RDATA", 0x4136c, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41370, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41374, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41378, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x4137c, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41380, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41384, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41388, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x4138c, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41390, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41394, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x41398, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x4139c, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x413a0, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x413a4, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x413a8, 0 },
+ { "MC_UE_ERR_DATA_RDATA", 0x413ac, 0 },
+ { "MC_CE_ADDR", 0x413b0, 0 },
+ { "MC_UE_ADDR", 0x413b4, 0 },
+ { "MC_P_DEEP_SLEEP", 0x413b8, 0 },
+ { "SleepStatus", 1, 1 },
+ { "SleepReq", 0, 1 },
+ { "MC_P_FPGA_BONUS", 0x413bc, 0 },
+ { "MC_P_DEBUG_CFG", 0x413c0, 0 },
+ { "DEBUG_OR", 15, 1 },
+ { "DEBUG_HI", 14, 1 },
+ { "DEBUG_RPT", 13, 1 },
+ { "DEBUGPAGE", 10, 3 },
+ { "DEBUGSELH", 5, 5 },
+ { "DEBUGSELL", 0, 5 },
+ { "MC_P_DEBUG_RPT", 0x413c4, 0 },
+ { "MC_P_PHY_ADR_CK_EN", 0x413c8, 0 },
+ { "MC_CE_ERR_ECC_DATA0", 0x413d0, 0 },
+ { "MC_CE_ERR_ECC_DATA1", 0x413d4, 0 },
+ { "MC_UE_ERR_ECC_DATA0", 0x413d8, 0 },
+ { "MC_UE_ERR_ECC_DATA1", 0x413dc, 0 },
+ { "MC_P_RMW_PRIO", 0x413f0, 0 },
+ { "WR_HI_TH", 24, 8 },
+ { "WR_MID_TH", 16, 8 },
+ { "RD_HI_TH", 8, 8 },
+ { "RD_MID_TH", 0, 8 },
+ { "MC_P_BIST_CMD", 0x41400, 0 },
+ { "START_BIST", 31, 1 },
+ { "BURST_LEN", 16, 2 },
+ { "BIST_CMD_GAP", 8, 8 },
+ { "BIST_OPCODE", 0, 2 },
+ { "MC_P_BIST_CMD_ADDR", 0x41404, 0 },
+ { "MC_P_BIST_CMD_LEN", 0x41408, 0 },
+ { "MC_P_BIST_DATA_PATTERN", 0x4140c, 0 },
+ { "MC_P_BIST_USER_WMASK0", 0x41414, 0 },
+ { "MC_P_BIST_USER_WMASK1", 0x41418, 0 },
+ { "MC_P_BIST_USER_WMASK2", 0x4141c, 0 },
+ { "MASK_128_1", 9, 1 },
+ { "MASK_128_0", 8, 1 },
+ { "USER_MASK_ECC", 0, 8 },
+ { "MC_P_BIST_NUM_ERR", 0x41480, 0 },
+ { "MC_P_BIST_ERR_FIRST_ADDR", 0x41484, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x41488, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x4148c, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x41490, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x41494, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x41498, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x4149c, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414a0, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414a4, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414a8, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414ac, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414b0, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414b4, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414b8, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414bc, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414c0, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414c4, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414c8, 0 },
+ { "MC_P_BIST_STATUS_RDATA", 0x414cc, 0 },
+ { "MC_P_BIST_CRC_SEED", 0x414d0, 0 },
+ { NULL }
+};
+
+struct reg_info t6_edc_t60_regs[] = {
+ { "EDC_H_REF", 0x50000, 0 },
+ { "SleepStatus", 31, 1 },
+ { "SleepReq", 30, 1 },
+ { "PING_PONG", 29, 1 },
+ { "QDR_ClkPhase", 24, 3 },
+ { "MaxOpsPerTRC", 21, 3 },
+ { "NumPipeStages", 19, 2 },
+ { "EDC_INST_NUM", 18, 1 },
+ { "ENABLE_PERF", 17, 1 },
+ { "ECC_BYPASS", 16, 1 },
+ { "RefFreq", 0, 16 },
+ { "EDC_H_BIST_CMD", 0x50004, 0 },
+ { "START_BIST", 31, 1 },
+ { "BURST_LEN", 16, 2 },
+ { "BIST_CMD_GAP", 8, 8 },
+ { "BIST_OPCODE", 0, 2 },
+ { "EDC_H_BIST_CMD_ADDR", 0x50008, 0 },
+ { "EDC_H_BIST_CMD_LEN", 0x5000c, 0 },
+ { "EDC_H_BIST_DATA_PATTERN", 0x50010, 0 },
+ { "EDC_H_BIST_USER_WDATA0", 0x50014, 0 },
+ { "EDC_H_BIST_USER_WDATA1", 0x50018, 0 },
+ { "EDC_H_BIST_USER_WDATA2", 0x5001c, 0 },
+ { "USER_DATA_MASK", 8, 9 },
+ { "USER_DATA2", 0, 8 },
+ { "EDC_H_BIST_NUM_ERR", 0x50020, 0 },
+ { "EDC_H_BIST_ERR_FIRST_ADDR", 0x50024, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50028, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5002c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50030, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50034, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50038, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5003c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50040, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50044, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50048, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5004c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50050, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50054, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50058, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5005c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50060, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50064, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50068, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5006c, 0 },
+ { "EDC_H_PAR_ENABLE", 0x50070, 0 },
+ { "ECC_UE_PAR_ENABLE", 2, 1 },
+ { "ECC_CE_PAR_ENABLE", 1, 1 },
+ { "PERR_PAR_ENABLE", 0, 1 },
+ { "EDC_H_INT_ENABLE", 0x50074, 0 },
+ { "ECC_UE_INT_ENABLE", 2, 1 },
+ { "ECC_CE_INT_ENABLE", 1, 1 },
+ { "PERR_INT_ENABLE", 0, 1 },
+ { "EDC_H_INT_CAUSE", 0x50078, 0 },
+ { "ECC_UE_INT0_CAUSE", 5, 1 },
+ { "ECC_CE_INT0_CAUSE", 4, 1 },
+ { "PERR_INT0_CAUSE", 3, 1 },
+ { "ECC_UE_INT_CAUSE", 2, 1 },
+ { "ECC_CE_INT_CAUSE", 1, 1 },
+ { "PERR_INT_CAUSE", 0, 1 },
+ { "EDC_H_ECC_STATUS", 0x5007c, 0 },
+ { "ECC_CECNT", 16, 16 },
+ { "ECC_UECNT", 0, 16 },
+ { "EDC_H_ECC_ERR_SEL", 0x50080, 0 },
+ { "EDC_H_ECC_ERR_ADDR", 0x50084, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50090, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50094, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50098, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x5009c, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500a0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500a4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500a8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500ac, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500b0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500b4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500b8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500bc, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500c0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500c4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500c8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x500cc, 0 },
+ { "EDC_H_DBG_MA_CMD_INTF", 0x50300, 0 },
+ { "MCmdAddr", 12, 20 },
+ { "MCmdLen", 5, 7 },
+ { "MCmdNRE", 4, 1 },
+ { "MCmdNRB", 3, 1 },
+ { "MCmdWr", 2, 1 },
+ { "MCmdRdy", 1, 1 },
+ { "MCmdVld", 0, 1 },
+ { "EDC_H_DBG_MA_WDATA_INTF", 0x50304, 0 },
+ { "MWDataVld", 31, 1 },
+ { "MWDataRdy", 30, 1 },
+ { "MWData", 0, 30 },
+ { "EDC_H_DBG_MA_RDATA_INTF", 0x50308, 0 },
+ { "MRspVld", 31, 1 },
+ { "MRspRdy", 30, 1 },
+ { "MRspData", 0, 30 },
+ { "EDC_H_DBG_BIST_CMD_INTF", 0x5030c, 0 },
+ { "BCmdAddr", 9, 23 },
+ { "BCmdLen", 3, 6 },
+ { "BCmdWr", 2, 1 },
+ { "BCmdRdy", 1, 1 },
+ { "BCmdVld", 0, 1 },
+ { "EDC_H_DBG_BIST_WDATA_INTF", 0x50310, 0 },
+ { "BWDataVld", 31, 1 },
+ { "BWDataRdy", 30, 1 },
+ { "BWData", 0, 30 },
+ { "EDC_H_DBG_BIST_RDATA_INTF", 0x50314, 0 },
+ { "BRspVld", 31, 1 },
+ { "BRspRdy", 30, 1 },
+ { "BRspData", 0, 30 },
+ { "EDC_H_DBG_EDRAM_CMD_INTF", 0x50318, 0 },
+ { "EdramAddr", 16, 16 },
+ { "EdramDwsn", 8, 8 },
+ { "EdramCra", 5, 3 },
+ { "EdramRefEnLo", 4, 1 },
+ { "Edram1WrEnLo", 3, 1 },
+ { "Edram1RdEnLo", 2, 1 },
+ { "Edram0WrEnLo", 1, 1 },
+ { "Edram0RdEnLo", 0, 1 },
+ { "EDC_H_DBG_EDRAM_WDATA_INTF", 0x5031c, 0 },
+ { "EdramWData", 9, 23 },
+ { "EdramWByteEn", 0, 9 },
+ { "EDC_H_DBG_EDRAM0_RDATA_INTF", 0x50320, 0 },
+ { "EDC_H_DBG_EDRAM1_RDATA_INTF", 0x50324, 0 },
+ { "EDC_H_DBG_MA_WR_REQ_CNT", 0x50328, 0 },
+ { "EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT", 0x5032c, 0 },
+ { "EDC_H_DBG_MA_WR_DAT_CYC_CNT", 0x50330, 0 },
+ { "EDC_H_DBG_MA_RD_REQ_CNT", 0x50334, 0 },
+ { "EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT", 0x50338, 0 },
+ { "EDC_H_DBG_MA_RD_DAT_CYC_CNT", 0x5033c, 0 },
+ { "EDC_H_DBG_BIST_WR_REQ_CNT", 0x50340, 0 },
+ { "EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT", 0x50344, 0 },
+ { "EDC_H_DBG_BIST_WR_DAT_CYC_CNT", 0x50348, 0 },
+ { "EDC_H_DBG_BIST_RD_REQ_CNT", 0x5034c, 0 },
+ { "EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT", 0x50350, 0 },
+ { "EDC_H_DBG_BIST_RD_DAT_CYC_CNT", 0x50354, 0 },
+ { "EDC_H_DBG_EDRAM0_WR_REQ_CNT", 0x50358, 0 },
+ { "EDC_H_DBG_EDRAM0_RD_REQ_CNT", 0x5035c, 0 },
+ { "EDC_H_DBG_EDRAM0_RMW_CNT", 0x50360, 0 },
+ { "EDC_H_DBG_EDRAM1_WR_REQ_CNT", 0x50364, 0 },
+ { "EDC_H_DBG_EDRAM1_RD_REQ_CNT", 0x50368, 0 },
+ { "EDC_H_DBG_EDRAM1_RMW_CNT", 0x5036c, 0 },
+ { "EDC_H_DBG_EDRAM_REF_BURST_CNT", 0x50370, 0 },
+ { "EDC_H_DBG_FIFO_STATUS", 0x50374, 0 },
+ { "rdtag_notfull", 17, 1 },
+ { "rdtag_notempty", 16, 1 },
+ { "inp_cmdq_notfull_arb", 15, 1 },
+ { "inp_cmdq_notempty", 14, 1 },
+ { "inp_wrdq_wrrdy", 13, 1 },
+ { "inp_wrdq_notempty", 12, 1 },
+ { "inp_beq_wrrdy_open", 11, 1 },
+ { "inp_beq_notempty", 10, 1 },
+ { "rddq_notfull_open", 9, 1 },
+ { "rddq_rdcnt", 4, 5 },
+ { "rdsideq_notfull", 3, 1 },
+ { "rdsideq_notempty", 2, 1 },
+ { "stg_cmdq_notempty", 1, 1 },
+ { "stg_wrdq_notempty", 0, 1 },
+ { "EDC_H_DBG_FSM_STATE", 0x50378, 0 },
+ { "CmdSplitFsm", 3, 1 },
+ { "CmdFsm", 0, 3 },
+ { "EDC_H_DBG_STALL_CYCLES", 0x5037c, 0 },
+ { "stall_rmw", 19, 1 },
+ { "stall_edc_cmd", 18, 1 },
+ { "dead_cycle0", 17, 1 },
+ { "dead_cycle1", 16, 1 },
+ { "dead_cycle0_bbi", 15, 1 },
+ { "dead_cycle1_bbi", 14, 1 },
+ { "dead_cycle0_max_op", 13, 1 },
+ { "dead_cycle1_max_op", 12, 1 },
+ { "dead_cycle0_pre_ref", 11, 1 },
+ { "dead_cycle1_pre_ref", 10, 1 },
+ { "dead_cycle0_post_ref", 9, 1 },
+ { "dead_cycle1_post_ref", 8, 1 },
+ { "dead_cycle0_rmw", 7, 1 },
+ { "dead_cycle1_rmw", 6, 1 },
+ { "dead_cycle0_bbi_rmw", 5, 1 },
+ { "dead_cycle1_bbi_rmw", 4, 1 },
+ { "dead_cycle0_pre_ref_rmw", 3, 1 },
+ { "dead_cycle1_pre_ref_rmw", 2, 1 },
+ { "dead_cycle0_post_ref_rmw", 1, 1 },
+ { "dead_cycle1_post_ref_rmw", 0, 1 },
+ { "EDC_H_DBG_CMD_QUEUE", 0x50380, 0 },
+ { "ECmdNRE", 31, 1 },
+ { "ECmdNRB", 30, 1 },
+ { "ECmdWr", 29, 1 },
+ { "ECmdLen", 22, 7 },
+ { "ECmdAddr", 0, 22 },
+ { "EDC_H_DBG_REFRESH", 0x50384, 0 },
+ { "RefDone", 12, 1 },
+ { "RefCntExpr", 11, 1 },
+ { "RefPtr", 8, 3 },
+ { "RefCnt", 0, 8 },
+ { "EDC_H_BIST_CRC_SEED", 0x50400, 0 },
+ { NULL }
+};
+
+struct reg_info t6_edc_t61_regs[] = {
+ { "EDC_H_REF", 0x50800, 0 },
+ { "SleepStatus", 31, 1 },
+ { "SleepReq", 30, 1 },
+ { "PING_PONG", 29, 1 },
+ { "QDR_ClkPhase", 24, 3 },
+ { "MaxOpsPerTRC", 21, 3 },
+ { "NumPipeStages", 19, 2 },
+ { "EDC_INST_NUM", 18, 1 },
+ { "ENABLE_PERF", 17, 1 },
+ { "ECC_BYPASS", 16, 1 },
+ { "RefFreq", 0, 16 },
+ { "EDC_H_BIST_CMD", 0x50804, 0 },
+ { "START_BIST", 31, 1 },
+ { "BURST_LEN", 16, 2 },
+ { "BIST_CMD_GAP", 8, 8 },
+ { "BIST_OPCODE", 0, 2 },
+ { "EDC_H_BIST_CMD_ADDR", 0x50808, 0 },
+ { "EDC_H_BIST_CMD_LEN", 0x5080c, 0 },
+ { "EDC_H_BIST_DATA_PATTERN", 0x50810, 0 },
+ { "EDC_H_BIST_USER_WDATA0", 0x50814, 0 },
+ { "EDC_H_BIST_USER_WDATA1", 0x50818, 0 },
+ { "EDC_H_BIST_USER_WDATA2", 0x5081c, 0 },
+ { "USER_DATA_MASK", 8, 9 },
+ { "USER_DATA2", 0, 8 },
+ { "EDC_H_BIST_NUM_ERR", 0x50820, 0 },
+ { "EDC_H_BIST_ERR_FIRST_ADDR", 0x50824, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50828, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5082c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50830, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50834, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50838, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5083c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50840, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50844, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50848, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5084c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50850, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50854, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50858, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5085c, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50860, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50864, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x50868, 0 },
+ { "EDC_H_BIST_STATUS_RDATA", 0x5086c, 0 },
+ { "EDC_H_PAR_ENABLE", 0x50870, 0 },
+ { "ECC_UE_PAR_ENABLE", 2, 1 },
+ { "ECC_CE_PAR_ENABLE", 1, 1 },
+ { "PERR_PAR_ENABLE", 0, 1 },
+ { "EDC_H_INT_ENABLE", 0x50874, 0 },
+ { "ECC_UE_INT_ENABLE", 2, 1 },
+ { "ECC_CE_INT_ENABLE", 1, 1 },
+ { "PERR_INT_ENABLE", 0, 1 },
+ { "EDC_H_INT_CAUSE", 0x50878, 0 },
+ { "ECC_UE_INT0_CAUSE", 5, 1 },
+ { "ECC_CE_INT0_CAUSE", 4, 1 },
+ { "PERR_INT0_CAUSE", 3, 1 },
+ { "ECC_UE_INT_CAUSE", 2, 1 },
+ { "ECC_CE_INT_CAUSE", 1, 1 },
+ { "PERR_INT_CAUSE", 0, 1 },
+ { "EDC_H_ECC_STATUS", 0x5087c, 0 },
+ { "ECC_CECNT", 16, 16 },
+ { "ECC_UECNT", 0, 16 },
+ { "EDC_H_ECC_ERR_SEL", 0x50880, 0 },
+ { "EDC_H_ECC_ERR_ADDR", 0x50884, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50890, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50894, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x50898, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x5089c, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508a0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508a4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508a8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508ac, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508b0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508b4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508b8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508bc, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508c0, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508c4, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508c8, 0 },
+ { "EDC_H_ECC_ERR_DATA_RDATA", 0x508cc, 0 },
+ { "EDC_H_DBG_MA_CMD_INTF", 0x50b00, 0 },
+ { "MCmdAddr", 12, 20 },
+ { "MCmdLen", 5, 7 },
+ { "MCmdNRE", 4, 1 },
+ { "MCmdNRB", 3, 1 },
+ { "MCmdWr", 2, 1 },
+ { "MCmdRdy", 1, 1 },
+ { "MCmdVld", 0, 1 },
+ { "EDC_H_DBG_MA_WDATA_INTF", 0x50b04, 0 },
+ { "MWDataVld", 31, 1 },
+ { "MWDataRdy", 30, 1 },
+ { "MWData", 0, 30 },
+ { "EDC_H_DBG_MA_RDATA_INTF", 0x50b08, 0 },
+ { "MRspVld", 31, 1 },
+ { "MRspRdy", 30, 1 },
+ { "MRspData", 0, 30 },
+ { "EDC_H_DBG_BIST_CMD_INTF", 0x50b0c, 0 },
+ { "BCmdAddr", 9, 23 },
+ { "BCmdLen", 3, 6 },
+ { "BCmdWr", 2, 1 },
+ { "BCmdRdy", 1, 1 },
+ { "BCmdVld", 0, 1 },
+ { "EDC_H_DBG_BIST_WDATA_INTF", 0x50b10, 0 },
+ { "BWDataVld", 31, 1 },
+ { "BWDataRdy", 30, 1 },
+ { "BWData", 0, 30 },
+ { "EDC_H_DBG_BIST_RDATA_INTF", 0x50b14, 0 },
+ { "BRspVld", 31, 1 },
+ { "BRspRdy", 30, 1 },
+ { "BRspData", 0, 30 },
+ { "EDC_H_DBG_EDRAM_CMD_INTF", 0x50b18, 0 },
+ { "EdramAddr", 16, 16 },
+ { "EdramDwsn", 8, 8 },
+ { "EdramCra", 5, 3 },
+ { "EdramRefEnLo", 4, 1 },
+ { "Edram1WrEnLo", 3, 1 },
+ { "Edram1RdEnLo", 2, 1 },
+ { "Edram0WrEnLo", 1, 1 },
+ { "Edram0RdEnLo", 0, 1 },
+ { "EDC_H_DBG_EDRAM_WDATA_INTF", 0x50b1c, 0 },
+ { "EdramWData", 9, 23 },
+ { "EdramWByteEn", 0, 9 },
+ { "EDC_H_DBG_EDRAM0_RDATA_INTF", 0x50b20, 0 },
+ { "EDC_H_DBG_EDRAM1_RDATA_INTF", 0x50b24, 0 },
+ { "EDC_H_DBG_MA_WR_REQ_CNT", 0x50b28, 0 },
+ { "EDC_H_DBG_MA_WR_EXP_DAT_CYC_CNT", 0x50b2c, 0 },
+ { "EDC_H_DBG_MA_WR_DAT_CYC_CNT", 0x50b30, 0 },
+ { "EDC_H_DBG_MA_RD_REQ_CNT", 0x50b34, 0 },
+ { "EDC_H_DBG_MA_RD_EXP_DAT_CYC_CNT", 0x50b38, 0 },
+ { "EDC_H_DBG_MA_RD_DAT_CYC_CNT", 0x50b3c, 0 },
+ { "EDC_H_DBG_BIST_WR_REQ_CNT", 0x50b40, 0 },
+ { "EDC_H_DBG_BIST_WR_EXP_DAT_CYC_CNT", 0x50b44, 0 },
+ { "EDC_H_DBG_BIST_WR_DAT_CYC_CNT", 0x50b48, 0 },
+ { "EDC_H_DBG_BIST_RD_REQ_CNT", 0x50b4c, 0 },
+ { "EDC_H_DBG_BIST_RD_EXP_DAT_CYC_CNT", 0x50b50, 0 },
+ { "EDC_H_DBG_BIST_RD_DAT_CYC_CNT", 0x50b54, 0 },
+ { "EDC_H_DBG_EDRAM0_WR_REQ_CNT", 0x50b58, 0 },
+ { "EDC_H_DBG_EDRAM0_RD_REQ_CNT", 0x50b5c, 0 },
+ { "EDC_H_DBG_EDRAM0_RMW_CNT", 0x50b60, 0 },
+ { "EDC_H_DBG_EDRAM1_WR_REQ_CNT", 0x50b64, 0 },
+ { "EDC_H_DBG_EDRAM1_RD_REQ_CNT", 0x50b68, 0 },
+ { "EDC_H_DBG_EDRAM1_RMW_CNT", 0x50b6c, 0 },
+ { "EDC_H_DBG_EDRAM_REF_BURST_CNT", 0x50b70, 0 },
+ { "EDC_H_DBG_FIFO_STATUS", 0x50b74, 0 },
+ { "rdtag_notfull", 17, 1 },
+ { "rdtag_notempty", 16, 1 },
+ { "inp_cmdq_notfull_arb", 15, 1 },
+ { "inp_cmdq_notempty", 14, 1 },
+ { "inp_wrdq_wrrdy", 13, 1 },
+ { "inp_wrdq_notempty", 12, 1 },
+ { "inp_beq_wrrdy_open", 11, 1 },
+ { "inp_beq_notempty", 10, 1 },
+ { "rddq_notfull_open", 9, 1 },
+ { "rddq_rdcnt", 4, 5 },
+ { "rdsideq_notfull", 3, 1 },
+ { "rdsideq_notempty", 2, 1 },
+ { "stg_cmdq_notempty", 1, 1 },
+ { "stg_wrdq_notempty", 0, 1 },
+ { "EDC_H_DBG_FSM_STATE", 0x50b78, 0 },
+ { "CmdSplitFsm", 3, 1 },
+ { "CmdFsm", 0, 3 },
+ { "EDC_H_DBG_STALL_CYCLES", 0x50b7c, 0 },
+ { "stall_rmw", 19, 1 },
+ { "stall_edc_cmd", 18, 1 },
+ { "dead_cycle0", 17, 1 },
+ { "dead_cycle1", 16, 1 },
+ { "dead_cycle0_bbi", 15, 1 },
+ { "dead_cycle1_bbi", 14, 1 },
+ { "dead_cycle0_max_op", 13, 1 },
+ { "dead_cycle1_max_op", 12, 1 },
+ { "dead_cycle0_pre_ref", 11, 1 },
+ { "dead_cycle1_pre_ref", 10, 1 },
+ { "dead_cycle0_post_ref", 9, 1 },
+ { "dead_cycle1_post_ref", 8, 1 },
+ { "dead_cycle0_rmw", 7, 1 },
+ { "dead_cycle1_rmw", 6, 1 },
+ { "dead_cycle0_bbi_rmw", 5, 1 },
+ { "dead_cycle1_bbi_rmw", 4, 1 },
+ { "dead_cycle0_pre_ref_rmw", 3, 1 },
+ { "dead_cycle1_pre_ref_rmw", 2, 1 },
+ { "dead_cycle0_post_ref_rmw", 1, 1 },
+ { "dead_cycle1_post_ref_rmw", 0, 1 },
+ { "EDC_H_DBG_CMD_QUEUE", 0x50b80, 0 },
+ { "ECmdNRE", 31, 1 },
+ { "ECmdNRB", 30, 1 },
+ { "ECmdWr", 29, 1 },
+ { "ECmdLen", 22, 7 },
+ { "ECmdAddr", 0, 22 },
+ { "EDC_H_DBG_REFRESH", 0x50b84, 0 },
+ { "RefDone", 12, 1 },
+ { "RefCntExpr", 11, 1 },
+ { "RefPtr", 8, 3 },
+ { "RefCnt", 0, 8 },
+ { "EDC_H_BIST_CRC_SEED", 0x50c00, 0 },
+ { NULL }
+};
+
+struct reg_info t6_hma_t6_regs[] = {
+ { "HMA_TABLE_ACCESS", 0x51000, 0 },
+ { "TRIG", 31, 1 },
+ { "RW", 30, 1 },
+ { "L_SEL", 0, 4 },
+ { "HMA_TABLE_LINE0", 0x51004, 0 },
+ { "HMA_TABLE_LINE1", 0x51008, 0 },
+ { "HMA_TABLE_LINE2", 0x5100c, 0 },
+ { "HMA_TABLE_LINE3", 0x51010, 0 },
+ { "HMA_TABLE_LINE4", 0x51014, 0 },
+ { "HMA_TABLE_LINE5", 0x51018, 0 },
+ { "FID", 16, 11 },
+ { "NOS", 15, 1 },
+ { "RO", 14, 1 },
+ { "TPH", 12, 2 },
+ { "TPH_V", 11, 1 },
+ { "DCA", 0, 11 },
+ { "HMA_COOKIE", 0x5101c, 0 },
+ { "C_REQ", 31, 1 },
+ { "C_FID", 18, 11 },
+ { "C_VAL", 8, 10 },
+ { "C_SEL", 0, 4 },
+ { "HMA_CFG", 0x51020, 0 },
+ { "OP_MODE", 31, 1 },
+ { "HMA_TLB_ACCESS", 0x51028, 0 },
+ { "TRIG", 31, 1 },
+ { "RW", 30, 1 },
+ { "INV_ALL", 29, 1 },
+ { "LOCK_ENTRY", 28, 1 },
+ { "E_SEL", 0, 5 },
+ { "HMA_TLB_BITS", 0x5102c, 0 },
+ { "VA", 12, 20 },
+ { "VALID_E", 4, 1 },
+ { "LOCK", 3, 1 },
+ { "USED", 2, 1 },
+ { "REGION", 0, 2 },
+ { "HMA_TLB_DESC_0_H", 0x51030, 0 },
+ { "HMA_TLB_DESC_0_L", 0x51034, 0 },
+ { "HMA_TLB_DESC_1_H", 0x51038, 0 },
+ { "HMA_TLB_DESC_1_L", 0x5103c, 0 },
+ { "HMA_TLB_DESC_2_H", 0x51040, 0 },
+ { "HMA_TLB_DESC_2_L", 0x51044, 0 },
+ { "HMA_TLB_DESC_3_H", 0x51048, 0 },
+ { "HMA_TLB_DESC_3_L", 0x5104c, 0 },
+ { "HMA_TLB_DESC_4_H", 0x51050, 0 },
+ { "HMA_TLB_DESC_4_L", 0x51054, 0 },
+ { "HMA_TLB_DESC_5_H", 0x51058, 0 },
+ { "HMA_TLB_DESC_5_L", 0x5105c, 0 },
+ { "HMA_TLB_DESC_6_H", 0x51060, 0 },
+ { "HMA_TLB_DESC_6_L", 0x51064, 0 },
+ { "HMA_TLB_DESC_7_H", 0x51068, 0 },
+ { "HMA_TLB_DESC_7_L", 0x5106c, 0 },
+ { "HMA_REG0_MIN", 0x51070, 0 },
+ { "ADDR0_MIN", 12, 20 },
+ { "HMA_REG0_MAX", 0x51074, 0 },
+ { "ADDR0_MAX", 12, 20 },
+ { "HMA_REG0_MASK", 0x51078, 0 },
+ { "PAGE_SIZE0", 12, 20 },
+ { "HMA_REG0_BASE", 0x5107c, 0 },
+ { "HMA_REG1_MIN", 0x51080, 0 },
+ { "ADDR1_MIN", 12, 20 },
+ { "HMA_REG1_MAX", 0x51084, 0 },
+ { "ADDR1_MAX", 12, 20 },
+ { "HMA_REG1_MASK", 0x51088, 0 },
+ { "PAGE_SIZE1", 12, 20 },
+ { "HMA_REG1_BASE", 0x5108c, 0 },
+ { "HMA_REG2_MIN", 0x51090, 0 },
+ { "ADDR2_MIN", 12, 20 },
+ { "HMA_REG2_MAX", 0x51094, 0 },
+ { "ADDR2_MAX", 12, 20 },
+ { "HMA_REG2_MASK", 0x51098, 0 },
+ { "PAGE_SIZE2", 12, 20 },
+ { "HMA_REG2_BASE", 0x5109c, 0 },
+ { "HMA_REG3_MIN", 0x510a0, 0 },
+ { "ADDR3_MIN", 12, 20 },
+ { "HMA_REG3_MAX", 0x510a4, 0 },
+ { "ADDR3_MAX", 12, 20 },
+ { "HMA_REG3_MASK", 0x510a8, 0 },
+ { "PAGE_SIZE3", 12, 20 },
+ { "HMA_REG3_BASE", 0x510ac, 0 },
+ { "HMA_SW_SYNC", 0x510b0, 0 },
+ { "ENTER_SYNC", 31, 1 },
+ { "EXIT_SYNC", 30, 1 },
+ { "HMA_PAR_ENABLE", 0x51300, 0 },
+ { "HMA_INT_ENABLE", 0x51304, 0 },
+ { "IDTF_INT_ENABLE", 5, 1 },
+ { "OTF_INT_ENABLE", 4, 1 },
+ { "RTF_INT_ENABLE", 3, 1 },
+ { "PCIEMST_INT_ENABLE", 2, 1 },
+ { "MAMST_INT_ENABLE", 1, 1 },
+ { "PERR_INT_ENABLE", 0, 1 },
+ { "HMA_INT_CAUSE", 0x51308, 0 },
+ { "IDTF_INT_CAUSE", 5, 1 },
+ { "OTF_INT_CAUSE", 4, 1 },
+ { "RTF_INT_CAUSE", 3, 1 },
+ { "PCIEMST_INT_CAUSE", 2, 1 },
+ { "MAMST_INT_CAUSE", 1, 1 },
+ { "PERR_INT_CAUSE", 0, 1 },
+ { "HMA_MA_MST_ERR", 0x5130c, 0 },
+ { "HMA_RTF_ERR", 0x51310, 0 },
+ { "HMA_OTF_ERR", 0x51314, 0 },
+ { "HMA_IDTF_ERR", 0x51318, 0 },
+ { "HMA_EXIT_TF", 0x5131c, 0 },
+ { "TRIG", 31, 1 },
+ { "RTF", 30, 1 },
+ { "OTF", 29, 1 },
+ { "IDTF", 28, 1 },
+ { "HMA_LOCAL_DEBUG_CFG", 0x51320, 0 },
+ { "DEBUG_OR", 15, 1 },
+ { "DEBUG_HI", 14, 1 },
+ { "DEBUG_RPT", 13, 1 },
+ { "DEBUGPAGE", 10, 3 },
+ { "DEBUGSELH", 5, 5 },
+ { "DEBUGSELL", 0, 5 },
+ { "HMA_LOCAL_DEBUG_RPT", 0x51324, 0 },
+ { NULL }
+};
diff --git a/usr/src/pkg/manifests/driver-network-cxgbe.mf b/usr/src/pkg/manifests/driver-network-cxgbe.mf
index d36f01e36a..d948a8ccff 100644
--- a/usr/src/pkg/manifests/driver-network-cxgbe.mf
+++ b/usr/src/pkg/manifests/driver-network-cxgbe.mf
@@ -10,7 +10,7 @@
#
#
-# Copyright (c) 2016 by Chelsio Communications, Inc. All rights reserved.
+# Copyright (c) 2019 by Chelsio Communications, Inc. All rights reserved.
#
<include global_zone_only_component>
@@ -94,6 +94,21 @@ driver name=t4nex clone_perms="t4nex 0666 root sys" \
alias=pciex1425,549f \
alias=pciex1425,54a0 \
alias=pciex1425,54a1 \
+ alias=pciex1425,54a2 \
+ alias=pciex1425,54a3 \
+ alias=pciex1425,54a4 \
+ alias=pciex1425,54a5 \
+ alias=pciex1425,54a6 \
+ alias=pciex1425,54a7 \
+ alias=pciex1425,54a8 \
+ alias=pciex1425,54a9 \
+ alias=pciex1425,54aa \
+ alias=pciex1425,54ab \
+ alias=pciex1425,54ac \
+ alias=pciex1425,54ad \
+ alias=pciex1425,54ae \
+ alias=pciex1425,54af \
+ alias=pciex1425,54b0 \
alias=pciex1425,6400 \
alias=pciex1425,6401 \
alias=pciex1425,6402 \
@@ -110,7 +125,17 @@ driver name=t4nex clone_perms="t4nex 0666 root sys" \
alias=pciex1425,6414 \
alias=pciex1425,6415 \
alias=pciex1425,6480 \
- alias=pciex1425,6481
+ alias=pciex1425,6481 \
+ alias=pciex1425,6482 \
+ alias=pciex1425,6483 \
+ alias=pciex1425,6484 \
+ alias=pciex1425,6485 \
+ alias=pciex1425,6486 \
+ alias=pciex1425,6487 \
+ alias=pciex1425,6488 \
+ alias=pciex1425,6489 \
+ alias=pciex1425,648a \
+ alias=pciex1425,648b
file path=kernel/drv/$(ARCH64)/cxgbe group=sys
file path=kernel/drv/$(ARCH64)/t4nex group=sys
file path=usr/sbin/cxgbetool mode=0555
diff --git a/usr/src/uts/common/Makefile.files b/usr/src/uts/common/Makefile.files
index c7cfd2d364..73479d6743 100644
--- a/usr/src/uts/common/Makefile.files
+++ b/usr/src/uts/common/Makefile.files
@@ -1939,9 +1939,11 @@ CH_COM_OBJS = ch_mac.o ch_subr.o cspi.o espi.o ixf1010.o mc3.o mc4.o mc5.o \
# Chelsio Terminator 4 10G NIC nexus driver module
#
CXGBE_FW_OBJS = t4_fw.o t4_cfg.o t5_cfg.o t5_fw.o t6_cfg.o t6_fw.o
-CXGBE_COM_OBJS = t4_hw.o
+CXGBE_COM_OBJS = t4_hw.o common.o
CXGBE_NEX_OBJS = t4_nexus.o t4_sge.o t4_mac.o t4_ioctl.o shared.o \
- t4_l2t.o osdep.o
+ t4_l2t.o osdep.o cudbg_lib.o cudbg_wtp.o fastlz.o \
+ fastlz_api.o cudbg_common.o cudbg_flash_utils.o \
+ cudbg.o
#
# Chelsio Terminator 4 10G NIC driver module
diff --git a/usr/src/uts/common/io/cxgbe/common/common.c b/usr/src/uts/common/io/cxgbe/common/common.c
new file mode 100644
index 0000000000..ebb0a714ca
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/common/common.c
@@ -0,0 +1,124 @@
+#include "t4_hw.h"
+#include "t4_chip_type.h"
+#include "common.h"
+
+/* legacy compatibility routines */
+int t4_memory_rw(struct adapter *adap, int win,
+ int mtype, u32 maddr, u32 len,
+ void *hbuf, int dir)
+{
+ return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir);
+}
+
+/**
+ * hash_mac_addr - return the hash value of a MAC address
+ * @addr: the 48-bit Ethernet MAC address
+ *
+ * Hashes a MAC address according to the hash function used by hardware
+ * inexact (hash) address matching. The description in the hardware
+ * documentation for the MPS says this:
+ *
+ * The hash function takes the 48 bit MAC address and hashes
+ * it down to six bits. Bit zero of the hash is the XOR of
+ * bits 0, 6 ... 42 of the MAC address. The other hash bits
+ * are computed in a similar fashion ending with bit five of
+ * the hash as the XOR of bits 5, 11 ... 47 of the MAC address.
+ */
+int hash_mac_addr(const u8 *addr)
+{
+ u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
+ u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
+
+ a ^= b;
+ a ^= (a >> 12);
+ a ^= (a >> 6);
+ return a & 0x3f;
+}
+
+int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
+ int size, void *rpl)
+{
+ return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
+}
+
+int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
+ const void *cmd, int size, void *rpl,
+ int timeout)
+{
+ return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
+ timeout);
+}
+
+unsigned int dack_ticks_to_usec(const struct adapter *adap,
+ unsigned int ticks)
+{
+ return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
+}
+
+unsigned int us_to_core_ticks(const struct adapter *adap,
+ unsigned int us)
+{
+ return (us * adap->params.vpd.cclk) / 1000;
+}
+
+int is_offload(const struct adapter *adap)
+{
+ return adap->params.offload;
+}
+
+/*
+ * Given a pointer to a Firmware Mailbox Command Log and a log entry index,
+ * return a pointer to the specified entry.
+ */
+struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
+ unsigned int entry_idx)
+{
+ return &((struct mbox_cmd *)&(log)[1])[entry_idx];
+}
+
+int is_t4(enum chip_type chip)
+{
+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4);
+}
+
+int is_t5(enum chip_type chip)
+{
+
+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
+}
+
+int is_t6(enum chip_type chip)
+{
+ return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
+}
+
+int is_fpga(enum chip_type chip)
+{
+ return chip & CHELSIO_CHIP_FPGA;
+}
+
+/**
+ * t4_is_inserted_mod_type - is a plugged in Firmware Module Type
+ * @fw_mod_type: the Firmware Mofule Type
+ *
+ * Return whether the Firmware Module Type represents a real Transceiver
+ * Module/Cable Module Type which has been inserted.
+ */
+bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
+{
+ return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
+ fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
+ fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
+ fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
+}
+
+int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
+ int size, void *rpl)
+{
+ return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
+}
+
+unsigned int core_ticks_per_usec(const struct adapter *adap)
+{
+ return adap->params.vpd.cclk / 1000;
+}
diff --git a/usr/src/uts/common/io/cxgbe/common/common.h b/usr/src/uts/common/io/cxgbe/common/common.h
index e455f23b7a..c7de2c4ebf 100644
--- a/usr/src/uts/common/io/cxgbe/common/common.h
+++ b/usr/src/uts/common/io/cxgbe/common/common.h
@@ -12,7 +12,7 @@
/*
* This file is part of the Chelsio T4/T5/T6 Ethernet driver.
*
- * Copyright (C) 2005-2017 Chelsio Communications. All rights reserved.
+ * Copyright (C) 2005-2019 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
@@ -31,7 +31,7 @@
#define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \
F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \
- F_CPL_SWITCH | F_SGE | F_ULP_TX)
+ F_CPL_SWITCH | F_SGE | F_ULP_TX | F_SF)
#ifdef __cplusplus
extern "C" {
@@ -75,7 +75,7 @@ enum {
T5_REGMAP_SIZE = (332 * 1024),
};
-enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
+enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1, MEM_HMA };
enum {
MEMWIN0_APERTURE = 2048,
@@ -100,12 +100,14 @@ enum {
PAUSE_TX = 1 << 1,
PAUSE_AUTONEG = 1 << 2
};
+typedef unsigned char cc_pause_t;
enum {
FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
FEC_RS = 1 << 1, /* Reed-Solomon */
FEC_BASER_RS = 1 << 2, /* BaseR/Reed-Solomon */
};
+typedef unsigned char cc_fec_t;
enum {
ULP_T10DIF_ISCSI = 1 << 0,
@@ -271,6 +273,7 @@ struct tp_params {
unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
+ u32 filter_mask;
u32 ingress_config; /* cached TP_INGRESS_CONFIG */
/* cached TP_OUT_CONFIG compressed error vector
* and passing outer header info for encapsulated packets.
@@ -310,6 +313,22 @@ struct vpd_params {
u8 na[MACADDR_LEN + 1];
};
+/*
+ * Maximum resources provisioned for a PCI PF.
+ */
+struct pf_resources {
+ unsigned int nvi; /* N virtual interfaces */
+ unsigned int neq; /* N egress Qs */
+ unsigned int nethctrl; /* N egress ETH or CTRL Qs */
+ unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
+ unsigned int niq; /* N ingress Qs */
+ unsigned int tc; /* PCI-E traffic class */
+ unsigned int pmask; /* port access rights mask */
+ unsigned int nexactf; /* N exact MPS filters */
+ unsigned int r_caps; /* read capabilities */
+ unsigned int wx_caps; /* write/execute capabilities */
+};
+
struct pci_params {
uint16_t vendor_id;
uint16_t device_id;
@@ -342,6 +361,7 @@ struct adapter_params {
struct sge_params sge;
struct tp_params tp;
struct vpd_params vpd;
+ struct pf_resources pfres;
struct pci_params pci;
struct devlog_params devlog;
enum pcie_memwin drv_memwin;
@@ -386,6 +406,18 @@ struct adapter_params {
unsigned char ulp_crypto; /* Crypto support */
bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
bool filter2_wr_support; /* FW support for FILTER2_WR */
+ bool viid_smt_extn_support; /* FW returns vin and smt index? */
+ u8 fw_caps_support; /* 32-bit Port Capabilities */
+
+ /*
+ * MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
+ * used by the Port
+ */
+ u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
+ bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
+ bool write_cmpl_support; /* FW supports WRITE_CMPL */
+ /* FW supports adding source mac address to TCAM */
+ bool smac_add_support;
};
/*
@@ -420,15 +452,8 @@ struct mbox_cmd_log {
/* variable length mailbox command log starts here */
};
-/*
- * Given a pointer to a Firmware Mailbox Command Log and a log entry index,
- * return a pointer to the specified entry.
- */
-static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
- unsigned int entry_idx)
-{
- return &((struct mbox_cmd *)&(log)[1])[entry_idx];
-}
+struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
+ unsigned int entry_idx);
#include <t4fw_interface.h>
@@ -457,20 +482,45 @@ struct trace_params {
unsigned char port;
};
+/*
+ * Firmware Port Capabilities types.
+ */
+typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
+typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
+
+enum fw_caps {
+ FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
+ FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
+ FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
+};
+
struct link_config {
- unsigned short supported; /* link capabilities */
- unsigned short advertising; /* advertised capabilities */
- unsigned short lp_advertising; /* peer advertised capabilities */
- unsigned int requested_speed; /* speed user has requested */
- unsigned int speed; /* actual link speed */
- unsigned char requested_fc; /* flow control user has requested */
- unsigned char fc; /* actual link flow control */
- unsigned char auto_fec; /* Forward Error Correction: */
- unsigned char requested_fec; /* "automatic" (IEEE 802.3), */
- unsigned char fec; /* requested, and actual in use */
- unsigned char autoneg; /* autonegotiating? */
- unsigned char link_ok; /* link up? */
- unsigned char link_down_rc; /* link down reason */
+ fw_port_cap32_t pcaps; /* link capabilities */
+ fw_port_cap32_t def_acaps; /* default advertised capabilities */
+ fw_port_cap32_t acaps; /* advertised capabilities */
+ fw_port_cap32_t lpacaps; /* peer advertised capabilities */
+
+ fw_port_cap32_t speed_caps; /* speed(s) user has requested */
+ u32 speed; /* actual link speed (Mb/s) */
+
+ cc_pause_t requested_fc; /* flow control user has requested */
+ cc_pause_t fc; /* actual link flow control */
+
+ cc_fec_t requested_fec; /* Forward Error Correction: */
+ cc_fec_t fec; /* requested and actual in use */
+
+ unsigned char autoneg; /* autonegotiating? */
+
+ unsigned char link_ok; /* link up? */
+ unsigned char link_down_rc; /* link down reason */
+
+ /*
+ * State variables between Common Code and OS-dependent "contract"
+ * routines. These are used to communicate information and desired
+ * actions out-of-band.
+ */
+ bool new_module; /* ->OS Transceiver Module inserted */
+ bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */
};
/*
@@ -485,6 +535,7 @@ struct t4_vpd_hdr {
u8 vpdr_len[2];
};
+#if _KERNEL
#include "adapter.h"
#ifndef PCI_VENDOR_ID_CHELSIO
@@ -494,79 +545,12 @@ struct t4_vpd_hdr {
#define for_each_port(adapter, iter) \
for (iter = 0; iter < (adapter)->params.nports; ++iter)
-static inline int is_offload(const struct adapter *adap)
-{
- return adap->params.offload;
-}
-
-static inline int is_crypto(const struct adapter *adap)
-{
- return (adap->params.ulp_crypto & ULP_CRYPTO_LOOKASIDE);
-}
-
-static inline int is_hashfilter(const struct adapter *adap)
-{
- return adap->params.hash_filter;
-}
-
-static inline int is_bypass(const adapter_t *adap)
-{
- return adap->params.bypass;
-}
-
-static inline int is_bypass_device(int device)
-{
- /* XXX - this should be set based upon device capabilities */
- switch(device) {
-#ifdef CONFIG_CHELSIO_BYPASS
- case 0x440b:
- case 0x440c:
- return 1;
-#endif
-
- default:
- return 0;
- }
-}
-
-static inline int is_10gbt_device(int device)
-{
- /* XXX - this should be set based upon device capabilities */
- switch(device) {
- case 0x4409:
- case 0x4486:
- return 1;
-
- default:
- return 0;
- }
-}
-
-static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
-{
- return adap->params.vpd.cclk / 1000;
-}
-
-static inline unsigned int us_to_core_ticks(const struct adapter *adap,
- unsigned int us)
-{
- return (us * adap->params.vpd.cclk) / 1000;
-}
-
-static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
- unsigned int ticks)
-{
- /* add Core Clock / 2 to round ticks to nearest uS */
- return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
- adapter->params.vpd.cclk);
-}
-
-static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
- unsigned int ticks)
-{
- return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
-}
-
+int is_offload(const struct adapter *adap);
+unsigned int core_ticks_per_usec(const struct adapter *adap);
+unsigned int us_to_core_ticks(const struct adapter *adap,
+ unsigned int us);
+unsigned int dack_ticks_to_usec(const struct adapter *adap,
+ unsigned int ticks);
void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
void t4_record_mbox_marker(struct adapter *adapter,
@@ -576,26 +560,13 @@ int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
void *rpl, bool sleep_ok);
-static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
+int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
const void *cmd, int size, void *rpl,
- int timeout)
-{
- return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
- timeout);
-}
-
-static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
- int size, void *rpl)
-{
- return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
-}
-
-static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
- int size, void *rpl)
-{
- return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
-}
-
+ int timeout);
+int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
+ int size, void *rpl);
+int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
+ int size, void *rpl);
void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
unsigned int data_reg, u32 *vals, unsigned int nregs,
unsigned int start_idx);
@@ -612,8 +583,25 @@ void t4_intr_disable(struct adapter *adapter);
int t4_slow_intr_handler(struct adapter *adapter);
int t4_hash_mac_addr(const u8 *addr);
-int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
- struct link_config *lc);
+
+fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
+ struct link_config *lc);
+int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
+ unsigned int port, struct link_config *lc,
+ bool sleep_ok, int timeout);
+static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
+ unsigned int port, struct link_config *lc)
+{
+ return t4_link_l1cfg_core(adapter, mbox, port, lc,
+ true, FW_CMD_MAX_TIMEOUT);
+}
+static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
+ unsigned int port, struct link_config *lc)
+{
+ return t4_link_l1cfg_core(adapter, mbox, port, lc,
+ false, FW_CMD_MAX_TIMEOUT);
+}
+
int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
@@ -621,6 +609,7 @@ int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
int t4_seeprom_wp(struct adapter *adapter, int enable);
int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
+int t4_get_pfres(struct adapter *adapter);
int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
u32 *data, int byte_oriented);
int t4_write_flash(struct adapter *adapter, unsigned int addr,
@@ -638,6 +627,7 @@ int t5_fw_init_extern_mem(struct adapter *adap);
int t4_erase_sf(struct adapter *adapter);
#endif
int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
+int t4_read_bootcfg(struct adapter *adap, u8 *cfg_data, unsigned int size);
int t4_load_boot(struct adapter *adap, u8 *boot_data,
unsigned int boot_addr, unsigned int size);
int t4_flash_erase_sectors(struct adapter *adapter, int start, int end);
@@ -682,10 +672,13 @@ int t4_create_filter_info(const struct adapter *adapter,
int tos, int protocol, int ethertype,
int macmatch, int mpshittype, int fragmentation);
int t4_init_rss_mode(struct adapter *adap, int mbox);
+int t4_init_portinfo_viid(struct port_info *pi, int mbox,
+ int port, int pf, int vf, u8 mac[], bool alloc_vi);
int t4_init_portinfo(struct port_info *pi, int mbox,
int port, int pf, int vf, u8 mac[]);
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
-int t4_mirror_init(struct adapter *adap, int mbox, int pf, int vf);
+int t4_mirror_init(struct adapter *adap, int mbox, int pf, int vf,
+ bool enable_mirror);
void t4_fatal_err(struct adapter *adapter);
void t4_db_full(struct adapter *adapter);
void t4_db_dropped(struct adapter *adapter);
@@ -693,6 +686,7 @@ int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
int filter_index, int enable);
void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
int filter_index, int *enabled);
+unsigned int t4_chip_rss_size(struct adapter *adapter);
int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
int start, int n, const u16 *rspq, unsigned int nrspq);
int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
@@ -752,51 +746,12 @@ int t4_memory_rw_mtype(struct adapter *adap, int win,
int mtype, u32 maddr, u32 len,
void *hbuf, int dir);
-/* legacy compatibility routines */
-static inline int t4_memory_rw(struct adapter *adap, int win,
+int t4_memory_rw(struct adapter *adap, int win,
int mtype, u32 maddr, u32 len,
- void *hbuf, int dir)
-{
- return t4_memory_rw_mtype(adap, win, mtype, maddr, len, hbuf, dir);
-}
-
-static inline int t4_memory_read(struct adapter *adap, int mtype, u32 addr,
- u32 len, __be32 *buf)
-{
- return t4_memory_rw(adap, MEMWIN_NIC, mtype, addr, len, buf, T4_MEMORY_READ);
-}
-
-static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
- u32 len, __be32 *buf)
-{
- return t4_memory_rw(adap, MEMWIN_NIC, mtype, addr, len, buf, T4_MEMORY_WRITE);
-}
-
-/**
- * hash_mac_addr - return the hash value of a MAC address
- * @addr: the 48-bit Ethernet MAC address
- *
- * Hashes a MAC address according to the hash function used by hardware
- * inexact (hash) address matching. The description in the hardware
- * documentation for the MPS says this:
- *
- * The hash function takes the 48 bit MAC address and hashes
- * it down to six bits. Bit zero of the hash is the XOR of
- * bits 0, 6 ... 42 of the MAC address. The other hash bits
- * are computed in a similar fashion ending with bit five of
- * the hash as the XOR of bits 5, 11 ... 47 of the MAC address.
- */
-static inline int hash_mac_addr(const u8 *addr)
-{
- u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
- u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
-
- a ^= b;
- a ^= (a >> 12);
- a ^= (a >> 6);
- return a & 0x3f;
-}
+ void *hbuf, int dir);
+int hash_mac_addr(const u8 *addr);
+bool t4_is_inserted_mod_type(unsigned int fw_mod_type);
extern unsigned int t4_get_regs_len(struct adapter *adapter);
extern void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
@@ -876,10 +831,11 @@ int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
unsigned int port, unsigned int pf, unsigned int vf,
unsigned int nmac, u8 *mac, unsigned int *rss_size,
+ u8 *vivld, u8 *vin,
unsigned int portfunc, unsigned int idstype);
int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
- unsigned int *rss_size);
+ unsigned int *rss_size, u8 *vivld, u8 *vin);
int t4_free_vi(struct adapter *adap, unsigned int mbox,
unsigned int pf, unsigned int vf,
unsigned int viid);
@@ -892,15 +848,31 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid
int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
unsigned int viid, unsigned int naddr,
const u8 **addr, bool sleep_ok);
+int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
+ int idx, bool sleep_ok);
+int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
+ const u8 *addr, const u8 *mask, unsigned int idx,
+ u8 lookup_type, u8 port_id, bool sleep_ok);
int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
const u8 *addr, const u8 *mask, unsigned int idx,
- u8 lookup_type, bool sleep_ok);
+ u8 lookup_type, u8 port_id, bool sleep_ok);
+int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
+ const u8 *addr, const u8 *mask, unsigned int vni,
+ unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
+ bool sleep_ok);
int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
- int idx, const u8 *addr, bool persist, bool add_smt);
+ int idx, const u8 *addr, bool persist, u8 *smt_idx);
+int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
+ const u8 *addr, bool smac);
+int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
+ int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac);
int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
bool ucast, u64 vec, bool sleep_ok);
int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
+int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
+ struct port_info *pi,
+ bool rx_en, bool tx_en, bool dcb_en);
int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
bool rx_en, bool tx_en);
int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
@@ -909,6 +881,10 @@ int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
unsigned int mmd, unsigned int reg, unsigned int *valp);
int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
unsigned int mmd, unsigned int reg, unsigned int val);
+int t4_i2c_io(struct adapter *adap, unsigned int mbox,
+ int port, unsigned int devid,
+ unsigned int offset, unsigned int len,
+ u8 *buf, bool write);
int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
int port, unsigned int devid,
unsigned int offset, unsigned int len,
@@ -933,17 +909,30 @@ int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
enum ctxt_type ctype, u32 *data);
int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
u32 *data);
-int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
+int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
+int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
+ u16 *dbqtimers);
const char *t4_link_down_rc_str(unsigned char link_down_rc);
void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
int t4_update_port_info(struct port_info *pi);
+int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
+ unsigned int *speedp, unsigned int *mtup);
int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
int t4_sched_config(struct adapter *adapter, int type, int minmaxen);
-int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
- int rateunit, int ratemode, int channel, int class,
- int minrate, int maxrate, int weight, int pktsize);
+int t4_sched_params(struct adapter *adapter,
+ int channel, int cls,
+ int level, int mode, int type,
+ int rateunit, int ratemode,
+ int minrate, int maxrate, int weight,
+ int pktsize, int burstsize);
+int t4_read_sched_params(struct adapter *adapter,
+ int channel, int cls,
+ int *level, int *mode, int *type,
+ int *rateunit, int *ratemode,
+ int *minrate, int *maxrate, int *weight,
+ int *pktsize, int *burstsize);
int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
unsigned int pf, unsigned int vf,
unsigned int timeout, unsigned int action);
@@ -960,6 +949,11 @@ void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
u32 start_index, bool sleep_ok);
void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
u32 start_index, bool sleep_ok);
+int t4_configure_ringbb(struct adapter *adap);
+int t4_configure_add_smac(struct adapter *adap);
+int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
+ u16 vlan);
+#endif
#ifdef __cplusplus
}
#endif
diff --git a/usr/src/uts/common/io/cxgbe/common/t4_chip_type.h b/usr/src/uts/common/io/cxgbe/common/t4_chip_type.h
index 7c9ba3bb2d..4f7fb5a50a 100644
--- a/usr/src/uts/common/io/cxgbe/common/t4_chip_type.h
+++ b/usr/src/uts/common/io/cxgbe/common/t4_chip_type.h
@@ -12,7 +12,7 @@
/*
* This file is part of the Chelsio T4/T5/T6 Ethernet driver.
*
- * Copyright (C) 2003-2017 Chelsio Communications. All rights reserved.
+ * Copyright (C) 2003-2019 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
@@ -45,38 +45,6 @@
#define CHELSIO_T6_FPGA 0xc
/*
- * Translate a PCI Device ID to a base Chelsio Chip Version -- CHELSIO_T4,
- * CHELSIO_T5, etc. If it weren't for the screwed up numbering of the FPGAs
- * we could do this simply as DeviceID >> 12 (because we know the real
- * encoding oc CHELSIO_Tx identifiers). However, the FPGAs _do_ have weird
- * Device IDs so we need to do this translation here. Note that only constant
- * arithmetic and comparisons can be done here since this is being used to
- * initialize static tables, etc.
- *
- * Finally: This will of course need to be expanded as future chips are
- * developed.
- */
-static inline unsigned int
-CHELSIO_PCI_ID_CHIP_VERSION(unsigned int DeviceID)
-{
- switch (CHELSIO_PCI_ID_VER(DeviceID)) {
- case CHELSIO_T4:
- case CHELSIO_T4_FPGA:
- return CHELSIO_T4;
-
- case CHELSIO_T5:
- case CHELSIO_T5_FPGA:
- return CHELSIO_T5;
-
- case CHELSIO_T6:
- case CHELSIO_T6_FPGA:
- return CHELSIO_T6;
- }
-
- return 0;
-}
-
-/*
* Internally we code the Chelsio T4 Family "Chip Code" as a tuple:
*
* (Is FPGA, Chip Version, Chip Revision)
@@ -108,25 +76,9 @@ enum chip_type {
T6_LAST_REV = T6_A0,
};
-static inline int is_t4(enum chip_type chip)
-{
- return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4);
-}
-
-static inline int is_t5(enum chip_type chip)
-{
-
- return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
-}
-
-static inline int is_t6(enum chip_type chip)
-{
- return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
-}
-
-static inline int is_fpga(enum chip_type chip)
-{
- return chip & CHELSIO_CHIP_FPGA;
-}
+int is_t4(enum chip_type chip);
+int is_t5(enum chip_type chip);
+int is_t6(enum chip_type chip);
+int is_fpga(enum chip_type chip);
#endif /* __T4_CHIP_TYPE_H__ */
diff --git a/usr/src/uts/common/io/cxgbe/common/t4_hw.c b/usr/src/uts/common/io/cxgbe/common/t4_hw.c
index 1f31a53d14..ae88f36f15 100644
--- a/usr/src/uts/common/io/cxgbe/common/t4_hw.c
+++ b/usr/src/uts/common/io/cxgbe/common/t4_hw.c
@@ -12,7 +12,7 @@
/*
* This file is part of the Chelsio T4/T5/T6 Ethernet driver.
*
- * Copyright (C) 2003-2017 Chelsio Communications. All rights reserved.
+ * Copyright (C) 2003-2019 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
@@ -185,9 +185,11 @@ static void t4_report_fw_error(struct adapter *adap)
u32 pcie_fw;
pcie_fw = t4_read_reg(adap, A_PCIE_FW);
- if (pcie_fw & F_PCIE_FW_ERR)
+ if (pcie_fw & F_PCIE_FW_ERR) {
CH_ERR(adap, "Firmware reports adapter error: %s\n",
reason[G_PCIE_FW_EVAL(pcie_fw)]);
+ adap->flags &= ~FW_OK;
+ }
}
/*
@@ -930,7 +932,7 @@ int t4_memory_rw_addr(struct adapter *adap, int win, u32 addr,
* t4_memory_rw_mtype - read/write EDC 0, EDC 1 or MC via PCIE memory window
* @adap: the adapter
* @win: PCI-E Memory Window to use
- * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
+ * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
* @maddr: address within indicated memory type
* @len: amount of memory to transfer
* @hbuf: host memory buffer
@@ -950,9 +952,12 @@ int t4_memory_rw_mtype(struct adapter *adap, int win, int mtype, u32 maddr,
* MEM_EDC1 = 1
* MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
* MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
+ * MEM_HMA = 4
*/
edc_size = G_EDRAM0_SIZE(t4_read_reg(adap, A_MA_EDRAM0_BAR));
- if (mtype != MEM_MC1)
+ if (mtype == MEM_HMA) {
+ mtype_offset = 2 * (edc_size * 1024 * 1024);
+ } else if (mtype != MEM_MC1)
mtype_offset = (mtype * (edc_size * 1024 * 1024));
else {
mc_size = G_EXT_MEM0_SIZE(t4_read_reg(adap,
@@ -2340,7 +2345,7 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
0x1180, 0x1184,
0x1190, 0x1194,
0x11a0, 0x11a4,
- 0x11b0, 0x11b4,
+ 0x11b0, 0x11c4,
0x11fc, 0x1274,
0x1280, 0x133c,
0x1800, 0x18fc,
@@ -2396,7 +2401,7 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
0x7e4c, 0x7e78,
0x7e80, 0x7edc,
0x7ee8, 0x7efc,
- 0x8dc0, 0x8de4,
+ 0x8dc0, 0x8de0,
0x8df8, 0x8e04,
0x8e10, 0x8e84,
0x8ea0, 0x8f88,
@@ -2454,7 +2459,6 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
0x191d0, 0x191e8,
0x19238, 0x19290,
0x192a4, 0x192b0,
- 0x192bc, 0x192bc,
0x19348, 0x1934c,
0x193f8, 0x19418,
0x19420, 0x19428,
@@ -2472,7 +2476,7 @@ void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
0x19d00, 0x19d28,
0x19d50, 0x19d78,
0x19d94, 0x19d98,
- 0x19da0, 0x19dc8,
+ 0x19da0, 0x19de0,
0x19df0, 0x19e10,
0x19e50, 0x19e6c,
0x19ea0, 0x19ebc,
@@ -3117,10 +3121,8 @@ int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
max_poll = EEPROM_MAX_POLL;
do {
udelay(EEPROM_DELAY);
- ret = t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
- if (!ret && (stats_reg & 0x1))
- break;
- } while (--max_poll);
+ t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
+ } while ((stats_reg & 0x1) && --max_poll);
if (!max_poll)
return -ETIMEDOUT;
@@ -3353,6 +3355,59 @@ int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
return 0;
}
+/**
+ * t4_get_pfres - retrieve VF resource limits
+ * @adapter: the adapter
+ *
+ * Retrieves configured resource limits and capabilities for a physical
+ * function. The results are stored in @adapter->pfres.
+ */
+int t4_get_pfres(struct adapter *adapter)
+{
+ struct pf_resources *pfres = &adapter->params.pfres;
+ struct fw_pfvf_cmd cmd, rpl;
+ int v;
+ u32 word;
+
+ /*
+ * Execute PFVF Read command to get VF resource limits; bail out early
+ * with error on command failure.
+ */
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) |
+ F_FW_CMD_REQUEST |
+ F_FW_CMD_READ |
+ V_FW_PFVF_CMD_PFN(adapter->pf) |
+ V_FW_PFVF_CMD_VFN(0));
+ cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
+ v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
+ if (v != FW_SUCCESS)
+ return v;
+
+ /*
+ * Extract PF resource limits and return success.
+ */
+ word = be32_to_cpu(rpl.niqflint_niq);
+ pfres->niqflint = G_FW_PFVF_CMD_NIQFLINT(word);
+ pfres->niq = G_FW_PFVF_CMD_NIQ(word);
+
+ word = be32_to_cpu(rpl.type_to_neq);
+ pfres->neq = G_FW_PFVF_CMD_NEQ(word);
+ pfres->pmask = G_FW_PFVF_CMD_PMASK(word);
+
+ word = be32_to_cpu(rpl.tc_to_nexactf);
+ pfres->tc = G_FW_PFVF_CMD_TC(word);
+ pfres->nvi = G_FW_PFVF_CMD_NVI(word);
+ pfres->nexactf = G_FW_PFVF_CMD_NEXACTF(word);
+
+ word = be32_to_cpu(rpl.r_caps_to_nethctrl);
+ pfres->r_caps = G_FW_PFVF_CMD_R_CAPS(word);
+ pfres->wx_caps = G_FW_PFVF_CMD_WX_CAPS(word);
+ pfres->nethctrl = G_FW_PFVF_CMD_NETHCTRL(word);
+
+ return 0;
+}
+
/* serial flash and firmware constants and flash config file constants */
enum {
SF_ATTEMPTS = 10, /* max retries for SF operations */
@@ -4460,91 +4515,177 @@ void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
}
}
-#define ADVERT_MASK (V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED) | \
- FW_PORT_CAP_ANEG)
+/* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
+ * Capabilities which we control with separate controls -- see, for instance,
+ * Pause Frames and Forward Error Correction. In order to determine what the
+ * full set of Advertised Port Capabilities are, the base Advertised Port
+ * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
+ * Port Capabilities associated with those other controls. See
+ * t4_link_acaps() for how this is done.
+ */
+#define ADVERT_MASK (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) | \
+ FW_PORT_CAP32_ANEG)
+
+/**
+ * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
+ * @caps16: a 16-bit Port Capabilities value
+ *
+ * Returns the equivalent 32-bit Port Capabilities value.
+ */
+static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
+{
+ fw_port_cap32_t caps32 = 0;
+
+ #define CAP16_TO_CAP32(__cap) \
+ do { \
+ if (caps16 & FW_PORT_CAP_##__cap) \
+ caps32 |= FW_PORT_CAP32_##__cap; \
+ } while (0)
+
+ CAP16_TO_CAP32(SPEED_100M);
+ CAP16_TO_CAP32(SPEED_1G);
+ CAP16_TO_CAP32(SPEED_25G);
+ CAP16_TO_CAP32(SPEED_10G);
+ CAP16_TO_CAP32(SPEED_40G);
+ CAP16_TO_CAP32(SPEED_100G);
+ CAP16_TO_CAP32(FC_RX);
+ CAP16_TO_CAP32(FC_TX);
+ CAP16_TO_CAP32(ANEG);
+ CAP16_TO_CAP32(FORCE_PAUSE);
+ CAP16_TO_CAP32(MDIAUTO);
+ CAP16_TO_CAP32(MDISTRAIGHT);
+ CAP16_TO_CAP32(FEC_RS);
+ CAP16_TO_CAP32(FEC_BASER_RS);
+ CAP16_TO_CAP32(802_3_PAUSE);
+ CAP16_TO_CAP32(802_3_ASM_DIR);
+
+ #undef CAP16_TO_CAP32
+
+ return caps32;
+}
+
+/**
+ * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
+ * @caps32: a 32-bit Port Capabilities value
+ *
+ * Returns the equivalent 16-bit Port Capabilities value. Note that
+ * not all 32-bit Port Capabilities can be represented in the 16-bit
+ * Port Capabilities and some fields/values may not make it.
+ */
+static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
+{
+ fw_port_cap16_t caps16 = 0;
+
+ #define CAP32_TO_CAP16(__cap) \
+ do { \
+ if (caps32 & FW_PORT_CAP32_##__cap) \
+ caps16 |= FW_PORT_CAP_##__cap; \
+ } while (0)
+
+ CAP32_TO_CAP16(SPEED_100M);
+ CAP32_TO_CAP16(SPEED_1G);
+ CAP32_TO_CAP16(SPEED_10G);
+ CAP32_TO_CAP16(SPEED_25G);
+ CAP32_TO_CAP16(SPEED_40G);
+ CAP32_TO_CAP16(SPEED_100G);
+ CAP32_TO_CAP16(FC_RX);
+ CAP32_TO_CAP16(FC_TX);
+ CAP32_TO_CAP16(802_3_PAUSE);
+ CAP32_TO_CAP16(802_3_ASM_DIR);
+ CAP32_TO_CAP16(ANEG);
+ CAP32_TO_CAP16(FORCE_PAUSE);
+ CAP32_TO_CAP16(MDIAUTO);
+ CAP32_TO_CAP16(MDISTRAIGHT);
+ CAP32_TO_CAP16(FEC_RS);
+ CAP32_TO_CAP16(FEC_BASER_RS);
+
+ #undef CAP32_TO_CAP16
+
+ return caps16;
+}
/* Translate Firmware Port Capabilities Pause specification to Common Code */
-static inline unsigned int fwcap_to_cc_pause(unsigned int fw_pause)
+static inline cc_pause_t fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
{
- unsigned int cc_pause = 0;
+ cc_pause_t cc_pause = 0;
- if (fw_pause & FW_PORT_CAP_FC_RX)
+ if (fw_pause & FW_PORT_CAP32_FC_RX)
cc_pause |= PAUSE_RX;
- if (fw_pause & FW_PORT_CAP_FC_TX)
+ if (fw_pause & FW_PORT_CAP32_FC_TX)
cc_pause |= PAUSE_TX;
return cc_pause;
}
/* Translate Common Code Pause specification into Firmware Port Capabilities */
-static inline unsigned int cc_to_fwcap_pause(unsigned int cc_pause)
+static inline fw_port_cap32_t cc_to_fwcap_pause(cc_pause_t cc_pause)
{
- unsigned int fw_pause = 0;
+ fw_port_cap32_t fw_pause = 0;
+ /* Translate orthogonal RX/TX Pause Controls for L1 Configure
+ * commands, etc.
+ */
if (cc_pause & PAUSE_RX)
- fw_pause |= FW_PORT_CAP_FC_RX;
+ fw_pause |= FW_PORT_CAP32_FC_RX;
if (cc_pause & PAUSE_TX)
- fw_pause |= FW_PORT_CAP_FC_TX;
+ fw_pause |= FW_PORT_CAP32_FC_TX;
+ if (!(cc_pause & PAUSE_AUTONEG))
+ fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
return fw_pause;
}
/* Translate Firmware Forward Error Correction specification to Common Code */
-static inline unsigned int fwcap_to_cc_fec(unsigned int fw_fec)
+static inline cc_fec_t fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
{
- unsigned int cc_fec = 0;
+ cc_fec_t cc_fec = 0;
- if (fw_fec & FW_PORT_CAP_FEC_RS)
+ if (fw_fec & FW_PORT_CAP32_FEC_RS)
cc_fec |= FEC_RS;
- if (fw_fec & FW_PORT_CAP_FEC_BASER_RS)
+ if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
cc_fec |= FEC_BASER_RS;
return cc_fec;
}
/* Translate Common Code Forward Error Correction specification to Firmware */
-static inline unsigned int cc_to_fwcap_fec(unsigned int cc_fec)
+static inline fw_port_cap32_t cc_to_fwcap_fec(cc_fec_t cc_fec)
{
- unsigned int fw_fec = 0;
+ fw_port_cap32_t fw_fec = 0;
if (cc_fec & FEC_RS)
- fw_fec |= FW_PORT_CAP_FEC_RS;
+ fw_fec |= FW_PORT_CAP32_FEC_RS;
if (cc_fec & FEC_BASER_RS)
- fw_fec |= FW_PORT_CAP_FEC_BASER_RS;
+ fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
return fw_fec;
}
/**
- * t4_link_l1cfg - apply link configuration to MAC/PHY
- * @phy: the PHY to setup
- * @mac: the MAC to setup
- * @lc: the requested link configuration
+ * t4_link_acaps - compute Link Advertised Port Capabilities
+ * @adapter: the adapter
+ * @port: the Port ID
+ * @lc: the Port's Link Configuration
*
- * Set up a port's MAC and PHY according to a desired link configuration.
- * - If the PHY can auto-negotiate first decide what to advertise, then
- * enable/disable auto-negotiation as desired, and reset.
- * - If the PHY does not auto-negotiate just reset it.
- * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
- * otherwise do it later based on the outcome of auto-negotiation.
+ * Synthesize the Advertised Port Capabilities we'll be using based on
+ * the base Advertised Port Capabilities (which have been filtered by
+ * ADVERT_MASK) plus the individual controls for things like Pause
+ * Frames, Forward Error Correction, MDI, etc.
*/
-int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
- struct link_config *lc)
+fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
+ struct link_config *lc)
{
- struct fw_port_cmd c;
- unsigned int fw_mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
- unsigned int fw_fc, cc_fec, fw_fec;
+ unsigned int fw_mdi =
+ (V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
+ fw_port_cap32_t fw_fc, fw_fec, acaps;
+ cc_fec_t cc_fec;
- lc->link_ok = 0;
-
- /*
- * Convert driver coding of Pause Frame Flow Control settings into the
+ /* Convert driver coding of Pause Frame Flow Control settings into the
* Firmware's API.
*/
fw_fc = cc_to_fwcap_pause(lc->requested_fc);
- /*
- * Convert Common Code Forward Error Control settings into the
+ /* Convert Common Code Forward Error Control settings into the
* Firmware's API. If the current Requested FEC has "Automatic"
* (IEEE 802.3) specified, then we use whatever the Firmware
* sent us as part of it's IEEE 802.3-based interpratation of
@@ -4552,34 +4693,111 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
* use whatever is in the current Requested FEC settings.
*/
if (lc->requested_fec & FEC_AUTO)
- cc_fec = lc->auto_fec;
+ cc_fec = fwcap_to_cc_fec(lc->def_acaps);
else
cc_fec = lc->requested_fec;
fw_fec = cc_to_fwcap_fec(cc_fec);
- memset(&c, 0, sizeof(c));
- c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
- F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
- V_FW_PORT_CMD_PORTID(port));
- c.action_to_len16 =
- cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
- FW_LEN16(c));
-
- if (!(lc->supported & FW_PORT_CAP_ANEG)) {
- c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
- fw_fc | fw_fec);
+ /* Figure out what our Requested Port Capabilities are going to be.
+ * Note parallel structure in t4_handle_get_port_info() and
+ * init_link_config().
+ */
+ if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
+ acaps = lc->acaps | fw_fc | fw_fec;
lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
lc->fec = cc_fec;
} else if (lc->autoneg == AUTONEG_DISABLE) {
- c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed |
- fw_fc | fw_fec | fw_mdi);
+ acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
lc->fec = cc_fec;
} else
- c.u.l1cfg.rcap = cpu_to_be32(lc->advertising |
- fw_fc | fw_fec | fw_mdi);
+ acaps = lc->acaps | fw_fc | fw_fec | fw_mdi;
- return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
+ /* Some Requested Port Capabilities are trivially wrong if they exceed
+ * the Physical Port Capabilities. We can check that here and provide
+ * moderately useful feedback in the system log.
+ *
+ * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
+ * we need to exclude this from this check in order to maintain
+ * compatibility ...
+ */
+ if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
+ CH_ERR(adapter,
+ "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
+ acaps, lc->pcaps);
+ return 0;
+ }
+
+ return acaps;
+}
+
+/**
+ * t4_link_l1cfg_core - apply link configuration to MAC/PHY
+ * @adapter: the adapter
+ * @mbox: the Firmware Mailbox to use
+ * @port: the Port ID
+ * @lc: the Port's Link Configuration
+ * @sleep_ok: if true we may sleep while awaiting command completion
+ * @timeout: time to wait for command to finish before timing out
+ * (negative implies @sleep_ok=false)
+ *
+ * Set up a port's MAC and PHY according to a desired link configuration.
+ * - If the PHY can auto-negotiate first decide what to advertise, then
+ * enable/disable auto-negotiation as desired, and reset.
+ * - If the PHY does not auto-negotiate just reset it.
+ * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
+ * otherwise do it later based on the outcome of auto-negotiation.
+ */
+int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
+ unsigned int port, struct link_config *lc,
+ bool sleep_ok, int timeout)
+{
+ unsigned int fw_caps = adapter->params.fw_caps_support;
+ fw_port_cap32_t rcap;
+ struct fw_port_cmd cmd;
+ int ret;
+
+ /* Filter out nonsense.
+ */
+ if (!(lc->pcaps & FW_PORT_CAP32_ANEG) &&
+ lc->autoneg == AUTONEG_ENABLE)
+ return -EINVAL;
+
+ /* Compute our Requested Port Capabilities and send that on to the
+ * Firmware.
+ */
+ rcap = t4_link_acaps(adapter, port, lc);
+ if(!rcap)
+ return -EINVAL;
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
+ F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
+ V_FW_PORT_CMD_PORTID(port));
+ cmd.action_to_len16 =
+ cpu_to_be32(V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16
+ ? FW_PORT_ACTION_L1_CFG
+ : FW_PORT_ACTION_L1_CFG32) |
+ FW_LEN16(cmd));
+ if (fw_caps == FW_CAPS16)
+ cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
+ else
+ cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
+ ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
+ sleep_ok, timeout);
+
+ /* Unfortunately, even if the Requested Port Capabilities "fit" within
+ * the Physical Port Capabilities, some combinations of features may
+ * still not be legal. For example, 40Gb/s and Reed-Solomon Forward
+ * Error Correction. So if the Firmware rejects the L1 Configure
+ * request, flag that here.
+ */
+ if (ret) {
+ CH_ERR(adapter,
+ "Requested Port Capabilities %#x rejected, error %d\n",
+ rcap, -ret);
+ return ret;
+ }
+ return 0;
}
/**
@@ -4592,6 +4810,7 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
*/
int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
{
+ unsigned int fw_caps = adap->params.fw_caps_support;
struct fw_port_cmd c;
memset(&c, 0, sizeof(c));
@@ -4599,9 +4818,14 @@ int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
V_FW_PORT_CMD_PORTID(port));
c.action_to_len16 =
- cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
+ cpu_to_be32(V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16
+ ? FW_PORT_ACTION_L1_CFG
+ : FW_PORT_ACTION_L1_CFG32) |
FW_LEN16(c));
- c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
+ if (fw_caps == FW_CAPS16)
+ c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
+ else
+ c.u.l1cfg32.rcap32 = cpu_to_be32(FW_PORT_CAP32_ANEG);
return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
}
@@ -4794,7 +5018,7 @@ static void tp_intr_handler(struct adapter *adapter)
*/
static void sge_intr_handler(struct adapter *adapter)
{
- u64 v;
+ u32 v = 0, perr;
u32 err;
static const struct intr_info sge_intr_info[] = {
@@ -4842,13 +5066,22 @@ static void sge_intr_handler(struct adapter *adapter)
{ 0 }
};
- v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) |
- ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32);
- if (v) {
- CH_ALERT(adapter, "SGE parity error (%#llx)\n",
- (unsigned long long)v);
- t4_write_reg(adapter, A_SGE_INT_CAUSE1, v);
- t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32);
+ perr = t4_read_reg(adapter, A_SGE_INT_CAUSE1);
+ if (perr) {
+ v |= perr;
+ CH_ALERT(adapter, "SGE Cause1 Parity Error %#x\n", perr);
+ }
+ perr = t4_read_reg(adapter, A_SGE_INT_CAUSE2);
+ if (perr) {
+ v |= perr;
+ CH_ALERT(adapter, "SGE Cause2 Parity Error %#x\n", perr);
+ }
+ if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
+ perr = t4_read_reg(adapter, A_SGE_INT_CAUSE5);
+ if (perr) {
+ v |= perr;
+ CH_ALERT(adapter, "SGE Cause5 Parity Error %#x\n", perr);
+ }
}
v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info);
@@ -4890,6 +5123,7 @@ static void cim_intr_handler(struct adapter *adapter)
{ F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
{ F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
{ F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
+ { F_TIMER0INT, "CIM TIMER0 interrupt", -1, 1 },
{ 0 }
};
static const struct intr_info cim_upintr_info[] = {
@@ -4923,11 +5157,26 @@ static void cim_intr_handler(struct adapter *adapter)
{ F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
{ 0 }
};
+ u32 val, fw_err;
int fat;
- if (t4_read_reg(adapter, A_PCIE_FW) & F_PCIE_FW_ERR)
+ fw_err = t4_read_reg(adapter, A_PCIE_FW);
+ if (fw_err & F_PCIE_FW_ERR)
t4_report_fw_error(adapter);
+ /* When the Firmware detects an internal error which normally wouldn't
+ * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order
+ * to make sure the Host sees the Firmware Crash. So if we have a
+ * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0
+ * interrupt.
+ */
+ val = t4_read_reg(adapter, A_CIM_HOST_INT_CAUSE);
+ if (val & F_TIMER0INT)
+ if (!(fw_err & F_PCIE_FW_ERR) ||
+ (G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH))
+ t4_write_reg(adapter, A_CIM_HOST_INT_CAUSE,
+ F_TIMER0INT);
+
fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE,
cim_intr_info) +
t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE,
@@ -5052,6 +5301,8 @@ static void le_intr_handler(struct adapter *adap)
};
static struct intr_info t6_le_intr_info[] = {
+ /* log an error for HASHTBLMEMCRCERR and clear the bit */
+ { F_T6_HASHTBLMEMCRCERR, "LE hash table mem crc error", -1, 0 },
{ F_T6_LIPMISS, "LE LIP miss", -1, 0 },
{ F_T6_LIP0, "LE 0 LIP error", -1, 0 },
{ F_TCAMINTPERR, "LE parity error", -1, 1 },
@@ -5087,6 +5338,18 @@ static void mps_intr_handler(struct adapter *adapter)
{ F_FRMERR, "MPS Tx framing error", -1, 1 },
{ 0 }
};
+ static const struct intr_info t6_mps_tx_intr_info[] = {
+ { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 },
+ { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
+ { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error",
+ -1, 1 },
+ { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error",
+ -1, 1 },
+ /* MPS Tx Bubble is normal for T6 */
+ { F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
+ { F_FRMERR, "MPS Tx framing error", -1, 1 },
+ { 0 }
+ };
static const struct intr_info mps_trc_intr_info[] = {
{ V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 },
{ V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1,
@@ -5118,7 +5381,9 @@ static void mps_intr_handler(struct adapter *adapter)
fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE,
mps_rx_intr_info) +
t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE,
- mps_tx_intr_info) +
+ is_t6(adapter->params.chip)
+ ? t6_mps_tx_intr_info
+ : mps_tx_intr_info) +
t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE,
mps_trc_intr_info) +
t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM,
@@ -5278,18 +5543,61 @@ static void xgmac_intr_handler(struct adapter *adap, int port)
}
/*
+ * PL Parity Error interrupt handler.
+ */
+static void pl_perr_intr_handler(struct adapter *adap)
+{
+ static const struct intr_info pl_perr_info[] = {
+ { F_UART, "UART Parity Error", -1, },
+ { F_ULP_TX, "ULP TX Parity Error", -1 },
+ { F_SGE, "SGE Parity Error", -1 },
+ { F_HMA, "HMA Parity Error", -1 },
+ { F_CPL_SWITCH, "CPL Switch Parity Error", -1 },
+ { F_ULP_RX, "ULP RX Parity Error", -1 },
+ { F_PM_RX, "PM RX Parity Error", -1 },
+ { F_PM_TX, "PM TX Parity Error", -1 },
+ { F_MA, "MA Parity Error", -1 },
+ { F_TP, "TP Parity Error", -1 },
+ { F_LE, "LE Parity Error", -1 },
+ { F_EDC1, "EDC1 Parity Error", -1 },
+ { F_EDC0, "EDC0 Parity Error", -1 },
+ { F_MC, "MC Parity Error", -1 },
+ { F_PCIE, "PCIE Parity Error", -1 },
+ { F_PMU, "PMU Parity Error", -1 },
+ { F_XGMAC_KR1, "XGMAC_KR1 Parity Error", -1 },
+ { F_XGMAC_KR0, "XGMAC_KR0 Parity Error", -1 },
+ { F_XGMAC1, "XGMAC1 Parity Error", -1 },
+ { F_XGMAC0, "XGMAC0 Parity Error", -1 },
+ { F_SMB, "SMB Parity Error", -1 },
+ { F_SF, "SF Parity Error", -1 },
+ { F_PL, "PL Parity Error", -1 },
+ { F_NCSI, "NCSI Parity Error", -1 },
+ { F_MPS, "MPS Parity Error", -1 },
+ { F_MI, "MI Parity Error", -1 },
+ { F_DBG, "DBG Parity Error", -1 },
+ { F_I2CM, "I2CM Parity Error", -1 },
+ { F_CIM, "CIM Parity Error", -1 },
+ };
+
+ t4_handle_intr_status(adap, A_PL_PERR_CAUSE, pl_perr_info);
+ /* pl_intr_handler() will do the t4_fatal_err(adap) */
+}
+
+/*
* PL interrupt handler.
*/
static void pl_intr_handler(struct adapter *adap)
{
static const struct intr_info pl_intr_info[] = {
- { F_FATALPERR, "Fatal parity error", -1, 1 },
+ { F_FATALPERR, "Fatal parity error", -1, 1,
+ pl_perr_intr_handler },
{ F_PERRVFID, "PL VFID_MAP parity error", -1, 1 },
{ 0 }
};
static struct intr_info t5_pl_intr_info[] = {
- { F_FATALPERR, "Fatal parity error", -1, 1 },
+ { F_FATALPERR, "Fatal parity error", -1, 1,
+ pl_perr_intr_handler },
{ 0 }
};
@@ -5311,10 +5619,21 @@ static void pl_intr_handler(struct adapter *adap)
*/
int t4_slow_intr_handler(struct adapter *adapter)
{
- u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE);
+ /* There are rare cases where a PL_INT_CAUSE bit may end up getting
+ * set when the corresponding PL_INT_ENABLE bit isn't set. It's
+ * easiest just to mask that case here.
+ */
+ u32 raw_cause = t4_read_reg(adapter, A_PL_INT_CAUSE);
+ u32 enable = t4_read_reg(adapter, A_PL_INT_ENABLE);
+ u32 cause = raw_cause & enable;
if (!(cause & GLBL_INTR_MASK))
return 0;
+
+ /* Disable all the interrupt(bits) in PL_INT_ENABLE */
+ t4_write_reg(adapter, A_PL_INT_ENABLE, 0);
+ (void)t4_read_reg(adapter, A_PL_INT_ENABLE); /* flush */
+
if (cause & F_CIM)
cim_intr_handler(adapter);
if (cause & F_MPS)
@@ -5363,8 +5682,13 @@ int t4_slow_intr_handler(struct adapter *adapter)
ulptx_intr_handler(adapter);
/* Clear the interrupts just processed for which we are the master. */
- t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK);
- (void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */
+ t4_write_reg(adapter, A_PL_INT_CAUSE, raw_cause & GLBL_INTR_MASK);
+
+ /* re-enable the interrupts (bits that were disabled
+ * earlier in PL_INT_ENABLE)
+ */
+ t4_write_reg(adapter, A_PL_INT_ENABLE, enable);
+ (void)t4_read_reg(adapter, A_PL_INT_ENABLE); /* flush */
return 1;
}
@@ -5423,6 +5747,14 @@ void t4_intr_disable(struct adapter *adapter)
t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
}
+unsigned int t4_chip_rss_size(struct adapter *adap)
+{
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
+ return RSS_NENTRIES;
+ else
+ return T6_RSS_NENTRIES;
+}
+
/**
* t4_config_rss_range - configure a portion of the RSS mapping table
* @adapter: the adapter
@@ -5593,9 +5925,10 @@ static int rd_rss_row(struct adapter *adap, int row, u32 *val)
int t4_read_rss(struct adapter *adapter, u16 *map)
{
u32 val;
- int i, ret;
+ int i, ret, nentries;
- for (i = 0; i < RSS_NENTRIES / 2; ++i) {
+ nentries = t4_chip_rss_size(adapter);
+ for (i = 0; i < nentries / 2; ++i) {
ret = rd_rss_row(adapter, i, &val);
if (ret)
return ret;
@@ -6486,6 +6819,46 @@ void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
}
/**
+ * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
+ * @adapter: the adapter
+ * @pidx: the port index
+ *
+ * Compuytes and returns a bitmap indicating which MPS buffer groups are
+ * associated with the given Port. Bit i is set if buffer group i is
+ * used by the Port.
+ */
+static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
+ int pidx)
+{
+ unsigned int chip_version, nports;
+
+ chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
+ nports = 1 << G_NUMPORTS(t4_read_reg(adapter, A_MPS_CMN_CTL));
+
+ switch (chip_version) {
+ case CHELSIO_T4:
+ case CHELSIO_T5:
+ switch (nports) {
+ case 1: return 0xf;
+ case 2: return 3 << (2 * pidx);
+ case 4: return 1 << pidx;
+ }
+ break;
+
+ case CHELSIO_T6:
+ switch (nports) {
+ case 2: return 1 << (2 * pidx);
+ }
+ break;
+ }
+
+ CH_ERR(adapter, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
+ chip_version, nports);
+
+ return 0;
+}
+
+/**
* t4_get_mps_bg_map - return the buffer groups associated with a port
* @adapter: the adapter
* @pidx: the port index
@@ -6496,57 +6869,58 @@ void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
*/
unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
{
- unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
- unsigned int nports = 1 << G_NUMPORTS(t4_read_reg(adapter, A_MPS_CMN_CTL));
- u32 param, val;
- int ret;
+ u8 *mps_bg_map;
+ unsigned int nports;
+ nports = 1 << G_NUMPORTS(t4_read_reg(adapter, A_MPS_CMN_CTL));
if (pidx >= nports) {
CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n", pidx, nports);
return 0;
}
- /* FW version >= 1.16.34.0 can determine buffergroup map using
- * FW_PARAMS_PARAM_DEV_MPSBGMAP API. We will initially try to
- * use this API. If it fails, revert back to old hardcoded way.
- * The value obtained from FW is encoded in below format
+ /* If we've already retrieved/computed this, just return the result.
+ */
+ mps_bg_map = adapter->params.mps_bg_map;
+ if (mps_bg_map[pidx])
+ return mps_bg_map[pidx];
+
+ /* Newer Firmware can tell us what the MPS Buffer Group Map is.
+ * If we're talking to such Firmware, let it tell us. If the new
+ * API isn't supported, revert back to old hardcoded way. The value
+ * obtained from Firmware is encoded in below format:
+ *
* val = (( MPSBGMAP[Port 3] << 24 ) |
* ( MPSBGMAP[Port 2] << 16 ) |
* ( MPSBGMAP[Port 1] << 8 ) |
* ( MPSBGMAP[Port 0] << 0 ))
*/
if (adapter->flags & FW_OK) {
+ u32 param, val;
+ int ret;
+
param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MPSBGMAP));
ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
0, 1, &param, &val);
- if (!ret)
- return (val >> (8 * pidx)) & 0xff;
- }
+ if (!ret) {
+ int p;
- /* FW_PARAMS_PARAM_DEV_MPSBGMAP API has failed. Falling back to driver
- * to determine bgmap.
- */
- switch (chip_version) {
- case CHELSIO_T4:
- case CHELSIO_T5:
- switch (nports) {
- case 1: return 0xf;
- case 2: return 3 << (2 * pidx);
- case 4: return 1 << pidx;
- }
- break;
+ /* Store the BG Map for all of the Ports in order to
+ * avoid more calls to the Firmware in the future.
+ */
+ for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
+ mps_bg_map[p] = val & 0xff;
- case CHELSIO_T6:
- switch (nports) {
- case 2: return 1 << (2 * pidx);
+ return mps_bg_map[pidx];
}
- break;
}
- CH_ERR(adapter, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
- chip_version, nports);
- return 0;
+ /* Either we're not talking to the Firmware or we're dealing with
+ * older Firmware which doesn't support the new API to get the MPS
+ * Buffer Group Map. Fall back to computing it ourselves.
+ */
+ mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
+ return mps_bg_map[pidx];
}
/**
@@ -6613,6 +6987,7 @@ unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx)
case CHELSIO_T6:
switch (nports) {
+ case 1: return 1 << pidx;
case 2: return 1 << pidx;
}
break;
@@ -6652,6 +7027,7 @@ const char *t4_get_port_type_description(enum fw_port_type port_type)
"CR2_QSFP",
"SFP28",
"KR_SFP28",
+ "KR_XLAUI",
};
if (port_type < ARRAY_SIZE(port_type_description))
@@ -6725,10 +7101,8 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
- if (stat_ctl & F_COUNTPAUSESTATTX) {
- p->tx_frames -= p->tx_pause;
- p->tx_octets -= p->tx_pause * 64;
- }
+ if (stat_ctl & F_COUNTPAUSESTATTX)
+ p->tx_frames_64 -= p->tx_pause;
if (stat_ctl & F_COUNTPAUSEMCTX)
p->tx_mcast_frames -= p->tx_pause;
}
@@ -6762,10 +7136,8 @@ void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
- if (stat_ctl & F_COUNTPAUSESTATRX) {
- p->rx_frames -= p->rx_pause;
- p->rx_octets -= p->rx_pause * 64;
- }
+ if (stat_ctl & F_COUNTPAUSESTATRX)
+ p->rx_frames_64 -= p->rx_pause;
if (stat_ctl & F_COUNTPAUSEMCRX)
p->rx_mcast_frames -= p->rx_pause;
}
@@ -7111,14 +7483,16 @@ void t4_sge_decode_idma_state(struct adapter *adapter, int state)
* Issues a FW command through the given mailbox to flush the
* SGE context cache.
*/
-int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
+int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
{
int ret;
u32 ldst_addrspace;
struct fw_ldst_cmd c;
memset(&c, 0, sizeof(c));
- ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC);
+ ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ?
+ FW_LDST_ADDRSPC_SGE_EGRC :
+ FW_LDST_ADDRSPC_SGE_INGC);
c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
F_FW_CMD_REQUEST | F_FW_CMD_READ |
ldst_addrspace);
@@ -7130,6 +7504,47 @@ int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
}
/**
+ * t4_read_sge_dbqtimers - reag SGE Doorbell Queue Timer values
+ * @adap - the adapter
+ * @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
+ * @dbqtimers: SGE Doorbell Queue Timer table
+ *
+ * Reads the SGE Doorbell Queue Timer values into the provided table.
+ * Returns 0 on success (Firmware and Hardware support this feature),
+ * an error on failure.
+ */
+int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
+ u16 *dbqtimers)
+{
+ int ret, dbqtimerix;
+
+ ret = 0;
+ dbqtimerix = 0;
+ while (dbqtimerix < ndbqtimers) {
+ int nparams, param;
+ u32 params[7], vals[7];
+
+ nparams = ndbqtimers - dbqtimerix;
+ if (nparams > ARRAY_SIZE(params))
+ nparams = ARRAY_SIZE(params);
+
+ for (param = 0; param < nparams; param++)
+ params[param] =
+ (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
+ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DBQ_TIMER) |
+ V_FW_PARAMS_PARAM_Y(dbqtimerix + param));
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
+ nparams, params, vals);
+ if (ret)
+ break;
+
+ for (param = 0; param < nparams; param++)
+ dbqtimers[dbqtimerix++] = vals[param];
+ }
+ return ret;
+}
+
+/**
* t4_fw_hello - establish communication with FW
* @adap: the adapter
* @mbox: mailbox to use for the FW command
@@ -7464,6 +7879,17 @@ int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
goto out;
/*
+ * If there was a Firmware Configuration File staored in FLASH,
+ * there's a good chance that it won't be compatible with the new
+ * Firmware. In order to prevent difficult to diagnose adapter
+ * initialization issues, we clear out the Firmware Configuration File
+ * portion of the FLASH . The user will need to re-FLASH a new
+ * Firmware Configuration File which is compatible with the new
+ * Firmware if that's desired.
+ */
+ (void)t4_load_cfg(adap, NULL, 0);
+
+ /*
* Older versions of the firmware don't understand the new
* PCIE_FW.HALT flag and so won't know to perform a RESET when they
* restart. So for newly loaded older firmware we'll have to do the
@@ -7473,6 +7899,14 @@ int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
*/
reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
ret = t4_fw_restart(adap, mbox, reset);
+
+ /* Grab potentially new Firmware Device Log parameters so we can see
+ * how helthy the new Firmware is. It's okay to contact the new
+ * Firmware for these parameters even though, as far as it's
+ * concerned, we've never said "HELLO" to it ...
+ */
+ (void)t4_init_devlog_params(adap, 1);
+
out:
adap->flags |= FW_OK;
return ret;
@@ -7769,9 +8203,18 @@ int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
}
ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
- if (ret == 0)
- for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
- *val++ = be32_to_cpu(*p);
+
+ /*
+ * We always copy back the reults, even if there's an error. We'll
+ * get an error if any of the parameters was unknown to the Firmware,
+ * but there will be results for the others ... (Older Firmware
+ * stopped at the first unknown parameter; newer Firmware processes
+ * them all and flags the unknown parameters with a return value of
+ * ~0UL.)
+ */
+ for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
+ *val++ = be32_to_cpu(*p);
+
return ret;
}
@@ -7923,6 +8366,7 @@ int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
unsigned int port, unsigned int pf, unsigned int vf,
unsigned int nmac, u8 *mac, unsigned int *rss_size,
+ u8 *vivld, u8 *vin,
unsigned int portfunc, unsigned int idstype)
{
int ret;
@@ -7962,6 +8406,13 @@ int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
}
if (rss_size)
*rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
+
+ if (vivld)
+ *vivld = G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16));
+
+ if (vin)
+ *vin = G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16));
+
return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
}
@@ -7982,10 +8433,10 @@ int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
*/
int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
- unsigned int *rss_size)
+ unsigned int *rss_size, u8 *vivld, u8 *vin)
{
return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
- FW_VI_FUNC_ETH, 0);
+ vivld, vin, FW_VI_FUNC_ETH, 0);
}
@@ -8063,12 +8514,62 @@ int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
}
/**
+ * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
+ * @adap: the adapter
+ * @viid: the VI id
+ * @mac: the MAC address
+ * @mask: the mask
+ * @vni: the VNI id for the tunnel protocol
+ * @vni_mask: mask for the VNI id
+ * @dip_hit: to enable DIP match for the MPS entry
+ * @lookup_type: MAC address for inner (1) or outer (0) header
+ * @sleep_ok: call is allowed to sleep
+ *
+ * Allocates an MPS entry with specified MAC address and VNI value.
+ *
+ * Returns a negative error number or the allocated index for this mac.
+ */
+int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
+ const u8 *addr, const u8 *mask, unsigned int vni,
+ unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
+ bool sleep_ok)
+{
+ struct fw_vi_mac_cmd c;
+ struct fw_vi_mac_vni *p = c.u.exact_vni;
+ int ret = 0;
+ u32 val;
+
+ memset(&c, 0, sizeof(c));
+ c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
+ F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
+ V_FW_VI_MAC_CMD_VIID(viid));
+ val = V_FW_CMD_LEN16(1) |
+ V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI);
+ c.freemacs_to_len16 = cpu_to_be32(val);
+ p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
+ V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
+ memcpy(p->macaddr, addr, sizeof(p->macaddr));
+ memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
+
+ p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) |
+ V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) |
+ V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type));
+ p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask));
+
+ ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
+ if (ret == 0)
+ ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
+ return ret;
+}
+
+/**
* t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
* @adap: the adapter
* @viid: the VI id
* @mac: the MAC address
* @mask: the mask
* @idx: index at which to add this entry
+ * @port_id: the port index
* @lookup_type: MAC address for inner (1) or outer (0) header
* @sleep_ok: call is allowed to sleep
*
@@ -8078,7 +8579,7 @@ int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
*/
int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
const u8 *addr, const u8 *mask, unsigned int idx,
- u8 lookup_type, bool sleep_ok)
+ u8 lookup_type, u8 port_id, bool sleep_ok)
{
int ret = 0;
struct fw_vi_mac_cmd c;
@@ -8097,8 +8598,11 @@ int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx));
/* Lookup Type. Outer header: 0, Inner header: 1 */
- p->data0_pkd = cpu_to_be32(lookup_type << 10);
- p->data0m_pkd = cpu_to_be64(3 << 10); /* Lookup mask */
+ p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
+ V_DATAPORTNUM(port_id));
+ /* Lookup mask and port mask */
+ p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
+ V_DATAPORTNUM(M_DATAPORTNUM));
/* Copy the address and the mask */
memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
@@ -8208,6 +8712,95 @@ int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
}
/**
+ * t4_free_encap_mac_filt - frees MPS entry at given index
+ * @adap: the adapter
+ * @viid: the VI id
+ * @idx: index of MPS entry to be freed
+ * @sleep_ok: call is allowed to sleep
+ *
+ * Frees the MPS entry at supplied index
+ *
+ * Returns a negative error number or zero on success
+ */
+int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
+ int idx, bool sleep_ok)
+{
+ struct fw_vi_mac_exact *p;
+ struct fw_vi_mac_cmd c;
+ u8 addr[] = {0,0,0,0,0,0};
+ int ret = 0;
+ u32 exact;
+
+ memset(&c, 0, sizeof(c));
+ c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
+ F_FW_CMD_REQUEST |
+ F_FW_CMD_WRITE |
+ V_FW_CMD_EXEC(0) |
+ V_FW_VI_MAC_CMD_VIID(viid));
+ exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC);
+ c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
+ exact |
+ V_FW_CMD_LEN16(1));
+ p = c.u.exact;
+ p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
+ V_FW_VI_MAC_CMD_IDX(idx));
+ memcpy(p->macaddr, addr, sizeof(p->macaddr));
+
+ ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
+ return ret;
+}
+
+/**
+ * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
+ * @adap: the adapter
+ * @viid: the VI id
+ * @addr: the MAC address
+ * @mask: the mask
+ * @idx: index of the entry in mps tcam
+ * @lookup_type: MAC address for inner (1) or outer (0) header
+ * @port_id: the port index
+ * @sleep_ok: call is allowed to sleep
+ *
+ * Removes the mac entry at the specified index using raw mac interface.
+ *
+ * Returns a negative error number on failure.
+ */
+int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
+ const u8 *addr, const u8 *mask, unsigned int idx,
+ u8 lookup_type, u8 port_id, bool sleep_ok)
+{
+ struct fw_vi_mac_cmd c;
+ struct fw_vi_mac_raw *p = &c.u.raw;
+ u32 raw;
+
+ memset(&c, 0, sizeof(c));
+ c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
+ F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
+ V_FW_CMD_EXEC(0) |
+ V_FW_VI_MAC_CMD_VIID(viid));
+ raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
+ c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
+ raw |
+ V_FW_CMD_LEN16(1));
+
+ p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) |
+ FW_VI_MAC_ID_BASED_FREE);
+
+ /* Lookup Type. Outer header: 0, Inner header: 1 */
+ p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
+ V_DATAPORTNUM(port_id));
+ /* Lookup mask and port mask */
+ p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
+ V_DATAPORTNUM(M_DATAPORTNUM));
+
+ /* Copy the address and the mask */
+ memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
+ memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
+
+ return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
+}
+
+/**
* t4_free_mac_filt - frees exact-match filters of given MAC addresses
* @adap: the adapter
* @mbox: mailbox to use for the FW command
@@ -8305,34 +8898,10 @@ int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
* MAC value. Note that this index may differ from @idx.
*/
int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
- int idx, const u8 *addr, bool persist, bool add_smt)
+ int idx, const u8 *addr, bool persist, u8 *smt_idx)
{
- int ret, mode;
- struct fw_vi_mac_cmd c;
- struct fw_vi_mac_exact *p = c.u.exact;
- unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
-
- if (idx < 0) /* new allocation */
- idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
- mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
-
- memset(&c, 0, sizeof(c));
- c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
- F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
- V_FW_VI_MAC_CMD_VIID(viid));
- c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
- p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
- V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
- V_FW_VI_MAC_CMD_IDX(idx));
- memcpy(p->macaddr, addr, sizeof(p->macaddr));
-
- ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
- if (ret == 0) {
- ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
- if (ret >= max_mac_addr)
- ret = -ENOMEM;
- }
- return ret;
+ /* This will add this mac address to the destination TCAM region */
+ return t4_add_mac(adap, mbox, viid, idx, addr, persist, smt_idx, 0);
}
/**
@@ -8409,6 +8978,34 @@ int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
}
/**
+ * t4_enable_pi_params - enable/disable a Port's Virtual Interface
+ * @adap: the adapter
+ * @mbox: mailbox to use for the FW command
+ * @pi: the Port Information structure
+ * @rx_en: 1=enable Rx, 0=disable Rx
+ * @tx_en: 1=enable Tx, 0=disable Tx
+ * @dcb_en: 1=enable delivery of Data Center Bridging messages.
+ *
+ * Enables/disables a Port's Virtual Interface. Note that setting DCB
+ * Enable only makes sense when enabling a Virtual Interface ...
+ * If the Virtual Interface enable/disable operation is successful,
+ * we notify the OS-specific code of a potential Link Status change
+ * via the OS Contract API t4_os_link_changed().
+ */
+int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
+ struct port_info *pi,
+ bool rx_en, bool tx_en, bool dcb_en)
+{
+ int ret = t4_enable_vi_params(adap, mbox, pi->viid,
+ rx_en, tx_en, dcb_en);
+ if (ret)
+ return ret;
+ t4_os_link_changed(adap, pi->port_id,
+ rx_en && tx_en && pi->link_cfg.link_ok);
+ return 0;
+}
+
+/**
* t4_identify_port - identify a VI's port by blinking its LED
* @adap: the adapter
* @mbox: mailbox to use for the FW command
@@ -8596,28 +9193,99 @@ const char *t4_link_down_rc_str(unsigned char link_down_rc)
}
/**
- * Get the highest speed for the port from the advertised port capabilities.
- * It will be either the highest speed from the list of speeds or
- * whatever user has set using ethtool.
+ * Return the highest speed set in the port capabilities, in Mb/s.
+ */
+static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
+{
+ #define TEST_SPEED_RETURN(__caps_speed, __speed) \
+ do { \
+ if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
+ return __speed; \
+ } while (0)
+
+ TEST_SPEED_RETURN(400G, 400000);
+ TEST_SPEED_RETURN(200G, 200000);
+ TEST_SPEED_RETURN(100G, 100000);
+ TEST_SPEED_RETURN(50G, 50000);
+ TEST_SPEED_RETURN(40G, 40000);
+ TEST_SPEED_RETURN(25G, 25000);
+ TEST_SPEED_RETURN(10G, 10000);
+ TEST_SPEED_RETURN(1G, 1000);
+ TEST_SPEED_RETURN(100M, 100);
+
+ #undef TEST_SPEED_RETURN
+
+ return 0;
+}
+
+/**
+ * fwcap_to_fwspeed - return highest speed in Port Capabilities
+ * @acaps: advertised Port Capabilities
+ *
+ * Get the highest speed for the port from the advertised Port
+ * Capabilities. It will be either the highest speed from the list of
+ * speeds or whatever user has set using ethtool.
*/
-static inline unsigned int fwcap_to_fw_speed(unsigned int acaps)
+static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
{
- if (acaps & FW_PORT_CAP_SPEED_100G)
- return FW_PORT_CAP_SPEED_100G;
- if (acaps & FW_PORT_CAP_SPEED_40G)
- return FW_PORT_CAP_SPEED_40G;
- if (acaps & FW_PORT_CAP_SPEED_25G)
- return FW_PORT_CAP_SPEED_25G;
- if (acaps & FW_PORT_CAP_SPEED_10G)
- return FW_PORT_CAP_SPEED_10G;
- if (acaps & FW_PORT_CAP_SPEED_1G)
- return FW_PORT_CAP_SPEED_1G;
- if (acaps & FW_PORT_CAP_SPEED_100M)
- return FW_PORT_CAP_SPEED_100M;
+ #define TEST_SPEED_RETURN(__caps_speed) \
+ do { \
+ if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
+ return FW_PORT_CAP32_SPEED_##__caps_speed; \
+ } while (0)
+
+ TEST_SPEED_RETURN(400G);
+ TEST_SPEED_RETURN(200G);
+ TEST_SPEED_RETURN(100G);
+ TEST_SPEED_RETURN(50G);
+ TEST_SPEED_RETURN(40G);
+ TEST_SPEED_RETURN(25G);
+ TEST_SPEED_RETURN(10G);
+ TEST_SPEED_RETURN(1G);
+ TEST_SPEED_RETURN(100M);
+
+ #undef TEST_SPEED_RETURN
+
return 0;
}
/**
+ * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
+ * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
+ *
+ * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
+ * 32-bit Port Capabilities value.
+ */
+static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
+{
+ fw_port_cap32_t linkattr = 0;
+
+ /*
+ * Unfortunately the format of the Link Status in the old
+ * 16-bit Port Information message isn't the same as the
+ * 16-bit Port Capabilities bitfield used everywhere else ...
+ */
+ if (lstatus & F_FW_PORT_CMD_RXPAUSE)
+ linkattr |= FW_PORT_CAP32_FC_RX;
+ if (lstatus & F_FW_PORT_CMD_TXPAUSE)
+ linkattr |= FW_PORT_CAP32_FC_TX;
+ if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
+ linkattr |= FW_PORT_CAP32_SPEED_100M;
+ if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
+ linkattr |= FW_PORT_CAP32_SPEED_1G;
+ if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
+ linkattr |= FW_PORT_CAP32_SPEED_10G;
+ if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
+ linkattr |= FW_PORT_CAP32_SPEED_25G;
+ if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
+ linkattr |= FW_PORT_CAP32_SPEED_40G;
+ if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
+ linkattr |= FW_PORT_CAP32_SPEED_100G;
+
+ return linkattr;
+}
+
+/**
* t4_handle_get_port_info - process a FW reply message
* @pi: the port info
* @rpl: start of the FW message
@@ -8626,94 +9294,179 @@ static inline unsigned int fwcap_to_fw_speed(unsigned int acaps)
*/
void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
{
- const struct fw_port_cmd *p = (const void *)rpl;
- unsigned int acaps = be16_to_cpu(p->u.info.acap);
- struct adapter *adap = pi->adapter;
+ const struct fw_port_cmd *cmd = (const void *)rpl;
+ int action = G_FW_PORT_CMD_ACTION(be32_to_cpu(cmd->action_to_len16));
+ struct adapter *adapter = pi->adapter;
+ struct link_config *lc = &pi->link_cfg;
+ int link_ok, linkdnrc;
+ enum fw_port_type port_type;
+ enum fw_port_module_type mod_type;
+ unsigned int speed, fc, fec;
+ fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
+
+ /*
+ * Extract the various fields from the Port Information message.
+ */
+ switch (action) {
+ case FW_PORT_ACTION_GET_PORT_INFO: {
+ u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
+
+ link_ok = (lstatus & F_FW_PORT_CMD_LSTATUS) != 0;
+ linkdnrc = G_FW_PORT_CMD_LINKDNRC(lstatus);
+ port_type = G_FW_PORT_CMD_PTYPE(lstatus);
+ mod_type = G_FW_PORT_CMD_MODTYPE(lstatus);
+ pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
+ acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
+ lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
+ linkattr = lstatus_to_fwcap(lstatus);
+ break;
+ }
+
+ case FW_PORT_ACTION_GET_PORT_INFO32: {
+ u32 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
- /* link/module state change message */
- int speed = 0;
- unsigned int fc, fec;
- struct link_config *lc;
- u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
- int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
- u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
+ link_ok = (lstatus32 & F_FW_PORT_CMD_LSTATUS32) != 0;
+ linkdnrc = G_FW_PORT_CMD_LINKDNRC32(lstatus32);
+ port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);
+ mod_type = G_FW_PORT_CMD_MODTYPE32(lstatus32);
+ pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
+ acaps = be32_to_cpu(cmd->u.info32.acaps32);
+ lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
+ linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
+ break;
+ }
+
+ default:
+ CH_ERR(adapter, "Handle Port Information: Bad Command/Action %#x\n",
+ be32_to_cpu(cmd->action_to_len16));
+ return;
+ }
+
+ fec = fwcap_to_cc_fec(linkattr);
+ fc = fwcap_to_cc_pause(linkattr);
+ speed = fwcap_to_speed(linkattr);
/*
- * Unfortunately the format of the Link Status returned by the
- * Firmware isn't the same as the Firmware Port Capabilities bitfield
- * used everywhere else ...
- */
- fc = 0;
- if (stat & F_FW_PORT_CMD_RXPAUSE)
- fc |= PAUSE_RX;
- if (stat & F_FW_PORT_CMD_TXPAUSE)
- fc |= PAUSE_TX;
-
- fec = fwcap_to_cc_fec(acaps);
-
- if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
- speed = 100;
- else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
- speed = 1000;
- else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
- speed = 10000;
- else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
- speed = 25000;
- else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
- speed = 40000;
- else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
- speed = 100000;
-
- lc = &pi->link_cfg;
-
- if (mod != pi->mod_type) {
+ * Reset state for communicating new Transceiver Module status and
+ * whether the OS-dependent layer wants us to redo the current
+ * "sticky" L1 Configure Link Parameters.
+ */
+ lc->new_module = false;
+ lc->redo_l1cfg = false;
+
+ if (mod_type != pi->mod_type) {
+ /*
+ * With the newer SFP28 and QSFP28 Transceiver Module Types,
+ * various fundamental Port Capabilities which used to be
+ * immutable can now change radically. We can now have
+ * Speeds, Auto-Negotiation, Forward Error Correction, etc.
+ * all change based on what Transceiver Module is inserted.
+ * So we need to record the Physical "Port" Capabilities on
+ * every Transceiver Module change.
+ */
+ lc->pcaps = pcaps;
+
/*
* When a new Transceiver Module is inserted, the Firmware
- * will examine any Forward Error Correction parameters
- * present in the Transceiver Module i2c EPROM and determine
- * the supported and recommended FEC settings from those
- * based on IEEE 802.3 standards. We always record the
- * IEEE 802.3 recommended "automatic" settings.
+ * will examine its i2c EPROM to determine its type and
+ * general operating parameters including things like Forward
+ * Error Control, etc. Various IEEE 802.3 standards dictate
+ * how to interpret these i2c values to determine default
+ * "sutomatic" settings. We record these for future use when
+ * the user explicitly requests these standards-based values.
+ */
+ lc->def_acaps = acaps;
+
+ /*
+ * Some versions of the early T6 Firmware "cheated" when
+ * handling different Transceiver Modules by changing the
+ * underlaying Port Type reported to the Host Drivers. As
+ * such we need to capture whatever Port Type the Firmware
+ * sends us and record it in case it's different from what we
+ * were told earlier. Unfortunately, since Firmware is
+ * forever, we'll need to keep this code here forever, but in
+ * later T6 Firmware it should just be an assignment of the
+ * same value already recorded.
+ */
+ pi->port_type = port_type;
+
+ /*
+ * Record new Module Type information.
+ */
+ pi->mod_type = mod_type;
+
+ /*
+ * Let the OS-dependent layer know if we have a new
+ * Transceiver Module inserted.
*/
- lc->auto_fec = fec;
+ lc->new_module = t4_is_inserted_mod_type(mod_type);
- pi->mod_type = mod;
- t4_os_portmod_changed(adap, pi->port_id);
+ t4_os_portmod_changed(adapter, pi->port_id);
}
if (link_ok != lc->link_ok || speed != lc->speed ||
fc != lc->fc || fec != lc->fec) { /* something changed */
if (!link_ok && lc->link_ok) {
- unsigned char rc = G_FW_PORT_CMD_LINKDNRC(stat);
-
- lc->link_down_rc = rc;
- CH_WARN_RATELIMIT(adap,
+ lc->link_down_rc = linkdnrc;
+ CH_WARN_RATELIMIT(adapter,
"Port %d link down, reason: %s\n",
- pi->tx_chan, t4_link_down_rc_str(rc));
+ pi->tx_chan, t4_link_down_rc_str(linkdnrc));
}
lc->link_ok = link_ok;
lc->speed = speed;
lc->fc = fc;
lc->fec = fec;
- lc->supported = be16_to_cpu(p->u.info.pcap);
- lc->lp_advertising = be16_to_cpu(p->u.info.lpacap);
- lc->advertising = be16_to_cpu(p->u.info.acap) & ADVERT_MASK;
+ lc->lpacaps = lpacaps;
+ lc->acaps = acaps & ADVERT_MASK;
- if (lc->advertising & FW_PORT_CAP_ANEG) {
+ /* If we're not physically capable of Auto-Negotiation, note
+ * this as Auto-Negotiation disabled. Otherwise, we track
+ * what Auto-Negotiation settings we have. Note parallel
+ * structure in t4_link_l1cfg_core() and init_link_config().
+ */
+ if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
+ lc->autoneg = AUTONEG_DISABLE;
+ } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
lc->autoneg = AUTONEG_ENABLE;
} else {
/* When Autoneg is disabled, user needs to set
* single speed.
* Similar to cxgb4_ethtool.c: set_link_ksettings
*/
- lc->advertising = 0;
- lc->requested_speed = fwcap_to_fw_speed(acaps);
+ lc->acaps = 0;
+ lc->speed_caps = fwcap_to_fwspeed(acaps);
lc->autoneg = AUTONEG_DISABLE;
}
- t4_os_link_changed(adap, pi->port_id, link_ok);
+ t4_os_link_changed(adapter, pi->port_id, link_ok);
}
+
+ /*
+ * If we have a new Transceiver Module and the OS-dependent code has
+ * told us that it wants us to redo whatever "sticky" L1 Configuration
+ * Link Parameters are set, do that now.
+ */
+ if (lc->new_module && lc->redo_l1cfg) {
+ struct link_config old_lc;
+ int ret;
+
+ /*
+ * Save the current L1 Configuration and restore it if an
+ * error occurs. We probably should fix the l1_cfg*()
+ * routines not to change the link_config when an error
+ * occurs ...
+ */
+ old_lc = *lc;
+ ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
+ if (ret) {
+ *lc = old_lc;
+ CH_WARN(adapter,
+ "Attempt to update new Transceiver Module settings failed\n");
+ }
+ }
+ lc->new_module = false;
+ lc->redo_l1cfg = false;
}
/**
@@ -8724,17 +9477,20 @@ void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
* successful, we check to see if anything is different from what we
* last recorded and update things accordingly.
*/
- int t4_update_port_info(struct port_info *pi)
- {
+int t4_update_port_info(struct port_info *pi)
+{
+ unsigned int fw_caps = pi->adapter->params.fw_caps_support;
struct fw_port_cmd port_cmd;
int ret;
memset(&port_cmd, 0, sizeof port_cmd);
port_cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
F_FW_CMD_REQUEST | F_FW_CMD_READ |
- V_FW_PORT_CMD_PORTID(pi->tx_chan));
+ V_FW_PORT_CMD_PORTID(pi->lport));
port_cmd.action_to_len16 = cpu_to_be32(
- V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
+ V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16
+ ? FW_PORT_ACTION_GET_PORT_INFO
+ : FW_PORT_ACTION_GET_PORT_INFO32) |
FW_LEN16(port_cmd));
ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
&port_cmd, sizeof(port_cmd), &port_cmd);
@@ -8746,6 +9502,63 @@ void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
}
/**
+ * t4_get_link_params - retrieve basic link parameters for given port
+ * @pi: the port
+ * @link_okp: value return pointer for link up/down
+ * @speedp: value return pointer for speed (Mb/s)
+ * @mtup: value return pointer for mtu
+ *
+ * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
+ * and MTU for a specified port. A negative error is returned on
+ * failure; 0 on success.
+ */
+int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
+ unsigned int *speedp, unsigned int *mtup)
+{
+ unsigned int fw_caps = pi->adapter->params.fw_caps_support;
+ struct fw_port_cmd port_cmd;
+ unsigned int action, link_ok, mtu;
+ fw_port_cap32_t linkattr;
+ int ret;
+
+ memset(&port_cmd, 0, sizeof port_cmd);
+ port_cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
+ F_FW_CMD_REQUEST | F_FW_CMD_READ |
+ V_FW_PORT_CMD_PORTID(pi->tx_chan));
+ action = (fw_caps == FW_CAPS16
+ ? FW_PORT_ACTION_GET_PORT_INFO
+ : FW_PORT_ACTION_GET_PORT_INFO32);
+ port_cmd.action_to_len16 = cpu_to_be32(
+ V_FW_PORT_CMD_ACTION(action) |
+ FW_LEN16(port_cmd));
+ ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
+ &port_cmd, sizeof(port_cmd), &port_cmd);
+ if (ret)
+ return ret;
+
+ if (action == FW_PORT_ACTION_GET_PORT_INFO) {
+ u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
+
+ link_ok = !!(lstatus & F_FW_PORT_CMD_LSTATUS);
+ linkattr = lstatus_to_fwcap(lstatus);
+ mtu = be16_to_cpu(port_cmd.u.info.mtu);;
+ } else {
+ u32 lstatus32 = be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
+
+ link_ok = !!(lstatus32 & F_FW_PORT_CMD_LSTATUS32);
+ linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
+ mtu = G_FW_PORT_CMD_MTU32(
+ be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
+ }
+
+ *link_okp = link_ok;
+ *speedp = fwcap_to_speed(linkattr);
+ *mtup = mtu;
+
+ return 0;
+}
+
+/**
* t4_handle_fw_rpl - process a FW reply message
* @adap: the adapter
* @rpl: start of the FW message
@@ -8766,14 +9579,16 @@ int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
unsigned int action =
G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
- if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
+ if (opcode == FW_PORT_CMD &&
+ (action == FW_PORT_ACTION_GET_PORT_INFO ||
+ action == FW_PORT_ACTION_GET_PORT_INFO32)) {
int i;
int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
struct port_info *pi = NULL;
for_each_port(adap, i) {
pi = adap2pinfo(adap, i);
- if (pi->tx_chan == chan)
+ if (pi->lport == chan)
break;
}
@@ -8816,12 +9631,13 @@ static void get_pci_mode(struct adapter *adapter,
* Initializes the SW state maintained for each link, including the link's
* capabilities and default speed/flow-control/autonegotiation settings.
*/
-static void init_link_config(struct link_config *lc, unsigned int pcaps,
- unsigned int acaps)
+static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
+ fw_port_cap32_t acaps)
{
- lc->supported = pcaps;
- lc->lp_advertising = 0;
- lc->requested_speed = 0;
+ lc->pcaps = pcaps;
+ lc->def_acaps = acaps;
+ lc->lpacaps = 0;
+ lc->speed_caps = 0;
lc->speed = 0;
lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
@@ -8829,17 +9645,24 @@ static void init_link_config(struct link_config *lc, unsigned int pcaps,
* For Forward Error Control, we default to whatever the Firmware
* tells us the Link is currently advertising.
*/
- lc->auto_fec = fwcap_to_cc_fec(acaps);
lc->requested_fec = FEC_AUTO;
- lc->fec = lc->auto_fec;
+ lc->fec = fwcap_to_cc_fec(lc->def_acaps);
- if (lc->supported & FW_PORT_CAP_ANEG) {
- lc->advertising = lc->supported & ADVERT_MASK;
+ /* If the Port is capable of Auto-Negtotiation, initialize it as
+ * "enabled" and copy over all of the Physical Port Capabilities
+ * to the Advertised Port Capabilities. Otherwise mark it as
+ * Auto-Negotiate disabled and select the highest supported speed
+ * for the link. Note parallel structure in t4_link_l1cfg_core()
+ * and t4_handle_get_port_info().
+ */
+ if (lc->pcaps & FW_PORT_CAP32_ANEG) {
+ lc->acaps = lc->pcaps & ADVERT_MASK;
lc->autoneg = AUTONEG_ENABLE;
lc->requested_fc |= PAUSE_AUTONEG;
} else {
- lc->advertising = 0;
+ lc->acaps = 0;
lc->autoneg = AUTONEG_DISABLE;
+ lc->speed_caps = fwcap_to_fwspeed(acaps);
}
}
@@ -8916,10 +9739,10 @@ int t4_get_flash_params(struct adapter *adapter)
}
/*
- * Decode Flash part size. The code below looks repetitive with
+ * Decode Flash part size. The code below looks repetative with
* common encodings, but that's not guaranteed in the JEDEC
- * specification for the Read JEDEC ID command. The only thing that
- * we're guaranteed by the JEDEC specification is where the
+ * specification for the Read JADEC ID command. The only thing that
+ * we're guaranteed by the JADEC specification is where the
* Manufacturer ID is in the returned result. After that each
* Manufacturer ~could~ encode things completely differently.
* Note, all Flash parts must have 64KB sectors.
@@ -9432,8 +10255,8 @@ int t4_init_sge_params(struct adapter *adapter)
*/
int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
{
- int chan;
- u32 v;
+ u32 param, val, v;
+ int chan, ret;
v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
adap->params.tp.tre = G_TIMERRESOLUTION(v);
@@ -9443,11 +10266,47 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
for (chan = 0; chan < NCHAN; chan++)
adap->params.tp.tx_modq[chan] = chan;
- /* Cache the adapter's Compressed Filter Mode and global Incress
+ /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
* Configuration.
*/
- t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
- A_TP_VLAN_PRI_MAP, sleep_ok);
+
+ param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
+ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
+ V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK));
+
+ /* Read current value */
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
+ &param, &val);
+ if (ret == 0) {
+ CH_INFO(adap,
+ "Current filter mode/mask 0x%x:0x%x\n",
+ G_FW_PARAMS_PARAM_FILTER_MODE(val),
+ G_FW_PARAMS_PARAM_FILTER_MASK(val));
+ adap->params.tp.vlan_pri_map = G_FW_PARAMS_PARAM_FILTER_MODE(val);
+ adap->params.tp.filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val);
+ } else {
+ CH_WARN(adap,
+ "Reading filter mode/mask not supported via fw api, "
+ "falling back to older indirect-reg-read \n");
+
+ /* Incase of older-fw (which doesn't expose the api
+ * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
+ * the fw api) combination, fall-back to older method of reading
+ * the filter mode from indirect-register
+ */
+ t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
+ A_TP_VLAN_PRI_MAP, sleep_ok);
+
+ /* With the older-fw and newer-driver combination we might run
+ * into an issue when user wants to use hash filter region but
+ * the filter_mask is zero, in this case filter_mask validation
+ * is tough. To avoid that we set the filter_mask same as filter
+ * mode, which will behave exactly as the older way of ignoring
+ * the filter mask validation.
+ */
+ adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
+ }
+
t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
A_TP_INGRESS_CONFIG, sleep_ok);
@@ -9477,13 +10336,6 @@ int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
F_MPSHITTYPE);
adap->params.tp.frag_shift = t4_filter_field_shift(adap,
F_FRAGMENTATION);
-
- /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
- * represents the presence of an Outer VLAN instead of a VNIC ID.
- */
- if ((adap->params.tp.ingress_config & F_VNIC) == 0)
- adap->params.tp.vnic_shift = -1;
-
return 0;
}
@@ -9698,25 +10550,45 @@ static int t4_init_portmirror(struct port_info *pi, int mbox,
{
struct adapter *adapter = pi->adapter;
int ret;
+ u8 vivld = 0, vin = 0;
- ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, NULL, NULL);
+ ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, NULL, NULL,
+ &vivld, &vin);
if (ret < 0)
return ret;
- CH_INFO(adapter, "Port %d Traffic Mirror PF = %u; VF = %u\n",
- port, G_FW_VIID_PFN(ret), G_FW_VIID_VIN(ret));
-
pi->viid_mirror = ret;
+
+ /* If fw supports returning the VIN as part of FW_VI_CMD,
+ * save the returned values.
+ */
+ if (adapter->params.viid_smt_extn_support) {
+ pi->vivld_mirror = vivld;
+ pi->vin_mirror = vin;
+ } else {
+ /* Retrieve the values from VIID */
+ pi->vivld_mirror = G_FW_VIID_VIVLD(pi->viid_mirror);
+ pi->vin_mirror = G_FW_VIID_VIN(pi->viid_mirror);
+ }
+
+ CH_INFO(pi->adapter, "Port %d Traffic Mirror PF = %u; VF = %u\n",
+ port, pf, pi->vin_mirror);
return 0;
}
-int t4_mirror_init(struct adapter *adap, int mbox, int pf, int vf)
+int t4_mirror_init(struct adapter *adap, int mbox, int pf, int vf,
+ bool enable_ringbb)
{
int ret, i, j = 0;
for_each_port(adap, i) {
struct port_info *pi = adap2pinfo(adap, i);
+ /* We want mirroring only on Port0 for ringbackbone
+ * configuration.
+ */
+ if (enable_ringbb && i)
+ break;
while ((adap->params.portvec & (1 << j)) == 0)
j++;
@@ -9729,58 +10601,144 @@ int t4_mirror_init(struct adapter *adap, int mbox, int pf, int vf)
}
/**
- * t4_init_portinfo - allocate a virtual interface and initialize port_info
+ * t4_init_portinfo_viid - allocate a virtual interface and initialize
+ * port_info
* @pi: the port_info
* @mbox: mailbox to use for the FW command
* @port: physical port associated with the VI
* @pf: the PF owning the VI
* @vf: the VF owning the VI
* @mac: the MAC address of the VI
+ * @alloc_vi: Indicator to alloc VI
*
* Allocates a virtual interface for the given physical port. If @mac is
* not %NULL it contains the MAC address of the VI as assigned by FW.
* @mac should be large enough to hold an Ethernet address.
* Returns < 0 on error.
*/
-int t4_init_portinfo(struct port_info *pi, int mbox,
- int port, int pf, int vf, u8 mac[])
+int t4_init_portinfo_viid(struct port_info *pi, int mbox,
+ int port, int pf, int vf, u8 mac[], bool alloc_vi)
{
- int ret;
- struct fw_port_cmd c;
+ struct adapter *adapter = pi->adapter;
+ unsigned int fw_caps = adapter->params.fw_caps_support;
+ struct fw_port_cmd cmd;
unsigned int rss_size;
+ enum fw_port_type port_type;
+ int mdio_addr;
+ fw_port_cap32_t pcaps, acaps;
+ int ret;
- memset(&c, 0, sizeof(c));
- c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
- F_FW_CMD_REQUEST | F_FW_CMD_READ |
- V_FW_PORT_CMD_PORTID(port));
- c.action_to_len16 = cpu_to_be32(
- V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
- FW_LEN16(c));
- ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
+ /*
+ * If we haven't yet determined whether we're talking to Firmware
+ * which knows the new 32-bit Port Capabilities, it's time to find
+ * out now. This will also tell new Firmware to send us Port Status
+ * Updates using the new 32-bit Port Capabilities version of the
+ * Port Information message.
+ */
+ if (fw_caps == FW_CAPS_UNKNOWN) {
+ u32 param, val;
+
+ param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) |
+ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
+ val = 1;
+ ret = t4_set_params(adapter, mbox, pf, vf, 1, &param, &val);
+ fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
+ adapter->params.fw_caps_support = fw_caps;
+ }
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
+ F_FW_CMD_REQUEST | F_FW_CMD_READ |
+ V_FW_PORT_CMD_PORTID(port));
+ cmd.action_to_len16 = cpu_to_be32(
+ V_FW_PORT_CMD_ACTION(fw_caps == FW_CAPS16
+ ? FW_PORT_ACTION_GET_PORT_INFO
+ : FW_PORT_ACTION_GET_PORT_INFO32) |
+ FW_LEN16(cmd));
+ ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
if (ret)
return ret;
- ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
- if (ret < 0)
- return ret;
+ /*
+ * Extract the various fields from the Port Information message.
+ */
+ if (fw_caps == FW_CAPS16) {
+ u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
+
+ port_type = G_FW_PORT_CMD_PTYPE(lstatus);
+ mdio_addr = ((lstatus & F_FW_PORT_CMD_MDIOCAP)
+ ? G_FW_PORT_CMD_MDIOADDR(lstatus)
+ : -1);
+ pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
+ acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
+ } else {
+ u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
+
+ port_type = G_FW_PORT_CMD_PORTTYPE32(lstatus32);
+ mdio_addr = ((lstatus32 & F_FW_PORT_CMD_MDIOCAP32)
+ ? G_FW_PORT_CMD_MDIOADDR32(lstatus32)
+ : -1);
+ pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
+ acaps = be32_to_cpu(cmd.u.info32.acaps32);
+ }
+
+ if (alloc_vi) {
+ u8 vivld = 0, vin = 0;
+
+ ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac,
+ &rss_size, &vivld, &vin);
+ if (ret < 0)
+ return ret;
+
+ pi->viid = ret;
+ pi->rss_size = rss_size;
+
+ /* If fw supports returning the VIN as part of FW_VI_CMD,
+ * save the returned values.
+ */
+ if (adapter->params.viid_smt_extn_support) {
+ pi->vivld = vivld;
+ pi->vin = vin;
+ } else {
+ /* Retrieve the values from VIID */
+ pi->vivld = G_FW_VIID_VIVLD(pi->viid);
+ pi->vin = G_FW_VIID_VIN(pi->viid);
+ }
+ }
- pi->viid = ret;
pi->tx_chan = port;
pi->lport = port;
- pi->rss_size = rss_size;
- pi->rx_chan = t4_get_tp_e2c_map(pi->adapter, port);
+ pi->rx_chan = port;
+ pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
- ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
- pi->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
- G_FW_PORT_CMD_MDIOADDR(ret) : -1;
- pi->port_type = G_FW_PORT_CMD_PTYPE(ret);
+ pi->port_type = port_type;
+ pi->mdio_addr = mdio_addr;
pi->mod_type = FW_PORT_MOD_TYPE_NA;
- init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap),
- be16_to_cpu(c.u.info.acap));
+ init_link_config(&pi->link_cfg, pcaps, acaps);
return 0;
}
+/**
+ * t4_init_portinfo - allocate a virtual interface and initialize port_info
+ * @pi: the port_info
+ * @mbox: mailbox to use for the FW command
+ * @port: physical port associated with the VI
+ * @pf: the PF owning the VI
+ * @vf: the VF owning the VI
+ * @mac: the MAC address of the VI
+ *
+ * Allocates a virtual interface for the given physical port. If @mac is
+ * not %NULL it contains the MAC address of the VI as assigned by FW.
+ * @mac should be large enough to hold an Ethernet address.
+ * Returns < 0 on error.
+ */
+int t4_init_portinfo(struct port_info *pi, int mbox,
+ int port, int pf, int vf, u8 mac[])
+{
+ return t4_init_portinfo_viid(pi, mbox, port, pf, vf, mac, true);
+}
+
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
{
u8 addr[6];
@@ -10030,15 +10988,15 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
if (ret)
break;
- /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */
- idx = (idx + 1) & M_UPDBGLARDPTR;
- /*
- * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
+ /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
* identify the 32-bit portion of the full 312-bit data
*/
- if (is_t6(adap->params.chip))
- while ((idx & 0xf) > 9)
- idx = (idx + 1) % M_UPDBGLARDPTR;
+ if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
+ idx = (idx & 0xff0) + 0x10;
+ else
+ idx++;
+ /* address can't exceed 0xfff */
+ idx &= M_UPDBGLARDPTR;
}
restart:
if (cfg & F_UPDBGLAEN) {
@@ -10789,6 +11747,49 @@ out:
}
/**
+ * t4_read_bootcfg - read the current (boot)OptionROM configuration from FLASH
+ * @adap: the adapter
+ * @cfg_data: where to store the read OptionROM configuration data
+ *
+ * Read the current OptionROM configuration from FLASH and write to the
+ * buffer @cfg_data supplied.
+ */
+int t4_read_bootcfg(struct adapter *adap, u8 *cfg_data, unsigned int size)
+{
+ u32 *ptr = (u32 *)cfg_data;
+ int i, n, cfg_addr;
+ int ret = 0;
+
+ if (size > FLASH_BOOTCFG_MAX_SIZE) {
+ CH_ERR(adap, "bootcfg file too big, max is %u bytes\n",
+ FLASH_BOOTCFG_MAX_SIZE);
+ return -EINVAL;
+ }
+
+ cfg_addr = t4_flash_bootcfg_addr(adap);
+ if (cfg_addr < 0)
+ return cfg_addr;
+
+ size = size / sizeof (u32);
+ for (i = 0; i < size; i += SF_PAGE_SIZE) {
+ if ( (size - i) < SF_PAGE_SIZE)
+ n = size - i;
+ else
+ n = SF_PAGE_SIZE;
+
+ ret = t4_read_flash(adap, cfg_addr, n, ptr, 0);
+ if (ret)
+ goto out;
+
+ cfg_addr += (n*4);
+ ptr += n;
+ }
+
+out:
+ return ret;
+}
+
+/**
* t4_set_filter_mode - configure the optional components of filter tuples
* @adap: the adapter
* @mode_map: a bitmap selcting which optional filter components to enable
@@ -10851,88 +11852,81 @@ void t4_clr_port_stats(struct adapter *adap, int idx)
}
/**
- * t4_i2c_rd - read I2C data from adapter
+ * t4_i2c_io - read/write I2C data from adapter
* @adap: the adapter
* @port: Port number if per-port device; <0 if not
* @devid: per-port device ID or absolute device ID
* @offset: byte offset into device I2C space
* @len: byte length of I2C space data
- * @buf: buffer in which to return I2C data
- *
- * Reads the I2C data from the indicated device and location.
+ * @buf: buffer in which to return I2C data for read
+ * buffer which holds the I2C data for write
+ * @write: if true, do a write; else do a read
+ * Reads/Writes the I2C data from/to the indicated device and location.
*/
-int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
+int t4_i2c_io(struct adapter *adap, unsigned int mbox,
int port, unsigned int devid,
unsigned int offset, unsigned int len,
- u8 *buf)
+ u8 *buf, bool write)
{
- u32 ldst_addrspace;
- struct fw_ldst_cmd ldst;
- int ret;
+ struct fw_ldst_cmd ldst_cmd, ldst_rpl;
+ unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
+ int ret = 0;
- if (port >= 4 ||
- devid >= 256 ||
- offset >= 256 ||
- len > sizeof ldst.u.i2c.data)
+ if (len > I2C_PAGE_SIZE)
return -EINVAL;
- memset(&ldst, 0, sizeof ldst);
- ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
- ldst.op_to_addrspace =
+ /* Dont allow reads that spans multiple pages */
+ if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
+ return -EINVAL;
+
+ memset(&ldst_cmd, 0, sizeof(ldst_cmd));
+ ldst_cmd.op_to_addrspace =
cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
F_FW_CMD_REQUEST |
- F_FW_CMD_READ |
- ldst_addrspace);
- ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
- ldst.u.i2c.pid = (port < 0 ? 0xff : port);
- ldst.u.i2c.did = devid;
- ldst.u.i2c.boffset = offset;
- ldst.u.i2c.blen = len;
- ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
- if (!ret)
- memcpy(buf, ldst.u.i2c.data, len);
+ (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) |
+ V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C));
+ ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
+ ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
+ ldst_cmd.u.i2c.did = devid;
+
+ while (len > 0) {
+ unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
+
+ ldst_cmd.u.i2c.boffset = offset;
+ ldst_cmd.u.i2c.blen = i2c_len;
+
+ if (write)
+ memcpy(ldst_cmd.u.i2c.data, buf, i2c_len);
+
+ ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
+ write ? NULL : &ldst_rpl);
+ if (ret)
+ break;
+
+ if (!write)
+ memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
+ offset += i2c_len;
+ buf += i2c_len;
+ len -= i2c_len;
+ }
+
return ret;
}
-/**
- * t4_i2c_wr - write I2C data to adapter
- * @adap: the adapter
- * @port: Port number if per-port device; <0 if not
- * @devid: per-port device ID or absolute device ID
- * @offset: byte offset into device I2C space
- * @len: byte length of I2C space data
- * @buf: buffer containing new I2C data
- *
- * Write the I2C data to the indicated device and location.
- */
-int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
+int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
int port, unsigned int devid,
unsigned int offset, unsigned int len,
u8 *buf)
{
- u32 ldst_addrspace;
- struct fw_ldst_cmd ldst;
-
- if (port >= 4 ||
- devid >= 256 ||
- offset >= 256 ||
- len > sizeof ldst.u.i2c.data)
- return -EINVAL;
+ return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false);
+}
- memset(&ldst, 0, sizeof ldst);
- ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
- ldst.op_to_addrspace =
- cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
- F_FW_CMD_REQUEST |
- F_FW_CMD_WRITE |
- ldst_addrspace);
- ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
- ldst.u.i2c.pid = (port < 0 ? 0xff : port);
- ldst.u.i2c.did = devid;
- ldst.u.i2c.boffset = offset;
- ldst.u.i2c.blen = len;
- memcpy(ldst.u.i2c.data, buf, len);
- return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
+int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
+ int port, unsigned int devid,
+ unsigned int offset, unsigned int len,
+ u8 *buf)
+{
+ return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true);
}
/**
@@ -11020,9 +12014,12 @@ int t4_sched_config(struct adapter *adapter, int type, int minmaxen)
NULL, 1);
}
-int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
- int rateunit, int ratemode, int channel, int class,
- int minrate, int maxrate, int weight, int pktsize)
+int t4_sched_params(struct adapter *adapter,
+ int channel, int cls,
+ int level, int mode, int type,
+ int rateunit, int ratemode,
+ int minrate, int maxrate, int weight,
+ int pktsize, int burstsize)
{
struct fw_sched_cmd cmd;
@@ -11037,18 +12034,58 @@ int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
cmd.u.params.level = level;
cmd.u.params.mode = mode;
cmd.u.params.ch = channel;
- cmd.u.params.cl = class;
+ cmd.u.params.cl = cls;
cmd.u.params.unit = rateunit;
cmd.u.params.rate = ratemode;
cmd.u.params.min = cpu_to_be32(minrate);
cmd.u.params.max = cpu_to_be32(maxrate);
cmd.u.params.weight = cpu_to_be16(weight);
cmd.u.params.pktsize = cpu_to_be16(pktsize);
+ cmd.u.params.burstsize = cpu_to_be16(burstsize);
return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
NULL, 1);
}
+int t4_read_sched_params(struct adapter *adapter,
+ int channel, int cls,
+ int *level, int *mode, int *type,
+ int *rateunit, int *ratemode,
+ int *minrate, int *maxrate, int *weight,
+ int *pktsize, int *burstsize)
+{
+ struct fw_sched_cmd cmd;
+ int ret = 0;
+
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
+ F_FW_CMD_REQUEST |
+ F_FW_CMD_READ);
+ cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
+ cmd.u.params.sc = FW_SCHED_SC_PARAMS;
+ cmd.u.params.ch = channel;
+ cmd.u.params.cl = cls;
+
+ ret = t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
+ &cmd, 1);
+ if (ret)
+ goto out;
+
+ *level = cmd.u.params.level;
+ *mode = cmd.u.params.mode;
+ *type = cmd.u.params.type;
+ *rateunit = cmd.u.params.unit;
+ *ratemode = cmd.u.params.rate;
+ *minrate = be32_to_cpu(cmd.u.params.min);
+ *maxrate = be32_to_cpu(cmd.u.params.max);
+ *weight = be16_to_cpu(cmd.u.params.weight);
+ *pktsize = be16_to_cpu(cmd.u.params.pktsize);
+ *burstsize = be16_to_cpu(cmd.u.params.burstsize);
+
+out:
+ return ret;
+}
+
/*
* t4_config_watchdog - configure (enable/disable) a watchdog timer
* @adapter: the adapter
@@ -11124,3 +12161,219 @@ int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
sizeof(devlog_cmd), &devlog_cmd);
}
+int t4_configure_add_smac(struct adapter *adap)
+{
+ unsigned int param, val;
+ int ret = 0;
+
+ adap->params.smac_add_support = 0;
+ param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
+ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC));
+ /* Query FW to check if FW supports adding source mac address
+ * to TCAM feature or not.
+ * If FW returns 1, driver can use this feature and driver need to send
+ * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to
+ * enable adding smac to TCAM.
+ */
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
+ if (ret)
+ return ret;
+
+ if (val == 1) {
+ ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
+ &param, &val);
+ if (!ret)
+ /* Firmware allows adding explicit TCAM entries.
+ * Save this internally.
+ */
+ adap->params.smac_add_support = 1;
+ }
+
+ return ret;
+}
+
+int t4_configure_ringbb(struct adapter *adap)
+{
+ unsigned int param, val;
+ int ret = 0;
+
+ param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
+ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE));
+ /* Query FW to check if FW supports ring switch feature or not.
+ * If FW returns 1, driver can use this feature and driver need to send
+ * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to
+ * enable the ring backbone configuration.
+ */
+ ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
+ if (ret < 0) {
+ CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n",
+ ret);
+ goto out;
+ }
+
+ if (val != 1) {
+ CH_ERR(adap, "FW doesnot support ringbackbone features\n");
+ goto out;
+ }
+
+ ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
+ if (ret < 0) {
+ CH_ERR(adap, "Could not set Ringbackbone, err= %d\n",
+ ret);
+ goto out;
+ }
+
+out:
+ return ret;
+}
+
+/*
+ * t4_set_vlan_acl - Set a VLAN id for the specified VF
+ * @adapter: the adapter
+ * @mbox: mailbox to use for the FW command
+ * @vf: one of the VFs instantiated by the specified PF
+ * @vlan: The vlanid to be set
+ *
+ */
+int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
+ u16 vlan)
+{
+ struct fw_acl_vlan_cmd vlan_cmd;
+ unsigned int enable;
+
+ enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0);
+ memset(&vlan_cmd, 0, sizeof(vlan_cmd));
+ vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) |
+ F_FW_CMD_REQUEST |
+ F_FW_CMD_WRITE |
+ F_FW_CMD_EXEC |
+ V_FW_ACL_VLAN_CMD_PFN(adap->pf) |
+ V_FW_ACL_VLAN_CMD_VFN(vf));
+ vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
+ /* Drop all packets that donot match vlan id */
+ vlan_cmd.dropnovlan_fm = (enable
+ ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN |
+ F_FW_ACL_VLAN_CMD_FM)
+ : 0);
+ if (enable != 0) {
+ vlan_cmd.nvlan = 1;
+ vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
+ }
+
+ return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
+}
+
+/**
+ * t4_del_mac - Removes the exact-match filter for a MAC address
+ * @adap: the adapter
+ * @mbox: mailbox to use for the FW command
+ * @viid: the VI id
+ * @addr: the MAC address value
+ * @smac: if true, delete from only the smac region of MPS
+ *
+ * Modifies an exact-match filter and sets it to the new MAC address if
+ * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
+ * latter case the address is added persistently if @persist is %true.
+ *
+ * Returns a negative error number or the index of the filter with the new
+ * MAC value. Note that this index may differ from @idx.
+ */
+int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
+ const u8 *addr, bool smac)
+{
+ int ret;
+ struct fw_vi_mac_cmd c;
+ struct fw_vi_mac_exact *p = c.u.exact;
+ unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
+
+ memset(&c, 0, sizeof(c));
+ c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
+ F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
+ V_FW_VI_MAC_CMD_VIID(viid));
+ c.freemacs_to_len16 = cpu_to_be32(
+ V_FW_CMD_LEN16(1) |
+ (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0));
+
+ memcpy(p->macaddr, addr, sizeof(p->macaddr));
+ p->valid_to_idx = cpu_to_be16(
+ F_FW_VI_MAC_CMD_VALID |
+ V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE));
+
+ ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
+ if (ret == 0) {
+ ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
+ if (ret < max_mac_addr)
+ return -ENOMEM;
+ }
+
+ return ret;
+}
+
+/**
+ * t4_add_mac - Adds an exact-match filter for a MAC address
+ * @adap: the adapter
+ * @mbox: mailbox to use for the FW command
+ * @viid: the VI id
+ * @idx: index of existing filter for old value of MAC address, or -1
+ * @addr: the new MAC address value
+ * @persist: whether a new MAC allocation should be persistent
+ * @add_smt: if true also add the address to the HW SMT
+ * @smac: if true, update only the smac region of MPS
+ *
+ * Modifies an exact-match filter and sets it to the new MAC address if
+ * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the
+ * latter case the address is added persistently if @persist is %true.
+ *
+ * Returns a negative error number or the index of the filter with the new
+ * MAC value. Note that this index may differ from @idx.
+ */
+int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
+ int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac)
+{
+ int ret, mode;
+ struct fw_vi_mac_cmd c;
+ struct fw_vi_mac_exact *p = c.u.exact;
+ unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
+
+ if (idx < 0) /* new allocation */
+ idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
+ mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
+
+ memset(&c, 0, sizeof(c));
+ c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
+ F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
+ V_FW_VI_MAC_CMD_VIID(viid));
+ c.freemacs_to_len16 = cpu_to_be32(
+ V_FW_CMD_LEN16(1) |
+ (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0));
+ p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
+ V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
+ V_FW_VI_MAC_CMD_IDX(idx));
+ memcpy(p->macaddr, addr, sizeof(p->macaddr));
+
+ ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
+ if (ret == 0) {
+ ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
+ if (ret >= max_mac_addr)
+ return -ENOMEM;
+ if (smt_idx) {
+ /* Does fw supports returning smt_idx? */
+ if (adap->params.viid_smt_extn_support)
+ *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
+ else {
+ /* In T4/T5, SMT contains 256 SMAC entries
+ * organized in 128 rows of 2 entries each.
+ * In T6, SMT contains 256 SMAC entries in
+ * 256 rows.
+ */
+ if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
+ *smt_idx = ((viid & M_FW_VIID_VIN) << 1);
+ else
+ *smt_idx = (viid & M_FW_VIID_VIN);
+ }
+ }
+ }
+
+ return ret;
+}
+
diff --git a/usr/src/uts/common/io/cxgbe/common/t4_hw.h b/usr/src/uts/common/io/cxgbe/common/t4_hw.h
index ef1b41ad0c..72a9d5ddce 100644
--- a/usr/src/uts/common/io/cxgbe/common/t4_hw.h
+++ b/usr/src/uts/common/io/cxgbe/common/t4_hw.h
@@ -12,7 +12,7 @@
/*
* This file is part of the Chelsio T4/T5/T6 Ethernet driver.
*
- * Copyright (C) 2009-2017 Chelsio Communications. All rights reserved.
+ * Copyright (C) 2009-2019 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
@@ -32,6 +32,7 @@ enum {
EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
+ T6_RSS_NENTRIES = 4096, /* # of entries in RSS mapping table */
TCB_SIZE = 128, /* TCB size */
NMTUS = 16, /* size of MTU table */
NCCTRL_WIN = 32, /* # of congestion control windows */
@@ -74,6 +75,7 @@ enum {
SGE_CTXT_SIZE = 24, /* size of SGE context */
SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
+ SGE_NDBQTIMERS = 8, /* # of Doorbell Queue Timer values */
SGE_MAX_IQ_SIZE = 65520,
};
@@ -290,4 +292,14 @@ enum {
#define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP)
#define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP)
+#define I2C_DEV_ADDR_A0 0xa0
+#define I2C_DEV_ADDR_A2 0xa2
+#define I2C_PAGE_SIZE 0x100
+#define SFP_DIAG_TYPE_ADDR 0x5c
+#define SFP_DIAG_TYPE_LEN 0x1
+#define SFF_8472_COMP_ADDR 0x5e
+#define SFF_8472_COMP_LEN 0x1
+#define SFF_REV_ADDR 0x1
+#define SFF_REV_LEN 0x1
+
#endif /* __T4_HW_H */
diff --git a/usr/src/uts/common/io/cxgbe/common/t4_msg.h b/usr/src/uts/common/io/cxgbe/common/t4_msg.h
index 45a91f54fc..aeb018f72f 100644
--- a/usr/src/uts/common/io/cxgbe/common/t4_msg.h
+++ b/usr/src/uts/common/io/cxgbe/common/t4_msg.h
@@ -12,7 +12,7 @@
/*
* Definitions of T4/T5/T6 work request and CPL5 commands and status codes
*
- * Copyright (C) 2008-2017 Chelsio Communications. All rights reserved.
+ * Copyright (C) 2008-2019 Chelsio Communications. All rights reserved.
*
* Written by Dimitris Michailidis (dm@chelsio.com)
*
@@ -3092,6 +3092,12 @@ struct cpl_rx_mps_pkt {
#define G_CPL_RX_MPS_PKT_TYPE(x) \
(((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE)
+#define S_CPL_RX_MPS_PKT_LENGTH 0
+#define M_CPL_RX_MPS_PKT_LENGTH 0xffff
+#define V_CPL_RX_MPS_PKT_LENGTH(x) ((x) << S_CPL_RX_MPS_PKT_LENGTH)
+#define G_CPL_RX_MPS_PKT_LENGTH(x) \
+ (((x) >> S_CPL_RX_MPS_PKT_LENGTH) & M_CPL_RX_MPS_PKT_LENGTH)
+
/*
* Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field.
*/
diff --git a/usr/src/uts/common/io/cxgbe/common/t4_regs.h b/usr/src/uts/common/io/cxgbe/common/t4_regs.h
index bea5f5e3ca..999574e96a 100644
--- a/usr/src/uts/common/io/cxgbe/common/t4_regs.h
+++ b/usr/src/uts/common/io/cxgbe/common/t4_regs.h
@@ -1,3 +1,4 @@
+
/*
* This file and its contents are supplied under the terms of the
* Common Development and Distribution License ("CDDL"), version 1.0.
@@ -10,10 +11,10 @@
*/
/* This file is automatically generated --- changes will be lost */
-/* Generation Date : Thu Feb 16 10:13:37 IST 2017 */
-/* Directory name: t4_reg.txt, Changeset: */
-/* Directory name: t5_reg.txt, Changeset: 6939:9fe6306ea018 */
-/* Directory name: t6_reg.txt, Changeset: 4259:6bffc83b6848 */
+/* Generation Date : Fri Jun 22 10:51:50 PDT 2018 */
+/* Directory name: t4_reg.txt, Date: Not specified */
+/* Directory name: t5_reg.txt, Changeset: 6940:daefc1fa1d8a */
+/* Directory name: t6_reg.txt, Changeset: 4270:552778f380ec */
#define MYPF_BASE 0x1b000
#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
@@ -441,9 +442,6 @@
#define LE_DB_DBGI_REQ_MASK_T6(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
#define NUM_LE_DB_DBGI_REQ_MASK_T6_INSTANCES 11
-#define LE_DB_DBGI_RSP_DATA_T6(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
-#define NUM_LE_DB_DBGI_RSP_DATA_T6_INSTANCES 11
-
#define LE_DB_ACTIVE_MASK_IPV6_T6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
#define NUM_LE_DB_ACTIVE_MASK_IPV6_T6_INSTANCES 8
@@ -2352,6 +2350,22 @@
#define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
#define A_SGE_PC1_RSP_BIST_CMD 0x11b0
#define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
+#define A_SGE_DBQ_TIMER_DBG 0x11c4
+
+#define S_DBQ_TIMER_CMD 31
+#define V_DBQ_TIMER_CMD(x) ((x) << S_DBQ_TIMER_CMD)
+#define F_DBQ_TIMER_CMD V_DBQ_TIMER_CMD(1U)
+
+#define S_DBQ_TIMER_INDEX 24
+#define M_DBQ_TIMER_INDEX 0x3fU
+#define V_DBQ_TIMER_INDEX(x) ((x) << S_DBQ_TIMER_INDEX)
+#define G_DBQ_TIMER_INDEX(x) (((x) >> S_DBQ_TIMER_INDEX) & M_DBQ_TIMER_INDEX)
+
+#define S_DBQ_TIMER_QCNT 0
+#define M_DBQ_TIMER_QCNT 0x1ffffU
+#define V_DBQ_TIMER_QCNT(x) ((x) << S_DBQ_TIMER_QCNT)
+#define G_DBQ_TIMER_QCNT(x) (((x) >> S_DBQ_TIMER_QCNT) & M_DBQ_TIMER_QCNT)
+
#define A_SGE_CTXT_CMD 0x11fc
#define S_BUSY 31
@@ -6517,6 +6531,36 @@
#define A_TP_INT_CAUSE 0x7e74
#define A_TP_PER_ENABLE 0x7e78
+#define A_TP_FLM_FREE_PS_CNT 0x7e80
+
+#define S_FREEPSTRUCTCOUNT 0
+#define M_FREEPSTRUCTCOUNT 0x1fffffU
+#define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
+#define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
+
+#define A_TP_FLM_FREE_RX_CNT 0x7e84
+
+#define S_FREERXPAGECHN 28
+#define V_FREERXPAGECHN(x) ((x) << S_FREERXPAGECHN)
+#define F_FREERXPAGECHN V_FREERXPAGECHN(1U)
+
+#define S_FREERXPAGECOUNT 0
+#define M_FREERXPAGECOUNT 0x1fffffU
+#define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
+#define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
+
+#define A_TP_FLM_FREE_TX_CNT 0x7e88
+
+#define S_FREETXPAGECHN 28
+#define M_FREETXPAGECHN 0x3U
+#define V_FREETXPAGECHN(x) ((x) << S_FREETXPAGECHN)
+#define G_FREETXPAGECHN(x) (((x) >> S_FREETXPAGECHN) & M_FREETXPAGECHN)
+
+#define S_FREETXPAGECOUNT 0
+#define M_FREETXPAGECOUNT 0x1fffffU
+#define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
+#define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
+
#define A_TP_TX_ORATE 0x7ebc
#define S_OFDRATE3 24
@@ -7600,6 +7644,32 @@
#define A_ULP_TX_LA_RDDATA_10 0x8f64
#define A_ULP_TX_LA_WRPTR_10 0x8f68
#define A_ULP_TX_LA_RESERVED_10 0x8f6c
+#define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70
+
+#define S_LA_WR0 0
+#define V_LA_WR0(x) ((x) << S_LA_WR0)
+#define F_LA_WR0 V_LA_WR0(1U)
+
+#define A_ULP_TX_ASIC_DEBUG_0 0x8f74
+#define A_ULP_TX_ASIC_DEBUG_1 0x8f78
+#define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
+#define A_ULP_TX_ASIC_DEBUG_3 0x8f80
+#define A_ULP_TX_ASIC_DEBUG_4 0x8f84
+#define A_ULP_TX_TLS_CH0_PERR_CAUSE 0xc
+
+#define S_GLUE_PERR 3
+#define V_GLUE_PERR(x) ((x) << S_GLUE_PERR)
+#define F_GLUE_PERR V_GLUE_PERR(1U)
+
+#define S_DSGL_PERR 2
+#define V_DSGL_PERR(x) ((x) << S_DSGL_PERR)
+#define F_DSGL_PERR V_DSGL_PERR(1U)
+
+#define S_SGE_PERR 1
+#define V_SGE_PERR(x) ((x) << S_SGE_PERR)
+#define F_SGE_PERR V_SGE_PERR(1U)
+
+#define A_ULP_TX_TLS_CH1_PERR_CAUSE 0x4c
/* registers for module PM_RX */
#define PM_RX_BASE_ADDR 0x8fc0
@@ -9778,27 +9848,7 @@
#define V_T6_VFID(x) ((x) << S_T6_VFID)
#define G_T6_VFID(x) (((x) >> S_T6_VFID) & M_T6_VFID)
-#define A_PL_INT_CAUSE 0x1940c
-
-#define S_MC1 31
-#define V_MC1(x) ((x) << S_MC1)
-#define F_MC1 V_MC1(1U)
-
-#define S_MAC3 12
-#define V_MAC3(x) ((x) << S_MAC3)
-#define F_MAC3 V_MAC3(1U)
-
-#define S_MAC2 11
-#define V_MAC2(x) ((x) << S_MAC2)
-#define F_MAC2 V_MAC2(1U)
-
-#define S_FLR 30
-#define V_FLR(x) ((x) << S_FLR)
-#define F_FLR V_FLR(1U)
-
-#define S_SW_CIM 29
-#define V_SW_CIM(x) ((x) << S_SW_CIM)
-#define F_SW_CIM V_SW_CIM(1U)
+#define A_PL_PERR_CAUSE 0x19404
#define S_UART 28
#define V_UART(x) ((x) << S_UART)
@@ -9852,9 +9902,9 @@
#define V_EDC0(x) ((x) << S_EDC0)
#define F_EDC0 V_EDC0(1U)
-#define S_MC0 15
-#define V_MC0(x) ((x) << S_MC0)
-#define F_MC0 V_MC0(1U)
+#define S_MC 15
+#define V_MC(x) ((x) << S_MC)
+#define F_MC V_MC(1U)
#define S_PCIE 14
#define V_PCIE(x) ((x) << S_PCIE)
@@ -9864,18 +9914,30 @@
#define V_PMU(x) ((x) << S_PMU)
#define F_PMU V_PMU(1U)
-#define S_MAC1 10
-#define V_MAC1(x) ((x) << S_MAC1)
-#define F_MAC1 V_MAC1(1U)
+#define S_XGMAC_KR1 12
+#define V_XGMAC_KR1(x) ((x) << S_XGMAC_KR1)
+#define F_XGMAC_KR1 V_XGMAC_KR1(1U)
-#define S_MAC0 9
-#define V_MAC0(x) ((x) << S_MAC0)
-#define F_MAC0 V_MAC0(1U)
+#define S_XGMAC_KR0 11
+#define V_XGMAC_KR0(x) ((x) << S_XGMAC_KR0)
+#define F_XGMAC_KR0 V_XGMAC_KR0(1U)
+
+#define S_XGMAC1 10
+#define V_XGMAC1(x) ((x) << S_XGMAC1)
+#define F_XGMAC1 V_XGMAC1(1U)
+
+#define S_XGMAC0 9
+#define V_XGMAC0(x) ((x) << S_XGMAC0)
+#define F_XGMAC0 V_XGMAC0(1U)
#define S_SMB 8
#define V_SMB(x) ((x) << S_SMB)
#define F_SMB V_SMB(1U)
+#define S_SF 7
+#define V_SF(x) ((x) << S_SF)
+#define F_SF V_SF(1U)
+
#define S_PL 6
#define V_PL(x) ((x) << S_PL)
#define F_PL V_PL(1U)
@@ -9904,12 +9966,41 @@
#define V_CIM(x) ((x) << S_CIM)
#define F_CIM V_CIM(1U)
-#define A_PL_INT_ENABLE 0x19410
+#define A_PL_INT_CAUSE 0x1940c
-#define S_SF 7
-#define V_SF(x) ((x) << S_SF)
-#define F_SF V_SF(1U)
+#define S_MC1 31
+#define V_MC1(x) ((x) << S_MC1)
+#define F_MC1 V_MC1(1U)
+
+#define S_MAC3 12
+#define V_MAC3(x) ((x) << S_MAC3)
+#define F_MAC3 V_MAC3(1U)
+
+#define S_MAC2 11
+#define V_MAC2(x) ((x) << S_MAC2)
+#define F_MAC2 V_MAC2(1U)
+
+#define S_FLR 30
+#define V_FLR(x) ((x) << S_FLR)
+#define F_FLR V_FLR(1U)
+#define S_SW_CIM 29
+#define V_SW_CIM(x) ((x) << S_SW_CIM)
+#define F_SW_CIM V_SW_CIM(1U)
+
+#define S_MC0 15
+#define V_MC0(x) ((x) << S_MC0)
+#define F_MC0 V_MC0(1U)
+
+#define S_MAC1 10
+#define V_MAC1(x) ((x) << S_MAC1)
+#define F_MAC1 V_MAC1(1U)
+
+#define S_MAC0 9
+#define V_MAC0(x) ((x) << S_MAC0)
+#define F_MAC0 V_MAC0(1U)
+
+#define A_PL_INT_ENABLE 0x19410
#define A_PL_INT_MAP0 0x19414
#define S_MAPNCSI 16
diff --git a/usr/src/uts/common/io/cxgbe/common/t4_regs_values.h b/usr/src/uts/common/io/cxgbe/common/t4_regs_values.h
index 25cc139196..d946f63c55 100644
--- a/usr/src/uts/common/io/cxgbe/common/t4_regs_values.h
+++ b/usr/src/uts/common/io/cxgbe/common/t4_regs_values.h
@@ -12,7 +12,7 @@
/*
* This file is part of the Chelsio T4/T5/T6 support code.
*
- * Copyright (C) 2003-2017 Chelsio Communications. All rights reserved.
+ * Copyright (C) 2003-2019 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
@@ -138,6 +138,11 @@
#define X_FETCHBURSTMIN_64B 2
#define X_FETCHBURSTMIN_128B 3
+/* T6 and later use a single-bit encoding for FetchBurstMin */
+#define X_FETCHBURSTMIN_SHIFT_T6 6
+#define X_FETCHBURSTMIN_64B_T6 0
+#define X_FETCHBURSTMIN_128B_T6 1
+
#define X_FETCHBURSTMAX_SHIFT 6
#define X_FETCHBURSTMAX_64B 0
#define X_FETCHBURSTMAX_128B 1
diff --git a/usr/src/uts/common/io/cxgbe/firmware/t4_fw.c b/usr/src/uts/common/io/cxgbe/firmware/t4_fw.c
index 3c9c60e356..eea7b44b6d 100644
--- a/usr/src/uts/common/io/cxgbe/firmware/t4_fw.c
+++ b/usr/src/uts/common/io/cxgbe/firmware/t4_fw.c
@@ -3,35685 +3,35750 @@
*/
unsigned char t4fw_data[] = {
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- 0x78, 0xff, 0xff, 0xff, 0x1f, 0xfc, 0xe1, 0x40, 0x80, 0x00, 0x00, 0x01, 0xe1, 0x00, 0x7b, 0x70,
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- 0xcd, 0x13, 0xff, 0xcd, 0x93, 0x20, 0x12, 0xff, 0xcd, 0x13, 0xff, 0xcd, 0x84, 0x20, 0x04, 0x33,
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+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
};
int t4fw_size = sizeof(t4fw_data);
diff --git a/usr/src/uts/common/io/cxgbe/firmware/t4_fw.h b/usr/src/uts/common/io/cxgbe/firmware/t4_fw.h
index f03b0b3f4f..bdde097201 100644
--- a/usr/src/uts/common/io/cxgbe/firmware/t4_fw.h
+++ b/usr/src/uts/common/io/cxgbe/firmware/t4_fw.h
@@ -5,10 +5,10 @@
#ifndef __T4FW_H
#define __T4FW_H
-#define FW_VERSION_MAJOR 1
-#define FW_VERSION_MINOR 23
-#define FW_VERSION_MICRO 4
-#define FW_VERSION_BUILD 0
+#define T4FW_VERSION_MAJOR 1
+#define T4FW_VERSION_MINOR 24
+#define T4FW_VERSION_MICRO 3
+#define T4FW_VERSION_BUILD 0
extern unsigned char t4fw_data[];
extern int t4fw_size;
diff --git a/usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h b/usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h
index 01d9db43fe..d705c73891 100644
--- a/usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h
+++ b/usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h
@@ -70,6 +70,7 @@ enum fw_memtype {
FW_MEMTYPE_FLASH = 0x4,
FW_MEMTYPE_INTERNAL = 0x5,
FW_MEMTYPE_EXTMEM1 = 0x6,
+ FW_MEMTYPE_HMA = 0x7,
};
/******************************************************************************
@@ -92,6 +93,7 @@ enum fw_wr_opcodes {
FW_OFLD_TX_DATA_WR = 0x0b,
FW_CMD_WR = 0x10,
FW_ETH_TX_PKT_VM_WR = 0x11,
+ FW_ETH_TX_PKTS_VM_WR = 0x12,
FW_RI_RES_WR = 0x0c,
FW_RI_RDMA_WRITE_WR = 0x14,
FW_RI_SEND_WR = 0x15,
@@ -100,6 +102,7 @@ enum fw_wr_opcodes {
FW_RI_BIND_MW_WR = 0x18,
FW_RI_FR_NSMR_WR = 0x19,
FW_RI_FR_NSMR_TPTE_WR = 0x20,
+ FW_RI_RDMA_WRITE_CMPL_WR = 0x21,
FW_RI_INV_LSTAG_WR = 0x1a,
FW_RI_SEND_IMMEDIATE_WR = 0x15,
FW_RI_ATOMIC_WR = 0x16,
@@ -360,7 +363,7 @@ struct fw_filter2_wr {
__be16 fpm;
__be16 r7;
__u8 sma[6];
- __u8 r8_hi[2];
+ __be16 r8;
__u8 filter_type_swapmac;
__u8 natmode_to_ulp_type;
__be16 newlport;
@@ -368,7 +371,7 @@ struct fw_filter2_wr {
__u8 newlip[16];
__u8 newfip[16];
__be32 natseqcheck;
- __be32 dip_hit_vni;
+ __be32 r9;
__be64 r10;
__be64 r11;
__be64 r12;
@@ -408,6 +411,20 @@ struct fw_filter2_wr {
(((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
#define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
+#define S_FW_FILTER2_WR_DROP_ENCAP 30
+#define M_FW_FILTER2_WR_DROP_ENCAP 0x1
+#define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP)
+#define G_FW_FILTER2_WR_DROP_ENCAP(x) \
+ (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP)
+#define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U)
+
+#define S_FW_FILTER2_WR_TX_LOOP 29
+#define M_FW_FILTER2_WR_TX_LOOP 0x1
+#define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP)
+#define G_FW_FILTER2_WR_TX_LOOP(x) \
+ (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP)
+#define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U)
+
#define S_FW_FILTER_WR_RPTTID 25
#define M_FW_FILTER_WR_RPTTID 0x1
#define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
@@ -592,19 +609,6 @@ struct fw_filter2_wr {
#define G_FW_FILTER2_WR_ULP_TYPE(x) \
(((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)
-#define S_FW_FILTER2_WR_DIP_HIT 24
-#define M_FW_FILTER2_WR_DIP_HIT 0x1
-#define V_FW_FILTER2_WR_DIP_HIT(x) ((x) << S_FW_FILTER2_WR_DIP_HIT)
-#define G_FW_FILTER2_WR_DIP_HIT(x) \
- (((x) >> S_FW_FILTER2_WR_DIP_HIT) & M_FW_FILTER2_WR_DIP_HIT)
-#define F_FW_FILTER2_WR_DIP_HIT V_FW_FILTER2_WR_DIP_HIT(1U)
-
-#define S_FW_FILTER2_WR_VNI 0
-#define M_FW_FILTER2_WR_VNI 0xffffff
-#define V_FW_FILTER2_WR_VNI(x) ((x) << S_FW_FILTER2_WR_VNI)
-#define G_FW_FILTER2_WR_VNI(x) \
- (((x) >> S_FW_FILTER2_WR_VNI) & M_FW_FILTER2_WR_VNI)
-
#define S_FW_FILTER_WR_MACI 23
#define M_FW_FILTER_WR_MACI 0x1ff
#define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
@@ -661,6 +665,15 @@ struct fw_ulptx_wr {
__u64 cookie;
};
+/* flag for packet type - control packet (0), data packet (1)
+ */
+#define S_FW_ULPTX_WR_DATA 28
+#define M_FW_ULPTX_WR_DATA 0x1
+#define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA)
+#define G_FW_ULPTX_WR_DATA(x) \
+ (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA)
+#define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U)
+
struct fw_tp_wr {
__be32 op_to_immdlen;
__be32 flowid_len16;
@@ -1146,6 +1159,19 @@ struct fw_eth_tx_pkt_vm_wr {
__be16 vlantci;
};
+struct fw_eth_tx_pkts_vm_wr {
+ __be32 op_pkd;
+ __be32 equiq_to_len16;
+ __be32 r3;
+ __be16 plen;
+ __u8 npkt;
+ __u8 r4;
+ __u8 ethmacdst[6];
+ __u8 ethmacsrc[6];
+ __be16 ethtype;
+ __be16 vlantci;
+};
+
/******************************************************************************
* R I W O R K R E Q U E S T s
**************************************/
@@ -1176,7 +1202,8 @@ enum fw_ri_wr_opcode {
FW_RI_FAST_REGISTER = 0xd,
FW_RI_LOCAL_INV = 0xe,
#endif
- FW_RI_SGE_EC_CR_RETURN = 0xf
+ FW_RI_SGE_EC_CR_RETURN = 0xf,
+ FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT,
};
enum fw_ri_wr_flags {
@@ -1185,7 +1212,8 @@ enum fw_ri_wr_flags {
FW_RI_SOLICITED_EVENT_FLAG = 0x04,
FW_RI_READ_FENCE_FLAG = 0x08,
FW_RI_LOCAL_FENCE_FLAG = 0x10,
- FW_RI_RDMA_READ_INVALIDATE = 0x20
+ FW_RI_RDMA_READ_INVALIDATE = 0x20,
+ FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40
};
enum fw_ri_mpa_attrs {
@@ -1437,6 +1465,13 @@ struct fw_ri_cqe {
__be32 stag;
__be32 msn;
} rcqe;
+ struct fw_ri_rcqe_imm {
+ __be32 qpid_n_stat_rxtx_type;
+ __be32 plen;
+ __be32 mo;
+ __be32 msn;
+ __u64 imm_data;
+ } imm_data_rcqe;
} u;
};
@@ -1764,7 +1799,7 @@ struct fw_ri_rdma_write_wr {
__u16 wrid;
__u8 r1[3];
__u8 len16;
- __be64 r2;
+ __u64 immd_data;
__be32 plen;
__be32 stag_sink;
__be64 to_sink;
@@ -1801,6 +1836,37 @@ struct fw_ri_send_wr {
#define G_FW_RI_SEND_WR_SENDOP(x) \
(((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
+struct fw_ri_rdma_write_cmpl_wr {
+ __u8 opcode;
+ __u8 flags;
+ __u16 wrid;
+ __u8 r1[3];
+ __u8 len16;
+ __u8 r2;
+ __u8 flags_send;
+ __u16 wrid_send;
+ __be32 stag_inv;
+ __be32 plen;
+ __be32 stag_sink;
+ __be64 to_sink;
+ union fw_ri_cmpl {
+ struct fw_ri_immd_cmpl {
+ __u8 op;
+ __u8 r1[6];
+ __u8 immdlen;
+ __u8 data[16];
+ } immd_src;
+ struct fw_ri_isgl isgl_src;
+ } u_cmpl;
+ __be64 r3;
+#ifndef C99_NOT_SUPPORTED
+ union fw_ri_write {
+ struct fw_ri_immd immd_src[0];
+ struct fw_ri_isgl isgl_src[0];
+ } u;
+#endif
+};
+
struct fw_ri_rdma_read_wr {
__u8 opcode;
__u8 flags;
@@ -4107,6 +4173,7 @@ enum fw_cmd_opcodes {
FW_DCB_IEEE_CMD = 0x3a,
FW_DIAG_CMD = 0x3d,
FW_PTP_CMD = 0x3e,
+ FW_HMA_CMD = 0x3f,
FW_LASTC2E_CMD = 0x40,
FW_ERROR_CMD = 0x80,
FW_DEBUG_CMD = 0x81,
@@ -4710,6 +4777,22 @@ enum fw_params_mnem {
/*
* device parameters
*/
+#define S_FW_PARAMS_PARAM_FILTER_MODE 16
+#define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff
+#define V_FW_PARAMS_PARAM_FILTER_MODE(x) \
+ ((x) << S_FW_PARAMS_PARAM_FILTER_MODE)
+#define G_FW_PARAMS_PARAM_FILTER_MODE(x) \
+ (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \
+ M_FW_PARAMS_PARAM_FILTER_MODE)
+
+#define S_FW_PARAMS_PARAM_FILTER_MASK 0
+#define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff
+#define V_FW_PARAMS_PARAM_FILTER_MASK(x) \
+ ((x) << S_FW_PARAMS_PARAM_FILTER_MASK)
+#define G_FW_PARAMS_PARAM_FILTER_MASK(x) \
+ (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \
+ M_FW_PARAMS_PARAM_FILTER_MASK)
+
enum fw_params_param_dev {
FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
@@ -4749,6 +4832,21 @@ enum fw_params_param_dev {
FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F,
+ FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20,
+ FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
+ FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22,
+ FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23,
+ FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24,
+ FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25,
+ FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26,
+ FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
+ FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
+ FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29,
+ FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,
+ FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B,
+ FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C,
+ FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D,
+ FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
};
/*
@@ -4776,6 +4874,12 @@ enum fw_params_param_dev_phyfw {
enum fw_params_param_dev_diag {
FW_PARAM_DEV_DIAG_TMP = 0x00,
FW_PARAM_DEV_DIAG_VDD = 0x01,
+ FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02,
+};
+
+enum fw_params_param_dev_filter{
+ FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00,
+ FW_PARAM_DEV_FILTER_MODE_MASK = 0x01,
};
enum fw_params_param_dev_fwcache {
@@ -4837,6 +4941,22 @@ enum fw_params_param_pfvf {
FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38,
FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
+ FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
+ FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,
+ FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,
+ FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D,
+ FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E,
+ FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F,
+ FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,
+};
+
+/*
+ * virtual link state as seen by the specified VF
+ */
+enum vf_link_states {
+ VF_LINK_STATE_AUTO = 0x00,
+ VF_LINK_STATE_ENABLE = 0x01,
+ VF_LINK_STATE_DISABLE = 0x02,
};
/*
@@ -4852,6 +4972,7 @@ enum fw_params_param_dmaq {
FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14,
+ FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15,
FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30
};
@@ -5073,6 +5194,12 @@ enum fw_iq_type {
FW_IQ_TYPE_VF_CQ
};
+enum fw_iq_iqtype {
+ FW_IQ_IQTYPE_OTHER,
+ FW_IQ_IQTYPE_NIC,
+ FW_IQ_IQTYPE_OFLD,
+};
+
struct fw_iq_cmd {
__be32 op_to_vfn;
__be32 alloc_to_len16;
@@ -5279,6 +5406,12 @@ struct fw_iq_cmd {
(((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
#define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U)
+#define S_FW_IQ_CMD_IQTYPE 24
+#define M_FW_IQ_CMD_IQTYPE 0x3
+#define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE)
+#define G_FW_IQ_CMD_IQTYPE(x) \
+ (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE)
+
#define S_FW_IQ_CMD_FL0CNGCHMAP 20
#define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
#define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
@@ -5785,7 +5918,7 @@ struct fw_eq_eth_cmd {
__be32 dcaen_to_eqsize;
__be64 eqaddr;
__be32 autoequiqe_to_viid;
- __be32 r8_lo;
+ __be32 timeren_timerix;
__be64 r9;
};
@@ -5979,6 +6112,19 @@ struct fw_eq_eth_cmd {
#define G_FW_EQ_ETH_CMD_VIID(x) \
(((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
+#define S_FW_EQ_ETH_CMD_TIMEREN 3
+#define M_FW_EQ_ETH_CMD_TIMEREN 0x1
+#define V_FW_EQ_ETH_CMD_TIMEREN(x) ((x) << S_FW_EQ_ETH_CMD_TIMEREN)
+#define G_FW_EQ_ETH_CMD_TIMEREN(x) \
+ (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN)
+#define F_FW_EQ_ETH_CMD_TIMEREN V_FW_EQ_ETH_CMD_TIMEREN(1U)
+
+#define S_FW_EQ_ETH_CMD_TIMERIX 0
+#define M_FW_EQ_ETH_CMD_TIMERIX 0x7
+#define V_FW_EQ_ETH_CMD_TIMERIX(x) ((x) << S_FW_EQ_ETH_CMD_TIMERIX)
+#define G_FW_EQ_ETH_CMD_TIMERIX(x) \
+ (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX)
+
struct fw_eq_ctrl_cmd {
__be32 op_to_vfn;
__be32 alloc_to_len16;
@@ -6364,6 +6510,23 @@ struct fw_eq_ofld_cmd {
#define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN)
#define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
+/* Macros for VIID parsing:
+ VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */
+#define S_FW_256VIID_PFN 9
+#define M_FW_256VIID_PFN 0x7
+#define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN)
+#define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN)
+
+#define S_FW_256VIID_VIVLD 8
+#define M_FW_256VIID_VIVLD 0x1
+#define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD)
+#define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD)
+
+#define S_FW_256VIID_VIN 0
+#define M_FW_256VIID_VIN 0xFF
+#define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN)
+#define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN)
+
enum fw_vi_func {
FW_VI_FUNC_ETH,
FW_VI_FUNC_OFLD,
@@ -6419,6 +6582,19 @@ struct fw_vi_cmd {
(((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
#define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
+#define S_FW_VI_CMD_VFVLD 24
+#define M_FW_VI_CMD_VFVLD 0x1
+#define V_FW_VI_CMD_VFVLD(x) ((x) << S_FW_VI_CMD_VFVLD)
+#define G_FW_VI_CMD_VFVLD(x) \
+ (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
+#define F_FW_VI_CMD_VFVLD V_FW_VI_CMD_VFVLD(1U)
+
+#define S_FW_VI_CMD_VIN 16
+#define M_FW_VI_CMD_VIN 0xff
+#define V_FW_VI_CMD_VIN(x) ((x) << S_FW_VI_CMD_VIN)
+#define G_FW_VI_CMD_VIN(x) \
+ (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
+
#define S_FW_VI_CMD_TYPE 15
#define M_FW_VI_CMD_TYPE 0x1
#define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
@@ -6473,6 +6649,7 @@ struct fw_vi_cmd {
#define FW_VI_MAC_ADD_MAC 0x3FF
#define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
#define FW_VI_MAC_MAC_BASED_FREE 0x3FD
+#define FW_VI_MAC_ID_BASED_FREE 0x3FC
enum fw_vi_mac_smac {
FW_VI_MAC_MPS_TCAM_ENTRY,
@@ -6492,6 +6669,7 @@ enum fw_vi_mac_entry_types {
FW_VI_MAC_TYPE_EXACTMAC,
FW_VI_MAC_TYPE_HASHVEC,
FW_VI_MAC_TYPE_RAW,
+ FW_VI_MAC_TYPE_EXACTMAC_VNI,
};
struct fw_vi_mac_cmd {
@@ -6512,9 +6690,23 @@ struct fw_vi_mac_cmd {
__be64 data0m_pkd;
__be32 data1m[2];
} raw;
+ struct fw_vi_mac_vni {
+ __be16 valid_to_idx;
+ __u8 macaddr[6];
+ __be16 r7;
+ __u8 macaddr_mask[6];
+ __be32 lookup_type_to_vni;
+ __be32 vni_mask_pkd;
+ } exact_vni[2];
} u;
};
+#define S_FW_VI_MAC_CMD_SMTID 12
+#define M_FW_VI_MAC_CMD_SMTID 0xff
+#define V_FW_VI_MAC_CMD_SMTID(x) ((x) << S_FW_VI_MAC_CMD_SMTID)
+#define G_FW_VI_MAC_CMD_SMTID(x) \
+ (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID)
+
#define S_FW_VI_MAC_CMD_VIID 0
#define M_FW_VI_MAC_CMD_VIID 0xfff
#define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
@@ -6528,6 +6720,13 @@ struct fw_vi_mac_cmd {
(((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
#define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U)
+#define S_FW_VI_MAC_CMD_IS_SMAC 30
+#define M_FW_VI_MAC_CMD_IS_SMAC 0x1
+#define V_FW_VI_MAC_CMD_IS_SMAC(x) ((x) << S_FW_VI_MAC_CMD_IS_SMAC)
+#define G_FW_VI_MAC_CMD_IS_SMAC(x) \
+ (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC)
+#define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U)
+
#define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
#define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7
#define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
@@ -6578,6 +6777,45 @@ struct fw_vi_mac_cmd {
#define G_FW_VI_MAC_CMD_DATA0(x) \
(((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0)
+#define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31
+#define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1
+#define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE)
+#define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \
+ (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE)
+#define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U)
+
+#define S_FW_VI_MAC_CMD_DIP_HIT 30
+#define M_FW_VI_MAC_CMD_DIP_HIT 0x1
+#define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT)
+#define G_FW_VI_MAC_CMD_DIP_HIT(x) \
+ (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT)
+#define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U)
+
+#define S_FW_VI_MAC_CMD_VNI 0
+#define M_FW_VI_MAC_CMD_VNI 0xffffff
+#define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI)
+#define G_FW_VI_MAC_CMD_VNI(x) \
+ (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI)
+
+/* Extracting loopback port number passed from driver.
+ * as a part of fw_vi_mac_vni For non loopback entries
+ * ignore the field and update port number from flowc.
+ * Fw will ignore if physical port number received.
+ * expected range (4-7).
+ */
+
+#define S_FW_VI_MAC_CMD_PORT 24
+#define M_FW_VI_MAC_CMD_PORT 0x7
+#define V_FW_VI_MAC_CMD_PORT(x) ((x) << S_FW_VI_MAC_CMD_PORT)
+#define G_FW_VI_MAC_CMD_PORT(x) \
+ (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT)
+
+#define S_FW_VI_MAC_CMD_VNI_MASK 0
+#define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff
+#define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK)
+#define G_FW_VI_MAC_CMD_VNI_MASK(x) \
+ (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK)
+
/* T4 max MTU supported */
#define T4_MAX_MTU_SUPPORTED 9600
#define FW_RXMODE_MTU_NO_CHG 65535
@@ -6847,6 +7085,20 @@ struct fw_acl_vlan_cmd {
(((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
#define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U)
+#define S_FW_ACL_VLAN_CMD_TRANSPARENT 30
+#define M_FW_ACL_VLAN_CMD_TRANSPARENT 0x1
+#define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \
+ ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT)
+#define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \
+ (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT)
+#define F_FW_ACL_VLAN_CMD_TRANSPARENT V_FW_ACL_VLAN_CMD_TRANSPARENT(1U)
+
+#define S_FW_ACL_VLAN_CMD_PMASK 16
+#define M_FW_ACL_VLAN_CMD_PMASK 0xf
+#define V_FW_ACL_VLAN_CMD_PMASK(x) ((x) << S_FW_ACL_VLAN_CMD_PMASK)
+#define G_FW_ACL_VLAN_CMD_PMASK(x) \
+ (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK)
+
#define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7
#define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1
#define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
@@ -6861,7 +7113,7 @@ struct fw_acl_vlan_cmd {
(((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
#define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U)
-/* port capabilities bitmap */
+/* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
enum fw_port_cap {
FW_PORT_CAP_SPEED_100M = 0x0001,
FW_PORT_CAP_SPEED_1G = 0x0002,
@@ -6872,11 +7124,11 @@ enum fw_port_cap {
FW_PORT_CAP_FC_RX = 0x0040,
FW_PORT_CAP_FC_TX = 0x0080,
FW_PORT_CAP_ANEG = 0x0100,
- FW_PORT_CAP_MDIX = 0x0200,
- FW_PORT_CAP_MDIAUTO = 0x0400,
+ FW_PORT_CAP_MDIAUTO = 0x0200,
+ FW_PORT_CAP_MDISTRAIGHT = 0x0400,
FW_PORT_CAP_FEC_RS = 0x0800,
FW_PORT_CAP_FEC_BASER_RS = 0x1000,
- FW_PORT_CAP_FEC_RESERVED = 0x2000,
+ FW_PORT_CAP_FORCE_PAUSE = 0x2000,
FW_PORT_CAP_802_3_PAUSE = 0x4000,
FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
};
@@ -6900,11 +7152,17 @@ enum fw_port_cap {
(((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
#define S_FW_PORT_CAP_FEC 11
-#define M_FW_PORT_CAP_FEC 0x7
+#define M_FW_PORT_CAP_FEC 0x3
#define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC)
#define G_FW_PORT_CAP_FEC(x) \
(((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC)
+#define S_FW_PORT_CAP_FORCE_PAUSE 13
+#define M_FW_PORT_CAP_FORCE_PAUSE 0x1
+#define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE)
+#define G_FW_PORT_CAP_FORCE_PAUSE(x) \
+ (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE)
+
#define S_FW_PORT_CAP_802_3 14
#define M_FW_PORT_CAP_802_3 0x3
#define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3)
@@ -6923,21 +7181,93 @@ enum fw_port_mdi {
#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
-#define S_FW_PORT_AUXLINFO_KX4 2
-#define M_FW_PORT_AUXLINFO_KX4 0x1
-#define V_FW_PORT_AUXLINFO_KX4(x) \
- ((x) << S_FW_PORT_AUXLINFO_KX4)
-#define G_FW_PORT_AUXLINFO_KX4(x) \
- (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
-#define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U)
-
-#define S_FW_PORT_AUXLINFO_KR 1
-#define M_FW_PORT_AUXLINFO_KR 0x1
-#define V_FW_PORT_AUXLINFO_KR(x) \
- ((x) << S_FW_PORT_AUXLINFO_KR)
-#define G_FW_PORT_AUXLINFO_KR(x) \
- (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
-#define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U)
+/* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
+#define FW_PORT_CAP32_SPEED_100M 0x00000001UL
+#define FW_PORT_CAP32_SPEED_1G 0x00000002UL
+#define FW_PORT_CAP32_SPEED_10G 0x00000004UL
+#define FW_PORT_CAP32_SPEED_25G 0x00000008UL
+#define FW_PORT_CAP32_SPEED_40G 0x00000010UL
+#define FW_PORT_CAP32_SPEED_50G 0x00000020UL
+#define FW_PORT_CAP32_SPEED_100G 0x00000040UL
+#define FW_PORT_CAP32_SPEED_200G 0x00000080UL
+#define FW_PORT_CAP32_SPEED_400G 0x00000100UL
+#define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL
+#define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL
+#define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL
+#define FW_PORT_CAP32_RESERVED1 0x0000f000UL
+#define FW_PORT_CAP32_FC_RX 0x00010000UL
+#define FW_PORT_CAP32_FC_TX 0x00020000UL
+#define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL
+#define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL
+#define FW_PORT_CAP32_ANEG 0x00100000UL
+#define FW_PORT_CAP32_MDIAUTO 0x00200000UL
+#define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL
+#define FW_PORT_CAP32_FEC_RS 0x00800000UL
+#define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL
+#define FW_PORT_CAP32_FEC_RESERVED1 0x02000000UL
+#define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL
+#define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL
+#define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL
+#define FW_PORT_CAP32_RESERVED2 0xe0000000UL
+
+#define S_FW_PORT_CAP32_SPEED 0
+#define M_FW_PORT_CAP32_SPEED 0xfff
+#define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED)
+#define G_FW_PORT_CAP32_SPEED(x) \
+ (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
+
+#define S_FW_PORT_CAP32_FC 16
+#define M_FW_PORT_CAP32_FC 0x3
+#define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC)
+#define G_FW_PORT_CAP32_FC(x) \
+ (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC)
+
+#define S_FW_PORT_CAP32_802_3 18
+#define M_FW_PORT_CAP32_802_3 0x3
+#define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3)
+#define G_FW_PORT_CAP32_802_3(x) \
+ (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3)
+
+#define S_FW_PORT_CAP32_ANEG 20
+#define M_FW_PORT_CAP32_ANEG 0x1
+#define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG)
+#define G_FW_PORT_CAP32_ANEG(x) \
+ (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG)
+
+#define S_FW_PORT_CAP32_FORCE_PAUSE 28
+#define M_FW_PORT_CAP32_FORCE_PAUSE 0x1
+#define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE)
+#define G_FW_PORT_CAP32_FORCE_PAUSE(x) \
+ (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE)
+
+enum fw_port_mdi32 {
+ FW_PORT_CAP32_MDI_UNCHANGED,
+ FW_PORT_CAP32_MDI_AUTO,
+ FW_PORT_CAP32_MDI_F_STRAIGHT,
+ FW_PORT_CAP32_MDI_F_CROSSOVER
+};
+
+#define S_FW_PORT_CAP32_MDI 21
+#define M_FW_PORT_CAP32_MDI 3
+#define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
+#define G_FW_PORT_CAP32_MDI(x) \
+ (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
+
+#define S_FW_PORT_CAP32_FEC 23
+#define M_FW_PORT_CAP32_FEC 0x1f
+#define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC)
+#define G_FW_PORT_CAP32_FEC(x) \
+ (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC)
+
+/* macros to isolate various 32-bit Port Capabilities sub-fields */
+#define CAP32_SPEED(__cap32) \
+ (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32)
+
+#define CAP32_FEC(__cap32) \
+ (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32)
+
+#define CAP32_FC(__cap32) \
+ (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32)
enum fw_port_action {
FW_PORT_ACTION_L1_CFG = 0x0001,
@@ -6948,6 +7278,8 @@ enum fw_port_action {
FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
FW_PORT_ACTION_DCB_READ_DET = 0x0008,
+ FW_PORT_ACTION_L1_CFG32 = 0x0009,
+ FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a,
FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
@@ -6974,7 +7306,8 @@ enum fw_port_l2cfg_ctlbf {
FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
FW_PORT_L2_CTLBF_IVLAN = 0x10,
FW_PORT_L2_CTLBF_TXIPG = 0x20,
- FW_PORT_L2_CTLBF_MTU = 0x40
+ FW_PORT_L2_CTLBF_MTU = 0x40,
+ FW_PORT_L2_CTLBF_OVLAN_FILT = 0x80,
};
enum fw_dcb_app_tlv_sf {
@@ -7091,13 +7424,15 @@ struct fw_port_cmd {
struct fw_port_dcb_pfc {
__u8 type;
__u8 pfcen;
- __u8 r10[5];
+ __u8 apply_pkd;
+ __u8 r10_lo[4];
__u8 max_pfc_tcs;
__be64 r11;
} pfc;
struct fw_port_app_priority {
__u8 type;
- __u8 r10[2];
+ __u8 apply_pkd;
+ __u8 r10_lo;
__u8 idx;
__u8 user_prio_map;
__u8 sel_field;
@@ -7112,6 +7447,18 @@ struct fw_port_cmd {
__be64 r12;
} control;
} dcb;
+ struct fw_port_l1cfg32 {
+ __be32 rcap32;
+ __be32 r;
+ } l1cfg32;
+ struct fw_port_info32 {
+ __be32 lstatus32_to_cbllen32;
+ __be32 auxlinfo32_mtu32;
+ __be32 linkattr32;
+ __be32 pcaps32;
+ __be32 acaps32;
+ __be32 lpacaps32;
+ } info32;
} u;
};
@@ -7169,6 +7516,13 @@ struct fw_port_cmd {
(((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
#define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U)
+#define S_FW_PORT_CMD_OVLAN_FILT 2
+#define M_FW_PORT_CMD_OVLAN_FILT 0x1
+#define V_FW_PORT_CMD_OVLAN_FILT(x) ((x) << S_FW_PORT_CMD_OVLAN_FILT)
+#define G_FW_PORT_CMD_OVLAN_FILT(x) \
+ (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT)
+#define F_FW_PORT_CMD_OVLAN_FILT V_FW_PORT_CMD_OVLAN_FILT(1U)
+
#define S_FW_PORT_CMD_TXIPG 3
#define M_FW_PORT_CMD_TXIPG 0x1fff
#define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG)
@@ -7254,6 +7608,22 @@ struct fw_port_cmd {
#define G_FW_PORT_CMD_MODTYPE(x) \
(((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
+#define S_FW_PORT_AUXLINFO_KX4 2
+#define M_FW_PORT_AUXLINFO_KX4 0x1
+#define V_FW_PORT_AUXLINFO_KX4(x) \
+ ((x) << S_FW_PORT_AUXLINFO_KX4)
+#define G_FW_PORT_AUXLINFO_KX4(x) \
+ (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
+#define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U)
+
+#define S_FW_PORT_AUXLINFO_KR 1
+#define M_FW_PORT_AUXLINFO_KR 0x1
+#define V_FW_PORT_AUXLINFO_KR(x) \
+ ((x) << S_FW_PORT_AUXLINFO_KR)
+#define G_FW_PORT_AUXLINFO_KR(x) \
+ (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
+#define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U)
+
#define S_FW_PORT_CMD_DCBXDIS 7
#define M_FW_PORT_CMD_DCBXDIS 0x1
#define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS)
@@ -7299,6 +7669,85 @@ struct fw_port_cmd {
#define G_FW_PORT_CMD_APP_STATE(x) \
(((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
+#define S_FW_PORT_CMD_LSTATUS32 31
+#define M_FW_PORT_CMD_LSTATUS32 0x1
+#define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32)
+#define G_FW_PORT_CMD_LSTATUS32(x) \
+ (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32)
+#define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U)
+
+#define S_FW_PORT_CMD_LINKDNRC32 28
+#define M_FW_PORT_CMD_LINKDNRC32 0x7
+#define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32)
+#define G_FW_PORT_CMD_LINKDNRC32(x) \
+ (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
+
+#define S_FW_PORT_CMD_DCBXDIS32 27
+#define M_FW_PORT_CMD_DCBXDIS32 0x1
+#define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32)
+#define G_FW_PORT_CMD_DCBXDIS32(x) \
+ (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32)
+#define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U)
+
+#define S_FW_PORT_CMD_MDIOCAP32 26
+#define M_FW_PORT_CMD_MDIOCAP32 0x1
+#define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32)
+#define G_FW_PORT_CMD_MDIOCAP32(x) \
+ (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32)
+#define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U)
+
+#define S_FW_PORT_CMD_MDIOADDR32 21
+#define M_FW_PORT_CMD_MDIOADDR32 0x1f
+#define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32)
+#define G_FW_PORT_CMD_MDIOADDR32(x) \
+ (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
+
+#define S_FW_PORT_CMD_PORTTYPE32 13
+#define M_FW_PORT_CMD_PORTTYPE32 0xff
+#define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32)
+#define G_FW_PORT_CMD_PORTTYPE32(x) \
+ (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
+
+#define S_FW_PORT_CMD_MODTYPE32 8
+#define M_FW_PORT_CMD_MODTYPE32 0x1f
+#define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32)
+#define G_FW_PORT_CMD_MODTYPE32(x) \
+ (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
+
+#define S_FW_PORT_CMD_CBLLEN32 0
+#define M_FW_PORT_CMD_CBLLEN32 0xff
+#define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32)
+#define G_FW_PORT_CMD_CBLLEN32(x) \
+ (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32)
+
+#define S_FW_PORT_CMD_AUXLINFO32 24
+#define M_FW_PORT_CMD_AUXLINFO32 0xff
+#define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32)
+#define G_FW_PORT_CMD_AUXLINFO32(x) \
+ (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32)
+
+#define S_FW_PORT_AUXLINFO32_KX4 2
+#define M_FW_PORT_AUXLINFO32_KX4 0x1
+#define V_FW_PORT_AUXLINFO32_KX4(x) \
+ ((x) << S_FW_PORT_AUXLINFO32_KX4)
+#define G_FW_PORT_AUXLINFO32_KX4(x) \
+ (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4)
+#define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U)
+
+#define S_FW_PORT_AUXLINFO32_KR 1
+#define M_FW_PORT_AUXLINFO32_KR 0x1
+#define V_FW_PORT_AUXLINFO32_KR(x) \
+ ((x) << S_FW_PORT_AUXLINFO32_KR)
+#define G_FW_PORT_AUXLINFO32_KR(x) \
+ (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR)
+#define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U)
+
+#define S_FW_PORT_CMD_MTU32 0
+#define M_FW_PORT_CMD_MTU32 0xffff
+#define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32)
+#define G_FW_PORT_CMD_MTU32(x) \
+ (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32)
+
/*
* These are configured into the VPD and hence tools that generate
* VPD may use this enumeration.
@@ -7331,6 +7780,7 @@ enum fw_port_type {
FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
+ FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/
FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
};
@@ -7783,7 +8233,7 @@ struct fw_ptp_cmd {
__u8 txchan;
__be16 absid;
__be16 mode;
- __be16 r3;
+ __be16 ptp_rx_ctrl_pkd;
} init;
struct fw_ptp_ts {
__u8 sc;
@@ -7802,6 +8252,14 @@ struct fw_ptp_cmd {
#define G_FW_PTP_CMD_PORTID(x) \
(((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID)
+#define S_FW_PTP_CMD_PTP_RX_CTRL 15
+#define M_FW_PTP_CMD_PTP_RX_CTRL 0x1
+#define V_FW_PTP_CMD_PTP_RX_CTRL(x) ((x) << S_FW_PTP_CMD_PTP_RX_CTRL)
+#define G_FW_PTP_CMD_PTP_RX_CTRL(x) \
+ (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL)
+#define F_FW_PTP_CMD_PTP_RX_CTRL V_FW_PTP_CMD_PTP_RX_CTRL(1U)
+
+
struct fw_rss_ind_tbl_cmd {
__be32 op_to_viid;
__be32 retval_len16;
@@ -8351,7 +8809,7 @@ enum fw_devlog_facility {
FW_DEVLOG_FACILITY_FOISCSI = 0x30,
FW_DEVLOG_FACILITY_FOFCOE = 0x32,
FW_DEVLOG_FACILITY_CHNET = 0x34,
- FW_DEVLOG_FACILITY_COiSCSI = 0x36,
+ FW_DEVLOG_FACILITY_COISCSI = 0x36,
FW_DEVLOG_FACILITY_MAX = 0x38,
};
@@ -8447,6 +8905,12 @@ struct fw_clip_cmd {
(((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
#define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
+#define S_FW_CLIP_CMD_INDEX 16
+#define M_FW_CLIP_CMD_INDEX 0x1fff
+#define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX)
+#define G_FW_CLIP_CMD_INDEX(x) \
+ (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX)
+
/******************************************************************************
* F O i S C S I C O M M A N D s
**************************************/
@@ -8469,7 +8933,8 @@ struct fw_chnet_iface_cmd {
__be32 op_to_portid;
__be32 retval_len16;
__u8 subop;
- __u8 r2[3];
+ __u8 r2[2];
+ __u8 flags;
__be32 ifid_ifstate;
__be16 mtu;
__be16 vlanid;
@@ -8892,7 +9357,8 @@ struct fw_dcb_ieee_cmd {
} dcbx_app_stats;
struct fw_dcbx_control {
__be32 multi_peer_invalidated;
- __be32 r5_lo;
+ __u8 version;
+ __u8 r6[3];
} dcbx_control;
} u;
};
@@ -9178,6 +9644,59 @@ struct fw_diag_cmd {
#define G_FW_DIAG_CMD_TYPE(x) \
(((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
+struct fw_hma_cmd {
+ __be32 op_pkd;
+ __be32 retval_len16;
+ __be32 mode_to_pcie_params;
+ __be32 naddr_size;
+ __be32 addr_size_pkd;
+ __be32 r6;
+ __be64 phy_address[5];
+};
+
+#define S_FW_HMA_CMD_MODE 31
+#define M_FW_HMA_CMD_MODE 0x1
+#define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE)
+#define G_FW_HMA_CMD_MODE(x) \
+ (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE)
+#define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U)
+
+#define S_FW_HMA_CMD_SOC 30
+#define M_FW_HMA_CMD_SOC 0x1
+#define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC)
+#define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC)
+#define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U)
+
+#define S_FW_HMA_CMD_EOC 29
+#define M_FW_HMA_CMD_EOC 0x1
+#define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC)
+#define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC)
+#define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U)
+
+#define S_FW_HMA_CMD_PCIE_PARAMS 0
+#define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff
+#define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS)
+#define G_FW_HMA_CMD_PCIE_PARAMS(x) \
+ (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS)
+
+#define S_FW_HMA_CMD_NADDR 12
+#define M_FW_HMA_CMD_NADDR 0x3f
+#define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR)
+#define G_FW_HMA_CMD_NADDR(x) \
+ (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR)
+
+#define S_FW_HMA_CMD_SIZE 0
+#define M_FW_HMA_CMD_SIZE 0xfff
+#define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE)
+#define G_FW_HMA_CMD_SIZE(x) \
+ (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE)
+
+#define S_FW_HMA_CMD_ADDR_SIZE 11
+#define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff
+#define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE)
+#define G_FW_HMA_CMD_ADDR_SIZE(x) \
+ (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE)
+
/******************************************************************************
* P C I E F W R E G I S T E R
**************************************/
@@ -9453,4 +9972,19 @@ enum {
FW_EPHY_HDR_MAGIC = 0x65706879,
};
+struct fw_ifconf_dhcp_info {
+ __be32 addr;
+ __be32 mask;
+ __be16 vlanid;
+ __be16 mtu;
+ __be32 gw;
+ __u8 op;
+ __u8 len;
+ __u8 data[270];
+};
+
+struct fw_ifconf_ping_info {
+ __be16 ping_pldsize;
+};
+
#endif /* _T4FW_INTERFACE_H_ */
diff --git a/usr/src/uts/common/io/cxgbe/firmware/t4fw_version.h b/usr/src/uts/common/io/cxgbe/firmware/t4fw_version.h
index 7402feb55d..488b8acf42 100644
--- a/usr/src/uts/common/io/cxgbe/firmware/t4fw_version.h
+++ b/usr/src/uts/common/io/cxgbe/firmware/t4fw_version.h
@@ -13,7 +13,7 @@
enum {
T4FW_VERSION_MAJOR = 0x01,
- T4FW_VERSION_MINOR = 0x17,
- T4FW_VERSION_MICRO = 0x04,
+ T4FW_VERSION_MINOR = 0x18,
+ T4FW_VERSION_MICRO = 0x03,
T4FW_VERSION_BUILD = 0x00,
};
diff --git a/usr/src/uts/common/io/cxgbe/firmware/t5_fw.c b/usr/src/uts/common/io/cxgbe/firmware/t5_fw.c
index 1ce1b1dee8..69b8a56254 100644
--- a/usr/src/uts/common/io/cxgbe/firmware/t5_fw.c
+++ b/usr/src/uts/common/io/cxgbe/firmware/t5_fw.c
@@ -3,41221 +3,41382 @@
*/
unsigned char t5fw_data[] = {
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+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
};
int t5fw_size = sizeof(t5fw_data);
diff --git a/usr/src/uts/common/io/cxgbe/firmware/t5_fw.h b/usr/src/uts/common/io/cxgbe/firmware/t5_fw.h
index 462e85f2c7..41536d817e 100644
--- a/usr/src/uts/common/io/cxgbe/firmware/t5_fw.h
+++ b/usr/src/uts/common/io/cxgbe/firmware/t5_fw.h
@@ -6,8 +6,8 @@
#define __T5FW_H
#define T5FW_VERSION_MAJOR 1
-#define T5FW_VERSION_MINOR 23
-#define T5FW_VERSION_MICRO 4
+#define T5FW_VERSION_MINOR 24
+#define T5FW_VERSION_MICRO 3
#define T5FW_VERSION_BUILD 0
extern unsigned char t5fw_data[];
diff --git a/usr/src/uts/common/io/cxgbe/firmware/t5fw_version.h b/usr/src/uts/common/io/cxgbe/firmware/t5fw_version.h
index 4092b4c63d..ec342390d5 100644
--- a/usr/src/uts/common/io/cxgbe/firmware/t5fw_version.h
+++ b/usr/src/uts/common/io/cxgbe/firmware/t5fw_version.h
@@ -13,7 +13,7 @@
enum {
T5FW_VERSION_MAJOR = 0x01,
- T5FW_VERSION_MINOR = 0x17,
- T5FW_VERSION_MICRO = 0x04,
+ T5FW_VERSION_MINOR = 0x18,
+ T5FW_VERSION_MICRO = 0x03,
T5FW_VERSION_BUILD = 0x00,
};
diff --git a/usr/src/uts/common/io/cxgbe/firmware/t6_fw.c b/usr/src/uts/common/io/cxgbe/firmware/t6_fw.c
index c624fb7e46..14639f6d32 100644
--- a/usr/src/uts/common/io/cxgbe/firmware/t6_fw.c
+++ b/usr/src/uts/common/io/cxgbe/firmware/t6_fw.c
@@ -3,44293 +3,44646 @@
*/
unsigned char t6fw_data[] = {
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+ 0x30, 0x2c, 0x73, 0x6f, 0x63, 0x6b, 0x65, 0x74, 0x6e, 0x75, 0x6d, 0x2c, 0x35, 0x0a, 0x5b, 0x66,
+ 0x69, 0x6e, 0x69, 0x5d, 0x0a, 0x76, 0x65, 0x72, 0x73, 0x69, 0x6f, 0x6e, 0x3d, 0x30, 0x78, 0x31,
+ 0x34, 0x32, 0x35, 0x30, 0x30, 0x31, 0x64, 0x0a, 0x63, 0x68, 0x65, 0x63, 0x6b, 0x73, 0x75, 0x6d,
+ 0x3d, 0x30, 0x78, 0x31, 0x34, 0x30, 0x39, 0x33, 0x37, 0x63, 0x39, 0x0a, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
};
int t6fw_size = sizeof(t6fw_data);
diff --git a/usr/src/uts/common/io/cxgbe/firmware/t6_fw.h b/usr/src/uts/common/io/cxgbe/firmware/t6_fw.h
index 7ede51e6d6..cec45d3479 100644
--- a/usr/src/uts/common/io/cxgbe/firmware/t6_fw.h
+++ b/usr/src/uts/common/io/cxgbe/firmware/t6_fw.h
@@ -6,8 +6,8 @@
#define __T6FW_H
#define T6FW_VERSION_MAJOR 1
-#define T6FW_VERSION_MINOR 23
-#define T6FW_VERSION_MICRO 4
+#define T6FW_VERSION_MINOR 24
+#define T6FW_VERSION_MICRO 3
#define T6FW_VERSION_BUILD 0
extern unsigned char t6fw_data[];
diff --git a/usr/src/uts/common/io/cxgbe/firmware/t6fw_version.h b/usr/src/uts/common/io/cxgbe/firmware/t6fw_version.h
index a06b41d001..f022d79504 100644
--- a/usr/src/uts/common/io/cxgbe/firmware/t6fw_version.h
+++ b/usr/src/uts/common/io/cxgbe/firmware/t6fw_version.h
@@ -13,7 +13,7 @@
enum {
T6FW_VERSION_MAJOR = 0x01,
- T6FW_VERSION_MINOR = 0x17,
- T6FW_VERSION_MICRO = 0x04,
+ T6FW_VERSION_MINOR = 0x18,
+ T6FW_VERSION_MICRO = 0x03,
T6FW_VERSION_BUILD = 0x00,
};
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/adapter.h b/usr/src/uts/common/io/cxgbe/t4nex/adapter.h
index 14f4fc9d75..48edc44341 100644
--- a/usr/src/uts/common/io/cxgbe/t4nex/adapter.h
+++ b/usr/src/uts/common/io/cxgbe/t4nex/adapter.h
@@ -121,6 +121,7 @@ struct port_info {
uint8_t port_id;
uint8_t tx_chan;
uint8_t rx_chan;
+ uint8_t rx_cchan;
uint8_t instance; /* Associated adapter instance */
uint8_t child_inst; /* Associated child instance */
uint8_t tmr_idx;
@@ -133,6 +134,14 @@ struct port_info {
u16 viid_mirror;
kstat_t *ksp_config;
kstat_t *ksp_info;
+
+ u8 vivld;
+ u8 vin;
+ u8 smt_idx;
+
+ u8 vivld_mirror;
+ u8 vin_mirror;
+ u8 smt_idx_mirror;
};
struct fl_sdesc {
@@ -714,7 +723,7 @@ t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
static inline bool
is_10G_port(const struct port_info *pi)
{
- return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
+ return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) != 0);
}
static inline struct sge_rxq *
@@ -726,19 +735,19 @@ iq_to_rxq(struct sge_iq *iq)
static inline bool
is_25G_port(const struct port_info *pi)
{
- return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
+ return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) != 0);
}
static inline bool
is_40G_port(const struct port_info *pi)
{
- return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
+ return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) != 0);
}
static inline bool
is_100G_port(const struct port_info *pi)
{
- return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
+ return ((pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) != 0);
}
static inline bool
@@ -881,4 +890,6 @@ int t4_addmac(void *arg, const uint8_t *ucaddr);
int t4_ioctl(struct adapter *sc, int cmd, void *data, int mode);
struct l2t_data *t4_init_l2t(struct adapter *sc);
+int begin_synchronized_op(struct port_info *pi, int hold, int waitok);
+void end_synchronized_op(struct port_info *pi, int held);
#endif /* __CXGBE_ADAPTER_H */
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/cudbg.c b/usr/src/uts/common/io/cxgbe/t4nex/cudbg.c
new file mode 100644
index 0000000000..2ad526b7d5
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/cudbg.c
@@ -0,0 +1,80 @@
+#include "cudbg.h"
+
+void
+init_cudbg_hdr(struct cudbg_init_hdr *hdr)
+{
+ hdr->major_ver = CUDBG_MAJOR_VERSION;
+ hdr->minor_ver = CUDBG_MINOR_VERSION;
+ hdr->build_ver = CUDBG_BUILD_VERSION;
+ hdr->init_struct_size = sizeof(struct cudbg_init);
+}
+
+/**
+ * cudbg_alloc_handle - Allocates and initializes a handle that represents
+ * cudbg state. Needs to called first before calling any other function.
+ *
+ * returns a pointer to memory that has a cudbg_init structure at the begining
+ * and enough space after that for internal book keeping.
+ */
+
+void *
+cudbg_alloc_handle(void)
+{
+ struct cudbg_private *handle;
+
+#ifdef _KERNEL
+ handle = kmem_zalloc(sizeof(*handle), KM_NOSLEEP);
+#else
+ handle = malloc(sizeof(*handle));
+#endif
+
+ if (handle == NULL)
+ return NULL;
+
+ init_cudbg_hdr(&handle->dbg_init.header);
+
+ return (handle);
+}
+
+/**
+ * cudbg_free_handle - Release cudbg resources.
+ * ## Parameters ##
+ * @handle : A pointer returned by cudbg_alloc_handle.
+ */
+void
+cudbg_free_handle(void *handle)
+{
+#ifdef _KERNEL
+ kmem_free(handle, sizeof(struct cudbg_private));
+#else
+ free(handle);
+#endif
+}
+
+/********************************* Helper functions *************************/
+void
+set_dbg_bitmap(u8 *bitmap, enum CUDBG_DBG_ENTITY_TYPE type)
+{
+ int index = type / 8;
+ int bit = type % 8;
+
+ bitmap[index] |= (1 << bit);
+}
+
+void
+reset_dbg_bitmap(u8 *bitmap, enum CUDBG_DBG_ENTITY_TYPE type)
+{
+ int index = type / 8;
+ int bit = type % 8;
+
+ bitmap[index] &= ~(1 << bit);
+}
+
+/********************************* End of Helper functions
+ * *************************/
+
+struct cudbg_init *
+cudbg_get_init(void *handle)
+{
+ return (handle);
+}
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/cudbg.h b/usr/src/uts/common/io/cxgbe/t4nex/cudbg.h
new file mode 100644
index 0000000000..cb21451e5c
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/cudbg.h
@@ -0,0 +1,447 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*-
+ * Copyright (c) 2019 Chelsio Communications, Inc.
+ * All rights reserved.
+ * * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Chelsio Unified Debug Interface header file.
+ * Version 1.1
+ */
+#ifndef _CUDBG_IF_H_
+#define _CUDBG_IF_H_
+
+#ifndef _KERNEL
+#include <stdlib.h>
+#endif
+
+#include "cudbg_lib_common.h"
+
+#ifdef __GNUC__
+#define ATTRIBUTE_UNUSED __attribute__ ((unused))
+#else
+#define ATTRIBUTE_UNUSED
+#endif
+
+#if defined(CONFIG_CUDBG_DEBUG)
+#define cudbg_debug(pdbg_init, format, ...) do {\
+ pdbg_init->print(format, ##__VA_ARGS__); \
+} while (0)
+#else
+#define cudbg_debug(pdbg_init, format, ...) do { } while (0)
+#endif
+
+#define OUT
+#define IN
+#define INOUT
+
+/* Error codes */
+
+#define CUDBG_STATUS_SUCCESS 0
+#define CUDBG_STATUS_NOSPACE -2
+#define CUDBG_STATUS_FLASH_WRITE_FAIL -3
+#define CUDBG_STATUS_FLASH_READ_FAIL -4
+#define CUDBG_STATUS_UNDEFINED_OUT_BUF -5
+#define CUDBG_STATUS_UNDEFINED_CBFN -6
+#define CUDBG_STATUS_UNDEFINED_PRINTF_CBFN -7
+#define CUDBG_STATUS_ADAP_INVALID -8
+#define CUDBG_STATUS_FLASH_EMPTY -9
+#define CUDBG_STATUS_NO_ADAPTER -10
+#define CUDBG_STATUS_NO_SIGNATURE -11
+#define CUDBG_STATUS_MULTIPLE_REG -12
+#define CUDBG_STATUS_UNREGISTERED -13
+#define CUDBG_STATUS_UNDEFINED_ENTITY -14
+#define CUDBG_STATUS_REG_FAIlED -15
+#define CUDBG_STATUS_DEVLOG_FAILED -16
+#define CUDBG_STATUS_SMALL_BUFF -17
+#define CUDBG_STATUS_CHKSUM_MISSMATCH -18
+#define CUDBG_STATUS_NO_SCRATCH_MEM -19
+#define CUDBG_STATUS_OUTBUFF_OVERFLOW -20
+#define CUDBG_STATUS_INVALID_BUFF -21 /* Invalid magic */
+#define CUDBG_STATUS_FILE_OPEN_FAIL -22
+#define CUDBG_STATUS_DEVLOG_INT_FAIL -23
+#define CUDBG_STATUS_ENTITY_NOT_FOUND -24
+#define CUDBG_STATUS_DECOMPRESS_FAIL -25
+#define CUDBG_STATUS_BUFFER_SHORT -26
+#define CUDBG_METADATA_VERSION_MISMATCH -27
+#define CUDBG_STATUS_NOT_IMPLEMENTED -28
+#define CUDBG_SYSTEM_ERROR -29
+#define CUDBG_STATUS_MMAP_FAILED -30
+#define CUDBG_STATUS_FILE_WRITE_FAILED -31
+#define CUDBG_STATUS_CCLK_NOT_DEFINED -32
+#define CUDBG_STATUS_FLASH_FULL -33
+#define CUDBG_STATUS_SECTOR_EMPTY -34
+#define CUDBG_STATUS_ENTITY_NOT_REQUESTED -35
+#define CUDBG_STATUS_NOT_SUPPORTED -36
+#define CUDBG_STATUS_FILE_READ_FAILED -37
+#define CUDBG_STATUS_CORRUPTED -38
+#define CUDBG_STATUS_INVALID_INDEX -39
+
+#define CUDBG_MAJOR_VERSION 1
+#define CUDBG_MINOR_VERSION 14
+#define CUDBG_BUILD_VERSION 0
+
+#define CUDBG_FILE_NAME_LEN 256
+#define CUDBG_DIR_NAME_LEN 256
+#define CUDBG_MAX_BITMAP_LEN 16
+
+static char ATTRIBUTE_UNUSED * err_msg[] = {
+ "Success",
+ "Unknown",
+ "No space",
+ "Flash write fail",
+ "Flash read fail",
+ "Undefined out buf",
+ "Callback function undefined",
+ "Print callback function undefined",
+ "ADAP invalid",
+ "Flash empty",
+ "No adapter",
+ "No signature",
+ "Multiple registration",
+ "Unregistered",
+ "Undefined entity",
+ "Reg failed",
+ "Devlog failed",
+ "Small buff",
+ "Checksum mismatch",
+ "No scratch memory",
+ "Outbuff overflow",
+ "Invalid buffer",
+ "File open fail",
+ "Devlog int fail",
+ "Entity not found",
+ "Decompress fail",
+ "Buffer short",
+ "Version mismatch",
+ "Not implemented",
+ "System error",
+ "Mmap failed",
+ "File write failed",
+ "cclk not defined",
+ "Flash full",
+ "Sector empty",
+ "Entity not requested",
+ "Not supported",
+ "File read fail",
+ "Corrupted",
+ "Invalid Index"
+};
+
+enum CUDBG_DBG_ENTITY_TYPE {
+ CUDBG_ALL = 0,
+ CUDBG_REG_DUMP = 1,
+ CUDBG_DEV_LOG = 2,
+ CUDBG_CIM_LA = 3,
+ CUDBG_CIM_MA_LA = 4,
+ CUDBG_CIM_QCFG = 5,
+ CUDBG_CIM_IBQ_TP0 = 6,
+ CUDBG_CIM_IBQ_TP1 = 7,
+ CUDBG_CIM_IBQ_ULP = 8,
+ CUDBG_CIM_IBQ_SGE0 = 9,
+ CUDBG_CIM_IBQ_SGE1 = 10,
+ CUDBG_CIM_IBQ_NCSI = 11,
+ CUDBG_CIM_OBQ_ULP0 = 12,
+ CUDBG_CIM_OBQ_ULP1 = 13,
+ CUDBG_CIM_OBQ_ULP2 = 14,
+ CUDBG_CIM_OBQ_ULP3 = 15,
+ CUDBG_CIM_OBQ_SGE = 16,
+ CUDBG_CIM_OBQ_NCSI = 17,
+ CUDBG_EDC0 = 18,
+ CUDBG_EDC1 = 19,
+ CUDBG_MC0 = 20,
+ CUDBG_MC1 = 21,
+ CUDBG_RSS = 22,
+ CUDBG_RSS_PF_CONF = 23,
+ CUDBG_RSS_KEY = 24,
+ CUDBG_RSS_VF_CONF = 25,
+ CUDBG_RSS_CONF = 26,
+ CUDBG_PATH_MTU = 27,
+ CUDBG_SW_STATE = 28,
+ CUDBG_WTP = 29,
+ CUDBG_PM_STATS = 30,
+ CUDBG_HW_SCHED = 31,
+ CUDBG_TCP_STATS = 32,
+ CUDBG_TP_ERR_STATS = 33,
+ CUDBG_FCOE_STATS = 34,
+ CUDBG_RDMA_STATS = 35,
+ CUDBG_TP_INDIRECT = 36,
+ CUDBG_SGE_INDIRECT = 37,
+ CUDBG_CPL_STATS = 38,
+ CUDBG_DDP_STATS = 39,
+ CUDBG_WC_STATS = 40,
+ CUDBG_ULPRX_LA = 41,
+ CUDBG_LB_STATS = 42,
+ CUDBG_TP_LA = 43,
+ CUDBG_MEMINFO = 44,
+ CUDBG_CIM_PIF_LA = 45,
+ CUDBG_CLK = 46,
+ CUDBG_CIM_OBQ_RXQ0 = 47,
+ CUDBG_CIM_OBQ_RXQ1 = 48,
+ CUDBG_MAC_STATS = 49,
+ CUDBG_PCIE_INDIRECT = 50,
+ CUDBG_PM_INDIRECT = 51,
+ CUDBG_FULL = 52,
+ CUDBG_TX_RATE = 53,
+ CUDBG_TID_INFO = 54,
+ CUDBG_PCIE_CONFIG = 55,
+ CUDBG_DUMP_CONTEXT = 56,
+ CUDBG_MPS_TCAM = 57,
+ CUDBG_VPD_DATA = 58,
+ CUDBG_LE_TCAM = 59,
+ CUDBG_CCTRL = 60,
+ CUDBG_MA_INDIRECT = 61,
+ CUDBG_ULPTX_LA = 62,
+ CUDBG_EXT_ENTITY = 63,
+ CUDBG_UP_CIM_INDIRECT = 64,
+ CUDBG_PBT_TABLE = 65,
+ CUDBG_MBOX_LOG = 66,
+ CUDBG_HMA_INDIRECT = 67,
+ CUDBG_MAX_ENTITY = 68,
+};
+
+#define ENTITY_FLAG_NULL 0
+#define ENTITY_FLAG_REGISTER 1
+#define ENTITY_FLAG_BINARY 2
+#define ENTITY_FLAG_FW_NO_ATTACH 3
+
+/* file_name matches Linux cxgb4 debugfs entry names. */
+struct el {char *name; char *file_name; int bit; u32 flag; };
+static struct el ATTRIBUTE_UNUSED entity_list[] = {
+ {"all", "all", CUDBG_ALL, ENTITY_FLAG_NULL},
+ {"regdump", "regdump", CUDBG_REG_DUMP, 1 << ENTITY_FLAG_REGISTER},
+ {"devlog", "devlog", CUDBG_DEV_LOG, ENTITY_FLAG_NULL},
+ {"cimla", "cim_la", CUDBG_CIM_LA, ENTITY_FLAG_NULL},
+ {"cimmala", "cim_ma_la", CUDBG_CIM_MA_LA, ENTITY_FLAG_NULL},
+ {"cimqcfg", "cim_qcfg", CUDBG_CIM_QCFG, ENTITY_FLAG_NULL},
+ {"ibqtp0", "ibq_tp0", CUDBG_CIM_IBQ_TP0, ENTITY_FLAG_NULL},
+ {"ibqtp1", "ibq_tp1", CUDBG_CIM_IBQ_TP1, ENTITY_FLAG_NULL},
+ {"ibqulp", "ibq_ulp", CUDBG_CIM_IBQ_ULP, ENTITY_FLAG_NULL},
+ {"ibqsge0", "ibq_sge0", CUDBG_CIM_IBQ_SGE0, ENTITY_FLAG_NULL},
+ {"ibqsge1", "ibq_sge1", CUDBG_CIM_IBQ_SGE1, ENTITY_FLAG_NULL},
+ {"ibqncsi", "ibq_ncsi", CUDBG_CIM_IBQ_NCSI, ENTITY_FLAG_NULL},
+ {"obqulp0", "obq_ulp0", CUDBG_CIM_OBQ_ULP0, ENTITY_FLAG_NULL},
+ {"obqulp1", "obq_ulp1", CUDBG_CIM_OBQ_ULP1, ENTITY_FLAG_NULL},
+ {"obqulp2", "obq_ulp2", CUDBG_CIM_OBQ_ULP2, ENTITY_FLAG_NULL},
+ {"obqulp3", "obq_ulp3", CUDBG_CIM_OBQ_ULP3, ENTITY_FLAG_NULL},
+ {"obqsge", "obq_sge", CUDBG_CIM_OBQ_SGE, ENTITY_FLAG_NULL},
+ {"obqncsi", "obq_ncsi", CUDBG_CIM_OBQ_NCSI, ENTITY_FLAG_NULL},
+ {"edc0", "edc0", CUDBG_EDC0, (1 << ENTITY_FLAG_BINARY)},
+ {"edc1", "edc1", CUDBG_EDC1, (1 << ENTITY_FLAG_BINARY)},
+ {"mc0", "mc0", CUDBG_MC0, (1 << ENTITY_FLAG_BINARY)},
+ {"mc1", "mc1", CUDBG_MC1, (1 << ENTITY_FLAG_BINARY)},
+ {"rss", "rss", CUDBG_RSS, ENTITY_FLAG_NULL},
+ {"rss_pf_config", "rss_pf_config", CUDBG_RSS_PF_CONF, ENTITY_FLAG_NULL},
+ {"rss_key", "rss_key", CUDBG_RSS_KEY, ENTITY_FLAG_NULL},
+ {"rss_vf_config", "rss_vf_config", CUDBG_RSS_VF_CONF, ENTITY_FLAG_NULL},
+ {"rss_config", "rss_config", CUDBG_RSS_CONF, ENTITY_FLAG_NULL},
+ {"pathmtu", "path_mtus", CUDBG_PATH_MTU, ENTITY_FLAG_NULL},
+ {"swstate", "sw_state", CUDBG_SW_STATE, ENTITY_FLAG_NULL},
+ {"wtp", "wtp", CUDBG_WTP, ENTITY_FLAG_NULL},
+ {"pmstats", "pm_stats", CUDBG_PM_STATS, ENTITY_FLAG_NULL},
+ {"hwsched", "hw_sched", CUDBG_HW_SCHED, ENTITY_FLAG_NULL},
+ {"tcpstats", "tcp_stats", CUDBG_TCP_STATS, ENTITY_FLAG_NULL},
+ {"tperrstats", "tp_err_stats", CUDBG_TP_ERR_STATS, ENTITY_FLAG_NULL},
+ {"fcoestats", "fcoe_stats", CUDBG_FCOE_STATS, ENTITY_FLAG_NULL},
+ {"rdmastats", "rdma_stats", CUDBG_RDMA_STATS, ENTITY_FLAG_NULL},
+ {"tpindirect", "tp_indirect", CUDBG_TP_INDIRECT,
+ 1 << ENTITY_FLAG_REGISTER},
+ {"sgeindirect", "sge_indirect", CUDBG_SGE_INDIRECT,
+ 1 << ENTITY_FLAG_REGISTER},
+ {"cplstats", "cpl_stats", CUDBG_CPL_STATS, ENTITY_FLAG_NULL},
+ {"ddpstats", "ddp_stats", CUDBG_DDP_STATS, ENTITY_FLAG_NULL},
+ {"wcstats", "wc_stats", CUDBG_WC_STATS, ENTITY_FLAG_NULL},
+ {"ulprxla", "ulprx_la", CUDBG_ULPRX_LA, ENTITY_FLAG_NULL},
+ {"lbstats", "lb_stats", CUDBG_LB_STATS, ENTITY_FLAG_NULL},
+ {"tpla", "tp_la", CUDBG_TP_LA, ENTITY_FLAG_NULL},
+ {"meminfo", "meminfo", CUDBG_MEMINFO, ENTITY_FLAG_NULL},
+ {"cimpifla", "cim_pif_la", CUDBG_CIM_PIF_LA, ENTITY_FLAG_NULL},
+ {"clk", "clk", CUDBG_CLK, ENTITY_FLAG_NULL},
+ {"obq_sge_rx_q0", "obq_sge_rx_q0", CUDBG_CIM_OBQ_RXQ0,
+ ENTITY_FLAG_NULL},
+ {"obq_sge_rx_q1", "obq_sge_rx_q1", CUDBG_CIM_OBQ_RXQ1,
+ ENTITY_FLAG_NULL},
+ {"macstats", "mac_stats", CUDBG_MAC_STATS, ENTITY_FLAG_NULL},
+ {"pcieindirect", "pcie_indirect", CUDBG_PCIE_INDIRECT,
+ 1 << ENTITY_FLAG_REGISTER},
+ {"pmindirect", "pm_indirect", CUDBG_PM_INDIRECT,
+ 1 << ENTITY_FLAG_REGISTER},
+ {"full", "full", CUDBG_FULL, ENTITY_FLAG_NULL},
+ {"txrate", "tx_rate", CUDBG_TX_RATE, ENTITY_FLAG_NULL},
+ {"tidinfo", "tids", CUDBG_TID_INFO, ENTITY_FLAG_NULL |
+ (1 << ENTITY_FLAG_FW_NO_ATTACH)},
+ {"pcieconfig", "pcie_config", CUDBG_PCIE_CONFIG, ENTITY_FLAG_NULL},
+ {"dumpcontext", "dump_context", CUDBG_DUMP_CONTEXT, ENTITY_FLAG_NULL},
+ {"mpstcam", "mps_tcam", CUDBG_MPS_TCAM, ENTITY_FLAG_NULL},
+ {"vpddata", "vpd_data", CUDBG_VPD_DATA, ENTITY_FLAG_NULL},
+ {"letcam", "le_tcam", CUDBG_LE_TCAM, ENTITY_FLAG_NULL},
+ {"cctrl", "cctrl", CUDBG_CCTRL, ENTITY_FLAG_NULL},
+ {"maindirect", "ma_indirect", CUDBG_MA_INDIRECT,
+ 1 << ENTITY_FLAG_REGISTER},
+ {"ulptxla", "ulptx_la", CUDBG_ULPTX_LA, ENTITY_FLAG_NULL},
+ {"extentity", "ext_entity", CUDBG_EXT_ENTITY, ENTITY_FLAG_NULL},
+ {"upcimindirect", "up_cim_indirect", CUDBG_UP_CIM_INDIRECT,
+ 1 << ENTITY_FLAG_REGISTER},
+ {"pbttables", "pbt_tables", CUDBG_PBT_TABLE, ENTITY_FLAG_NULL},
+ {"mboxlog", "mboxlog", CUDBG_MBOX_LOG, ENTITY_FLAG_NULL},
+ {"hmaindirect", "hma_indirect", CUDBG_HMA_INDIRECT,
+ 1 << ENTITY_FLAG_REGISTER},
+};
+
+#ifdef _KERNEL
+typedef int (*cudbg_print_cb) (dev_info_t *dip, ...);
+#else
+typedef int (*cudbg_print_cb) (char *, ...);
+#endif
+
+struct cudbg_init_hdr {
+ u8 major_ver;
+ u8 minor_ver;
+ u8 build_ver;
+ u8 res;
+ u16 init_struct_size;
+};
+
+struct cudbg_flash_hdr {
+ u32 signature;
+ u8 major_ver;
+ u8 minor_ver;
+ u8 build_ver;
+ u8 res;
+ u64 timestamp;
+ u64 time_res;
+ u32 hdr_len;
+ u32 data_len;
+ u32 hdr_flags;
+ u32 sec_seq_no;
+ u32 reserved[22];
+};
+
+struct cudbg_param {
+ u16 param_type;
+ u16 reserved;
+ union {
+ struct {
+ u32 memtype; /* which memory (EDC0, EDC1, MC) */
+ u32 start; /* start of log in firmware memory */
+ u32 size; /* size of log */
+ } devlog_param;
+ struct {
+ struct mbox_cmd_log *log;
+ u16 mbox_cmds;
+ } mboxlog_param;
+ struct {
+ u8 caller_string[100];
+ u8 os_type;
+ } sw_state_param;
+ u64 time;
+ u8 tcb_bit_param;
+ void *adap;
+ void *access_lock;
+ } u;
+};
+
+/* params for tcb_bit_param */
+#define CUDBG_TCB_BRIEF_PARAM 0x1
+#define CUDBG_TCB_FROM_CARD_PARAM 0x2
+#define CUDBG_TCB_AS_SCB_PARAM 0x4
+
+enum {
+ /* params for os_type */
+ CUDBG_OS_TYPE_WINDOWS = 1,
+ CUDBG_OS_TYPE_LINUX = 2,
+ CUDBG_OS_TYPE_ESX = 3,
+ CUDBG_OS_TYPE_UNKNOWN = 4,
+};
+
+/*
+ * * What is OFFLINE_VIEW_ONLY mode?
+ *
+ * cudbg frame work will be used only to interpret previously collected
+ * data store in a file (i.e NOT hw flash)
+ */
+
+struct cudbg_init {
+ struct cudbg_init_hdr header;
+ struct adapter *adap; /* Pointer to adapter structure
+ with filled fields */
+ cudbg_print_cb print; /* Platform dependent print
+ function */
+ u32 verbose:1; /* Turn on verbose print */
+ u32 use_flash:1; /* Use flash to collect or view
+ debug */
+ u32 full_mode:1; /* If set, cudbg will pull in
+ common code */
+ u32 no_compress:1; /* Dont compress will storing
+ the collected debug */
+ u32 info:1; /* Show just the info, Dont
+ interpret */
+ u32 reserved:27;
+ u8 dbg_bitmap[CUDBG_MAX_BITMAP_LEN];
+ /* Bit map to select the dbg
+ data type to be collected
+ or viewed */
+};
+
+struct cudbg_private {
+ struct cudbg_init dbg_init;
+#ifdef _KERNEL
+ struct cudbg_flash_sec_info sec_info;
+#endif
+};
+
+/********************************* Helper functions *************************/
+void set_dbg_bitmap(u8 *bitmap, enum CUDBG_DBG_ENTITY_TYPE type);
+void reset_dbg_bitmap(u8 *bitmap, enum CUDBG_DBG_ENTITY_TYPE type);
+struct cudbg_init * cudbg_get_init(void *handle);
+
+/**
+ * cudbg_collect - Collect and store debug information.
+ * ## Parameters ##
+ * @handle : A pointer returned by cudbg_alloc_handle.
+ * @outbuf : pointer to output buffer, to store the collected information
+ * or to use it as a scratch buffer in case HW flash is used to
+ * store the debug information.
+ * @outbuf_size : Size of output buffer.
+ * ## Return ##
+ * If the function succeeds, the return value will be size of debug information
+ * collected and stored.
+ * -ve value represent error.
+ */
+int cudbg_collect(void *handle, void *outbuf, u32 *outbuf_size);
+
+int cudbg_view(void *handle, void *pinbuf, u32 inbuf_size,
+ void *poutbuf, s64 *poutbuf_size);
+void init_cudbg_hdr(struct cudbg_init_hdr *hdr);
+void * cudbg_alloc_handle(void);
+void cudbg_free_handle(void *handle);
+#endif /* _CUDBG_IF_H_ */
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/cudbg_common.c b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_common.c
new file mode 100644
index 0000000000..e654d8e1cc
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_common.c
@@ -0,0 +1,85 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*-
+ * Copyright (c) 2019 Chelsio Communications, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+
+#ifdef _KERNEL
+#include "common/common.h"
+#else
+#include <stdio.h>
+#include <string.h>
+#endif
+#include "cudbg.h"
+#include "cudbg_lib_common.h"
+
+int
+get_scratch_buff(struct cudbg_buffer *pdbg_buff, u32 size,
+ struct cudbg_buffer *pscratch_buff)
+{
+ u32 scratch_offset;
+ int rc = 0;
+
+ scratch_offset = pdbg_buff->size - size;
+
+ if (pdbg_buff->offset > (int)scratch_offset || pdbg_buff->size < size) {
+ rc = CUDBG_STATUS_NO_SCRATCH_MEM;
+ goto err;
+ } else {
+ pscratch_buff->data = (char *)pdbg_buff->data + scratch_offset;
+ pscratch_buff->offset = 0;
+ pscratch_buff->size = size;
+ pdbg_buff->size -= size;
+ }
+
+err:
+ return rc;
+}
+
+void
+release_scratch_buff(struct cudbg_buffer *pscratch_buff,
+ struct cudbg_buffer *pdbg_buff)
+{
+ pdbg_buff->size += pscratch_buff->size;
+ /* Reset the used buffer to zero.
+ * If we dont do this, then it will effect the ext entity logic.
+ */
+ memset(pscratch_buff->data, 0, pscratch_buff->size);
+ pscratch_buff->data = NULL;
+ pscratch_buff->offset = 0;
+ pscratch_buff->size = 0;
+}
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/cudbg_entity.h b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_entity.h
new file mode 100644
index 0000000000..5c47df53e6
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_entity.h
@@ -0,0 +1,980 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*-
+ * Copyright (c) 2017 Chelsio Communications, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __CUDBG_ENTITY_H__
+#define __CUDBG_ENTITY_H__
+
+#include "common.h"
+
+#ifdef __GNUC__
+#define ATTRIBUTE_UNUSED __attribute__ ((unused))
+#else
+#define ATTRIBUTE_UNUSED
+#endif
+
+#define MC0_FLAG 1
+#define MC1_FLAG 2
+#define EDC0_FLAG 3
+#define EDC1_FLAG 4
+
+#define NUM_PCIE_CONFIG_REGS 0x61
+#define CUDBG_CTXT_SIZE_BYTES 24
+#define CUDBG_MAX_INGRESS_QIDS 65536
+#define CUDBG_MAX_FL_QIDS 2048
+#define CUDBG_MAX_CNM_QIDS 1024
+#define CUDBG_LOWMEM_MAX_CTXT_QIDS 256
+#define ETH_ALEN 6
+#define CUDBG_MAX_RPLC_SIZE 128
+#define CUDBG_NUM_REQ_REGS 17
+#define CUDBG_MAX_TCAM_TID 0x800
+#define CUDBG_NUM_ULPTX 11
+
+#define SN_REG_ADDR 0x183f
+#define BN_REG_ADDR 0x1819
+#define NA_REG_ADDR 0x185a
+#define MN_REG_ADDR 0x1803
+
+#define A_MPS_VF_RPLCT_MAP0 0x1111c
+#define A_MPS_VF_RPLCT_MAP1 0x11120
+#define A_MPS_VF_RPLCT_MAP2 0x11124
+#define A_MPS_VF_RPLCT_MAP3 0x11128
+#define A_MPS_VF_RPLCT_MAP4 0x11300
+#define A_MPS_VF_RPLCT_MAP5 0x11304
+#define A_MPS_VF_RPLCT_MAP6 0x11308
+#define A_MPS_VF_RPLCT_MAP7 0x1130c
+
+#define PORT_TYPE_ADDR 0x1869
+#define PORT_TYPE_LEN 8
+
+/* For T6 */
+#define SN_T6_ADDR 0x83f
+#define BN_T6_ADDR 0x819
+#define NA_T6_ADDR 0x85a
+#define MN_T6_ADDR 0x803
+
+#define SN_MAX_LEN 24
+#define BN_MAX_LEN 16
+#define NA_MAX_LEN 12
+#define MN_MAX_LEN 16
+#define MAX_VPD_DATA_LEN 32
+
+#define VPD_VER_ADDR 0x18c7
+#define VPD_VER_LEN 2
+#define SCFG_VER_ADDR 0x06
+#define SCFG_VER_LEN 4
+
+#define CUDBG_CIM_BUSY_BIT (1 << 17)
+
+#define CUDBG_CHAC_PBT_ADDR 0x2800
+#define CUDBG_CHAC_PBT_LRF 0x3000
+#define CUDBG_CHAC_PBT_DATA 0x3800
+#define CUDBG_PBT_DYNAMIC_ENTRIES 8
+#define CUDBG_PBT_STATIC_ENTRIES 16
+#define CUDBG_LRF_ENTRIES 8
+#define CUDBG_PBT_DATA_ENTRIES 512
+
+#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
+#define CUDBG_TID_INFO_REV 1
+#define CUDBG_MAC_STATS_REV 1
+#define CUDBG_ULPTX_LA_REV 1
+#define CUDBG_MEMINFO_REV 1
+
+#define CUDBG_ULPTX_LA_REV 1
+
+#define CUDBG_T6_CLIP 1536
+#define CUDBG_MAX_TID_COMP_EN 6144
+#define CUDBG_MAX_TID_COMP_DIS 3072
+#define CUDBG_NUM_ULPTX_READ 512
+#define CUDBG_NUM_ULPTX_ASIC 6
+#define CUDBG_NUM_ULPTX_ASIC_READ 128
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(_a) (sizeof((_a)) / sizeof((_a)[0]))
+#endif
+
+enum cudbg_qdesc_qtype {
+ CUDBG_QTYPE_UNKNOWN = 0,
+ CUDBG_QTYPE_NIC_TXQ,
+ CUDBG_QTYPE_NIC_RXQ,
+ CUDBG_QTYPE_NIC_FLQ,
+ CUDBG_QTYPE_CTRLQ,
+ CUDBG_QTYPE_FWEVTQ,
+ CUDBG_QTYPE_INTRQ,
+ CUDBG_QTYPE_PTP_TXQ,
+ CUDBG_QTYPE_OFLD_TXQ,
+ CUDBG_QTYPE_RDMA_RXQ,
+ CUDBG_QTYPE_RDMA_FLQ,
+ CUDBG_QTYPE_RDMA_CIQ,
+ CUDBG_QTYPE_ISCSI_RXQ,
+ CUDBG_QTYPE_ISCSI_FLQ,
+ CUDBG_QTYPE_ISCSIT_RXQ,
+ CUDBG_QTYPE_ISCSIT_FLQ,
+ CUDBG_QTYPE_CRYPTO_TXQ,
+ CUDBG_QTYPE_CRYPTO_RXQ,
+ CUDBG_QTYPE_CRYPTO_FLQ,
+ CUDBG_QTYPE_TLS_RXQ,
+ CUDBG_QTYPE_TLS_FLQ,
+ CUDBG_QTYPE_MAX,
+};
+
+struct cudbg_pbt_tables {
+ u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
+ u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
+ u32 lrf_table[CUDBG_LRF_ENTRIES];
+ u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
+};
+
+struct card_mem {
+ u16 size_mc0;
+ u16 size_mc1;
+ u16 size_edc0;
+ u16 size_edc1;
+ u16 mem_flag;
+ u16 res;
+};
+
+struct rss_pf_conf {
+ u32 rss_pf_map;
+ u32 rss_pf_mask;
+ u32 rss_pf_config;
+};
+
+struct cudbg_ch_cntxt {
+ uint32_t cntxt_type;
+ uint32_t cntxt_id;
+ uint32_t data[SGE_CTXT_SIZE / 4];
+};
+
+struct cudbg_tcam {
+ u32 filter_start;
+ u32 server_start;
+ u32 clip_start;
+ u32 routing_start;
+ u32 tid_hash_base;
+ u32 max_tid;
+};
+
+struct cudbg_mbox_log {
+ struct mbox_cmd entry;
+ u32 hi[MBOX_LEN / 8];
+ u32 lo[MBOX_LEN / 8];
+};
+
+struct cudbg_tid_data {
+ u32 tid;
+ u32 dbig_cmd;
+ u32 dbig_conf;
+ u32 dbig_rsp_stat;
+ u32 data[CUDBG_NUM_REQ_REGS];
+};
+
+struct cudbg_cntxt_field {
+ char *name;
+ u32 start_bit;
+ u32 end_bit;
+ u32 shift;
+ u32 islog2;
+};
+
+struct cudbg_mps_tcam {
+ u64 mask;
+ u32 rplc[8];
+ u32 idx;
+ u32 cls_lo;
+ u32 cls_hi;
+ u32 rplc_size;
+ u32 vniy;
+ u32 vnix;
+ u32 dip_hit;
+ u32 vlan_vld;
+ u32 repli;
+ u16 ivlan;
+ u8 addr[ETH_ALEN];
+ u8 lookup_type;
+ u8 port_num;
+ u8 reserved[2];
+};
+
+struct rss_vf_conf {
+ u32 rss_vf_vfl;
+ u32 rss_vf_vfh;
+};
+
+struct rss_config {
+ u32 tp_rssconf; /* A_TP_RSS_CONFIG */
+ u32 tp_rssconf_tnl; /* A_TP_RSS_CONFIG_TNL */
+ u32 tp_rssconf_ofd; /* A_TP_RSS_CONFIG_OFD */
+ u32 tp_rssconf_syn; /* A_TP_RSS_CONFIG_SYN */
+ u32 tp_rssconf_vrt; /* A_TP_RSS_CONFIG_VRT */
+ u32 tp_rssconf_cng; /* A_TP_RSS_CONFIG_CNG */
+ u32 chip;
+};
+
+struct struct_pm_stats {
+ u32 tx_cnt[T6_PM_NSTATS];
+ u32 rx_cnt[T6_PM_NSTATS];
+ u64 tx_cyc[T6_PM_NSTATS];
+ u64 rx_cyc[T6_PM_NSTATS];
+};
+
+struct struct_hw_sched {
+ u32 kbps[NTX_SCHED];
+ u32 ipg[NTX_SCHED];
+ u32 pace_tab[NTX_SCHED];
+ u32 mode;
+ u32 map;
+};
+
+struct struct_tcp_stats {
+ struct tp_tcp_stats v4, v6;
+};
+
+struct struct_tp_err_stats {
+ struct tp_err_stats stats;
+ u32 nchan;
+};
+
+struct struct_tp_fcoe_stats {
+ struct tp_fcoe_stats stats[4];
+ u32 nchan;
+};
+
+struct struct_mac_stats {
+ u32 port_count;
+ struct port_stats stats[4];
+};
+
+struct struct_mac_stats_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ u32 port_count;
+ u32 reserved;
+ struct port_stats stats[4];
+};
+
+struct struct_tp_cpl_stats {
+ struct tp_cpl_stats stats;
+ u32 nchan;
+};
+
+struct struct_wc_stats {
+ u32 wr_cl_success;
+ u32 wr_cl_fail;
+};
+
+struct struct_ulptx_la {
+ u32 rdptr[CUDBG_NUM_ULPTX];
+ u32 wrptr[CUDBG_NUM_ULPTX];
+ u32 rddata[CUDBG_NUM_ULPTX];
+ u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
+ u32 rdptr_asic[CUDBG_NUM_ULPTX_ASIC_READ];
+ u32 rddata_asic[CUDBG_NUM_ULPTX_ASIC_READ][CUDBG_NUM_ULPTX_ASIC];
+};
+
+struct struct_ulprx_la {
+ u32 data[ULPRX_LA_SIZE * 8];
+ u32 size;
+};
+
+struct struct_cim_qcfg {
+ u8 chip;
+ u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
+ u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
+ u16 thres[CIM_NUM_IBQ];
+ u32 obq_wr[2 * CIM_NUM_OBQ_T5];
+ u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
+};
+
+enum region_index {
+ REGN_DBQ_CONTEXS_IDX,
+ REGN_IMSG_CONTEXTS_IDX,
+ REGN_FLM_CACHE_IDX,
+ REGN_TCBS_IDX,
+ REGN_PSTRUCT_IDX,
+ REGN_TIMERS_IDX,
+ REGN_RX_FL_IDX,
+ REGN_TX_FL_IDX,
+ REGN_PSTRUCT_FL_IDX,
+ REGN_TX_PAYLOAD_IDX,
+ REGN_RX_PAYLOAD_IDX,
+ REGN_LE_HASH_IDX,
+ REGN_ISCSI_IDX,
+ REGN_TDDP_IDX,
+ REGN_TPT_IDX,
+ REGN_STAG_IDX,
+ REGN_RQ_IDX,
+ REGN_RQUDP_IDX,
+ REGN_PBL_IDX,
+ REGN_TXPBL_IDX,
+ REGN_DBVFIFO_IDX,
+ REGN_ULPRX_STATE_IDX,
+ REGN_ULPTX_STATE_IDX,
+#ifndef __NO_DRIVER_OCQ_SUPPORT__
+ REGN_ON_CHIP_Q_IDX,
+#endif
+};
+
+struct cudbg_qdesc_info {
+ u32 qdesc_entry_size;
+ u32 num_queues;
+ u8 data[0]; /* Must be last */
+};
+
+static const char * const region[] = {
+ "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
+ "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
+ "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
+ "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
+ "RQUDP region:", "PBL region:", "TXPBL region:",
+ "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
+#ifndef __NO_DRIVER_OCQ_SUPPORT__
+ "On-chip queues:"
+#endif
+};
+
+/* Info relative to memory region (i.e. wrt 0). */
+struct struct_region_info {
+ bool exist; /* Does region exists in current memory region? */
+ u32 start; /* Start wrt 0 */
+ u32 end; /* End wrt 0 */
+};
+
+struct struct_port_usage {
+ u32 id;
+ u32 used;
+ u32 alloc;
+};
+
+struct struct_lpbk_usage {
+ u32 id;
+ u32 used;
+ u32 alloc;
+};
+
+struct struct_mem_desc {
+ u32 base;
+ u32 limit;
+ u32 idx;
+};
+
+enum string_size_units {
+ STRING_UNITS_10, /* use powers of 10^3 (standard SI) */
+ STRING_UNITS_2, /* use binary powers of 2^10 */
+};
+
+struct struct_meminfo {
+ struct struct_mem_desc avail[4];
+ struct struct_mem_desc mem[ARRAY_SIZE(region) + 3];
+ u32 avail_c;
+ u32 mem_c;
+ u32 up_ram_lo;
+ u32 up_ram_hi;
+ u32 up_extmem2_lo;
+ u32 up_extmem2_hi;
+ u32 rx_pages_data[3];
+ u32 tx_pages_data[4];
+ u32 p_structs;
+ struct struct_port_usage port_data[4];
+ u32 port_used[4];
+ u32 port_alloc[4];
+ u32 loopback_used[NCHAN];
+ u32 loopback_alloc[NCHAN];
+ u32 pstructs_free_cnt;
+ u32 free_rx_cnt;
+ u32 free_tx_cnt;
+};
+
+#ifndef __GNUC__
+#pragma warning(disable : 4200)
+#endif
+
+struct struct_lb_stats {
+ int nchan;
+ struct lb_port_stats s[0];
+};
+
+struct struct_clk_info {
+ u64 retransmit_min;
+ u64 retransmit_max;
+ u64 persist_timer_min;
+ u64 persist_timer_max;
+ u64 keepalive_idle_timer;
+ u64 keepalive_interval;
+ u64 initial_srtt;
+ u64 finwait2_timer;
+ u32 dack_timer;
+ u32 res;
+ u32 cclk_ps;
+ u32 tre;
+ u32 dack_re;
+ char core_clk_period[32];
+ char tp_timer_tick[32];
+ char tcp_tstamp_tick[32];
+ char dack_tick[32];
+};
+
+struct cim_pif_la {
+ int size;
+ u8 data[0];
+};
+
+struct struct_tp_la {
+ u32 size;
+ u32 mode;
+ u8 data[0];
+};
+
+struct field_desc {
+ const char *name;
+ u32 start;
+ u32 width;
+};
+
+struct tp_mib_type {
+ char *key;
+ u32 addr;
+ u32 value;
+};
+
+struct wtp_type_0 {
+ u32 sop;
+ u32 eop;
+};
+
+struct wtp_type_1 {
+ u32 sop[2];
+ u32 eop[2];
+};
+
+struct wtp_type_2 {
+ u32 sop[4];
+ u32 eop[4];
+};
+
+struct wtp_type_3 {
+ u32 sop[4];
+ u32 eop[4];
+ u32 drops;
+};
+
+struct wtp_data {
+ /*TX path, Request Work request sub-path:*/
+
+ struct wtp_type_1 sge_pcie_cmd_req; /*SGE_DEBUG PC_Req_xOPn*/
+ struct wtp_type_1 pcie_core_cmd_req; /*PCIE_CMDR_REQ_CNT*/
+
+
+ /*TX path, Work request to uP sub-path*/
+ struct wtp_type_1 core_pcie_cmd_rsp; /*PCIE_CMDR_RSP_CNT*/
+ struct wtp_type_1 pcie_sge_cmd_rsp; /*SGE_DEBUG PC_Rsp_xOPn*/
+ struct wtp_type_1 sge_cim; /*SGE_DEBUG CIM_xOPn*/
+
+ /*TX path, Data request path from ULP_TX to core*/
+ struct wtp_type_2 utx_sge_dma_req; /*SGE UD_Rx_xOPn*/
+ struct wtp_type_2 sge_pcie_dma_req; /*SGE PD_Req_Rdn (no eops)*/
+ struct wtp_type_2 pcie_core_dma_req; /*PCIE_DMAR_REQ_CNT (no eops)*/
+
+ /*Main TX path, from core to wire*/
+ struct wtp_type_2 core_pcie_dma_rsp; /*PCIE_DMAR_RSP_SOP_CNT/
+ PCIE_DMAR_EOP_CNT*/
+ struct wtp_type_2 pcie_sge_dma_rsp; /*SGE_DEBUG PD_Rsp_xOPn*/
+ struct wtp_type_2 sge_utx; /*SGE_DEBUG U_Tx_xOPn*/
+ struct wtp_type_2 utx_tp; /*ULP_TX_SE_CNT_CHn[xOP_CNT_ULP2TP]*/
+ struct wtp_type_2 utx_tpcside; /*TP_DBG_CSIDE_RXn[RxXoPCnt]*/
+
+ struct wtp_type_2 tpcside_rxpld;
+ struct wtp_type_2 tpcside_rxarb; /*TP_DBG_CSIDE_RXn[RxArbXopCnt]*/
+ struct wtp_type_2 tpcside_rxcpl;
+
+ struct wtp_type_2 tpeside_mps; /*TP_DBG_ESDIE_PKT0[TxXoPCnt]*/
+ struct wtp_type_2 tpeside_pm;
+ struct wtp_type_2 tpeside_pld;
+
+ /*Tx path, PCIE t5 DMA stat*/
+ struct wtp_type_2 pcie_t5_dma_stat3;
+
+ /*Tx path, SGE debug data high index 6*/
+ struct wtp_type_2 sge_debug_data_high_index_6;
+
+ /*Tx path, SGE debug data high index 3*/
+ struct wtp_type_2 sge_debug_data_high_index_3;
+
+ /*Tx path, ULP SE CNT CHx*/
+ struct wtp_type_2 ulp_se_cnt_chx;
+
+ /*pcie cmd stat 2*/
+ struct wtp_type_2 pcie_cmd_stat2;
+
+ /*pcie cmd stat 3*/
+ struct wtp_type_2 pcie_cmd_stat3;
+
+ struct wtp_type_2 pcie_dma1_stat2_core;
+
+ struct wtp_type_1 sge_work_req_pkt;
+
+ struct wtp_type_2 sge_debug_data_high_indx5;
+
+ /*Tx path, mac portx pkt count*/
+ struct wtp_type_2 mac_portx_pkt_count;
+
+ /*Rx path, mac porrx pkt count*/
+ struct wtp_type_2 mac_porrx_pkt_count;
+
+ /*Rx path, PCIE T5 dma1 stat 2*/
+ struct wtp_type_2 pcie_dma1_stat2;
+
+ /*Rx path, sge debug data high index 7*/
+ struct wtp_type_2 sge_debug_data_high_indx7;
+
+ /*Rx path, sge debug data high index 1*/
+ struct wtp_type_1 sge_debug_data_high_indx1;
+
+ /*Rx path, TP debug CSIDE Tx register*/
+ struct wtp_type_1 utx_tpcside_tx;
+
+ /*Rx path, LE DB response count*/
+ struct wtp_type_0 le_db_rsp_cnt;
+
+ /*Rx path, TP debug Eside PKTx*/
+ struct wtp_type_2 tp_dbg_eside_pktx;
+
+ /*Rx path, sge debug data high index 9*/
+ struct wtp_type_1 sge_debug_data_high_indx9;
+
+ /*Tx path, mac portx aFramesTransmittesok*/
+ struct wtp_type_2 mac_portx_aframestra_ok;
+
+ /*Rx path, mac portx aFramesTransmittesok*/
+ struct wtp_type_2 mac_porrx_aframestra_ok;
+
+ /*Tx path, MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/
+ struct wtp_type_1 mac_portx_etherstatspkts;
+
+ /*Rx path, MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/
+ struct wtp_type_1 mac_porrx_etherstatspkts;
+
+ struct wtp_type_3 tp_mps; /*MPS_TX_SE_CNT_TP01 and
+ MPS_TX_SE_CNT_TP34*/
+ struct wtp_type_3 mps_xgm; /*MPS_TX_SE_CNT_MAC01 and
+ MPS_TX_SE_CNT_MAC34*/
+ struct wtp_type_2 tx_xgm_xgm; /*XGMAC_PORT_PKT_CNT_PORT_n*/
+ struct wtp_type_2 xgm_wire; /*XGMAC_PORT_XGM_STAT_TX_FRAME_LOW_PORT_N
+ (clear on read)*/
+
+ /*RX path, from wire to core.*/
+ struct wtp_type_2 wire_xgm; /*XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW_PORT_N
+ (clear on read)*/
+ struct wtp_type_2 rx_xgm_xgm; /*XGMAC_PORT_PKT_CNT_PORT_n*/
+ struct _xgm_mps { /*MPS_RX_SE_CNT_INn*/
+ u32 sop[8]; /* => undef,*/
+ u32 eop[8]; /* => undef,*/
+ u32 drop; /* => undef,*/
+ u32 cls_drop; /* => undef,*/
+ u32 err; /* => undef,*/
+ u32 bp; /* => undef,*/
+ } xgm_mps;
+
+ struct wtp_type_3 mps_tp; /*MPS_RX_SE_CNT_OUT01 and
+ MPS_RX_SE_CNT_OUT23*/
+ struct wtp_type_2 mps_tpeside; /*TP_DBG_ESIDE_PKTn*/
+ struct wtp_type_1 tpeside_pmrx; /*???*/
+ struct wtp_type_2 pmrx_ulprx; /*ULP_RX_SE_CNT_CHn[xOP_CNT_INn]*/
+ struct wtp_type_2 ulprx_tpcside; /*ULP_RX_SE_CNT_CHn[xOP_CNT_OUTn]*/
+ struct wtp_type_2 tpcside_csw; /*TP_DBG_CSIDE_TXn[TxSopCnt]*/
+ struct wtp_type_2 tpcside_pm;
+ struct wtp_type_2 tpcside_uturn;
+ struct wtp_type_2 tpcside_txcpl;
+ struct wtp_type_1 tp_csw; /*SGE_DEBUG CPLSW_TP_Rx_xOPn*/
+ struct wtp_type_1 csw_sge; /*SGE_DEBUG T_Rx_xOPn*/
+ struct wtp_type_2 sge_pcie; /*SGE_DEBUG PD_Req_SopN -
+ PD_Req_RdN - PD_ReqIntN*/
+ struct wtp_type_2 sge_pcie_ints; /*SGE_DEBUG PD_Req_IntN*/
+ struct wtp_type_2 pcie_core_dmaw; /*PCIE_DMAW_SOP_CNT and
+ PCIE_DMAW_EOP_CNT*/
+ struct wtp_type_2 pcie_core_dmai; /*PCIE_DMAI_CNT*/
+
+};
+
+struct tp_mib_data {
+ struct tp_mib_type TP_MIB_MAC_IN_ERR_0;
+ struct tp_mib_type TP_MIB_MAC_IN_ERR_1;
+ struct tp_mib_type TP_MIB_MAC_IN_ERR_2;
+ struct tp_mib_type TP_MIB_MAC_IN_ERR_3;
+ struct tp_mib_type TP_MIB_HDR_IN_ERR_0;
+ struct tp_mib_type TP_MIB_HDR_IN_ERR_1;
+ struct tp_mib_type TP_MIB_HDR_IN_ERR_2;
+ struct tp_mib_type TP_MIB_HDR_IN_ERR_3;
+ struct tp_mib_type TP_MIB_TCP_IN_ERR_0;
+ struct tp_mib_type TP_MIB_TCP_IN_ERR_1;
+ struct tp_mib_type TP_MIB_TCP_IN_ERR_2;
+ struct tp_mib_type TP_MIB_TCP_IN_ERR_3;
+ struct tp_mib_type TP_MIB_TCP_OUT_RST;
+ struct tp_mib_type TP_MIB_TCP_IN_SEG_HI;
+ struct tp_mib_type TP_MIB_TCP_IN_SEG_LO;
+ struct tp_mib_type TP_MIB_TCP_OUT_SEG_HI;
+ struct tp_mib_type TP_MIB_TCP_OUT_SEG_LO;
+ struct tp_mib_type TP_MIB_TCP_RXT_SEG_HI;
+ struct tp_mib_type TP_MIB_TCP_RXT_SEG_LO;
+ struct tp_mib_type TP_MIB_TNL_CNG_DROP_0;
+ struct tp_mib_type TP_MIB_TNL_CNG_DROP_1;
+ struct tp_mib_type TP_MIB_TNL_CNG_DROP_2;
+ struct tp_mib_type TP_MIB_TNL_CNG_DROP_3;
+ struct tp_mib_type TP_MIB_OFD_CHN_DROP_0;
+ struct tp_mib_type TP_MIB_OFD_CHN_DROP_1;
+ struct tp_mib_type TP_MIB_OFD_CHN_DROP_2;
+ struct tp_mib_type TP_MIB_OFD_CHN_DROP_3;
+ struct tp_mib_type TP_MIB_TNL_OUT_PKT_0;
+ struct tp_mib_type TP_MIB_TNL_OUT_PKT_1;
+ struct tp_mib_type TP_MIB_TNL_OUT_PKT_2;
+ struct tp_mib_type TP_MIB_TNL_OUT_PKT_3;
+ struct tp_mib_type TP_MIB_TNL_IN_PKT_0;
+ struct tp_mib_type TP_MIB_TNL_IN_PKT_1;
+ struct tp_mib_type TP_MIB_TNL_IN_PKT_2;
+ struct tp_mib_type TP_MIB_TNL_IN_PKT_3;
+ struct tp_mib_type TP_MIB_TCP_V6IN_ERR_0;
+ struct tp_mib_type TP_MIB_TCP_V6IN_ERR_1;
+ struct tp_mib_type TP_MIB_TCP_V6IN_ERR_2;
+ struct tp_mib_type TP_MIB_TCP_V6IN_ERR_3;
+ struct tp_mib_type TP_MIB_TCP_V6OUT_RST;
+ struct tp_mib_type TP_MIB_TCP_V6IN_SEG_HI;
+ struct tp_mib_type TP_MIB_TCP_V6IN_SEG_LO;
+ struct tp_mib_type TP_MIB_TCP_V6OUT_SEG_HI;
+ struct tp_mib_type TP_MIB_TCP_V6OUT_SEG_LO;
+ struct tp_mib_type TP_MIB_TCP_V6RXT_SEG_HI;
+ struct tp_mib_type TP_MIB_TCP_V6RXT_SEG_LO;
+ struct tp_mib_type TP_MIB_OFD_ARP_DROP;
+ struct tp_mib_type TP_MIB_OFD_DFR_DROP;
+ struct tp_mib_type TP_MIB_CPL_IN_REQ_0;
+ struct tp_mib_type TP_MIB_CPL_IN_REQ_1;
+ struct tp_mib_type TP_MIB_CPL_IN_REQ_2;
+ struct tp_mib_type TP_MIB_CPL_IN_REQ_3;
+ struct tp_mib_type TP_MIB_CPL_OUT_RSP_0;
+ struct tp_mib_type TP_MIB_CPL_OUT_RSP_1;
+ struct tp_mib_type TP_MIB_CPL_OUT_RSP_2;
+ struct tp_mib_type TP_MIB_CPL_OUT_RSP_3;
+ struct tp_mib_type TP_MIB_TNL_LPBK_0;
+ struct tp_mib_type TP_MIB_TNL_LPBK_1;
+ struct tp_mib_type TP_MIB_TNL_LPBK_2;
+ struct tp_mib_type TP_MIB_TNL_LPBK_3;
+ struct tp_mib_type TP_MIB_TNL_DROP_0;
+ struct tp_mib_type TP_MIB_TNL_DROP_1;
+ struct tp_mib_type TP_MIB_TNL_DROP_2;
+ struct tp_mib_type TP_MIB_TNL_DROP_3;
+ struct tp_mib_type TP_MIB_FCOE_DDP_0;
+ struct tp_mib_type TP_MIB_FCOE_DDP_1;
+ struct tp_mib_type TP_MIB_FCOE_DDP_2;
+ struct tp_mib_type TP_MIB_FCOE_DDP_3;
+ struct tp_mib_type TP_MIB_FCOE_DROP_0;
+ struct tp_mib_type TP_MIB_FCOE_DROP_1;
+ struct tp_mib_type TP_MIB_FCOE_DROP_2;
+ struct tp_mib_type TP_MIB_FCOE_DROP_3;
+ struct tp_mib_type TP_MIB_FCOE_BYTE_0_HI;
+ struct tp_mib_type TP_MIB_FCOE_BYTE_0_LO;
+ struct tp_mib_type TP_MIB_FCOE_BYTE_1_HI;
+ struct tp_mib_type TP_MIB_FCOE_BYTE_1_LO;
+ struct tp_mib_type TP_MIB_FCOE_BYTE_2_HI;
+ struct tp_mib_type TP_MIB_FCOE_BYTE_2_LO;
+ struct tp_mib_type TP_MIB_FCOE_BYTE_3_HI;
+ struct tp_mib_type TP_MIB_FCOE_BYTE_3_LO;
+ struct tp_mib_type TP_MIB_OFD_VLN_DROP_0;
+ struct tp_mib_type TP_MIB_OFD_VLN_DROP_1;
+ struct tp_mib_type TP_MIB_OFD_VLN_DROP_2;
+ struct tp_mib_type TP_MIB_OFD_VLN_DROP_3;
+ struct tp_mib_type TP_MIB_USM_PKTS;
+ struct tp_mib_type TP_MIB_USM_DROP;
+ struct tp_mib_type TP_MIB_USM_BYTES_HI;
+ struct tp_mib_type TP_MIB_USM_BYTES_LO;
+ struct tp_mib_type TP_MIB_TID_DEL;
+ struct tp_mib_type TP_MIB_TID_INV;
+ struct tp_mib_type TP_MIB_TID_ACT;
+ struct tp_mib_type TP_MIB_TID_PAS;
+ struct tp_mib_type TP_MIB_RQE_DFR_MOD;
+ struct tp_mib_type TP_MIB_RQE_DFR_PKT;
+};
+
+struct cudbg_reg_info {
+ const char *name;
+ unsigned int addr;
+ unsigned int len;
+};
+
+struct tp1_reg_info {
+ char addr[10];
+ char name[40];
+};
+
+struct ireg_field {
+ u32 ireg_addr;
+ u32 ireg_data;
+ u32 ireg_local_offset;
+ u32 ireg_offset_range;
+};
+
+struct ireg_buf {
+ struct ireg_field tp_pio;
+ u32 outbuf[32];
+};
+
+struct tx_rate {
+ u64 nrate[NCHAN];
+ u64 orate[NCHAN];
+ u32 nchan;
+};
+
+struct tid_info_region {
+ u32 ntids;
+ u32 nstids;
+ u32 stid_base;
+ u32 hash_base;
+
+ u32 natids;
+ u32 nftids;
+ u32 ftid_base;
+ u32 aftid_base;
+ u32 aftid_end;
+
+ /* Server filter region */
+ u32 sftid_base;
+ u32 nsftids;
+
+ /* UO context range */
+ u32 uotid_base;
+ u32 nuotids;
+
+ u32 sb;
+ u32 flags;
+ u32 le_db_conf;
+ u32 IP_users;
+ u32 IPv6_users;
+
+ u32 hpftid_base;
+ u32 nhpftids;
+};
+
+struct tid_info_region_rev1 {
+ struct cudbg_ver_hdr ver_hdr;
+ struct tid_info_region tid;
+ u32 tid_start;
+ u32 reserved[16];
+};
+
+struct struct_vpd_data {
+ u8 sn[SN_MAX_LEN + 1];
+ u8 bn[BN_MAX_LEN + 1];
+ u8 na[NA_MAX_LEN + 1];
+ u8 mn[MN_MAX_LEN + 1];
+ u16 fw_major;
+ u16 fw_minor;
+ u16 fw_micro;
+ u16 fw_build;
+ u32 scfg_vers;
+ u32 vpd_vers;
+};
+
+struct sw_state {
+ u32 fw_state;
+ u8 caller_string[100];
+ u8 os_type;
+ u8 reserved[3];
+ u32 reserved1[16];
+};
+
+struct sge_qbase_reg_field {
+ u32 reg_addr;
+ u32 reg_data[4];
+ u32 pf_data_value[8][4]; /* [max pf][4 data reg SGE_QBASE_MAP[0-3] */
+ u32 vf_data_value[256][4]; /* [max vf][4 data reg SGE_QBASE_MAP[0-3] */
+ u32 vfcount;
+};
+
+struct cudbg_qdesc_entry {
+ u32 data_size;
+ u32 qtype;
+ u32 qid;
+ u32 desc_size;
+ u32 num_desc;
+ u8 data[0]; /* Must be last */
+};
+
+static u32 ATTRIBUTE_UNUSED t6_tp_pio_array[][4] = {
+ {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
+ {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
+ {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
+ {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
+ {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
+ {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
+ {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
+ {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
+ {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
+ {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
+ {0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
+ {0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
+};
+
+static u32 ATTRIBUTE_UNUSED t5_tp_pio_array[][4] = {
+ {0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
+ {0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
+ {0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
+ {0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
+ {0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
+ {0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
+ {0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
+ {0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
+ {0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
+ {0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
+ {0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
+};
+
+static u32 ATTRIBUTE_UNUSED t6_ma_ireg_array[][4] = {
+ {0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
+ {0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
+ {0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
+};
+
+static u32 ATTRIBUTE_UNUSED t6_ma_ireg_array2[][4] = {
+ {0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
+ {0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
+};
+
+static u32 ATTRIBUTE_UNUSED t6_hma_ireg_array[][4] = {
+ {0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
+};
+static u32 ATTRIBUTE_UNUSED t5_pcie_pdbg_array[][4] = {
+ {0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
+ {0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
+ {0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
+};
+
+static u32 ATTRIBUTE_UNUSED t5_pcie_config_array[][2] = {
+ {0x0, 0x34},
+ {0x3c, 0x40},
+ {0x50, 0x64},
+ {0x70, 0x80},
+ {0x94, 0xa0},
+ {0xb0, 0xb8},
+ {0xd0, 0xd4},
+ {0x100, 0x128},
+ {0x140, 0x148},
+ {0x150, 0x164},
+ {0x170, 0x178},
+ {0x180, 0x194},
+ {0x1a0, 0x1b8},
+ {0x1c0, 0x208},
+};
+
+static u32 ATTRIBUTE_UNUSED t5_pcie_cdbg_array[][4] = {
+ {0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
+ {0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
+};
+
+static u32 ATTRIBUTE_UNUSED t6_tp_tm_pio_array[1][4] = {
+ {0x7e18, 0x7e1c, 0x0, 12}
+};
+
+static u32 ATTRIBUTE_UNUSED t5_tp_tm_pio_array[1][4] = {
+ {0x7e18, 0x7e1c, 0x0, 12}
+};
+
+static u32 ATTRIBUTE_UNUSED t5_pm_rx_array[][4] = {
+ {0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
+ {0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
+};
+
+static u32 ATTRIBUTE_UNUSED t5_pm_tx_array[][4] = {
+ {0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
+ {0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
+};
+
+static u32 ATTRIBUTE_UNUSED t6_tp_mib_index_array[6][4] = {
+ {0x7e50, 0x7e54, 0x0, 13},
+ {0x7e50, 0x7e54, 0x10, 6},
+ {0x7e50, 0x7e54, 0x18, 21},
+ {0x7e50, 0x7e54, 0x30, 32},
+ {0x7e50, 0x7e54, 0x50, 22},
+ {0x7e50, 0x7e54, 0x68, 12}
+};
+
+static u32 ATTRIBUTE_UNUSED t5_tp_mib_index_array[9][4] = {
+ {0x7e50, 0x7e54, 0x0, 13},
+ {0x7e50, 0x7e54, 0x10, 6},
+ {0x7e50, 0x7e54, 0x18, 8},
+ {0x7e50, 0x7e54, 0x20, 13},
+ {0x7e50, 0x7e54, 0x30, 16},
+ {0x7e50, 0x7e54, 0x40, 16},
+ {0x7e50, 0x7e54, 0x50, 16},
+ {0x7e50, 0x7e54, 0x60, 6},
+ {0x7e50, 0x7e54, 0x68, 4}
+};
+
+static u32 ATTRIBUTE_UNUSED t5_sge_dbg_index_array[9][4] = {
+ {0x10cc, 0x10d0, 0x0, 16},
+ {0x10cc, 0x10d4, 0x0, 16},
+};
+
+static u32 ATTRIBUTE_UNUSED t6_up_cim_reg_array[][4] = {
+ {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
+ {0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */
+ {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
+ {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
+ {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
+ {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
+ {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
+ {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
+ {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
+ {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
+ {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
+ {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
+ {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
+
+};
+
+static u32 ATTRIBUTE_UNUSED t5_up_cim_reg_array[][4] = {
+ {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
+ {0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */
+ {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
+ {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
+ {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
+ {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
+ {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
+ {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
+ {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
+ {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
+ {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
+ {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
+ {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
+};
+
+#endif
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/cudbg_flash_utils.c b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_flash_utils.c
new file mode 100644
index 0000000000..eb78e1d77f
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_flash_utils.c
@@ -0,0 +1,509 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*-
+ * Copyright (c) 2017 Chelsio Communications, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+
+#include "common/common.h"
+#include "common/t4_regs.h"
+#include "cudbg.h"
+#include "cudbg_lib_common.h"
+
+enum {
+ SF_ATTEMPTS = 10, /* max retries for SF operations */
+
+ /* flash command opcodes */
+ SF_PROG_PAGE = 2, /* program page */
+ SF_WR_DISABLE = 4, /* disable writes */
+ SF_RD_STATUS = 5, /* read status register */
+ SF_WR_ENABLE = 6, /* enable writes */
+ SF_RD_DATA_FAST = 0xb, /* read flash */
+ SF_RD_ID = 0x9f, /* read ID */
+ SF_ERASE_SECTOR = 0xd8, /* erase sector */
+};
+
+int write_flash(struct adapter *adap, u32 start_sec, void *data, u32 size);
+int read_flash(struct adapter *adap, u32 start_sec , void *data, u32 size,
+ u32 start_address);
+
+void
+update_skip_size(struct cudbg_flash_sec_info *sec_info, u32 size)
+{
+ sec_info->skip_size += size;
+}
+
+static
+void set_sector_availability(struct cudbg_flash_sec_info *sec_info,
+ int sector_nu, int avail)
+{
+ sector_nu -= CUDBG_START_SEC;
+ if (avail)
+ set_dbg_bitmap(sec_info->sec_bitmap, sector_nu);
+ else
+ reset_dbg_bitmap(sec_info->sec_bitmap, sector_nu);
+}
+
+/* This function will return empty sector available for filling */
+static int
+find_empty_sec(struct cudbg_flash_sec_info *sec_info)
+{
+ int i, index, bit;
+
+ for (i = CUDBG_START_SEC; i < CUDBG_SF_MAX_SECTOR; i++) {
+ index = (i - CUDBG_START_SEC) / 8;
+ bit = (i - CUDBG_START_SEC) % 8;
+ if (!(sec_info->sec_bitmap[index] & (1 << bit)))
+ return i;
+ }
+
+ return CUDBG_STATUS_FLASH_FULL;
+}
+
+/* This function will get header initially. If header is already there
+ * then it will update that header */
+static void
+update_headers(void *handle, struct cudbg_buffer *dbg_buff,
+ u64 timestamp, u32 cur_entity_hdr_offset,
+ u32 start_offset, u32 ext_size)
+{
+ struct cudbg_private *priv = handle;
+ struct cudbg_flash_sec_info *sec_info = &priv->sec_info;
+ void *sec_hdr;
+ struct cudbg_hdr *cudbg_hdr;
+ struct cudbg_flash_hdr *flash_hdr;
+ struct cudbg_entity_hdr *entity_hdr;
+ u32 hdr_offset;
+ u32 data_hdr_size;
+ u32 total_hdr_size;
+ u32 sec_hdr_start_addr;
+
+ data_hdr_size = CUDBG_MAX_ENTITY * sizeof(struct cudbg_entity_hdr) +
+ sizeof(struct cudbg_hdr);
+ total_hdr_size = data_hdr_size + sizeof(struct cudbg_flash_hdr);
+ sec_hdr_start_addr = CUDBG_SF_SECTOR_SIZE - total_hdr_size;
+ sec_hdr = sec_info->sec_data + sec_hdr_start_addr;
+
+ flash_hdr = (struct cudbg_flash_hdr *)(sec_hdr);
+ cudbg_hdr = (struct cudbg_hdr *)dbg_buff->data;
+
+ /* initially initialize flash hdr and copy all data headers and
+ * in next calling (else part) copy only current entity header
+ */
+ if ((start_offset - sec_info->skip_size) == data_hdr_size) {
+ flash_hdr->signature = CUDBG_FL_SIGNATURE;
+ flash_hdr->major_ver = CUDBG_FL_MAJOR_VERSION;
+ flash_hdr->minor_ver = CUDBG_FL_MINOR_VERSION;
+ flash_hdr->build_ver = CUDBG_FL_BUILD_VERSION;
+ flash_hdr->hdr_len = sizeof(struct cudbg_flash_hdr);
+ hdr_offset = sizeof(struct cudbg_flash_hdr);
+
+ memcpy((void *)((char *)sec_hdr + hdr_offset),
+ (void *)((char *)dbg_buff->data), data_hdr_size);
+ } else
+ memcpy((void *)((char *)sec_hdr +
+ sizeof(struct cudbg_flash_hdr) +
+ cur_entity_hdr_offset),
+ (void *)((char *)dbg_buff->data +
+ cur_entity_hdr_offset),
+ sizeof(struct cudbg_entity_hdr));
+
+ hdr_offset = data_hdr_size + sizeof(struct cudbg_flash_hdr);
+ flash_hdr->data_len = cudbg_hdr->data_len - sec_info->skip_size;
+ flash_hdr->timestamp = timestamp;
+
+ entity_hdr = (struct cudbg_entity_hdr *)((char *)sec_hdr +
+ sizeof(struct cudbg_flash_hdr) +
+ cur_entity_hdr_offset);
+ /* big entity like mc need to be skipped */
+ entity_hdr->start_offset -= sec_info->skip_size;
+
+ cudbg_hdr = (struct cudbg_hdr *)((char *)sec_hdr +
+ sizeof(struct cudbg_flash_hdr));
+ cudbg_hdr->data_len = flash_hdr->data_len;
+ flash_hdr->data_len += ext_size;
+}
+
+/* Write CUDBG data into serial flash */
+int
+cudbg_write_flash(void *handle, u64 timestamp, void *data,
+ u32 start_offset, u32 cur_entity_hdr_offset,
+ u32 cur_entity_size,
+ u32 ext_size)
+{
+ struct cudbg_private *priv = handle;
+ struct cudbg_init *cudbg_init = &priv->dbg_init;
+ struct cudbg_flash_sec_info *sec_info = &priv->sec_info;
+ struct adapter *adap = cudbg_init->adap;
+ struct cudbg_flash_hdr *flash_hdr = NULL;
+ struct cudbg_buffer *dbg_buff = (struct cudbg_buffer *)data;
+ u32 data_hdr_size;
+ u32 total_hdr_size;
+ u32 tmp_size;
+ u32 sec_data_offset;
+ u32 sec_hdr_start_addr;
+ u32 sec_data_size;
+ u32 space_left;
+ int rc = 0;
+ int sec;
+
+ data_hdr_size = CUDBG_MAX_ENTITY * sizeof(struct cudbg_entity_hdr) +
+ sizeof(struct cudbg_hdr);
+ total_hdr_size = data_hdr_size + sizeof(struct cudbg_flash_hdr);
+ sec_hdr_start_addr = CUDBG_SF_SECTOR_SIZE - total_hdr_size;
+ sec_data_size = sec_hdr_start_addr;
+
+ cudbg_init->print(adap->dip, CE_NOTE, "\tWriting %u bytes to flash\n", cur_entity_size);
+
+ /* this function will get header if sec_info->sec_data does not
+ * have any header and
+ * will update the header if it has header
+ */
+ update_headers(handle, dbg_buff, timestamp,
+ cur_entity_hdr_offset,
+ start_offset, ext_size);
+
+ if (ext_size) {
+ cur_entity_size += sizeof(struct cudbg_entity_hdr);
+ start_offset = dbg_buff->offset - cur_entity_size;
+ }
+
+ flash_hdr = (struct cudbg_flash_hdr *)(sec_info->sec_data +
+ sec_hdr_start_addr);
+
+ if (flash_hdr->data_len > CUDBG_FLASH_SIZE) {
+ rc = CUDBG_STATUS_FLASH_FULL;
+ goto out;
+ }
+
+ space_left = CUDBG_FLASH_SIZE - flash_hdr->data_len;
+
+ if (cur_entity_size > space_left) {
+ rc = CUDBG_STATUS_FLASH_FULL;
+ goto out;
+ }
+
+ while (cur_entity_size > 0) {
+ sec = find_empty_sec(sec_info);
+ if (sec_info->par_sec) {
+ sec_data_offset = sec_info->par_sec_offset;
+ set_sector_availability(sec_info, sec_info->par_sec, 0);
+ sec_info->par_sec = 0;
+ sec_info->par_sec_offset = 0;
+
+ } else {
+ sec_info->cur_seq_no++;
+ flash_hdr->sec_seq_no = sec_info->cur_seq_no;
+ sec_data_offset = 0;
+ }
+
+ if (cur_entity_size + sec_data_offset > sec_data_size) {
+ tmp_size = sec_data_size - sec_data_offset;
+ } else {
+ tmp_size = cur_entity_size;
+ sec_info->par_sec = sec;
+ sec_info->par_sec_offset = cur_entity_size +
+ sec_data_offset;
+ }
+
+ memcpy((void *)((char *)sec_info->sec_data + sec_data_offset),
+ (void *)((char *)dbg_buff->data + start_offset),
+ tmp_size);
+
+ rc = write_flash(adap, sec, sec_info->sec_data,
+ CUDBG_SF_SECTOR_SIZE);
+ if (rc)
+ goto out;
+
+ cur_entity_size -= tmp_size;
+ set_sector_availability(sec_info, sec, 1);
+ start_offset += tmp_size;
+ }
+out:
+ return rc;
+}
+
+int
+write_flash(struct adapter *adap, u32 start_sec, void *data, u32 size)
+{
+ unsigned int addr;
+ unsigned int i, n;
+ unsigned int sf_sec_size;
+ int rc = 0;
+
+ u8 *ptr = (u8 *)data;
+
+ sf_sec_size = adap->params.sf_size/adap->params.sf_nsec;
+
+ addr = start_sec * CUDBG_SF_SECTOR_SIZE;
+ i = DIV_ROUND_UP(size,/* # of sectors spanned */
+ sf_sec_size);
+
+ rc = t4_flash_erase_sectors(adap, start_sec,
+ start_sec + i - 1);
+ /*
+ * If size == 0 then we're simply erasing the FLASH sectors associated
+ * with the on-adapter OptionROM Configuration File.
+ */
+
+ if (rc || size == 0)
+ goto out;
+
+ /* this will write to the flash up to SF_PAGE_SIZE at a time */
+ for (i = 0; i < size; i += SF_PAGE_SIZE) {
+ if ((size - i) < SF_PAGE_SIZE)
+ n = size - i;
+ else
+ n = SF_PAGE_SIZE;
+ rc = t4_write_flash(adap, addr, n, ptr, 0);
+ if (rc)
+ goto out;
+
+ addr += n;
+ ptr += n;
+ }
+
+ return 0;
+out:
+ return rc;
+}
+
+int
+cudbg_read_flash_details(void *handle, struct cudbg_flash_hdr *data)
+{
+ int rc;
+ rc = cudbg_read_flash(handle, (void *)data,
+ sizeof(struct cudbg_flash_hdr), 0);
+
+ return rc;
+}
+
+int
+cudbg_read_flash_data(void *handle, void *buf, u32 buf_size)
+{
+ int rc;
+ u32 total_hdr_size, data_header_size;
+ void *payload = NULL;
+ u32 payload_size = 0;
+
+ data_header_size = CUDBG_MAX_ENTITY * sizeof(struct cudbg_entity_hdr) +
+ sizeof(struct cudbg_hdr);
+ total_hdr_size = data_header_size + sizeof(struct cudbg_flash_hdr);
+
+ /* Copy flash header to buffer */
+ rc = cudbg_read_flash(handle, buf, total_hdr_size, 0);
+ if (rc != 0)
+ goto out;
+ payload = (char *)buf + total_hdr_size;
+ payload_size = buf_size - total_hdr_size;
+
+ /* Reading flash data to buf */
+ rc = cudbg_read_flash(handle, payload, payload_size, 1);
+ if (rc != 0)
+ goto out;
+
+out:
+ return rc;
+}
+
+int
+cudbg_read_flash(void *handle, void *data, u32 size, int data_flag)
+{
+ struct cudbg_private *priv = handle;
+ struct cudbg_init *cudbg_init = &priv->dbg_init;
+ struct cudbg_flash_sec_info *sec_info = &priv->sec_info;
+ struct adapter *adap = cudbg_init->adap;
+ struct cudbg_flash_hdr flash_hdr;
+ u32 total_hdr_size;
+ u32 data_hdr_size;
+ u32 sec_hdr_start_addr;
+ u32 tmp_size;
+ u32 data_offset = 0;
+ u32 i, j;
+ int rc;
+
+ rc = t4_get_flash_params(adap);
+ if (rc) {
+ cudbg_init->print(adap->dip, CE_NOTE,"\nGet flash params failed."
+ "Try Again...readflash\n\n");
+ return rc;
+ }
+
+ data_hdr_size = CUDBG_MAX_ENTITY * sizeof(struct cudbg_entity_hdr) +
+ sizeof(struct cudbg_hdr);
+ total_hdr_size = data_hdr_size + sizeof(struct cudbg_flash_hdr);
+ sec_hdr_start_addr = CUDBG_SF_SECTOR_SIZE - total_hdr_size;
+
+ if (!data_flag) {
+ /* fill header */
+ if (!sec_info->max_timestamp) {
+ /* finding max time stamp because it may
+ * have older filled sector also
+ */
+ memset(&flash_hdr, 0, sizeof(struct cudbg_flash_hdr));
+ rc = read_flash(adap, CUDBG_START_SEC, &flash_hdr,
+ sizeof(struct cudbg_flash_hdr),
+ sec_hdr_start_addr);
+
+ if (flash_hdr.signature == CUDBG_FL_SIGNATURE) {
+ sec_info->max_timestamp = flash_hdr.timestamp;
+ } else {
+ rc = read_flash(adap, CUDBG_START_SEC + 1,
+ &flash_hdr,
+ sizeof(struct cudbg_flash_hdr),
+ sec_hdr_start_addr);
+
+ if (flash_hdr.signature == CUDBG_FL_SIGNATURE)
+ sec_info->max_timestamp =
+ flash_hdr.timestamp;
+ else {
+ cudbg_init->print(adap->dip, CE_NOTE,
+ "\n\tNo cudbg dump "\
+ "found in flash\n\n");
+ return CUDBG_STATUS_NO_SIGNATURE;
+ }
+
+ }
+
+ /* finding max sequence number because max sequenced
+ * sector has updated header
+ */
+ for (i = CUDBG_START_SEC; i <
+ CUDBG_SF_MAX_SECTOR; i++) {
+ memset(&flash_hdr, 0,
+ sizeof(struct cudbg_flash_hdr));
+ rc = read_flash(adap, i, &flash_hdr,
+ sizeof(struct cudbg_flash_hdr),
+ sec_hdr_start_addr);
+
+ if (flash_hdr.signature == CUDBG_FL_SIGNATURE &&
+ sec_info->max_timestamp ==
+ flash_hdr.timestamp &&
+ sec_info->max_seq_no <=
+ flash_hdr.sec_seq_no) {
+ if (sec_info->max_seq_no ==
+ flash_hdr.sec_seq_no) {
+ if (sec_info->hdr_data_len <
+ flash_hdr.data_len)
+ sec_info->max_seq_sec = i;
+ } else {
+ sec_info->max_seq_sec = i;
+ sec_info->hdr_data_len =
+ flash_hdr.data_len;
+ }
+ sec_info->max_seq_no = flash_hdr.sec_seq_no;
+ }
+ }
+ }
+ rc = read_flash(adap, sec_info->max_seq_sec,
+ (struct cudbg_flash_hdr *)data,
+ size, sec_hdr_start_addr);
+
+ if (rc)
+ cudbg_init->print(adap->dip, CE_NOTE,
+ "Read flash header failed, rc %d\n",
+ rc);
+
+ return rc;
+ }
+
+ /* finding sector sequence sorted */
+ for (i = 1; i <= sec_info->max_seq_no; i++) {
+ for (j = CUDBG_START_SEC; j < CUDBG_SF_MAX_SECTOR; j++) {
+ memset(&flash_hdr, 0, sizeof(struct cudbg_flash_hdr));
+ rc = read_flash(adap, j, &flash_hdr,
+ sizeof(struct cudbg_flash_hdr),
+ sec_hdr_start_addr);
+
+ if (flash_hdr.signature ==
+ CUDBG_FL_SIGNATURE &&
+ sec_info->max_timestamp ==
+ flash_hdr.timestamp &&
+ flash_hdr.sec_seq_no == i) {
+ if (size + total_hdr_size >
+ CUDBG_SF_SECTOR_SIZE)
+ tmp_size = CUDBG_SF_SECTOR_SIZE -
+ total_hdr_size;
+ else
+ tmp_size = size;
+
+ if ((i != sec_info->max_seq_no) ||
+ (i == sec_info->max_seq_no &&
+ j == sec_info->max_seq_sec)){
+ /* filling data buffer with sector data
+ * except sector header
+ */
+ rc = read_flash(adap, j,
+ (void *)((char *)data +
+ data_offset),
+ tmp_size, 0);
+ data_offset += (tmp_size);
+ size -= (tmp_size);
+ break;
+ }
+ }
+ }
+ }
+
+ return rc;
+}
+
+int
+read_flash(struct adapter *adap, u32 start_sec , void *data, u32 size,
+ u32 start_address)
+{
+ unsigned int addr, i, n;
+ int rc;
+ u32 *ptr = (u32 *)data;
+ addr = start_sec * CUDBG_SF_SECTOR_SIZE + start_address;
+ size = size / 4;
+ for (i = 0; i < size; i += SF_PAGE_SIZE) {
+ if ((size - i) < SF_PAGE_SIZE)
+ n = size - i;
+ else
+ n = SF_PAGE_SIZE;
+ rc = t4_read_flash(adap, addr, n, ptr, 0);
+ if (rc)
+ goto out;
+
+ addr = addr + (n*4);
+ ptr += n;
+ }
+
+ return 0;
+out:
+ return rc;
+}
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
new file mode 100644
index 0000000000..cc194d8714
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.c
@@ -0,0 +1,4437 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*-
+ * Copyright (c) 2019 Chelsio Communications, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+
+#include "common/common.h"
+#include "common/t4_regs.h"
+#include "common/t4_chip_type.h"
+#include "cudbg.h"
+#include "cudbg_lib_common.h"
+#include "cudbg_lib.h"
+#include "cudbg_entity.h"
+
+#define BUFFER_WARN_LIMIT 10000000
+
+struct large_entity large_entity_list[] = {
+ {CUDBG_EDC0, 0, 0},
+ {CUDBG_EDC1, 0 , 0},
+ {CUDBG_MC0, 0, 0},
+ {CUDBG_MC1, 0, 0}
+};
+
+static int
+is_fw_attached(struct cudbg_init *pdbg_init)
+{
+
+ return (pdbg_init->adap->flags & FW_OK);
+}
+
+/* This function will add additional padding bytes into debug_buffer to make it
+ * 4 byte aligned.*/
+static void
+align_debug_buffer(struct cudbg_buffer *dbg_buff,
+ struct cudbg_entity_hdr *entity_hdr)
+{
+ u8 zero_buf[4] = {0};
+ u8 padding, remain;
+
+ remain = (dbg_buff->offset - entity_hdr->start_offset) % 4;
+ padding = 4 - remain;
+ if (remain) {
+ memcpy(((u8 *) dbg_buff->data) + dbg_buff->offset, &zero_buf,
+ padding);
+ dbg_buff->offset += padding;
+ entity_hdr->num_pad = padding;
+ }
+
+ entity_hdr->size = dbg_buff->offset - entity_hdr->start_offset;
+}
+
+static void
+u32_swap(void *a, void *b, int size)
+{
+ u32 t = *(u32 *)a;
+
+ *(u32 *)a = *(u32 *)b;
+ *(u32 *)b = t;
+}
+
+static void
+generic_swap(void *a1, void *b1, int size)
+{
+ u8 t;
+ u8 *a = (u8 *)a1;
+ u8 *b = (u8 *)b1;
+
+ do {
+ t = *a;
+ *(a++) = *b;
+ *(b++) = t;
+ } while (--size > 0);
+}
+
+static void
+qsort(void *base_val, int num, int size,
+ int (*cmp_func)(const void *, const void *),
+ void (*swap_func)(void *, void *, int size))
+{
+ /* pre-scale counters for performance */
+ int i = (num / 2 - 1) * size;
+ int n = num * size;
+ int c, r;
+ u8 *base = (u8 *)base_val;
+
+ if (!swap_func)
+ swap_func = (size == 4 ? u32_swap : generic_swap);
+
+ /* heapify */
+ for (; i >= 0; i -= size) {
+ for (r = i; r * 2 + size < n; r = c) {
+ c = r * 2 + size;
+ if (c < n - size &&
+ cmp_func(base + c, base + c + size) < 0)
+ c += size;
+ if (cmp_func(base + r, base + c) >= 0)
+ break;
+ swap_func(base + r, base + c, size);
+ }
+ }
+
+ /* sort */
+ for (i = n - size; i > 0; i -= size) {
+ swap_func(base, base + i, size);
+ for (r = 0; r * 2 + size < i; r = c) {
+ c = r * 2 + size;
+ if (c < i - size &&
+ cmp_func(base + c, base + c + size) < 0)
+ c += size;
+ if (cmp_func(base + r, base + c) >= 0)
+ break;
+ swap_func(base + r, base + c, size);
+ }
+ }
+}
+
+static void
+read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
+ enum ctxt_type ctype, u32 *data)
+{
+ struct adapter *padap = pdbg_init->adap;
+ int rc = -1;
+
+ if (is_fw_attached(pdbg_init)) {
+ rc =begin_synchronized_op(padap->port[0], 1, 1);
+ if (rc != 0)
+ goto out;
+ rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype,
+ data);
+ end_synchronized_op(padap->port[0], 1);
+ }
+
+out:
+ if (rc)
+ t4_sge_ctxt_rd_bd(padap, cid, ctype, data);
+}
+
+static int
+get_next_ext_entity_hdr(void *outbuf, u32 *ext_size,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_entity_hdr **entity_hdr)
+{
+ struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf;
+ int rc = 0;
+ u32 ext_offset = cudbg_hdr->data_len;
+ *ext_size = 0;
+
+ if (dbg_buff->size - dbg_buff->offset <=
+ sizeof(struct cudbg_entity_hdr)) {
+ rc = CUDBG_STATUS_BUFFER_SHORT;
+ goto err;
+ }
+
+ *entity_hdr = (struct cudbg_entity_hdr *)
+ ((char *)outbuf + cudbg_hdr->data_len);
+
+ /* Find the last extended entity header */
+ while ((*entity_hdr)->size) {
+
+ ext_offset += sizeof(struct cudbg_entity_hdr) +
+ (*entity_hdr)->size;
+
+ *ext_size += (*entity_hdr)->size +
+ sizeof(struct cudbg_entity_hdr);
+
+ if (dbg_buff->size - dbg_buff->offset + *ext_size <=
+ sizeof(struct cudbg_entity_hdr)) {
+ rc = CUDBG_STATUS_BUFFER_SHORT;
+ goto err;
+ }
+
+ if (ext_offset != (*entity_hdr)->next_ext_offset) {
+ ext_offset -= sizeof(struct cudbg_entity_hdr) +
+ (*entity_hdr)->size;
+ break;
+ }
+
+ (*entity_hdr)->next_ext_offset = *ext_size;
+
+ *entity_hdr = (struct cudbg_entity_hdr *)
+ ((char *)outbuf +
+ ext_offset);
+ }
+
+ /* update the data offset */
+ dbg_buff->offset = ext_offset;
+err:
+ return rc;
+}
+
+static int
+wr_entity_to_flash(void *handle, struct cudbg_buffer *dbg_buff,
+ u32 cur_entity_data_offset,
+ u32 cur_entity_size,
+ int entity_nu, u32 ext_size)
+{
+ struct cudbg_private *priv = handle;
+ struct cudbg_init *cudbg_init = &priv->dbg_init;
+ struct cudbg_flash_sec_info *sec_info = &priv->sec_info;
+ struct adapter *adap = cudbg_init->adap;
+ u64 timestamp;
+ u32 cur_entity_hdr_offset = sizeof(struct cudbg_hdr);
+ u32 remain_flash_size;
+ u32 flash_data_offset;
+ u32 data_hdr_size;
+ int rc = -1;
+
+ data_hdr_size = CUDBG_MAX_ENTITY * sizeof(struct cudbg_entity_hdr) +
+ sizeof(struct cudbg_hdr);
+
+ flash_data_offset = (FLASH_CUDBG_NSECS *
+ (sizeof(struct cudbg_flash_hdr) +
+ data_hdr_size)) +
+ (cur_entity_data_offset - data_hdr_size);
+
+ if (flash_data_offset > CUDBG_FLASH_SIZE) {
+ update_skip_size(sec_info, cur_entity_size);
+ if (cudbg_init->verbose)
+ cudbg_init->print(adap->dip, CE_NOTE,
+ "Large entity skipping...\n");
+ return rc;
+ }
+
+ remain_flash_size = CUDBG_FLASH_SIZE - flash_data_offset;
+
+ if (cur_entity_size > remain_flash_size) {
+ update_skip_size(sec_info, cur_entity_size);
+ if (cudbg_init->verbose)
+ cudbg_init->print(adap->dip, CE_NOTE,
+ "Large entity skipping...\n");
+ } else {
+ timestamp = 0;
+
+ cur_entity_hdr_offset +=
+ (sizeof(struct cudbg_entity_hdr) *
+ (entity_nu - 1));
+
+ rc = cudbg_write_flash(handle, timestamp, dbg_buff,
+ cur_entity_data_offset,
+ cur_entity_hdr_offset,
+ cur_entity_size,
+ ext_size);
+ if (rc == CUDBG_STATUS_FLASH_FULL && cudbg_init->verbose)
+ cudbg_init->print(adap->dip, CE_NOTE,
+ "\n\tFLASH is full... "
+ "can not write in flash more\n\n");
+ }
+
+ return rc;
+}
+
+int
+cudbg_collect(void *handle, void *outbuf, u32 *outbuf_size)
+{
+ struct cudbg_entity_hdr *entity_hdr = NULL;
+ struct cudbg_entity_hdr *ext_entity_hdr = NULL;
+ struct cudbg_hdr *cudbg_hdr;
+ struct cudbg_buffer dbg_buff;
+ struct cudbg_error cudbg_err = {0};
+ int large_entity_code;
+
+ u8 *dbg_bitmap = ((struct cudbg_private *)handle)->dbg_init.dbg_bitmap;
+ struct cudbg_init *cudbg_init =
+ &(((struct cudbg_private *)handle)->dbg_init);
+ struct adapter *padap = cudbg_init->adap;
+ u32 total_size, remaining_buf_size;
+ u32 ext_size = 0;
+ int index, bit, i, rc = -1;
+ int all;
+ bool flag_ext = 0;
+
+ reset_skip_entity();
+
+ dbg_buff.data = outbuf;
+ dbg_buff.size = *outbuf_size;
+ dbg_buff.offset = 0;
+
+ cudbg_hdr = (struct cudbg_hdr *)dbg_buff.data;
+ cudbg_hdr->signature = CUDBG_SIGNATURE;
+ cudbg_hdr->hdr_len = sizeof(struct cudbg_hdr);
+ cudbg_hdr->major_ver = CUDBG_MAJOR_VERSION;
+ cudbg_hdr->minor_ver = CUDBG_MINOR_VERSION;
+ cudbg_hdr->max_entities = CUDBG_MAX_ENTITY;
+ cudbg_hdr->chip_ver = padap->params.chip;
+
+ if (cudbg_hdr->data_len)
+ flag_ext = 1;
+
+ if (sizeof(struct cudbg_entity_hdr) * CUDBG_MAX_ENTITY >
+ dbg_buff.size) {
+ rc = CUDBG_STATUS_SMALL_BUFF;
+ total_size = cudbg_hdr->hdr_len;
+ goto err;
+ }
+
+ /* If ext flag is set then move the offset to the end of the buf
+ * so that we can add ext entities
+ */
+ if (flag_ext) {
+ ext_entity_hdr = (struct cudbg_entity_hdr *)
+ ((char *)outbuf + cudbg_hdr->hdr_len +
+ (sizeof(struct cudbg_entity_hdr) *
+ (CUDBG_EXT_ENTITY - 1)));
+ ext_entity_hdr->start_offset = cudbg_hdr->data_len;
+ ext_entity_hdr->entity_type = CUDBG_EXT_ENTITY;
+ ext_entity_hdr->size = 0;
+ dbg_buff.offset = cudbg_hdr->data_len;
+ } else {
+ dbg_buff.offset += cudbg_hdr->hdr_len; /* move 24 bytes*/
+ dbg_buff.offset += CUDBG_MAX_ENTITY *
+ sizeof(struct cudbg_entity_hdr);
+ }
+
+ total_size = dbg_buff.offset;
+ all = dbg_bitmap[0] & (1 << CUDBG_ALL);
+
+ for (i = 1; i < CUDBG_MAX_ENTITY; i++) {
+ index = i / 8;
+ bit = i % 8;
+
+ if (entity_list[i].bit == CUDBG_EXT_ENTITY)
+ continue;
+
+ if (all || (dbg_bitmap[index] & (1 << bit))) {
+
+ if (!flag_ext) {
+ rc = get_entity_hdr(outbuf, i, dbg_buff.size,
+ &entity_hdr);
+ if (rc)
+ cudbg_hdr->hdr_flags = rc;
+ } else {
+ rc = get_next_ext_entity_hdr(outbuf, &ext_size,
+ &dbg_buff,
+ &entity_hdr);
+ if (rc)
+ goto err;
+
+ /* move the offset after the ext header */
+ dbg_buff.offset +=
+ sizeof(struct cudbg_entity_hdr);
+ }
+
+ entity_hdr->entity_type = i;
+ entity_hdr->start_offset = dbg_buff.offset;
+ /* process each entity by calling process_entity fp */
+ remaining_buf_size = dbg_buff.size - dbg_buff.offset;
+
+ if ((remaining_buf_size <= BUFFER_WARN_LIMIT) &&
+ is_large_entity(i)) {
+ if (cudbg_init->verbose)
+ cudbg_init->print(padap->dip, CE_NOTE,
+ "Skipping %s\n",
+ entity_list[i].name);
+ skip_entity(i);
+ continue;
+ } else {
+
+ /* If fw_attach is 0, then skip entities which
+ * communicates with firmware
+ */
+
+ if (!is_fw_attached(cudbg_init) &&
+ (entity_list[i].flag &
+ (1 << ENTITY_FLAG_FW_NO_ATTACH))) {
+ if (cudbg_init->verbose)
+ cudbg_init->print(padap->dip, CE_NOTE,
+ "Skipping %s entity,"\
+ "because fw_attach "\
+ "is 0\n",
+ entity_list[i].name);
+ continue;
+ }
+
+ if (cudbg_init->verbose)
+ cudbg_init->print(padap->dip, CE_NOTE,
+ "collecting debug entity: "\
+ "%s\n", entity_list[i].name);
+ memset(&cudbg_err, 0,
+ sizeof(struct cudbg_error));
+ rc = process_entity[i-1](cudbg_init, &dbg_buff,
+ &cudbg_err);
+ }
+
+ if (rc) {
+ entity_hdr->size = 0;
+ dbg_buff.offset = entity_hdr->start_offset;
+ } else
+ align_debug_buffer(&dbg_buff, entity_hdr);
+
+ if (cudbg_err.sys_err)
+ rc = CUDBG_SYSTEM_ERROR;
+
+ entity_hdr->hdr_flags = rc;
+ entity_hdr->sys_err = cudbg_err.sys_err;
+ entity_hdr->sys_warn = cudbg_err.sys_warn;
+
+ /* We don't want to include ext entity size in global
+ * header
+ */
+ if (!flag_ext)
+ total_size += entity_hdr->size;
+
+ cudbg_hdr->data_len = total_size;
+ *outbuf_size = total_size;
+
+ /* consider the size of the ext entity header and data
+ * also
+ */
+ if (flag_ext) {
+ ext_size += (sizeof(struct cudbg_entity_hdr) +
+ entity_hdr->size);
+ entity_hdr->start_offset -= cudbg_hdr->data_len;
+ ext_entity_hdr->size = ext_size;
+ entity_hdr->next_ext_offset = ext_size;
+ entity_hdr->flag |= CUDBG_EXT_DATA_VALID;
+ }
+
+ if (cudbg_init->use_flash) {
+ if (flag_ext) {
+ wr_entity_to_flash(handle,
+ &dbg_buff,
+ ext_entity_hdr->
+ start_offset,
+ entity_hdr->
+ size,
+ CUDBG_EXT_ENTITY,
+ ext_size);
+ }
+ else
+ wr_entity_to_flash(handle,
+ &dbg_buff,
+ entity_hdr->\
+ start_offset,
+ entity_hdr->size,
+ i, ext_size);
+ }
+ }
+ }
+
+ for (i = 0; i < sizeof(large_entity_list) / sizeof(struct large_entity);
+ i++) {
+ large_entity_code = large_entity_list[i].entity_code;
+ if (large_entity_list[i].skip_flag) {
+ if (!flag_ext) {
+ rc = get_entity_hdr(outbuf, large_entity_code,
+ dbg_buff.size, &entity_hdr);
+ if (rc)
+ cudbg_hdr->hdr_flags = rc;
+ } else {
+ rc = get_next_ext_entity_hdr(outbuf, &ext_size,
+ &dbg_buff,
+ &entity_hdr);
+ if (rc)
+ goto err;
+
+ dbg_buff.offset +=
+ sizeof(struct cudbg_entity_hdr);
+ }
+
+ /* If fw_attach is 0, then skip entities which
+ * communicates with firmware
+ */
+ if (!is_fw_attached(cudbg_init) &&
+ (entity_list[large_entity_code].flag &
+ (1 << ENTITY_FLAG_FW_NO_ATTACH))) {
+ if (cudbg_init->verbose)
+ cudbg_init->print(padap->dip, CE_NOTE,
+ "Skipping %s entity,"\
+ "because fw_attach "\
+ "is 0\n",
+ entity_list[large_entity_code]
+ .name);
+ continue;
+ }
+
+ entity_hdr->entity_type = large_entity_code;
+ entity_hdr->start_offset = dbg_buff.offset;
+ if (cudbg_init->verbose)
+ cudbg_init->print(padap->dip, CE_NOTE,
+ "Re-trying debug entity: %s\n",
+ entity_list[large_entity_code].name);
+
+ memset(&cudbg_err, 0, sizeof(struct cudbg_error));
+ rc = process_entity[large_entity_code - 1](cudbg_init,
+ &dbg_buff,
+ &cudbg_err);
+ if (rc) {
+ entity_hdr->size = 0;
+ dbg_buff.offset = entity_hdr->start_offset;
+ } else
+ align_debug_buffer(&dbg_buff, entity_hdr);
+
+ if (cudbg_err.sys_err)
+ rc = CUDBG_SYSTEM_ERROR;
+
+ entity_hdr->hdr_flags = rc;
+ entity_hdr->sys_err = cudbg_err.sys_err;
+ entity_hdr->sys_warn = cudbg_err.sys_warn;
+
+ /* We don't want to include ext entity size in global
+ * header
+ */
+ if (!flag_ext)
+ total_size += entity_hdr->size;
+
+ cudbg_hdr->data_len = total_size;
+ *outbuf_size = total_size;
+
+ /* consider the size of the ext entity header and
+ * data also
+ */
+ if (flag_ext) {
+ ext_size += (sizeof(struct cudbg_entity_hdr) +
+ entity_hdr->size);
+ entity_hdr->start_offset -=
+ cudbg_hdr->data_len;
+ ext_entity_hdr->size = ext_size;
+ entity_hdr->flag |= CUDBG_EXT_DATA_VALID;
+ }
+
+ if (cudbg_init->use_flash) {
+ if (flag_ext)
+ wr_entity_to_flash(handle,
+ &dbg_buff,
+ ext_entity_hdr->
+ start_offset,
+ entity_hdr->size,
+ CUDBG_EXT_ENTITY,
+ ext_size);
+ else
+ wr_entity_to_flash(handle,
+ &dbg_buff,
+ entity_hdr->
+ start_offset,
+ entity_hdr->
+ size,
+ large_entity_list[i].
+ entity_code,
+ ext_size);
+ }
+ }
+ }
+
+ cudbg_hdr->data_len = total_size;
+ *outbuf_size = total_size;
+
+ if (flag_ext)
+ *outbuf_size += ext_size;
+
+ return 0;
+err:
+ return rc;
+}
+
+void
+reset_skip_entity(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(large_entity_list); i++)
+ large_entity_list[i].skip_flag = 0;
+}
+
+void
+skip_entity(int entity_code)
+{
+ int i;
+ for (i = 0; i < sizeof(large_entity_list) / sizeof(struct large_entity);
+ i++) {
+ if (large_entity_list[i].entity_code == entity_code)
+ large_entity_list[i].skip_flag = 1;
+ }
+}
+
+int
+is_large_entity(int entity_code)
+{
+ int i;
+
+ for (i = 0; i < sizeof(large_entity_list) / sizeof(struct large_entity);
+ i++) {
+ if (large_entity_list[i].entity_code == entity_code)
+ return 1;
+ }
+ return 0;
+}
+
+int
+get_entity_hdr(void *outbuf, int i, u32 size,
+ struct cudbg_entity_hdr **entity_hdr)
+{
+ int rc = 0;
+ struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf;
+
+ if (cudbg_hdr->hdr_len + (sizeof(struct cudbg_entity_hdr)*i) > size)
+ return CUDBG_STATUS_SMALL_BUFF;
+
+ *entity_hdr = (struct cudbg_entity_hdr *)
+ ((char *)outbuf+cudbg_hdr->hdr_len +
+ (sizeof(struct cudbg_entity_hdr)*(i-1)));
+ return rc;
+}
+
+static int
+collect_rss(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ u32 size;
+ int rc = 0;
+
+ size = RSS_NENTRIES * sizeof(u16);
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ rc = t4_read_rss(padap, (u16 *)scratch_buff.data);
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s(), t4_read_rss failed!, rc: %d\n",
+ __func__, rc);
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_sw_state(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct sw_state *swstate;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct sw_state);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ swstate = (struct sw_state *) scratch_buff.data;
+
+ swstate->fw_state = t4_read_reg(padap, A_PCIE_FW);
+ snprintf((char *)swstate->caller_string, sizeof(swstate->caller_string), "%s",
+ "Illumos");
+ swstate->os_type = 0;
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_ddp_stats(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct tp_usm_stats *tp_usm_stats_buff;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct tp_usm_stats);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ tp_usm_stats_buff = (struct tp_usm_stats *) scratch_buff.data;
+
+ /* spin_lock(&padap->stats_lock); TODO*/
+ t4_get_usm_stats(padap, tp_usm_stats_buff, 1);
+ /* spin_unlock(&padap->stats_lock); TODO*/
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_ulptx_la(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_ulptx_la *ulptx_la_buff;
+ u32 size, i, j;
+ int rc = 0;
+
+ size = sizeof(struct struct_ulptx_la);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ ulptx_la_buff = (struct struct_ulptx_la *) scratch_buff.data;
+
+ for (i = 0; i < CUDBG_NUM_ULPTX; i++) {
+ ulptx_la_buff->rdptr[i] = t4_read_reg(padap,
+ A_ULP_TX_LA_RDPTR_0 +
+ 0x10 * i);
+ ulptx_la_buff->wrptr[i] = t4_read_reg(padap,
+ A_ULP_TX_LA_WRPTR_0 +
+ 0x10 * i);
+ ulptx_la_buff->rddata[i] = t4_read_reg(padap,
+ A_ULP_TX_LA_RDDATA_0 +
+ 0x10 * i);
+ for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++) {
+ ulptx_la_buff->rd_data[i][j] =
+ t4_read_reg(padap,
+ A_ULP_TX_LA_RDDATA_0 + 0x10 * i);
+ }
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+
+}
+
+static int
+collect_ulprx_la(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_ulprx_la *ulprx_la_buff;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct struct_ulprx_la);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ ulprx_la_buff = (struct struct_ulprx_la *) scratch_buff.data;
+ t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data);
+ ulprx_la_buff->size = ULPRX_LA_SIZE;
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_cpl_stats(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_tp_cpl_stats *tp_cpl_stats_buff;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct struct_tp_cpl_stats);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ tp_cpl_stats_buff = (struct struct_tp_cpl_stats *) scratch_buff.data;
+ tp_cpl_stats_buff->nchan = padap->params.arch.nchan;
+
+ t4_tp_get_cpl_stats(padap, &tp_cpl_stats_buff->stats, 1);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_wc_stats(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_wc_stats *wc_stats_buff;
+ u32 val1;
+ u32 val2;
+ u32 size;
+
+ int rc = 0;
+
+ size = sizeof(struct struct_wc_stats);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ wc_stats_buff = (struct struct_wc_stats *) scratch_buff.data;
+
+ if (!is_t4(padap->params.chip)) {
+ val1 = t4_read_reg(padap, A_SGE_STAT_TOTAL);
+ val2 = t4_read_reg(padap, A_SGE_STAT_MATCH);
+ wc_stats_buff->wr_cl_success = val1 - val2;
+ wc_stats_buff->wr_cl_fail = val2;
+ } else {
+ wc_stats_buff->wr_cl_success = 0;
+ wc_stats_buff->wr_cl_fail = 0;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+mem_desc_cmp(const void *a, const void *b)
+{
+ return ((const struct struct_mem_desc *)a)->base -
+ ((const struct struct_mem_desc *)b)->base;
+}
+
+static int
+fill_meminfo(struct adapter *padap,
+ struct struct_meminfo *meminfo_buff)
+{
+ struct struct_mem_desc *md;
+ u32 size, lo, hi;
+ u32 used, alloc;
+ int n, i, rc = 0;
+
+ size = sizeof(struct struct_meminfo);
+
+ memset(meminfo_buff->avail, 0,
+ ARRAY_SIZE(meminfo_buff->avail) *
+ sizeof(struct struct_mem_desc));
+ memset(meminfo_buff->mem, 0,
+ (ARRAY_SIZE(region) + 3) * sizeof(struct struct_mem_desc));
+ md = meminfo_buff->mem;
+
+ for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) {
+ meminfo_buff->mem[i].limit = 0;
+ meminfo_buff->mem[i].idx = i;
+ }
+
+ i = 0;
+
+ lo = t4_read_reg(padap, A_MA_TARGET_MEM_ENABLE);
+
+ if (lo & F_EDRAM0_ENABLE) {
+ hi = t4_read_reg(padap, A_MA_EDRAM0_BAR);
+ meminfo_buff->avail[i].base = G_EDRAM0_BASE(hi) << 20;
+ meminfo_buff->avail[i].limit = meminfo_buff->avail[i].base +
+ (G_EDRAM0_SIZE(hi) << 20);
+ meminfo_buff->avail[i].idx = 0;
+ i++;
+ }
+
+ if (lo & F_EDRAM1_ENABLE) {
+ hi = t4_read_reg(padap, A_MA_EDRAM1_BAR);
+ meminfo_buff->avail[i].base = G_EDRAM1_BASE(hi) << 20;
+ meminfo_buff->avail[i].limit = meminfo_buff->avail[i].base +
+ (G_EDRAM1_SIZE(hi) << 20);
+ meminfo_buff->avail[i].idx = 1;
+ i++;
+ }
+
+ if (is_t5(padap->params.chip)) {
+ if (lo & F_EXT_MEM0_ENABLE) {
+ hi = t4_read_reg(padap, A_MA_EXT_MEMORY0_BAR);
+ meminfo_buff->avail[i].base = G_EXT_MEM_BASE(hi) << 20;
+ meminfo_buff->avail[i].limit =
+ meminfo_buff->avail[i].base +
+ (G_EXT_MEM_SIZE(hi) << 20);
+ meminfo_buff->avail[i].idx = 3;
+ i++;
+ }
+
+ if (lo & F_EXT_MEM1_ENABLE) {
+ hi = t4_read_reg(padap, A_MA_EXT_MEMORY1_BAR);
+ meminfo_buff->avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
+ meminfo_buff->avail[i].limit =
+ meminfo_buff->avail[i].base +
+ (G_EXT_MEM1_SIZE(hi) << 20);
+ meminfo_buff->avail[i].idx = 4;
+ i++;
+ }
+ } else if (is_t6(padap->params.chip)) {
+ if (lo & F_EXT_MEM_ENABLE) {
+ hi = t4_read_reg(padap, A_MA_EXT_MEMORY_BAR);
+ meminfo_buff->avail[i].base = G_EXT_MEM_BASE(hi) << 20;
+ meminfo_buff->avail[i].limit =
+ meminfo_buff->avail[i].base +
+ (G_EXT_MEM_SIZE(hi) << 20);
+ meminfo_buff->avail[i].idx = 2;
+ i++;
+ }
+ }
+
+ if (!i) { /* no memory available */
+ rc = CUDBG_STATUS_ENTITY_NOT_FOUND;
+ goto err;
+ }
+
+ meminfo_buff->avail_c = i;
+ qsort(meminfo_buff->avail, i, sizeof(struct struct_mem_desc),
+ mem_desc_cmp, NULL);
+ (md++)->base = t4_read_reg(padap, A_SGE_DBQ_CTXT_BADDR);
+ (md++)->base = t4_read_reg(padap, A_SGE_IMSG_CTXT_BADDR);
+ (md++)->base = t4_read_reg(padap, A_SGE_FLM_CACHE_BADDR);
+ (md++)->base = t4_read_reg(padap, A_TP_CMM_TCB_BASE);
+ (md++)->base = t4_read_reg(padap, A_TP_CMM_MM_BASE);
+ (md++)->base = t4_read_reg(padap, A_TP_CMM_TIMER_BASE);
+ (md++)->base = t4_read_reg(padap, A_TP_CMM_MM_RX_FLST_BASE);
+ (md++)->base = t4_read_reg(padap, A_TP_CMM_MM_TX_FLST_BASE);
+ (md++)->base = t4_read_reg(padap, A_TP_CMM_MM_PS_FLST_BASE);
+
+ /* the next few have explicit upper bounds */
+ md->base = t4_read_reg(padap, A_TP_PMM_TX_BASE);
+ md->limit = md->base - 1 +
+ t4_read_reg(padap,
+ A_TP_PMM_TX_PAGE_SIZE) *
+ G_PMTXMAXPAGE(t4_read_reg(padap,
+ A_TP_PMM_TX_MAX_PAGE)
+ );
+ md++;
+
+ md->base = t4_read_reg(padap, A_TP_PMM_RX_BASE);
+ md->limit = md->base - 1 +
+ t4_read_reg(padap,
+ A_TP_PMM_RX_PAGE_SIZE) *
+ G_PMRXMAXPAGE(t4_read_reg(padap,
+ A_TP_PMM_RX_MAX_PAGE)
+ );
+ md++;
+ if (t4_read_reg(padap, A_LE_DB_CONFIG) & F_HASHEN) {
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) {
+ hi = t4_read_reg(padap, A_LE_DB_TID_HASHBASE) / 4;
+ md->base = t4_read_reg(padap, A_LE_DB_HASH_TID_BASE);
+ } else {
+ hi = t4_read_reg(padap, A_LE_DB_HASH_TID_BASE);
+ md->base = t4_read_reg(padap,
+ A_LE_DB_HASH_TBL_BASE_ADDR);
+ }
+ md->limit = 0;
+ } else {
+ md->base = 0;
+ md->idx = ARRAY_SIZE(region); /* hide it */
+ }
+ md++;
+#define ulp_region(reg) \
+ {\
+ md->base = t4_read_reg(padap, A_ULP_ ## reg ## _LLIMIT);\
+ (md++)->limit = t4_read_reg(padap, A_ULP_ ## reg ## _ULIMIT);\
+ }
+
+ ulp_region(RX_ISCSI);
+ ulp_region(RX_TDDP);
+ ulp_region(TX_TPT);
+ ulp_region(RX_STAG);
+ ulp_region(RX_RQ);
+ ulp_region(RX_RQUDP);
+ ulp_region(RX_PBL);
+ ulp_region(TX_PBL);
+#undef ulp_region
+ md->base = 0;
+ md->idx = ARRAY_SIZE(region);
+ if (!is_t4(padap->params.chip)) {
+ u32 sge_ctrl = t4_read_reg(padap, A_SGE_CONTROL2);
+ u32 fifo_size = t4_read_reg(padap, A_SGE_DBVFIFO_SIZE);
+ if (is_t5(padap->params.chip)) {
+ if (sge_ctrl & F_VFIFO_ENABLE)
+ size = G_DBVFIFO_SIZE(fifo_size);
+ } else
+ size = G_T6_DBVFIFO_SIZE(fifo_size);
+
+ if (size) {
+ md->base = G_BASEADDR(t4_read_reg(padap,
+ A_SGE_DBVFIFO_BADDR));
+ md->limit = md->base + (size << 2) - 1;
+ }
+ }
+
+ md++;
+
+ md->base = t4_read_reg(padap, A_ULP_RX_CTX_BASE);
+ md->limit = 0;
+ md++;
+ md->base = t4_read_reg(padap, A_ULP_TX_ERR_TABLE_BASE);
+ md->limit = 0;
+ md++;
+#ifndef __NO_DRIVER_OCQ_SUPPORT__
+ /*md->base = padap->vres.ocq.start;*/
+ /*if (adap->vres.ocq.size)*/
+ /* md->limit = md->base + adap->vres.ocq.size - 1;*/
+ /*else*/
+ md->idx = ARRAY_SIZE(region); /* hide it */
+ md++;
+#endif
+
+ /* add any address-space holes, there can be up to 3 */
+ for (n = 0; n < i - 1; n++)
+ if (meminfo_buff->avail[n].limit <
+ meminfo_buff->avail[n + 1].base)
+ (md++)->base = meminfo_buff->avail[n].limit;
+
+ if (meminfo_buff->avail[n].limit)
+ (md++)->base = meminfo_buff->avail[n].limit;
+
+ n = (int) (md - meminfo_buff->mem);
+ meminfo_buff->mem_c = n;
+
+ qsort(meminfo_buff->mem, n, sizeof(struct struct_mem_desc),
+ mem_desc_cmp, NULL);
+
+ lo = t4_read_reg(padap, A_CIM_SDRAM_BASE_ADDR);
+ hi = t4_read_reg(padap, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
+ meminfo_buff->up_ram_lo = lo;
+ meminfo_buff->up_ram_hi = hi;
+
+ lo = t4_read_reg(padap, A_CIM_EXTMEM2_BASE_ADDR);
+ hi = t4_read_reg(padap, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
+ meminfo_buff->up_extmem2_lo = lo;
+ meminfo_buff->up_extmem2_hi = hi;
+
+ lo = t4_read_reg(padap, A_TP_PMM_RX_MAX_PAGE);
+ meminfo_buff->rx_pages_data[0] = G_PMRXMAXPAGE(lo);
+ meminfo_buff->rx_pages_data[1] =
+ t4_read_reg(padap, A_TP_PMM_RX_PAGE_SIZE) >> 10;
+ meminfo_buff->rx_pages_data[2] = (lo & F_PMRXNUMCHN) ? 2 : 1 ;
+
+ lo = t4_read_reg(padap, A_TP_PMM_TX_MAX_PAGE);
+ hi = t4_read_reg(padap, A_TP_PMM_TX_PAGE_SIZE);
+ meminfo_buff->tx_pages_data[0] = G_PMTXMAXPAGE(lo);
+ meminfo_buff->tx_pages_data[1] =
+ hi >= (1 << 20) ? (hi >> 20) : (hi >> 10);
+ meminfo_buff->tx_pages_data[2] =
+ hi >= (1 << 20) ? 'M' : 'K';
+ meminfo_buff->tx_pages_data[3] = 1 << G_PMTXNUMCHN(lo);
+
+ for (i = 0; i < 4; i++) {
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
+ lo = t4_read_reg(padap,
+ A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
+ else
+ lo = t4_read_reg(padap, A_MPS_RX_PG_RSV0 + i * 4);
+ if (is_t5(padap->params.chip)) {
+ used = G_T5_USED(lo);
+ alloc = G_T5_ALLOC(lo);
+ } else {
+ used = G_USED(lo);
+ alloc = G_ALLOC(lo);
+ }
+ meminfo_buff->port_used[i] = used;
+ meminfo_buff->port_alloc[i] = alloc;
+ }
+
+ for (i = 0; i < padap->params.arch.nchan; i++) {
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
+ lo = t4_read_reg(padap,
+ A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
+ else
+ lo = t4_read_reg(padap, A_MPS_RX_PG_RSV4 + i * 4);
+ if (is_t5(padap->params.chip)) {
+ used = G_T5_USED(lo);
+ alloc = G_T5_ALLOC(lo);
+ } else {
+ used = G_USED(lo);
+ alloc = G_ALLOC(lo);
+ }
+ meminfo_buff->loopback_used[i] = used;
+ meminfo_buff->loopback_alloc[i] = alloc;
+ }
+err:
+ return rc;
+}
+
+static int
+collect_meminfo(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct struct_meminfo *meminfo_buff;
+ struct cudbg_buffer scratch_buff;
+ int rc = 0;
+ u32 size;
+
+ size = sizeof(struct struct_meminfo);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ meminfo_buff = (struct struct_meminfo *)scratch_buff.data;
+
+ rc = fill_meminfo(padap, meminfo_buff);
+ if (rc)
+ goto err;
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_lb_stats(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct struct_lb_stats *lb_stats_buff;
+ struct cudbg_buffer scratch_buff;
+ struct lb_port_stats *tmp_stats;
+ u32 i, n, size;
+ int rc = 0;
+
+ rc = padap->params.nports;
+ if (rc < 0)
+ goto err;
+
+ n = rc;
+ size = sizeof(struct struct_lb_stats) +
+ n * sizeof(struct lb_port_stats);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ lb_stats_buff = (struct struct_lb_stats *) scratch_buff.data;
+
+ lb_stats_buff->nchan = n;
+ tmp_stats = lb_stats_buff->s;
+
+ for (i = 0; i < n; i += 2, tmp_stats += 2) {
+ t4_get_lb_stats(padap, i, tmp_stats);
+ t4_get_lb_stats(padap, i + 1, tmp_stats+1);
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_rdma_stats(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_er)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct tp_rdma_stats *rdma_stats_buff;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct tp_rdma_stats);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ rdma_stats_buff = (struct tp_rdma_stats *) scratch_buff.data;
+
+ /* spin_lock(&padap->stats_lock); TODO*/
+ t4_tp_get_rdma_stats(padap, rdma_stats_buff, 1);
+ /* spin_unlock(&padap->stats_lock); TODO*/
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_clk_info(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct struct_clk_info *clk_info_buff;
+ u64 tp_tick_us;
+ int size;
+ int rc = 0;
+
+ if (!padap->params.vpd.cclk) {
+ rc = CUDBG_STATUS_CCLK_NOT_DEFINED;
+ goto err;
+ }
+
+ size = sizeof(struct struct_clk_info);
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ clk_info_buff = (struct struct_clk_info *) scratch_buff.data;
+
+ clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk; /* in ps
+ */
+ clk_info_buff->res = t4_read_reg(padap, A_TP_TIMER_RESOLUTION);
+ clk_info_buff->tre = G_TIMERRESOLUTION(clk_info_buff->res);
+ clk_info_buff->dack_re = G_DELAYEDACKRESOLUTION(clk_info_buff->res);
+ tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000;
+ /* in us */
+ clk_info_buff->dack_timer = ((clk_info_buff->cclk_ps <<
+ clk_info_buff->dack_re) / 1000000) *
+ t4_read_reg(padap, A_TP_DACK_TIMER);
+
+ clk_info_buff->retransmit_min =
+ tp_tick_us * t4_read_reg(padap, A_TP_RXT_MIN);
+ clk_info_buff->retransmit_max =
+ tp_tick_us * t4_read_reg(padap, A_TP_RXT_MAX);
+
+ clk_info_buff->persist_timer_min =
+ tp_tick_us * t4_read_reg(padap, A_TP_PERS_MIN);
+ clk_info_buff->persist_timer_max =
+ tp_tick_us * t4_read_reg(padap, A_TP_PERS_MAX);
+
+ clk_info_buff->keepalive_idle_timer =
+ tp_tick_us * t4_read_reg(padap, A_TP_KEEP_IDLE);
+ clk_info_buff->keepalive_interval =
+ tp_tick_us * t4_read_reg(padap, A_TP_KEEP_INTVL);
+
+ clk_info_buff->initial_srtt =
+ tp_tick_us * G_INITSRTT(t4_read_reg(padap, A_TP_INIT_SRTT));
+ clk_info_buff->finwait2_timer =
+ tp_tick_us * t4_read_reg(padap, A_TP_FINWAIT2_TIMER);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+
+}
+
+static int
+collect_macstats(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_mac_stats_rev1 *mac_stats_buff;
+ u32 i, n, size;
+ int rc = 0;
+
+ rc = padap->params.nports;
+ if (rc < 0)
+ goto err;
+
+ n = rc;
+ size = sizeof(struct struct_mac_stats_rev1);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ mac_stats_buff = (struct struct_mac_stats_rev1 *) scratch_buff.data;
+
+ mac_stats_buff->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ mac_stats_buff->ver_hdr.revision = CUDBG_MAC_STATS_REV;
+ mac_stats_buff->ver_hdr.size = sizeof(struct struct_mac_stats_rev1) -
+ sizeof(struct cudbg_ver_hdr);
+
+ mac_stats_buff->port_count = n;
+ for (i = 0; i < mac_stats_buff->port_count; i++)
+ t4_get_port_stats(padap, i, &mac_stats_buff->stats[i]);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_cim_pif_la(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct cim_pif_la *cim_pif_la_buff;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct cim_pif_la) +
+ 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ cim_pif_la_buff = (struct cim_pif_la *) scratch_buff.data;
+ cim_pif_la_buff->size = CIM_PIFLA_SIZE;
+
+ t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data,
+ (u32 *)cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE,
+ NULL, NULL);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_tp_la(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_tp_la *tp_la_buff;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct struct_tp_la) + TPLA_SIZE * sizeof(u64);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ tp_la_buff = (struct struct_tp_la *) scratch_buff.data;
+
+ tp_la_buff->mode = G_DBGLAMODE(t4_read_reg(padap, A_TP_DBG_LA_CONFIG));
+ t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_fcoe_stats(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_tp_fcoe_stats *tp_fcoe_stats_buff;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct struct_tp_fcoe_stats);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ tp_fcoe_stats_buff = (struct struct_tp_fcoe_stats *) scratch_buff.data;
+
+ t4_get_fcoe_stats(padap, 0, &tp_fcoe_stats_buff->stats[0], 1);
+ t4_get_fcoe_stats(padap, 1, &tp_fcoe_stats_buff->stats[1], 1);
+
+ if (padap->params.arch.nchan == NCHAN) {
+ t4_get_fcoe_stats(padap, 2, &tp_fcoe_stats_buff->stats[2], 1);
+ t4_get_fcoe_stats(padap, 3, &tp_fcoe_stats_buff->stats[3], 1);
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_tp_err_stats(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_tp_err_stats *tp_err_stats_buff;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct struct_tp_err_stats);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ tp_err_stats_buff = (struct struct_tp_err_stats *) scratch_buff.data;
+
+ t4_tp_get_err_stats(padap, &tp_err_stats_buff->stats, 1);
+ tp_err_stats_buff->nchan = padap->params.arch.nchan;
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_tcp_stats(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_tcp_stats *tcp_stats_buff;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct struct_tcp_stats);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ tcp_stats_buff = (struct struct_tcp_stats *) scratch_buff.data;
+
+ /* spin_lock(&padap->stats_lock); TODO*/
+ t4_tp_get_tcp_stats(padap, &tcp_stats_buff->v4, &tcp_stats_buff->v6, 1);
+ /* spin_unlock(&padap->stats_lock); TODO*/
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_hw_sched(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_hw_sched *hw_sched_buff;
+ u32 size;
+ int i, rc = 0;
+
+ if (!padap->params.vpd.cclk) {
+ rc = CUDBG_STATUS_CCLK_NOT_DEFINED;
+ goto err;
+ }
+
+ size = sizeof(struct struct_hw_sched);
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ hw_sched_buff = (struct struct_hw_sched *) scratch_buff.data;
+
+ hw_sched_buff->map = t4_read_reg(padap, A_TP_TX_MOD_QUEUE_REQ_MAP);
+ hw_sched_buff->mode = G_TIMERMODE(t4_read_reg(padap, A_TP_MOD_CONFIG));
+ t4_read_pace_tbl(padap, hw_sched_buff->pace_tab);
+
+ for (i = 0; i < NTX_SCHED; ++i) {
+ t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i],
+ &hw_sched_buff->ipg[i], 1);
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_pm_stats(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct struct_pm_stats *pm_stats_buff;
+ u32 size;
+ int rc = 0;
+
+ size = sizeof(struct struct_pm_stats);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ pm_stats_buff = (struct struct_pm_stats *) scratch_buff.data;
+
+ t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc);
+ t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_path_mtu(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ u32 size;
+ int rc = 0;
+
+ size = NMTUS * sizeof(u16);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ t4_read_mtu_tbl(padap, (u16 *)scratch_buff.data, NULL);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_rss_key(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ u32 size;
+
+ int rc = 0;
+
+ size = 10 * sizeof(u32);
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ t4_read_rss_key(padap, (u32 *)scratch_buff.data, 1);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_rss_config(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct rss_config *rss_conf;
+ int rc;
+ u32 size;
+
+ size = sizeof(struct rss_config);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ rss_conf = (struct rss_config *)scratch_buff.data;
+
+ rss_conf->tp_rssconf = t4_read_reg(padap, A_TP_RSS_CONFIG);
+ rss_conf->tp_rssconf_tnl = t4_read_reg(padap, A_TP_RSS_CONFIG_TNL);
+ rss_conf->tp_rssconf_ofd = t4_read_reg(padap, A_TP_RSS_CONFIG_OFD);
+ rss_conf->tp_rssconf_syn = t4_read_reg(padap, A_TP_RSS_CONFIG_SYN);
+ rss_conf->tp_rssconf_vrt = t4_read_reg(padap, A_TP_RSS_CONFIG_VRT);
+ rss_conf->tp_rssconf_cng = t4_read_reg(padap, A_TP_RSS_CONFIG_CNG);
+ rss_conf->chip = padap->params.chip;
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_rss_vf_config(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ struct rss_vf_conf *vfconf;
+ int vf, rc, vf_count = 0;
+ u32 size;
+
+ vf_count = padap->params.arch.vfcount;
+ size = vf_count * sizeof(*vfconf);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ vfconf = (struct rss_vf_conf *)scratch_buff.data;
+
+ for (vf = 0; vf < vf_count; vf++) {
+ t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl,
+ &vfconf[vf].rss_vf_vfh, 1);
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_rss_pf_config(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct rss_pf_conf *pfconf;
+ struct adapter *padap = pdbg_init->adap;
+ u32 rss_pf_map, rss_pf_mask, size;
+ int pf, rc;
+
+ size = 8 * sizeof(*pfconf);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ pfconf = (struct rss_pf_conf *)scratch_buff.data;
+
+ rss_pf_map = t4_read_rss_pf_map(padap, 1);
+ rss_pf_mask = t4_read_rss_pf_mask(padap, 1);
+
+ for (pf = 0; pf < 8; pf++) {
+ pfconf[pf].rss_pf_map = rss_pf_map;
+ pfconf[pf].rss_pf_mask = rss_pf_mask;
+ /* no return val */
+ t4_read_rss_pf_config(padap, pf, &pfconf[pf].rss_pf_config, 1);
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+check_valid(u32 *buf, int type)
+{
+ int index;
+ int bit;
+ int bit_pos = 0;
+
+ switch (type) {
+ case CTXT_EGRESS:
+ bit_pos = 176;
+ break;
+ case CTXT_INGRESS:
+ bit_pos = 141;
+ break;
+ case CTXT_FLM:
+ bit_pos = 89;
+ break;
+ }
+ index = bit_pos / 32;
+ bit = bit_pos % 32;
+
+ return buf[index] & (1U << bit);
+}
+
+/**
+ * Get EGRESS, INGRESS, FLM, and CNM max qid.
+ *
+ * For EGRESS and INGRESS, do the following calculation.
+ * max_qid = (DBQ/IMSG context region size in bytes) /
+ * (size of context in bytes).
+ *
+ * For FLM, do the following calculation.
+ * max_qid = (FLM cache region size in bytes) /
+ * ((number of pointers cached in EDRAM) * 8 (bytes per pointer)).
+ *
+ * There's a 1-to-1 mapping between FLM and CNM if there's no header splitting
+ * enabled; i.e., max CNM qid is equal to max FLM qid. However, if header
+ * splitting is enabled, then max CNM qid is half of max FLM qid.
+ */
+static int
+get_max_ctxt_qid(struct adapter *padap,
+ struct struct_meminfo *meminfo,
+ u32 *max_ctx_qid, u8 nelem)
+{
+ u32 i, idx, found = 0;
+
+ if (nelem != (CTXT_CNM + 1))
+ return -EINVAL;
+
+ for (i = 0; i < meminfo->mem_c; i++) {
+ if (meminfo->mem[i].idx >= ARRAY_SIZE(region))
+ continue; /* skip holes */
+
+ idx = meminfo->mem[i].idx;
+ /* Get DBQ, IMSG, and FLM context region size */
+ if (idx <= CTXT_FLM) {
+ if (!(meminfo->mem[i].limit))
+ meminfo->mem[i].limit =
+ i < meminfo->mem_c - 1 ?
+ meminfo->mem[i + 1].base - 1 : ~0;
+
+ if (idx < CTXT_FLM) {
+ /* Get EGRESS and INGRESS max qid. */
+ max_ctx_qid[idx] = (meminfo->mem[i].limit -
+ meminfo->mem[i].base + 1) /
+ CUDBG_CTXT_SIZE_BYTES;
+ found++;
+ } else {
+ /* Get FLM and CNM max qid. */
+ u32 value, edram_ptr_count;
+ u8 bytes_per_ptr = 8;
+ u8 nohdr;
+
+ value = t4_read_reg(padap, A_SGE_FLM_CFG);
+
+ /* Check if header splitting is enabled. */
+ nohdr = (value >> S_NOHDR) & 1U;
+
+ /* Get the number of pointers in EDRAM per
+ * qid in units of 32.
+ */
+ edram_ptr_count = 32 *
+ (1U << G_EDRAMPTRCNT(value));
+
+ /* EDRAMPTRCNT value of 3 is reserved.
+ * So don't exceed 128.
+ */
+ if (edram_ptr_count > 128)
+ edram_ptr_count = 128;
+
+ max_ctx_qid[idx] = (meminfo->mem[i].limit -
+ meminfo->mem[i].base + 1) /
+ (edram_ptr_count *
+ bytes_per_ptr);
+ found++;
+
+ /* CNM has 1-to-1 mapping with FLM.
+ * However, if header splitting is enabled,
+ * then max CNM qid is half of max FLM qid.
+ */
+ max_ctx_qid[CTXT_CNM] = nohdr ?
+ max_ctx_qid[idx] :
+ max_ctx_qid[idx] >> 1;
+
+ /* One more increment for CNM */
+ found++;
+ }
+ }
+ if (found == nelem)
+ break;
+ }
+
+ /* Sanity check. Ensure the values are within known max. */
+ max_ctx_qid[CTXT_EGRESS] = min_t(u32, max_ctx_qid[CTXT_EGRESS],
+ M_CTXTQID);
+ max_ctx_qid[CTXT_INGRESS] = min_t(u32, max_ctx_qid[CTXT_INGRESS],
+ CUDBG_MAX_INGRESS_QIDS);
+ max_ctx_qid[CTXT_FLM] = min_t(u32, max_ctx_qid[CTXT_FLM],
+ CUDBG_MAX_FL_QIDS);
+ max_ctx_qid[CTXT_CNM] = min_t(u32, max_ctx_qid[CTXT_CNM],
+ CUDBG_MAX_CNM_QIDS);
+ return 0;
+}
+
+static int
+collect_dump_context(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct cudbg_buffer temp_buff;
+ struct adapter *padap = pdbg_init->adap;
+ u32 size = 0, next_offset = 0, total_size = 0;
+ struct cudbg_ch_cntxt *buff = NULL;
+ struct struct_meminfo meminfo;
+ int bytes = 0;
+ int rc = 0;
+ u32 i, j;
+ u32 max_ctx_qid[CTXT_CNM + 1];
+ bool limit_qid = false;
+ u32 qid_count = 0;
+
+ rc = fill_meminfo(padap, &meminfo);
+ if (rc)
+ goto err;
+
+ /* Get max valid qid for each type of queue */
+ rc = get_max_ctxt_qid(padap, &meminfo, max_ctx_qid, CTXT_CNM + 1);
+ if (rc)
+ goto err;
+
+ /* There are four types of queues. Collect context upto max
+ * qid of each type of queue.
+ */
+ for (i = CTXT_EGRESS; i <= CTXT_CNM; i++)
+ size += sizeof(struct cudbg_ch_cntxt) * max_ctx_qid[i];
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc == CUDBG_STATUS_NO_SCRATCH_MEM) {
+ /* Not enough scratch Memory available.
+ * Collect context of at least CUDBG_LOWMEM_MAX_CTXT_QIDS
+ * for each queue type.
+ */
+ size = 0;
+ for (i = CTXT_EGRESS; i <= CTXT_CNM; i++)
+ size += sizeof(struct cudbg_ch_cntxt) *
+ CUDBG_LOWMEM_MAX_CTXT_QIDS;
+
+ limit_qid = true;
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+ }
+
+ buff = (struct cudbg_ch_cntxt *)scratch_buff.data;
+
+ /* Collect context data */
+ for (i = CTXT_EGRESS; i <= CTXT_FLM; i++) {
+ qid_count = 0;
+ for (j = 0; j < max_ctx_qid[i]; j++) {
+ read_sge_ctxt(pdbg_init, j, i, buff->data);
+
+ rc = check_valid(buff->data, i);
+ if (rc) {
+ buff->cntxt_type = i;
+ buff->cntxt_id = j;
+ buff++;
+ total_size += sizeof(struct cudbg_ch_cntxt);
+
+ if (i == CTXT_FLM) {
+ read_sge_ctxt(pdbg_init, j, CTXT_CNM,
+ buff->data);
+ buff->cntxt_type = CTXT_CNM;
+ buff->cntxt_id = j;
+ buff++;
+ total_size +=
+ sizeof(struct cudbg_ch_cntxt);
+ }
+ qid_count++;
+ }
+
+ /* If there's not enough space to collect more qids,
+ * then bail and move on to next queue type.
+ */
+ if (limit_qid &&
+ qid_count >= CUDBG_LOWMEM_MAX_CTXT_QIDS)
+ break;
+ }
+ }
+
+ scratch_buff.size = total_size;
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ /* Splitting buffer and writing in terms of CUDBG_CHUNK_SIZE */
+ while (total_size > 0) {
+ bytes = min_t(unsigned long, (unsigned long)total_size,
+ (unsigned long)CUDBG_CHUNK_SIZE);
+ temp_buff.size = bytes;
+ temp_buff.data = (void *)((char *)scratch_buff.data +
+ next_offset);
+
+ rc = compress_buff(&temp_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ total_size -= bytes;
+ next_offset += bytes;
+ }
+
+err1:
+ scratch_buff.size = size;
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_fw_devlog(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct devlog_params *dparams = &padap->params.devlog;
+ struct cudbg_buffer scratch_buff;
+ u32 offset;
+ int rc = 0;
+
+ rc = t4_init_devlog_params(padap, 1);
+
+ if (rc < 0) {
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s(), t4_init_devlog_params failed!, rc: "\
+ "%d\n", __func__, rc);
+ rc = CUDBG_SYSTEM_ERROR;
+ goto err;
+ }
+
+ rc = get_scratch_buff(dbg_buff, dparams->size, &scratch_buff);
+
+ if (rc)
+ goto err;
+
+ /* Collect FW devlog */
+ if (dparams->start != 0) {
+ offset = scratch_buff.offset;
+ rc = t4_memory_rw(padap, padap->params.drv_memwin,
+ dparams->memtype, dparams->start,
+ dparams->size,
+ (__be32 *)((char *)scratch_buff.data +
+ offset), 1);
+
+ if (rc) {
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s(), t4_memory_rw failed!, rc: "\
+ "%d\n", __func__, rc);
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+/* CIM OBQ */
+
+static int
+collect_cim_obq_ulp0(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 0;
+
+ rc = read_cim_obq(pdbg_init, dbg_buff, cudbg_err, qid);
+
+ return rc;
+}
+
+static int
+collect_cim_obq_ulp1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 1;
+
+ rc = read_cim_obq(pdbg_init, dbg_buff, cudbg_err, qid);
+
+ return rc;
+}
+
+static int
+collect_cim_obq_ulp2(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 2;
+
+ rc = read_cim_obq(pdbg_init, dbg_buff, cudbg_err, qid);
+
+ return rc;
+}
+
+static int
+collect_cim_obq_ulp3(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 3;
+
+ rc = read_cim_obq(pdbg_init, dbg_buff, cudbg_err, qid);
+
+ return rc;
+}
+
+static int
+collect_cim_obq_sge(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 4;
+
+ rc = read_cim_obq(pdbg_init, dbg_buff, cudbg_err, qid);
+
+ return rc;
+}
+
+static int
+collect_cim_obq_ncsi(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 5;
+
+ rc = read_cim_obq(pdbg_init, dbg_buff, cudbg_err, qid);
+
+ return rc;
+}
+
+static int
+collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 6;
+
+ rc = read_cim_obq(pdbg_init, dbg_buff, cudbg_err, qid);
+
+ return rc;
+}
+
+static int
+collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 7;
+
+ rc = read_cim_obq(pdbg_init, dbg_buff, cudbg_err, qid);
+
+ return rc;
+}
+
+static int
+read_cim_obq(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err, int qid)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ u32 qsize;
+ int rc;
+ int no_of_read_words;
+
+ /* collect CIM OBQ */
+ qsize = 6 * CIM_OBQ_SIZE * 4 * sizeof(u32);
+ rc = get_scratch_buff(dbg_buff, qsize, &scratch_buff);
+ if (rc)
+ goto err;
+
+ /* t4_read_cim_obq will return no. of read words or error */
+ no_of_read_words = t4_read_cim_obq(padap, qid,
+ (u32 *)((u32 *)scratch_buff.data +
+ scratch_buff.offset), qsize);
+
+ /* no_of_read_words is less than or equal to 0 means error */
+ if (no_of_read_words <= 0) {
+ if (no_of_read_words == 0)
+ rc = CUDBG_SYSTEM_ERROR;
+ else
+ rc = no_of_read_words;
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s: t4_read_cim_obq failed (%d)\n",
+ __func__, rc);
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ scratch_buff.size = no_of_read_words * 4;
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+ if (rc)
+ goto err1;
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+/* CIM IBQ */
+
+static int
+collect_cim_ibq_tp0(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 0;
+
+ rc = read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, qid);
+ return rc;
+}
+
+static int
+collect_cim_ibq_tp1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 1;
+
+ rc = read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, qid);
+ return rc;
+}
+
+static int
+collect_cim_ibq_ulp(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 2;
+
+ rc = read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, qid);
+ return rc;
+}
+
+static int
+collect_cim_ibq_sge0(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 3;
+
+ rc = read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, qid);
+ return rc;
+}
+
+static int
+collect_cim_ibq_sge1(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc = 0, qid = 4;
+
+ rc = read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, qid);
+ return rc;
+}
+
+static int
+collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ int rc, qid = 5;
+
+ rc = read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, qid);
+ return rc;
+}
+
+static int
+read_cim_ibq(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err, int qid)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_buffer scratch_buff;
+ u32 qsize;
+ int rc;
+ int no_of_read_words;
+
+ /* collect CIM IBQ */
+ qsize = CIM_IBQ_SIZE * 4 * sizeof(u32);
+ rc = get_scratch_buff(dbg_buff, qsize, &scratch_buff);
+
+ if (rc)
+ goto err;
+
+ /* t4_read_cim_ibq will return no. of read words or error */
+ no_of_read_words = t4_read_cim_ibq(padap, qid,
+ (u32 *)((u32 *)scratch_buff.data +
+ scratch_buff.offset), qsize);
+ /* no_of_read_words is less than or equal to 0 means error */
+ if (no_of_read_words <= 0) {
+ if (no_of_read_words == 0)
+ rc = CUDBG_SYSTEM_ERROR;
+ else
+ rc = no_of_read_words;
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s: t4_read_cim_ibq failed (%d)\n",
+ __func__, rc);
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+
+err:
+ return rc;
+}
+
+static int
+collect_cim_ma_la(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ u32 rc = 0;
+
+ /* collect CIM MA LA */
+ scratch_buff.size = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ /* no return */
+ t4_cim_read_ma_la(padap,
+ (u32 *) ((char *)scratch_buff.data +
+ scratch_buff.offset),
+ (u32 *) ((char *)scratch_buff.data +
+ scratch_buff.offset + 5 * CIM_MALA_SIZE));
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_cim_la(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+
+ int rc;
+ u32 cfg = 0;
+ int size;
+
+ /* collect CIM LA */
+ if (is_t6(padap->params.chip)) {
+ size = padap->params.cim_la_size / 10 + 1;
+ size *= 11 * sizeof(u32);
+ } else {
+ size = padap->params.cim_la_size / 8;
+ size *= 8 * sizeof(u32);
+ }
+
+ size += sizeof(cfg);
+
+ rc = get_scratch_buff(dbg_buff, size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ rc = t4_cim_read(padap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
+
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s: t4_cim_read failed (%d)\n",
+ __func__, rc);
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ memcpy((char *)scratch_buff.data + scratch_buff.offset, &cfg,
+ sizeof(cfg));
+
+ rc = t4_cim_read_la(padap,
+ (u32 *) ((char *)scratch_buff.data +
+ scratch_buff.offset + sizeof(cfg)), NULL);
+ if (rc < 0) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s: t4_cim_read_la failed (%d)\n",
+ __func__, rc);
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_cim_qcfg(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ u32 offset;
+ int rc = 0;
+
+ struct struct_cim_qcfg *cim_qcfg_data = NULL;
+
+ rc = get_scratch_buff(dbg_buff, sizeof(struct struct_cim_qcfg),
+ &scratch_buff);
+
+ if (rc)
+ goto err;
+
+ offset = scratch_buff.offset;
+
+ cim_qcfg_data =
+ (struct struct_cim_qcfg *)((u8 *)((char *)scratch_buff.data +
+ offset));
+
+ rc = t4_cim_read(padap, A_UP_IBQ_0_RDADDR,
+ ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat);
+
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s: t4_cim_read IBQ_0_RDADDR failed (%d)\n",
+ __func__, rc);
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ rc = t4_cim_read(padap, A_UP_OBQ_0_REALADDR,
+ ARRAY_SIZE(cim_qcfg_data->obq_wr),
+ cim_qcfg_data->obq_wr);
+
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s: t4_cim_read OBQ_0_REALADDR failed (%d)\n",
+ __func__, rc);
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ /* no return val */
+ t4_read_cimq_cfg(padap,
+ cim_qcfg_data->base,
+ cim_qcfg_data->size,
+ cim_qcfg_data->thres);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+read_fw_mem(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff, u8 mem_type,
+ unsigned long tot_len, struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ unsigned long bytes_read = 0;
+ unsigned long bytes_left;
+ unsigned long bytes;
+ int rc;
+
+ bytes_left = tot_len;
+ scratch_buff.size = tot_len;
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err;
+
+ while (bytes_left > 0) {
+ bytes = min_t(unsigned long, bytes_left, (unsigned long)CUDBG_CHUNK_SIZE);
+ rc = get_scratch_buff(dbg_buff, bytes, &scratch_buff);
+
+ if (rc) {
+ rc = CUDBG_STATUS_NO_SCRATCH_MEM;
+ goto err;
+ }
+
+ /* Read from file */
+ /*fread(scratch_buff.data, 1, Bytes, in);*/
+ rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type, bytes_read,
+ bytes, (__be32 *)(scratch_buff.data), 1);
+
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s: t4_memory_rw failed (%d)",
+ __func__, rc);
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ bytes_left -= bytes;
+ bytes_read += bytes;
+ release_scratch_buff(&scratch_buff, dbg_buff);
+ }
+
+err1:
+ if (rc)
+ release_scratch_buff(&scratch_buff, dbg_buff);
+
+err:
+ return rc;
+}
+
+static void
+collect_mem_info(struct cudbg_init *pdbg_init,
+ struct card_mem *mem_info)
+{
+ struct adapter *padap = pdbg_init->adap;
+ u32 value;
+ int t4 = 0;
+
+ if (is_t4(padap->params.chip))
+ t4 = 1;
+
+ if (t4) {
+ value = t4_read_reg(padap, A_MA_EXT_MEMORY_BAR);
+ value = G_EXT_MEM_SIZE(value);
+ mem_info->size_mc0 = (u16)value; /* size in MB */
+
+ value = t4_read_reg(padap, A_MA_TARGET_MEM_ENABLE);
+ if (value & F_EXT_MEM_ENABLE)
+ mem_info->mem_flag |= (1 << MC0_FLAG); /* set mc0 flag
+ bit */
+ } else {
+ value = t4_read_reg(padap, A_MA_EXT_MEMORY0_BAR);
+ value = G_EXT_MEM0_SIZE(value);
+ mem_info->size_mc0 = (u16)value;
+
+ value = t4_read_reg(padap, A_MA_EXT_MEMORY1_BAR);
+ value = G_EXT_MEM1_SIZE(value);
+ mem_info->size_mc1 = (u16)value;
+
+ value = t4_read_reg(padap, A_MA_TARGET_MEM_ENABLE);
+ if (value & F_EXT_MEM0_ENABLE)
+ mem_info->mem_flag |= (1 << MC0_FLAG);
+ if (value & F_EXT_MEM1_ENABLE)
+ mem_info->mem_flag |= (1 << MC1_FLAG);
+ }
+
+ value = t4_read_reg(padap, A_MA_EDRAM0_BAR);
+ value = G_EDRAM0_SIZE(value);
+ mem_info->size_edc0 = (u16)value;
+
+ value = t4_read_reg(padap, A_MA_EDRAM1_BAR);
+ value = G_EDRAM1_SIZE(value);
+ mem_info->size_edc1 = (u16)value;
+
+ value = t4_read_reg(padap, A_MA_TARGET_MEM_ENABLE);
+ if (value & F_EDRAM0_ENABLE)
+ mem_info->mem_flag |= (1 << EDC0_FLAG);
+ if (value & F_EDRAM1_ENABLE)
+ mem_info->mem_flag |= (1 << EDC1_FLAG);
+
+}
+
+static void
+cudbg_t4_fwcache(struct cudbg_init *pdbg_init,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ int rc;
+
+ if (is_fw_attached(pdbg_init)) {
+
+ /* Flush uP dcache before reading edcX/mcX */
+ rc = begin_synchronized_op(padap->port[0], 1, 1);
+ if (rc == 0) {
+ rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH);
+ end_synchronized_op(padap->port[0], 1);
+ }
+
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s: t4_fwcache failed (%d)\n",
+ __func__, rc);
+ cudbg_err->sys_warn = rc;
+ }
+ }
+}
+
+static int
+collect_edc0_meminfo(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct card_mem mem_info = {0};
+ unsigned long edc0_size;
+ int rc;
+
+ cudbg_t4_fwcache(pdbg_init, cudbg_err);
+
+ collect_mem_info(pdbg_init, &mem_info);
+
+ if (mem_info.mem_flag & (1 << EDC0_FLAG)) {
+ edc0_size = (((unsigned long)mem_info.size_edc0) * 1024 * 1024);
+ rc = read_fw_mem(pdbg_init, dbg_buff, MEM_EDC0,
+ edc0_size, cudbg_err);
+ if (rc)
+ goto err;
+
+ } else {
+ rc = CUDBG_STATUS_ENTITY_NOT_FOUND;
+ if (pdbg_init->verbose)
+ pdbg_init->print(pdbg_init->adap->dip, CE_NOTE,
+ "%s(), collect_mem_info failed!, %s\n",
+ __func__, err_msg[-rc]);
+ goto err;
+
+ }
+err:
+ return rc;
+}
+
+static int
+collect_edc1_meminfo(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct card_mem mem_info = {0};
+ unsigned long edc1_size;
+ int rc;
+
+ cudbg_t4_fwcache(pdbg_init, cudbg_err);
+
+ collect_mem_info(pdbg_init, &mem_info);
+
+ if (mem_info.mem_flag & (1 << EDC1_FLAG)) {
+ edc1_size = (((unsigned long)mem_info.size_edc1) * 1024 * 1024);
+ rc = read_fw_mem(pdbg_init, dbg_buff, MEM_EDC1,
+ edc1_size, cudbg_err);
+ if (rc)
+ goto err;
+ } else {
+ rc = CUDBG_STATUS_ENTITY_NOT_FOUND;
+ if (pdbg_init->verbose)
+ pdbg_init->print(pdbg_init->adap->dip, CE_NOTE,
+ "%s(), collect_mem_info failed!, %s\n",
+ __func__, err_msg[-rc]);
+ goto err;
+ }
+
+err:
+
+ return rc;
+}
+
+static int
+collect_mc0_meminfo(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct card_mem mem_info = {0};
+ unsigned long mc0_size;
+ int rc;
+
+ cudbg_t4_fwcache(pdbg_init, cudbg_err);
+
+ collect_mem_info(pdbg_init, &mem_info);
+
+ if (mem_info.mem_flag & (1 << MC0_FLAG)) {
+ mc0_size = (((unsigned long)mem_info.size_mc0) * 1024 * 1024);
+ rc = read_fw_mem(pdbg_init, dbg_buff, MEM_MC0,
+ mc0_size, cudbg_err);
+ if (rc)
+ goto err;
+ } else {
+ rc = CUDBG_STATUS_ENTITY_NOT_FOUND;
+ if (pdbg_init->verbose)
+ pdbg_init->print(pdbg_init->adap->dip, CE_NOTE,
+ "%s(), collect_mem_info failed!, %s\n",
+ __func__, err_msg[-rc]);
+ goto err;
+ }
+
+err:
+ return rc;
+}
+
+static int
+collect_mc1_meminfo(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct card_mem mem_info = {0};
+ unsigned long mc1_size;
+ int rc;
+
+ cudbg_t4_fwcache(pdbg_init, cudbg_err);
+
+ collect_mem_info(pdbg_init, &mem_info);
+
+ if (mem_info.mem_flag & (1 << MC1_FLAG)) {
+ mc1_size = (((unsigned long)mem_info.size_mc1) * 1024 * 1024);
+ rc = read_fw_mem(pdbg_init, dbg_buff, MEM_MC1,
+ mc1_size, cudbg_err);
+ if (rc)
+ goto err;
+ } else {
+ rc = CUDBG_STATUS_ENTITY_NOT_FOUND;
+
+ if (pdbg_init->verbose)
+ pdbg_init->print(pdbg_init->adap->dip, CE_NOTE,
+ "%s(), collect_mem_info failed!, %s\n",
+ __func__, err_msg[-rc]);
+ goto err;
+ }
+err:
+ return rc;
+}
+
+static int
+collect_reg_dump(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct cudbg_buffer tmp_scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ unsigned long bytes_read = 0;
+ unsigned long bytes_left;
+ u32 buf_size = 0, bytes = 0;
+ int rc = 0;
+
+ if (is_t4(padap->params.chip))
+ buf_size = T4_REGMAP_SIZE ;/*+ sizeof(unsigned int);*/
+ else if (is_t5(padap->params.chip) || is_t6(padap->params.chip))
+ buf_size = T5_REGMAP_SIZE;
+
+ scratch_buff.size = buf_size;
+
+ tmp_scratch_buff = scratch_buff;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ /* no return */
+ t4_get_regs(padap, (void *)scratch_buff.data, scratch_buff.size);
+ bytes_left = scratch_buff.size;
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ while (bytes_left > 0) {
+ tmp_scratch_buff.data =
+ ((char *)scratch_buff.data) + bytes_read;
+ bytes = min_t(unsigned long, bytes_left, (unsigned long)CUDBG_CHUNK_SIZE);
+ tmp_scratch_buff.size = bytes;
+ compress_buff(&tmp_scratch_buff, dbg_buff);
+ bytes_left -= bytes;
+ bytes_read += bytes;
+ }
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_cctrl(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ u32 size;
+ int rc;
+
+ size = sizeof(u16) * NMTUS * NCCTRL_WIN;
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ t4_read_cong_tbl(padap, (void *)scratch_buff.data);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+check_busy_bit(struct adapter *padap)
+{
+ u32 val;
+ u32 busy = 1;
+ int i = 0;
+ int retry = 10;
+ int status = 0;
+
+ while (busy & (1 < retry)) {
+ val = t4_read_reg(padap, A_CIM_HOST_ACC_CTRL);
+ busy = (0 != (val & CUDBG_CIM_BUSY_BIT));
+ i++;
+ }
+
+ if (busy)
+ status = -1;
+
+ return status;
+}
+
+static int
+cim_ha_rreg(struct adapter *padap, u32 addr, u32 *val)
+{
+ int rc = 0;
+
+ /* write register address into the A_CIM_HOST_ACC_CTRL */
+ t4_write_reg(padap, A_CIM_HOST_ACC_CTRL, addr);
+
+ /* Poll HOSTBUSY */
+ rc = check_busy_bit(padap);
+ if (rc)
+ goto err;
+
+ /* Read value from A_CIM_HOST_ACC_DATA */
+ *val = t4_read_reg(padap, A_CIM_HOST_ACC_DATA);
+
+err:
+ return rc;
+}
+
+static int
+dump_up_cim(struct adapter *padap, struct cudbg_init *pdbg_init,
+ struct ireg_field *up_cim_reg, u32 *buff)
+{
+ u32 i;
+ int rc = 0;
+
+ for (i = 0; i < up_cim_reg->ireg_offset_range; i++) {
+ rc = cim_ha_rreg(padap,
+ up_cim_reg->ireg_local_offset + (i * 4),
+ buff);
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "BUSY timeout reading"
+ "CIM_HOST_ACC_CTRL\n");
+ goto err;
+ }
+
+ buff++;
+ }
+
+err:
+ return rc;
+}
+
+static int
+collect_up_cim_indirect(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct ireg_buf *up_cim;
+ u32 size;
+ int i, rc, n;
+
+ n = sizeof(t5_up_cim_reg_array) / (4 * sizeof(u32));
+ size = sizeof(struct ireg_buf) * n;
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ up_cim = (struct ireg_buf *)scratch_buff.data;
+
+ for (i = 0; i < n; i++) {
+ struct ireg_field *up_cim_reg = &up_cim->tp_pio;
+ u32 *buff = up_cim->outbuf;
+
+ if (is_t5(padap->params.chip)) {
+ up_cim_reg->ireg_addr = t5_up_cim_reg_array[i][0];
+ up_cim_reg->ireg_data = t5_up_cim_reg_array[i][1];
+ up_cim_reg->ireg_local_offset =
+ t5_up_cim_reg_array[i][2];
+ up_cim_reg->ireg_offset_range =
+ t5_up_cim_reg_array[i][3];
+ } else if (is_t6(padap->params.chip)) {
+ up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0];
+ up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1];
+ up_cim_reg->ireg_local_offset =
+ t6_up_cim_reg_array[i][2];
+ up_cim_reg->ireg_offset_range =
+ t6_up_cim_reg_array[i][3];
+ }
+
+ rc = dump_up_cim(padap, pdbg_init, up_cim_reg, buff);
+
+ up_cim++;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_mbox_log(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+#ifdef notyet
+ struct cudbg_buffer scratch_buff;
+ struct cudbg_mbox_log *mboxlog = NULL;
+ struct mbox_cmd_log *log = NULL;
+ struct mbox_cmd *entry;
+ u64 flit;
+ u32 size;
+ unsigned int entry_idx;
+ int i, k, rc;
+ u16 mbox_cmds;
+
+ if (pdbg_init->dbg_params[CUDBG_MBOX_LOG_PARAM].u.mboxlog_param.log) {
+ log = pdbg_init->dbg_params[CUDBG_MBOX_LOG_PARAM].u.
+ mboxlog_param.log;
+ mbox_cmds = pdbg_init->dbg_params[CUDBG_MBOX_LOG_PARAM].u.
+ mboxlog_param.mbox_cmds;
+ } else {
+ if (pdbg_init->verbose)
+ pdbg_init->print(adap->dip, CE_NOTE,
+ "Mbox log is not requested\n");
+ return CUDBG_STATUS_ENTITY_NOT_REQUESTED;
+ }
+
+ size = sizeof(struct cudbg_mbox_log) * mbox_cmds;
+ scratch_buff.size = size;
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ mboxlog = (struct cudbg_mbox_log *)scratch_buff.data;
+
+ for (k = 0; k < mbox_cmds; k++) {
+ entry_idx = log->cursor + k;
+ if (entry_idx >= log->size)
+ entry_idx -= log->size;
+ entry = mbox_cmd_log_entry(log, entry_idx);
+
+ /* skip over unused entries */
+ if (entry->timestamp == 0)
+ continue;
+
+ memcpy(&mboxlog->entry, entry, sizeof(struct mbox_cmd));
+
+ for (i = 0; i < MBOX_LEN / 8; i++) {
+ flit = entry->cmd[i];
+ mboxlog->hi[i] = (u32)(flit >> 32);
+ mboxlog->lo[i] = (u32)flit;
+ }
+
+ mboxlog++;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+#endif
+ return (-1);
+}
+
+static int
+collect_pbt_tables(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_pbt_tables *pbt = NULL;
+ u32 size;
+ u32 addr;
+ int i, rc;
+
+ size = sizeof(struct cudbg_pbt_tables);
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ pbt = (struct cudbg_pbt_tables *)scratch_buff.data;
+
+ /* PBT dynamic entries */
+ addr = CUDBG_CHAC_PBT_ADDR;
+ for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) {
+ rc = cim_ha_rreg(padap, addr + (i * 4), &pbt->pbt_dynamic[i]);
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "BUSY timeout reading"
+ "CIM_HOST_ACC_CTRL\n");
+ goto err1;
+ }
+ }
+
+ /* PBT static entries */
+
+ /* static entries start when bit 6 is set */
+ addr = CUDBG_CHAC_PBT_ADDR + (1 << 6);
+ for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) {
+ rc = cim_ha_rreg(padap, addr + (i * 4), &pbt->pbt_static[i]);
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "BUSY timeout reading"
+ "CIM_HOST_ACC_CTRL\n");
+ goto err1;
+ }
+ }
+
+ /* LRF entries */
+ addr = CUDBG_CHAC_PBT_LRF;
+ for (i = 0; i < CUDBG_LRF_ENTRIES; i++) {
+ rc = cim_ha_rreg(padap, addr + (i * 4), &pbt->lrf_table[i]);
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "BUSY timeout reading"
+ "CIM_HOST_ACC_CTRL\n");
+ goto err1;
+ }
+ }
+
+ /* PBT data entries */
+ addr = CUDBG_CHAC_PBT_DATA;
+ for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) {
+ rc = cim_ha_rreg(padap, addr + (i * 4), &pbt->pbt_data[i]);
+ if (rc) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "BUSY timeout reading"
+ "CIM_HOST_ACC_CTRL\n");
+ goto err1;
+ }
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_pm_indirect(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct ireg_buf *ch_pm;
+ u32 size;
+ int i, rc, n;
+
+ n = sizeof(t5_pm_rx_array) / (4 * sizeof(u32));
+ size = sizeof(struct ireg_buf) * n * 2;
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ ch_pm = (struct ireg_buf *)scratch_buff.data;
+
+ /*PM_RX*/
+ for (i = 0; i < n; i++) {
+ struct ireg_field *pm_pio = &ch_pm->tp_pio;
+ u32 *buff = ch_pm->outbuf;
+
+ pm_pio->ireg_addr = t5_pm_rx_array[i][0];
+ pm_pio->ireg_data = t5_pm_rx_array[i][1];
+ pm_pio->ireg_local_offset = t5_pm_rx_array[i][2];
+ pm_pio->ireg_offset_range = t5_pm_rx_array[i][3];
+
+ t4_read_indirect(padap,
+ pm_pio->ireg_addr,
+ pm_pio->ireg_data,
+ buff,
+ pm_pio->ireg_offset_range,
+ pm_pio->ireg_local_offset);
+
+ ch_pm++;
+ }
+
+ /*PM_Tx*/
+ n = sizeof(t5_pm_tx_array) / (4 * sizeof(u32));
+ for (i = 0; i < n; i++) {
+ struct ireg_field *pm_pio = &ch_pm->tp_pio;
+ u32 *buff = ch_pm->outbuf;
+
+ pm_pio->ireg_addr = t5_pm_tx_array[i][0];
+ pm_pio->ireg_data = t5_pm_tx_array[i][1];
+ pm_pio->ireg_local_offset = t5_pm_tx_array[i][2];
+ pm_pio->ireg_offset_range = t5_pm_tx_array[i][3];
+
+ t4_read_indirect(padap,
+ pm_pio->ireg_addr,
+ pm_pio->ireg_data,
+ buff,
+ pm_pio->ireg_offset_range,
+ pm_pio->ireg_local_offset);
+
+ ch_pm++;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+
+}
+
+static int
+collect_tid(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct tid_info_region *tid;
+ struct tid_info_region_rev1 *tid1;
+ u32 para[7], val[7];
+ u32 mbox, pf;
+ int rc;
+
+ scratch_buff.size = sizeof(struct tid_info_region_rev1);
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+#define FW_PARAM_DEV_A(param) \
+ (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
+ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
+#define FW_PARAM_PFVF_A(param) \
+ (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
+ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)| \
+ V_FW_PARAMS_PARAM_Y(0) | \
+ V_FW_PARAMS_PARAM_Z(0))
+#define MAX_ATIDS_A 8192U
+
+ tid1 = (struct tid_info_region_rev1 *)scratch_buff.data;
+ tid = &(tid1->tid);
+ tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
+ tid1->ver_hdr.revision = CUDBG_TID_INFO_REV;
+ tid1->ver_hdr.size = sizeof(struct tid_info_region_rev1) -
+ sizeof(struct cudbg_ver_hdr);
+
+ if (is_t5(padap->params.chip)) {
+ tid->hash_base = t4_read_reg(padap, A_LE_DB_TID_HASHBASE);
+ tid1->tid_start = 0;
+ } else if (is_t6(padap->params.chip)) {
+ tid->hash_base = t4_read_reg(padap, A_T6_LE_DB_HASH_TID_BASE);
+ tid1->tid_start = t4_read_reg(padap, A_LE_DB_ACTIVE_TABLE_START_INDEX);
+ }
+
+ tid->le_db_conf = t4_read_reg(padap, A_LE_DB_CONFIG);
+
+ para[0] = FW_PARAM_PFVF_A(FILTER_START);
+ para[1] = FW_PARAM_PFVF_A(FILTER_END);
+ para[2] = FW_PARAM_PFVF_A(ACTIVE_FILTER_START);
+ para[3] = FW_PARAM_PFVF_A(ACTIVE_FILTER_END);
+ para[4] = FW_PARAM_DEV_A(NTID);
+ para[5] = FW_PARAM_PFVF_A(SERVER_START);
+ para[6] = FW_PARAM_PFVF_A(SERVER_END);
+
+ rc = begin_synchronized_op(padap->port[0], 1, 1);
+ if (rc)
+ goto err;
+ mbox = padap->mbox;
+ pf = padap->pf;
+ rc = t4_query_params(padap, mbox, pf, 0, 7, para, val);
+ if (rc < 0) {
+ if (rc == -FW_EPERM) {
+ /* It looks like we don't have permission to use
+ * padap->mbox.
+ *
+ * Try mbox 4. If it works, we'll continue to
+ * collect the rest of tid info from mbox 4.
+ * Else, quit trying to collect tid info.
+ */
+ mbox = 4;
+ pf = 4;
+ rc = t4_query_params(padap, mbox, pf, 0, 7, para, val);
+ if (rc < 0) {
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+ } else {
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+ }
+
+ tid->ftid_base = val[0];
+ tid->nftids = val[1] - val[0] + 1;
+ /*active filter region*/
+ if (val[2] != val[3]) {
+#ifdef notyet
+ tid->flags |= FW_OFLD_CONN;
+#endif
+ tid->aftid_base = val[2];
+ tid->aftid_end = val[3];
+ }
+ tid->ntids = val[4];
+ tid->natids = min_t(u32, tid->ntids / 2, MAX_ATIDS_A);
+ tid->stid_base = val[5];
+ tid->nstids = val[6] - val[5] + 1;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
+ para[0] = FW_PARAM_PFVF_A(HPFILTER_START);
+ para[1] = FW_PARAM_PFVF_A(HPFILTER_END);
+ rc = t4_query_params(padap, mbox, pf, 0, 2, para, val);
+ if (rc < 0) {
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ tid->hpftid_base = val[0];
+ tid->nhpftids = val[1] - val[0] + 1;
+ }
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) {
+ tid->sb = t4_read_reg(padap, A_LE_DB_SERVER_INDEX) / 4;
+ tid->hash_base /= 4;
+ } else
+ tid->sb = t4_read_reg(padap, A_LE_DB_SRVR_START_INDEX);
+
+ /*UO context range*/
+ para[0] = FW_PARAM_PFVF_A(ETHOFLD_START);
+ para[1] = FW_PARAM_PFVF_A(ETHOFLD_END);
+
+ rc = t4_query_params(padap, mbox, pf, 0, 2, para, val);
+ if (rc < 0) {
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ if (val[0] != val[1]) {
+ tid->uotid_base = val[0];
+ tid->nuotids = val[1] - val[0] + 1;
+ }
+ tid->IP_users = t4_read_reg(padap, A_LE_DB_ACT_CNT_IPV4);
+ tid->IPv6_users = t4_read_reg(padap, A_LE_DB_ACT_CNT_IPV6);
+
+#undef FW_PARAM_PFVF_A
+#undef FW_PARAM_DEV_A
+#undef MAX_ATIDS_A
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ end_synchronized_op(padap->port[0], 1);
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_tx_rate(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct tx_rate *tx_rate;
+ u32 size;
+ int rc;
+
+ size = sizeof(struct tx_rate);
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ tx_rate = (struct tx_rate *)scratch_buff.data;
+ t4_get_chan_txrate(padap, tx_rate->nrate, tx_rate->orate);
+ tx_rate->nchan = padap->params.arch.nchan;
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static inline void
+cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
+{
+ *mask = x | y;
+ y = (__force u64)cpu_to_be64(y);
+ memcpy(addr, (char *)&y + 2, ETH_ALEN);
+}
+
+static void
+mps_rpl_backdoor(struct adapter *padap, struct fw_ldst_mps_rplc *mps_rplc)
+{
+ if (is_t5(padap->params.chip)) {
+ mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
+ A_MPS_VF_RPLCT_MAP3));
+ mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
+ A_MPS_VF_RPLCT_MAP2));
+ mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
+ A_MPS_VF_RPLCT_MAP1));
+ mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
+ A_MPS_VF_RPLCT_MAP0));
+ } else {
+ mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
+ A_MPS_VF_RPLCT_MAP7));
+ mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
+ A_MPS_VF_RPLCT_MAP6));
+ mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
+ A_MPS_VF_RPLCT_MAP5));
+ mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
+ A_MPS_VF_RPLCT_MAP4));
+ }
+ mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, A_MPS_VF_RPLCT_MAP3));
+ mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, A_MPS_VF_RPLCT_MAP2));
+ mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, A_MPS_VF_RPLCT_MAP1));
+ mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, A_MPS_VF_RPLCT_MAP0));
+}
+
+static int
+collect_mps_tcam(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_mps_tcam *tcam = NULL;
+ u32 size = 0, i, n, total_size = 0;
+ u32 ctl, data2;
+ u64 tcamy, tcamx, val;
+ int rc;
+
+
+ n = padap->params.arch.mps_tcam_size;
+ size = sizeof(struct cudbg_mps_tcam) * n;
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+ memset(scratch_buff.data, 0, size);
+
+ tcam = (struct cudbg_mps_tcam *)scratch_buff.data;
+ for (i = 0; i < n; i++) {
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
+ /* CtlReqID - 1: use Host Driver Requester ID
+ * CtlCmdType - 0: Read, 1: Write
+ * CtlTcamSel - 0: TCAM0, 1: TCAM1
+ * CtlXYBitSel- 0: Y bit, 1: X bit
+ */
+
+ /* Read tcamy */
+ ctl = (V_CTLREQID(1) |
+ V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0));
+ if (i < 256)
+ ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
+ else
+ ctl |= V_CTLTCAMINDEX(i - 256) |
+ V_CTLTCAMSEL(1);
+
+ t4_write_reg(padap, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
+ val = t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
+ tcamy = G_DMACH(val) << 32;
+ tcamy |= t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
+ data2 = t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
+ tcam->lookup_type = G_DATALKPTYPE(data2);
+
+ /* 0 - Outer header, 1 - Inner header
+ * [71:48] bit locations are overloaded for
+ * outer vs. inner lookup types.
+ */
+
+ if (tcam->lookup_type &&
+ (tcam->lookup_type != M_DATALKPTYPE)) {
+ /* Inner header VNI */
+ tcam->vniy = ((data2 & F_DATAVIDH2) << 23) |
+ (G_DATAVIDH1(data2) << 16) |
+ G_VIDL(val);
+ tcam->dip_hit = data2 & F_DATADIPHIT;
+ } else {
+ tcam->vlan_vld = data2 & F_DATAVIDH2;
+ tcam->ivlan = G_VIDL(val);
+ }
+
+ tcam->port_num = G_DATAPORTNUM(data2);
+
+ /* Read tcamx. Change the control param */
+ ctl |= V_CTLXYBITSEL(1);
+ t4_write_reg(padap, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
+ val = t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
+ tcamx = G_DMACH(val) << 32;
+ tcamx |= t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
+ data2 = t4_read_reg(padap, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
+ if (tcam->lookup_type &&
+ (tcam->lookup_type != M_DATALKPTYPE)) {
+ /* Inner header VNI mask */
+ tcam->vnix = ((data2 & F_DATAVIDH2) << 23) |
+ (G_DATAVIDH1(data2) << 16) |
+ G_VIDL(val);
+ }
+ } else {
+ tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(i));
+ tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(i));
+ }
+
+ if (tcamx & tcamy)
+ continue;
+
+ tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(i));
+ tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(i));
+
+ if (is_t5(padap->params.chip))
+ tcam->repli = (tcam->cls_lo & F_REPLICATE);
+ else if (is_t6(padap->params.chip))
+ tcam->repli = (tcam->cls_lo & F_T6_REPLICATE);
+
+ if (tcam->repli) {
+ struct fw_ldst_cmd ldst_cmd;
+ struct fw_ldst_mps_rplc mps_rplc;
+
+ memset(&ldst_cmd, 0, sizeof(ldst_cmd));
+ ldst_cmd.op_to_addrspace =
+ htonl(V_FW_CMD_OP(FW_LDST_CMD) |
+ F_FW_CMD_REQUEST |
+ F_FW_CMD_READ |
+ V_FW_LDST_CMD_ADDRSPACE(
+ FW_LDST_ADDRSPC_MPS));
+
+ ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
+
+ ldst_cmd.u.mps.rplc.fid_idx =
+ htons(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
+ V_FW_LDST_CMD_IDX(i));
+
+ rc = begin_synchronized_op(padap->port[0], 1, 1);
+ if (rc == 0) {
+ rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd,
+ sizeof(ldst_cmd), &ldst_cmd);
+ end_synchronized_op(padap->port[0], 1);
+ }
+
+ if (rc)
+ mps_rpl_backdoor(padap, &mps_rplc);
+ else
+ mps_rplc = ldst_cmd.u.mps.rplc;
+
+ tcam->rplc[0] = ntohl(mps_rplc.rplc31_0);
+ tcam->rplc[1] = ntohl(mps_rplc.rplc63_32);
+ tcam->rplc[2] = ntohl(mps_rplc.rplc95_64);
+ tcam->rplc[3] = ntohl(mps_rplc.rplc127_96);
+ if (padap->params.arch.mps_rplc_size >
+ CUDBG_MAX_RPLC_SIZE) {
+ tcam->rplc[4] = ntohl(mps_rplc.rplc159_128);
+ tcam->rplc[5] = ntohl(mps_rplc.rplc191_160);
+ tcam->rplc[6] = ntohl(mps_rplc.rplc223_192);
+ tcam->rplc[7] = ntohl(mps_rplc.rplc255_224);
+ }
+ }
+ cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask);
+
+ tcam->idx = i;
+ tcam->rplc_size = padap->params.arch.mps_rplc_size;
+
+ total_size += sizeof(struct cudbg_mps_tcam);
+
+ tcam++;
+ }
+
+ if (total_size == 0) {
+ rc = CUDBG_SYSTEM_ERROR;
+ goto err1;
+ }
+
+ scratch_buff.size = total_size;
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ scratch_buff.size = size;
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_pcie_config(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ u32 size, *value, j;
+ int i, rc, n;
+
+ size = sizeof(u32) * NUM_PCIE_CONFIG_REGS;
+ n = sizeof(t5_pcie_config_array) / (2 * sizeof(u32));
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ value = (u32 *)scratch_buff.data;
+ for (i = 0; i < n; i++) {
+ for (j = t5_pcie_config_array[i][0];
+ j <= t5_pcie_config_array[i][1]; j += 4) {
+ t4_hw_pci_read_cfg4(padap, j, value++);
+ }
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid,
+ struct cudbg_tid_data *tid_data)
+{
+ int i, cmd_retry = 8;
+ struct adapter *padap = pdbg_init->adap;
+ u32 val;
+
+ /* Fill REQ_DATA regs with 0's */
+ for (i = 0; i < CUDBG_NUM_REQ_REGS; i++)
+ t4_write_reg(padap, A_LE_DB_DBGI_REQ_DATA + (i << 2), 0);
+
+ /* Write DBIG command */
+ val = (0x4 << S_DBGICMD) | tid;
+ t4_write_reg(padap, A_LE_DB_DBGI_REQ_TCAM_CMD, val);
+ tid_data->dbig_cmd = val;
+
+ val = 0;
+ val |= 1 << S_DBGICMDSTRT;
+ val |= 1; /* LE mode */
+ t4_write_reg(padap, A_LE_DB_DBGI_CONFIG, val);
+ tid_data->dbig_conf = val;
+
+ /* Poll the DBGICMDBUSY bit */
+ val = 1;
+ while (val) {
+ val = t4_read_reg(padap, A_LE_DB_DBGI_CONFIG);
+ val = (val >> S_DBGICMDBUSY) & 1;
+ cmd_retry--;
+ if (!cmd_retry) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s(): Timeout waiting for non-busy\n",
+ __func__);
+ return CUDBG_SYSTEM_ERROR;
+ }
+ }
+
+ /* Check RESP status */
+ val = 0;
+ val = t4_read_reg(padap, A_LE_DB_DBGI_RSP_STATUS);
+ tid_data->dbig_rsp_stat = val;
+ if (!(val & 1)) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "%s(): DBGI command failed\n", __func__);
+ return CUDBG_SYSTEM_ERROR;
+ }
+
+ /* Read RESP data */
+ for (i = 0; i < CUDBG_NUM_REQ_REGS; i++)
+ tid_data->data[i] = t4_read_reg(padap,
+ A_LE_DB_DBGI_RSP_DATA +
+ (i << 2));
+
+ tid_data->tid = tid;
+
+ return 0;
+}
+
+static int
+collect_le_tcam(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct cudbg_tcam tcam_region = {0};
+ struct cudbg_tid_data *tid_data = NULL;
+ u32 value, bytes = 0, bytes_left = 0;
+ u32 i;
+ int rc, size;
+
+ /* Get the LE regions */
+ value = t4_read_reg(padap, A_LE_DB_TID_HASHBASE); /* Get hash base
+ index */
+ tcam_region.tid_hash_base = value;
+
+ /* Get routing table index */
+ value = t4_read_reg(padap, A_LE_DB_ROUTING_TABLE_INDEX);
+ tcam_region.routing_start = value;
+
+ /*Get clip table index */
+ value = t4_read_reg(padap, A_LE_DB_CLIP_TABLE_INDEX);
+ tcam_region.clip_start = value;
+
+ /* Get filter table index */
+ value = t4_read_reg(padap, A_LE_DB_FILTER_TABLE_INDEX);
+ tcam_region.filter_start = value;
+
+ /* Get server table index */
+ value = t4_read_reg(padap, A_LE_DB_SERVER_INDEX);
+ tcam_region.server_start = value;
+
+ /* Check whether hash is enabled and calculate the max tids */
+ value = t4_read_reg(padap, A_LE_DB_CONFIG);
+ if ((value >> S_HASHEN) & 1) {
+ value = t4_read_reg(padap, A_LE_DB_HASH_CONFIG);
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
+ tcam_region.max_tid = (value & 0xFFFFF) +
+ tcam_region.tid_hash_base;
+ else { /* for T5 */
+ value = G_HASHTIDSIZE(value);
+ value = 1 << value;
+ tcam_region.max_tid = value +
+ tcam_region.tid_hash_base;
+ }
+ } else /* hash not enabled */
+ tcam_region.max_tid = CUDBG_MAX_TCAM_TID;
+
+ size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid;
+ size += sizeof(struct cudbg_tcam);
+ scratch_buff.size = size;
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err;
+
+ rc = get_scratch_buff(dbg_buff, CUDBG_CHUNK_SIZE, &scratch_buff);
+ if (rc)
+ goto err;
+
+ memcpy(scratch_buff.data, &tcam_region, sizeof(struct cudbg_tcam));
+
+ tid_data = (struct cudbg_tid_data *)(((struct cudbg_tcam *)
+ scratch_buff.data) + 1);
+ bytes_left = CUDBG_CHUNK_SIZE - sizeof(struct cudbg_tcam);
+ bytes = sizeof(struct cudbg_tcam);
+
+ /* read all tid */
+ for (i = 0; i < tcam_region.max_tid; i++) {
+ if (bytes_left < sizeof(struct cudbg_tid_data)) {
+ scratch_buff.size = bytes;
+ rc = compress_buff(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+ scratch_buff.size = CUDBG_CHUNK_SIZE;
+ release_scratch_buff(&scratch_buff, dbg_buff);
+
+ /* new alloc */
+ rc = get_scratch_buff(dbg_buff, CUDBG_CHUNK_SIZE,
+ &scratch_buff);
+ if (rc)
+ goto err;
+
+ tid_data = (struct cudbg_tid_data *)(scratch_buff.data);
+ bytes_left = CUDBG_CHUNK_SIZE;
+ bytes = 0;
+ }
+
+ rc = cudbg_read_tid(pdbg_init, i, tid_data);
+
+ if (rc) {
+ cudbg_err->sys_err = rc;
+ goto err1;
+ }
+
+ tid_data++;
+ bytes_left -= sizeof(struct cudbg_tid_data);
+ bytes += sizeof(struct cudbg_tid_data);
+ }
+
+ if (bytes) {
+ scratch_buff.size = bytes;
+ rc = compress_buff(&scratch_buff, dbg_buff);
+ }
+
+err1:
+ scratch_buff.size = CUDBG_CHUNK_SIZE;
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_ma_indirect(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct ireg_buf *ma_indr = NULL;
+ u32 size, j;
+ int i, rc, n;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "MA indirect available only in T6\n");
+ rc = CUDBG_STATUS_ENTITY_NOT_FOUND;
+ goto err;
+ }
+
+ n = sizeof(t6_ma_ireg_array) / (4 * sizeof(u32));
+ size = sizeof(struct ireg_buf) * n * 2;
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ ma_indr = (struct ireg_buf *)scratch_buff.data;
+
+ for (i = 0; i < n; i++) {
+ struct ireg_field *ma_fli = &ma_indr->tp_pio;
+ u32 *buff = ma_indr->outbuf;
+
+ ma_fli->ireg_addr = t6_ma_ireg_array[i][0];
+ ma_fli->ireg_data = t6_ma_ireg_array[i][1];
+ ma_fli->ireg_local_offset = t6_ma_ireg_array[i][2];
+ ma_fli->ireg_offset_range = t6_ma_ireg_array[i][3];
+
+ t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data,
+ buff, ma_fli->ireg_offset_range,
+ ma_fli->ireg_local_offset);
+
+ ma_indr++;
+
+ }
+
+ n = sizeof(t6_ma_ireg_array2) / (4 * sizeof(u32));
+
+ for (i = 0; i < n; i++) {
+ struct ireg_field *ma_fli = &ma_indr->tp_pio;
+ u32 *buff = ma_indr->outbuf;
+
+ ma_fli->ireg_addr = t6_ma_ireg_array2[i][0];
+ ma_fli->ireg_data = t6_ma_ireg_array2[i][1];
+ ma_fli->ireg_local_offset = t6_ma_ireg_array2[i][2];
+
+ for (j = 0; j < t6_ma_ireg_array2[i][3]; j++) {
+ t4_read_indirect(padap, ma_fli->ireg_addr,
+ ma_fli->ireg_data, buff, 1,
+ ma_fli->ireg_local_offset);
+ buff++;
+ ma_fli->ireg_local_offset += 0x20;
+ }
+ ma_indr++;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_hma_indirect(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct ireg_buf *hma_indr = NULL;
+ u32 size;
+ int i, rc, n;
+
+ if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6) {
+ if (pdbg_init->verbose)
+ pdbg_init->print(padap->dip, CE_NOTE,
+ "HMA indirect available only in T6\n");
+ rc = CUDBG_STATUS_ENTITY_NOT_FOUND;
+ goto err;
+ }
+
+ n = sizeof(t6_hma_ireg_array) / (4 * sizeof(u32));
+ size = sizeof(struct ireg_buf) * n;
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ hma_indr = (struct ireg_buf *)scratch_buff.data;
+
+ for (i = 0; i < n; i++) {
+ struct ireg_field *hma_fli = &hma_indr->tp_pio;
+ u32 *buff = hma_indr->outbuf;
+
+ hma_fli->ireg_addr = t6_hma_ireg_array[i][0];
+ hma_fli->ireg_data = t6_hma_ireg_array[i][1];
+ hma_fli->ireg_local_offset = t6_hma_ireg_array[i][2];
+ hma_fli->ireg_offset_range = t6_hma_ireg_array[i][3];
+
+ t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data,
+ buff, hma_fli->ireg_offset_range,
+ hma_fli->ireg_local_offset);
+
+ hma_indr++;
+
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_pcie_indirect(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct ireg_buf *ch_pcie;
+ u32 size;
+ int i, rc, n;
+
+ n = sizeof(t5_pcie_pdbg_array) / (4 * sizeof(u32));
+ size = sizeof(struct ireg_buf) * n * 2;
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ ch_pcie = (struct ireg_buf *)scratch_buff.data;
+
+ /*PCIE_PDBG*/
+ for (i = 0; i < n; i++) {
+ struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
+ u32 *buff = ch_pcie->outbuf;
+
+ pcie_pio->ireg_addr = t5_pcie_pdbg_array[i][0];
+ pcie_pio->ireg_data = t5_pcie_pdbg_array[i][1];
+ pcie_pio->ireg_local_offset = t5_pcie_pdbg_array[i][2];
+ pcie_pio->ireg_offset_range = t5_pcie_pdbg_array[i][3];
+
+ t4_read_indirect(padap,
+ pcie_pio->ireg_addr,
+ pcie_pio->ireg_data,
+ buff,
+ pcie_pio->ireg_offset_range,
+ pcie_pio->ireg_local_offset);
+
+ ch_pcie++;
+ }
+
+ /*PCIE_CDBG*/
+ n = sizeof(t5_pcie_cdbg_array) / (4 * sizeof(u32));
+ for (i = 0; i < n; i++) {
+ struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
+ u32 *buff = ch_pcie->outbuf;
+
+ pcie_pio->ireg_addr = t5_pcie_cdbg_array[i][0];
+ pcie_pio->ireg_data = t5_pcie_cdbg_array[i][1];
+ pcie_pio->ireg_local_offset = t5_pcie_cdbg_array[i][2];
+ pcie_pio->ireg_offset_range = t5_pcie_cdbg_array[i][3];
+
+ t4_read_indirect(padap,
+ pcie_pio->ireg_addr,
+ pcie_pio->ireg_data,
+ buff,
+ pcie_pio->ireg_offset_range,
+ pcie_pio->ireg_local_offset);
+
+ ch_pcie++;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+
+}
+
+static int
+collect_tp_indirect(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct ireg_buf *ch_tp_pio;
+ u32 size;
+ int i, rc, n = 0;
+
+ if (is_t5(padap->params.chip))
+ n = sizeof(t5_tp_pio_array) / (4 * sizeof(u32));
+ else if (is_t6(padap->params.chip))
+ n = sizeof(t6_tp_pio_array) / (4 * sizeof(u32));
+
+ size = sizeof(struct ireg_buf) * n * 3;
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ ch_tp_pio = (struct ireg_buf *)scratch_buff.data;
+
+ /* TP_PIO*/
+ for (i = 0; i < n; i++) {
+ struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
+ u32 *buff = ch_tp_pio->outbuf;
+
+ if (is_t5(padap->params.chip)) {
+ tp_pio->ireg_addr = t5_tp_pio_array[i][0];
+ tp_pio->ireg_data = t5_tp_pio_array[i][1];
+ tp_pio->ireg_local_offset = t5_tp_pio_array[i][2];
+ tp_pio->ireg_offset_range = t5_tp_pio_array[i][3];
+ } else if (is_t6(padap->params.chip)) {
+ tp_pio->ireg_addr = t6_tp_pio_array[i][0];
+ tp_pio->ireg_data = t6_tp_pio_array[i][1];
+ tp_pio->ireg_local_offset = t6_tp_pio_array[i][2];
+ tp_pio->ireg_offset_range = t6_tp_pio_array[i][3];
+ }
+
+ t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range,
+ tp_pio->ireg_local_offset, true);
+
+ ch_tp_pio++;
+ }
+
+ /* TP_TM_PIO*/
+ if (is_t5(padap->params.chip))
+ n = sizeof(t5_tp_tm_pio_array) / (4 * sizeof(u32));
+ else if (is_t6(padap->params.chip))
+ n = sizeof(t6_tp_tm_pio_array) / (4 * sizeof(u32));
+
+ for (i = 0; i < n; i++) {
+ struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
+ u32 *buff = ch_tp_pio->outbuf;
+
+ if (is_t5(padap->params.chip)) {
+ tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0];
+ tp_pio->ireg_data = t5_tp_tm_pio_array[i][1];
+ tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2];
+ tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3];
+ } else if (is_t6(padap->params.chip)) {
+ tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0];
+ tp_pio->ireg_data = t6_tp_tm_pio_array[i][1];
+ tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2];
+ tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3];
+ }
+
+ t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range,
+ tp_pio->ireg_local_offset, true);
+
+ ch_tp_pio++;
+ }
+
+ /* TP_MIB_INDEX*/
+ if (is_t5(padap->params.chip))
+ n = sizeof(t5_tp_mib_index_array) / (4 * sizeof(u32));
+ else if (is_t6(padap->params.chip))
+ n = sizeof(t6_tp_mib_index_array) / (4 * sizeof(u32));
+
+ for (i = 0; i < n ; i++) {
+ struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
+ u32 *buff = ch_tp_pio->outbuf;
+
+ if (is_t5(padap->params.chip)) {
+ tp_pio->ireg_addr = t5_tp_mib_index_array[i][0];
+ tp_pio->ireg_data = t5_tp_mib_index_array[i][1];
+ tp_pio->ireg_local_offset =
+ t5_tp_mib_index_array[i][2];
+ tp_pio->ireg_offset_range =
+ t5_tp_mib_index_array[i][3];
+ } else if (is_t6(padap->params.chip)) {
+ tp_pio->ireg_addr = t6_tp_mib_index_array[i][0];
+ tp_pio->ireg_data = t6_tp_mib_index_array[i][1];
+ tp_pio->ireg_local_offset =
+ t6_tp_mib_index_array[i][2];
+ tp_pio->ireg_offset_range =
+ t6_tp_mib_index_array[i][3];
+ }
+
+ t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range,
+ tp_pio->ireg_local_offset, true);
+
+ ch_tp_pio++;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_sge_indirect(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct ireg_buf *ch_sge_dbg;
+ u32 size;
+ int i, rc;
+
+ size = sizeof(struct ireg_buf) * 2;
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ ch_sge_dbg = (struct ireg_buf *)scratch_buff.data;
+
+ for (i = 0; i < 2; i++) {
+ struct ireg_field *sge_pio = &ch_sge_dbg->tp_pio;
+ u32 *buff = ch_sge_dbg->outbuf;
+
+ sge_pio->ireg_addr = t5_sge_dbg_index_array[i][0];
+ sge_pio->ireg_data = t5_sge_dbg_index_array[i][1];
+ sge_pio->ireg_local_offset = t5_sge_dbg_index_array[i][2];
+ sge_pio->ireg_offset_range = t5_sge_dbg_index_array[i][3];
+
+ t4_read_indirect(padap,
+ sge_pio->ireg_addr,
+ sge_pio->ireg_data,
+ buff,
+ sge_pio->ireg_offset_range,
+ sge_pio->ireg_local_offset);
+
+ ch_sge_dbg++;
+ }
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_full(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ u32 reg_addr, reg_data, reg_local_offset, reg_offset_range;
+ u32 *sp;
+ int rc;
+ int nreg = 0;
+
+ /* Collect Registers:
+ * TP_DBG_SCHED_TX (0x7e40 + 0x6a),
+ * TP_DBG_SCHED_RX (0x7e40 + 0x6b),
+ * TP_DBG_CSIDE_INT (0x7e40 + 0x23f),
+ * TP_DBG_ESIDE_INT (0x7e40 + 0x148),
+ * PCIE_CDEBUG_INDEX[AppData0] (0x5a10 + 2),
+ * PCIE_CDEBUG_INDEX[AppData1] (0x5a10 + 3) This is for T6
+ * SGE_DEBUG_DATA_HIGH_INDEX_10 (0x12a8)
+ **/
+
+ if (is_t5(padap->params.chip))
+ nreg = 6;
+ else if (is_t6(padap->params.chip))
+ nreg = 7;
+
+ scratch_buff.size = nreg * sizeof(u32);
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ sp = (u32 *)scratch_buff.data;
+
+ /* TP_DBG_SCHED_TX */
+ reg_local_offset = t5_tp_pio_array[3][2] + 0xa;
+ reg_offset_range = 1;
+
+ t4_tp_pio_read(padap, sp, reg_offset_range, reg_local_offset, true);
+
+ sp++;
+
+ /* TP_DBG_SCHED_RX */
+ reg_local_offset = t5_tp_pio_array[3][2] + 0xb;
+ reg_offset_range = 1;
+
+ t4_tp_pio_read(padap, sp, reg_offset_range, reg_local_offset, true);
+
+ sp++;
+
+ /* TP_DBG_CSIDE_INT */
+ reg_local_offset = t5_tp_pio_array[9][2] + 0xf;
+ reg_offset_range = 1;
+
+ t4_tp_pio_read(padap, sp, reg_offset_range, reg_local_offset, true);
+
+ sp++;
+
+ /* TP_DBG_ESIDE_INT */
+ reg_local_offset = t5_tp_pio_array[8][2] + 3;
+ reg_offset_range = 1;
+
+ t4_tp_pio_read(padap, sp, reg_offset_range, reg_local_offset, true);
+
+ sp++;
+
+ /* PCIE_CDEBUG_INDEX[AppData0] */
+ reg_addr = t5_pcie_cdbg_array[0][0];
+ reg_data = t5_pcie_cdbg_array[0][1];
+ reg_local_offset = t5_pcie_cdbg_array[0][2] + 2;
+ reg_offset_range = 1;
+
+ t4_read_indirect(padap, reg_addr, reg_data, sp, reg_offset_range,
+ reg_local_offset);
+
+ sp++;
+
+ if (is_t6(padap->params.chip)) {
+ /* PCIE_CDEBUG_INDEX[AppData1] */
+ reg_addr = t5_pcie_cdbg_array[0][0];
+ reg_data = t5_pcie_cdbg_array[0][1];
+ reg_local_offset = t5_pcie_cdbg_array[0][2] + 3;
+ reg_offset_range = 1;
+
+ t4_read_indirect(padap, reg_addr, reg_data, sp,
+ reg_offset_range, reg_local_offset);
+
+ sp++;
+ }
+
+ /* SGE_DEBUG_DATA_HIGH_INDEX_10 */
+ *sp = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_10);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+collect_vpd_data(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+#ifdef notyet
+ struct cudbg_buffer scratch_buff;
+ struct adapter *padap = pdbg_init->adap;
+ struct struct_vpd_data *vpd_data;
+ char vpd_ver[4];
+ u32 fw_vers;
+ u32 size;
+ int rc;
+
+ size = sizeof(struct struct_vpd_data);
+ scratch_buff.size = size;
+
+ rc = get_scratch_buff(dbg_buff, scratch_buff.size, &scratch_buff);
+ if (rc)
+ goto err;
+
+ vpd_data = (struct struct_vpd_data *)scratch_buff.data;
+
+ if (is_t5(padap->params.chip)) {
+ read_vpd_reg(padap, SN_REG_ADDR, SN_MAX_LEN, vpd_data->sn);
+ read_vpd_reg(padap, BN_REG_ADDR, BN_MAX_LEN, vpd_data->bn);
+ read_vpd_reg(padap, NA_REG_ADDR, NA_MAX_LEN, vpd_data->na);
+ read_vpd_reg(padap, MN_REG_ADDR, MN_MAX_LEN, vpd_data->mn);
+ } else if (is_t6(padap->params.chip)) {
+ read_vpd_reg(padap, SN_T6_ADDR, SN_MAX_LEN, vpd_data->sn);
+ read_vpd_reg(padap, BN_T6_ADDR, BN_MAX_LEN, vpd_data->bn);
+ read_vpd_reg(padap, NA_T6_ADDR, NA_MAX_LEN, vpd_data->na);
+ read_vpd_reg(padap, MN_T6_ADDR, MN_MAX_LEN, vpd_data->mn);
+ }
+
+ if (is_fw_attached(pdbg_init)) {
+ rc = t4_get_scfg_version(padap, &vpd_data->scfg_vers);
+ } else {
+ rc = 1;
+ }
+
+ if (rc) {
+ /* Now trying with backdoor mechanism */
+ rc = read_vpd_reg(padap, SCFG_VER_ADDR, SCFG_VER_LEN,
+ (u8 *)&vpd_data->scfg_vers);
+ if (rc)
+ goto err1;
+ }
+
+ if (is_fw_attached(pdbg_init)) {
+ rc = t4_get_vpd_version(padap, &vpd_data->vpd_vers);
+ } else {
+ rc = 1;
+ }
+
+ if (rc) {
+ /* Now trying with backdoor mechanism */
+ rc = read_vpd_reg(padap, VPD_VER_ADDR, VPD_VER_LEN,
+ (u8 *)vpd_ver);
+ if (rc)
+ goto err1;
+ /* read_vpd_reg return string of stored hex
+ * converting hex string to char string
+ * vpd version is 2 bytes only */
+ sprintf(vpd_ver, "%c%c\n", vpd_ver[0], vpd_ver[1]);
+ vpd_data->vpd_vers = simple_strtoul(vpd_ver, NULL, 16);
+ }
+
+ /* Get FW version if it's not already filled in */
+ fw_vers = padap->params.fw_vers;
+ if (!fw_vers) {
+ rc = t4_get_fw_version(padap, &fw_vers);
+ if (rc)
+ goto err1;
+ }
+
+ vpd_data->fw_major = G_FW_HDR_FW_VER_MAJOR(fw_vers);
+ vpd_data->fw_minor = G_FW_HDR_FW_VER_MINOR(fw_vers);
+ vpd_data->fw_micro = G_FW_HDR_FW_VER_MICRO(fw_vers);
+ vpd_data->fw_build = G_FW_HDR_FW_VER_BUILD(fw_vers);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+#endif
+ return (-1);
+}
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.h b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.h
new file mode 100644
index 0000000000..c6b59991e5
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib.h
@@ -0,0 +1,263 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*-
+ * Copyright (c) 2017 Chelsio Communications, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __CUDBG_LIB_H__
+#define __CUDBG_LIB_H__
+
+#ifndef min_t
+#define min_t(type, _a, _b) (((type)(_a) < (type)(_b)) ? (type)(_a) : (type)(_b))
+#endif
+
+static int collect_reg_dump(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_fw_devlog(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_qcfg(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_la(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_ma_la(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_obq_ulp0(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_obq_ulp1(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_obq_ulp2(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_obq_ulp3(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_obq_sge(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_obq_ncsi(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_ibq_tp0(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_ibq_tp1(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_ibq_ulp(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_ibq_sge0(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_ibq_sge1(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_ibq_ncsi(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_edc0_meminfo(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_edc1_meminfo(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_mc0_meminfo(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_mc1_meminfo(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_rss(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_rss_key(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_rss_pf_config(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_rss_vf_config(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_rss_config(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_path_mtu(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_sw_state(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+int collect_wtp_data(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_pm_stats(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_hw_sched(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_tcp_stats(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_tp_err_stats(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_fcoe_stats(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_rdma_stats(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_tp_indirect(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_sge_indirect(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cpl_stats(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_ddp_stats(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_wc_stats(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_ulprx_la(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_lb_stats(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_tp_la(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_meminfo(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cim_pif_la(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_clk_info(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_obq_sge_rx_q0(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_obq_sge_rx_q1(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_macstats(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_pcie_indirect(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_pm_indirect(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_full(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_tx_rate(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_tid(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_pcie_config(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_dump_context(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_mps_tcam(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_vpd_data(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_le_tcam(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_cctrl(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_ma_indirect(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_ulptx_la(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_up_cim_indirect(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_pbt_tables(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_mbox_log(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+static int collect_hma_indirect(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *);
+
+static int (*process_entity[])
+ (struct cudbg_init *, struct cudbg_buffer *, struct cudbg_error *) = {
+ collect_reg_dump,
+ collect_fw_devlog,
+ collect_cim_la, /*3*/
+ collect_cim_ma_la,
+ collect_cim_qcfg,
+ collect_cim_ibq_tp0,
+ collect_cim_ibq_tp1,
+ collect_cim_ibq_ulp,
+ collect_cim_ibq_sge0,
+ collect_cim_ibq_sge1,
+ collect_cim_ibq_ncsi,
+ collect_cim_obq_ulp0,
+ collect_cim_obq_ulp1, /*13*/
+ collect_cim_obq_ulp2,
+ collect_cim_obq_ulp3,
+ collect_cim_obq_sge,
+ collect_cim_obq_ncsi,
+ collect_edc0_meminfo,
+ collect_edc1_meminfo,
+ collect_mc0_meminfo,
+ collect_mc1_meminfo,
+ collect_rss, /*22*/
+ collect_rss_pf_config,
+ collect_rss_key,
+ collect_rss_vf_config,
+ collect_rss_config, /*26*/
+ collect_path_mtu, /*27*/
+ collect_sw_state,
+ collect_wtp_data,
+ collect_pm_stats,
+ collect_hw_sched,
+ collect_tcp_stats,
+ collect_tp_err_stats,
+ collect_fcoe_stats,
+ collect_rdma_stats,
+ collect_tp_indirect,
+ collect_sge_indirect,
+ collect_cpl_stats,
+ collect_ddp_stats,
+ collect_wc_stats,
+ collect_ulprx_la,
+ collect_lb_stats,
+ collect_tp_la,
+ collect_meminfo,
+ collect_cim_pif_la,
+ collect_clk_info,
+ collect_obq_sge_rx_q0,
+ collect_obq_sge_rx_q1,
+ collect_macstats,
+ collect_pcie_indirect,
+ collect_pm_indirect,
+ collect_full,
+ collect_tx_rate,
+ collect_tid,
+ collect_pcie_config,
+ collect_dump_context,
+ collect_mps_tcam,
+ collect_vpd_data,
+ collect_le_tcam,
+ collect_cctrl,
+ collect_ma_indirect,
+ collect_ulptx_la,
+ NULL, /* ext entity */
+ collect_up_cim_indirect,
+ collect_pbt_tables,
+ collect_mbox_log,
+ collect_hma_indirect,
+ };
+
+struct large_entity {
+ int entity_code;
+ int skip_flag;
+ int priority; /* 1 is high priority */
+};
+
+static int read_cim_ibq(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error * , int);
+static int read_cim_obq(struct cudbg_init *, struct cudbg_buffer *,
+ struct cudbg_error *, int);
+int get_entity_hdr(void *outbuf, int i, u32 size, struct cudbg_entity_hdr **);
+void skip_entity(int entity_code);
+void reset_skip_entity(void);
+int is_large_entity(int entity_code);
+#endif
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib_common.h b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib_common.h
new file mode 100644
index 0000000000..72b901f47c
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_lib_common.h
@@ -0,0 +1,153 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*-
+ * Copyright (c) 2017 Chelsio Communications, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef __CUDBG_LIB_COMMON_H__
+#define __CUDBG_LIB_COMMON_H__
+
+#define CUDBG_EXT_DATA_BIT 0
+#define CUDBG_EXT_DATA_VALID (1 << CUDBG_EXT_DATA_BIT)
+
+#ifdef _KERNEL
+#include "common/t4_hw.h"
+
+#define CUDBG_SF_MAX_SECTOR (FLASH_CUDBG_START_SEC + FLASH_CUDBG_NSECS)
+#define CUDBG_SF_SECTOR_SIZE SF_SEC_SIZE
+#define CUDBG_START_SEC FLASH_CUDBG_START_SEC
+#define CUDBG_FLASH_SIZE FLASH_CUDBG_MAX_SIZE
+
+struct cudbg_flash_sec_info {
+ int par_sec; /* Represent partially filled sector no */
+ int par_sec_offset; /* Offset in partially filled sector */
+ int cur_seq_no;
+ u32 max_seq_no;
+ u32 max_seq_sec;
+ u32 hdr_data_len; /* Total data */
+ u32 skip_size; /* Total size of large entities. */
+ u64 max_timestamp;
+ char sec_data[CUDBG_SF_SECTOR_SIZE];
+ u8 sec_bitmap[8];
+};
+
+void update_skip_size(struct cudbg_flash_sec_info *, u32);
+#endif
+#include "osdep.h"
+
+struct cudbg_hdr {
+ u32 signature;
+ u32 hdr_len;
+ u16 major_ver;
+ u16 minor_ver;
+ u32 data_len;
+ u32 hdr_flags;
+ u16 max_entities;
+ u8 chip_ver;
+ u8 reserved1;
+ u32 reserved[8];
+};
+
+struct cudbg_entity_hdr {
+ u32 entity_type;
+ u32 start_offset;
+ u32 size;
+ int hdr_flags;
+ u32 sys_warn;
+ u32 sys_err;
+ u8 num_pad;
+ u8 flag; /* bit 0 is used to indicate ext data */
+ u8 reserved1[2];
+ u32 next_ext_offset; /* pointer to next extended entity meta data */
+ u32 reserved[5];
+};
+
+struct cudbg_ver_hdr {
+ u32 signature;
+ u16 revision;
+ u16 size;
+};
+
+struct cudbg_buffer {
+ u32 size;
+ u32 offset;
+ char *data;
+};
+
+struct cudbg_error {
+ int sys_err;
+ int sys_warn;
+ int app_err;
+};
+
+#define HTONL_NIBBLE(data) ( \
+ (((uint32_t)(data) >> 28) & 0x0000000F) | \
+ (((uint32_t)(data) >> 20) & 0x000000F0) | \
+ (((uint32_t)(data) >> 12) & 0x00000F00) | \
+ (((uint32_t)(data) >> 4) & 0x0000F000) | \
+ (((uint32_t)(data) << 4) & 0x000F0000) | \
+ (((uint32_t)(data) << 12) & 0x00F00000) | \
+ (((uint32_t)(data) << 20) & 0x0F000000) | \
+ (((uint32_t)(data) << 28) & 0xF0000000))
+
+#define CDUMP_MAX_COMP_BUF_SIZE ((64 * 1024) - 1)
+#define CUDBG_CHUNK_SIZE ((CDUMP_MAX_COMP_BUF_SIZE/1024) * 1024)
+
+#define CUDBG_LEGACY_SIGNATURE 123
+#define CUDBG_SIGNATURE 67856866 /* CUDB in ascii */
+#define CUDBG_FL_SIGNATURE 0x4355464c /* CUFL in ascii */
+
+#define CUDBG_FL_MAJOR_VERSION 1
+#define CUDBG_FL_MINOR_VERSION 1
+#define CUDBG_FL_BUILD_VERSION 0
+
+int write_compression_hdr(struct cudbg_buffer *, struct cudbg_buffer *);
+int compress_buff(struct cudbg_buffer *, struct cudbg_buffer *);
+int get_scratch_buff(struct cudbg_buffer *, u32, struct cudbg_buffer *);
+void release_scratch_buff(struct cudbg_buffer *, struct cudbg_buffer *);
+int decompress_buffer(struct cudbg_buffer *, struct cudbg_buffer *);
+int validate_buffer(struct cudbg_buffer *compressed_buffer);
+int decompress_buffer_wrapper(struct cudbg_buffer *pc_buff,
+ struct cudbg_buffer *pdc_buff);
+int get_entity_rev(struct cudbg_ver_hdr *ver_hdr);
+void sort_t(void *base, int num, int size,
+ int (*cmp_func)(const void *, const void *),
+ void (*swap_func)(void *, void *, int size));
+int cudbg_read_flash(void *handle, void *data, u32 size, int data_flag);
+int cudbg_write_flash(void *handle, u64 timestamp, void *data,
+ u32 start_offset, u32 start_hdr_offset,
+ u32 cur_entity_size,
+ u32 ext_size);
+#endif
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
new file mode 100644
index 0000000000..ef4660d442
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/cudbg_wtp.c
@@ -0,0 +1,1323 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*-
+ * Copyright (c) 2017 Chelsio Communications, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <sys/param.h>
+
+#include "common/common.h"
+#include "common/t4_regs.h"
+#include "cudbg.h"
+#include "cudbg_lib_common.h"
+#include "cudbg_entity.h"
+
+int collect_wtp_data(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err);
+/*SGE_DEBUG Registers.*/
+#define TP_MIB_SIZE 0x5e
+
+struct sge_debug_reg_data {
+ /*indx0*/
+ u32 reserved1:4;
+ u32 reserved2:4;
+ u32 debug_uP_SOP_cnt:4;
+ u32 debug_uP_EOP_cnt:4;
+ u32 debug_CIM_SOP1_cnt:4;
+ u32 debug_CIM_EOP1_cnt:4;
+ u32 debug_CIM_SOP0_cnt:4;
+ u32 debug_CIM_EOP0_cnt:4;
+
+ /*indx1*/
+ u32 reserved3:32;
+
+ /*indx2*/
+ u32 debug_T_Rx_SOP1_cnt:4;
+ u32 debug_T_Rx_EOP1_cnt:4;
+ u32 debug_T_Rx_SOP0_cnt:4;
+ u32 debug_T_Rx_EOP0_cnt:4;
+ u32 debug_U_Rx_SOP1_cnt:4;
+ u32 debug_U_Rx_EOP1_cnt:4;
+ u32 debug_U_Rx_SOP0_cnt:4;
+ u32 debug_U_Rx_EOP0_cnt:4;
+
+ /*indx3*/
+ u32 reserved4:32;
+
+ /*indx4*/
+ u32 debug_UD_Rx_SOP3_cnt:4;
+ u32 debug_UD_Rx_EOP3_cnt:4;
+ u32 debug_UD_Rx_SOP2_cnt:4;
+ u32 debug_UD_Rx_EOP2_cnt:4;
+ u32 debug_UD_Rx_SOP1_cnt:4;
+ u32 debug_UD_Rx_EOP1_cnt:4;
+ u32 debug_UD_Rx_SOP0_cnt:4;
+ u32 debug_UD_Rx_EOP0_cnt:4;
+
+ /*indx5*/
+ u32 reserved5:32;
+
+ /*indx6*/
+ u32 debug_U_Tx_SOP3_cnt:4;
+ u32 debug_U_Tx_EOP3_cnt:4;
+ u32 debug_U_Tx_SOP2_cnt:4;
+ u32 debug_U_Tx_EOP2_cnt:4;
+ u32 debug_U_Tx_SOP1_cnt:4;
+ u32 debug_U_Tx_EOP1_cnt:4;
+ u32 debug_U_Tx_SOP0_cnt:4;
+ u32 debug_U_Tx_EOP0_cnt:4;
+
+ /*indx7*/
+ u32 reserved6:32;
+
+ /*indx8*/
+ u32 debug_PC_Rsp_SOP1_cnt:4;
+ u32 debug_PC_Rsp_EOP1_cnt:4;
+ u32 debug_PC_Rsp_SOP0_cnt:4;
+ u32 debug_PC_Rsp_EOP0_cnt:4;
+ u32 debug_PC_Req_SOP1_cnt:4;
+ u32 debug_PC_Req_EOP1_cnt:4;
+ u32 debug_PC_Req_SOP0_cnt:4;
+ u32 debug_PC_Req_EOP0_cnt:4;
+
+ /*indx9*/
+ u32 reserved7:32;
+
+ /*indx10*/
+ u32 debug_PD_Req_SOP3_cnt:4;
+ u32 debug_PD_Req_EOP3_cnt:4;
+ u32 debug_PD_Req_SOP2_cnt:4;
+ u32 debug_PD_Req_EOP2_cnt:4;
+ u32 debug_PD_Req_SOP1_cnt:4;
+ u32 debug_PD_Req_EOP1_cnt:4;
+ u32 debug_PD_Req_SOP0_cnt:4;
+ u32 debug_PD_Req_EOP0_cnt:4;
+
+ /*indx11*/
+ u32 reserved8:32;
+
+ /*indx12*/
+ u32 debug_PD_Rsp_SOP3_cnt:4;
+ u32 debug_PD_Rsp_EOP3_cnt:4;
+ u32 debug_PD_Rsp_SOP2_cnt:4;
+ u32 debug_PD_Rsp_EOP2_cnt:4;
+ u32 debug_PD_Rsp_SOP1_cnt:4;
+ u32 debug_PD_Rsp_EOP1_cnt:4;
+ u32 debug_PD_Rsp_SOP0_cnt:4;
+ u32 debug_PD_Rsp_EOP0_cnt:4;
+
+ /*indx13*/
+ u32 reserved9:32;
+
+ /*indx14*/
+ u32 debug_CPLSW_TP_Rx_SOP1_cnt:4;
+ u32 debug_CPLSW_TP_Rx_EOP1_cnt:4;
+ u32 debug_CPLSW_TP_Rx_SOP0_cnt:4;
+ u32 debug_CPLSW_TP_Rx_EOP0_cnt:4;
+ u32 debug_CPLSW_CIM_SOP1_cnt:4;
+ u32 debug_CPLSW_CIM_EOP1_cnt:4;
+ u32 debug_CPLSW_CIM_SOP0_cnt:4;
+ u32 debug_CPLSW_CIM_EOP0_cnt:4;
+
+ /*indx15*/
+ u32 reserved10:32;
+
+ /*indx16*/
+ u32 debug_PD_Req_Rd3_cnt:4;
+ u32 debug_PD_Req_Rd2_cnt:4;
+ u32 debug_PD_Req_Rd1_cnt:4;
+ u32 debug_PD_Req_Rd0_cnt:4;
+ u32 debug_PD_Req_Int3_cnt:4;
+ u32 debug_PD_Req_Int2_cnt:4;
+ u32 debug_PD_Req_Int1_cnt:4;
+ u32 debug_PD_Req_Int0_cnt:4;
+
+};
+
+struct tp_mib_type tp_mib[] = {
+ {"tp_mib_mac_in_err_0", 0x0},
+ {"tp_mib_mac_in_err_1", 0x1},
+ {"tp_mib_mac_in_err_2", 0x2},
+ {"tp_mib_mac_in_err_3", 0x3},
+ {"tp_mib_hdr_in_err_0", 0x4},
+ {"tp_mib_hdr_in_err_1", 0x5},
+ {"tp_mib_hdr_in_err_2", 0x6},
+ {"tp_mib_hdr_in_err_3", 0x7},
+ {"tp_mib_tcp_in_err_0", 0x8},
+ {"tp_mib_tcp_in_err_1", 0x9},
+ {"tp_mib_tcp_in_err_2", 0xa},
+ {"tp_mib_tcp_in_err_3", 0xb},
+ {"tp_mib_tcp_out_rst", 0xc},
+ {"tp_mib_tcp_in_seg_hi", 0x10},
+ {"tp_mib_tcp_in_seg_lo", 0x11},
+ {"tp_mib_tcp_out_seg_hi", 0x12},
+ {"tp_mib_tcp_out_seg_lo", 0x13},
+ {"tp_mib_tcp_rxt_seg_hi", 0x14},
+ {"tp_mib_tcp_rxt_seg_lo", 0x15},
+ {"tp_mib_tnl_cng_drop_0", 0x18},
+ {"tp_mib_tnl_cng_drop_1", 0x19},
+ {"tp_mib_tnl_cng_drop_2", 0x1a},
+ {"tp_mib_tnl_cng_drop_3", 0x1b},
+ {"tp_mib_ofd_chn_drop_0", 0x1c},
+ {"tp_mib_ofd_chn_drop_1", 0x1d},
+ {"tp_mib_ofd_chn_drop_2", 0x1e},
+ {"tp_mib_ofd_chn_drop_3", 0x1f},
+ {"tp_mib_tnl_out_pkt_0", 0x20},
+ {"tp_mib_tnl_out_pkt_1", 0x21},
+ {"tp_mib_tnl_out_pkt_2", 0x22},
+ {"tp_mib_tnl_out_pkt_3", 0x23},
+ {"tp_mib_tnl_in_pkt_0", 0x24},
+ {"tp_mib_tnl_in_pkt_1", 0x25},
+ {"tp_mib_tnl_in_pkt_2", 0x26},
+ {"tp_mib_tnl_in_pkt_3", 0x27},
+ {"tp_mib_tcp_v6in_err_0", 0x28},
+ {"tp_mib_tcp_v6in_err_1", 0x29},
+ {"tp_mib_tcp_v6in_err_2", 0x2a},
+ {"tp_mib_tcp_v6in_err_3", 0x2b},
+ {"tp_mib_tcp_v6out_rst", 0x2c},
+ {"tp_mib_tcp_v6in_seg_hi", 0x30},
+ {"tp_mib_tcp_v6in_seg_lo", 0x31},
+ {"tp_mib_tcp_v6out_seg_hi", 0x32},
+ {"tp_mib_tcp_v6out_seg_lo", 0x33},
+ {"tp_mib_tcp_v6rxt_seg_hi", 0x34},
+ {"tp_mib_tcp_v6rxt_seg_lo", 0x35},
+ {"tp_mib_ofd_arp_drop", 0x36},
+ {"tp_mib_ofd_dfr_drop", 0x37},
+ {"tp_mib_cpl_in_req_0", 0x38},
+ {"tp_mib_cpl_in_req_1", 0x39},
+ {"tp_mib_cpl_in_req_2", 0x3a},
+ {"tp_mib_cpl_in_req_3", 0x3b},
+ {"tp_mib_cpl_out_rsp_0", 0x3c},
+ {"tp_mib_cpl_out_rsp_1", 0x3d},
+ {"tp_mib_cpl_out_rsp_2", 0x3e},
+ {"tp_mib_cpl_out_rsp_3", 0x3f},
+ {"tp_mib_tnl_lpbk_0", 0x40},
+ {"tp_mib_tnl_lpbk_1", 0x41},
+ {"tp_mib_tnl_lpbk_2", 0x42},
+ {"tp_mib_tnl_lpbk_3", 0x43},
+ {"tp_mib_tnl_drop_0", 0x44},
+ {"tp_mib_tnl_drop_1", 0x45},
+ {"tp_mib_tnl_drop_2", 0x46},
+ {"tp_mib_tnl_drop_3", 0x47},
+ {"tp_mib_fcoe_ddp_0", 0x48},
+ {"tp_mib_fcoe_ddp_1", 0x49},
+ {"tp_mib_fcoe_ddp_2", 0x4a},
+ {"tp_mib_fcoe_ddp_3", 0x4b},
+ {"tp_mib_fcoe_drop_0", 0x4c},
+ {"tp_mib_fcoe_drop_1", 0x4d},
+ {"tp_mib_fcoe_drop_2", 0x4e},
+ {"tp_mib_fcoe_drop_3", 0x4f},
+ {"tp_mib_fcoe_byte_0_hi", 0x50},
+ {"tp_mib_fcoe_byte_0_lo", 0x51},
+ {"tp_mib_fcoe_byte_1_hi", 0x52},
+ {"tp_mib_fcoe_byte_1_lo", 0x53},
+ {"tp_mib_fcoe_byte_2_hi", 0x54},
+ {"tp_mib_fcoe_byte_2_lo", 0x55},
+ {"tp_mib_fcoe_byte_3_hi", 0x56},
+ {"tp_mib_fcoe_byte_3_lo", 0x57},
+ {"tp_mib_ofd_vln_drop_0", 0x58},
+ {"tp_mib_ofd_vln_drop_1", 0x59},
+ {"tp_mib_ofd_vln_drop_2", 0x5a},
+ {"tp_mib_ofd_vln_drop_3", 0x5b},
+ {"tp_mib_usm_pkts", 0x5c},
+ {"tp_mib_usm_drop", 0x5d},
+ {"tp_mib_usm_bytes_hi", 0x5e},
+ {"tp_mib_usm_bytes_lo", 0x5f},
+ {"tp_mib_tid_del", 0x60},
+ {"tp_mib_tid_inv", 0x61},
+ {"tp_mib_tid_act", 0x62},
+ {"tp_mib_tid_pas", 0x63},
+ {"tp_mib_rqe_dfr_mod", 0x64},
+ {"tp_mib_rqe_dfr_pkt", 0x65}
+};
+
+static u32
+read_sge_debug_data(struct cudbg_init *pdbg_init, u32 *sge_dbg_reg)
+{
+ struct adapter *padap = pdbg_init->adap;
+ u32 value;
+ int i = 0;
+
+ for (i = 0; i <= 15; i++) {
+ t4_write_reg(padap, A_SGE_DEBUG_INDEX, (u32)i);
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_LOW);
+ /*printf("LOW 0x%08x\n", value);*/
+ sge_dbg_reg[(i << 1) | 1] = HTONL_NIBBLE(value);
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH);
+ /*printf("HIGH 0x%08x\n", value);*/
+ sge_dbg_reg[(i << 1)] = HTONL_NIBBLE(value);
+ }
+ return 0;
+}
+
+static u32
+read_tp_mib_data(struct cudbg_init *pdbg_init,
+ struct tp_mib_data **ppTp_Mib)
+{
+ struct adapter *padap = pdbg_init->adap;
+ u32 i = 0;
+
+ for (i = 0; i < TP_MIB_SIZE; i++) {
+ t4_tp_mib_read(padap, &tp_mib[i].value, 1,
+ (u32)tp_mib[i].addr, true);
+ }
+ *ppTp_Mib = (struct tp_mib_data *)&tp_mib[0];
+
+ return 0;
+}
+
+static int
+t5_wtp_data(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct sge_debug_reg_data *sge_dbg_reg = NULL;
+ struct cudbg_buffer scratch_buff;
+ struct tp_mib_data *ptp_mib = NULL;
+ struct wtp_data *wtp;
+ u32 Sge_Dbg[32] = {0};
+ u32 value = 0;
+ u32 i = 0;
+ u32 drop = 0;
+ u32 err = 0;
+ u32 offset;
+ int rc = 0;
+
+ rc = get_scratch_buff(dbg_buff, sizeof(struct wtp_data), &scratch_buff);
+
+ if (rc)
+ goto err;
+
+ offset = scratch_buff.offset;
+ wtp = (struct wtp_data *)((char *)scratch_buff.data + offset);
+
+ read_sge_debug_data(pdbg_init, Sge_Dbg);
+ read_tp_mib_data(pdbg_init, &ptp_mib);
+
+ sge_dbg_reg = (struct sge_debug_reg_data *) &Sge_Dbg[0];
+
+ /*#######################################################################*/
+ /*# TX PATH, starting from pcie*/
+ /*#######################################################################*/
+
+ /* Get Reqests of commmands from SGE to PCIE*/
+
+ wtp->sge_pcie_cmd_req.sop[0] = sge_dbg_reg->debug_PC_Req_SOP0_cnt;
+ wtp->sge_pcie_cmd_req.sop[1] = sge_dbg_reg->debug_PC_Req_SOP1_cnt;
+
+ wtp->sge_pcie_cmd_req.eop[0] = sge_dbg_reg->debug_PC_Req_EOP0_cnt;
+ wtp->sge_pcie_cmd_req.eop[1] = sge_dbg_reg->debug_PC_Req_EOP1_cnt;
+
+ /* Get Reqests of commmands from PCIE to core*/
+ value = t4_read_reg(padap, A_PCIE_CMDR_REQ_CNT);
+
+ wtp->pcie_core_cmd_req.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->pcie_core_cmd_req.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ /* there is no EOP for this, so we fake it.*/
+ wtp->pcie_core_cmd_req.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->pcie_core_cmd_req.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
+
+ /* Get DMA stats*/
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT3 + (i * 0x10));
+ wtp->pcie_t5_dma_stat3.sop[i] = value & 0xFF;
+ wtp->pcie_t5_dma_stat3.eop[i] = ((value >> 16) & 0xFF);
+ }
+
+ /* Get SGE debug data high index 6*/
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_6);
+ wtp->sge_debug_data_high_index_6.sop[0] = ((value >> 4) & 0x0F);
+ wtp->sge_debug_data_high_index_6.eop[0] = ((value >> 0) & 0x0F);
+ wtp->sge_debug_data_high_index_6.sop[1] = ((value >> 12) & 0x0F);
+ wtp->sge_debug_data_high_index_6.eop[1] = ((value >> 8) & 0x0F);
+ wtp->sge_debug_data_high_index_6.sop[2] = ((value >> 20) & 0x0F);
+ wtp->sge_debug_data_high_index_6.eop[2] = ((value >> 16) & 0x0F);
+ wtp->sge_debug_data_high_index_6.sop[3] = ((value >> 28) & 0x0F);
+ wtp->sge_debug_data_high_index_6.eop[3] = ((value >> 24) & 0x0F);
+
+ /* Get SGE debug data high index 3*/
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_3);
+ wtp->sge_debug_data_high_index_3.sop[0] = ((value >> 4) & 0x0F);
+ wtp->sge_debug_data_high_index_3.eop[0] = ((value >> 0) & 0x0F);
+ wtp->sge_debug_data_high_index_3.sop[1] = ((value >> 12) & 0x0F);
+ wtp->sge_debug_data_high_index_3.eop[1] = ((value >> 8) & 0x0F);
+ wtp->sge_debug_data_high_index_3.sop[2] = ((value >> 20) & 0x0F);
+ wtp->sge_debug_data_high_index_3.eop[2] = ((value >> 16) & 0x0F);
+ wtp->sge_debug_data_high_index_3.sop[3] = ((value >> 28) & 0x0F);
+ wtp->sge_debug_data_high_index_3.eop[3] = ((value >> 24) & 0x0F);
+
+ /* Get ULP SE CNT CHx*/
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap, A_ULP_TX_SE_CNT_CH0 + (i * 4));
+ wtp->ulp_se_cnt_chx.sop[i] = ((value >> 28) & 0x0F);
+ wtp->ulp_se_cnt_chx.eop[i] = ((value >> 24) & 0x0F);
+ }
+
+ /* Get MAC PORTx PKT COUNT*/
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap, 0x3081c + ((i * 4) << 12));
+ wtp->mac_portx_pkt_count.sop[i] = ((value >> 24) & 0xFF);
+ wtp->mac_portx_pkt_count.eop[i] = ((value >> 16) & 0xFF);
+ wtp->mac_porrx_pkt_count.sop[i] = ((value >> 8) & 0xFF);
+ wtp->mac_porrx_pkt_count.eop[i] = ((value >> 0) & 0xFF);
+ }
+
+ /* Get mac portx aFramesTransmittedok*/
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap, 0x30a80 + ((i * 4) << 12));
+ wtp->mac_portx_aframestra_ok.sop[i] = (value & 0xFF);
+ wtp->mac_portx_aframestra_ok.eop[i] = (value & 0xFF);
+ }
+
+ /* Get command respones from core to PCIE*/
+ value = t4_read_reg(padap, A_PCIE_CMDR_RSP_CNT);
+
+ wtp->core_pcie_cmd_rsp.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->core_pcie_cmd_rsp.sop[1] = ((value >> 16) & 0xFF); /*bit 16:23*/
+
+ wtp->core_pcie_cmd_rsp.eop[0] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->core_pcie_cmd_rsp.eop[1] = ((value >> 24) & 0xFF); /*bit 24:31*/
+
+ /*Get command Resposes from PCIE to SGE*/
+ wtp->pcie_sge_cmd_rsp.sop[0] = sge_dbg_reg->debug_PC_Rsp_SOP0_cnt;
+ wtp->pcie_sge_cmd_rsp.sop[1] = sge_dbg_reg->debug_PC_Rsp_SOP1_cnt;
+
+ wtp->pcie_sge_cmd_rsp.eop[0] = sge_dbg_reg->debug_PC_Rsp_EOP0_cnt;
+ wtp->pcie_sge_cmd_rsp.eop[1] = sge_dbg_reg->debug_PC_Rsp_EOP1_cnt;
+
+ /* Get commands sent from SGE to CIM/uP*/
+ wtp->sge_cim.sop[0] = sge_dbg_reg->debug_CIM_SOP0_cnt;
+ wtp->sge_cim.sop[1] = sge_dbg_reg->debug_CIM_SOP1_cnt;
+
+ wtp->sge_cim.eop[0] = sge_dbg_reg->debug_CIM_EOP0_cnt;
+ wtp->sge_cim.eop[1] = sge_dbg_reg->debug_CIM_EOP1_cnt;
+
+ /* Get Reqests of data from PCIE by SGE*/
+ wtp->utx_sge_dma_req.sop[0] = sge_dbg_reg->debug_UD_Rx_SOP0_cnt;
+ wtp->utx_sge_dma_req.sop[1] = sge_dbg_reg->debug_UD_Rx_SOP1_cnt;
+ wtp->utx_sge_dma_req.sop[2] = sge_dbg_reg->debug_UD_Rx_SOP2_cnt;
+ wtp->utx_sge_dma_req.sop[3] = sge_dbg_reg->debug_UD_Rx_SOP3_cnt;
+
+ wtp->utx_sge_dma_req.eop[0] = sge_dbg_reg->debug_UD_Rx_EOP0_cnt;
+ wtp->utx_sge_dma_req.eop[1] = sge_dbg_reg->debug_UD_Rx_EOP1_cnt;
+ wtp->utx_sge_dma_req.eop[2] = sge_dbg_reg->debug_UD_Rx_EOP2_cnt;
+ wtp->utx_sge_dma_req.eop[3] = sge_dbg_reg->debug_UD_Rx_EOP3_cnt;
+
+ /* Get Reqests of data from PCIE by SGE*/
+ wtp->sge_pcie_dma_req.sop[0] = sge_dbg_reg->debug_PD_Req_Rd0_cnt;
+ wtp->sge_pcie_dma_req.sop[1] = sge_dbg_reg->debug_PD_Req_Rd1_cnt;
+ wtp->sge_pcie_dma_req.sop[2] = sge_dbg_reg->debug_PD_Req_Rd2_cnt;
+ wtp->sge_pcie_dma_req.sop[3] = sge_dbg_reg->debug_PD_Req_Rd3_cnt;
+ /*no EOP's, so fake it.*/
+ wtp->sge_pcie_dma_req.eop[0] = sge_dbg_reg->debug_PD_Req_Rd0_cnt;
+ wtp->sge_pcie_dma_req.eop[1] = sge_dbg_reg->debug_PD_Req_Rd1_cnt;
+ wtp->sge_pcie_dma_req.eop[2] = sge_dbg_reg->debug_PD_Req_Rd2_cnt;
+ wtp->sge_pcie_dma_req.eop[3] = sge_dbg_reg->debug_PD_Req_Rd3_cnt;
+
+ /* Get Reqests of data from PCIE to core*/
+ value = t4_read_reg(padap, A_PCIE_DMAR_REQ_CNT);
+
+ wtp->pcie_core_dma_req.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->pcie_core_dma_req.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->pcie_core_dma_req.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
+ wtp->pcie_core_dma_req.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
+ /* There is no eop so fake it.*/
+ wtp->pcie_core_dma_req.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->pcie_core_dma_req.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->pcie_core_dma_req.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
+ wtp->pcie_core_dma_req.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
+
+ /* Get data responses from core to PCIE*/
+ value = t4_read_reg(padap, A_PCIE_DMAR_RSP_SOP_CNT);
+
+ wtp->core_pcie_dma_rsp.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->core_pcie_dma_rsp.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->core_pcie_dma_rsp.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
+ wtp->core_pcie_dma_rsp.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
+
+ value = t4_read_reg(padap, A_PCIE_DMAR_RSP_EOP_CNT);
+
+ wtp->core_pcie_dma_rsp.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->core_pcie_dma_rsp.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->core_pcie_dma_rsp.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
+ wtp->core_pcie_dma_rsp.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
+
+ /* Get PCIE_DATA to SGE*/
+ wtp->pcie_sge_dma_rsp.sop[0] = sge_dbg_reg->debug_PD_Rsp_SOP0_cnt;
+ wtp->pcie_sge_dma_rsp.sop[1] = sge_dbg_reg->debug_PD_Rsp_SOP1_cnt;
+ wtp->pcie_sge_dma_rsp.sop[2] = sge_dbg_reg->debug_PD_Rsp_SOP2_cnt;
+ wtp->pcie_sge_dma_rsp.sop[3] = sge_dbg_reg->debug_PD_Rsp_SOP3_cnt;
+
+ wtp->pcie_sge_dma_rsp.eop[0] = sge_dbg_reg->debug_PD_Rsp_EOP0_cnt;
+ wtp->pcie_sge_dma_rsp.eop[1] = sge_dbg_reg->debug_PD_Rsp_EOP1_cnt;
+ wtp->pcie_sge_dma_rsp.eop[2] = sge_dbg_reg->debug_PD_Rsp_EOP2_cnt;
+ wtp->pcie_sge_dma_rsp.eop[3] = sge_dbg_reg->debug_PD_Rsp_EOP3_cnt;
+
+ /*Get SGE to ULP_TX*/
+ wtp->sge_utx.sop[0] = sge_dbg_reg->debug_U_Tx_SOP0_cnt;
+ wtp->sge_utx.sop[1] = sge_dbg_reg->debug_U_Tx_SOP1_cnt;
+ wtp->sge_utx.sop[2] = sge_dbg_reg->debug_U_Tx_SOP2_cnt;
+ wtp->sge_utx.sop[3] = sge_dbg_reg->debug_U_Tx_SOP3_cnt;
+
+ wtp->sge_utx.eop[0] = sge_dbg_reg->debug_U_Tx_EOP0_cnt;
+ wtp->sge_utx.eop[1] = sge_dbg_reg->debug_U_Tx_EOP1_cnt;
+ wtp->sge_utx.eop[2] = sge_dbg_reg->debug_U_Tx_EOP2_cnt;
+ wtp->sge_utx.eop[3] = sge_dbg_reg->debug_U_Tx_EOP3_cnt;
+
+ /* Get ULP_TX to TP*/
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap, (A_ULP_TX_SE_CNT_CH0 + (i*4)));
+
+ wtp->utx_tp.sop[i] = ((value >> 28) & 0xF); /*bits 28:31*/
+ wtp->utx_tp.eop[i] = ((value >> 24) & 0xF); /*bits 24:27*/
+ }
+
+ /* Get TP_DBG_CSIDE registers*/
+ for (i = 0; i < 4; i++) {
+ t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i),
+ true);
+
+ wtp->utx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/
+ wtp->utx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/
+ wtp->tpcside_rxpld.sop[i] = ((value >> 20) & 0xF);/*bits 20:23*/
+ wtp->tpcside_rxpld.eop[i] = ((value >> 16) & 0xF);/*bits 16:19*/
+ wtp->tpcside_rxarb.sop[i] = ((value >> 12) & 0xF);/*bits 12:15*/
+ wtp->tpcside_rxarb.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/
+ wtp->tpcside_rxcpl.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/
+ wtp->tpcside_rxcpl.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/
+ }
+
+ /* TP_DBG_ESIDE*/
+ for (i = 0; i < 4; i++) {
+ t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
+ true);
+
+ wtp->tpeside_mps.sop[i] = ((value >> 28) & 0xF); /*bits 28:31*/
+ wtp->tpeside_mps.eop[i] = ((value >> 24) & 0xF); /*bits 24:27*/
+ wtp->tpeside_pm.sop[i] = ((value >> 20) & 0xF); /*bits 20:23*/
+ wtp->tpeside_pm.eop[i] = ((value >> 16) & 0xF); /*bits 16:19*/
+ wtp->mps_tpeside.sop[i] = ((value >> 12) & 0xF); /*bits 12:15*/
+ wtp->mps_tpeside.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/
+ wtp->tpeside_pld.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/
+ wtp->tpeside_pld.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/
+
+ }
+
+ /*PCIE CMD STAT2*/
+ for (i = 0; i < 3; i++) {
+ value = t4_read_reg(padap, 0x5988 + (i * 0x10));
+ wtp->pcie_cmd_stat2.sop[i] = value & 0xFF;
+ wtp->pcie_cmd_stat2.eop[i] = value & 0xFF;
+ }
+
+ /*PCIE cmd stat3*/
+ for (i = 0; i < 3; i++) {
+ value = t4_read_reg(padap, 0x598c + (i * 0x10));
+ wtp->pcie_cmd_stat3.sop[i] = value & 0xFF;
+ wtp->pcie_cmd_stat3.eop[i] = value & 0xFF;
+ }
+
+ /* ULP_RX input/output*/
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, (A_ULP_RX_SE_CNT_CH0 + (i*4)));
+
+ wtp->pmrx_ulprx.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/
+ wtp->pmrx_ulprx.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/
+ wtp->ulprx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/
+ wtp->ulprx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/
+ }
+
+ /* Get the MPS input from TP*/
+ drop = 0;
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_TP01 + (i << 2)));
+ wtp->tp_mps.sop[(i*2)] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->tp_mps.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->tp_mps.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31
+ */
+ wtp->tp_mps.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23
+ */
+ }
+ drop = ptp_mib->TP_MIB_OFD_ARP_DROP.value;
+ drop += ptp_mib->TP_MIB_OFD_DFR_DROP.value;
+
+ drop += ptp_mib->TP_MIB_TNL_DROP_0.value;
+ drop += ptp_mib->TP_MIB_TNL_DROP_1.value;
+ drop += ptp_mib->TP_MIB_TNL_DROP_2.value;
+ drop += ptp_mib->TP_MIB_TNL_DROP_3.value;
+
+ wtp->tp_mps.drops = drop;
+
+ /* Get the MPS output to the MAC's*/
+ drop = 0;
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_MAC01 + (i << 2)));
+ wtp->mps_xgm.sop[(i*2)] = ((value >> 8) & 0xFF);/*bit 8:15*/
+ wtp->mps_xgm.eop[(i*2)] = ((value >> 0) & 0xFF);/*bit 0:7*/
+ wtp->mps_xgm.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31
+ */
+ wtp->mps_xgm.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23
+ */
+ }
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_TX_PORT_DROP_L) +
+ (i * T5_PORT_STRIDE)));
+ drop += value;
+ }
+ wtp->mps_xgm.drops = (drop & 0xFF);
+
+ /* Get the SOP/EOP counters into and out of MAC. [JHANEL] I think this
+ * is*/
+ /* clear on read, so you have to read both TX and RX path at same
+ * time.*/
+ drop = 0;
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MAC_PORT_PKT_COUNT) +
+ (i * T5_PORT_STRIDE)));
+
+ wtp->tx_xgm_xgm.sop[i] = ((value >> 24) & 0xFF); /*bit 24:31*/
+ wtp->tx_xgm_xgm.eop[i] = ((value >> 16) & 0xFF); /*bit 16:23*/
+ wtp->rx_xgm_xgm.sop[i] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->rx_xgm_xgm.eop[i] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ }
+
+ /* Get the MAC's output to the wire*/
+ drop = 0;
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MAC_PORT_AFRAMESTRANSMITTEDOK) +
+ (i * T5_PORT_STRIDE)));
+ wtp->xgm_wire.sop[i] = (value);
+ wtp->xgm_wire.eop[i] = (value); /* No EOP for XGMAC, so fake
+ it.*/
+ }
+
+ /*########################################################################*/
+ /*# RX PATH, starting from wire*/
+ /*########################################################################*/
+
+ /* Add up the wire input to the MAC*/
+ drop = 0;
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MAC_PORT_AFRAMESRECEIVEDOK) +
+ (i * T5_PORT_STRIDE)));
+
+ wtp->wire_xgm.sop[i] = (value);
+ wtp->wire_xgm.eop[i] = (value); /* No EOP for XGMAC, so fake
+ it.*/
+ }
+
+ /* Already read the rx_xgm_xgm when reading TX path.*/
+
+ /* Add up SOP/EOP's on all 8 MPS buffer channels*/
+ drop = 0;
+ for (i = 0; i < 8; i++) {
+ value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_IN0 + (i << 2)));
+
+ wtp->xgm_mps.sop[i] = ((value >> 8) & 0xFF); /*bits 8:15*/
+ wtp->xgm_mps.eop[i] = ((value >> 0) & 0xFF); /*bits 0:7*/
+ }
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap, (A_MPS_RX_CLS_DROP_CNT0 + (i << 2)));
+ /* typo in JHANEL's code.*/
+ drop += (value & 0xFFFF) + ((value >> 16) & 0xFFFF);
+ }
+ wtp->xgm_mps.cls_drop = drop & 0xFF;
+
+ /* Add up the overflow drops on all 4 ports.*/
+ drop = 0;
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
+ (i << 3)));
+ drop += value;
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
+ (i << 2)));
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L +
+ (i << 3)));
+ drop += value;
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
+ (i << 2)));
+
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
+ (i << 3)));
+ drop += value;
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
+ (i << 3)));
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L +
+ (i << 3)));
+ drop += value;
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
+ (i << 3)));
+
+ value = t4_read_reg(padap,
+ T5_PORT0_REG(A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES) +
+ (i * T5_PORT_STRIDE));
+ drop += value;
+ }
+ wtp->xgm_mps.drop = (drop & 0xFF);
+
+ /* Add up the MPS errors that should result in dropped packets*/
+ err = 0;
+ for (i = 0; i < 4; i++) {
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) +
+ (i * T5_PORT_STRIDE) + 4));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) +
+ (i * T5_PORT_STRIDE) + 4));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) +
+ (i * T5_PORT_STRIDE) + 4));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) +
+ (i * T5_PORT_STRIDE) + 4));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) +
+ (i * T5_PORT_STRIDE) + 4));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG((A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) +
+ (i * T5_PORT_STRIDE) + 4)));
+ }
+ wtp->xgm_mps.err = (err & 0xFF);
+
+ drop = 0;
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_OUT01 + (i << 2)));
+
+ wtp->mps_tp.sop[(i*2)] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->mps_tp.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->mps_tp.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31
+ */
+ wtp->mps_tp.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23
+ */
+ }
+ drop = ptp_mib->TP_MIB_TNL_CNG_DROP_0.value;
+ drop += ptp_mib->TP_MIB_TNL_CNG_DROP_1.value;
+ drop += ptp_mib->TP_MIB_TNL_CNG_DROP_2.value;
+ drop += ptp_mib->TP_MIB_TNL_CNG_DROP_3.value;
+ drop += ptp_mib->TP_MIB_OFD_CHN_DROP_0.value;
+ drop += ptp_mib->TP_MIB_OFD_CHN_DROP_1.value;
+ drop += ptp_mib->TP_MIB_OFD_CHN_DROP_2.value;
+ drop += ptp_mib->TP_MIB_OFD_CHN_DROP_3.value;
+ drop += ptp_mib->TP_MIB_FCOE_DROP_0.value;
+ drop += ptp_mib->TP_MIB_FCOE_DROP_1.value;
+ drop += ptp_mib->TP_MIB_FCOE_DROP_2.value;
+ drop += ptp_mib->TP_MIB_FCOE_DROP_3.value;
+ drop += ptp_mib->TP_MIB_OFD_VLN_DROP_0.value;
+ drop += ptp_mib->TP_MIB_OFD_VLN_DROP_1.value;
+ drop += ptp_mib->TP_MIB_OFD_VLN_DROP_2.value;
+ drop += ptp_mib->TP_MIB_OFD_VLN_DROP_3.value;
+ drop += ptp_mib->TP_MIB_USM_DROP.value;
+
+ wtp->mps_tp.drops = drop;
+
+ /* Get TP_DBG_CSIDE_TX registers*/
+ for (i = 0; i < 4; i++) {
+ t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i),
+ true);
+
+ wtp->tpcside_csw.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/
+ wtp->tpcside_csw.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/
+ wtp->tpcside_pm.sop[i] = ((value >> 20) & 0xF);/*bits 20:23*/
+ wtp->tpcside_pm.eop[i] = ((value >> 16) & 0xF);/*bits 16:19*/
+ wtp->tpcside_uturn.sop[i] = ((value >> 12) & 0xF);/*bits 12:15*/
+ wtp->tpcside_uturn.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/
+ wtp->tpcside_txcpl.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/
+ wtp->tpcside_txcpl.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/
+ }
+
+ /* TP to CPL_SWITCH*/
+ wtp->tp_csw.sop[0] = sge_dbg_reg->debug_CPLSW_TP_Rx_SOP0_cnt;
+ wtp->tp_csw.sop[1] = sge_dbg_reg->debug_CPLSW_TP_Rx_SOP1_cnt;
+
+ wtp->tp_csw.eop[0] = sge_dbg_reg->debug_CPLSW_TP_Rx_EOP0_cnt;
+ wtp->tp_csw.eop[1] = sge_dbg_reg->debug_CPLSW_TP_Rx_EOP1_cnt;
+
+ /* TP/CPL_SWITCH to SGE*/
+ wtp->csw_sge.sop[0] = sge_dbg_reg->debug_T_Rx_SOP0_cnt;
+ wtp->csw_sge.sop[1] = sge_dbg_reg->debug_T_Rx_SOP1_cnt;
+
+ wtp->csw_sge.eop[0] = sge_dbg_reg->debug_T_Rx_EOP0_cnt;
+ wtp->csw_sge.eop[1] = sge_dbg_reg->debug_T_Rx_EOP1_cnt;
+
+ wtp->sge_pcie.sop[0] = sge_dbg_reg->debug_PD_Req_SOP0_cnt;
+ wtp->sge_pcie.sop[1] = sge_dbg_reg->debug_PD_Req_SOP1_cnt;
+ wtp->sge_pcie.sop[2] = sge_dbg_reg->debug_PD_Req_SOP2_cnt;
+ wtp->sge_pcie.sop[3] = sge_dbg_reg->debug_PD_Req_SOP3_cnt;
+
+ wtp->sge_pcie.eop[0] = sge_dbg_reg->debug_PD_Req_EOP0_cnt;
+ wtp->sge_pcie.eop[1] = sge_dbg_reg->debug_PD_Req_EOP1_cnt;
+ wtp->sge_pcie.eop[2] = sge_dbg_reg->debug_PD_Req_EOP2_cnt;
+ wtp->sge_pcie.eop[3] = sge_dbg_reg->debug_PD_Req_EOP3_cnt;
+
+ wtp->sge_pcie_ints.sop[0] = sge_dbg_reg->debug_PD_Req_Int0_cnt;
+ wtp->sge_pcie_ints.sop[1] = sge_dbg_reg->debug_PD_Req_Int1_cnt;
+ wtp->sge_pcie_ints.sop[2] = sge_dbg_reg->debug_PD_Req_Int2_cnt;
+ wtp->sge_pcie_ints.sop[3] = sge_dbg_reg->debug_PD_Req_Int3_cnt;
+ /* NO EOP, so fake it.*/
+ wtp->sge_pcie_ints.eop[0] = sge_dbg_reg->debug_PD_Req_Int0_cnt;
+ wtp->sge_pcie_ints.eop[1] = sge_dbg_reg->debug_PD_Req_Int1_cnt;
+ wtp->sge_pcie_ints.eop[2] = sge_dbg_reg->debug_PD_Req_Int2_cnt;
+ wtp->sge_pcie_ints.eop[3] = sge_dbg_reg->debug_PD_Req_Int3_cnt;
+
+ /*Get PCIE DMA1 STAT2*/
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT2 + (i * 0x10));
+ wtp->pcie_dma1_stat2.sop[i] = ((value >> 8) & 0x0F);
+ wtp->pcie_dma1_stat2.eop[i] = ((value >> 8) & 0x0F);
+ wtp->pcie_dma1_stat2_core.sop[i] += value & 0x0F;
+ wtp->pcie_dma1_stat2_core.eop[i] += value & 0x0F;
+ }
+
+ /* Get mac porrx aFramesTransmittedok*/
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap, 0x30a88 + ((i * 4) << 12));
+ wtp->mac_porrx_aframestra_ok.sop[i] = (value & 0xFF);
+ wtp->mac_porrx_aframestra_ok.eop[i] = (value & 0xFF);
+ }
+
+ /*Get SGE debug data high index 7*/
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7);
+ wtp->sge_debug_data_high_indx7.sop[0] = ((value >> 4) & 0x0F);
+ wtp->sge_debug_data_high_indx7.eop[0] = ((value >> 0) & 0x0F);
+ wtp->sge_debug_data_high_indx7.sop[1] = ((value >> 12) & 0x0F);
+ wtp->sge_debug_data_high_indx7.eop[1] = ((value >> 8) & 0x0F);
+ wtp->sge_debug_data_high_indx7.sop[2] = ((value >> 20) & 0x0F);
+ wtp->sge_debug_data_high_indx7.eop[2] = ((value >> 16) & 0x0F);
+ wtp->sge_debug_data_high_indx7.sop[3] = ((value >> 28) & 0x0F);
+ wtp->sge_debug_data_high_indx7.eop[3] = ((value >> 24) & 0x0F);
+
+ /*Get SGE debug data high index 1*/
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_1);
+ wtp->sge_debug_data_high_indx1.sop[0] = ((value >> 20) & 0x0F);
+ wtp->sge_debug_data_high_indx1.eop[0] = ((value >> 16) & 0x0F);
+ wtp->sge_debug_data_high_indx1.sop[1] = ((value >> 28) & 0x0F);
+ wtp->sge_debug_data_high_indx1.eop[1] = ((value >> 24) & 0x0F);
+
+ /*Get TP debug CSIDE Tx registers*/
+ for (i = 0; i < 2; i++) {
+ t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_TX0 + i),
+ true);
+
+ wtp->utx_tpcside_tx.sop[i] = ((value >> 28) & 0xF);/*bits 28:31
+ */
+ wtp->utx_tpcside_tx.eop[i] = ((value >> 24) & 0xF);
+ }
+
+ /*Get SGE debug data high index 9*/
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9);
+ wtp->sge_debug_data_high_indx9.sop[0] = ((value >> 20) & 0x0F);
+ wtp->sge_debug_data_high_indx9.sop[1] = ((value >> 28) & 0x0F);
+ wtp->sge_debug_data_high_indx9.eop[0] = ((value >> 16) & 0x0F);
+ wtp->sge_debug_data_high_indx9.eop[1] = ((value >> 24) & 0x0F);
+ wtp->sge_work_req_pkt.sop[0] = ((value >> 4) & 0x0F);
+ wtp->sge_work_req_pkt.sop[1] = ((value >> 12) & 0x0F);
+
+ /*Get LE DB response count*/
+ value = t4_read_reg(padap, A_LE_DB_REQ_RSP_CNT);
+ wtp->le_db_rsp_cnt.sop = value & 0xF;
+ wtp->le_db_rsp_cnt.eop = (value >> 16) & 0xF;
+
+ /*Get TP debug Eside PKTx*/
+ for (i = 0; i < 4; i++) {
+ t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
+ true);
+
+ wtp->tp_dbg_eside_pktx.sop[i] = ((value >> 12) & 0xF);
+ wtp->tp_dbg_eside_pktx.eop[i] = ((value >> 8) & 0xF);
+ }
+
+ /* Get data responses from core to PCIE*/
+ value = t4_read_reg(padap, A_PCIE_DMAW_SOP_CNT);
+
+ wtp->pcie_core_dmaw.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->pcie_core_dmaw.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->pcie_core_dmaw.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
+ wtp->pcie_core_dmaw.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
+
+ value = t4_read_reg(padap, A_PCIE_DMAW_EOP_CNT);
+
+ wtp->pcie_core_dmaw.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->pcie_core_dmaw.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->pcie_core_dmaw.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
+ wtp->pcie_core_dmaw.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
+
+ value = t4_read_reg(padap, A_PCIE_DMAI_CNT);
+
+ wtp->pcie_core_dmai.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->pcie_core_dmai.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->pcie_core_dmai.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
+ wtp->pcie_core_dmai.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
+ /* no eop for interrups, just fake it.*/
+ wtp->pcie_core_dmai.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->pcie_core_dmai.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->pcie_core_dmai.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
+ wtp->pcie_core_dmai.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+static int
+t6_wtp_data(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ struct sge_debug_reg_data *sge_dbg_reg = NULL;
+ struct cudbg_buffer scratch_buff;
+ struct tp_mib_data *ptp_mib = NULL;
+ struct wtp_data *wtp;
+ u32 Sge_Dbg[32] = {0};
+ u32 value = 0;
+ u32 i = 0;
+ u32 drop = 0;
+ u32 err = 0;
+ u32 offset;
+ int rc = 0;
+
+ rc = get_scratch_buff(dbg_buff, sizeof(struct wtp_data), &scratch_buff);
+
+ if (rc)
+ goto err;
+
+ offset = scratch_buff.offset;
+ wtp = (struct wtp_data *)((char *)scratch_buff.data + offset);
+
+ read_sge_debug_data(pdbg_init, Sge_Dbg);
+ read_tp_mib_data(pdbg_init, &ptp_mib);
+
+ sge_dbg_reg = (struct sge_debug_reg_data *) &Sge_Dbg[0];
+
+ /*# TX PATH*/
+
+ /*PCIE CMD STAT2*/
+ value = t4_read_reg(padap, A_PCIE_T5_CMD_STAT2);
+ wtp->pcie_cmd_stat2.sop[0] = value & 0xFF;
+ wtp->pcie_cmd_stat2.eop[0] = value & 0xFF;
+
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7);
+ wtp->sge_pcie_cmd_req.sop[0] = ((value >> 20) & 0x0F);
+ wtp->sge_pcie_cmd_req.eop[0] = ((value >> 16) & 0x0F);
+ wtp->sge_pcie_cmd_req.sop[1] = ((value >> 28) & 0x0F);
+ wtp->sge_pcie_cmd_req.eop[1] = ((value >> 24) & 0x0F);
+
+ value = t4_read_reg(padap, A_PCIE_T5_CMD_STAT3);
+ wtp->pcie_cmd_stat3.sop[0] = value & 0xFF;
+ wtp->pcie_cmd_stat3.eop[0] = value & 0xFF;
+
+ /*Get command Resposes from PCIE to SGE*/
+ wtp->pcie_sge_cmd_rsp.sop[0] = sge_dbg_reg->debug_PC_Rsp_SOP0_cnt;
+ wtp->pcie_sge_cmd_rsp.eop[0] = sge_dbg_reg->debug_PC_Rsp_EOP0_cnt;
+ wtp->pcie_sge_cmd_rsp.sop[1] = sge_dbg_reg->debug_PC_Rsp_SOP1_cnt;
+ wtp->pcie_sge_cmd_rsp.eop[1] = sge_dbg_reg->debug_PC_Rsp_EOP0_cnt;
+
+ /* Get commands sent from SGE to CIM/uP*/
+ wtp->sge_cim.sop[0] = sge_dbg_reg->debug_CIM_SOP0_cnt;
+ wtp->sge_cim.sop[1] = sge_dbg_reg->debug_CIM_SOP1_cnt;
+
+ wtp->sge_cim.eop[0] = sge_dbg_reg->debug_CIM_EOP0_cnt;
+ wtp->sge_cim.eop[1] = sge_dbg_reg->debug_CIM_EOP1_cnt;
+
+ /*Get SGE debug data high index 9*/
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9);
+ wtp->sge_work_req_pkt.sop[0] = ((value >> 4) & 0x0F);
+ wtp->sge_work_req_pkt.eop[0] = ((value >> 0) & 0x0F);
+
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT2 + (i * 0x10));
+ wtp->pcie_dma1_stat2.sop[i] = ((value >> 8) & 0x0F);
+ wtp->pcie_dma1_stat2.eop[i] = ((value >> 8) & 0x0F);
+ wtp->pcie_dma1_stat2_core.sop[i] = value & 0x0F;
+ wtp->pcie_dma1_stat2_core.eop[i] = value & 0x0F;
+ }
+
+ /* Get DMA0 stats3*/
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT3 + (i * 0x10));
+ wtp->pcie_t5_dma_stat3.sop[i] = value & 0xFF;
+ wtp->pcie_t5_dma_stat3.eop[i] = ((value >> 16) & 0xFF);
+ }
+
+ /* Get ULP SE CNT CHx*/
+ for (i = 0; i < 4; i++) {
+ value = t4_read_reg(padap, A_ULP_TX_SE_CNT_CH0 + (i * 4));
+ wtp->ulp_se_cnt_chx.sop[i] = ((value >> 28) & 0x0F);
+ wtp->ulp_se_cnt_chx.eop[i] = ((value >> 24) & 0x0F);
+ }
+
+ /* Get TP_DBG_CSIDE registers*/
+ for (i = 0; i < 4; i++) {
+ t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i),
+ true);
+
+ wtp->utx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/
+ wtp->utx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/
+ wtp->tpcside_rxarb.sop[i] = ((value >> 12) & 0xF);/*bits 12:15*/
+ wtp->tpcside_rxarb.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/
+ }
+
+ for (i = 0; i < 4; i++) {
+ t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
+ true);
+
+
+ wtp->tpeside_mps.sop[i] = ((value >> 28) & 0xF); /*bits 28:31*/
+ wtp->tpeside_mps.eop[i] = ((value >> 24) & 0xF); /*bits 24:27*/
+ }
+
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_TP01 + (i << 2)));
+ wtp->tp_mps.sop[(i*2)] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->tp_mps.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->tp_mps.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31
+ */
+ wtp->tp_mps.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23
+ */
+ }
+
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_MAC01 + (i << 2)));
+ wtp->mps_xgm.sop[(i*2)] = ((value >> 8) & 0xFF);/*bit 8:15*/
+ wtp->mps_xgm.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->mps_xgm.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31
+ */
+ wtp->mps_xgm.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23
+ */
+ }
+
+ /* Get MAC PORTx PKT COUNT*/
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, 0x3081c + ((i * 4) << 12));
+ wtp->mac_portx_pkt_count.sop[i] = ((value >> 24) & 0xFF);
+ wtp->mac_portx_pkt_count.eop[i] = ((value >> 16) & 0xFF);
+ wtp->mac_porrx_pkt_count.sop[i] = ((value >> 8) & 0xFF);
+ wtp->mac_porrx_pkt_count.eop[i] = ((value >> 0) & 0xFF);
+ }
+
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, 0x30f20 + ((i * 4) << 12));
+ wtp->mac_portx_aframestra_ok.sop[i] = value & 0xff;
+ wtp->mac_portx_aframestra_ok.eop[i] = value & 0xff;
+ }
+
+ /*MAC_PORT_MTIP_1G10G_TX_etherStatsPkts*/
+
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, 0x30f60 + ((i * 4) << 12));
+ wtp->mac_portx_etherstatspkts.sop[i] = value & 0xff;
+ wtp->mac_portx_etherstatspkts.eop[i] = value & 0xff;
+ }
+
+ /*RX path*/
+
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7);
+ wtp->sge_debug_data_high_indx7.sop[0] = ((value >> 4) & 0x0F);
+ wtp->sge_debug_data_high_indx7.eop[0] = ((value >> 0) & 0x0F);
+ wtp->sge_debug_data_high_indx7.sop[1] = ((value >> 12) & 0x0F);
+ wtp->sge_debug_data_high_indx7.eop[1] = ((value >> 8) & 0x0F);
+
+ /*Get SGE debug data high index 1*/
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_1);
+ wtp->sge_debug_data_high_indx1.sop[0] = ((value >> 20) & 0x0F);
+ wtp->sge_debug_data_high_indx1.eop[0] = ((value >> 16) & 0x0F);
+ wtp->sge_debug_data_high_indx1.sop[1] = ((value >> 28) & 0x0F);
+ wtp->sge_debug_data_high_indx1.eop[1] = ((value >> 24) & 0x0F);
+
+ value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9);
+ wtp->sge_debug_data_high_indx9.sop[0] = ((value >> 20) & 0x0F);
+ wtp->sge_debug_data_high_indx9.sop[1] = ((value >> 28) & 0x0F);
+
+ wtp->sge_debug_data_high_indx9.eop[0] = ((value >> 16) & 0x0F);
+ wtp->sge_debug_data_high_indx9.eop[1] = ((value >> 24) & 0x0F);
+
+ for (i = 0; i < 2; i++) {
+ t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_TX0 + i),
+ true);
+
+ wtp->utx_tpcside_tx.sop[i] = ((value >> 28) & 0xF);/*bits 28:31
+ */
+ wtp->utx_tpcside_tx.eop[i] = ((value >> 24) & 0xF);
+ }
+
+ /*ULP_RX input/output*/
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, (A_ULP_RX_SE_CNT_CH0 + (i*4)));
+
+ wtp->pmrx_ulprx.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/
+ wtp->pmrx_ulprx.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/
+ wtp->ulprx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/
+ wtp->ulprx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/
+ }
+
+ /*Get LE DB response count*/
+ value = t4_read_reg(padap, A_LE_DB_REQ_RSP_CNT);
+ wtp->le_db_rsp_cnt.sop = value & 0xF;
+ wtp->le_db_rsp_cnt.eop = (value >> 16) & 0xF;
+
+ /*Get TP debug Eside PKTx*/
+ for (i = 0; i < 4; i++) {
+ t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
+ true);
+
+ wtp->tp_dbg_eside_pktx.sop[i] = ((value >> 12) & 0xF);
+ wtp->tp_dbg_eside_pktx.eop[i] = ((value >> 8) & 0xF);
+ }
+
+ drop = 0;
+ /*MPS_RX_SE_CNT_OUT01*/
+ value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_OUT01 + (i << 2)));
+ wtp->mps_tp.sop[0] = ((value >> 8) & 0xFF); /*bit 8:15*/
+ wtp->mps_tp.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
+ wtp->mps_tp.sop[1] = ((value >> 24) & 0xFF); /*bit 24:31*/
+ wtp->mps_tp.eop[1] = ((value >> 16) & 0xFF); /*bit 16:23*/
+
+ drop = ptp_mib->TP_MIB_TNL_CNG_DROP_0.value;
+ drop += ptp_mib->TP_MIB_TNL_CNG_DROP_1.value;
+ drop += ptp_mib->TP_MIB_OFD_CHN_DROP_0.value;
+ drop += ptp_mib->TP_MIB_OFD_CHN_DROP_1.value;
+ drop += ptp_mib->TP_MIB_FCOE_DROP_0.value;
+ drop += ptp_mib->TP_MIB_FCOE_DROP_1.value;
+ drop += ptp_mib->TP_MIB_OFD_VLN_DROP_0.value;
+ drop += ptp_mib->TP_MIB_OFD_VLN_DROP_1.value;
+ drop += ptp_mib->TP_MIB_USM_DROP.value;
+
+ wtp->mps_tp.drops = drop;
+
+ drop = 0;
+ for (i = 0; i < 8; i++) {
+ value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_IN0 + (i << 2)));
+
+ wtp->xgm_mps.sop[i] = ((value >> 8) & 0xFF); /*bits 8:15*/
+ wtp->xgm_mps.eop[i] = ((value >> 0) & 0xFF); /*bits 0:7*/
+ }
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, (A_MPS_RX_CLS_DROP_CNT0 + (i << 2)));
+ drop += (value & 0xFFFF) + ((value >> 16) & 0xFFFF);
+ }
+ wtp->xgm_mps.cls_drop = drop & 0xFF;
+
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, 0x30e20 + ((i * 4) << 12));
+ wtp->mac_porrx_aframestra_ok.sop[i] = value & 0xff;
+ wtp->mac_porrx_aframestra_ok.eop[i] = value & 0xff;
+ }
+
+ /*MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap, 0x30e60 + ((i * 4) << 12));
+ wtp->mac_porrx_etherstatspkts.sop[i] = value & 0xff;
+ wtp->mac_porrx_etherstatspkts.eop[i] = value & 0xff;
+ }
+
+ wtp->sge_pcie_ints.sop[0] = sge_dbg_reg->debug_PD_Req_Int0_cnt;
+ wtp->sge_pcie_ints.sop[1] = sge_dbg_reg->debug_PD_Req_Int1_cnt;
+ wtp->sge_pcie_ints.sop[2] = sge_dbg_reg->debug_PD_Req_Int2_cnt;
+ wtp->sge_pcie_ints.sop[3] = sge_dbg_reg->debug_PD_Req_Int3_cnt;
+
+ /* Add up the overflow drops on all 4 ports.*/
+ drop = 0;
+ for (i = 0; i < 2; i++) {
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
+ (i << 3)));
+ drop += value;
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
+ (i << 2)));
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L +
+ (i << 3)));
+ drop += value;
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
+ (i << 2)));
+
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
+ (i << 3)));
+ drop += value;
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
+ (i << 3)));
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L +
+ (i << 3)));
+ drop += value;
+ value = t4_read_reg(padap,
+ (A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
+ (i << 3)));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES) +
+ (i * T5_PORT_STRIDE)));
+ drop += value;
+ }
+ wtp->xgm_mps.drop = (drop & 0xFF);
+
+ /* Add up the MPS errors that should result in dropped packets*/
+ err = 0;
+ for (i = 0; i < 2; i++) {
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) +
+ (i * T5_PORT_STRIDE) + 4));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) +
+ (i * T5_PORT_STRIDE) + 4));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) +
+ (i * T5_PORT_STRIDE) + 4));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) +
+ (i * T5_PORT_STRIDE) + 4));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) +
+ (i * T5_PORT_STRIDE) + 4));
+
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) +
+ (i * T5_PORT_STRIDE)));
+ err += value;
+ value = t4_read_reg(padap,
+ (T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) +
+ (i * T5_PORT_STRIDE) + 4));
+ }
+ wtp->xgm_mps.err = (err & 0xFF);
+
+ rc = write_compression_hdr(&scratch_buff, dbg_buff);
+
+ if (rc)
+ goto err1;
+
+ rc = compress_buff(&scratch_buff, dbg_buff);
+
+err1:
+ release_scratch_buff(&scratch_buff, dbg_buff);
+err:
+ return rc;
+}
+
+int
+collect_wtp_data(struct cudbg_init *pdbg_init,
+ struct cudbg_buffer *dbg_buff,
+ struct cudbg_error *cudbg_err)
+{
+ struct adapter *padap = pdbg_init->adap;
+ int rc = -1;
+
+ if (is_t5(padap->params.chip))
+ rc = t5_wtp_data(pdbg_init, dbg_buff, cudbg_err);
+ else if (is_t6(padap->params.chip))
+ rc = t6_wtp_data(pdbg_init, dbg_buff, cudbg_err);
+
+ return rc;
+}
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/fastlz.c b/usr/src/uts/common/io/cxgbe/t4nex/fastlz.c
new file mode 100644
index 0000000000..a45d54dc73
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/fastlz.c
@@ -0,0 +1,572 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ FastLZ - lightning-fast lossless compression library
+
+ Copyright (C) 2007 Ariya Hidayat (ariya@kde.org)
+ Copyright (C) 2006 Ariya Hidayat (ariya@kde.org)
+ Copyright (C) 2005 Ariya Hidayat (ariya@kde.org)
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+ */
+#include "osdep.h"
+#include "fastlz.h"
+
+#if !defined(FASTLZ__COMPRESSOR) && !defined(FASTLZ_DECOMPRESSOR)
+
+/*
+ * Always check for bound when decompressing.
+ * Generally it is best to leave it defined.
+ */
+#define FASTLZ_SAFE
+
+#if defined(WIN32) || defined(__NT__) || defined(_WIN32) || defined(__WIN32__)
+#if defined(_MSC_VER) || defined(__GNUC__)
+/* #include <windows.h> */
+#pragma warning(disable : 4242)
+#pragma warning(disable : 4244)
+#endif
+#endif
+
+/*
+ * Give hints to the compiler for branch prediction optimization.
+ */
+#if defined(__GNUC__) && (__GNUC__ > 2)
+#define FASTLZ_EXPECT_CONDITIONAL(c) (__builtin_expect((c), 1))
+#define FASTLZ_UNEXPECT_CONDITIONAL(c) (__builtin_expect((c), 0))
+#else
+#define FASTLZ_EXPECT_CONDITIONAL(c) (c)
+#define FASTLZ_UNEXPECT_CONDITIONAL(c) (c)
+#endif
+
+/*
+ * Use inlined functions for supported systems.
+ */
+#if defined(__GNUC__) || defined(__DMC__) || defined(__POCC__) ||\
+ defined(__WATCOMC__) || defined(__SUNPRO_C)
+#define FASTLZ_INLINE inline
+#elif defined(__BORLANDC__) || defined(_MSC_VER) || defined(__LCC__)
+#define FASTLZ_INLINE __inline
+#else
+#define FASTLZ_INLINE
+#endif
+
+/*
+ * Prevent accessing more than 8-bit at once, except on x86 architectures.
+ */
+#if !defined(FASTLZ_STRICT_ALIGN)
+#define FASTLZ_STRICT_ALIGN
+#if defined(__i386__) || defined(__386) /* GNU C, Sun Studio */
+#undef FASTLZ_STRICT_ALIGN
+#elif defined(__i486__) || defined(__i586__) || defined(__i686__) /* GNU C */
+#undef FASTLZ_STRICT_ALIGN
+#elif defined(_M_IX86) /* Intel, MSVC */
+#undef FASTLZ_STRICT_ALIGN
+#elif defined(__386)
+#undef FASTLZ_STRICT_ALIGN
+#elif defined(_X86_) /* MinGW */
+#undef FASTLZ_STRICT_ALIGN
+#elif defined(__I86__) /* Digital Mars */
+#undef FASTLZ_STRICT_ALIGN
+#endif
+#endif
+
+/*
+ * FIXME: use preprocessor magic to set this on different platforms!
+ */
+
+#define MAX_COPY 32
+#define MAX_LEN 264 /* 256 + 8 */
+#define MAX_DISTANCE 8192
+
+#if !defined(FASTLZ_STRICT_ALIGN)
+#define FASTLZ_READU16(p) (*((const unsigned short *)(p)))
+#else
+#define FASTLZ_READU16(p) ((p)[0] | (p)[1]<<8)
+#endif
+
+#define HASH_LOG 13
+#define HASH_SIZE (1 << HASH_LOG)
+#define HASH_MASK (HASH_SIZE - 1)
+#define HASH_FUNCTION(v, p) {\
+ v = FASTLZ_READU16(p);\
+ v ^= FASTLZ_READU16(p + 1)^\
+ (v>>(16 - HASH_LOG));\
+ v &= HASH_MASK;\
+ }
+
+#undef FASTLZ_LEVEL
+#define FASTLZ_LEVEL 1
+
+#undef FASTLZ_COMPRESSOR
+#undef FASTLZ_DECOMPRESSOR
+#define FASTLZ_COMPRESSOR fastlz1_compress
+#define FASTLZ_DECOMPRESSOR fastlz1_decompress
+static int FASTLZ_COMPRESSOR(const void *input, int length,
+ void *output);
+static int FASTLZ_DECOMPRESSOR(const void *input, int length,
+ void *output, int maxout);
+#include "fastlz.c"
+
+#undef FASTLZ_LEVEL
+#define FASTLZ_LEVEL 2
+
+#undef MAX_DISTANCE
+#define MAX_DISTANCE 8191
+#define MAX_FARDISTANCE (65535 + MAX_DISTANCE - 1)
+
+#undef FASTLZ_COMPRESSOR
+#undef FASTLZ_DECOMPRESSOR
+#define FASTLZ_COMPRESSOR fastlz2_compress
+#define FASTLZ_DECOMPRESSOR fastlz2_decompress
+static int FASTLZ_COMPRESSOR(const void *input, int length,
+ void *output);
+static int FASTLZ_DECOMPRESSOR(const void *input, int length,
+ void *output, int maxout);
+#include "fastlz.c"
+
+int
+fastlz_compress(const void *input, int length, void *output)
+{
+ /* for short block, choose fastlz1 */
+ if (length < 65536)
+ return fastlz1_compress(input, length, output);
+
+ /* else... */
+ return fastlz2_compress(input, length, output);
+}
+
+int
+fastlz_decompress(const void *input, int length, void *output, int maxout)
+{
+ /* magic identifier for compression level */
+ int level = ((*(const unsigned char *)input) >> 5) + 1;
+
+ if (level == 1)
+ return fastlz1_decompress(input, length, output, maxout);
+ if (level == 2)
+ return fastlz2_decompress(input, length, output, maxout);
+
+ /* unknown level, trigger error */
+ return 0;
+}
+
+int
+fastlz_compress_level(int level, const void *input, int length,
+ void *output)
+{
+ if (level == 1)
+ return fastlz1_compress(input, length, output);
+ if (level == 2)
+ return fastlz2_compress(input, length, output);
+
+ return 0;
+}
+
+#else /* !defined(FASTLZ_COMPRESSOR) && !defined(FASTLZ_DECOMPRESSOR) */
+
+
+static int
+FASTLZ_COMPRESSOR(const void *input, int length,
+ void *output)
+{
+ const unsigned char *ip = (const unsigned char *) input;
+ const unsigned char *ip_bound = ip + length - 2;
+ const unsigned char *ip_limit = ip + length - 12;
+ unsigned char *op = (unsigned char *) output;
+ static const unsigned char *g_htab[HASH_SIZE];
+
+ const unsigned char **htab = g_htab;
+ const unsigned char **hslot;
+ unsigned int hval;
+
+ unsigned int copy;
+
+ /* sanity check */
+ if (FASTLZ_UNEXPECT_CONDITIONAL(length < 4)) {
+ if (length) {
+ /* create literal copy only */
+ *op++ = length - 1;
+ ip_bound++;
+ while (ip <= ip_bound)
+ *op++ = *ip++;
+ return length + 1;
+ } else
+ return 0;
+ }
+
+ /* initializes hash table */
+ for (hslot = htab; hslot < htab + HASH_SIZE; hslot++)
+ *hslot = ip;
+
+ /* we start with literal copy */
+ copy = 2;
+ *op++ = MAX_COPY - 1;
+ *op++ = *ip++;
+ *op++ = *ip++;
+
+ /* main loop */
+ while (FASTLZ_EXPECT_CONDITIONAL(ip < ip_limit)) {
+ const unsigned char *ref;
+ unsigned int distance;
+
+ /* minimum match length */
+ unsigned int len = 3;
+
+ /* comparison starting-point */
+ const unsigned char *anchor = ip;
+
+ /* check for a run */
+#if FASTLZ_LEVEL == 2
+ if (ip[0] == ip[-1] &&
+ FASTLZ_READU16(ip - 1) == FASTLZ_READU16(ip + 1)) {
+ distance = 1;
+ ip += 3;
+ ref = anchor - 1 + 3;
+ goto match;
+ }
+#endif
+
+ /* find potential match */
+ HASH_FUNCTION(hval, ip);
+ hslot = htab + hval;
+ ref = htab[hval];
+
+ /* calculate distance to the match */
+ distance = anchor - ref;
+
+ /* update hash table */
+ *hslot = anchor;
+
+ if (!ref)
+ goto literal;
+ /* is this a match? check the first 3 bytes */
+ if (distance == 0 ||
+#if FASTLZ_LEVEL == 1
+ (distance >= MAX_DISTANCE) ||
+#else
+ (distance >= MAX_FARDISTANCE) ||
+#endif
+ *ref++ != *ip++ || *ref++ != *ip++ ||
+ *ref++ != *ip++)
+ goto literal;
+
+#if FASTLZ_LEVEL == 2
+ /* far, needs at least 5-byte match */
+ if (distance >= MAX_DISTANCE) {
+ if (*ip++ != *ref++ || *ip++ != *ref++)
+ goto literal;
+ len += 2;
+ }
+
+match:
+#endif
+
+ /* last matched byte */
+ ip = anchor + len;
+
+ /* distance is biased */
+ distance--;
+
+ if (!distance) {
+ /* zero distance means a run */
+ unsigned char x = ip[-1];
+ while (ip < ip_bound)
+ if (*ref++ != x)
+ break;
+ else
+ ip++;
+ } else
+ for (;;) {
+ /* safe because the outer check
+ * against ip limit */
+ if (*ref++ != *ip++)
+ break;
+ if (*ref++ != *ip++)
+ break;
+ if (*ref++ != *ip++)
+ break;
+ if (*ref++ != *ip++)
+ break;
+ if (*ref++ != *ip++)
+ break;
+ if (*ref++ != *ip++)
+ break;
+ if (*ref++ != *ip++)
+ break;
+ if (*ref++ != *ip++)
+ break;
+ while (ip < ip_bound)
+ if (*ref++ != *ip++)
+ break;
+ break;
+ }
+
+ /* if we have copied something, adjust the copy count */
+ if (copy)
+ /* copy is biased, '0' means 1 byte copy */
+ *(op - copy - 1) = copy - 1;
+ else
+ /* back, to overwrite the copy count */
+ op--;
+
+ /* reset literal counter */
+ copy = 0;
+
+ /* length is biased, '1' means a match of 3 bytes */
+ ip -= 3;
+ len = ip - anchor;
+
+ /* encode the match */
+#if FASTLZ_LEVEL == 2
+ if (distance < MAX_DISTANCE) {
+ if (len < 7) {
+ *op++ = (len << 5) + (distance >> 8);
+ *op++ = (distance & 255);
+ } else {
+ *op++ = (7 << 5) + (distance >> 8);
+ for (len -= 7; len >= 255; len -= 255)
+ *op++ = 255;
+ *op++ = len;
+ *op++ = (distance & 255);
+ }
+ } else {
+ /* far away, but not yet in the another galaxy... */
+ if (len < 7) {
+ distance -= MAX_DISTANCE;
+ *op++ = (len << 5) + 31;
+ *op++ = 255;
+ *op++ = distance >> 8;
+ *op++ = distance & 255;
+ } else {
+ distance -= MAX_DISTANCE;
+ *op++ = (7 << 5) + 31;
+ for (len -= 7; len >= 255; len -= 255)
+ *op++ = 255;
+ *op++ = len;
+ *op++ = 255;
+ *op++ = distance >> 8;
+ *op++ = distance & 255;
+ }
+ }
+#else
+
+ if (FASTLZ_UNEXPECT_CONDITIONAL(len > MAX_LEN - 2))
+ while (len > MAX_LEN - 2) {
+ *op++ = (7 << 5) + (distance >> 8);
+ *op++ = MAX_LEN - 2 - 7 - 2;
+ *op++ = (distance & 255);
+ len -= MAX_LEN - 2;
+ }
+
+ if (len < 7) {
+ *op++ = (len << 5) + (distance >> 8);
+ *op++ = (distance & 255);
+ } else {
+ *op++ = (7 << 5) + (distance >> 8);
+ *op++ = len - 7;
+ *op++ = (distance & 255);
+ }
+#endif
+
+ /* update the hash at match boundary */
+ HASH_FUNCTION(hval, ip);
+ htab[hval] = ip++;
+ HASH_FUNCTION(hval, ip);
+ htab[hval] = ip++;
+
+ /* assuming literal copy */
+ *op++ = MAX_COPY - 1;
+
+ continue;
+
+literal:
+ *op++ = *anchor++;
+ ip = anchor;
+ copy++;
+ if (FASTLZ_UNEXPECT_CONDITIONAL(copy == MAX_COPY)) {
+ copy = 0;
+ *op++ = MAX_COPY - 1;
+ }
+ }
+
+ /* left-over as literal copy */
+ ip_bound++;
+ while (ip <= ip_bound) {
+ *op++ = *ip++;
+ copy++;
+ if (copy == MAX_COPY) {
+ copy = 0;
+ *op++ = MAX_COPY - 1;
+ }
+ }
+
+ /* if we have copied something, adjust the copy length */
+ if (copy)
+ *(op - copy - 1) = copy - 1;
+ else
+ op--;
+
+#if FASTLZ_LEVEL == 2
+ /* marker for fastlz2 */
+ *(unsigned char *)output |= (1 << 5);
+#endif
+
+ return op - (unsigned char *)output;
+}
+
+static int
+FASTLZ_DECOMPRESSOR(const void *input, int length,
+ void *output, int maxout)
+{
+ const unsigned char *ip = (const unsigned char *) input;
+ const unsigned char *ip_limit = ip + length;
+ unsigned char *op = (unsigned char *) output;
+ unsigned char *op_limit = op + maxout;
+ unsigned int ctrl = (*ip++) & 31;
+ int loop = 1;
+
+ do {
+ const unsigned char *ref = op;
+#ifndef __CHECKER__
+ unsigned int len = ctrl >> 5;
+#endif
+ unsigned int ofs = (ctrl & 31) << 8;
+
+ if (ctrl >= 32) {
+#if FASTLZ_LEVEL == 2
+ unsigned char code;
+#endif
+ len--;
+ ref -= ofs;
+#ifndef __CHECKER__
+ if (len == 7 - 1)
+#if FASTLZ_LEVEL == 1
+ len += *ip++;
+ ref -= *ip++;
+#else
+ do {
+ code = *ip++;
+ len += code;
+ } while (code == 255);
+ code = *ip++;
+ ref -= code;
+
+ /* match from 16-bit distance */
+ if (FASTLZ_UNEXPECT_CONDITIONAL(code == 255))
+ if (FASTLZ_EXPECT_CONDITIONAL(ofs ==
+ (31 << 8))) {
+ ofs = (*ip++) << 8;
+ ofs += *ip++;
+ ref = op - ofs - MAX_DISTANCE;
+ }
+#endif
+
+#ifdef FASTLZ_SAFE
+ if (FASTLZ_UNEXPECT_CONDITIONAL(op + len + 3 >
+ op_limit))
+ return 0;
+
+ if (FASTLZ_UNEXPECT_CONDITIONAL(ref - 1 <
+ (unsigned char *)output)
+ )
+ return 0;
+#endif
+
+ if (FASTLZ_EXPECT_CONDITIONAL(ip < ip_limit))
+ ctrl = *ip++;
+ else
+ loop = 0;
+
+ if (ref == op) {
+ /* optimize copy for a run */
+ unsigned char b = ref[-1];
+ *op++ = b;
+ *op++ = b;
+ *op++ = b;
+ for (; len; --len)
+ *op++ = b;
+ } else {
+#if !defined(FASTLZ_STRICT_ALIGN)
+ const unsigned short *p;
+ unsigned short *q;
+#endif
+ /* copy from reference */
+ ref--;
+ *op++ = *ref++;
+ *op++ = *ref++;
+ *op++ = *ref++;
+
+#if !defined(FASTLZ_STRICT_ALIGN)
+ /* copy a byte, so that now it's word aligned */
+ if (len & 1) {
+ *op++ = *ref++;
+ len--;
+ }
+
+ /* copy 16-bit at once */
+ q = (unsigned short *) op;
+ op += len;
+ p = (const unsigned short *) ref;
+ for (len >>= 1; len > 4; len -= 4) {
+ *q++ = *p++;
+ *q++ = *p++;
+ *q++ = *p++;
+ *q++ = *p++;
+ }
+ for (; len; --len)
+ *q++ = *p++;
+#else
+ for (; len; --len)
+ *op++ = *ref++;
+#endif
+ }
+#endif /* __CHECKER__ */
+ } else {
+ ctrl++;
+#ifdef FASTLZ_SAFE
+ if (FASTLZ_UNEXPECT_CONDITIONAL(op + ctrl > op_limit))
+ return 0;
+ if (FASTLZ_UNEXPECT_CONDITIONAL(ip + ctrl > ip_limit))
+ return 0;
+#endif
+
+ *op++ = *ip++;
+ for (--ctrl; ctrl; ctrl--)
+ *op++ = *ip++;
+
+ loop = FASTLZ_EXPECT_CONDITIONAL(ip < ip_limit);
+ if (loop)
+ ctrl = *ip++;
+ }
+ } while (FASTLZ_EXPECT_CONDITIONAL(loop));
+
+ return op - (unsigned char *)output;
+}
+
+#endif /* !defined(FASTLZ_COMPRESSOR) && !defined(FASTLZ_DECOMPRESSOR) */
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/fastlz.h b/usr/src/uts/common/io/cxgbe/t4nex/fastlz.h
new file mode 100644
index 0000000000..7a0a726895
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/fastlz.h
@@ -0,0 +1,73 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ FastLZ - lightning-fast lossless compression library
+
+ Copyright (C) 2007 Ariya Hidayat (ariya@kde.org)
+ Copyright (C) 2006 Ariya Hidayat (ariya@kde.org)
+ Copyright (C) 2005 Ariya Hidayat (ariya@kde.org)
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+
+ $FreeBSD$
+ */
+#ifndef FASTLZ_H
+#define FASTLZ_H
+
+#define FASTLZ_VERSION 0x000100
+
+#define FASTLZ_VERSION_MAJOR 0
+#define FASTLZ_VERSION_MINOR 0
+#define FASTLZ_VERSION_REVISION 0
+
+#define FASTLZ_VERSION_STRING "0.1.0"
+
+struct cudbg_buffer;
+
+int fastlz_compress(const void *input, int length, void *output);
+int fastlz_compress_level(int level, const void *input, int length,
+ void *output);
+int fastlz_decompress(const void *input, int length, void *output, int maxout);
+
+/* prototypes */
+
+int write_magic(struct cudbg_buffer *);
+int detect_magic(struct cudbg_buffer *);
+
+int write_to_buf(void *, u32, u32 *, void *, u32);
+int read_from_buf(void *, u32, u32 *, void *, u32);
+
+int write_chunk_header(struct cudbg_buffer *, int, int, unsigned long,
+ unsigned long, unsigned long);
+
+int read_chunk_header(struct cudbg_buffer *, int* , int*, unsigned long*,
+ unsigned long*, unsigned long*);
+
+unsigned long block_compress(const unsigned char *, unsigned long length,
+ unsigned char *);
+#endif /* FASTLZ_H */
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/fastlz_api.c b/usr/src/uts/common/io/cxgbe/t4nex/fastlz_api.c
new file mode 100644
index 0000000000..8ae092b9ca
--- /dev/null
+++ b/usr/src/uts/common/io/cxgbe/t4nex/fastlz_api.c
@@ -0,0 +1,556 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source. A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ FastLZ - lightning-fast lossless compression library
+
+ Copyright (C) 2007 Ariya Hidayat (ariya@kde.org)
+ Copyright (C) 2006 Ariya Hidayat (ariya@kde.org)
+ Copyright (C) 2005 Ariya Hidayat (ariya@kde.org)
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.
+ */
+
+#include "osdep.h"
+#include "cudbg.h"
+#include "cudbg_lib_common.h"
+#include "fastlz.h"
+
+#ifndef _KERNEL
+#include <string.h>
+#endif
+
+static unsigned char sixpack_magic[8] = {137, '6', 'P', 'K', 13, 10, 26, 10};
+
+#define CUDBG_BLOCK_SIZE (63*1024)
+#define CUDBG_CHUNK_BUF_LEN 16
+#define CUDBG_MIN_COMPR_LEN 32 /*min data length for applying compression*/
+
+/* for Adler-32 checksum algorithm, see RFC 1950 Section 8.2 */
+
+#define ADLER32_BASE 65521
+
+static unsigned long
+update_adler32(unsigned long checksum,
+ const void *buf, int len)
+{
+ const unsigned char *ptr = (const unsigned char *)buf;
+ unsigned long s1 = checksum & 0xffff;
+ unsigned long s2 = (checksum >> 16) & 0xffff;
+
+ while (len > 0) {
+ unsigned k = len < 5552 ? len : 5552;
+ len -= k;
+
+ while (k >= 8) {
+ s1 += *ptr++; s2 += s1;
+ s1 += *ptr++; s2 += s1;
+ s1 += *ptr++; s2 += s1;
+ s1 += *ptr++; s2 += s1;
+ s1 += *ptr++; s2 += s1;
+ s1 += *ptr++; s2 += s1;
+ s1 += *ptr++; s2 += s1;
+ s1 += *ptr++; s2 += s1;
+ k -= 8;
+ }
+
+ while (k-- > 0) {
+ s1 += *ptr++; s2 += s1;
+ }
+ s1 = s1 % ADLER32_BASE;
+ s2 = s2 % ADLER32_BASE;
+ }
+ return (s2 << 16) + s1;
+}
+
+int
+write_magic(struct cudbg_buffer *_out_buff)
+{
+ int rc;
+
+ rc = write_to_buf(_out_buff->data, _out_buff->size, &_out_buff->offset,
+ sixpack_magic, 8);
+
+ return rc;
+}
+
+int
+write_to_buf(void *out_buf, u32 out_buf_size, u32 *offset, void *in_buf,
+ u32 in_buf_size)
+{
+ int rc = 0;
+
+ if (*offset >= out_buf_size) {
+ rc = CUDBG_STATUS_OUTBUFF_OVERFLOW;
+ goto err;
+ }
+
+ memcpy((char *)out_buf + *offset, in_buf, in_buf_size);
+ *offset = *offset + in_buf_size;
+
+err:
+ return rc;
+}
+
+int
+read_from_buf(void *in_buf, u32 in_buf_size, u32 *offset, void *out_buf,
+ u32 out_buf_size)
+{
+ if (in_buf_size - *offset < out_buf_size)
+ return 0;
+
+ memcpy((char *)out_buf, (char *)in_buf + *offset, out_buf_size);
+ *offset = *offset + out_buf_size;
+ return out_buf_size;
+}
+
+int
+write_chunk_header(struct cudbg_buffer *_outbuf, int id, int options,
+ unsigned long size, unsigned long checksum,
+ unsigned long extra)
+{
+ unsigned char buffer[CUDBG_CHUNK_BUF_LEN];
+ int rc = 0;
+
+ buffer[0] = id & 255;
+ buffer[1] = (unsigned char)(id >> 8);
+ buffer[2] = options & 255;
+ buffer[3] = (unsigned char)(options >> 8);
+ buffer[4] = size & 255;
+ buffer[5] = (size >> 8) & 255;
+ buffer[6] = (size >> 16) & 255;
+ buffer[7] = (size >> 24) & 255;
+ buffer[8] = checksum & 255;
+ buffer[9] = (checksum >> 8) & 255;
+ buffer[10] = (checksum >> 16) & 255;
+ buffer[11] = (checksum >> 24) & 255;
+ buffer[12] = extra & 255;
+ buffer[13] = (extra >> 8) & 255;
+ buffer[14] = (extra >> 16) & 255;
+ buffer[15] = (extra >> 24) & 255;
+
+ rc = write_to_buf(_outbuf->data, _outbuf->size, &_outbuf->offset,
+ buffer, 16);
+
+ return rc;
+}
+
+int
+write_compression_hdr(struct cudbg_buffer *pin_buff,
+ struct cudbg_buffer *pout_buff)
+{
+ struct cudbg_buffer tmp_buffer;
+ unsigned long fsize = pin_buff->size;
+ unsigned char *buffer;
+ unsigned long checksum;
+ int rc;
+ char *shown_name = "abc";
+
+ /* Always release inner scratch buffer, before releasing outer. */
+ rc = get_scratch_buff(pout_buff, 10, &tmp_buffer);
+
+ if (rc)
+ goto err;
+
+ buffer = (unsigned char *)tmp_buffer.data;
+
+ rc = write_magic(pout_buff);
+
+ if (rc)
+ goto err1;
+
+ /* chunk for File Entry */
+ buffer[0] = fsize & 255;
+ buffer[1] = (fsize >> 8) & 255;
+ buffer[2] = (fsize >> 16) & 255;
+ buffer[3] = (fsize >> 24) & 255;
+ buffer[4] = 0;
+ buffer[5] = 0;
+ buffer[6] = 0;
+ buffer[7] = 0;
+ buffer[8] = (strlen(shown_name)+1) & 255;
+ buffer[9] = (unsigned char)((strlen(shown_name)+1) >> 8);
+ checksum = 1L;
+ checksum = update_adler32(checksum, buffer, 10);
+ checksum = update_adler32(checksum, shown_name,
+ (int)strlen(shown_name)+1);
+
+ rc = write_chunk_header(pout_buff, 1, 0,
+ 10+(unsigned long)strlen(shown_name)+1,
+ checksum, 0);
+
+ if (rc)
+ goto err1;
+
+ rc = write_to_buf(pout_buff->data, pout_buff->size,
+ &(pout_buff->offset), buffer, 10);
+
+ if (rc)
+ goto err1;
+
+ rc = write_to_buf(pout_buff->data, pout_buff->size,
+ &(pout_buff->offset), shown_name,
+ (u32)strlen(shown_name)+1);
+
+ if (rc)
+ goto err1;
+
+err1:
+ release_scratch_buff(&tmp_buffer, pout_buff);
+err:
+ return rc;
+}
+
+int
+compress_buff(struct cudbg_buffer *pin_buff, struct cudbg_buffer *pout_buff)
+{
+ struct cudbg_buffer tmp_buffer;
+ struct cudbg_hdr *cudbg_hdr;
+ unsigned long checksum;
+ unsigned char *result;
+ unsigned int bytes_read;
+ int chunk_size, level = 2, rc = 0;
+ int compress_method = 1;
+
+ bytes_read = pin_buff->size;
+ rc = get_scratch_buff(pout_buff, CUDBG_BLOCK_SIZE, &tmp_buffer);
+
+ if (rc)
+ goto err;
+
+ result = (unsigned char *)tmp_buffer.data;
+
+ if (bytes_read < 32)
+ compress_method = 0;
+
+ cudbg_hdr = (struct cudbg_hdr *) pout_buff->data;
+
+ switch (compress_method) {
+ case 1:
+ chunk_size = fastlz_compress_level(level, pin_buff->data,
+ bytes_read, result);
+
+ checksum = update_adler32(1L, result, chunk_size);
+
+ if ((chunk_size > 62000) && (cudbg_hdr->reserved[7] < (u32)
+ chunk_size)) /* 64512 */
+ cudbg_hdr->reserved[7] = (u32) chunk_size;
+
+ rc = write_chunk_header(pout_buff, 17, 1, chunk_size, checksum,
+ bytes_read);
+
+ if (rc)
+ goto err_put_buff;
+
+ rc = write_to_buf(pout_buff->data, pout_buff->size,
+ &pout_buff->offset, result, chunk_size);
+
+ if (rc)
+ goto err_put_buff;
+
+ break;
+
+ /* uncompressed, also fallback method */
+ case 0:
+ default:
+ checksum = update_adler32(1L, pin_buff->data, bytes_read);
+
+ rc = write_chunk_header(pout_buff, 17, 0, bytes_read, checksum,
+ bytes_read);
+
+ if (rc)
+ goto err_put_buff;
+
+ rc = write_to_buf(pout_buff->data, pout_buff->size,
+ &pout_buff->offset, pin_buff->data,
+ bytes_read);
+ if (rc)
+ goto err_put_buff;
+
+ break;
+ }
+
+err_put_buff:
+ release_scratch_buff(&tmp_buffer, pout_buff);
+err:
+ return rc;
+}
+
+/* return non-zero if magic sequence is detected */
+/* warning: reset the read pointer to the beginning of the file */
+int
+detect_magic(struct cudbg_buffer *_c_buff)
+{
+ unsigned char buffer[8];
+ size_t bytes_read;
+ int c;
+
+ bytes_read = read_from_buf(_c_buff->data, _c_buff->size,
+ &_c_buff->offset, buffer, 8);
+
+ if (bytes_read < 8)
+ return 0;
+
+ for (c = 0; c < 8; c++)
+ if (buffer[c] != sixpack_magic[c])
+ return 0;
+
+ return -1;
+}
+
+static unsigned long
+readU16(const unsigned char *ptr)
+{
+ return ptr[0]+(ptr[1]<<8);
+}
+
+static unsigned long
+readU32(const unsigned char *ptr)
+{
+ return ptr[0]+(ptr[1]<<8)+(ptr[2]<<16)+(ptr[3]<<24);
+}
+
+int
+read_chunk_header(struct cudbg_buffer *pc_buff, int *pid, int *poptions,
+ unsigned long *psize, unsigned long *pchecksum,
+ unsigned long *pextra)
+{
+ unsigned char buffer[CUDBG_CHUNK_BUF_LEN];
+ int byte_r = read_from_buf(pc_buff->data, pc_buff->size,
+ &pc_buff->offset, buffer, 16);
+ if (byte_r == 0)
+ return 0;
+
+ *pid = readU16(buffer) & 0xffff;
+ *poptions = readU16(buffer+2) & 0xffff;
+ *psize = readU32(buffer+4) & 0xffffffff;
+ *pchecksum = readU32(buffer+8) & 0xffffffff;
+ *pextra = readU32(buffer+12) & 0xffffffff;
+ return 0;
+}
+
+int
+validate_buffer(struct cudbg_buffer *compressed_buffer)
+{
+ if (!detect_magic(compressed_buffer))
+ return CUDBG_STATUS_INVALID_BUFF;
+
+ return 0;
+}
+
+int
+decompress_buffer(struct cudbg_buffer *pc_buff,
+ struct cudbg_buffer *pd_buff)
+{
+ struct cudbg_buffer tmp_compressed_buffer;
+ struct cudbg_buffer tmp_decompressed_buffer;
+ unsigned char *compressed_buffer;
+ unsigned char *decompressed_buffer;
+ unsigned char buffer[CUDBG_MIN_COMPR_LEN];
+ unsigned long chunk_size;
+ unsigned long chunk_checksum;
+ unsigned long chunk_extra;
+ unsigned long checksum;
+ unsigned long total_extracted = 0;
+ unsigned long r;
+ unsigned long remaining;
+ unsigned long bytes_read;
+ u32 decompressed_size = 0;
+ int chunk_id, chunk_options, rc;
+
+ if (pd_buff->size < 2 * CUDBG_BLOCK_SIZE)
+ return CUDBG_STATUS_SMALL_BUFF;
+
+ rc = get_scratch_buff(pd_buff, CUDBG_BLOCK_SIZE,
+ &tmp_compressed_buffer);
+
+ if (rc)
+ goto err_cbuff;
+
+ rc = get_scratch_buff(pd_buff, CUDBG_BLOCK_SIZE,
+ &tmp_decompressed_buffer);
+ if (rc)
+ goto err_dcbuff;
+
+ compressed_buffer = (unsigned char *)tmp_compressed_buffer.data;
+ decompressed_buffer = (unsigned char *)tmp_decompressed_buffer.data;
+
+ /* main loop */
+
+ for (;;) {
+ if (pc_buff->offset > pc_buff->size)
+ break;
+
+ rc = read_chunk_header(pc_buff, &chunk_id, &chunk_options,
+ &chunk_size, &chunk_checksum,
+ &chunk_extra);
+ if (rc != 0)
+ break;
+
+ /* skip 8+16 */
+ if ((chunk_id == 1) && (chunk_size > 10) &&
+ (chunk_size < CUDBG_BLOCK_SIZE)) {
+
+ bytes_read = read_from_buf(pc_buff->data, pc_buff->size,
+ &pc_buff->offset, buffer,
+ chunk_size);
+
+ if (bytes_read == 0)
+ return 0;
+
+ checksum = update_adler32(1L, buffer, chunk_size);
+ if (checksum != chunk_checksum)
+ return CUDBG_STATUS_CHKSUM_MISSMATCH;
+
+ decompressed_size = (u32)readU32(buffer);
+
+ if (pd_buff->size < decompressed_size) {
+
+ pd_buff->size = 2 * CUDBG_BLOCK_SIZE +
+ decompressed_size;
+ pc_buff->offset -= chunk_size + 16;
+ return CUDBG_STATUS_SMALL_BUFF;
+ }
+ total_extracted = 0;
+
+ }
+
+ if (chunk_size > CUDBG_BLOCK_SIZE) {
+ /* Release old allocated memory */
+ release_scratch_buff(&tmp_decompressed_buffer, pd_buff);
+ release_scratch_buff(&tmp_compressed_buffer, pd_buff);
+
+ /* allocate new memory with chunk_size size */
+ rc = get_scratch_buff(pd_buff, chunk_size,
+ &tmp_compressed_buffer);
+ if (rc)
+ goto err_cbuff;
+
+ rc = get_scratch_buff(pd_buff, chunk_size,
+ &tmp_decompressed_buffer);
+ if (rc)
+ goto err_dcbuff;
+
+ compressed_buffer = (unsigned char *)tmp_compressed_buffer.data;
+ decompressed_buffer = (unsigned char *)tmp_decompressed_buffer.data;
+ }
+
+ if ((chunk_id == 17) && decompressed_size) {
+ /* uncompressed */
+ switch (chunk_options) {
+ /* stored, simply copy to output */
+ case 0:
+ total_extracted += chunk_size;
+ remaining = chunk_size;
+ checksum = 1L;
+ for (;;) {
+ /* Write a funtion for this */
+ r = (CUDBG_BLOCK_SIZE < remaining) ?
+ CUDBG_BLOCK_SIZE : remaining;
+ bytes_read =
+ read_from_buf(pc_buff->data,
+ pc_buff->size,
+ &pc_buff->offset, buffer,
+ r);
+
+ if (bytes_read == 0)
+ return 0;
+
+ write_to_buf(pd_buff->data,
+ pd_buff->size,
+ &pd_buff->offset, buffer,
+ bytes_read);
+ checksum = update_adler32(checksum,
+ buffer,
+ bytes_read);
+ remaining -= bytes_read;
+
+ /* verify everything is written
+ * correctly */
+ if (checksum != chunk_checksum)
+ return
+ CUDBG_STATUS_CHKSUM_MISSMATCH;
+ }
+
+ break;
+
+ /* compressed using FastLZ */
+ case 1:
+ bytes_read = read_from_buf(pc_buff->data,
+ pc_buff->size,
+ &pc_buff->offset,
+ compressed_buffer,
+ chunk_size);
+
+ if (bytes_read == 0)
+ return 0;
+
+ checksum = update_adler32(1L, compressed_buffer,
+ chunk_size);
+ total_extracted += chunk_extra;
+
+ /* verify that the chunk data is correct */
+ if (checksum != chunk_checksum) {
+ return CUDBG_STATUS_CHKSUM_MISSMATCH;
+ } else {
+ /* decompress and verify */
+ remaining =
+ fastlz_decompress(compressed_buffer,
+ chunk_size,
+ decompressed_buffer,
+ chunk_extra);
+
+ if (remaining != chunk_extra) {
+ rc =
+ CUDBG_STATUS_DECOMPRESS_FAIL;
+ goto err;
+ } else {
+ write_to_buf(pd_buff->data,
+ pd_buff->size,
+ &pd_buff->offset,
+ decompressed_buffer,
+ chunk_extra);
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ }
+
+ }
+
+err:
+ release_scratch_buff(&tmp_decompressed_buffer, pd_buff);
+err_dcbuff:
+ release_scratch_buff(&tmp_compressed_buffer, pd_buff);
+
+err_cbuff:
+ return rc;
+}
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c b/usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
index 7fffa8076b..8b03bb9e84 100644
--- a/usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
+++ b/usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c
@@ -27,6 +27,7 @@
#include "t4nex.h"
#include "common/common.h"
#include "common/t4_regs.h"
+#include "cudbg.h"
/* helpers */
static int pci_rw(struct adapter *sc, void *data, int flags, int write);
@@ -45,6 +46,7 @@ static int read_cim_qcfg(struct adapter *sc, void *data, int flags);
static int read_cim_ibq(struct adapter *sc, void *data, int flags);
static int read_edc(struct adapter *sc, void *data, int flags);
static int flash_fw(struct adapter *, void *, int);
+static int get_cudbg(struct adapter *, void *, int);
int
t4_ioctl(struct adapter *sc, int cmd, void *data, int mode)
@@ -93,6 +95,9 @@ t4_ioctl(struct adapter *sc, int cmd, void *data, int mode)
case T4_IOCTL_LOAD_FW:
rc = flash_fw(sc, data, mode);
break;
+ case T4_IOCTL_GET_CUDBG:
+ rc = get_cudbg(sc, data, mode);
+ break;
default:
return (EINVAL);
}
@@ -1675,3 +1680,54 @@ flash_fw(struct adapter *sc, void *data, int flags)
return (rc);
}
+
+static int
+get_cudbg(struct adapter *sc, void *data, int flags)
+{
+ struct t4_cudbg_dump dump;
+ struct cudbg_init *cudbg;
+ void *handle, *buf;
+ int size;
+ int rc = 0;
+
+ if (ddi_copyin(data, &dump, sizeof(struct t4_cudbg_dump), flags) < 0)
+ return EFAULT;
+
+ size = dump.len;
+ buf = (u8 *)kmem_zalloc(dump.len, KM_NOSLEEP);
+ if (buf == NULL)
+ return ENOMEM;
+
+ handle = cudbg_alloc_handle();
+ if (handle == NULL) {
+ rc = ENOMEM;
+ goto free;
+ }
+
+ cudbg = cudbg_get_init(handle);
+ cudbg->adap = sc;
+ cudbg->print = (cudbg_print_cb)cxgb_printf;
+
+ memcpy(cudbg->dbg_bitmap, dump.bitmap, sizeof(cudbg->dbg_bitmap));
+
+ rc = cudbg_collect(handle, buf, &dump.len);
+ if (rc != 0) {
+ cxgb_printf(sc->dip, CE_WARN, "cudbg collect failed\n");
+ goto exit;
+ }
+
+ if(ddi_copyout(buf, (void *)((uintptr_t)data + sizeof(dump)),
+ dump.len, flags) < 0){
+ rc = EFAULT;
+ }
+
+ if (ddi_copyout(&dump, data, sizeof(dump), flags) < 0){
+ rc = EFAULT;
+ }
+exit:
+ cudbg_free_handle(handle);
+free:
+ kmem_free(buf, size);
+
+ return rc;
+}
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/t4_mac.c b/usr/src/uts/common/io/cxgbe/t4nex/t4_mac.c
index d5f2fdea78..59c0ddde8d 100644
--- a/usr/src/uts/common/io/cxgbe/t4nex/t4_mac.c
+++ b/usr/src/uts/common/io/cxgbe/t4nex/t4_mac.c
@@ -45,8 +45,6 @@ static int t4_mc_getprop(void *arg, const char *name, mac_prop_id_t id,
static void t4_mc_propinfo(void *arg, const char *name, mac_prop_id_t id,
mac_prop_info_handle_t ph);
-static int begin_synchronized_op(struct port_info *pi, int hold, int waitok);
-static void end_synchronized_op(struct port_info *pi, int held);
static int t4_init_synchronized(struct port_info *pi);
static int t4_uninit_synchronized(struct port_info *pi);
static void propinfo(struct port_info *pi, const char *name,
@@ -230,30 +228,30 @@ t4_mc_getstat(void *arg, uint_t stat, uint64_t *val)
return (ENOTSUP);
case ETHER_STAT_CAP_100GFDX:
- *val = !!(lc->supported & FW_PORT_CAP_SPEED_100G);
+ *val = !!(lc->pcaps & FW_PORT_CAP32_SPEED_100G);
break;
case ETHER_STAT_CAP_40GFDX:
- *val = !!(lc->supported & FW_PORT_CAP_SPEED_40G);
+ *val = !!(lc->pcaps & FW_PORT_CAP32_SPEED_40G);
break;
case ETHER_STAT_CAP_25GFDX:
- *val = !!(lc->supported & FW_PORT_CAP_SPEED_25G);
+ *val = !!(lc->pcaps & FW_PORT_CAP32_SPEED_25G);
break;
case ETHER_STAT_CAP_10GFDX:
- *val = !!(lc->supported & FW_PORT_CAP_SPEED_10G);
+ *val = !!(lc->pcaps & FW_PORT_CAP32_SPEED_10G);
break;
case ETHER_STAT_CAP_1000FDX:
- *val = !!(lc->supported & FW_PORT_CAP_SPEED_1G);
+ *val = !!(lc->pcaps & FW_PORT_CAP32_SPEED_1G);
break;
case ETHER_STAT_CAP_1000HDX:
return (ENOTSUP);
case ETHER_STAT_CAP_100FDX:
- *val = !!(lc->supported & FW_PORT_CAP_SPEED_100M);
+ *val = !!(lc->pcaps & FW_PORT_CAP32_SPEED_100M);
break;
case ETHER_STAT_CAP_100HDX:
@@ -272,7 +270,7 @@ t4_mc_getstat(void *arg, uint_t stat, uint64_t *val)
break;
case ETHER_STAT_CAP_AUTONEG:
- *val = !!(lc->supported & FW_PORT_CAP_ANEG);
+ *val = !!(lc->pcaps & FW_PORT_CAP32_ANEG);
break;
/*
@@ -309,27 +307,27 @@ t4_mc_getstat(void *arg, uint_t stat, uint64_t *val)
break;
case ETHER_STAT_ADV_CAP_100GFDX:
- *val = !!(lc->advertising & FW_PORT_CAP_SPEED_100G);
+ *val = !!(lc->acaps & FW_PORT_CAP32_SPEED_100G);
break;
case ETHER_STAT_ADV_CAP_40GFDX:
- *val = !!(lc->advertising & FW_PORT_CAP_SPEED_40G);
+ *val = !!(lc->acaps & FW_PORT_CAP32_SPEED_40G);
break;
case ETHER_STAT_ADV_CAP_25GFDX:
- *val = !!(lc->advertising & FW_PORT_CAP_SPEED_25G);
+ *val = !!(lc->acaps & FW_PORT_CAP32_SPEED_25G);
break;
case ETHER_STAT_ADV_CAP_10GFDX:
- *val = !!(lc->advertising & FW_PORT_CAP_SPEED_10G);
+ *val = !!(lc->acaps & FW_PORT_CAP32_SPEED_10G);
break;
case ETHER_STAT_ADV_CAP_1000FDX:
- *val = !!(lc->advertising & FW_PORT_CAP_SPEED_1G);
+ *val = !!(lc->acaps & FW_PORT_CAP32_SPEED_1G);
break;
case ETHER_STAT_ADV_CAP_AUTONEG:
- *val = !!(lc->advertising & FW_PORT_CAP_ANEG);
+ *val = !!(lc->acaps & FW_PORT_CAP32_ANEG);
break;
case ETHER_STAT_ADV_CAP_1000HDX:
@@ -341,27 +339,27 @@ t4_mc_getstat(void *arg, uint_t stat, uint64_t *val)
case ETHER_STAT_LP_CAP_100GFDX:
- *val = !!(lc->lp_advertising & FW_PORT_CAP_SPEED_100G);
+ *val = !!(lc->acaps & FW_PORT_CAP32_SPEED_100G);
break;
case ETHER_STAT_LP_CAP_40GFDX:
- *val = !!(lc->lp_advertising & FW_PORT_CAP_SPEED_40G);
+ *val = !!(lc->acaps & FW_PORT_CAP32_SPEED_40G);
break;
case ETHER_STAT_LP_CAP_25GFDX:
- *val = !!(lc->lp_advertising & FW_PORT_CAP_SPEED_25G);
+ *val = !!(lc->acaps & FW_PORT_CAP32_SPEED_25G);
break;
case ETHER_STAT_LP_CAP_10GFDX:
- *val = !!(lc->lp_advertising & FW_PORT_CAP_SPEED_10G);
+ *val = !!(lc->acaps & FW_PORT_CAP32_SPEED_10G);
break;
case ETHER_STAT_LP_CAP_1000FDX:
- *val = !!(lc->lp_advertising & FW_PORT_CAP_SPEED_1G);
+ *val = !!(lc->acaps & FW_PORT_CAP32_SPEED_1G);
break;
case ETHER_STAT_LP_CAP_AUTONEG:
- *val = !!(lc->lp_advertising & FW_PORT_CAP_ANEG);
+ *val = !!(lc->acaps & FW_PORT_CAP32_ANEG);
break;
case ETHER_STAT_LP_CAP_1000HDX:
@@ -515,7 +513,7 @@ t4_mc_unicst(void *arg, const uint8_t *ucaddr)
return (ENOSPC);
}
rc = t4_change_mac(sc, sc->mbox, pi->viid, pi->xact_addr_filt, ucaddr,
- true, true);
+ true, &pi->smt_idx);
if (rc < 0)
rc = -rc;
else {
@@ -953,7 +951,7 @@ t4_mc_setprop(void *arg, const char *name, mac_prop_id_t id, uint_t size,
switch (id) {
case MAC_PROP_AUTONEG:
- if (lc->supported & FW_PORT_CAP_ANEG) {
+ if (lc->pcaps & FW_PORT_CAP32_ANEG) {
old = lc->autoneg;
new = v8 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
if (old != new) {
@@ -962,20 +960,20 @@ t4_mc_setprop(void *arg, const char *name, mac_prop_id_t id, uint_t size,
relink = 1;
if (new == AUTONEG_DISABLE) {
/* Only 100M is available */
- lc->requested_speed =
- FW_PORT_CAP_SPEED_100M;
- lc->advertising =
- FW_PORT_CAP_SPEED_100M;
+ lc->speed_caps =
+ FW_PORT_CAP32_SPEED_100M;
+ lc->acaps =
+ FW_PORT_CAP32_SPEED_100M;
} else {
/*
* Advertise autonegotiation capability
* along with supported speeds
*/
- lc->advertising |= (FW_PORT_CAP_ANEG |
- (lc->supported &
- (FW_PORT_CAP_SPEED_100M |
- FW_PORT_CAP_SPEED_1G)));
- lc->requested_speed = 0;
+ lc->acaps |= (FW_PORT_CAP32_ANEG |
+ (lc->pcaps &
+ (FW_PORT_CAP32_SPEED_100M |
+ FW_PORT_CAP32_SPEED_1G)));
+ lc->speed_caps = 0;
}
}
} else
@@ -1012,12 +1010,12 @@ t4_mc_setprop(void *arg, const char *name, mac_prop_id_t id, uint_t size,
break;
case MAC_PROP_EN_10GFDX_CAP:
- if (lc->supported & FW_PORT_CAP_ANEG && is_10G_port(pi)) {
- old = lc->advertising & FW_PORT_CAP_SPEED_10G;
- new = v8 ? FW_PORT_CAP_SPEED_10G : 0;
+ if (lc->pcaps & FW_PORT_CAP32_ANEG && is_10G_port(pi)) {
+ old = lc->acaps & FW_PORT_CAP32_SPEED_10G;
+ new = v8 ? FW_PORT_CAP32_SPEED_10G : 0;
if (new != old) {
- lc->advertising &= ~FW_PORT_CAP_SPEED_10G;
- lc->advertising |= new;
+ lc->acaps &= ~FW_PORT_CAP32_SPEED_10G;
+ lc->acaps |= new;
relink = 1;
}
} else
@@ -1028,12 +1026,12 @@ t4_mc_setprop(void *arg, const char *name, mac_prop_id_t id, uint_t size,
case MAC_PROP_EN_1000FDX_CAP:
/* Forced 1G */
if (lc->autoneg == AUTONEG_ENABLE) {
- old = lc->advertising & FW_PORT_CAP_SPEED_1G;
- new = v8 ? FW_PORT_CAP_SPEED_1G : 0;
+ old = lc->acaps & FW_PORT_CAP32_SPEED_1G;
+ new = v8 ? FW_PORT_CAP32_SPEED_1G : 0;
if (old != new) {
- lc->advertising &= ~FW_PORT_CAP_SPEED_1G;
- lc->advertising |= new;
+ lc->acaps &= ~FW_PORT_CAP32_SPEED_1G;
+ lc->acaps |= new;
relink = 1;
}
} else
@@ -1043,11 +1041,11 @@ t4_mc_setprop(void *arg, const char *name, mac_prop_id_t id, uint_t size,
case MAC_PROP_EN_100FDX_CAP:
/* Forced 100M */
if (lc->autoneg == AUTONEG_ENABLE) {
- old = lc->advertising & FW_PORT_CAP_SPEED_100M;
- new = v8 ? FW_PORT_CAP_SPEED_100M : 0;
+ old = lc->acaps & FW_PORT_CAP32_SPEED_100M;
+ new = v8 ? FW_PORT_CAP32_SPEED_100M : 0;
if (old != new) {
- lc->advertising &= ~FW_PORT_CAP_SPEED_100M;
- lc->advertising |= new;
+ lc->acaps &= ~FW_PORT_CAP32_SPEED_100M;
+ lc->acaps |= new;
relink = 1;
}
} else
@@ -1147,32 +1145,32 @@ t4_mc_getprop(void *arg, const char *name, mac_prop_id_t id, uint_t size,
case MAC_PROP_ADV_100GFDX_CAP:
case MAC_PROP_EN_100GFDX_CAP:
- *u = !!(lc->advertising & FW_PORT_CAP_SPEED_100G);
+ *u = !!(lc->acaps & FW_PORT_CAP32_SPEED_100G);
break;
case MAC_PROP_ADV_40GFDX_CAP:
case MAC_PROP_EN_40GFDX_CAP:
- *u = !!(lc->advertising & FW_PORT_CAP_SPEED_40G);
+ *u = !!(lc->acaps & FW_PORT_CAP32_SPEED_40G);
break;
case MAC_PROP_ADV_25GFDX_CAP:
case MAC_PROP_EN_25GFDX_CAP:
- *u = !!(lc->advertising & FW_PORT_CAP_SPEED_25G);
+ *u = !!(lc->acaps & FW_PORT_CAP32_SPEED_25G);
break;
case MAC_PROP_ADV_10GFDX_CAP:
case MAC_PROP_EN_10GFDX_CAP:
- *u = !!(lc->advertising & FW_PORT_CAP_SPEED_10G);
+ *u = !!(lc->acaps & FW_PORT_CAP32_SPEED_10G);
break;
case MAC_PROP_ADV_1000FDX_CAP:
case MAC_PROP_EN_1000FDX_CAP:
- *u = !!(lc->advertising & FW_PORT_CAP_SPEED_1G);
+ *u = !!(lc->acaps & FW_PORT_CAP32_SPEED_1G);
break;
case MAC_PROP_ADV_100FDX_CAP:
case MAC_PROP_EN_100FDX_CAP:
- *u = !!(lc->advertising & FW_PORT_CAP_SPEED_100M);
+ *u = !!(lc->acaps & FW_PORT_CAP32_SPEED_100M);
break;
case MAC_PROP_PRIVATE:
@@ -1200,7 +1198,7 @@ t4_mc_propinfo(void *arg, const char *name, mac_prop_id_t id,
break;
case MAC_PROP_AUTONEG:
- if (lc->supported & FW_PORT_CAP_ANEG)
+ if (lc->pcaps & FW_PORT_CAP32_ANEG)
mac_prop_info_set_default_uint8(ph, 1);
else
mac_prop_info_set_perm(ph, MAC_PROP_PERM_READ);
@@ -1215,24 +1213,24 @@ t4_mc_propinfo(void *arg, const char *name, mac_prop_id_t id,
break;
case MAC_PROP_EN_10GFDX_CAP:
- if (lc->supported & FW_PORT_CAP_ANEG &&
- lc->supported & FW_PORT_CAP_SPEED_10G)
+ if (lc->pcaps & FW_PORT_CAP32_ANEG &&
+ lc->pcaps & FW_PORT_CAP32_SPEED_10G)
mac_prop_info_set_default_uint8(ph, 1);
else
mac_prop_info_set_perm(ph, MAC_PROP_PERM_READ);
break;
case MAC_PROP_EN_1000FDX_CAP:
- if (lc->supported & FW_PORT_CAP_ANEG &&
- lc->supported & FW_PORT_CAP_SPEED_1G)
+ if (lc->pcaps & FW_PORT_CAP32_ANEG &&
+ lc->pcaps & FW_PORT_CAP32_SPEED_1G)
mac_prop_info_set_default_uint8(ph, 1);
else
mac_prop_info_set_perm(ph, MAC_PROP_PERM_READ);
break;
case MAC_PROP_EN_100FDX_CAP:
- if (lc->supported & FW_PORT_CAP_ANEG &&
- lc->supported & FW_PORT_CAP_SPEED_100M)
+ if (lc->pcaps & FW_PORT_CAP32_ANEG &&
+ lc->pcaps & FW_PORT_CAP32_SPEED_100M)
mac_prop_info_set_default_uint8(ph, 1);
else
mac_prop_info_set_perm(ph, MAC_PROP_PERM_READ);
@@ -1253,7 +1251,7 @@ t4_mc_propinfo(void *arg, const char *name, mac_prop_id_t id,
}
}
-static int
+int
begin_synchronized_op(struct port_info *pi, int hold, int waitok)
{
struct adapter *sc = pi->adapter;
@@ -1286,7 +1284,7 @@ failed:
return (rc);
}
-static void
+void
end_synchronized_op(struct port_info *pi, int held)
{
struct adapter *sc = pi->adapter;
@@ -1330,7 +1328,7 @@ t4_init_synchronized(struct port_info *pi)
goto done;
}
rc = t4_change_mac(sc, sc->mbox, pi->viid, pi->xact_addr_filt,
- pi->hw_addr, true, true);
+ pi->hw_addr, true, &pi->smt_idx);
if (rc < 0) {
cxgb_printf(pi->dip, CE_WARN, "change_mac failed: %d", rc);
rc = -rc;
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c b/usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c
index b9ce760bf2..b587656ba1 100644
--- a/usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c
+++ b/usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c
@@ -1347,7 +1347,9 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
c.iqsize = cpu_to_be16(iq->qsize);
c.iqaddr = cpu_to_be64(iq->ba);
if (cong >= 0)
- c.iqns_to_fl0congen = BE_32(F_FW_IQ_CMD_IQFLINTCONGEN);
+ c.iqns_to_fl0congen = BE_32(F_FW_IQ_CMD_IQFLINTCONGEN |
+ V_FW_IQ_CMD_IQTYPE(cong ?
+ FW_IQ_IQTYPE_NIC : FW_IQ_IQTYPE_OFLD));
if (fl != NULL) {
unsigned int chip_ver = CHELSIO_CHIP_VERSION(sc->params.chip);
@@ -1587,7 +1589,8 @@ alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int i)
int rc;
rxq->port = pi;
- rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, 1 << pi->tx_chan);
+ rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx,
+ t4_get_tp_ch_map(pi->adapter, pi->tx_chan));
if (rc != 0)
return (rc);
@@ -1621,7 +1624,7 @@ alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq,
int rc;
rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
- 1 << pi->tx_chan);
+ t4_get_tp_ch_map(pi->adapter, pi->tx_chan));
if (rc != 0)
return (rc);
diff --git a/usr/src/uts/common/io/cxgbe/t4nex/t4nex.h b/usr/src/uts/common/io/cxgbe/t4nex/t4nex.h
index da6edbd88b..fa2bd2ec7b 100644
--- a/usr/src/uts/common/io/cxgbe/t4nex/t4nex.h
+++ b/usr/src/uts/common/io/cxgbe/t4nex/t4nex.h
@@ -43,6 +43,7 @@ extern "C" {
#define T4_IOCTL_GET_CIM_IBQ (T4_IOCTL + 13)
#define T4_IOCTL_GET_EDC (T4_IOCTL + 14)
#define T4_IOCTL_LOAD_FW (T4_IOCTL + 15)
+#define T4_IOCTL_GET_CUDBG (T4_IOCTL + 16)
enum {
T4_CTXT_EGRESS,
@@ -124,6 +125,13 @@ struct t4_ldfw {
uint32_t data[0];
};
+struct t4_cudbg_dump {
+ uint8_t wr_flash;
+ uint8_t bitmap[16];
+ uint32_t len;
+ uint32_t data[0];
+};
+
#ifdef __cplusplus
}
#endif
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-31 13:02:12 +0000