5 files changed, 35 insertions, 11 deletions
diff --git a/usr/src/uts/common/io/pciex/pcie_fault.c b/usr/src/uts/common/io/pciex/pcie_fault.c
index ae540274c3..df4118b323 100644
--- a/usr/src/uts/common/io/pciex/pcie_fault.c
+++ b/usr/src/uts/common/io/pciex/pcie_fault.c
@@ -268,6 +268,11 @@ done:
 	return (analyse_flag);
 }
 
+void
+pcie_force_fullscan() {
+	pcie_full_scan = B_TRUE;
+}
+
 /*
  * pf_dispatch walks the device tree and calls the pf_default_hdl if the device
  * falls in the error path.
diff --git a/usr/src/uts/common/sys/pcie_impl.h b/usr/src/uts/common/sys/pcie_impl.h
index 0943da2c92..378e9b94d3 100644
--- a/usr/src/uts/common/sys/pcie_impl.h
+++ b/usr/src/uts/common/sys/pcie_impl.h
@@ -505,6 +505,7 @@ extern void pf_fini(dev_info_t *, ddi_detach_cmd_t);
 extern int pf_hdl_lookup(dev_info_t *, uint64_t, uint32_t, uint64_t,
     pcie_req_id_t);
 extern int pf_tlp_decode(pcie_bus_t *, pf_pcie_adv_err_regs_t *);
+extern void pcie_force_fullscan();
 
 #ifdef	DEBUG
 extern uint_t pcie_debug_flags;
diff --git a/usr/src/uts/i86pc/io/pciex/npe.c b/usr/src/uts/i86pc/io/pciex/npe.c
index 23b02640f5..6e40f73475 100644
--- a/usr/src/uts/i86pc/io/pciex/npe.c
+++ b/usr/src/uts/i86pc/io/pciex/npe.c
@@ -173,8 +173,8 @@ static int npe_initchild(dev_info_t *child);
 extern void	npe_query_acpi_mcfg(dev_info_t *dip);
 extern void	npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
 extern int	npe_disable_empty_bridges_workaround(dev_info_t *child);
-extern void	npe_nvidia_error_mask(ddi_acc_handle_t cfg_hdl);
-extern void	npe_intel_error_mask(ddi_acc_handle_t cfg_hdl);
+extern void	npe_nvidia_error_workaround(ddi_acc_handle_t cfg_hdl);
+extern void	npe_intel_error_workaround(ddi_acc_handle_t cfg_hdl);
 extern boolean_t npe_is_mmcfg_supported(dev_info_t *dip);
 extern void	npe_enable_htmsi_children(dev_info_t *dip);
 extern int	npe_save_htconfig_children(dev_info_t *dip);
@@ -934,8 +934,8 @@ npe_initchild(dev_info_t *child)
 
 	if (pci_config_setup(child, &cfg_hdl) == DDI_SUCCESS) {
 		npe_ck804_fix_aer_ptr(cfg_hdl);
-		npe_nvidia_error_mask(cfg_hdl);
-		npe_intel_error_mask(cfg_hdl);
+		npe_nvidia_error_workaround(cfg_hdl);
+		npe_intel_error_workaround(cfg_hdl);
 		pci_config_teardown(&cfg_hdl);
 	}
 
diff --git a/usr/src/uts/i86pc/io/pciex/npe_misc.c b/usr/src/uts/i86pc/io/pciex/npe_misc.c
index 59dfbce86e..94c55d3857 100644
--- a/usr/src/uts/i86pc/io/pciex/npe_misc.c
+++ b/usr/src/uts/i86pc/io/pciex/npe_misc.c
@@ -46,8 +46,8 @@
 void	npe_query_acpi_mcfg(dev_info_t *dip);
 void	npe_ck804_fix_aer_ptr(ddi_acc_handle_t cfg_hdl);
 int	npe_disable_empty_bridges_workaround(dev_info_t *child);
-void	npe_nvidia_error_mask(ddi_acc_handle_t cfg_hdl);
-void	npe_intel_error_mask(ddi_acc_handle_t cfg_hdl);
+void	npe_nvidia_error_workaround(ddi_acc_handle_t cfg_hdl);
+void	npe_intel_error_workaround(ddi_acc_handle_t cfg_hdl);
 boolean_t npe_is_child_pci(dev_info_t *dip);
 
 /*
@@ -55,8 +55,7 @@ boolean_t npe_is_child_pci(dev_info_t *dip);
  */
 int64_t npe_default_ecfga_base = 0xE0000000;
 
-extern uint32_t	npe_aer_uce_mask;
-extern boolean_t pcie_full_scan;
+extern uint32_t npe_aer_uce_mask;
 
 /* AMD's northbridges vendor-id and device-ids */
 #define	AMD_NTBRDIGE_VID		0x1022	/* AMD vendor-id */
@@ -201,7 +200,7 @@ npe_disable_empty_bridges_workaround(dev_info_t *child)
 }
 
 void
-npe_nvidia_error_mask(ddi_acc_handle_t cfg_hdl) {
+npe_nvidia_error_workaround(ddi_acc_handle_t cfg_hdl) {
 	uint32_t regs;
 	uint16_t vendor_id = pci_config_get16(cfg_hdl, PCI_CONF_VENID);
 	uint16_t dev_id = pci_config_get16(cfg_hdl, PCI_CONF_DEVID);
@@ -216,14 +215,15 @@ npe_nvidia_error_mask(ddi_acc_handle_t cfg_hdl) {
 		 * Turn full scan on since the Error Source ID register may not
 		 * have the correct ID.
 		 */
-		pcie_full_scan = B_TRUE;
+		pcie_force_fullscan();
 	}
 }
 
 void
-npe_intel_error_mask(ddi_acc_handle_t cfg_hdl) {
+npe_intel_error_workaround(ddi_acc_handle_t cfg_hdl) {
 	uint32_t regs;
 	uint16_t vendor_id = pci_config_get16(cfg_hdl, PCI_CONF_VENID);
+	uint16_t dev_id = pci_config_get16(cfg_hdl, PCI_CONF_DEVID);
 
 	if (vendor_id == INTEL_VENDOR_ID) {
 		/*
@@ -240,6 +240,18 @@ npe_intel_error_mask(ddi_acc_handle_t cfg_hdl) {
 		 */
 		regs = pcie_get_aer_uce_mask() | PCIE_AER_UCE_ECRC;
 		pcie_set_aer_uce_mask(regs);
+
+		if (INTEL_NB5500_PCIE_DEV_ID(dev_id) ||
+		    INTEL_NB5520_PCIE_DEV_ID(dev_id)) {
+			/*
+			 * Turn full scan on since the Error Source ID register
+			 * may not have the correct ID. See Intel 5520 and
+			 * Intel 5500 Chipsets errata #34 and #54 in the August
+			 * 2009 specification update, document number
+			 * 321329-006.
+			 */
+			pcie_force_fullscan();
+		}
 	}
 }
 
diff --git a/usr/src/uts/intel/io/pciex/pcie_nb5000.h b/usr/src/uts/intel/io/pciex/pcie_nb5000.h
index 7063c67508..9fb07f404f 100644
--- a/usr/src/uts/intel/io/pciex/pcie_nb5000.h
+++ b/usr/src/uts/intel/io/pciex/pcie_nb5000.h
@@ -43,6 +43,12 @@ extern "C" {
 #define	INTEL_NB5100_PCIE_DEV_ID(did) (((did) >= 0x65e2 && (did) <= 0x65e7) || \
 	((did) >= 0x65f7 && (did) <= 0x65fa))
 
+#define	INTEL_NB5500_PCIE_DEV_ID(did) (((did) >= 0x3408 && (did) <= 0x3411) || \
+	(did) == 0x3420 || (did) == 0x3403)
+
+#define	INTEL_NB5520_PCIE_DEV_ID(did) (((did) >= 0x3408 && (did) <= 0x3411) || \
+	(did) == 0x3421 || (did) == 0x3406)
+
 #define	INTEL_ESB2_SW_PCIE_DEV_ID(did) (((did) >= 0x3500 && (did) <= 0x3503) ||\
 	((did) >= 0x3510 && (did) <= 0x351B))