diff options
Diffstat (limited to 'usr/src')
| -rw-r--r-- | usr/src/uts/common/io/nxge/nxge_main.c | 54 | ||||
| -rw-r--r-- | usr/src/uts/common/io/nxge/nxge_send.c | 4 |
2 files changed, 52 insertions, 6 deletions
diff --git a/usr/src/uts/common/io/nxge/nxge_main.c b/usr/src/uts/common/io/nxge/nxge_main.c index 9b20c438f4..84b1814993 100644 --- a/usr/src/uts/common/io/nxge/nxge_main.c +++ b/usr/src/uts/common/io/nxge/nxge_main.c @@ -360,6 +360,22 @@ nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); #define NXGE_MSIX_REQUEST_10G 8 #define NXGE_MSIX_REQUEST_1G 2 static int nxge_create_msi_property(p_nxge_t); +/* + * For applications that care about the + * latency, it was requested by PAE and the + * customers that the driver has tunables that + * allow the user to tune it to a higher number + * interrupts to spread the interrupts among + * multiple channels. The DDI framework limits + * the maximum number of MSI-X resources to allocate + * to 8 (ddi_msix_alloc_limit). If more than 8 + * is set, ddi_msix_alloc_limit must be set accordingly. + * The default number of MSI interrupts are set to + * 8 for 10G and 2 for 1G link. + */ +#define NXGE_MSIX_MAX_ALLOWED 32 +uint32_t nxge_msix_10g_intrs = NXGE_MSIX_REQUEST_10G; +uint32_t nxge_msix_1g_intrs = NXGE_MSIX_REQUEST_1G; /* * These global variables control the message @@ -6716,12 +6732,30 @@ nxge_create_msi_property(p_nxge_t nxgep) DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); /* * The maximum MSI-X requested will be 8. - * If the # of CPUs is less than 8, we will reqeust - * # MSI-X based on the # of CPUs. + * If the # of CPUs is less than 8, we will request + * # MSI-X based on the # of CPUs (default). */ - if (ncpus >= NXGE_MSIX_REQUEST_10G) { + NXGE_DEBUG_MSG((nxgep, MOD_CTL, + "==>nxge_create_msi_property (10G): nxge_msix_10g_intrs %d", + nxge_msix_10g_intrs)); + if ((nxge_msix_10g_intrs == 0) || + (nxge_msix_10g_intrs > NXGE_MSIX_MAX_ALLOWED)) { nmsi = NXGE_MSIX_REQUEST_10G; + NXGE_DEBUG_MSG((nxgep, MOD_CTL, + "==>nxge_create_msi_property (10G): reset to 8")); } else { + nmsi = nxge_msix_10g_intrs; + } + + /* + * If # of interrupts requested is 8 (default), + * the checking of the number of cpus will be + * be maintained. + */ + if ((nmsi == NXGE_MSIX_REQUEST_10G) && + (ncpus < nmsi)) { + NXGE_DEBUG_MSG((nxgep, MOD_CTL, + "==>nxge_create_msi_property (10G): reset to 8")); nmsi = ncpus; } NXGE_DEBUG_MSG((nxgep, MOD_CTL, @@ -6731,7 +6765,19 @@ nxge_create_msi_property(p_nxge_t nxgep) break; default: - nmsi = NXGE_MSIX_REQUEST_1G; + (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, + DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); + NXGE_DEBUG_MSG((nxgep, MOD_CTL, + "==>nxge_create_msi_property (1G): nxge_msix_1g_intrs %d", + nxge_msix_1g_intrs)); + if ((nxge_msix_1g_intrs == 0) || + (nxge_msix_1g_intrs > NXGE_MSIX_MAX_ALLOWED)) { + nmsi = NXGE_MSIX_REQUEST_1G; + NXGE_DEBUG_MSG((nxgep, MOD_CTL, + "==>nxge_create_msi_property (1G): reset to 2")); + } else { + nmsi = nxge_msix_1g_intrs; + } NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, diff --git a/usr/src/uts/common/io/nxge/nxge_send.c b/usr/src/uts/common/io/nxge/nxge_send.c index 2b21d22a1c..0bb35ef423 100644 --- a/usr/src/uts/common/io/nxge/nxge_send.c +++ b/usr/src/uts/common/io/nxge/nxge_send.c @@ -173,7 +173,7 @@ nxge_start(p_nxge_t nxgep, p_tx_ring_t tx_ring_p, p_mblk_t mp) tx_desc_t tx_desc, *tmp_desc_p; tx_desc_t sop_tx_desc, *sop_tx_desc_p; p_tx_pkt_header_t hdrp; - tx_pkt_header_t tmp_hdrp; + tx_pkt_hdr_all_t tmp_hdrp; p_tx_pkt_hdr_all_t pkthdrp; uint8_t npads = 0; uint64_t dma_ioaddr; @@ -324,7 +324,7 @@ nxge_start(p_nxge_t nxgep, p_tx_ring_t tx_ring_p, p_mblk_t mp) pkthdrp = (p_tx_pkt_hdr_all_t)&tmp_hdrp; pkthdrp->reserved = 0; - tmp_hdrp.value = 0; + tmp_hdrp.pkthdr.value = 0; nxge_fill_tx_hdr(mp, B_FALSE, cksum_on, 0, 0, pkthdrp, start_offset, stuff_offset); |