From 70f54ead78cbbb40e97bd3ff9f175c5c71783c3c Mon Sep 17 00:00:00 2001
From: esaxe <none@none>
Date: Fri, 22 Jul 2005 15:00:13 -0700
Subject: 6279871 need interim core level load balancing solution for Niagara

---
 usr/src/uts/sun4v/cpu/generic.c | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'usr/src/uts/sun4v/cpu/generic.c')

diff --git a/usr/src/uts/sun4v/cpu/generic.c b/usr/src/uts/sun4v/cpu/generic.c
index b56a51e0ce..8c29c18b42 100644
--- a/usr/src/uts/sun4v/cpu/generic.c
+++ b/usr/src/uts/sun4v/cpu/generic.c
@@ -215,6 +215,12 @@ dtrace_flush_sec(uintptr_t addr)
 void
 cpu_init_private(struct cpu *cp)
 {
+	/*
+	 * The cpu_ipipe field is initialized based on the execution
+	 * unit sharing information from the Machine Description table.
+	 * It defaults to the CPU id in the absence of such information.
+	 */
+	cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id);
 }
 
 void
-- 
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