/* * CDDL HEADER START * * The contents of this file are subject to the terms of the * Common Development and Distribution License, Version 1.0 only * (the "License"). You may not use this file except in compliance * with the License. * * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE * or http://www.opensolaris.org/os/licensing. * See the License for the specific language governing permissions * and limitations under the License. * * When distributing Covered Code, include this CDDL HEADER in each * file and include the License file at usr/src/OPENSOLARIS.LICENSE. * If applicable, add the following below this CDDL HEADER, with the * fields enclosed by brackets "[]" replaced with your own identifying * information: Portions Copyright [yyyy] [name of copyright owner] * * CDDL HEADER END */ /* * Copyright (c) 2001 by Sun Microsystems, Inc. * All rights reserved. * Automatically Generated file based on CSR definitions * */ /* * This file automatically generated from * wci_defs.csr * 11/27/2000 17:21:38 * Using ./csr_filter.pl by pcw */ /* **DO NOT EDIT THIS FILE** */ /* * File ../../../design/wci/include/wci_offsets.h * */ #ifndef _SYS_WCI_OFFSETS_H #define _SYS_WCI_OFFSETS_H #pragma ident "%Z%%M% %I% %E% SMI" #ifdef __cplusplus extern "C" { #endif /* * Include any headers you depend on. */ #define ADDR_WCI_SRAM_ARRAY 0x00000000000 #define ENTRIES_WCI_SRAM_ARRAY 0x1000000 #define STRIDE_WCI_SRAM_ARRAY 0x20 #define ADDR_WCI_SHADOW_ADDR 0x00000000000 #define ADDR_WCI_SHADOW_DATA 0x00000000020 #define ADDR_WCI_CONFIG 0x00000000040 #define ADDR_WCI_DOMAIN_CONFIG 0x00000000060 #define ADDR_WCI_LOCAL_DEVICE_ID 0x00000000080 #define ADDR_WCI_RESET_CONFIG 0x000000000a0 #define ADDR_WCI_RESET_STATUS 0x000000000c0 #define ADDR_WCI_ID 0x000000000e0 #define ADDR_WCI_BOARD2CNID_CONTROL 0x00000000100 #define ADDR_WCI_CSR_CONTROL 0x00000000120 #define ADDR_WCI_ERROR_SUMMARY 0x00000000160 #define ADDR_WCI_ERROR_PAUSE_TIMER_HOLD 0x00000000180 #define ADDR_WCI_FIRST_ERROR_TIME 0x000000001a0 #define ADDR_WCI_CSRA_ESR 0x000000001c0 #define ADDR_WCI_CSRA_ESR_MASK 0x000000001e0 #define ADDR_WCI_CSRA_STATUS 0x00000000200 #define ADDR_WCI_CSRA_TIMEOUT_CONFIG 0x00000000220 #define ADDR_WCI_DC_ESR 0x00000000240 #define ADDR_WCI_DC_ESR_MASK 0x00000000260 #define ADDR_WCI_DCO_STATE 0x00000000280 #define ADDR_WCI_DCO_CE_COUNT 0x000000002a0 #define ADDR_WCI_DCI_STATE 0x000000002c0 #define ADDR_WCI_HLI_STRANGE_PKT_1 0x000000002e0 #define ADDR_WCI_HLI_STRANGE_PKT_0 0x00000000300 #define ADDR_WCI_HLI_ESR 0x00000000320 #define ADDR_WCI_HLI_ESR_MASK 0x00000000340 #define ADDR_WCI_HLI_STATE 0x00000000360 #define ADDR_WCI_SFQ_ESR 0x00000000380 #define ADDR_WCI_SFQ_ESR_MASK 0x000000003a0 #define ADDR_WCI_SFQ_STATE 0x000000003c0 #define ADDR_WCI_ERROR_INDUCEMENT 0x000000003e0 #define ADDR_WCI_UE_DIRECTION 0x00000000400 #define ADDR_WCI_GENERATES_CESR_NUMBER 0x00000000420 #define ADDR_WCI_DIF_TIMEOUT_CNTL 0x00000000440 #define ADDR_WCI_DIF_TIMEOUT_COUNT 0x00000000460 #define ADDR_WCI_MAX 0x00000000480 #define ADDR_WCI_JNK_ROUTE_MAP0 0x00000002000 #define ADDR_WCI_JNK_ROUTE_MAP1 0x00000002020 #define ADDR_WCI_STICK_RATE 0x00000004000 #define ADDR_WCI_STICK 0x00000004020 #define ADDR_WCI_MISC_CTR 0x00000006000 #define ADDR_WCI_MISC_CTR_CTL 0x00000006020 #define ADDR_WCI_MONITOR_PINS 0x00000006040 #define ADDR_WCI_SRAM_CONFIG 0x00000010000 #define ADDR_WCI_CLUSTER_MEMBERS_BITS 0x00000010080 #define ENTRIES_WCI_CLUSTER_MEMBERS_BITS 0x4 #define STRIDE_WCI_CLUSTER_MEMBERS_BITS 0x20 #define ADDR_WCI_NC_SLICE_CONFIG_ARRAY 0x00000010200 #define ENTRIES_WCI_NC_SLICE_CONFIG_ARRAY 0x8 #define STRIDE_WCI_NC_SLICE_CONFIG_ARRAY 0x20 #define ADDR_WCI_CLUSTER_CTR_CTL 0x00000010300 #define ADDR_WCI_SRAM_STATUS 0x00000010320 #define ADDR_WCI_SRAM_CE_COUNT 0x00000010340 #define ADDR_WCI_SRAM_ECC_ADDRESS 0x00000010360 #define ADDR_WCI_CCI_ESR 0x00000010380 #define ADDR_WCI_CCI_ESR_MASK 0x000000103a0 #define ADDR_WCI_CCI_ROUTE_MAP0 0x000000103c0 #define ADDR_WCI_CCI_ROUTE_MAP1 0x000000103e0 #define ADDR_WCI_CLUSTER_WRITE_LOCKOUT 0x00000010480 #define ENTRIES_WCI_CLUSTER_WRITE_LOCKOUT 0x4 #define STRIDE_WCI_CLUSTER_WRITE_LOCKOUT 0x20 #define ADDR_WCI_CLUSTER_CONFIG 0x00000020000 #define ADDR_WCI_CA_FREEZE 0x00000020020 #define ADDR_WCI_CA_BUSY 0x00000020040 #define ADDR_WCI_CA_FIRST_PACKET_0 0x00000020060 #define ADDR_WCI_CA_FIRST_PACKET_1 0x00000020080 #define ADDR_WCI_CA_ECC_ADDRESS 0x000000200a0 #define ADDR_WCI_CA_ERROR_TRANSACTION 0x000000200c0 #define ADDR_WCI_CA_TIMEOUT_CONFIG 0x000000200e0 #define ADDR_WCI_CA_CONFIG 0x00000020100 #define ADDR_WCI_CA_ESR_0 0x00000020120 #define ADDR_WCI_CA_ESR_1 0x00000020140 #define ADDR_WCI_CA_ESR_MASK 0x00000020160 #define ADDR_WCI_CLUSTER_SYNC 0x00000020180 #define ADDR_WCI_CA_TIMEOUT_CONFIG_2 0x000000201a0 #define ADDR_WCI_CA_ERROR_TRANSACTION_2 0x000000201c0 #define ADDR_WCI_QLIM_CONFIG_CAG 0x000000201e0 #define ADDR_WCI_QLIM_CAG_TIMER 0x00000020200 #define ADDR_WCI_BOARD2CNID_ARRAY 0x00000030000 #define ENTRIES_WCI_BOARD2CNID_ARRAY 0x38 #define STRIDE_WCI_BOARD2CNID_ARRAY 0x20 #define ADDR_WCI_INID2DNID_ARRAY 0x00000030800 #define ENTRIES_WCI_INID2DNID_ARRAY 0x40 #define STRIDE_WCI_INID2DNID_ARRAY 0x20 #define ADDR_WCI_RA_FREEZE 0x00000031000 #define ADDR_WCI_RA_BUSY 0x00000031020 #define ADDR_WCI_RA_FIRST_ERROR_AGENT 0x00000031040 #define ADDR_WCI_RA_FIRST_PACKET_0 0x00000031060 #define ADDR_WCI_RA_FIRST_PACKET_1 0x00000031080 #define ADDR_WCI_RA_ECC_ADDRESS 0x000000310a0 #define ADDR_WCI_RA_ERROR_TRANSACTION_0 0x000000310c0 #define ADDR_WCI_RA_ERROR_TRANSACTION_1 0x000000310e0 #define ADDR_WCI_RA_TIMEOUT_CONFIG 0x00000031100 #define ADDR_WCI_RA_ESR_0 0x00000031120 #define ADDR_WCI_RA_ESR_1 0x00000031140 #define ADDR_WCI_RA_ESR_MASK 0x00000031160 #define ADDR_WCI_RA_STATUS_ARRAY 0x00000031400 #define ENTRIES_WCI_RA_STATUS_ARRAY 0x20 #define STRIDE_WCI_RA_STATUS_ARRAY 0x20 #define ADDR_WCI_RA_STATUS_2_ARRAY 0x00000031800 #define ENTRIES_WCI_RA_STATUS_2_ARRAY 0x20 #define STRIDE_WCI_RA_STATUS_2_ARRAY 0x20 #define ADDR_WCI_RA_WRITE_LOCKOUT_STATUS 0x00000031c00 #define ADDR_WCI_RAG_ROUTE_MAP0 0x00000031c20 #define ADDR_WCI_RAG_ROUTE_MAP1 0x00000031c40 #define ADDR_WCI_CLUSTER_ERROR_STATUS_ARRAY 0x00000032000 #define ENTRIES_WCI_CLUSTER_ERROR_STATUS_ARRAY 0x100 #define STRIDE_WCI_CLUSTER_ERROR_STATUS_ARRAY 0x20 #define ADDR_WCI_CLUSTER_ERROR_COUNT 0x00000034000 #define ADDR_WCI_INT_DEST_BUSY_COUNT 0x00000034020 #define ADDR_WCI_QLIM_3REQ_PRIORITY 0x00000034040 #define ADDR_WCI_QLIM_2REQ_PRIORITY 0x00000034060 #define ADDR_WCI_QLIM_CONFIG_PIQ 0x00000034080 #define ADDR_WCI_QLIM_CONFIG_NIQ 0x000000340a0 #define ADDR_WCI_QLIM_CONFIG_CIQ 0x000000340c0 #define ADDR_WCI_QLIM_PIQ_TIMER 0x000000340e0 #define ADDR_WCI_QLIM_NIQ_TIMER 0x00000034100 #define ADDR_WCI_QLIM_CIQ_TIMER 0x00000034120 #define ADDR_WCI_OS_CLUSTER_DISABLE 0x00000034140 #define ADDR_WCI_SC_CLUSTER_DISABLE 0x00000034160 #define ADDR_WCI_HA_FREEZE 0x00000040000 #define ADDR_WCI_HA_BUSY 0x00000040020 #define ADDR_WCI_HA_FIRST_ERROR_AGENT 0x00000040040 #define ADDR_WCI_HA_FIRST_PACKET_0 0x00000040060 #define ADDR_WCI_HA_FIRST_PACKET_1 0x00000040080 #define ADDR_WCI_HA_ECC_ADDRESS 0x000000400a0 #define ADDR_WCI_HA_ERROR_ADDRESS 0x000000400c0 #define ADDR_WCI_HA_TIMEOUT_CONFIG 0x000000400e0 #define ADDR_WCI_HA_ESR_0 0x00000040100 #define ADDR_WCI_HA_ESR_1 0x00000040120 #define ADDR_WCI_HA_HW_ERR_STATUS 0x00000040140 #define ADDR_WCI_HA_ESR_MASK 0x00000040160 #define ADDR_WCI_PROBE_MEMORY 0x00000040180 #define ADDR_WCI_HA_STATUS_ARRAY 0x00000040200 #define ENTRIES_WCI_HA_STATUS_ARRAY 0x10 #define STRIDE_WCI_HA_STATUS_ARRAY 0x20 #define ADDR_WCI_HA_STATUS_2_ARRAY 0x00000040400 #define ENTRIES_WCI_HA_STATUS_2_ARRAY 0x10 #define STRIDE_WCI_HA_STATUS_2_ARRAY 0x20 #define ADDR_WCI_HA_CONFIG 0x00000040600 #define ADDR_WCI_HAG_ROUTE_MAP0 0x00000040620 #define ADDR_WCI_HAG_ROUTE_MAP1 0x00000040640 #define ADDR_WCI_EMISS_CNTL_ARRAY 0x00000042000 #define ENTRIES_WCI_EMISS_CNTL_ARRAY 0x10 #define STRIDE_WCI_EMISS_CNTL_ARRAY 0x20 #define ADDR_WCI_EMISS_DATA_ARRAY 0x00000042200 #define ENTRIES_WCI_EMISS_DATA_ARRAY 0x10 #define STRIDE_WCI_EMISS_DATA_ARRAY 0x20 #define ADDR_WCI_EMISS_RESET_CTL 0x00000042400 #define ADDR_WCI_GLOBAL_EMISS_COUNTER 0x00000042420 #define ADDR_WCI_SA_FREEZE 0x00000050000 #define ADDR_WCI_SA_BUSY 0x00000050020 #define ADDR_WCI_SA_FIRST_ERROR_AGENT 0x00000050040 #define ADDR_WCI_SA_FIRST_PACKET_0 0x00000050060 #define ADDR_WCI_SA_FIRST_PACKET_1 0x00000050080 #define ADDR_WCI_SA_ECC_ADDRESS 0x000000500a0 #define ADDR_WCI_SA_TIMEOUT_CONFIG 0x000000500c0 #define ADDR_WCI_SA_ESR_0 0x000000500e0 #define ADDR_WCI_SA_HW_ERR_STATE 0x00000050100 #define ADDR_WCI_SA_ESR_MASK 0x00000050120 #define ADDR_WCI_SA_STATUS_ARRAY 0x00000050200 #define ENTRIES_WCI_SA_STATUS_ARRAY 0x8 #define STRIDE_WCI_SA_STATUS_ARRAY 0x20 #define ADDR_WCI_SA_STATUS_2_ARRAY 0x00000050300 #define ENTRIES_WCI_SA_STATUS_2_ARRAY 0x8 #define STRIDE_WCI_SA_STATUS_2_ARRAY 0x20 #define ADDR_WCI_SA_STATUS_3_ARRAY 0x00000050400 #define ENTRIES_WCI_SA_STATUS_3_ARRAY 0x8 #define STRIDE_WCI_SA_STATUS_3_ARRAY 0x20 #define ADDR_WCI_SA_STATUS_4_ARRAY 0x00000050500 #define ENTRIES_WCI_SA_STATUS_4_ARRAY 0x8 #define STRIDE_WCI_SA_STATUS_4_ARRAY 0x20 #define ADDR_WCI_SA_STATUS_5_ARRAY 0x00000050600 #define ENTRIES_WCI_SA_STATUS_5_ARRAY 0x8 #define STRIDE_WCI_SA_STATUS_5_ARRAY 0x20 #define ADDR_WCI_SA_STATUS_6_ARRAY 0x00000050700 #define ENTRIES_WCI_SA_STATUS_6_ARRAY 0x8 #define STRIDE_WCI_SA_STATUS_6_ARRAY 0x20 #define ADDR_WCI_SAG_ROUTE_MAP0 0x00000050800 #define ADDR_WCI_SAG_ROUTE_MAP1 0x00000050820 #define ADDR_WCI_NC2NID_ARRAY 0x00000060000 #define ENTRIES_WCI_NC2NID_ARRAY 0x100 #define STRIDE_WCI_NC2NID_ARRAY 0x20 #define ADDR_WCI_SFI_TRANSID_ALLOC 0x00000062000 #define ADDR_WCI_SFI_ESR 0x00000062020 #define ADDR_WCI_SFI_ESR_MASK 0x00000062040 #define ADDR_WCI_SFI_STATE 0x00000062060 #define ADDR_WCI_SFI_STATE1 0x00000062080 #define ADDR_WCI_SFI_CTR1_MASK 0x00000064000 #define ADDR_WCI_SFI_CTR1_MATCH_TRANSACTION 0x00000064020 #define ADDR_WCI_SFI_CTR1_MATCH 0x00000064040 #define ADDR_WCI_SFI_CTR0_MASK 0x00000064060 #define ADDR_WCI_SFI_CTR0_MATCH_TRANSACTION 0x00000064080 #define ADDR_WCI_SFI_CTR0_MATCH 0x000000640a0 #define ADDR_WCI_SFI_ANALYZER 0x000000640c0 #define ADDR_WCI_SFI_ROUTE_MAP0 0x000000640e0 #define ADDR_WCI_SFI_ROUTE_MAP1 0x00000064100 #define ADDR_WCI_QLIM_SORT_PIQ 0x00000064120 #define ADDR_WCI_QLIM_SORT_NIQ 0x00000064140 #define ADDR_WCI_QLIM_SORT_CIQ 0x00000064160 #define ADDR_WCI_LINK_ESR 0x00000070000 #define ADDR_WCI_LINK_ESR_MASK 0x00000070100 #define ADDR_WCI_SW_ESR 0x00000070120 #define ADDR_WCI_SW_ESR_MASK 0x00000070140 #define ADDR_WCI_SW_LINK_CONTROL 0x00000070200 #define ENTRIES_WCI_SW_LINK_CONTROL 0x3 #define STRIDE_WCI_SW_LINK_CONTROL 0x20 #define ADDR_WCI_SW_LINK_ERROR_COUNT 0x00000070300 #define ENTRIES_WCI_SW_LINK_ERROR_COUNT 0x3 #define STRIDE_WCI_SW_LINK_ERROR_COUNT 0x20 #define ADDR_WCI_SW_LINK_STATUS 0x00000070400 #define ENTRIES_WCI_SW_LINK_STATUS 0x3 #define STRIDE_WCI_SW_LINK_STATUS 0x20 #define ADDR_WCI_SW_CONFIG 0x00000070500 #define ADDR_WCI_SW_STATUS 0x00000070520 #define ADDR_WCI_LINK_CTR_CTL 0x00000070600 #define ENTRIES_WCI_LINK_CTR_CTL 0x3 #define STRIDE_WCI_LINK_CTR_CTL 0x20 #define ADDR_WCI_LPBK_CTR_CTL 0x00000070700 #define ADDR_WCI_LINK_CTR 0x00000070800 #define ENTRIES_WCI_LINK_CTR 0x3 #define STRIDE_WCI_LINK_CTR 0x20 #define ADDR_WCI_LPBK_CTR 0x00000070900 #define ADDR_WCI_SW_ESR_A 0x00000070920 #define ADDR_WCI_SW_ESR_A_MASK 0x00000070940 #define ADDR_WCI_GNID_MAP0 0x00000070960 #define ADDR_WCI_GNID_MAP1 0x00000070980 #define ADDR_WCI_FO_ROUTE_MAP 0x000000709a0 #define ADDR_WCI_SEC_FO_ROUTE_MAP 0x000000709c0 #define ADDR_WCI_FO_TNID_MAP 0x000000709e0 #define ADDR_WCI_SW_LINK_REXMIT 0x00000070b00 #define ENTRIES_WCI_SW_LINK_REXMIT 0x3 #define STRIDE_WCI_SW_LINK_REXMIT 0x20 #define ADDR_WCI_DNID2GNID 0x00000070c00 #ifdef __cplusplus } #endif #endif /* _SYS_WCI_OFFSETS_H */