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| author | John Levon <john.levon@joyent.com> | 2018-01-28 22:05:38 +0000 |
|---|---|---|
| committer | Dan McDonald <danmcd@joyent.com> | 2018-04-10 10:36:59 -0400 |
| commit | 1d9a8ab82e5abe86cb1e43c502f88c7c655658fd (patch) | |
| tree | ed0c2ef6de1637afc88a84c67f78419cbf12dc6e | |
| parent | 399ca3a7ff315244c51a7bbd1d3ce2709ef6c7c6 (diff) | |
| download | illumos-joyent-1d9a8ab82e5abe86cb1e43c502f88c7c655658fd.tar.gz | |
9215 update CPUID defines
Reviewed by: Yuri Pankov <yuripv@yuripv.net>
Approved by: Gordon Ross <gwr@nexenta.com>
| -rw-r--r-- | usr/src/uts/intel/sys/x86_archext.h | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h index 5a548273a3..ed1e896792 100644 --- a/usr/src/uts/intel/sys/x86_archext.h +++ b/usr/src/uts/intel/sys/x86_archext.h @@ -27,7 +27,7 @@ * All rights reserved. */ /* - * Copyright 2017 Joyent, Inc. + * Copyright 2018 Joyent, Inc. * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> @@ -91,7 +91,7 @@ extern "C" { #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ - /* 0x00000004 - reserved */ +#define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ @@ -104,15 +104,16 @@ extern "C" { #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ - /* 0x00008000 - reserved */ +#define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ /* 0x00010000 - reserved */ - /* 0x00020000 - reserved */ +#define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ +#define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ @@ -170,9 +171,17 @@ extern "C" { #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ -#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ +#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */ #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ + /* 0x00004000 - reserved */ +#define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ +#define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ + /* 0x00020000 - reserved */ + /* 0x00040000 - reserved */ +#define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ + /* 0x00100000 - reserved */ +#define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ /* |