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authorRobert Mustacchi <rm@joyent.com>2018-06-14 15:55:36 +0000
committerRobert Mustacchi <rm@joyent.com>2018-06-19 21:15:14 +0000
commitf367310f219802eaffd224b4cdddf2133302efa6 (patch)
tree965da3edf9f832bb59b9b769b05d3376f34bff12
parent28a4d80723e5da0288e478dae17be1c0474d200e (diff)
downloadillumos-joyent-f367310f219802eaffd224b4cdddf2133302efa6.tar.gz
OS-7023 invalidate cache before microcode update
Reviewed by: John Levon <john.levon@joyent.com> Approved by: Joshua M. Clulow <jmc@joyent.com>
-rw-r--r--usr/src/uts/i86pc/os/microcode.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/usr/src/uts/i86pc/os/microcode.c b/usr/src/uts/i86pc/os/microcode.c
index e59bdb8530..afc48953f5 100644
--- a/usr/src/uts/i86pc/os/microcode.c
+++ b/usr/src/uts/i86pc/os/microcode.c
@@ -24,6 +24,7 @@
* Use is subject to license terms.
*
* Copyright 2012 Nexenta Systems, Inc. All rights reserved.
+ * Copyright (c) 2018, Joyent, Inc.
*/
#include <sys/asm_linkage.h>
@@ -754,8 +755,15 @@ ucode_write(xc_arg_t arg1, xc_arg_t unused2, xc_arg_t unused3)
return (0);
}
- if (!on_trap(&otd, OT_DATA_ACCESS))
+ if (!on_trap(&otd, OT_DATA_ACCESS)) {
+ /*
+ * On some platforms a cache invalidation is required for the
+ * ucode update to be successful due to the parts of the
+ * processor that the microcode is updating.
+ */
+ invalidate_cache();
wrmsr(ucode->write_msr, (uintptr_t)uusp->ucodep);
+ }
no_trap();
#endif
@@ -849,6 +857,12 @@ ucode_load_intel(ucode_file_t *ufp, cpu_ucode_info_t *uinfop, cpu_t *cp)
uus.new_rev = uinfop->cui_rev;
#else
kpreempt_disable();
+ /*
+ * On some platforms a cache invalidation is required for the
+ * ucode update to be successful due to the parts of the
+ * processor that the microcode is updating.
+ */
+ invalidate_cache();
wrmsr(ucode->write_msr, (uintptr_t)ucodefp->uf_body);
ucode->read_rev(uinfop);
kpreempt_enable();