12371 dis x86 EVEX prefix mishandled

12372 dis EVEX encoding SIB mishandled
12373 dis support for EVEX vaes instructions
12374 dis support for EVEX vpclmulqdq instructions
12375 dis support for gfni instructions
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Approved by: Joshua M. Clulow <josh@sysmgr.org>

14 files changed, 1543 insertions, 56 deletions

diff --git a/usr/src/common/dis/i386/dis_tables.c b/usr/src/common/dis/i386/dis_tables.c
index ddca678f1c..928fa51916 100644
--- a/usr/src/common/dis/i386/dis_tables.c
+++ b/usr/src/common/dis/i386/dis_tables.c
@@ -22,6 +22,7 @@
 /*
  * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
  * Copyright 2019 Joyent, Inc.
+ * Copyright 2020 Robert Mustacchi
  */
 
 /*
@@ -246,7 +247,8 @@ enum {
 	ADX,		/* ADX instructions, support REX.w, mod_rm->mod_reg */
 	EVEX_RX,	/* EVEX  mod_reg                      -> mod_rm */
 	EVEX_MX,	/* EVEX  mod_rm                       -> mod_reg */
-	EVEX_RMrX	/* EVEX  EVEX.vvvv, mod_rm            -> mod_reg */
+	EVEX_RMrX,	/* EVEX  EVEX.vvvv, mod_rm            -> mod_reg */
+	EVEX_RMRX	/* EVEX  EVEX.vvvv, mod_rm, imm8      -> mod_reg */
 };
 
 /*
@@ -343,7 +345,6 @@ enum {
 #define	TSZ(name, amode, sz)	{TERM, amode, name, 1, 0, 0, 0, 0}
 #define	TSaZ(name, amode, sz)	{TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2}
 #define	TSq(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q}
-#define	TSd(name, amode)	{TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5D}
 #define	TSZx(name, amode, sz)	{TERM, amode, name, 1, 1, 0, 0, 0}
 #define	TSZy(name, amode, sz)	{TERM, amode, name, 1, 0, 1, 0, 0}
 #define	INVALID			{TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
@@ -366,7 +367,6 @@ enum {
 #define	TSZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0}
 #define	TSaZ(name, amode, sz)	{TERM, amode, sz, 0, 0, 0, 0, 0, AVS2}
 #define	TSq(name, amode)	{TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q}
-#define	TSd(name, amode)	{TERM, amode, 0, 0, 0, 0, 0, 0, AVS5D}
 #define	TSZx(name, amode, sz)	{TERM, amode, sz, 1, 0, 0, 0}
 #define	TSZy(name, amode, sz)	{TERM, amode, sz, 0, 1, 0, 0}
 #define	INVALID			{TERM, UNKNOWN, 0, 0, 0, 0, 0}
@@ -1461,22 +1461,22 @@ const instable_t dis_opAVXF30F[256] = {
 };
 
 /*
- * Table for instructions with an EVEX prefix.
+ * Table for instructions with an EVEX prefix followed by 0F.
  */
-const instable_t dis_opAVX62[256] = {
+const instable_t dis_opEVEX0F[256] = {
 /*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
 
-/*  [10]  */	TSd("vmovup",EVEX_MX),	TSd("vmovup",EVEX_RX),	INVALID,		INVALID,
+/*  [10]  */	TNS("vmovups",EVEX_MX),	TNS("vmovups",EVEX_RX),	INVALID,		INVALID,
 /*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
 
 /*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
-/*  [28]  */	TSd("vmovap",EVEX_MX),	TSd("vmovap",EVEX_RX),	INVALID,		INVALID,
+/*  [28]  */	TNS("vmovaps",EVEX_MX),	TNS("vmovaps",EVEX_RX),	INVALID,		INVALID,
 /*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
 
 /*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
@@ -1489,20 +1489,105 @@ const instable_t dis_opAVX62[256] = {
 /*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
 
-/*  [50]  */	TNSZ("vpdpbusd",EVEX_RMrX,16),TNSZ("vpdpbusds",EVEX_RMrX,16),TNSZ("vpdpwssd",EVEX_RMrX,16),TNSZ("vpdpwssds",EVEX_RMrX,16),
-/*  [54]  */	TSd("vandp",EVEX_RMrX), TSd("vandnp",EVEX_RMrX), TSd("vorp",EVEX_RMrX),		TSd("vxorp",EVEX_RMrX),
+/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [54]  */	TNS("vandps",EVEX_RMrX),TNS("vandnps",EVEX_RMrX),TNS("vorps",EVEX_RMrX),TNS("vxorps",EVEX_RMrX),
+/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+};
+
+/*
+ * Decode tables for EVEX 66 0F
+ */
+const instable_t dis_opEVEX660F[256] = {
+/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [10]  */	TNS("vmovupd",EVEX_MX),	TNS("vmovupd",EVEX_RX),	INVALID,		INVALID,
+/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [28]  */	TNS("vmovapd",EVEX_MX),	TNS("vmovapd",EVEX_RX),	INVALID,		INVALID,
+/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [54]  */	TNS("vandpd",EVEX_RMrX),TNS("vandnpd",EVEX_RMrX),TNS("vorpd",EVEX_RMrX),TNS("vxorpd",EVEX_RMrX),
 /*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
 
 /*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
-/*  [6C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdq",EVEX_MX),
+/*  [6C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqa",EVEX_MX),
 
 /*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
-/*  [7C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdq",EVEX_RX),
+/*  [7C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqa",EVEX_RX),
 
 /*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
@@ -1545,6 +1630,334 @@ const instable_t dis_opAVX62[256] = {
 /*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
 };
 
+const instable_t dis_opEVEX660F38[256] = {
+/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [50]  */	TNSZ("vpdpbusd",EVEX_RMrX,16),TNSZ("vpdpbusds",EVEX_RMrX,16),TNSZ("vpdpwssd",EVEX_RMrX,16),TNSZ("vpdpwssds",EVEX_RMrX,16),
+/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [CC]  */	INVALID,		INVALID,		INVALID,		TNS("vgf2p8mulb",EVEX_RMrX),
+
+/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [DC]  */	TNSZ("vaesenc",EVEX_RMrX,16),TNSZ("vaesenclast",EVEX_RMrX,16),TNSZ("vaesdec",EVEX_RMrX,16),TNSZ("vaesdeclast",EVEX_RMrX,16),
+
+/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+};
+
+const instable_t dis_opEVEX660F3A[256] = {
+/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [44]  */	TNSZ("vpclmulqdq",EVEX_RMRX,16),INVALID,		INVALID,		INVALID,
+/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [6C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [7C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [8C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [CC]  */	INVALID,		INVALID,		TNS("vgf2p8affineqb",EVEX_RMRX),TNS("vgf2p8affineinvqb",EVEX_RMRX),
+
+/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+};
+
+
+const instable_t dis_opEVEXF20F[256] = {
+/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [6C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_MX),
+
+/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [7C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_RX),
+
+/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+};
+
+const instable_t dis_opEVEXF30F[256] = {
+/*  [00]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [04]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [08]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [10]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [14]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [18]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [1C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [20]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [24]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [28]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [2C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [30]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [34]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [38]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [3C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [40]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [44]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [48]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [4C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [50]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [54]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [58]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [5C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [60]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [64]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [68]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [6C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_MX),
+
+/*  [70]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [74]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [78]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [7C]  */	INVALID,		INVALID,		INVALID,		TNS("vmovdqu",EVEX_RX),
+
+/*  [80]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [84]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [88]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [0C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [90]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [94]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [98]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [9C]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [A0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [A4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [A8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [AC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [B0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [B4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [B8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [BC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [D8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [DC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [E0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [E4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [E8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [EC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+
+/*  [F0]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [F4]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [F8]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [FC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+};
 /*
  * The following two tables are used to encode crc32 and movbe
  * since they share the same opcodes.
@@ -1632,7 +2045,7 @@ const instable_t dis_op0F38[256] = {
 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [C8]  */	TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16),
-/*  [CC]  */	TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID,		INVALID,
+/*  [CC]  */	TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID,		TNS("gf2p8mulb",XMM_66r),
 
 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
@@ -1713,7 +2126,7 @@ const instable_t dis_opAVX660F38[256] = {
 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
-/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [CC]  */	INVALID,		INVALID,		INVALID,		TNS("vgf2p8mulb",VEX_RMrX),
 
 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
@@ -1794,7 +2207,7 @@ const instable_t dis_op0F3A[256] = {
 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
-/*  [CC]  */	TNSZ("sha1rnds4",XMMP,16),INVALID,		INVALID,		INVALID,
+/*  [CC]  */	TNSZ("sha1rnds4",XMMP,16),INVALID,		TNS("gf2p8affineqb",XMMP_66r),TNS("gf2p8affineinvqb",XMMP_66r),
 
 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
@@ -1876,7 +2289,7 @@ const instable_t dis_opAVX660F3A[256] = {
 /*  [C0]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [C4]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [C8]  */	INVALID,		INVALID,		INVALID,		INVALID,
-/*  [CC]  */	INVALID,		INVALID,		INVALID,		INVALID,
+/*  [CC]  */	INVALID,		INVALID,		TNS("vgf2p8affineqb",VEX_RMRX),TNS("vgf2p8affineinvqb",VEX_RMRX),
 
 /*  [D0]  */	INVALID,		INVALID,		INVALID,		INVALID,
 /*  [D4]  */	INVALID,		INVALID,		INVALID,		INVALID,
@@ -2669,45 +3082,36 @@ dtrace_evex_mnem_adjust(dis86_t *x, const instable_t *dp, uint_t vex_W,
     uint_t evex_byte2)
 {
 #ifdef DIS_TEXT
-	/* No adjustments needed for VNNI instructions. */
-	if (dp == &dis_opAVX62[0x50] || dp == &dis_opAVX62[0x51] ||
-	    dp == &dis_opAVX62[0x52] || dp == &dis_opAVX62[0x53]) {
-		return;
+	if (dp == &dis_opEVEX660F[0x7f] ||		/* vmovdqa */
+	    dp == &dis_opEVEX660F[0x6f]) {
+		(void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32",
+		    OPLEN);
 	}
 
-	if (dp == &dis_opAVX62[0x7f] ||		/* vmovdq */
-	    dp == &dis_opAVX62[0x6f]) {
-		/* Aligned or Unaligned? */
-		if ((evex_byte2 & 0x3) == 0x01) {
-			(void) strlcat(x->d86_mnem, "a", OPLEN);
-			(void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32",
-			    OPLEN);
-		} else {
-			(void) strlcat(x->d86_mnem, "u", OPLEN);
-			switch (evex_byte2 & 0x81) {
-			case 0x0:
-				(void) strlcat(x->d86_mnem, "32", OPLEN);
-				break;
-			case 0x1:
-				(void) strlcat(x->d86_mnem, "8", OPLEN);
-				break;
-			case 0x80:
-				(void) strlcat(x->d86_mnem, "64", OPLEN);
-				break;
-			case 0x81:
-				(void) strlcat(x->d86_mnem, "16", OPLEN);
-				break;
-			}
-		}
-	} else {
-		if (dp->it_avxsuf == AVS5Q) {
-			(void) strlcat(x->d86_mnem, vex_W != 0 ?  "q" : "d",
-			    OPLEN);
-		} else {
-			(void) strlcat(x->d86_mnem, vex_W != 0 ?  "d" : "s",
-			    OPLEN);
+	if (dp == &dis_opEVEXF20F[0x7f] ||		/* vmovdqu */
+	    dp == &dis_opEVEXF20F[0x6f] ||
+	    dp == &dis_opEVEXF30F[0x7f] ||
+	    dp == &dis_opEVEXF30F[0x6f]) {
+		switch (evex_byte2 & 0x81) {
+		case 0x0:
+			(void) strlcat(x->d86_mnem, "32", OPLEN);
+			break;
+		case 0x1:
+			(void) strlcat(x->d86_mnem, "8", OPLEN);
+			break;
+		case 0x80:
+			(void) strlcat(x->d86_mnem, "64", OPLEN);
+			break;
+		case 0x81:
+			(void) strlcat(x->d86_mnem, "16", OPLEN);
+			break;
 		}
 	}
+
+	if (dp->it_avxsuf == AVS5Q) {
+		(void) strlcat(x->d86_mnem, vex_W != 0 ?  "q" : "d",
+		    OPLEN);
+	}
 #endif
 }
 
@@ -3032,10 +3436,12 @@ dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex)
 	}
 
 	/*
-	 * 32 and 64 bit addressing modes are more complex since they
-	 * can involve an SIB (scaled index and base) byte to decode.
+	 * 32 and 64 bit addressing modes are more complex since they can
+	 * involve an SIB (scaled index and base) byte to decode. When using VEX
+	 * and EVEX encodings, the r_m indicator for a SIB may be offset by 8
+	 * and 24 (8 + 16) respectively.
 	 */
-	if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) {
+	if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8 || r_m == ESP_REGNO + 24) {
 		have_SIB = 1;
 		dtrace_get_SIB(x, &ss, &index, &base);
 		if (x->d86_error)
@@ -3296,6 +3702,7 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
 	uint_t vex_L = 0;
 	uint_t evex_L = 0;
 	uint_t evex_modrm = 0;
+	uint_t evex_prefix = 0;
 	dis_gather_regs_t *vreg;
 
 #ifdef	DIS_TEXT
@@ -3430,6 +3837,8 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
 	 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0.
 	 */
 	if (opcode1 == 0x6 && opcode2 == 0x2) {
+		evex_prefix = 0x62;
+
 		/*
 		 * An EVEX prefix is 4 bytes long, get the next 3 bytes.
 		 */
@@ -3486,10 +3895,60 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode)
 		vex_W = (opcode6 & VEX_W) >> 3;
 		vex_p = opcode7 & VEX_p;
 
+		/*
+		 * Store the corresponding prefix information for later use when
+		 * calculating the SIB.
+		 */
+		if ((evex_byte1 & VEX_R) == 0)
+			x->d86_rex_prefix |= REX_R;
+		if ((evex_byte1 & VEX_X) == 0)
+			x->d86_rex_prefix |= REX_X;
+		if ((evex_byte1 & VEX_B) == 0)
+			x->d86_rex_prefix |= REX_B;
+
 		/* Currently only 3 valid values for evex L'L: 00, 01, 10 */
 		evex_L = (opcode8 & EVEX_L) >> 1;
 
-		dp = (instable_t *)&dis_opAVX62[(opcode1 << 4) | opcode2];
+		switch (vex_p) {
+		case VEX_p_66:
+			switch (vex_m) {
+			case VEX_m_0F:
+				dp = &dis_opEVEX660F[(opcode1 << 4) | opcode2];
+				break;
+			case VEX_m_0F38:
+				dp = &dis_opEVEX660F38[(opcode1 << 4) |
+				    opcode2];
+				break;
+			case VEX_m_0F3A:
+				dp = &dis_opEVEX660F3A[(opcode1 << 4) |
+				    opcode2];
+				break;
+			default:
+				goto error;
+			}
+			break;
+		case VEX_p_F3:
+			switch (vex_m) {
+			case VEX_m_0F:
+				dp = &dis_opEVEXF30F[(opcode1 << 4) | opcode2];
+				break;
+			default:
+				goto error;
+			}
+			break;
+		case VEX_p_F2:
+			switch (vex_m) {
+			case VEX_m_0F:
+				dp = &dis_opEVEXF20F[(opcode1 << 4) | opcode2];
+				break;
+			default:
+				goto error;
+			}
+			break;
+		default:
+			dp = &dis_opEVEX0F[(opcode1 << 4) | opcode2];
+			break;
+		}
 	}
 not_avx512:
 
@@ -4171,7 +4630,7 @@ not_avx512:
 	/*
 	 * In vex mode the rex_prefix has no meaning
 	 */
-	if (!vex_prefix)
+	if (!vex_prefix && evex_prefix == 0)
 		x->d86_rex_prefix = rex_prefix;
 	x->d86_opnd_size = opnd_size;
 	x->d86_addr_size = addr_size;
@@ -5909,6 +6368,29 @@ L_VEX_RM:
 		dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm);
 		dtrace_evex_adjust_z_opmask(x, 2, evex_byte3);
 		break;
+	case EVEX_RMRX:
+		/* ModR/M.reg := op(EVEX.vvvv, ModR/M.r_m, imm8) */
+		x->d86_numopnds = 4;
+
+		dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2);
+		dtrace_get_modrm(x, &mode, &reg, &r_m);
+		evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff;
+		dtrace_evex_adjust_reg(evex_byte1, &reg);
+		dtrace_evex_adjust_rm(evex_byte1, &r_m);
+		dtrace_evex_adjust_reg_name(evex_L, &wbit);
+		dtrace_get_operand(x, REG_ONLY, reg, wbit, 3);
+		/*
+		 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the
+		 * register specifier). The EVEX prefix handling uses the vex_v
+		 * variable for these bits.
+		 */
+		dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2);
+		dtrace_get_operand(x, mode, r_m, wbit, 1);
+		dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm);
+		dtrace_evex_adjust_z_opmask(x, 3, evex_byte3);
+
+		dtrace_imm_opnd(x, wbit, 1, 0);
+		break;
 	/* an invalid op code */
 	case AM:
 	case DM:
@@ -6179,7 +6661,6 @@ dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf,
 				save_mask = mask;
 			}
 			(void) strlcat(buf, op->d86_opnd, buflen);
-
 			break;
 
 		case MODE_IPREL:
diff --git a/usr/src/pkg/manifests/system-test-utiltest.mf b/usr/src/pkg/manifests/system-test-utiltest.mf
index 58174802a5..2a23e780a5 100644
--- a/usr/src/pkg/manifests/system-test-utiltest.mf
+++ b/usr/src/pkg/manifests/system-test-utiltest.mf
@@ -1173,6 +1173,8 @@ file path=opt/util-tests/tests/dis/i386/32.avx512.out mode=0444
 file path=opt/util-tests/tests/dis/i386/32.avx512.s mode=0444
 file path=opt/util-tests/tests/dis/i386/32.avx512_vnni.out mode=0444
 file path=opt/util-tests/tests/dis/i386/32.avx512_vnni.s mode=0444
+file path=opt/util-tests/tests/dis/i386/32.avx512_vpclmulqdq.out mode=0444
+file path=opt/util-tests/tests/dis/i386/32.avx512_vpclmulqdq.s mode=0444
 file path=opt/util-tests/tests/dis/i386/32.bmi1.out mode=0444
 file path=opt/util-tests/tests/dis/i386/32.bmi1.s mode=0444
 file path=opt/util-tests/tests/dis/i386/32.bmi2.out mode=0444
@@ -1189,6 +1191,8 @@ file path=opt/util-tests/tests/dis/i386/32.fma-sd.out mode=0444
 file path=opt/util-tests/tests/dis/i386/32.fma-sd.s mode=0444
 file path=opt/util-tests/tests/dis/i386/32.fma-ss.out mode=0444
 file path=opt/util-tests/tests/dis/i386/32.fma-ss.s mode=0444
+file path=opt/util-tests/tests/dis/i386/32.gfni.out mode=0444
+file path=opt/util-tests/tests/dis/i386/32.gfni.s mode=0444
 file path=opt/util-tests/tests/dis/i386/32.lzcnt.out mode=0444
 file path=opt/util-tests/tests/dis/i386/32.lzcnt.s mode=0444
 file path=opt/util-tests/tests/dis/i386/32.movbe.out mode=0444
@@ -1209,6 +1213,8 @@ file path=opt/util-tests/tests/dis/i386/32.sse-4.2.out mode=0444
 file path=opt/util-tests/tests/dis/i386/32.sse-4.2.s mode=0444
 file path=opt/util-tests/tests/dis/i386/32.ssse3.out mode=0444
 file path=opt/util-tests/tests/dis/i386/32.ssse3.s mode=0444
+file path=opt/util-tests/tests/dis/i386/32.vaes.out mode=0444
+file path=opt/util-tests/tests/dis/i386/32.vaes.s mode=0444
 file path=opt/util-tests/tests/dis/i386/32.xsave.out mode=0444
 file path=opt/util-tests/tests/dis/i386/32.xsave.s mode=0444
 file path=opt/util-tests/tests/dis/i386/64.adx.out mode=0444
@@ -1225,6 +1231,8 @@ file path=opt/util-tests/tests/dis/i386/64.avx512.out mode=0444
 file path=opt/util-tests/tests/dis/i386/64.avx512.s mode=0444
 file path=opt/util-tests/tests/dis/i386/64.avx512_vnni.out mode=0444
 file path=opt/util-tests/tests/dis/i386/64.avx512_vnni.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.avx512_vpclmulqdq.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.avx512_vpclmulqdq.s mode=0444
 file path=opt/util-tests/tests/dis/i386/64.bmi1.out mode=0444
 file path=opt/util-tests/tests/dis/i386/64.bmi1.s mode=0444
 file path=opt/util-tests/tests/dis/i386/64.bmi2.out mode=0444
@@ -1245,6 +1253,8 @@ file path=opt/util-tests/tests/dis/i386/64.fma-ss.out mode=0444
 file path=opt/util-tests/tests/dis/i386/64.fma-ss.s mode=0444
 file path=opt/util-tests/tests/dis/i386/64.fsbase.out mode=0444
 file path=opt/util-tests/tests/dis/i386/64.fsbase.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.gfni.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.gfni.s mode=0444
 file path=opt/util-tests/tests/dis/i386/64.lzcnt.out mode=0444
 file path=opt/util-tests/tests/dis/i386/64.lzcnt.s mode=0444
 file path=opt/util-tests/tests/dis/i386/64.movbe.out mode=0444
@@ -1267,6 +1277,8 @@ file path=opt/util-tests/tests/dis/i386/64.sse-4.2.out mode=0444
 file path=opt/util-tests/tests/dis/i386/64.sse-4.2.s mode=0444
 file path=opt/util-tests/tests/dis/i386/64.ssse3.out mode=0444
 file path=opt/util-tests/tests/dis/i386/64.ssse3.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.vaes.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.vaes.s mode=0444
 file path=opt/util-tests/tests/dis/i386/64.vmx.out mode=0444
 file path=opt/util-tests/tests/dis/i386/64.vmx.s mode=0444
 file path=opt/util-tests/tests/dis/i386/64.xsave.out mode=0444
diff --git a/usr/src/test/util-tests/tests/dis/i386/32.avx512_vpclmulqdq.out b/usr/src/test/util-tests/tests/dis/i386/32.avx512_vpclmulqdq.out
new file mode 100644
index 0000000000..fa7b7814f1
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/32.avx512_vpclmulqdq.out
@@ -0,0 +1,11 @@
+    libdis_test:      c4 e3 75 44 d0 23  vpclmulqdq $0x23,%ymm0,%ymm1,%ymm2
+    libdis_test+0x6:  c4 e3 65 44 a0 45  vpclmulqdq $0x42,0x12345(%eax),%ymm3,%ymm4
+                      23 01 00 42 
+    libdis_test+0x10: c4 e3 65 44 a4 8b  vpclmulqdq $-0x17,0x678(%ebx,%ecx,4),%ymm3,%ymm4	<0xe9>
+                      78 06 00 00 e9 
+    libdis_test+0x1b: 62 f3 75 48 44 d0  vpclmulqdq $0x23,%zmm0,%zmm1,%zmm2
+                      23 
+    libdis_test+0x22: 62 f3 65 48 44 a0  vpclmulqdq $0x42,0x12345(%eax),%zmm3,%zmm4
+                      45 23 01 00 42 
+    libdis_test+0x2d: 62 f3 65 48 44 a4  vpclmulqdq $-0x17,0x678(%ebx,%ecx,4),%zmm3,%zmm4	<0xe9>
+                      8b 78 06 00 00 e9 
diff --git a/usr/src/test/util-tests/tests/dis/i386/32.avx512_vpclmulqdq.s b/usr/src/test/util-tests/tests/dis/i386/32.avx512_vpclmulqdq.s
new file mode 100644
index 0000000000..d795517bdc
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/32.avx512_vpclmulqdq.s
@@ -0,0 +1,32 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source.  A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright 2020 Robert Mustacchi
+ */
+
+/*
+ * Test AVX512 vpclmulqdq related instructions
+ */
+
+.text
+.align 16
+.globl libdis_test
+.type libdis_test, @function
+libdis_test:
+	vpclmulqdq	$0x23, %ymm0, %ymm1, %ymm2
+	vpclmulqdq	$0x42, 0x12345(%eax), %ymm3, %ymm4
+	vpclmulqdq	$-0x17, 0x678(%ebx, %ecx, 4), %ymm3, %ymm4
+
+	vpclmulqdq	$0x23, %zmm0, %zmm1, %zmm2
+	vpclmulqdq	$0x42, 0x12345(%eax), %zmm3, %zmm4
+	vpclmulqdq	$-0x17, 0x678(%ebx, %ecx, 4), %zmm3, %zmm4
+.size libdis_test, [.-libdis_test]
diff --git a/usr/src/test/util-tests/tests/dis/i386/32.gfni.out b/usr/src/test/util-tests/tests/dis/i386/32.gfni.out
new file mode 100644
index 0000000000..4ea2c1c863
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/32.gfni.out
@@ -0,0 +1,205 @@
+    libdis_test:       66 0f 3a cf c8 23  gf2p8affineinvqb $0x23,%xmm0,%xmm1
+    libdis_test+0x6:   66 0f 3a cf 10 51  gf2p8affineinvqb $0x51,(%eax),%xmm2
+    libdis_test+0xc:   66 0f 3a cf 5b 12  gf2p8affineinvqb $0x19,0x12(%ebx),%xmm3
+                       19 
+    libdis_test+0x13:  66 0f 3a cf 64 91  gf2p8affineinvqb $0x77,0x12(%ecx,%edx,4),%xmm4
+                       12 77 
+    libdis_test+0x1b:  66 0f 3a ce f7 23  gf2p8affineqb $0x23,%xmm7,%xmm6
+    libdis_test+0x21:  66 0f 3a ce 28 51  gf2p8affineqb $0x51,(%eax),%xmm5
+    libdis_test+0x27:  66 0f 3a ce 63 12  gf2p8affineqb $0x19,0x12(%ebx),%xmm4
+                       19 
+    libdis_test+0x2e:  66 0f 3a ce 5c 91  gf2p8affineqb $0x77,0x12(%ecx,%edx,4),%xmm3
+                       12 77 
+    libdis_test+0x36:  66 0f 38 cf da     gf2p8mulb %xmm2,%xmm3
+    libdis_test+0x3b:  66 0f 38 cf 20     gf2p8mulb (%eax),%xmm4
+    libdis_test+0x40:  66 0f 38 cf 5b 12  gf2p8mulb 0x12(%ebx),%xmm3
+    libdis_test+0x46:  66 0f 38 cf 54 91  gf2p8mulb 0x17(%ecx,%edx,4),%xmm2
+                       17 
+    libdis_test+0x4d:  c4 e3 f1 cf e8 23  vgf2p8affineinvqb $0x23,%xmm0,%xmm1,%xmm5
+    libdis_test+0x53:  c4 e3 e9 cf 30 51  vgf2p8affineinvqb $0x51,(%eax),%xmm2,%xmm6
+    libdis_test+0x59:  c4 e3 e1 cf 7b 12  vgf2p8affineinvqb $0x19,0x12(%ebx),%xmm3,%xmm7
+                       19 
+    libdis_test+0x60:  c4 e3 d9 cf 44 91  vgf2p8affineinvqb $0x77,0x12(%ecx,%edx,4),%xmm4,%xmm0
+                       12 77 
+    libdis_test+0x68:  c4 e3 c9 ce c7 23  vgf2p8affineqb $0x23,%xmm7,%xmm6,%xmm0
+    libdis_test+0x6e:  c4 e3 d1 ce 08 51  vgf2p8affineqb $0x51,(%eax),%xmm5,%xmm1
+    libdis_test+0x74:  c4 e3 d9 ce 53 12  vgf2p8affineqb $0x19,0x12(%ebx),%xmm4,%xmm2
+                       19 
+    libdis_test+0x7b:  c4 e3 e1 ce 74 91  vgf2p8affineqb $0x77,0x12(%ecx,%edx,4),%xmm3,%xmm6
+                       12 77 
+    libdis_test+0x83:  c4 e2 61 cf c2     vgf2p8mulb %xmm2,%xmm3,%xmm0
+    libdis_test+0x88:  c4 e2 59 cf 08     vgf2p8mulb (%eax),%xmm4,%xmm1
+    libdis_test+0x8d:  c4 e2 61 cf 53 12  vgf2p8mulb 0x12(%ebx),%xmm3,%xmm2
+    libdis_test+0x93:  c4 e2 69 cf 5c 91  vgf2p8mulb 0x17(%ecx,%edx,4),%xmm2,%xmm3
+                       17 
+    libdis_test+0x9a:  c4 e3 f5 cf e8 23  vgf2p8affineinvqb $0x23,%ymm0,%ymm1,%ymm5
+    libdis_test+0xa0:  c4 e3 ed cf 30 51  vgf2p8affineinvqb $0x51,(%eax),%ymm2,%ymm6
+    libdis_test+0xa6:  c4 e3 e5 cf 7b 12  vgf2p8affineinvqb $0x19,0x12(%ebx),%ymm3,%ymm7
+                       19 
+    libdis_test+0xad:  c4 e3 dd cf 44 91  vgf2p8affineinvqb $0x77,0x12(%ecx,%edx,4),%ymm4,%ymm0
+                       12 77 
+    libdis_test+0xb5:  c4 e3 cd ce c7 23  vgf2p8affineqb $0x23,%ymm7,%ymm6,%ymm0
+    libdis_test+0xbb:  c4 e3 d5 ce 08 51  vgf2p8affineqb $0x51,(%eax),%ymm5,%ymm1
+    libdis_test+0xc1:  c4 e3 dd ce 53 12  vgf2p8affineqb $0x19,0x12(%ebx),%ymm4,%ymm2
+                       19 
+    libdis_test+0xc8:  c4 e3 e5 ce 74 91  vgf2p8affineqb $0x77,0x12(%ecx,%edx,4),%ymm3,%ymm6
+                       12 77 
+    libdis_test+0xd0:  c4 e2 65 cf c2     vgf2p8mulb %ymm2,%ymm3,%ymm0
+    libdis_test+0xd5:  c4 e2 5d cf 08     vgf2p8mulb (%eax),%ymm4,%ymm1
+    libdis_test+0xda:  c4 e2 65 cf 53 12  vgf2p8mulb 0x12(%ebx),%ymm3,%ymm2
+    libdis_test+0xe0:  c4 e2 6d cf 5c 91  vgf2p8mulb 0x17(%ecx,%edx,4),%ymm2,%ymm3
+                       17 
+    libdis_test+0xe7:  62 f3 f5 48 cf e8  vgf2p8affineinvqb $0x23,%zmm0,%zmm1,%zmm5
+                       23 
+    libdis_test+0xee:  62 f3 ed 48 cf 30  vgf2p8affineinvqb $0x51,(%eax),%zmm2,%zmm6
+                       51 
+    libdis_test+0xf5:  62 f3 e5 48 cf bb  vgf2p8affineinvqb $0x19,0x12(%ebx),%zmm3,%zmm7
+                       12 00 00 00 19 
+    libdis_test+0x100: 62 f3 dd 48 cf 84  vgf2p8affineinvqb $0x77,0x12(%ecx,%edx,4),%zmm4,%zmm0
+                       91 12 00 00 00 77 
+    libdis_test+0x10c: 62 f3 cd 48 ce c7  vgf2p8affineqb $0x23,%zmm7,%zmm6,%zmm0
+                       23 
+    libdis_test+0x113: 62 f3 d5 48 ce 08  vgf2p8affineqb $0x51,(%eax),%zmm5,%zmm1
+                       51 
+    libdis_test+0x11a: 62 f3 dd 48 ce 93  vgf2p8affineqb $0x19,0x12(%ebx),%zmm4,%zmm2
+                       12 00 00 00 19 
+    libdis_test+0x125: 62 f3 e5 48 ce b4  vgf2p8affineqb $0x77,0x12(%ecx,%edx,4),%zmm3,%zmm6
+                       91 12 00 00 00 77 
+    libdis_test+0x131: 62 f2 65 48 cf c2  vgf2p8mulb %zmm2,%zmm3,%zmm0
+    libdis_test+0x137: 62 f2 5d 48 cf 08  vgf2p8mulb (%eax),%zmm4,%zmm1
+    libdis_test+0x13d: 62 f2 65 48 cf 93  vgf2p8mulb 0x12(%ebx),%zmm3,%zmm2
+                       12 00 00 00 
+    libdis_test+0x147: 62 f2 6d 48 cf 9c  vgf2p8mulb 0x17(%ecx,%edx,4),%zmm2,%zmm3
+                       91 17 00 00 00 
+    libdis_test+0x152: 62 f3 f5 49 cf e8  vgf2p8affineinvqb $0x23,%zmm0,%zmm1,%zmm5{%k1}
+                       23 
+    libdis_test+0x159: 62 f3 f5 ca cf e8  vgf2p8affineinvqb $0x23,%zmm0,%zmm1,%zmm5{%k2}{z}
+                       23 
+    libdis_test+0x160: 62 f3 ed 4b cf 30  vgf2p8affineinvqb $0x51,(%eax),%zmm2,%zmm6{%k3}
+                       51 
+    libdis_test+0x167: 62 f3 ed cc cf 30  vgf2p8affineinvqb $0x51,(%eax),%zmm2,%zmm6{%k4}{z}
+                       51 
+    libdis_test+0x16e: 62 f3 e5 4d cf bb  vgf2p8affineinvqb $0x19,0x12(%ebx),%zmm3,%zmm7{%k5}
+                       12 00 00 00 19 
+    libdis_test+0x179: 62 f3 e5 ce cf bb  vgf2p8affineinvqb $0x19,0x12(%ebx),%zmm3,%zmm7{%k6}{z}
+                       12 00 00 00 19 
+    libdis_test+0x184: 62 f3 dd 4f cf 84  vgf2p8affineinvqb $0x77,0x12(%ecx,%edx,4),%zmm4,%zmm0{%k7}
+                       91 12 00 00 00 77 
+    libdis_test+0x190: 62 f3 dd cf cf 84  vgf2p8affineinvqb $0x77,0x12(%ecx,%edx,4),%zmm4,%zmm0{%k7}{z}
+                       91 12 00 00 00 77 
+    libdis_test+0x19c: 62 f3 cd 4f ce c7  vgf2p8affineqb $0x23,%zmm7,%zmm6,%zmm0{%k7}
+                       23 
+    libdis_test+0x1a3: 62 f3 cd ce ce c7  vgf2p8affineqb $0x23,%zmm7,%zmm6,%zmm0{%k6}{z}
+                       23 
+    libdis_test+0x1aa: 62 f3 d5 4d ce 08  vgf2p8affineqb $0x51,(%eax),%zmm5,%zmm1{%k5}
+                       51 
+    libdis_test+0x1b1: 62 f3 d5 cc ce 08  vgf2p8affineqb $0x51,(%eax),%zmm5,%zmm1{%k4}{z}
+                       51 
+    libdis_test+0x1b8: 62 f3 dd 4b ce 93  vgf2p8affineqb $0x19,0x12(%ebx),%zmm4,%zmm2{%k3}
+                       12 00 00 00 19 
+    libdis_test+0x1c3: 62 f3 dd ca ce 93  vgf2p8affineqb $0x19,0x12(%ebx),%zmm4,%zmm2{%k2}{z}
+                       12 00 00 00 19 
+    libdis_test+0x1ce: 62 f3 e5 49 ce b4  vgf2p8affineqb $0x77,0x12(%ecx,%edx,4),%zmm3,%zmm6{%k1}
+                       91 12 00 00 00 77 
+    libdis_test+0x1da: 62 f3 e5 ca ce b4  vgf2p8affineqb $0x77,0x12(%ecx,%edx,4),%zmm3,%zmm6{%k2}{z}
+                       91 12 00 00 00 77 
+    libdis_test+0x1e6: 62 f2 65 4b cf c2  vgf2p8mulb %zmm2,%zmm3,%zmm0{%k3}
+    libdis_test+0x1ec: 62 f2 65 ca cf c2  vgf2p8mulb %zmm2,%zmm3,%zmm0{%k2}{z}
+    libdis_test+0x1f2: 62 f2 5d 4c cf 08  vgf2p8mulb (%eax),%zmm4,%zmm1{%k4}
+    libdis_test+0x1f8: 62 f2 5d cd cf 08  vgf2p8mulb (%eax),%zmm4,%zmm1{%k5}{z}
+    libdis_test+0x1fe: 62 f2 65 49 cf 93  vgf2p8mulb 0x12(%ebx),%zmm3,%zmm2{%k1}
+                       12 00 00 00 
+    libdis_test+0x208: 62 f2 65 ca cf 93  vgf2p8mulb 0x12(%ebx),%zmm3,%zmm2{%k2}{z}
+                       12 00 00 00 
+    libdis_test+0x212: 62 f2 6d 4f cf 9c  vgf2p8mulb 0x17(%ecx,%edx,4),%zmm2,%zmm3{%k7}
+                       91 17 00 00 00 
+    libdis_test+0x21d: 62 f2 6d ce cf 9c  vgf2p8mulb 0x17(%ecx,%edx,4),%zmm2,%zmm3{%k6}{z}
+                       91 17 00 00 00 
+    libdis_test+0x228: 62 f3 f5 29 cf e8  vgf2p8affineinvqb $0x23,%ymm0,%ymm1,%ymm5{%k1}
+                       23 
+    libdis_test+0x22f: 62 f3 f5 aa cf e8  vgf2p8affineinvqb $0x23,%ymm0,%ymm1,%ymm5{%k2}{z}
+                       23 
+    libdis_test+0x236: 62 f3 ed 2b cf 30  vgf2p8affineinvqb $0x51,(%eax),%ymm2,%ymm6{%k3}
+                       51 
+    libdis_test+0x23d: 62 f3 ed ac cf 30  vgf2p8affineinvqb $0x51,(%eax),%ymm2,%ymm6{%k4}{z}
+                       51 
+    libdis_test+0x244: 62 f3 e5 2d cf bb  vgf2p8affineinvqb $0x19,0x12(%ebx),%ymm3,%ymm7{%k5}
+                       12 00 00 00 19 
+    libdis_test+0x24f: 62 f3 e5 ae cf bb  vgf2p8affineinvqb $0x19,0x12(%ebx),%ymm3,%ymm7{%k6}{z}
+                       12 00 00 00 19 
+    libdis_test+0x25a: 62 f3 dd 2f cf 84  vgf2p8affineinvqb $0x77,0x12(%ecx,%edx,4),%ymm4,%ymm0{%k7}
+                       91 12 00 00 00 77 
+    libdis_test+0x266: 62 f3 dd af cf 84  vgf2p8affineinvqb $0x77,0x12(%ecx,%edx,4),%ymm4,%ymm0{%k7}{z}
+                       91 12 00 00 00 77 
+    libdis_test+0x272: 62 f3 cd 2f ce c7  vgf2p8affineqb $0x23,%ymm7,%ymm6,%ymm0{%k7}
+                       23 
+    libdis_test+0x279: 62 f3 cd ae ce c7  vgf2p8affineqb $0x23,%ymm7,%ymm6,%ymm0{%k6}{z}
+                       23 
+    libdis_test+0x280: 62 f3 d5 2d ce 08  vgf2p8affineqb $0x51,(%eax),%ymm5,%ymm1{%k5}
+                       51 
+    libdis_test+0x287: 62 f3 d5 ac ce 08  vgf2p8affineqb $0x51,(%eax),%ymm5,%ymm1{%k4}{z}
+                       51 
+    libdis_test+0x28e: 62 f3 dd 2b ce 93  vgf2p8affineqb $0x19,0x12(%ebx),%ymm4,%ymm2{%k3}
+                       12 00 00 00 19 
+    libdis_test+0x299: 62 f3 dd aa ce 93  vgf2p8affineqb $0x19,0x12(%ebx),%ymm4,%ymm2{%k2}{z}
+                       12 00 00 00 19 
+    libdis_test+0x2a4: 62 f3 e5 29 ce b4  vgf2p8affineqb $0x77,0x12(%ecx,%edx,4),%ymm3,%ymm6{%k1}
+                       91 12 00 00 00 77 
+    libdis_test+0x2b0: 62 f3 e5 aa ce b4  vgf2p8affineqb $0x77,0x12(%ecx,%edx,4),%ymm3,%ymm6{%k2}{z}
+                       91 12 00 00 00 77 
+    libdis_test+0x2bc: 62 f2 65 2b cf c2  vgf2p8mulb %ymm2,%ymm3,%ymm0{%k3}
+    libdis_test+0x2c2: 62 f2 65 aa cf c2  vgf2p8mulb %ymm2,%ymm3,%ymm0{%k2}{z}
+    libdis_test+0x2c8: 62 f2 5d 2c cf 08  vgf2p8mulb (%eax),%ymm4,%ymm1{%k4}
+    libdis_test+0x2ce: 62 f2 5d ad cf 08  vgf2p8mulb (%eax),%ymm4,%ymm1{%k5}{z}
+    libdis_test+0x2d4: 62 f2 65 29 cf 93  vgf2p8mulb 0x12(%ebx),%ymm3,%ymm2{%k1}
+                       12 00 00 00 
+    libdis_test+0x2de: 62 f2 65 aa cf 93  vgf2p8mulb 0x12(%ebx),%ymm3,%ymm2{%k2}{z}
+                       12 00 00 00 
+    libdis_test+0x2e8: 62 f2 6d 2f cf 9c  vgf2p8mulb 0x17(%ecx,%edx,4),%ymm2,%ymm3{%k7}
+                       91 17 00 00 00 
+    libdis_test+0x2f3: 62 f2 6d ae cf 9c  vgf2p8mulb 0x17(%ecx,%edx,4),%ymm2,%ymm3{%k6}{z}
+                       91 17 00 00 00 
+    libdis_test+0x2fe: 62 f3 f5 09 cf e8  vgf2p8affineinvqb $0x23,%xmm0,%xmm1,%xmm5{%k1}
+                       23 
+    libdis_test+0x305: 62 f3 f5 8a cf e8  vgf2p8affineinvqb $0x23,%xmm0,%xmm1,%xmm5{%k2}{z}
+                       23 
+    libdis_test+0x30c: 62 f3 ed 0b cf 30  vgf2p8affineinvqb $0x51,(%eax),%xmm2,%xmm6{%k3}
+                       51 
+    libdis_test+0x313: 62 f3 ed 8c cf 30  vgf2p8affineinvqb $0x51,(%eax),%xmm2,%xmm6{%k4}{z}
+                       51 
+    libdis_test+0x31a: 62 f3 e5 0d cf bb  vgf2p8affineinvqb $0x19,0x12(%ebx),%xmm3,%xmm7{%k5}
+                       12 00 00 00 19 
+    libdis_test+0x325: 62 f3 e5 8e cf bb  vgf2p8affineinvqb $0x19,0x12(%ebx),%xmm3,%xmm7{%k6}{z}
+                       12 00 00 00 19 
+    libdis_test+0x330: 62 f3 dd 0f cf 84  vgf2p8affineinvqb $0x77,0x12(%ecx,%edx,4),%xmm4,%xmm0{%k7}
+                       91 12 00 00 00 77 
+    libdis_test+0x33c: 62 f3 dd 8f cf 84  vgf2p8affineinvqb $0x77,0x12(%ecx,%edx,4),%xmm4,%xmm0{%k7}{z}
+                       91 12 00 00 00 77 
+    libdis_test+0x348: 62 f3 cd 0f ce c7  vgf2p8affineqb $0x23,%xmm7,%xmm6,%xmm0{%k7}
+                       23 
+    libdis_test+0x34f: 62 f3 cd 8e ce c7  vgf2p8affineqb $0x23,%xmm7,%xmm6,%xmm0{%k6}{z}
+                       23 
+    libdis_test+0x356: 62 f3 d5 0d ce 08  vgf2p8affineqb $0x51,(%eax),%xmm5,%xmm1{%k5}
+                       51 
+    libdis_test+0x35d: 62 f3 d5 8c ce 08  vgf2p8affineqb $0x51,(%eax),%xmm5,%xmm1{%k4}{z}
+                       51 
+    libdis_test+0x364: 62 f3 dd 0b ce 93  vgf2p8affineqb $0x19,0x12(%ebx),%xmm4,%xmm2{%k3}
+                       12 00 00 00 19 
+    libdis_test+0x36f: 62 f3 dd 8a ce 93  vgf2p8affineqb $0x19,0x12(%ebx),%xmm4,%xmm2{%k2}{z}
+                       12 00 00 00 19 
+    libdis_test+0x37a: 62 f3 e5 09 ce b4  vgf2p8affineqb $0x77,0x12(%ecx,%edx,4),%xmm3,%xmm6{%k1}
+                       91 12 00 00 00 77 
+    libdis_test+0x386: 62 f3 e5 8a ce b4  vgf2p8affineqb $0x77,0x12(%ecx,%edx,4),%xmm3,%xmm6{%k2}{z}
+                       91 12 00 00 00 77 
+    libdis_test+0x392: 62 f2 65 0b cf c2  vgf2p8mulb %xmm2,%xmm3,%xmm0{%k3}
+    libdis_test+0x398: 62 f2 65 8a cf c2  vgf2p8mulb %xmm2,%xmm3,%xmm0{%k2}{z}
+    libdis_test+0x39e: 62 f2 5d 0c cf 08  vgf2p8mulb (%eax),%xmm4,%xmm1{%k4}
+    libdis_test+0x3a4: 62 f2 5d 8d cf 08  vgf2p8mulb (%eax),%xmm4,%xmm1{%k5}{z}
+    libdis_test+0x3aa: 62 f2 65 09 cf 93  vgf2p8mulb 0x12(%ebx),%xmm3,%xmm2{%k1}
+                       12 00 00 00 
+    libdis_test+0x3b4: 62 f2 65 8a cf 93  vgf2p8mulb 0x12(%ebx),%xmm3,%xmm2{%k2}{z}
+                       12 00 00 00 
+    libdis_test+0x3be: 62 f2 6d 0f cf 9c  vgf2p8mulb 0x17(%ecx,%edx,4),%xmm2,%xmm3{%k7}
+                       91 17 00 00 00 
+    libdis_test+0x3c9: 62 f2 6d 8e cf 9c  vgf2p8mulb 0x17(%ecx,%edx,4),%xmm2,%xmm3{%k6}{z}
+                       91 17 00 00 00 
diff --git a/usr/src/test/util-tests/tests/dis/i386/32.gfni.s b/usr/src/test/util-tests/tests/dis/i386/32.gfni.s
new file mode 100644
index 0000000000..a9bfa07aa8
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/32.gfni.s
@@ -0,0 +1,172 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source.  A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright 2020 Robert Mustacchi
+ */
+
+/*
+ * Test GFNI related instructions
+ */
+
+.text
+.align 16
+.globl libdis_test
+.type libdis_test, @function
+libdis_test:
+	/* SSE Form */
+	gf2p8affineinvqb	$0x23, %xmm0, %xmm1
+	gf2p8affineinvqb	$0x51, (%eax), %xmm2
+	gf2p8affineinvqb	$0x19, 0x12(%ebx), %xmm3
+	gf2p8affineinvqb	$0x77, 0x12(%ecx, %edx, 4), %xmm4
+
+	gf2p8affineqb		$0x23, %xmm7, %xmm6
+	gf2p8affineqb		$0x51, (%eax), %xmm5
+	gf2p8affineqb		$0x19, 0x12(%ebx), %xmm4
+	gf2p8affineqb		$0x77, 0x12(%ecx, %edx, 4), %xmm3
+
+	gf2p8mulb		%xmm2, %xmm3
+	gf2p8mulb		(%eax), %xmm4
+	gf2p8mulb		0x12(%ebx), %xmm3
+	gf2p8mulb		0x17(%ecx, %edx, 4), %xmm2
+
+	/* VEX Form - xmm */
+	vgf2p8affineinvqb	$0x23, %xmm0, %xmm1, %xmm5
+	vgf2p8affineinvqb	$0x51, (%eax), %xmm2, %xmm6
+	vgf2p8affineinvqb	$0x19, 0x12(%ebx), %xmm3, %xmm7
+	vgf2p8affineinvqb	$0x77, 0x12(%ecx, %edx, 4), %xmm4, %xmm0
+
+	vgf2p8affineqb		$0x23, %xmm7, %xmm6, %xmm0
+	vgf2p8affineqb		$0x51, (%eax), %xmm5, %xmm1
+	vgf2p8affineqb		$0x19, 0x12(%ebx), %xmm4, %xmm2
+	vgf2p8affineqb		$0x77, 0x12(%ecx, %edx, 4), %xmm3, %xmm6
+
+	vgf2p8mulb		%xmm2, %xmm3, %xmm0
+	vgf2p8mulb		(%eax), %xmm4, %xmm1
+	vgf2p8mulb		0x12(%ebx), %xmm3, %xmm2
+	vgf2p8mulb		0x17(%ecx, %edx, 4), %xmm2, %xmm3
+
+	/* VEX Form - ymm */
+	vgf2p8affineinvqb	$0x23, %ymm0, %ymm1, %ymm5
+	vgf2p8affineinvqb	$0x51, (%eax), %ymm2, %ymm6
+	vgf2p8affineinvqb	$0x19, 0x12(%ebx), %ymm3, %ymm7
+	vgf2p8affineinvqb	$0x77, 0x12(%ecx, %edx, 4), %ymm4, %ymm0
+
+	vgf2p8affineqb		$0x23, %ymm7, %ymm6, %ymm0
+	vgf2p8affineqb		$0x51, (%eax), %ymm5, %ymm1
+	vgf2p8affineqb		$0x19, 0x12(%ebx), %ymm4, %ymm2
+	vgf2p8affineqb		$0x77, 0x12(%ecx, %edx, 4), %ymm3, %ymm6
+
+	vgf2p8mulb		%ymm2, %ymm3, %ymm0
+	vgf2p8mulb		(%eax), %ymm4, %ymm1
+	vgf2p8mulb		0x12(%ebx), %ymm3, %ymm2
+	vgf2p8mulb		0x17(%ecx, %edx, 4), %ymm2, %ymm3
+
+	/* EVEX Form - basic zmm */
+	vgf2p8affineinvqb	$0x23, %zmm0, %zmm1, %zmm5
+	vgf2p8affineinvqb	$0x51, (%eax), %zmm2, %zmm6
+	vgf2p8affineinvqb	$0x19, 0x12(%ebx), %zmm3, %zmm7
+	vgf2p8affineinvqb	$0x77, 0x12(%ecx, %edx, 4), %zmm4, %zmm0
+
+	vgf2p8affineqb		$0x23, %zmm7, %zmm6, %zmm0
+	vgf2p8affineqb		$0x51, (%eax), %zmm5, %zmm1
+	vgf2p8affineqb		$0x19, 0x12(%ebx), %zmm4, %zmm2
+	vgf2p8affineqb		$0x77, 0x12(%ecx, %edx, 4), %zmm3, %zmm6
+
+	vgf2p8mulb		%zmm2, %zmm3, %zmm0
+	vgf2p8mulb		(%eax), %zmm4, %zmm1
+	vgf2p8mulb		0x12(%ebx), %zmm3, %zmm2
+	vgf2p8mulb		0x17(%ecx, %edx, 4), %zmm2, %zmm3
+
+	/* EVEX Form - zmm, masks */
+	vgf2p8affineinvqb	$0x23, %zmm0, %zmm1, %zmm5{%k1}
+	vgf2p8affineinvqb	$0x23, %zmm0, %zmm1, %zmm5{%k2}{z}
+	vgf2p8affineinvqb	$0x51, (%eax), %zmm2, %zmm6{%k3}
+	vgf2p8affineinvqb	$0x51, (%eax), %zmm2, %zmm6{%k4}{z}
+	vgf2p8affineinvqb	$0x19, 0x12(%ebx), %zmm3, %zmm7{%k5}
+	vgf2p8affineinvqb	$0x19, 0x12(%ebx), %zmm3, %zmm7{%k6}{z}
+	vgf2p8affineinvqb	$0x77, 0x12(%ecx, %edx, 4), %zmm4, %zmm0{%k7}
+	vgf2p8affineinvqb	$0x77, 0x12(%ecx, %edx, 4), %zmm4, %zmm0{%k7}{z}
+
+	vgf2p8affineqb		$0x23, %zmm7, %zmm6, %zmm0{%k7}
+	vgf2p8affineqb		$0x23, %zmm7, %zmm6, %zmm0{%k6}{z}
+	vgf2p8affineqb		$0x51, (%eax), %zmm5, %zmm1{%k5}
+	vgf2p8affineqb		$0x51, (%eax), %zmm5, %zmm1{%k4}{z}
+	vgf2p8affineqb		$0x19, 0x12(%ebx), %zmm4, %zmm2{%k3}
+	vgf2p8affineqb		$0x19, 0x12(%ebx), %zmm4, %zmm2{%k2}{z}
+	vgf2p8affineqb		$0x77, 0x12(%ecx, %edx, 4), %zmm3, %zmm6{%k1}
+	vgf2p8affineqb		$0x77, 0x12(%ecx, %edx, 4), %zmm3, %zmm6{%k2}{z}
+
+	vgf2p8mulb		%zmm2, %zmm3, %zmm0{%k3}
+	vgf2p8mulb		%zmm2, %zmm3, %zmm0{%k2}{z}
+	vgf2p8mulb		(%eax), %zmm4, %zmm1{%k4}
+	vgf2p8mulb		(%eax), %zmm4, %zmm1{%k5}{z}
+	vgf2p8mulb		0x12(%ebx), %zmm3, %zmm2{%k1}
+	vgf2p8mulb		0x12(%ebx), %zmm3, %zmm2{%k2}{z}
+	vgf2p8mulb		0x17(%ecx, %edx, 4), %zmm2, %zmm3{%k7}
+	vgf2p8mulb		0x17(%ecx, %edx, 4), %zmm2, %zmm3{%k6}{z}
+
+	/* EVEX Form - ymm, masks */
+	vgf2p8affineinvqb	$0x23, %ymm0, %ymm1, %ymm5{%k1}
+	vgf2p8affineinvqb	$0x23, %ymm0, %ymm1, %ymm5{%k2}{z}
+	vgf2p8affineinvqb	$0x51, (%eax), %ymm2, %ymm6{%k3}
+	vgf2p8affineinvqb	$0x51, (%eax), %ymm2, %ymm6{%k4}{z}
+	vgf2p8affineinvqb	$0x19, 0x12(%ebx), %ymm3, %ymm7{%k5}
+	vgf2p8affineinvqb	$0x19, 0x12(%ebx), %ymm3, %ymm7{%k6}{z}
+	vgf2p8affineinvqb	$0x77, 0x12(%ecx, %edx, 4), %ymm4, %ymm0{%k7}
+	vgf2p8affineinvqb	$0x77, 0x12(%ecx, %edx, 4), %ymm4, %ymm0{%k7}{z}
+
+	vgf2p8affineqb		$0x23, %ymm7, %ymm6, %ymm0{%k7}
+	vgf2p8affineqb		$0x23, %ymm7, %ymm6, %ymm0{%k6}{z}
+	vgf2p8affineqb		$0x51, (%eax), %ymm5, %ymm1{%k5}
+	vgf2p8affineqb		$0x51, (%eax), %ymm5, %ymm1{%k4}{z}
+	vgf2p8affineqb		$0x19, 0x12(%ebx), %ymm4, %ymm2{%k3}
+	vgf2p8affineqb		$0x19, 0x12(%ebx), %ymm4, %ymm2{%k2}{z}
+	vgf2p8affineqb		$0x77, 0x12(%ecx, %edx, 4), %ymm3, %ymm6{%k1}
+	vgf2p8affineqb		$0x77, 0x12(%ecx, %edx, 4), %ymm3, %ymm6{%k2}{z}
+
+	vgf2p8mulb		%ymm2, %ymm3, %ymm0{%k3}
+	vgf2p8mulb		%ymm2, %ymm3, %ymm0{%k2}{z}
+	vgf2p8mulb		(%eax), %ymm4, %ymm1{%k4}
+	vgf2p8mulb		(%eax), %ymm4, %ymm1{%k5}{z}
+	vgf2p8mulb		0x12(%ebx), %ymm3, %ymm2{%k1}
+	vgf2p8mulb		0x12(%ebx), %ymm3, %ymm2{%k2}{z}
+	vgf2p8mulb		0x17(%ecx, %edx, 4), %ymm2, %ymm3{%k7}
+	vgf2p8mulb		0x17(%ecx, %edx, 4), %ymm2, %ymm3{%k6}{z}
+
+	/* EVEX Form - ymm, masks */
+	vgf2p8affineinvqb	$0x23, %xmm0, %xmm1, %xmm5{%k1}
+	vgf2p8affineinvqb	$0x23, %xmm0, %xmm1, %xmm5{%k2}{z}
+	vgf2p8affineinvqb	$0x51, (%eax), %xmm2, %xmm6{%k3}
+	vgf2p8affineinvqb	$0x51, (%eax), %xmm2, %xmm6{%k4}{z}
+	vgf2p8affineinvqb	$0x19, 0x12(%ebx), %xmm3, %xmm7{%k5}
+	vgf2p8affineinvqb	$0x19, 0x12(%ebx), %xmm3, %xmm7{%k6}{z}
+	vgf2p8affineinvqb	$0x77, 0x12(%ecx, %edx, 4), %xmm4, %xmm0{%k7}
+	vgf2p8affineinvqb	$0x77, 0x12(%ecx, %edx, 4), %xmm4, %xmm0{%k7}{z}
+
+	vgf2p8affineqb		$0x23, %xmm7, %xmm6, %xmm0{%k7}
+	vgf2p8affineqb		$0x23, %xmm7, %xmm6, %xmm0{%k6}{z}
+	vgf2p8affineqb		$0x51, (%eax), %xmm5, %xmm1{%k5}
+	vgf2p8affineqb		$0x51, (%eax), %xmm5, %xmm1{%k4}{z}
+	vgf2p8affineqb		$0x19, 0x12(%ebx), %xmm4, %xmm2{%k3}
+	vgf2p8affineqb		$0x19, 0x12(%ebx), %xmm4, %xmm2{%k2}{z}
+	vgf2p8affineqb		$0x77, 0x12(%ecx, %edx, 4), %xmm3, %xmm6{%k1}
+	vgf2p8affineqb		$0x77, 0x12(%ecx, %edx, 4), %xmm3, %xmm6{%k2}{z}
+
+	vgf2p8mulb		%xmm2, %xmm3, %xmm0{%k3}
+	vgf2p8mulb		%xmm2, %xmm3, %xmm0{%k2}{z}
+	vgf2p8mulb		(%eax), %xmm4, %xmm1{%k4}
+	vgf2p8mulb		(%eax), %xmm4, %xmm1{%k5}{z}
+	vgf2p8mulb		0x12(%ebx), %xmm3, %xmm2{%k1}
+	vgf2p8mulb		0x12(%ebx), %xmm3, %xmm2{%k2}{z}
+	vgf2p8mulb		0x17(%ecx, %edx, 4), %xmm2, %xmm3{%k7}
+	vgf2p8mulb		0x17(%ecx, %edx, 4), %xmm2, %xmm3{%k6}{z}
+.size libdis_test, [.-libdis_test]
diff --git a/usr/src/test/util-tests/tests/dis/i386/32.vaes.out b/usr/src/test/util-tests/tests/dis/i386/32.vaes.out
new file mode 100644
index 0000000000..fdf2d813be
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/32.vaes.out
@@ -0,0 +1,24 @@
+    libdis_test:      c4 e2 71 dc d0     vaesenc %xmm0,%xmm1,%xmm2
+    libdis_test+0x5:  c4 e2 71 dc 10     vaesenc (%eax),%xmm1,%xmm2
+    libdis_test+0xa:  c4 e2 5d dc eb     vaesenc %ymm3,%ymm4,%ymm5
+    libdis_test+0xf:  c4 e2 5d dc 2b     vaesenc (%ebx),%ymm4,%ymm5
+    libdis_test+0x14: 62 f2 45 48 dc c6  vaesenc %zmm6,%zmm7,%zmm0
+    libdis_test+0x1a: 62 f2 45 48 dc 01  vaesenc (%ecx),%zmm7,%zmm0
+    libdis_test+0x20: c4 e2 71 dd d0     vaesenclast %xmm0,%xmm1,%xmm2
+    libdis_test+0x25: c4 e2 71 dd 10     vaesenclast (%eax),%xmm1,%xmm2
+    libdis_test+0x2a: c4 e2 5d dd eb     vaesenclast %ymm3,%ymm4,%ymm5
+    libdis_test+0x2f: c4 e2 5d dd 2b     vaesenclast (%ebx),%ymm4,%ymm5
+    libdis_test+0x34: 62 f2 45 48 dd c6  vaesenclast %zmm6,%zmm7,%zmm0
+    libdis_test+0x3a: 62 f2 45 48 dd 01  vaesenclast (%ecx),%zmm7,%zmm0
+    libdis_test+0x40: c4 e2 71 de d0     vaesdec %xmm0,%xmm1,%xmm2
+    libdis_test+0x45: c4 e2 71 de 10     vaesdec (%eax),%xmm1,%xmm2
+    libdis_test+0x4a: c4 e2 5d de eb     vaesdec %ymm3,%ymm4,%ymm5
+    libdis_test+0x4f: c4 e2 5d de 2b     vaesdec (%ebx),%ymm4,%ymm5
+    libdis_test+0x54: 62 f2 45 48 de c6  vaesdec %zmm6,%zmm7,%zmm0
+    libdis_test+0x5a: 62 f2 45 48 de 01  vaesdec (%ecx),%zmm7,%zmm0
+    libdis_test+0x60: c4 e2 71 df d0     vaesdeclast %xmm0,%xmm1,%xmm2
+    libdis_test+0x65: c4 e2 71 df 10     vaesdeclast (%eax),%xmm1,%xmm2
+    libdis_test+0x6a: c4 e2 5d df eb     vaesdeclast %ymm3,%ymm4,%ymm5
+    libdis_test+0x6f: c4 e2 5d df 2b     vaesdeclast (%ebx),%ymm4,%ymm5
+    libdis_test+0x74: 62 f2 45 48 df c6  vaesdeclast %zmm6,%zmm7,%zmm0
+    libdis_test+0x7a: 62 f2 45 48 df 01  vaesdeclast (%ecx),%zmm7,%zmm0
diff --git a/usr/src/test/util-tests/tests/dis/i386/32.vaes.s b/usr/src/test/util-tests/tests/dis/i386/32.vaes.s
new file mode 100644
index 0000000000..fcc1edd976
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/32.vaes.s
@@ -0,0 +1,52 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source.  A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright 2020 Robert Mustacchi
+ */
+
+/*
+ * Test VAES related instructions
+ */
+
+.text
+.align 16
+.globl libdis_test
+.type libdis_test, @function
+libdis_test:
+	vaesenc	%xmm0, %xmm1, %xmm2
+	vaesenc	(%eax), %xmm1, %xmm2
+	vaesenc	%ymm3, %ymm4, %ymm5
+	vaesenc	(%ebx), %ymm4, %ymm5
+	vaesenc	%zmm6, %zmm7, %zmm0
+	vaesenc	(%ecx), %zmm7, %zmm0
+
+	vaesenclast	%xmm0, %xmm1, %xmm2
+	vaesenclast	(%eax), %xmm1, %xmm2
+	vaesenclast	%ymm3, %ymm4, %ymm5
+	vaesenclast	(%ebx), %ymm4, %ymm5
+	vaesenclast	%zmm6, %zmm7, %zmm0
+	vaesenclast	(%ecx), %zmm7, %zmm0
+
+	vaesdec	%xmm0, %xmm1, %xmm2
+	vaesdec	(%eax), %xmm1, %xmm2
+	vaesdec	%ymm3, %ymm4, %ymm5
+	vaesdec	(%ebx), %ymm4, %ymm5
+	vaesdec	%zmm6, %zmm7, %zmm0
+	vaesdec	(%ecx), %zmm7, %zmm0
+
+	vaesdeclast	%xmm0, %xmm1, %xmm2
+	vaesdeclast	(%eax), %xmm1, %xmm2
+	vaesdeclast	%ymm3, %ymm4, %ymm5
+	vaesdeclast	(%ebx), %ymm4, %ymm5
+	vaesdeclast	%zmm6, %zmm7, %zmm0
+	vaesdeclast	(%ecx), %zmm7, %zmm0
+.size libdis_test, [.-libdis_test]
diff --git a/usr/src/test/util-tests/tests/dis/i386/64.avx512_vpclmulqdq.out b/usr/src/test/util-tests/tests/dis/i386/64.avx512_vpclmulqdq.out
new file mode 100644
index 0000000000..a98d4b9c5f
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/64.avx512_vpclmulqdq.out
@@ -0,0 +1,13 @@
+    libdis_test:      c4 43 25 44 e2 23  vpclmulqdq $0x23,%ymm10,%ymm11,%ymm12
+    libdis_test+0x6:  67 c4 63 15 44 b0  addr32 vpclmulqdq $0x42,0x12345(%rax),%ymm13,%ymm14
+                      45 23 01 00 42 
+    libdis_test+0x11: 67 62 e3 05 28 44  addr32 vpclmulqdq $-0x17,0x678(%rbx,%rcx,4),%ymm15,%ymm16	<0xe9>
+                      84 8b 78 06 00 00 
+                      e9 
+    libdis_test+0x1e: 62 53 25 48 44 d4  vpclmulqdq $0x23,%zmm12,%zmm11,%zmm10
+                      23 
+    libdis_test+0x25: 67 62 73 3d 48 44  addr32 vpclmulqdq $0x42,0x12345(%rax),%zmm8,%zmm8
+                      80 45 23 01 00 42 
+    libdis_test+0x31: 67 62 f3 45 48 44  addr32 vpclmulqdq $-0x17,0x678(%rbx,%rcx,4),%zmm7,%zmm6	<0xe9>
+                      b4 8b 78 06 00 00 
+                      e9 
diff --git a/usr/src/test/util-tests/tests/dis/i386/64.avx512_vpclmulqdq.s b/usr/src/test/util-tests/tests/dis/i386/64.avx512_vpclmulqdq.s
new file mode 100644
index 0000000000..26ddfe1e08
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/64.avx512_vpclmulqdq.s
@@ -0,0 +1,32 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source.  A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright 2020 Robert Mustacchi
+ */
+
+/*
+ * Test AVX512 vpclmulqdq related instructions
+ */
+
+.text
+.align 16
+.globl libdis_test
+.type libdis_test, @function
+libdis_test:
+	vpclmulqdq	$0x23, %ymm10, %ymm11, %ymm12
+	vpclmulqdq	$0x42, 0x12345(%eax), %ymm13, %ymm14
+	vpclmulqdq	$-0x17, 0x678(%ebx, %ecx, 4), %ymm15, %ymm16
+
+	vpclmulqdq	$0x23, %zmm12, %zmm11, %zmm10
+	vpclmulqdq	$0x42, 0x12345(%eax), %zmm8, %zmm8
+	vpclmulqdq	$-0x17, 0x678(%ebx, %ecx, 4), %zmm7, %zmm6
+.size libdis_test, [.-libdis_test]
diff --git a/usr/src/test/util-tests/tests/dis/i386/64.gfni.out b/usr/src/test/util-tests/tests/dis/i386/64.gfni.out
new file mode 100644
index 0000000000..42ddd4529b
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/64.gfni.out
@@ -0,0 +1,205 @@
+    libdis_test:       66 0f 3a cf c8 23  gf2p8affineinvqb $0x23,%xmm0,%xmm1
+    libdis_test+0x6:   66 0f 3a cf 10 51  gf2p8affineinvqb $0x51,(%rax),%xmm2
+    libdis_test+0xc:   66 0f 3a cf 5b 12  gf2p8affineinvqb $0x19,0x12(%rbx),%xmm3
+                       19 
+    libdis_test+0x13:  66 43 0f 3a cf 64  gf2p8affineinvqb $0x77,0x12(%r10,%r12,4),%xmm4
+                       a2 12 77 
+    libdis_test+0x1c:  66 0f 3a ce f7 23  gf2p8affineqb $0x23,%xmm7,%xmm6
+    libdis_test+0x22:  66 0f 3a ce 28 51  gf2p8affineqb $0x51,(%rax),%xmm5
+    libdis_test+0x28:  66 0f 3a ce 63 12  gf2p8affineqb $0x19,0x12(%rbx),%xmm4
+                       19 
+    libdis_test+0x2f:  66 43 0f 3a ce 5c  gf2p8affineqb $0x77,0x12(%r10,%r12,4),%xmm3
+                       a2 12 77 
+    libdis_test+0x38:  66 0f 38 cf da     gf2p8mulb %xmm2,%xmm3
+    libdis_test+0x3d:  66 0f 38 cf 20     gf2p8mulb (%rax),%xmm4
+    libdis_test+0x42:  66 0f 38 cf 5b 12  gf2p8mulb 0x12(%rbx),%xmm3
+    libdis_test+0x48:  66 43 0f 38 cf 54  gf2p8mulb 0x17(%r10,%r12,4),%xmm2
+                       a2 17 
+    libdis_test+0x50:  c4 e3 f1 cf e8 23  vgf2p8affineinvqb $0x23,%xmm0,%xmm1,%xmm5
+    libdis_test+0x56:  c4 e3 e9 cf 30 51  vgf2p8affineinvqb $0x51,(%rax),%xmm2,%xmm6
+    libdis_test+0x5c:  c4 e3 e1 cf 7b 12  vgf2p8affineinvqb $0x19,0x12(%rbx),%xmm3,%xmm7
+                       19 
+    libdis_test+0x63:  c4 83 d9 cf 44 a2  vgf2p8affineinvqb $0x77,0x12(%r10,%r12,4),%xmm4,%xmm0
+                       12 77 
+    libdis_test+0x6b:  c4 e3 c9 ce c7 23  vgf2p8affineqb $0x23,%xmm7,%xmm6,%xmm0
+    libdis_test+0x71:  c4 e3 d1 ce 08 51  vgf2p8affineqb $0x51,(%rax),%xmm5,%xmm1
+    libdis_test+0x77:  c4 e3 d9 ce 53 12  vgf2p8affineqb $0x19,0x12(%rbx),%xmm4,%xmm2
+                       19 
+    libdis_test+0x7e:  c4 83 e1 ce 74 a2  vgf2p8affineqb $0x77,0x12(%r10,%r12,4),%xmm3,%xmm6
+                       12 77 
+    libdis_test+0x86:  c4 e2 61 cf c2     vgf2p8mulb %xmm2,%xmm3,%xmm0
+    libdis_test+0x8b:  c4 e2 59 cf 08     vgf2p8mulb (%rax),%xmm4,%xmm1
+    libdis_test+0x90:  c4 e2 61 cf 53 12  vgf2p8mulb 0x12(%rbx),%xmm3,%xmm2
+    libdis_test+0x96:  c4 82 69 cf 5c a2  vgf2p8mulb 0x17(%r10,%r12,4),%xmm2,%xmm3
+                       17 
+    libdis_test+0x9d:  c4 e3 f5 cf e8 23  vgf2p8affineinvqb $0x23,%ymm0,%ymm1,%ymm5
+    libdis_test+0xa3:  c4 e3 ed cf 30 51  vgf2p8affineinvqb $0x51,(%rax),%ymm2,%ymm6
+    libdis_test+0xa9:  c4 e3 e5 cf 7b 12  vgf2p8affineinvqb $0x19,0x12(%rbx),%ymm3,%ymm7
+                       19 
+    libdis_test+0xb0:  c4 83 dd cf 44 a2  vgf2p8affineinvqb $0x77,0x12(%r10,%r12,4),%ymm4,%ymm0
+                       12 77 
+    libdis_test+0xb8:  c4 e3 cd ce c7 23  vgf2p8affineqb $0x23,%ymm7,%ymm6,%ymm0
+    libdis_test+0xbe:  c4 e3 d5 ce 08 51  vgf2p8affineqb $0x51,(%rax),%ymm5,%ymm1
+    libdis_test+0xc4:  c4 e3 dd ce 53 12  vgf2p8affineqb $0x19,0x12(%rbx),%ymm4,%ymm2
+                       19 
+    libdis_test+0xcb:  c4 83 e5 ce 74 a2  vgf2p8affineqb $0x77,0x12(%r10,%r12,4),%ymm3,%ymm6
+                       12 77 
+    libdis_test+0xd3:  c4 e2 65 cf c2     vgf2p8mulb %ymm2,%ymm3,%ymm0
+    libdis_test+0xd8:  c4 e2 5d cf 08     vgf2p8mulb (%rax),%ymm4,%ymm1
+    libdis_test+0xdd:  c4 e2 65 cf 53 12  vgf2p8mulb 0x12(%rbx),%ymm3,%ymm2
+    libdis_test+0xe3:  c4 82 6d cf 5c a2  vgf2p8mulb 0x17(%r10,%r12,4),%ymm2,%ymm3
+                       17 
+    libdis_test+0xea:  62 f3 f5 48 cf e8  vgf2p8affineinvqb $0x23,%zmm0,%zmm1,%zmm5
+                       23 
+    libdis_test+0xf1:  62 f3 ed 48 cf 30  vgf2p8affineinvqb $0x51,(%rax),%zmm2,%zmm6
+                       51 
+    libdis_test+0xf8:  62 f3 e5 48 cf bb  vgf2p8affineinvqb $0x19,0x12(%rbx),%zmm3,%zmm7
+                       12 00 00 00 19 
+    libdis_test+0x103: 62 93 dd 48 cf 84  vgf2p8affineinvqb $0x77,0x12(%r10,%r12,4),%zmm4,%zmm0
+                       a2 12 00 00 00 77 
+    libdis_test+0x10f: 62 f3 cd 48 ce c7  vgf2p8affineqb $0x23,%zmm7,%zmm6,%zmm0
+                       23 
+    libdis_test+0x116: 62 f3 d5 48 ce 08  vgf2p8affineqb $0x51,(%rax),%zmm5,%zmm1
+                       51 
+    libdis_test+0x11d: 62 f3 dd 48 ce 93  vgf2p8affineqb $0x19,0x12(%rbx),%zmm4,%zmm2
+                       12 00 00 00 19 
+    libdis_test+0x128: 62 93 e5 48 ce b4  vgf2p8affineqb $0x77,0x12(%r10,%r12,4),%zmm3,%zmm6
+                       a2 12 00 00 00 77 
+    libdis_test+0x134: 62 f2 65 48 cf c2  vgf2p8mulb %zmm2,%zmm3,%zmm0
+    libdis_test+0x13a: 62 f2 5d 48 cf 08  vgf2p8mulb (%rax),%zmm4,%zmm1
+    libdis_test+0x140: 62 f2 65 48 cf 93  vgf2p8mulb 0x12(%rbx),%zmm3,%zmm2
+                       12 00 00 00 
+    libdis_test+0x14a: 62 92 6d 48 cf 9c  vgf2p8mulb 0x17(%r10,%r12,4),%zmm2,%zmm3
+                       a2 17 00 00 00 
+    libdis_test+0x155: 62 f3 f5 49 cf e8  vgf2p8affineinvqb $0x23,%zmm0,%zmm1,%zmm5{%k1}
+                       23 
+    libdis_test+0x15c: 62 f3 f5 ca cf e8  vgf2p8affineinvqb $0x23,%zmm0,%zmm1,%zmm5{%k2}{z}
+                       23 
+    libdis_test+0x163: 62 f3 ed 4b cf 30  vgf2p8affineinvqb $0x51,(%rax),%zmm2,%zmm6{%k3}
+                       51 
+    libdis_test+0x16a: 62 f3 ed cc cf 30  vgf2p8affineinvqb $0x51,(%rax),%zmm2,%zmm6{%k4}{z}
+                       51 
+    libdis_test+0x171: 62 f3 e5 4d cf bb  vgf2p8affineinvqb $0x19,0x12(%rbx),%zmm3,%zmm7{%k5}
+                       12 00 00 00 19 
+    libdis_test+0x17c: 62 f3 e5 ce cf bb  vgf2p8affineinvqb $0x19,0x12(%rbx),%zmm3,%zmm7{%k6}{z}
+                       12 00 00 00 19 
+    libdis_test+0x187: 62 93 dd 4f cf 84  vgf2p8affineinvqb $0x77,0x12(%r10,%r12,4),%zmm4,%zmm0{%k7}
+                       a2 12 00 00 00 77 
+    libdis_test+0x193: 62 93 dd cf cf 84  vgf2p8affineinvqb $0x77,0x12(%r10,%r12,4),%zmm4,%zmm0{%k7}{z}
+                       a2 12 00 00 00 77 
+    libdis_test+0x19f: 62 f3 cd 4f ce c7  vgf2p8affineqb $0x23,%zmm7,%zmm6,%zmm0{%k7}
+                       23 
+    libdis_test+0x1a6: 62 f3 cd ce ce c7  vgf2p8affineqb $0x23,%zmm7,%zmm6,%zmm0{%k6}{z}
+                       23 
+    libdis_test+0x1ad: 62 f3 d5 4d ce 08  vgf2p8affineqb $0x51,(%rax),%zmm5,%zmm1{%k5}
+                       51 
+    libdis_test+0x1b4: 62 f3 d5 cc ce 08  vgf2p8affineqb $0x51,(%rax),%zmm5,%zmm1{%k4}{z}
+                       51 
+    libdis_test+0x1bb: 62 f3 dd 4b ce 93  vgf2p8affineqb $0x19,0x12(%rbx),%zmm4,%zmm2{%k3}
+                       12 00 00 00 19 
+    libdis_test+0x1c6: 62 f3 dd ca ce 93  vgf2p8affineqb $0x19,0x12(%rbx),%zmm4,%zmm2{%k2}{z}
+                       12 00 00 00 19 
+    libdis_test+0x1d1: 62 93 e5 49 ce b4  vgf2p8affineqb $0x77,0x12(%r10,%r12,4),%zmm3,%zmm6{%k1}
+                       a2 12 00 00 00 77 
+    libdis_test+0x1dd: 62 93 e5 ca ce b4  vgf2p8affineqb $0x77,0x12(%r10,%r12,4),%zmm3,%zmm6{%k2}{z}
+                       a2 12 00 00 00 77 
+    libdis_test+0x1e9: 62 f2 65 4b cf c2  vgf2p8mulb %zmm2,%zmm3,%zmm0{%k3}
+    libdis_test+0x1ef: 62 f2 65 ca cf c2  vgf2p8mulb %zmm2,%zmm3,%zmm0{%k2}{z}
+    libdis_test+0x1f5: 62 f2 5d 4c cf 08  vgf2p8mulb (%rax),%zmm4,%zmm1{%k4}
+    libdis_test+0x1fb: 62 f2 5d cd cf 08  vgf2p8mulb (%rax),%zmm4,%zmm1{%k5}{z}
+    libdis_test+0x201: 62 f2 65 49 cf 93  vgf2p8mulb 0x12(%rbx),%zmm3,%zmm2{%k1}
+                       12 00 00 00 
+    libdis_test+0x20b: 62 f2 65 ca cf 93  vgf2p8mulb 0x12(%rbx),%zmm3,%zmm2{%k2}{z}
+                       12 00 00 00 
+    libdis_test+0x215: 62 92 6d 4f cf 9c  vgf2p8mulb 0x17(%r10,%r12,4),%zmm2,%zmm3{%k7}
+                       a2 17 00 00 00 
+    libdis_test+0x220: 62 92 6d ce cf 9c  vgf2p8mulb 0x17(%r10,%r12,4),%zmm2,%zmm3{%k6}{z}
+                       a2 17 00 00 00 
+    libdis_test+0x22b: 62 f3 f5 29 cf e8  vgf2p8affineinvqb $0x23,%ymm0,%ymm1,%ymm5{%k1}
+                       23 
+    libdis_test+0x232: 62 f3 f5 aa cf e8  vgf2p8affineinvqb $0x23,%ymm0,%ymm1,%ymm5{%k2}{z}
+                       23 
+    libdis_test+0x239: 62 f3 ed 2b cf 30  vgf2p8affineinvqb $0x51,(%rax),%ymm2,%ymm6{%k3}
+                       51 
+    libdis_test+0x240: 62 f3 ed ac cf 30  vgf2p8affineinvqb $0x51,(%rax),%ymm2,%ymm6{%k4}{z}
+                       51 
+    libdis_test+0x247: 62 f3 e5 2d cf bb  vgf2p8affineinvqb $0x19,0x12(%rbx),%ymm3,%ymm7{%k5}
+                       12 00 00 00 19 
+    libdis_test+0x252: 62 f3 e5 ae cf bb  vgf2p8affineinvqb $0x19,0x12(%rbx),%ymm3,%ymm7{%k6}{z}
+                       12 00 00 00 19 
+    libdis_test+0x25d: 62 93 dd 2f cf 84  vgf2p8affineinvqb $0x77,0x12(%r10,%r12,4),%ymm4,%ymm0{%k7}
+                       a2 12 00 00 00 77 
+    libdis_test+0x269: 62 93 dd af cf 84  vgf2p8affineinvqb $0x77,0x12(%r10,%r12,4),%ymm4,%ymm0{%k7}{z}
+                       a2 12 00 00 00 77 
+    libdis_test+0x275: 62 f3 cd 2f ce c7  vgf2p8affineqb $0x23,%ymm7,%ymm6,%ymm0{%k7}
+                       23 
+    libdis_test+0x27c: 62 f3 cd ae ce c7  vgf2p8affineqb $0x23,%ymm7,%ymm6,%ymm0{%k6}{z}
+                       23 
+    libdis_test+0x283: 62 f3 d5 2d ce 08  vgf2p8affineqb $0x51,(%rax),%ymm5,%ymm1{%k5}
+                       51 
+    libdis_test+0x28a: 62 f3 d5 ac ce 08  vgf2p8affineqb $0x51,(%rax),%ymm5,%ymm1{%k4}{z}
+                       51 
+    libdis_test+0x291: 62 f3 dd 2b ce 93  vgf2p8affineqb $0x19,0x12(%rbx),%ymm4,%ymm2{%k3}
+                       12 00 00 00 19 
+    libdis_test+0x29c: 62 f3 dd aa ce 93  vgf2p8affineqb $0x19,0x12(%rbx),%ymm4,%ymm2{%k2}{z}
+                       12 00 00 00 19 
+    libdis_test+0x2a7: 62 93 e5 29 ce b4  vgf2p8affineqb $0x77,0x12(%r10,%r12,4),%ymm3,%ymm6{%k1}
+                       a2 12 00 00 00 77 
+    libdis_test+0x2b3: 62 93 e5 aa ce b4  vgf2p8affineqb $0x77,0x12(%r10,%r12,4),%ymm3,%ymm6{%k2}{z}
+                       a2 12 00 00 00 77 
+    libdis_test+0x2bf: 62 f2 65 2b cf c2  vgf2p8mulb %ymm2,%ymm3,%ymm0{%k3}
+    libdis_test+0x2c5: 62 f2 65 aa cf c2  vgf2p8mulb %ymm2,%ymm3,%ymm0{%k2}{z}
+    libdis_test+0x2cb: 62 f2 5d 2c cf 08  vgf2p8mulb (%rax),%ymm4,%ymm1{%k4}
+    libdis_test+0x2d1: 62 f2 5d ad cf 08  vgf2p8mulb (%rax),%ymm4,%ymm1{%k5}{z}
+    libdis_test+0x2d7: 62 f2 65 29 cf 93  vgf2p8mulb 0x12(%rbx),%ymm3,%ymm2{%k1}
+                       12 00 00 00 
+    libdis_test+0x2e1: 62 f2 65 aa cf 93  vgf2p8mulb 0x12(%rbx),%ymm3,%ymm2{%k2}{z}
+                       12 00 00 00 
+    libdis_test+0x2eb: 62 92 6d 2f cf 9c  vgf2p8mulb 0x17(%r10,%r12,4),%ymm2,%ymm3{%k7}
+                       a2 17 00 00 00 
+    libdis_test+0x2f6: 62 92 6d ae cf 9c  vgf2p8mulb 0x17(%r10,%r12,4),%ymm2,%ymm3{%k6}{z}
+                       a2 17 00 00 00 
+    libdis_test+0x301: 62 f3 f5 09 cf e8  vgf2p8affineinvqb $0x23,%xmm0,%xmm1,%xmm5{%k1}
+                       23 
+    libdis_test+0x308: 62 f3 f5 8a cf e8  vgf2p8affineinvqb $0x23,%xmm0,%xmm1,%xmm5{%k2}{z}
+                       23 
+    libdis_test+0x30f: 62 f3 ed 0b cf 30  vgf2p8affineinvqb $0x51,(%rax),%xmm2,%xmm6{%k3}
+                       51 
+    libdis_test+0x316: 62 f3 ed 8c cf 30  vgf2p8affineinvqb $0x51,(%rax),%xmm2,%xmm6{%k4}{z}
+                       51 
+    libdis_test+0x31d: 62 f3 e5 0d cf bb  vgf2p8affineinvqb $0x19,0x12(%rbx),%xmm3,%xmm7{%k5}
+                       12 00 00 00 19 
+    libdis_test+0x328: 62 f3 e5 8e cf bb  vgf2p8affineinvqb $0x19,0x12(%rbx),%xmm3,%xmm7{%k6}{z}
+                       12 00 00 00 19 
+    libdis_test+0x333: 62 93 dd 0f cf 84  vgf2p8affineinvqb $0x77,0x12(%r10,%r12,4),%xmm4,%xmm0{%k7}
+                       a2 12 00 00 00 77 
+    libdis_test+0x33f: 62 93 dd 8f cf 84  vgf2p8affineinvqb $0x77,0x12(%r10,%r12,4),%xmm4,%xmm0{%k7}{z}
+                       a2 12 00 00 00 77 
+    libdis_test+0x34b: 62 f3 cd 0f ce c7  vgf2p8affineqb $0x23,%xmm7,%xmm6,%xmm0{%k7}
+                       23 
+    libdis_test+0x352: 62 f3 cd 8e ce c7  vgf2p8affineqb $0x23,%xmm7,%xmm6,%xmm0{%k6}{z}
+                       23 
+    libdis_test+0x359: 62 f3 d5 0d ce 08  vgf2p8affineqb $0x51,(%rax),%xmm5,%xmm1{%k5}
+                       51 
+    libdis_test+0x360: 62 f3 d5 8c ce 08  vgf2p8affineqb $0x51,(%rax),%xmm5,%xmm1{%k4}{z}
+                       51 
+    libdis_test+0x367: 62 f3 dd 0b ce 93  vgf2p8affineqb $0x19,0x12(%rbx),%xmm4,%xmm2{%k3}
+                       12 00 00 00 19 
+    libdis_test+0x372: 62 f3 dd 8a ce 93  vgf2p8affineqb $0x19,0x12(%rbx),%xmm4,%xmm2{%k2}{z}
+                       12 00 00 00 19 
+    libdis_test+0x37d: 62 93 e5 09 ce b4  vgf2p8affineqb $0x77,0x12(%r10,%r12,4),%xmm3,%xmm6{%k1}
+                       a2 12 00 00 00 77 
+    libdis_test+0x389: 62 93 e5 8a ce b4  vgf2p8affineqb $0x77,0x12(%r10,%r12,4),%xmm3,%xmm6{%k2}{z}
+                       a2 12 00 00 00 77 
+    libdis_test+0x395: 62 f2 65 0b cf c2  vgf2p8mulb %xmm2,%xmm3,%xmm0{%k3}
+    libdis_test+0x39b: 62 f2 65 8a cf c2  vgf2p8mulb %xmm2,%xmm3,%xmm0{%k2}{z}
+    libdis_test+0x3a1: 62 f2 5d 0c cf 08  vgf2p8mulb (%rax),%xmm4,%xmm1{%k4}
+    libdis_test+0x3a7: 62 f2 5d 8d cf 08  vgf2p8mulb (%rax),%xmm4,%xmm1{%k5}{z}
+    libdis_test+0x3ad: 62 f2 65 09 cf 93  vgf2p8mulb 0x12(%rbx),%xmm3,%xmm2{%k1}
+                       12 00 00 00 
+    libdis_test+0x3b7: 62 f2 65 8a cf 93  vgf2p8mulb 0x12(%rbx),%xmm3,%xmm2{%k2}{z}
+                       12 00 00 00 
+    libdis_test+0x3c1: 62 92 6d 0f cf 9c  vgf2p8mulb 0x17(%r10,%r12,4),%xmm2,%xmm3{%k7}
+                       a2 17 00 00 00 
+    libdis_test+0x3cc: 62 92 6d 8e cf 9c  vgf2p8mulb 0x17(%r10,%r12,4),%xmm2,%xmm3{%k6}{z}
+                       a2 17 00 00 00 
diff --git a/usr/src/test/util-tests/tests/dis/i386/64.gfni.s b/usr/src/test/util-tests/tests/dis/i386/64.gfni.s
new file mode 100644
index 0000000000..56b0c19939
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/64.gfni.s
@@ -0,0 +1,172 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source.  A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright 2020 Robert Mustacchi
+ */
+
+/*
+ * Test GFNI related instructions
+ */
+
+.text
+.align 16
+.globl libdis_test
+.type libdis_test, @function
+libdis_test:
+	/* SSE Form */
+	gf2p8affineinvqb	$0x23, %xmm0, %xmm1
+	gf2p8affineinvqb	$0x51, (%rax), %xmm2
+	gf2p8affineinvqb	$0x19, 0x12(%rbx), %xmm3
+	gf2p8affineinvqb	$0x77, 0x12(%r10, %r12, 4), %xmm4
+
+	gf2p8affineqb		$0x23, %xmm7, %xmm6
+	gf2p8affineqb		$0x51, (%rax), %xmm5
+	gf2p8affineqb		$0x19, 0x12(%rbx), %xmm4
+	gf2p8affineqb		$0x77, 0x12(%r10, %r12, 4), %xmm3
+
+	gf2p8mulb		%xmm2, %xmm3
+	gf2p8mulb		(%rax), %xmm4
+	gf2p8mulb		0x12(%rbx), %xmm3
+	gf2p8mulb		0x17(%r10, %r12, 4), %xmm2
+
+	/* VEX Form - xmm */
+	vgf2p8affineinvqb	$0x23, %xmm0, %xmm1, %xmm5
+	vgf2p8affineinvqb	$0x51, (%rax), %xmm2, %xmm6
+	vgf2p8affineinvqb	$0x19, 0x12(%rbx), %xmm3, %xmm7
+	vgf2p8affineinvqb	$0x77, 0x12(%r10, %r12, 4), %xmm4, %xmm0
+
+	vgf2p8affineqb		$0x23, %xmm7, %xmm6, %xmm0
+	vgf2p8affineqb		$0x51, (%rax), %xmm5, %xmm1
+	vgf2p8affineqb		$0x19, 0x12(%rbx), %xmm4, %xmm2
+	vgf2p8affineqb		$0x77, 0x12(%r10, %r12, 4), %xmm3, %xmm6
+
+	vgf2p8mulb		%xmm2, %xmm3, %xmm0
+	vgf2p8mulb		(%rax), %xmm4, %xmm1
+	vgf2p8mulb		0x12(%rbx), %xmm3, %xmm2
+	vgf2p8mulb		0x17(%r10, %r12, 4), %xmm2, %xmm3
+
+	/* VEX Form - ymm */
+	vgf2p8affineinvqb	$0x23, %ymm0, %ymm1, %ymm5
+	vgf2p8affineinvqb	$0x51, (%rax), %ymm2, %ymm6
+	vgf2p8affineinvqb	$0x19, 0x12(%rbx), %ymm3, %ymm7
+	vgf2p8affineinvqb	$0x77, 0x12(%r10, %r12, 4), %ymm4, %ymm0
+
+	vgf2p8affineqb		$0x23, %ymm7, %ymm6, %ymm0
+	vgf2p8affineqb		$0x51, (%rax), %ymm5, %ymm1
+	vgf2p8affineqb		$0x19, 0x12(%rbx), %ymm4, %ymm2
+	vgf2p8affineqb		$0x77, 0x12(%r10, %r12, 4), %ymm3, %ymm6
+
+	vgf2p8mulb		%ymm2, %ymm3, %ymm0
+	vgf2p8mulb		(%rax), %ymm4, %ymm1
+	vgf2p8mulb		0x12(%rbx), %ymm3, %ymm2
+	vgf2p8mulb		0x17(%r10, %r12, 4), %ymm2, %ymm3
+
+	/* EVEX Form - basic zmm */
+	vgf2p8affineinvqb	$0x23, %zmm0, %zmm1, %zmm5
+	vgf2p8affineinvqb	$0x51, (%rax), %zmm2, %zmm6
+	vgf2p8affineinvqb	$0x19, 0x12(%rbx), %zmm3, %zmm7
+	vgf2p8affineinvqb	$0x77, 0x12(%r10, %r12, 4), %zmm4, %zmm0
+
+	vgf2p8affineqb		$0x23, %zmm7, %zmm6, %zmm0
+	vgf2p8affineqb		$0x51, (%rax), %zmm5, %zmm1
+	vgf2p8affineqb		$0x19, 0x12(%rbx), %zmm4, %zmm2
+	vgf2p8affineqb		$0x77, 0x12(%r10, %r12, 4), %zmm3, %zmm6
+
+	vgf2p8mulb		%zmm2, %zmm3, %zmm0
+	vgf2p8mulb		(%rax), %zmm4, %zmm1
+	vgf2p8mulb		0x12(%rbx), %zmm3, %zmm2
+	vgf2p8mulb		0x17(%r10, %r12, 4), %zmm2, %zmm3
+
+	/* EVEX Form - zmm, masks */
+	vgf2p8affineinvqb	$0x23, %zmm0, %zmm1, %zmm5{%k1}
+	vgf2p8affineinvqb	$0x23, %zmm0, %zmm1, %zmm5{%k2}{z}
+	vgf2p8affineinvqb	$0x51, (%rax), %zmm2, %zmm6{%k3}
+	vgf2p8affineinvqb	$0x51, (%rax), %zmm2, %zmm6{%k4}{z}
+	vgf2p8affineinvqb	$0x19, 0x12(%rbx), %zmm3, %zmm7{%k5}
+	vgf2p8affineinvqb	$0x19, 0x12(%rbx), %zmm3, %zmm7{%k6}{z}
+	vgf2p8affineinvqb	$0x77, 0x12(%r10, %r12, 4), %zmm4, %zmm0{%k7}
+	vgf2p8affineinvqb	$0x77, 0x12(%r10, %r12, 4), %zmm4, %zmm0{%k7}{z}
+
+	vgf2p8affineqb		$0x23, %zmm7, %zmm6, %zmm0{%k7}
+	vgf2p8affineqb		$0x23, %zmm7, %zmm6, %zmm0{%k6}{z}
+	vgf2p8affineqb		$0x51, (%rax), %zmm5, %zmm1{%k5}
+	vgf2p8affineqb		$0x51, (%rax), %zmm5, %zmm1{%k4}{z}
+	vgf2p8affineqb		$0x19, 0x12(%rbx), %zmm4, %zmm2{%k3}
+	vgf2p8affineqb		$0x19, 0x12(%rbx), %zmm4, %zmm2{%k2}{z}
+	vgf2p8affineqb		$0x77, 0x12(%r10, %r12, 4), %zmm3, %zmm6{%k1}
+	vgf2p8affineqb		$0x77, 0x12(%r10, %r12, 4), %zmm3, %zmm6{%k2}{z}
+
+	vgf2p8mulb		%zmm2, %zmm3, %zmm0{%k3}
+	vgf2p8mulb		%zmm2, %zmm3, %zmm0{%k2}{z}
+	vgf2p8mulb		(%rax), %zmm4, %zmm1{%k4}
+	vgf2p8mulb		(%rax), %zmm4, %zmm1{%k5}{z}
+	vgf2p8mulb		0x12(%rbx), %zmm3, %zmm2{%k1}
+	vgf2p8mulb		0x12(%rbx), %zmm3, %zmm2{%k2}{z}
+	vgf2p8mulb		0x17(%r10, %r12, 4), %zmm2, %zmm3{%k7}
+	vgf2p8mulb		0x17(%r10, %r12, 4), %zmm2, %zmm3{%k6}{z}
+
+	/* EVEX Form - ymm, masks */
+	vgf2p8affineinvqb	$0x23, %ymm0, %ymm1, %ymm5{%k1}
+	vgf2p8affineinvqb	$0x23, %ymm0, %ymm1, %ymm5{%k2}{z}
+	vgf2p8affineinvqb	$0x51, (%rax), %ymm2, %ymm6{%k3}
+	vgf2p8affineinvqb	$0x51, (%rax), %ymm2, %ymm6{%k4}{z}
+	vgf2p8affineinvqb	$0x19, 0x12(%rbx), %ymm3, %ymm7{%k5}
+	vgf2p8affineinvqb	$0x19, 0x12(%rbx), %ymm3, %ymm7{%k6}{z}
+	vgf2p8affineinvqb	$0x77, 0x12(%r10, %r12, 4), %ymm4, %ymm0{%k7}
+	vgf2p8affineinvqb	$0x77, 0x12(%r10, %r12, 4), %ymm4, %ymm0{%k7}{z}
+
+	vgf2p8affineqb		$0x23, %ymm7, %ymm6, %ymm0{%k7}
+	vgf2p8affineqb		$0x23, %ymm7, %ymm6, %ymm0{%k6}{z}
+	vgf2p8affineqb		$0x51, (%rax), %ymm5, %ymm1{%k5}
+	vgf2p8affineqb		$0x51, (%rax), %ymm5, %ymm1{%k4}{z}
+	vgf2p8affineqb		$0x19, 0x12(%rbx), %ymm4, %ymm2{%k3}
+	vgf2p8affineqb		$0x19, 0x12(%rbx), %ymm4, %ymm2{%k2}{z}
+	vgf2p8affineqb		$0x77, 0x12(%r10, %r12, 4), %ymm3, %ymm6{%k1}
+	vgf2p8affineqb		$0x77, 0x12(%r10, %r12, 4), %ymm3, %ymm6{%k2}{z}
+
+	vgf2p8mulb		%ymm2, %ymm3, %ymm0{%k3}
+	vgf2p8mulb		%ymm2, %ymm3, %ymm0{%k2}{z}
+	vgf2p8mulb		(%rax), %ymm4, %ymm1{%k4}
+	vgf2p8mulb		(%rax), %ymm4, %ymm1{%k5}{z}
+	vgf2p8mulb		0x12(%rbx), %ymm3, %ymm2{%k1}
+	vgf2p8mulb		0x12(%rbx), %ymm3, %ymm2{%k2}{z}
+	vgf2p8mulb		0x17(%r10, %r12, 4), %ymm2, %ymm3{%k7}
+	vgf2p8mulb		0x17(%r10, %r12, 4), %ymm2, %ymm3{%k6}{z}
+
+	/* EVEX Form - ymm, masks */
+	vgf2p8affineinvqb	$0x23, %xmm0, %xmm1, %xmm5{%k1}
+	vgf2p8affineinvqb	$0x23, %xmm0, %xmm1, %xmm5{%k2}{z}
+	vgf2p8affineinvqb	$0x51, (%rax), %xmm2, %xmm6{%k3}
+	vgf2p8affineinvqb	$0x51, (%rax), %xmm2, %xmm6{%k4}{z}
+	vgf2p8affineinvqb	$0x19, 0x12(%rbx), %xmm3, %xmm7{%k5}
+	vgf2p8affineinvqb	$0x19, 0x12(%rbx), %xmm3, %xmm7{%k6}{z}
+	vgf2p8affineinvqb	$0x77, 0x12(%r10, %r12, 4), %xmm4, %xmm0{%k7}
+	vgf2p8affineinvqb	$0x77, 0x12(%r10, %r12, 4), %xmm4, %xmm0{%k7}{z}
+
+	vgf2p8affineqb		$0x23, %xmm7, %xmm6, %xmm0{%k7}
+	vgf2p8affineqb		$0x23, %xmm7, %xmm6, %xmm0{%k6}{z}
+	vgf2p8affineqb		$0x51, (%rax), %xmm5, %xmm1{%k5}
+	vgf2p8affineqb		$0x51, (%rax), %xmm5, %xmm1{%k4}{z}
+	vgf2p8affineqb		$0x19, 0x12(%rbx), %xmm4, %xmm2{%k3}
+	vgf2p8affineqb		$0x19, 0x12(%rbx), %xmm4, %xmm2{%k2}{z}
+	vgf2p8affineqb		$0x77, 0x12(%r10, %r12, 4), %xmm3, %xmm6{%k1}
+	vgf2p8affineqb		$0x77, 0x12(%r10, %r12, 4), %xmm3, %xmm6{%k2}{z}
+
+	vgf2p8mulb		%xmm2, %xmm3, %xmm0{%k3}
+	vgf2p8mulb		%xmm2, %xmm3, %xmm0{%k2}{z}
+	vgf2p8mulb		(%rax), %xmm4, %xmm1{%k4}
+	vgf2p8mulb		(%rax), %xmm4, %xmm1{%k5}{z}
+	vgf2p8mulb		0x12(%rbx), %xmm3, %xmm2{%k1}
+	vgf2p8mulb		0x12(%rbx), %xmm3, %xmm2{%k2}{z}
+	vgf2p8mulb		0x17(%r10, %r12, 4), %xmm2, %xmm3{%k7}
+	vgf2p8mulb		0x17(%r10, %r12, 4), %xmm2, %xmm3{%k6}{z}
+.size libdis_test, [.-libdis_test]
diff --git a/usr/src/test/util-tests/tests/dis/i386/64.vaes.out b/usr/src/test/util-tests/tests/dis/i386/64.vaes.out
new file mode 100644
index 0000000000..80e87ea6c6
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/64.vaes.out
@@ -0,0 +1,24 @@
+    libdis_test:      c4 e2 71 dc d0     vaesenc %xmm0,%xmm1,%xmm2
+    libdis_test+0x5:  c4 e2 71 dc 10     vaesenc (%rax),%xmm1,%xmm2
+    libdis_test+0xa:  c4 e2 5d dc eb     vaesenc %ymm3,%ymm4,%ymm5
+    libdis_test+0xf:  c4 e2 5d dc 2b     vaesenc (%rbx),%ymm4,%ymm5
+    libdis_test+0x14: 62 f2 45 48 dc c6  vaesenc %zmm6,%zmm7,%zmm0
+    libdis_test+0x1a: 62 f2 45 48 dc 01  vaesenc (%rcx),%zmm7,%zmm0
+    libdis_test+0x20: c4 e2 71 dd d0     vaesenclast %xmm0,%xmm1,%xmm2
+    libdis_test+0x25: c4 e2 71 dd 10     vaesenclast (%rax),%xmm1,%xmm2
+    libdis_test+0x2a: c4 e2 5d dd eb     vaesenclast %ymm3,%ymm4,%ymm5
+    libdis_test+0x2f: c4 e2 5d dd 2b     vaesenclast (%rbx),%ymm4,%ymm5
+    libdis_test+0x34: 62 f2 45 48 dd c6  vaesenclast %zmm6,%zmm7,%zmm0
+    libdis_test+0x3a: 62 f2 45 48 dd 01  vaesenclast (%rcx),%zmm7,%zmm0
+    libdis_test+0x40: c4 e2 71 de d0     vaesdec %xmm0,%xmm1,%xmm2
+    libdis_test+0x45: c4 e2 71 de 10     vaesdec (%rax),%xmm1,%xmm2
+    libdis_test+0x4a: c4 e2 5d de eb     vaesdec %ymm3,%ymm4,%ymm5
+    libdis_test+0x4f: c4 e2 5d de 2b     vaesdec (%rbx),%ymm4,%ymm5
+    libdis_test+0x54: 62 f2 45 48 de c6  vaesdec %zmm6,%zmm7,%zmm0
+    libdis_test+0x5a: 62 f2 45 48 de 01  vaesdec (%rcx),%zmm7,%zmm0
+    libdis_test+0x60: c4 e2 71 df d0     vaesdeclast %xmm0,%xmm1,%xmm2
+    libdis_test+0x65: c4 e2 71 df 10     vaesdeclast (%rax),%xmm1,%xmm2
+    libdis_test+0x6a: c4 e2 5d df eb     vaesdeclast %ymm3,%ymm4,%ymm5
+    libdis_test+0x6f: c4 e2 5d df 2b     vaesdeclast (%rbx),%ymm4,%ymm5
+    libdis_test+0x74: 62 f2 45 48 df c6  vaesdeclast %zmm6,%zmm7,%zmm0
+    libdis_test+0x7a: 62 f2 45 48 df 01  vaesdeclast (%rcx),%zmm7,%zmm0
diff --git a/usr/src/test/util-tests/tests/dis/i386/64.vaes.s b/usr/src/test/util-tests/tests/dis/i386/64.vaes.s
new file mode 100644
index 0000000000..7c5f53e7ae
--- /dev/null
+++ b/usr/src/test/util-tests/tests/dis/i386/64.vaes.s
@@ -0,0 +1,52 @@
+/*
+ * This file and its contents are supplied under the terms of the
+ * Common Development and Distribution License ("CDDL"), version 1.0.
+ * You may only use this file in accordance with the terms of version
+ * 1.0 of the CDDL.
+ *
+ * A full copy of the text of the CDDL should have accompanied this
+ * source.  A copy of the CDDL is also available via the Internet at
+ * http://www.illumos.org/license/CDDL.
+ */
+
+/*
+ * Copyright 2020 Robert Mustacchi
+ */
+
+/*
+ * Test VAES related instructions
+ */
+
+.text
+.align 16
+.globl libdis_test
+.type libdis_test, @function
+libdis_test:
+	vaesenc	%xmm0, %xmm1, %xmm2
+	vaesenc	(%rax), %xmm1, %xmm2
+	vaesenc	%ymm3, %ymm4, %ymm5
+	vaesenc	(%rbx), %ymm4, %ymm5
+	vaesenc	%zmm6, %zmm7, %zmm0
+	vaesenc	(%rcx), %zmm7, %zmm0
+
+	vaesenclast	%xmm0, %xmm1, %xmm2
+	vaesenclast	(%rax), %xmm1, %xmm2
+	vaesenclast	%ymm3, %ymm4, %ymm5
+	vaesenclast	(%rbx), %ymm4, %ymm5
+	vaesenclast	%zmm6, %zmm7, %zmm0
+	vaesenclast	(%rcx), %zmm7, %zmm0
+
+	vaesdec	%xmm0, %xmm1, %xmm2
+	vaesdec	(%rax), %xmm1, %xmm2
+	vaesdec	%ymm3, %ymm4, %ymm5
+	vaesdec	(%rbx), %ymm4, %ymm5
+	vaesdec	%zmm6, %zmm7, %zmm0
+	vaesdec	(%rcx), %zmm7, %zmm0
+
+	vaesdeclast	%xmm0, %xmm1, %xmm2
+	vaesdeclast	(%rax), %xmm1, %xmm2
+	vaesdeclast	%ymm3, %ymm4, %ymm5
+	vaesdeclast	(%rbx), %ymm4, %ymm5
+	vaesdeclast	%zmm6, %zmm7, %zmm0
+	vaesdeclast	(%rcx), %zmm7, %zmm0
+.size libdis_test, [.-libdis_test]