diff options
| author | Robert Mustacchi <rm@joyent.com> | 2018-01-28 21:34:48 +0000 |
|---|---|---|
| committer | Robert Mustacchi <rm@joyent.com> | 2018-04-04 20:15:13 +0000 |
| commit | e89016e771abb6871cb08b54316d9a1a826a9193 (patch) | |
| tree | 3354ddfd98122bc249153e8219216b1031cc07bb | |
| parent | 7d815089a43a963b49eaddf97e514194ec29805b (diff) | |
| download | illumos-joyent-e89016e771abb6871cb08b54316d9a1a826a9193.tar.gz | |
9044 Need support for mpt_sas tri-mode parts
9045 Clean up mpt_sas compiler warnings
9046 mptsas_handle_topo_change can return without its locks held
9047 workaround SAS3408 firmware issue
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Hans Rosenfeld <hans.rosenfeld@joyent.com>
Reviewed by: Albert Lee <trisk@forkgnu.org>
Reviewed by: Yuri Pankov <yuripv@yuripv.net>
Approved by: Richard Lowe <richlowe@richlowe.net>
24 files changed, 1795 insertions, 218 deletions
diff --git a/exception_lists/copyright b/exception_lists/copyright index 9c0ad7bbae..5ebfb21e03 100644 --- a/exception_lists/copyright +++ b/exception_lists/copyright @@ -460,18 +460,5 @@ usr/src/uts/common/fs/zfs/THIRDPARTYLICENSE.lz4.descrip usr/src/uts/common/fs/zfs/THIRDPARTYLICENSE.cityhash.descrip usr/src/uts/common/sys/THIRDPARTYLICENSE.firmload usr/src/uts/common/sys/THIRDPARTYLICENSE.firmload.descrip -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE.descrip -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_hbd.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_history.txt -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ra.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_targ.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h +usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/* usr/src/uts/sparc/nsmb/ioc_check.ref diff --git a/exception_lists/cstyle b/exception_lists/cstyle index 740b1e636e..12548bd7b2 100644 --- a/exception_lists/cstyle +++ b/exception_lists/cstyle @@ -1039,17 +1039,7 @@ usr/src/uts/common/io/sfxge/common/siena_nvram.c usr/src/uts/common/io/sfxge/common/siena_phy.c usr/src/uts/common/io/sfxge/common/siena_sram.c usr/src/uts/common/io/sfxge/common/siena_vpd.c -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_hbd.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ra.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_targ.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h +usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/* usr/src/uts/intel/io/acpica/debugger/dbcmds.c usr/src/uts/intel/io/acpica/debugger/dbdisply.c usr/src/uts/intel/io/acpica/debugger/dbexec.c diff --git a/exception_lists/hdrchk b/exception_lists/hdrchk index 88d0df1cda..e7bd18910e 100644 --- a/exception_lists/hdrchk +++ b/exception_lists/hdrchk @@ -323,17 +323,7 @@ usr/src/uts/common/io/i40e/core/i40e_adminq_cmd.h usr/src/uts/common/io/udmf/dm9601reg.h usr/src/uts/common/io/upf/adm8511reg.h usr/src/uts/common/io/urf/rtl8150reg.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_hbd.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ra.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_targ.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h -usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h +usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/* usr/src/uts/intel/sys/acpi/acdebug.h usr/src/uts/intel/sys/acpi/acdisasm.h usr/src/uts/intel/sys/acpi/acevents.h diff --git a/usr/src/cmd/mdb/common/modules/mpt_sas/mpt_sas.c b/usr/src/cmd/mdb/common/modules/mpt_sas/mpt_sas.c index c39583b1f5..fe63ea02e2 100644 --- a/usr/src/cmd/mdb/common/modules/mpt_sas/mpt_sas.c +++ b/usr/src/cmd/mdb/common/modules/mpt_sas/mpt_sas.c @@ -24,7 +24,7 @@ */ /* - * Copyright 2014 Joyent, Inc. All rights reserved. + * Copyright (c) 2017 Joyent, Inc. * Copyright (c) 2014, Tegile Systems Inc. All rights reserved. */ @@ -716,6 +716,46 @@ display_deviceinfo(struct mptsas *mp) case MPI25_MFGPAGE_DEVID_SAS3108_6: mdb_printf("(SAS3108) "); break; + case MPI26_MFGPAGE_DEVID_SAS3216: + case MPI26_MFGPAGE_DEVID_SAS3316_1: + case MPI26_MFGPAGE_DEVID_SAS3316_2: + case MPI26_MFGPAGE_DEVID_SAS3316_3: + case MPI26_MFGPAGE_DEVID_SAS3316_4: + mdb_printf("(SAS3216) "); + break; + case MPI26_MFGPAGE_DEVID_SAS3224: + case MPI26_MFGPAGE_DEVID_SAS3324_1: + case MPI26_MFGPAGE_DEVID_SAS3324_2: + case MPI26_MFGPAGE_DEVID_SAS3324_3: + case MPI26_MFGPAGE_DEVID_SAS3324_4: + mdb_printf("(SAS3224) "); + break; + case MPI26_MFGPAGE_DEVID_SAS3408: + mdb_printf("(SAS3408) "); + break; + case MPI26_MFGPAGE_DEVID_SAS3416: + mdb_printf("(SAS3416) "); + break; + case MPI26_MFGPAGE_DEVID_SAS3508: + case MPI26_MFGPAGE_DEVID_SAS3508_1: + mdb_printf("(SAS3508) "); + break; + case MPI26_MFGPAGE_DEVID_SAS3516: + case MPI26_MFGPAGE_DEVID_SAS3516_1: + mdb_printf("(SAS3516) "); + break; + case MPI26_MFGPAGE_DEVID_SAS3616: + mdb_printf("(SAS3616) "); + break; + case MPI26_MFGPAGE_DEVID_SAS3708: + mdb_printf("(SAS3708) "); + break; + case MPI26_MFGPAGE_DEVID_SAS3716: + mdb_printf("(SAS3716) "); + break; + case MPI26_MFGPAGE_DEVID_SAS4008: + mdb_printf("(SAS4008) "); + break; default: mdb_printf("(SAS????) "); break; diff --git a/usr/src/man/man7d/mpt_sas.7d b/usr/src/man/man7d/mpt_sas.7d index 08d7447a89..bdb5899ae1 100644 --- a/usr/src/man/man7d/mpt_sas.7d +++ b/usr/src/man/man7d/mpt_sas.7d @@ -1,14 +1,14 @@ '\" te .\" Copyright (c) 2009, Sun Microsystems, Inc. All Rights Reserved +.\" Copyright (c) 2017, Joyent, Inc. .\" Copyright 2014, Nexenta Systems, Inc. All Rights Reserved .\" The contents of this file are subject to the terms of the Common Development and Distribution License (the "License"). You may not use this file except in compliance with the License. You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE .\" or http://www.opensolaris.org/os/licensing. See the License for the specific language governing permissions and limitations under the License. When distributing Covered Code, include this CDDL HEADER in each file and include the License file at usr/src/OPENSOLARIS.LICENSE. If applicable, add .\" the following below this CDDL HEADER, with the fields enclosed by brackets "[]" replaced with your own identifying information: Portions Copyright [yyyy] [name of copyright owner] -.TH MPT_SAS 7D "Apr 24, 2014" +.TH MPT_SAS 7D "Dec 15, 2017" .SH NAME mpt_sas \- SAS-2/3 host bus adapter driver .SH SYNOPSIS -.sp .in +2 .nf scsi@unit-address @@ -16,14 +16,13 @@ scsi@unit-address .in -2 .SH DESCRIPTION -.sp .LP -The \fBmpt_sas\fR host bus adapter driver is a nexus driver that supports the -LSI SAS200x/2x08 and SAS300x/3x08 series of chips. These chips support SAS/SATA +The \fBmpt_sas\fR host bus adapter driver is a nexus driver that supports +Broadcom (formerly LSI and Avago) SAS chipsets including the SAS200x/2x08/2x16 +and SAS300x/3x08/3x16/3x24 series of chips. These chips support SAS/SATA interfaces, including tagged and untagged queuing, SATA 3G/SAS 3G/SAS 6G/SAS 12G. .SS "Configuration" -.sp .LP The \fBmpt_sas\fR driver is configured by defining properties in \fBmpt_sas.conf\fR. These properties override the global SCSI settings. The @@ -70,7 +69,6 @@ mpxio-disable="yes"; .in -2 .SH FILES -.sp .ne 2 .na \fB\fB/kernel/drv/mpt_sas\fR\fR @@ -111,7 +109,6 @@ Optional configuration file .RE .SH ATTRIBUTES -.sp .LP See \fBattributes\fR(5) for a description of the following attributes: .sp @@ -127,7 +124,6 @@ Architecture SPARC, x86 .TE .SH SEE ALSO -.sp .LP \fBprtconf\fR(1M), \fBdriver.conf\fR(4), \fBpci\fR(4), \fBattributes\fR(5), \fBscsi_abort\fR(9F), \fBscsi_device\fR(9S), \fBscsi_extended_sense\fR(9S), diff --git a/usr/src/pkg/manifests/driver-storage-mpt_sas.mf b/usr/src/pkg/manifests/driver-storage-mpt_sas.mf index ae55dc9422..c0506e3307 100644 --- a/usr/src/pkg/manifests/driver-storage-mpt_sas.mf +++ b/usr/src/pkg/manifests/driver-storage-mpt_sas.mf @@ -71,8 +71,25 @@ driver name=mpt_sas class=scsi-self-identifying \ alias=pciex1000,95 \ alias=pciex1000,96 \ alias=pciex1000,97 \ + alias=pciex1000,aa \ + alias=pciex1000,ab \ + alias=pciex1000,ac \ + alias=pciex1000,ad \ + alias=pciex1000,ae \ + alias=pciex1000,af \ + alias=pciex1000,c0 \ + alias=pciex1000,c1 \ + alias=pciex1000,c2 \ + alias=pciex1000,c3 \ alias=pciex1000,c4 \ - alias=pciex1000,c9 + alias=pciex1000,c5 \ + alias=pciex1000,c6 \ + alias=pciex1000,c7 \ + alias=pciex1000,c8 \ + alias=pciex1000,c9 \ + alias=pciex1000,d0 \ + alias=pciex1000,d1 \ + alias=pciex1000,d2 file path=kernel/drv/$(ARCH64)/mpt_sas group=sys file path=kernel/drv/mpt_sas.conf group=sys \ original_name=SUNWmptsas:kernel/drv/mpt_sas.conf preserve=true @@ -81,3 +98,5 @@ legacy pkg=SUNWmptsas desc="LSI MPT SAS 2.0/2.5 Controller HBA Driver" \ name="LSI MPT SAS 2.0/2.5 Controller HBA Driver" license cr_Sun license=cr_Sun license lic_CDDL license=lic_CDDL +license usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE \ + license=usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE diff --git a/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c b/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c index 6719ffec26..23db051212 100644 --- a/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c +++ b/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c @@ -1897,7 +1897,8 @@ mptsas_do_detach(dev_info_t *dip) */ ndi_devi_enter(scsi_vhci_dip, &circ1); ndi_devi_enter(dip, &circ); - while (pip = mdi_get_next_client_path(dip, NULL)) { + while ((pip = mdi_get_next_client_path(dip, NULL)) != + NULL) { if (mdi_pi_free(pip, 0) == MDI_SUCCESS) { continue; } @@ -6464,10 +6465,11 @@ handle_topo_change: * If HBA is being reset, don't perform operations depending * on the IOC. We must free the topo list, however. */ - if (!mpt->m_in_reset) + if (!mpt->m_in_reset) { mptsas_handle_topo_change(topo_node, parent); - else + } else { NDBG20(("skipping topo change received during reset")); + } save_node = topo_node; topo_node = topo_node->next; ASSERT(save_node); @@ -6903,6 +6905,7 @@ mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, MPTSAS_VIRTUAL_PORT); mptsas_log(mpt, CE_WARN, "mptsas virtual port " "prop update failed"); + mutex_enter(&mpt->m_mutex); return; } /* @@ -6915,6 +6918,7 @@ mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, MPTSAS_NUM_PHYS); mptsas_log(mpt, CE_WARN, "mptsas num phys" "prop update failed"); + mutex_enter(&mpt->m_mutex); return; } /* @@ -6928,6 +6932,7 @@ mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, SCSI_ADDR_PROP_ATTACHED_PORT); mptsas_log(mpt, CE_WARN, "mptsas attached port " "prop update failed"); + mutex_enter(&mpt->m_mutex); return; } } @@ -7062,8 +7067,8 @@ mptsas_handle_event_sync(void *args) (mpt->m_reply_frame_dma_addr & 0xffffffffu))); event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); - if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, - &eventreply->IOCStatus)) { + if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, + &eventreply->IOCStatus)) != 0) { if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { mptsas_log(mpt, CE_WARN, "!mptsas_handle_event_sync: event 0x%x, " @@ -7767,8 +7772,8 @@ mptsas_handle_event(void *args) (mpt->m_reply_frame_dma_addr & 0xffffffffu))); event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); - if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, - &eventreply->IOCStatus)) { + if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, + &eventreply->IOCStatus)) != 0) { if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { mptsas_log(mpt, CE_WARN, "!mptsas_handle_event: IOCStatus=0x%x, " @@ -8302,6 +8307,60 @@ mptsas_handle_event(void *args) } break; } + case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: + { + pMpi26EventDataActiveCableExcept_t actcable; + uint32_t power; + uint8_t reason, id; + + actcable = (pMpi26EventDataActiveCableExcept_t) + eventreply->EventData; + power = ddi_get32(mpt->m_acc_reply_frame_hdl, + &actcable->ActiveCablePowerRequirement); + reason = ddi_get8(mpt->m_acc_reply_frame_hdl, + &actcable->ReasonCode); + id = ddi_get8(mpt->m_acc_reply_frame_hdl, + &actcable->ReceptacleID); + + /* + * It'd be nice if this weren't just logging to the system but + * were telling FMA about the active cable problem and FMA was + * aware of the cable topology and state. + */ + switch (reason) { + case MPI26_EVENT_ACTIVE_CABLE_PRESENT: + /* Don't log anything if it's fine */ + break; + case MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER: + mptsas_log(mpt, CE_WARN, "An active cable (id %u) does " + "not have sufficient power to be enabled. " + "Devices connected to this cable will not be " + "visible to the system.", id); + if (power == UINT32_MAX) { + mptsas_log(mpt, CE_CONT, "The cable's power " + "requirements are unknown.\n"); + } else { + mptsas_log(mpt, CE_CONT, "The cable requires " + "%u mW of power to function.\n", power); + } + break; + case MPI26_EVENT_ACTIVE_CABLE_DEGRADED: + mptsas_log(mpt, CE_WARN, "An active cable (id %u) is " + "degraded and not running at its full speed. " + "Some devices might not appear.", id); + break; + default: + break; + } + break; + } + case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE: + case MPI2_EVENT_PCIE_ENUMERATION: + case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: + case MPI2_EVENT_PCIE_LINK_COUNTER: + mptsas_log(mpt, CE_NOTE, "Unhandled mpt_sas PCIe device " + "event received (0x%x)", event); + break; default: NDBG20(("mptsas%d: unknown event %x received", mpt->m_instance, event)); @@ -10671,15 +10730,17 @@ mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt) pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) + sizeof (*tcsge); - if (pt->request_size != pt->sgl_offset) + if (pt->request_size != pt->sgl_offset) { NDBG15(("mpi_pre_fw_download(): Incorrect req size, " "0x%x, should be 0x%x, dataoutsz 0x%x", (int)pt->request_size, (int)pt->sgl_offset, (int)pt->dataout_size)); - if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) + } + if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) { NDBG15(("mpi_pre_fw_download(): Incorrect rep size, " "0x%x, should be 0x%x", pt->data_size, (int)sizeof (MPI2_FW_DOWNLOAD_REPLY))); + } } /* @@ -10709,15 +10770,17 @@ mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt) req25->ImageSize = tcsge->ImageSize; pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL); - if (pt->request_size != pt->sgl_offset) + if (pt->request_size != pt->sgl_offset) { NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, " "0x%x, should be 0x%x, dataoutsz 0x%x", pt->request_size, pt->sgl_offset, pt->dataout_size)); - if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) + } + if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) { NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, " "0x%x, should be 0x%x", pt->data_size, (int)sizeof (MPI2_FW_UPLOAD_REPLY))); + } } /* @@ -10753,15 +10816,17 @@ mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt) pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) + sizeof (*tcsge); - if (pt->request_size != pt->sgl_offset) + if (pt->request_size != pt->sgl_offset) { NDBG15(("mpi_pre_fw_upload(): Incorrect req size, " "0x%x, should be 0x%x, dataoutsz 0x%x", pt->request_size, pt->sgl_offset, pt->dataout_size)); - if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) + } + if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) { NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, " "0x%x, should be 0x%x", pt->data_size, (int)sizeof (MPI2_FW_UPLOAD_REPLY))); + } } /* @@ -10791,15 +10856,17 @@ mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt) req25->ImageSize = tcsge->ImageSize; pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL); - if (pt->request_size != pt->sgl_offset) + if (pt->request_size != pt->sgl_offset) { NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, " "0x%x, should be 0x%x, dataoutsz 0x%x", pt->request_size, pt->sgl_offset, pt->dataout_size)); - if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) + } + if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) { NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, " "0x%x, should be 0x%x", pt->data_size, (int)sizeof (MPI2_FW_UPLOAD_REPLY))); + } } /* @@ -10811,16 +10878,18 @@ mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt) #ifndef __lock_lint _NOTE(ARGUNUSED(mpt)) #endif - if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST)) + if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST)) { NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, " "0x%x, should be 0x%x, dataoutsz 0x%x", pt->request_size, (int)sizeof (MPI2_IOC_FACTS_REQUEST), pt->dataout_size)); - if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY)) + } + if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY)) { NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, " "0x%x, should be 0x%x", pt->data_size, (int)sizeof (MPI2_IOC_FACTS_REPLY))); + } pt->sgl_offset = (uint16_t)pt->request_size; } @@ -10833,16 +10902,18 @@ mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt) #ifndef __lock_lint _NOTE(ARGUNUSED(mpt)) #endif - if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST)) + if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST)) { NDBG15(("mpi_pre_port_facts(): Incorrect req size, " "0x%x, should be 0x%x, dataoutsz 0x%x", pt->request_size, (int)sizeof (MPI2_PORT_FACTS_REQUEST), pt->dataout_size)); - if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY)) + } + if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY)) { NDBG15(("mpi_pre_port_facts(): Incorrect rep size, " "0x%x, should be 0x%x", pt->data_size, (int)sizeof (MPI2_PORT_FACTS_REPLY))); + } pt->sgl_offset = (uint16_t)pt->request_size; } @@ -10856,15 +10927,17 @@ mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt) _NOTE(ARGUNUSED(mpt)) #endif pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL); - if (pt->request_size != pt->sgl_offset) + if (pt->request_size != pt->sgl_offset) { NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, " "0x%x, should be 0x%x, dataoutsz 0x%x", pt->request_size, pt->sgl_offset, pt->dataout_size)); - if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY)) + } + if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY)) { NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, " "0x%x, should be 0x%x", pt->data_size, (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY))); + } } static void @@ -10874,15 +10947,17 @@ mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt) _NOTE(ARGUNUSED(mpt)) #endif pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL); - if (pt->request_size != pt->sgl_offset) + if (pt->request_size != pt->sgl_offset) { NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, " "0x%x, should be 0x%x, dataoutsz 0x%x", pt->request_size, pt->sgl_offset, pt->dataout_size)); - if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY)) + } + if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY)) { NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, " "0x%x, should be 0x%x", pt->data_size, (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY))); + } } /* @@ -10895,14 +10970,16 @@ mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt) _NOTE(ARGUNUSED(mpt)) #endif pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE); - if (pt->request_size != pt->sgl_offset) + if (pt->request_size != pt->sgl_offset) { NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, " "should be 0x%x, dataoutsz 0x%x", pt->request_size, pt->sgl_offset, pt->dataout_size)); - if (pt->data_size != sizeof (MPI2_CONFIG_REPLY)) + } + if (pt->data_size != sizeof (MPI2_CONFIG_REPLY)) { NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, " "should be 0x%x", pt->data_size, (int)sizeof (MPI2_CONFIG_REPLY))); + } pt->simple = 1; } @@ -10916,15 +10993,17 @@ mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt) _NOTE(ARGUNUSED(mpt)) #endif pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL); - if (pt->request_size != pt->sgl_offset) + if (pt->request_size != pt->sgl_offset) { NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, " "should be 0x%x, dataoutsz 0x%x", pt->request_size, pt->sgl_offset, pt->dataout_size)); - if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY)) + } + if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY)) { NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, " "should be 0x%x", pt->data_size, (int)sizeof (MPI2_SCSI_IO_REPLY))); + } } /* @@ -14188,6 +14267,9 @@ mptsas_bus_config(dev_info_t *pdip, uint_t flag, mptsas_config_all(pdip); ret = NDI_SUCCESS; break; + default: + ret = NDI_FAILURE; + break; } if ((ret == NDI_SUCCESS) && bconfig) { @@ -14475,11 +14557,13 @@ mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt) continue; } saved_repluns[lun_cnt] = lun_num; - if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) + if ((cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) != + NULL) { ret = DDI_SUCCESS; - else + } else { ret = mptsas_probe_lun(pdip, lun_num, &cdip, ptgt); + } if ((ret == DDI_SUCCESS) && (cdip != NULL)) { (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip, MPTSAS_DEV_GONE); diff --git a/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas_impl.c b/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas_impl.c index e10b1bf6c5..e11b8ac15d 100644 --- a/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas_impl.c +++ b/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas_impl.c @@ -1707,9 +1707,12 @@ mptsas_sasiou_page_0_cb(mptsas_t *mpt, caddr_t page_memp, /* * ASSERT that the num_phys value in SAS IO Unit Page 0 is the same as * was initially set. This should never change throughout the life of - * the driver. + * the driver. Note, due to cases where we've seen page zero have more + * phys than the reported manufacturing information, we limit the number + * of phys here to what we got from the manufacturing information. */ - ASSERT(num_phys == mpt->m_num_phys); + ASSERT3U(num_phys, >=, mpt->m_num_phys); + num_phys = mpt->m_num_phys; for (i = 0; i < num_phys; i++) { cpdi[i] = ddi_get32(accessp, &sasioupage0->PhyData[i]. @@ -1771,11 +1774,14 @@ mptsas_sasiou_page_1_cb(mptsas_t *mpt, caddr_t page_memp, sasioupage1 = (pMpi2SasIOUnitPage1_t)page_memp; num_phys = ddi_get8(accessp, &sasioupage1->NumPhys); /* - * ASSERT that the num_phys value in SAS IO Unit Page 1 is the same as + * ASSERT that the num_phys value in SAS IO Unit Page 0 is the same as * was initially set. This should never change throughout the life of - * the driver. + * the driver. Note, due to cases where we've seen page zero have more + * phys than the reported manufacturing information, we limit the number + * of phys here to what we got from the manufacturing information. */ - ASSERT(num_phys == mpt->m_num_phys); + ASSERT3U(num_phys, >=, mpt->m_num_phys); + num_phys = mpt->m_num_phys; for (i = 0; i < num_phys; i++) { cpdi[i] = ddi_get32(accessp, &sasioupage1->PhyData[i]. ControllerPhyDeviceInfo); @@ -1932,7 +1938,7 @@ mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt) pMpi2SasIOUnitPage1_t sasioupage1; int recv_numbytes; caddr_t recv_memp, page_memp; - int i, num_phys, start_phy = 0; + uint_t i, num_phys, start_phy = 0; int page0_size = sizeof (MPI2_CONFIG_PAGE_SASIOUNIT_0) + (sizeof (MPI2_SAS_IO_UNIT0_PHY_DATA) * (MPTSAS_MAX_PHYS - 1)); @@ -2112,7 +2118,6 @@ mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt) num_phys = ddi_get8(page_accessp, &sasioupage0->NumPhys); - ASSERT(num_phys == mpt->m_num_phys); if (num_phys > MPTSAS_MAX_PHYS) { mptsas_log(mpt, CE_WARN, "Number of phys " "supported by HBA (%d) is more than max " @@ -2122,6 +2127,26 @@ mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt) rval = DDI_FAILURE; goto cleanup; } + if (num_phys > mpt->m_num_phys) { + mptsas_log(mpt, CE_WARN, "Number of phys " + "reported by HBA SAS IO Unit Page 0 (%u) " + "is greater than that reported by the " + "manufacturing information (%u). Driver " + "phy count limited to %u. Please contact " + "the firmware vendor about this.", num_phys, + mpt->m_num_phys, mpt->m_num_phys); + num_phys = mpt->m_num_phys; + } else if (num_phys < mpt->m_num_phys) { + mptsas_log(mpt, CE_WARN, "Number of phys " + "reported by HBA SAS IO Unit Page 0 (%u) " + "is less than that reported by the " + "manufacturing information (%u). Driver " + "will not attach. Please contact the " + "firmware vendor about this.", num_phys, + mpt->m_num_phys); + rval = DDI_FAILURE; + goto cleanup; + } for (i = start_phy; i < num_phys; i++, start_phy = i) { cpdi[i] = ddi_get32(page_accessp, &sasioupage0->PhyData[i]. @@ -2193,7 +2218,6 @@ mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt) num_phys = ddi_get8(page_accessp, &sasioupage1->NumPhys); - ASSERT(num_phys == mpt->m_num_phys); if (num_phys > MPTSAS_MAX_PHYS) { mptsas_log(mpt, CE_WARN, "Number of phys " "supported by HBA (%d) is more than max " @@ -2203,6 +2227,26 @@ mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt) rval = DDI_FAILURE; goto cleanup; } + if (num_phys > mpt->m_num_phys) { + mptsas_log(mpt, CE_WARN, "Number of phys " + "reported by HBA SAS IO Unit Page 1 (%u) " + "is greater than that reported by the " + "manufacturing information (%u). Limiting " + "phy count to %u. Please contact the " + "firmware vendor about this.", num_phys, + mpt->m_num_phys, mpt->m_num_phys); + num_phys = mpt->m_num_phys; + } else if (num_phys < mpt->m_num_phys) { + mptsas_log(mpt, CE_WARN, "Number of phys " + "reported by HBA SAS IO Unit Page 1 (%u) " + "is less than that reported by the " + "manufacturing information (%u). Driver " + "will not attach. Please contact the " + "firmware vendor about this.", num_phys, + mpt->m_num_phys); + rval = DDI_FAILURE; + goto cleanup; + } for (i = 0; i < num_phys; i++) { cpdi[i] = ddi_get32(page_accessp, &sasioupage1->PhyData[i]. @@ -2307,7 +2351,8 @@ mptsas_get_manufacture_page5(mptsas_t *mpt) goto done; } - if (iocstatus = ddi_get16(recv_accessp, &configreply->IOCStatus)) { + if ((iocstatus = ddi_get16(recv_accessp, &configreply->IOCStatus)) != + 0) { mptsas_log(mpt, CE_WARN, "mptsas_get_manufacture_page5 update: " "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, ddi_get32(recv_accessp, &configreply->IOCLogInfo)); @@ -2367,7 +2412,8 @@ mptsas_get_manufacture_page5(mptsas_t *mpt) goto done; } - if (iocstatus = ddi_get16(recv_accessp, &configreply->IOCStatus)) { + if ((iocstatus = ddi_get16(recv_accessp, &configreply->IOCStatus)) != + 0) { mptsas_log(mpt, CE_WARN, "mptsas_get_manufacture_page5 config: " "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, ddi_get32(recv_accessp, &configreply->IOCLogInfo)); @@ -2685,7 +2731,8 @@ mptsas_get_manufacture_page0(mptsas_t *mpt) goto done; } - if (iocstatus = ddi_get16(recv_accessp, &configreply->IOCStatus)) { + if ((iocstatus = ddi_get16(recv_accessp, &configreply->IOCStatus)) != + 0) { mptsas_log(mpt, CE_WARN, "mptsas_get_manufacture_page5 update: " "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, ddi_get32(recv_accessp, &configreply->IOCLogInfo)); @@ -2743,7 +2790,8 @@ mptsas_get_manufacture_page0(mptsas_t *mpt) goto done; } - if (iocstatus = ddi_get16(recv_accessp, &configreply->IOCStatus)) { + if ((iocstatus = ddi_get16(recv_accessp, &configreply->IOCStatus)) != + 0) { mptsas_log(mpt, CE_WARN, "mptsas_get_manufacture_page0 config: " "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, ddi_get32(recv_accessp, &configreply->IOCLogInfo)); diff --git a/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas_init.c b/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas_init.c index aaf5092322..7027c530f3 100644 --- a/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas_init.c +++ b/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas_init.c @@ -137,6 +137,36 @@ mptsas_devid_type_string(mptsas_t *mpt) case MPI25_MFGPAGE_DEVID_SAS3108_5: case MPI25_MFGPAGE_DEVID_SAS3108_6: return ("SAS3108"); + case MPI26_MFGPAGE_DEVID_SAS3216: + case MPI26_MFGPAGE_DEVID_SAS3316_1: + case MPI26_MFGPAGE_DEVID_SAS3316_2: + case MPI26_MFGPAGE_DEVID_SAS3316_3: + case MPI26_MFGPAGE_DEVID_SAS3316_4: + return ("SAS3216"); + case MPI26_MFGPAGE_DEVID_SAS3224: + case MPI26_MFGPAGE_DEVID_SAS3324_1: + case MPI26_MFGPAGE_DEVID_SAS3324_2: + case MPI26_MFGPAGE_DEVID_SAS3324_3: + case MPI26_MFGPAGE_DEVID_SAS3324_4: + return ("SAS3224"); + case MPI26_MFGPAGE_DEVID_SAS3408: + return ("SAS3408"); + case MPI26_MFGPAGE_DEVID_SAS3416: + return ("SAS3416"); + case MPI26_MFGPAGE_DEVID_SAS3508: + case MPI26_MFGPAGE_DEVID_SAS3508_1: + return ("SAS3508"); + case MPI26_MFGPAGE_DEVID_SAS3516: + case MPI26_MFGPAGE_DEVID_SAS3516_1: + return ("SAS3516"); + case MPI26_MFGPAGE_DEVID_SAS3616: + return ("SAS3616"); + case MPI26_MFGPAGE_DEVID_SAS3708: + return ("SAS3708"); + case MPI26_MFGPAGE_DEVID_SAS3716: + return ("SAS3716"); + case MPI26_MFGPAGE_DEVID_SAS4008: + return ("SAS4008"); default: return ("?"); } @@ -219,7 +249,7 @@ mptsas_ioc_do_get_facts_reply(mptsas_t *mpt, caddr_t memp, int var, return (DDI_FAILURE); } - if (iocstatus = ddi_get16(accessp, &factsreply->IOCStatus)) { + if ((iocstatus = ddi_get16(accessp, &factsreply->IOCStatus)) != 0) { mptsas_log(mpt, CE_WARN, "mptsas_ioc_do_get_facts_reply: " "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, ddi_get32(accessp, &factsreply->IOCLogInfo)); @@ -432,7 +462,7 @@ mptsas_ioc_do_get_port_facts_reply(mptsas_t *mpt, caddr_t memp, int var, return (DDI_FAILURE); } - if (iocstatus = ddi_get16(accessp, &factsreply->IOCStatus)) { + if ((iocstatus = ddi_get16(accessp, &factsreply->IOCStatus)) != 0) { mptsas_log(mpt, CE_WARN, "mptsas_ioc_do_get_port_facts_reply: " "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, ddi_get32(accessp, &factsreply->IOCLogInfo)); @@ -512,7 +542,7 @@ mptsas_ioc_do_enable_port_reply(mptsas_t *mpt, caddr_t memp, int var, return (DDI_FAILURE); } - if (iocstatus = ddi_get16(accessp, &portreply->IOCStatus)) { + if ((iocstatus = ddi_get16(accessp, &portreply->IOCStatus)) != 0) { mptsas_log(mpt, CE_WARN, "mptsas_ioc_do_enable_port_reply: " "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, ddi_get32(accessp, &portreply->IOCLogInfo)); @@ -594,7 +624,7 @@ mptsas_ioc_do_enable_event_notification_reply(mptsas_t *mpt, caddr_t memp, return (DDI_FAILURE); } - if (iocstatus = ddi_get16(accessp, &eventsreply->IOCStatus)) { + if ((iocstatus = ddi_get16(accessp, &eventsreply->IOCStatus)) != 0) { mptsas_log(mpt, CE_WARN, "mptsas_ioc_do_enable_event_notification_reply: " "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, @@ -721,7 +751,7 @@ mptsas_do_ioc_init_reply(mptsas_t *mpt, caddr_t memp, int var, return (DDI_FAILURE); } - if (iocstatus = ddi_get16(accessp, &initreply->IOCStatus)) { + if ((iocstatus = ddi_get16(accessp, &initreply->IOCStatus)) != 0) { mptsas_log(mpt, CE_WARN, "mptsas_do_ioc_init_reply: " "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, ddi_get32(accessp, &initreply->IOCLogInfo)); diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE index f8cd22f7df..7741eb3a6b 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE @@ -1,6 +1,7 @@ -Copyright (c) 2013 LSI Corp. +Copyright (c) 2012-2015 LSI Corp. +Copyright (c) 2013-2016 Avago Technologies All rights reserved. - + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -12,7 +13,7 @@ are met: 3. Neither the name of the author nor the names of any co-contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE.descrip b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE.descrip index 88aaf438dc..3d80aca794 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE.descrip +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/THIRDPARTYLICENSE.descrip @@ -1 +1 @@ -LSI Fusion-MPT MPI 2.0 / 2.5 Header Files +LSI Fusion-MPT MPI 2.0 / 2.5 / 2.6 Header Files diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2.h index 2c00944720..b3d78c450f 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,7 +29,9 @@ */ /* - * Copyright (c) 2000-2013 LSI Corporation. + * Copyright (c) 2000-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2.h @@ -37,7 +40,7 @@ * scatter/gather formats. * Creation Date: June 21, 2006 * - * mpi2.h Version: 02.00.33 + * mpi2.h Version: 02.00.46 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -119,6 +122,31 @@ * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. + * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT. + * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. + * 11-18-14 02.00.36 Updated copyright information. + * Bumped MPI2_HEADER_VERSION_UNIT. + * 03-16-15 02.00.37 Updated for MPI v2.6. + * Bumped MPI2_HEADER_VERSION_UNIT. + * Added Scratchpad registers and + * AtomicRequestDescriptorPost register to + * MPI2_SYSTEM_INTERFACE_REGS. + * Added MPI2_DIAG_SBR_RELOAD. + * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER. + * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. + * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT + * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. + * Added V7 HostDiagnostic register defines + * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT + * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT + * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines + * to be unique within first 32 characters. + * Removed AHCI support. + * Removed SOP support. + * Bumped MPI2_HEADER_VERSION_UNIT. + * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT. + * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT. + * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. * -------------------------------------------------------------------------- */ @@ -154,8 +182,15 @@ #define MPI2_VERSION_02_05 (0x0205) +/* minor version for MPI v2.6 compatible products */ +#define MPI26_VERSION_MINOR (0x06) +#define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ + MPI26_VERSION_MINOR) +#define MPI2_VERSION_02_06 (0x0206) + + /* Unit and Dev versioning for this MPI header set */ -#define MPI2_HEADER_VERSION_UNIT (0x21) +#define MPI2_HEADER_VERSION_UNIT (0x2E) #define MPI2_HEADER_VERSION_DEV (0x00) #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) @@ -211,10 +246,12 @@ typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS U32 HCBSize; /* 0x74 */ U32 HCBAddressLow; /* 0x78 */ U32 HCBAddressHigh; /* 0x7C */ - U32 Reserved6[16]; /* 0x80 */ + U32 Reserved6[12]; /* 0x80 */ + U32 Scratchpad[4]; /* 0xB0 */ U32 RequestDescriptorPostLow; /* 0xC0 */ U32 RequestDescriptorPostHigh; /* 0xC4 */ - U32 Reserved7[14]; /* 0xC8 */ + U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier versions */ + U32 Reserved7[13]; /* 0xCC */ } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; @@ -255,10 +292,18 @@ typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS */ #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) +#define MPI2_DIAG_SBR_RELOAD (0x00002000) + #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) +/* Defines for V7A/V7R HostDiagnostic Register */ +#define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000) +#define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800) +#define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000) +#define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800) + #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) #define MPI2_DIAG_HCB_MODE (0x00000100) @@ -329,10 +374,19 @@ typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) /* - * Offsets for the Request Queue + * Offsets for the Scratchpad registers + */ +#define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) +#define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) +#define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) +#define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) + +/* + * Offsets for the Request Descriptor Post Queue */ #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) +#define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) /* Hard Reset delay timings */ @@ -361,13 +415,15 @@ typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; /* defines for the RequestFlags field */ -#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) +#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) +#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */ #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) +#define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10) #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) @@ -435,6 +491,14 @@ typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t; +/* PCIe Encapsulated Request Descriptor */ +typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR + MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, + MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, + Mpi26PCIeEncapsulatedRequestDescriptor_t, + MPI2_POINTER pMpi26PCIeEncapsulatedRequestDescriptor_t; + + /* union of Request Descriptors */ typedef union _MPI2_REQUEST_DESCRIPTOR_UNION { @@ -444,11 +508,39 @@ typedef union _MPI2_REQUEST_DESCRIPTOR_UNION MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; + MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated; U64 Words; } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; +/* Atomic Request Descriptors */ + +/* + * All Atomic Request Descriptors have the same format, so the following + * structure is used for all Atomic Request Descriptors: + * Atomic Default Request Descriptor + * Atomic High Priority Request Descriptor + * Atomic SCSI IO Request Descriptor + * Atomic SCSI Target Request Descriptor + * Atomic RAID Accelerator Request Descriptor + * Atomic Fast Path SCSI IO Request Descriptor + * Atomic PCIe Encapsulated Request Descriptor + */ + +/* Atomic Request Descriptor */ +typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR +{ + U8 RequestFlags; /* 0x00 */ + U8 MSIxIndex; /* 0x01 */ + U16 SMID; /* 0x02 */ +} MPI26_ATOMIC_REQUEST_DESCRIPTOR, + MPI2_POINTER PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, + Mpi26AtomicRequestDescriptor_t, MPI2_POINTER pMpi26AtomicRequestDescriptor_t; + +/* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */ + + /* Reply Descriptors */ /* Default Reply Descriptor */ @@ -469,6 +561,7 @@ typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) +#define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08) #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) /* values for marking a reply descriptor as unused */ @@ -556,6 +649,14 @@ typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; +/* PCIe Encapsulated Success Reply Descriptor */ +typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR + MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, + MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, + Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t, + MPI2_POINTER pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t; + + /* union of Reply Descriptors */ typedef union _MPI2_REPLY_DESCRIPTORS_UNION { @@ -566,6 +667,7 @@ typedef union _MPI2_REPLY_DESCRIPTORS_UNION MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; + MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR PCIeEncapsulatedSuccess; U64 Words; } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; @@ -597,7 +699,8 @@ typedef union _MPI2_REPLY_DESCRIPTORS_UNION #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ -#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ +#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */ +#define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */ #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ @@ -607,6 +710,7 @@ typedef union _MPI2_REPLY_DESCRIPTORS_UNION #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */ +#define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */ #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ @@ -640,6 +744,7 @@ typedef union _MPI2_REPLY_DESCRIPTORS_UNION #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) +#define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */ /**************************************************************************** * Config IOCStatus values @@ -1117,7 +1222,7 @@ typedef union _MPI2_IEEE_SGE_CHAIN_UNION } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; -/* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */ +/* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ typedef struct _MPI25_IEEE_SGE_CHAIN64 { U64 Address; @@ -1175,16 +1280,25 @@ typedef union _MPI25_SGE_IO_UNION #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) +/* Next Segment Format */ + +#define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) +#define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) +#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) +#define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) + /* Data Location Address Space */ #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) -#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ +#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */ #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */ #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */ #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ +#define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */ + /**************************************************************************** * IEEE SGE operation Macros ****************************************************************************/ @@ -1240,8 +1354,9 @@ typedef union _MPI2_SGE_IO_UNION #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) -#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) -#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) +#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */ +#define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */ +#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */ /* values for SGL Type subfield */ #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h index a22f2da240..73b063015e 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,14 +29,16 @@ */ /* - * Copyright (c) 2000-2013 LSI Corporation. + * Copyright (c) 2000-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2_cnfg.h * Title: MPI Configuration messages and pages * Creation Date: November 10, 2006 * - * mpi2_cnfg.h Version: 02.00.27 + * mpi2_cnfg.h Version: 02.00.39 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -204,6 +207,50 @@ * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. + * 01-08-14 02.00.28 Added more defines for the BiosOptions field of + * MPI2_CONFIG_PAGE_BIOS_1. + * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and + * more defines for the BiosOptions field. + * 11-18-14 02.00.30 Updated copyright information. + * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. + * Added AdapterOrderAux fields to BIOS Page 3. + * 03-16-15 02.00.31 Updated for MPI v2.6. + * Added BoardPowerRequirement, PCISlotPowerAllocation, and + * Flags field to IO Unit Page 7. + * Added IO Unit Page 11. + * Added new SAS Phy Event codes + * Added PCIe configuration pages. + * 03-19-15 02.00.32 Fixed PCIe Link Config page structure names to be + * unique in first 32 characters. + * 05-25-15 02.00.33 Added more defines for the BiosOptions field of + * MPI2_CONFIG_PAGE_BIOS_1. + * 08-25-15 02.00.34 Added PCIe Device Page 2 SGL format capability. + * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. + * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. + * Added Link field to PCIe Link Pages + * Added EnclosureLevel and ConnectorName to PCIe + * Device Page 0. + * Added define for PCIE IoUnit page 1 max rate shift. + * Added comment for reserved ExtPageTypes. + * Added SAS 4 22.5 gbs speed support. + * Added PCIe 4 16.0 GT/sec speec support. + * Removed AHCI support. + * Removed SOP support. + * Added NegotiatedLinkRate and NegotiatedPortWidth to + * PCIe device page 0. + * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines + * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. + * Changed declaration of ConnectorName in PCIe DevicePage0 + * to match SAS DevicePage 0. + * Added SATADeviceWaitTime to IO Unit Page 11. + * Added MPI26_MFGPAGE_DEVID_SAS4008 + * Added x16 PCIe width to IO Unit Page 7 + * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 + * phy data. + * Added InitStatus to PCIe IO Unit Page 1 header. + * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. + * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and + * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. * -------------------------------------------------------------------------- */ @@ -288,6 +335,12 @@ typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) +#define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) /* MPI v2.6 and later */ +#define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) /* MPI v2.6 and later */ +#define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) /* MPI v2.6 and later */ +#define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) /* MPI v2.6 and later */ +/* Product specific reserved values 0xE0 - 0xEF */ +/* Vendor specific reserved values 0xF0 - 0xFF */ /***************************************************************************** @@ -355,6 +408,12 @@ typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) +/* Enclosure PageAddress format */ +#define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) +#define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) +#define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) + +#define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) /* RAID Configuration PageAddress format */ #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) @@ -381,6 +440,32 @@ typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) +/* PCIe Switch PageAddress format */ +#define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) +#define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) +#define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) +#define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) + +#define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) +#define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) +#define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) + + +/* PCIe Device PageAddress format */ +#define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) +#define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) +#define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) + +#define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) + +/* PCIe Link PageAddress format */ +#define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) +#define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) +#define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) + +#define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) + + /**************************************************************************** * Configuration messages @@ -485,7 +570,30 @@ typedef struct _MPI2_CONFIG_REPLY #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) +/* MPI v2.6 SAS Products */ +#define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) +#define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) +#define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) +#define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) +#define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) +#define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) +#define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) +#define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) +#define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) +#define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) + +#define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) +#define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) +#define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) +#define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) +#define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) +#define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) +#define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) +#define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) +#define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) + +#define MPI26_MFGPAGE_DEVID_SAS4008 (0x00A1) /* Manufacturing Page 0 */ @@ -725,6 +833,12 @@ typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) +#define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) +#define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) +#define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) +#define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) +#define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) +#define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) /* defines for the Location field */ #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) @@ -956,14 +1070,16 @@ typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 U16 BoardTemperature; /* 0x14 */ U8 BoardTemperatureUnits; /* 0x16 */ U8 Reserved3; /* 0x17 */ - U32 Reserved4; /* 0x18 */ - U32 Reserved5; /* 0x1C */ - U32 Reserved6; /* 0x20 */ - U32 Reserved7; /* 0x24 */ + U32 BoardPowerRequirement; /* 0x18 */ /* reserved prior to MPI v2.6 */ + U32 PCISlotPowerAllocation; /* 0x1C */ /* reserved prior to MPI v2.6 */ + U8 Flags; /* 0x20 */ /* reserved prior to MPI v2.6 */ + U8 Reserved6; /* 0x21 */ + U16 Reserved7; /* 0x22 */ + U32 Reserved8; /* 0x24 */ } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; -#define MPI2_IOUNITPAGE7_PAGEVERSION (0x04) +#define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) @@ -985,11 +1101,13 @@ typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) +#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) /* defines for IO Unit Page 7 PCIeSpeed field */ #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) +#define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) /* defines for IO Unit Page 7 ProcessorState field */ #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) @@ -1044,6 +1162,9 @@ typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) +/* defines for IO Unit Page 7 Flags field */ +#define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) + /* IO Unit Page 8 */ @@ -1162,6 +1283,58 @@ typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) +/* IO Unit Page 11 (for MPI v2.6 and later) */ + +typedef struct _MPI26_IOUNIT11_SPINUP_GROUP +{ + U8 MaxTargetSpinup; /* 0x00 */ + U8 SpinupDelay; /* 0x01 */ + U8 SpinupFlags; /* 0x02 */ + U8 Reserved1; /* 0x03 */ +} MPI26_IOUNIT11_SPINUP_GROUP, MPI2_POINTER PTR_MPI26_IOUNIT11_SPINUP_GROUP, + Mpi26IOUnit11SpinupGroup_t, MPI2_POINTER pMpi26IOUnit11SpinupGroup_t; + +/* defines for IO Unit Page 11 SpinupFlags */ +#define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) + + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * four and check the value returned for NumPhys at runtime. + */ +#ifndef MPI26_IOUNITPAGE11_PHY_MAX +#define MPI26_IOUNITPAGE11_PHY_MAX (4) +#endif + +typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 +{ + MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U32 Reserved1; /* 0x04 */ + MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ + U32 Reserved2; /* 0x18 */ + U32 Reserved3; /* 0x1C */ + U32 Reserved4; /* 0x20 */ + U8 BootDeviceWaitTime; /* 0x24 */ + U8 SATADeviceWaitTime; /* 0x25 */ + U16 Reserved6; /* 0x26 */ + U8 NumPhys; /* 0x28 */ + U8 PEInitialSpinupDelay; /* 0x29 */ + U8 PEReplyDelay; /* 0x2A */ + U8 Flags; /* 0x2B */ + U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */ +} MPI26_CONFIG_PAGE_IO_UNIT_11, + MPI2_POINTER PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, + Mpi26IOUnitPage11_t, MPI2_POINTER pMpi26IOUnitPage11_t; + +#define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) + +/* defines for Flags field */ +#define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) + +/* defines for PHY field */ +#define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) + + /**************************************************************************** * IOC Config Pages @@ -1325,7 +1498,9 @@ typedef struct _MPI2_CONFIG_PAGE_BIOS_1 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 BiosOptions; /* 0x04 */ U32 IOCSettings; /* 0x08 */ - U32 Reserved1; /* 0x0C */ + U8 SSUTimeout; /* 0x0C */ + U8 Reserved1; /* 0x0D */ + U16 Reserved2; /* 0x0E */ U32 DeviceSettings; /* 0x10 */ U16 NumberOfDevices; /* 0x14 */ U16 UEFIVersion; /* 0x16 */ @@ -1336,18 +1511,36 @@ typedef struct _MPI2_CONFIG_PAGE_BIOS_1 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; -#define MPI2_BIOSPAGE1_PAGEVERSION (0x05) +#define MPI2_BIOSPAGE1_PAGEVERSION (0x07) /* values for BIOS Page 1 BiosOptions field */ -#define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) -#define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) +#define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) +#define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) + +#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) +#define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) +#define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) +#define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) +#define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) +#define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) -#define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) -#define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) -#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) -#define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) +#define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) -#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) +#define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) +#define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) +#define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) +#define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) +#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) + +#define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) +#define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) + +#define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) +#define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) +#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) +#define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) + +#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) /* values for BIOS Page 1 IOCSettings field */ #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) @@ -1471,6 +1664,8 @@ typedef struct _MPI2_CONFIG_PAGE_BIOS_2 /* BIOS Page 3 */ +#define MPI2_BIOSPAGE3_NUM_ADAPTER (4) + typedef struct _MPI2_ADAPTER_INFO { U8 PciBusNumber; /* 0x00 */ @@ -1482,17 +1677,26 @@ typedef struct _MPI2_ADAPTER_INFO #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) +typedef struct _MPI2_ADAPTER_ORDER_AUX +{ + U64 WWID; /* 0x00 */ + U32 Reserved1; /* 0x08 */ + U32 Reserved2; /* 0x0C */ +} MPI2_ADAPTER_ORDER_AUX, MPI2_POINTER PTR_MPI2_ADAPTER_ORDER_AUX, + Mpi2AdapterOrderAux_t, MPI2_POINTER pMpi2AdapterOrderAux_t; + typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 GlobalFlags; /* 0x04 */ U32 BiosVersion; /* 0x08 */ - MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ + MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */ U32 Reserved1; /* 0x1C */ + MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and newer */ } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; -#define MPI2_BIOSPAGE3_PAGEVERSION (0x00) +#define MPI2_BIOSPAGE3_PAGEVERSION (0x01) /* values for BIOS Page 3 GlobalFlags */ #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) @@ -1848,6 +2052,7 @@ typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) +#define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) /* values for AttachedPhyInfo fields */ @@ -1915,12 +2120,14 @@ typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) +#define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) +#define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) /* values for SAS HwLinkRate fields */ @@ -1929,11 +2136,13 @@ typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) +#define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) +#define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) @@ -1984,6 +2193,8 @@ typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) /* values for SAS IO Unit Page 0 PhyFlags */ +#define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) +#define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) @@ -2076,6 +2287,7 @@ typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ /* values for SAS IO Unit Page 1 AdditionalControlFlags */ +#define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) @@ -2093,6 +2305,8 @@ typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) /* values for SAS IO Unit Page 1 PhyFlags */ +#define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) +#define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) @@ -2102,16 +2316,18 @@ typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) +#define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) +#define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ -/* SAS IO Unit Page 4 */ +/* SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { @@ -2142,7 +2358,7 @@ typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 U32 Reserved2; /* 0x1C */ U32 Reserved3; /* 0x20 */ U8 BootDeviceWaitTime; /* 0x24 */ - U8 Reserved4; /* 0x25 */ + U8 SATADeviceWaitTime; /* 0x25 */ U16 Reserved5; /* 0x26 */ U8 NumPhys; /* 0x28 */ U8 PEInitialSpinupDelay; /* 0x29 */ @@ -2589,10 +2805,10 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) +#define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) - /* SAS Device Page 1 */ typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 @@ -2759,6 +2975,17 @@ typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) +/* Following codes are product specific and in MPI v2.6 and later */ +#define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) +#define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) +#define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) +#define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) +#define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) +#define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) +#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) +#define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) +#define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) +#define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) /* values for the CounterType field */ #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) @@ -2850,7 +3077,7 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 * SAS Enclosure Config Pages ****************************************************************************/ -/* SAS Enclosure Page 0 */ +/* SAS Enclosure Page 0, Enclosure Page 0 */ typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { @@ -2868,7 +3095,10 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 U32 Reserved4; /* 0x24 */ } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, - Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; + Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t, + MPI26_CONFIG_PAGE_ENCLOSURE_0, + MPI2_POINTER PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, + Mpi26EnclosurePage0_t, MPI2_POINTER pMpi26EnclosurePage0_t; #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) @@ -2882,6 +3112,17 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) +#define MPI26_ENCLOSURE0_PAGEVERSION (0x04) + +/* Values for Enclosure Page 0 Flags field */ +#define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) +#define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) +#define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) +#define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) +#define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) +#define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) +#define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) +#define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) /**************************************************************************** * Log Config Page @@ -3161,5 +3402,424 @@ typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS /* PageVersion should be provided by product-specific code */ + +/**************************************************************************** +* values for fields used by several types of PCIe Config Pages +****************************************************************************/ + +/* values for NegotiatedLinkRates fields */ +#define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) +/* link rates used for Negotiated Physical Link Rate */ +#define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) +#define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) +#define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) +#define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) +#define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) +#define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) + + +/**************************************************************************** +* PCIe IO Unit Config Pages (MPI v2.6 and later) +****************************************************************************/ + +/* PCIe IO Unit Page 0 */ + +typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA +{ + U8 Link; /* 0x00 */ + U8 LinkFlags; /* 0x01 */ + U8 PhyFlags; /* 0x02 */ + U8 NegotiatedLinkRate; /* 0x03 */ + U32 ControllerPhyDeviceInfo;/* 0x04 */ + U16 AttachedDevHandle; /* 0x08 */ + U16 ControllerDevHandle; /* 0x0A */ + U32 EnumerationStatus; /* 0x0C */ + U32 Reserved1; /* 0x10 */ +} MPI26_PCIE_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, + Mpi26PCIeIOUnit0PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit0PhyData_t; + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check the value returned for NumPhys at runtime. + */ +#ifndef MPI26_PCIE_IOUNIT0_PHY_MAX +#define MPI26_PCIE_IOUNIT0_PHY_MAX (1) +#endif + +typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 +{ + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ + U32 Reserved1; /* 0x08 */ + U8 NumPhys; /* 0x0C */ + U8 InitStatus; /* 0x0D */ + U16 Reserved3; /* 0x0E */ + MPI26_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /* 0x10 */ +} MPI26_CONFIG_PAGE_PIOUNIT_0, + MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, + Mpi26PCIeIOUnitPage0_t, MPI2_POINTER pMpi26PCIeIOUnitPage0_t; + +#define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) + +/* values for PCIe IO Unit Page 0 LinkFlags */ +#define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) + +/* values for PCIe IO Unit Page 0 PhyFlags */ +#define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) + +/* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ + +/* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ + +/* values for PCIe IO Unit Page 0 EnumerationStatus */ +#define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) +#define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) + + +/* PCIe IO Unit Page 1 */ + +typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA +{ + U8 Link; /* 0x00 */ + U8 LinkFlags; /* 0x01 */ + U8 PhyFlags; /* 0x02 */ + U8 MaxMinLinkRate; /* 0x03 */ + U32 ControllerPhyDeviceInfo; /* 0x04 */ + U32 Reserved1; /* 0x08 */ +} MPI26_PCIE_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, + Mpi26PCIeIOUnit1PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit1PhyData_t; + +/* values for LinkFlags */ +#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS (0x00) +#define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS (0x01) + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check the value returned for NumPhys at runtime. + */ +#ifndef MPI26_PCIE_IOUNIT1_PHY_MAX +#define MPI26_PCIE_IOUNIT1_PHY_MAX (1) +#endif + +typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 +{ + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ + U16 ControlFlags; /* 0x08 */ + U16 Reserved; /* 0x0A */ + U16 AdditionalControlFlags; /* 0x0C */ + U16 NVMeMaxQueueDepth; /* 0x0E */ + U8 NumPhys; /* 0x10 */ + U8 Reserved1; /* 0x11 */ + U16 Reserved2; /* 0x12 */ + MPI26_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/* 0x14 */ +} MPI26_CONFIG_PAGE_PIOUNIT_1, + MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, + Mpi26PCIeIOUnitPage1_t, MPI2_POINTER pMpi26PCIeIOUnitPage1_t; + +#define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) + +/* values for PCIe IO Unit Page 1 PhyFlags */ +#define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) +#define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) + +/* values for PCIe IO Unit Page 1 MaxMinLinkRate */ +#define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) +#define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) +#define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) +#define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) +#define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) +#define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) + +/* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ + + +/**************************************************************************** +* PCIe Switch Config Pages (MPI v2.6 and later) +****************************************************************************/ + +/* PCIe Switch Page 0 */ + +typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 +{ + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ + U8 PhysicalPort; /* 0x08 */ + U8 Reserved1; /* 0x09 */ + U16 Reserved2; /* 0x0A */ + U16 DevHandle; /* 0x0C */ + U16 ParentDevHandle; /* 0x0E */ + U8 NumPorts; /* 0x10 */ + U8 PCIeLevel; /* 0x11 */ + U16 Reserved3; /* 0x12 */ + U32 Reserved4; /* 0x14 */ + U32 Reserved5; /* 0x18 */ + U32 Reserved6; /* 0x1C */ +} MPI26_CONFIG_PAGE_PSWITCH_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_0, + Mpi26PCIeSwitchPage0_t, MPI2_POINTER pMpi26PCIeSwitchPage0_t; + +#define MPI26_PCIESWITCH0_PAGEVERSION (0x00) + + +/* PCIe Switch Page 1 */ + +typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 +{ + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ + U8 PhysicalPort; /* 0x08 */ + U8 Reserved1; /* 0x09 */ + U16 Reserved2; /* 0x0A */ + U8 NumPorts; /* 0x0C */ + U8 PortNum; /* 0x0D */ + U16 AttachedDevHandle; /* 0x0E */ + U16 SwitchDevHandle; /* 0x10 */ + U8 NegotiatedPortWidth; /* 0x12 */ + U8 NegotiatedLinkRate; /* 0x13 */ + U32 Reserved4; /* 0x14 */ + U32 Reserved5; /* 0x18 */ +} MPI26_CONFIG_PAGE_PSWITCH_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_1, + Mpi26PCIeSwitchPage1_t, MPI2_POINTER pMpi26PCIeSwitchPage1_t; + +#define MPI26_PCIESWITCH1_PAGEVERSION (0x00) + +/* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ + + +/**************************************************************************** +* PCIe Device Config Pages (MPI v2.6 and later) +****************************************************************************/ + +/* PCIe Device Page 0 */ + +typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 +{ + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ + U16 Slot; /* 0x08 */ + U16 EnclosureHandle; /* 0x0A */ + U64 WWID; /* 0x0C */ + U16 ParentDevHandle; /* 0x14 */ + U8 PortNum; /* 0x16 */ + U8 AccessStatus; /* 0x17 */ + U16 DevHandle; /* 0x18 */ + U8 PhysicalPort; /* 0x1A */ + U8 Reserved1; /* 0x1B */ + U32 DeviceInfo; /* 0x1C */ + U32 Flags; /* 0x20 */ + U8 SupportedLinkRates; /* 0x24 */ + U8 MaxPortWidth; /* 0x25 */ + U8 NegotiatedPortWidth; /* 0x26 */ + U8 NegotiatedLinkRate; /* 0x27 */ + U8 EnclosureLevel; /* 0x28 */ + U8 Reserved2; /* 0x29 */ + U16 Reserved3; /* 0x2A */ + U8 ConnectorName[4]; /* 0x2C */ + U32 Reserved4; /* 0x30 */ + U32 Reserved5; /* 0x34 */ +} MPI26_CONFIG_PAGE_PCIEDEV_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, + Mpi26PCIeDevicePage0_t, MPI2_POINTER pMpi26PCIeDevicePage0_t; + +#define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) + +/* values for PCIe Device Page 0 AccessStatus field */ +#define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) +#define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) +#define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) +#define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) +#define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) +#define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) +#define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) +#define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) + +#define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) +#define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) +#define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) +#define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) +#define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) +#define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) +#define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) +#define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) +#define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) + +#define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) + +/* see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo field */ + +/* values for PCIe Device Page 0 Flags field */ +#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) +#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x4000) +#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x2000) +#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x0400) +#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x0200) +#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x0100) +#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x0080) +#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x0040) +#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x0020) +#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x0010) +#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x0002) +#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x0001) + +/* values for PCIe Device Page 0 SupportedLinkRates field */ +#define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) +#define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) +#define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) +#define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) + +/* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ + + +/* PCIe Device Page 2 */ + +typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 +{ + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ + U16 DevHandle; /* 0x08 */ + U16 Reserved1; /* 0x0A */ + U32 MaximumDataTransferSize;/* 0x0C */ + U32 Capabilities; /* 0x10 */ + U32 Reserved2; /* 0x14 */ +} MPI26_CONFIG_PAGE_PCIEDEV_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, + Mpi26PCIeDevicePage2_t, MPI2_POINTER pMpi26PCIeDevicePage2_t; + +#define MPI26_PCIEDEVICE2_PAGEVERSION (0x00) + +/* defines for PCIe Device Page 2 Capabilities field */ +#define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) +#define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) +#define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) + + +/**************************************************************************** +* PCIe Link Config Pages (MPI v2.6 and later) +****************************************************************************/ + +/* PCIe Link Page 1 */ + +typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 +{ + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ + U8 Link; /* 0x08 */ + U8 Reserved1; /* 0x09 */ + U16 Reserved2; /* 0x0A */ + U32 CorrectableErrorCount; /* 0x0C */ + U16 NonFatalErrorCount; /* 0x10 */ + U16 Reserved3; /* 0x12 */ + U16 FatalErrorCount; /* 0x14 */ + U16 Reserved4; /* 0x16 */ +} MPI26_CONFIG_PAGE_PCIELINK_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_1, + Mpi26PcieLinkPage1_t, MPI2_POINTER pMpi26PcieLinkPage1_t; + +#define MPI26_PCIELINK1_PAGEVERSION (0x00) + +/* PCIe Link Page 2 */ + +typedef struct _MPI26_PCIELINK2_LINK_EVENT +{ + U8 LinkEventCode; /* 0x00 */ + U8 Reserved1; /* 0x01 */ + U16 Reserved2; /* 0x02 */ + U32 LinkEventInfo; /* 0x04 */ +} MPI26_PCIELINK2_LINK_EVENT, MPI2_POINTER PTR_MPI26_PCIELINK2_LINK_EVENT, + Mpi26PcieLink2LinkEvent_t, MPI2_POINTER pMpi26PcieLink2LinkEvent_t; + +/* use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ + + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check the value returned for NumLinkEvents at runtime. + */ +#ifndef MPI26_PCIELINK2_LINK_EVENT_MAX +#define MPI26_PCIELINK2_LINK_EVENT_MAX (1) +#endif + +typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 +{ + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ + U8 Link; /* 0x08 */ + U8 Reserved1; /* 0x09 */ + U16 Reserved2; /* 0x0A */ + U8 NumLinkEvents; /* 0x0C */ + U8 Reserved3; /* 0x0D */ + U16 Reserved4; /* 0x0E */ + MPI26_PCIELINK2_LINK_EVENT LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /* 0x10 */ +} MPI26_CONFIG_PAGE_PCIELINK_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_2, + Mpi26PcieLinkPage2_t, MPI2_POINTER pMpi26PcieLinkPage2_t; + +#define MPI26_PCIELINK2_PAGEVERSION (0x00) + + +/* PCIe Link Page 3 */ + +typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG +{ + U8 LinkEventCode; /* 0x00 */ + U8 Reserved1; /* 0x01 */ + U16 Reserved2; /* 0x02 */ + U8 CounterType; /* 0x04 */ + U8 ThresholdWindow; /* 0x05 */ + U8 TimeUnits; /* 0x06 */ + U8 Reserved3; /* 0x07 */ + U32 EventThreshold; /* 0x08 */ + U16 ThresholdFlags; /* 0x0C */ + U16 Reserved4; /* 0x0E */ +} MPI26_PCIELINK3_LINK_EVENT_CONFIG, MPI2_POINTER PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, + Mpi26PcieLink3LinkEventConfig_t, MPI2_POINTER pMpi26PcieLink3LinkEventConfig_t; + +/* values for LinkEventCode field */ +#define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) +#define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) +#define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) +#define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) +#define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) +#define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) +#define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) +#define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) +#define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) +#define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) +#define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) +#define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) +#define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) +#define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) +#define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) +#define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) +#define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) +#define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) +#define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) + +/* values for the CounterType field */ +#define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) +#define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) +#define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) + +/* values for the TimeUnits field */ +#define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) +#define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) +#define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) +#define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) + +/* values for the ThresholdFlags field */ +#define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check the value returned for NumLinkEvents at runtime. + */ +#ifndef MPI26_PCIELINK3_LINK_EVENT_MAX +#define MPI26_PCIELINK3_LINK_EVENT_MAX (1) +#endif + +typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 +{ + MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ + U8 Link; /* 0x08 */ + U8 Reserved1; /* 0x09 */ + U16 Reserved2; /* 0x0A */ + U8 NumLinkEvents; /* 0x0C */ + U8 Reserved3; /* 0x0D */ + U16 Reserved4; /* 0x0E */ + MPI26_PCIELINK3_LINK_EVENT_CONFIG LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /* 0x10 */ +} MPI26_CONFIG_PAGE_PCIELINK_3, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_3, + Mpi26PcieLinkPage3_t, MPI2_POINTER pMpi26PcieLinkPage3_t; + +#define MPI26_PCIELINK3_PAGEVERSION (0x00) + + #endif diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_hbd.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_hbd.h index 2e47c9e5d4..9e7b831f3e 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_hbd.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_hbd.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,14 +29,16 @@ */ /* - * Copyright (c) 2009-2011 LSI Corporation. + * Copyright (c) 2009-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2_hbd.h * Title: MPI Host Based Discovery messages and structures * Creation Date: October 21, 2009 * - * mpi2_hbd.h Version: 02.00.02 + * mpi2_hbd.h Version: 02.00.04 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -51,6 +54,8 @@ * 08-11-10 02.00.01 Removed PortGroups, DmaGroup, and ControlGroup from * HBD Action request, replaced by AdditionalInfo field. * 11-18-11 02.00.02 Incorporating additions for MPI v2.5. + * 11-18-14 02.00.03 Updated copyright information. + * 02-17-16 02.00.04 Added SAS 4 22.5 gbs speed support. * -------------------------------------------------------------------------- */ @@ -121,6 +126,7 @@ typedef struct _MPI2_HBD_ACTION_REQUEST #define MPI2_HBD_MAX_RATE_3_0 (0x09) #define MPI2_HBD_MAX_RATE_6_0 (0x0A) #define MPI25_HBD_MAX_RATE_12_0 (0x0B) +#define MPI26_HBD_MAX_RATE_22_5 (0x0C) /* Host Based Discovery Action Reply Message */ diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_history.txt b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_history.txt index 25ab7d57ea..482c7fa35a 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_history.txt +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_history.txt @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -25,33 +26,40 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. + * + * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD + * + * $FreeBSD$ */ ============================== Fusion-MPT MPI 2.0 / 2.5 Header File Change History ============================== - Copyright (c) 2000-2013 LSI Corporation. + Copyright (c) 2000-2015 LSI Corporation. + Copyright (c) 2013-2016 Avago Technologies + All rights reserved. --------------------------------------- - Header Set Release Version: 02.00.33 - Header Set Release Date: 12-05-13 + Header Set Release Version: 02.00.46 + Header Set Release Date: 09-07-16 --------------------------------------- Filename Current version Prior version ---------- --------------- ------------- - mpi2.h 02.00.33 02.00.32 - mpi2_cnfg.h 02.00.27 02.00.26 - mpi2_init.h 02.00.15 02.00.15 - mpi2_ioc.h 02.00.24 02.00.23 - mpi2_raid.h 02.00.10 02.00.10 - mpi2_sas.h 02.00.08 02.00.08 - mpi2_targ.h 02.00.06 02.00.06 - mpi2_tool.h 02.00.11 02.00.11 - mpi2_type.h 02.00.00 02.00.00 - mpi2_ra.h 02.00.00 02.00.00 - mpi2_hbd.h 02.00.02 02.00.02 - mpi2_history.txt 02.00.33 02.00.32 + mpi2.h 02.00.46 02.00.45 + mpi2_cnfg.h 02.00.39 02.00.38 + mpi2_init.h 02.00.21 02.00.21 + mpi2_ioc.h 02.00.30 02.00.29 + mpi2_raid.h 02.00.11 02.00.11 + mpi2_sas.h 02.00.10 02.00.10 + mpi2_targ.h 02.00.09 02.00.09 + mpi2_tool.h 02.00.14 02.00.13 + mpi2_type.h 02.00.01 02.00.01 + mpi2_ra.h 02.00.01 02.00.01 + mpi2_hbd.h 02.00.04 02.00.04 + mpi2_pci.h 02.00.02 02.00.02 + mpi2_history.txt 02.00.43 02.00.43 * Date Version Description @@ -128,6 +136,31 @@ mpi2.h * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. + * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT. + * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. + * 11-18-14 02.00.36 Updated copyright information. + * Bumped MPI2_HEADER_VERSION_UNIT. + * 03-16-15 02.00.37 Updated for MPI v2.6. + * Bumped MPI2_HEADER_VERSION_UNIT. + * Added Scratchpad registers and + * AtomicRequestDescriptorPost register to + * MPI2_SYSTEM_INTERFACE_REGS. + * Added MPI2_DIAG_SBR_RELOAD. + * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER. + * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. + * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT. + * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. + * Added V7 HostDiagnostic register defines + * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT + * 01-04-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT + * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines + * to be unique within first 32 characters. + * Removed AHCI support. + * Removed SOP support. + * Bumped MPI2_HEADER_VERSION_UNIT. + * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT. + * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT. + * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. * -------------------------------------------------------------------------- mpi2_cnfg.h @@ -288,6 +321,50 @@ mpi2_cnfg.h * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. + * 01-08-14 02.00.28 Added more defines for the BiosOptions field of + * MPI2_CONFIG_PAGE_BIOS_1. + * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and + * more defines for the BiosOptions field.. + * 11-18-14 02.00.30 Updated copyright information. + * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. + * Added AdapterOrderAux fields to BIOS Page 3. + * 03-16-15 02.00.31 Updated for MPI v2.6. + * Added BoardPowerRequirement, PCISlotPowerAllocation, and + * Flags field to IO Unit Page 7. + * Added IO Unit Page 11. + * Added new SAS Phy Event codes + * Added PCIe configuration pages. + * 03-19-15 02.00.32 Fixed PCIe Link Config page structure names to be + * unique in first 32 characters. + * 05-25-15 02.00.33 Added more defines for the BiosOptions field of + * MPI2_CONFIG_PAGE_BIOS_1. + * 08-25-15 02.00.34 Added PCIe Device Page 2 SGL format capability. + * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. + * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. + * Added Link field to PCIe Link Pages + * Added EnclosureLevel and ConnectorName to PCIe + * Device Page 0. + * Added define for PCIE IoUnit page 1 max rate shift. + * Added comment for reserved ExtPageTypes. + * Added SAS 4 22.5 gbs speed support. + * Added PCIe 4 16.0 GT/sec speec support. + * Removed AHCI support. + * Removed SOP support. + * Added NegotiatedLinkRate and NegotiatedPortWidth to + * PCIe device page 0. + * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines + * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. + * Changed declaration of ConnectorName in PCIe DevicePage0 + * to match SAS DevicePage 0. + * Added SATADeviceWaitTime to IO Unit Page 11. + * Added MPI26_MFGPAGE_DEVID_SAS4008 + * Added x16 PCIe width to IO Unit Page 7 + * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 + * phy data. + * Added InitStatus to PCIe IO Unit Page 1 header. + * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. + * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and + * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. * -------------------------------------------------------------------------- mpi2_init.h @@ -317,6 +394,18 @@ mpi2_init.h * Priority to match SAM-4. * Added EEDPErrorOffset to MPI2_SCSI_IO_REPLY. * 07-10-12 02.00.14 Added MPI2_SCSIIO_CONTROL_SHIFT_DATADIRECTION. + * 04-09-13 02.00.15 Added SCSIStatusQualifier field to MPI2_SCSI_IO_REPLY, + * replacing the Reserved4 field. + * 11-18-14 02.00.16 Updated copyright information. + * 03-16-15 02.00.17 Updated for MPI v2.6. + * Added MPI26_SCSIIO_IOFLAGS_ESCAPE_PASSTHROUGH. + * Added MPI2_SEP_REQ_SLOTSTATUS_DEV_OFF and + * MPI2_SEP_REPLY_SLOTSTATUS_DEV_OFF. + * 08-26-15 02.00.18 Added SCSITASKMGMT_MSGFLAGS for Target Reset. + * 12-18-15 02.00.19 Added EEDPObservedValue added to SCSI IO Reply message. + * 01-04-16 02.00.20 Modified EEDP reported values in SCSI IO Reply message. + * 01-21-16 02.00.21 Modified MPI26_SCSITASKMGMT_MSGFLAGS_PCIE* defines to + * be unique within first 32 characters. * -------------------------------------------------------------------------- mpi2_ioc.h @@ -435,7 +524,38 @@ mpi2_ioc.h * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. * Added Encrypted Hash Extended Image. * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS. - * -------------------------------------------------------------------------- + * 11-18-14 02.00.25 Updated copyright information. + * 03-16-15 02.00.26 Updated for MPI v2.6. + * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and + * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT. + * Added MPI2_EVENT_PCIE_LINK_COUNTER and + * MPI26_EVENT_DATA_PCIE_LINK_COUNTER. + * Added MPI26_CTRL_OP_SHUTDOWN. + * Added MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG + * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and + * MPI26_FW_HEADER_PID_FAMILY_3516_SAS. + * 08-25-15 02.00.27 Added IC ARCH Class based signature defines. + * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event. + * Added ConigurationFlags field to IOCInit message to + * support NVMe SGL format control. + * Added PCIe SRIOV support. + * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support. + * Added PCIe 4 16.0 GT/sec speec support. + * Removed AHCI support. + * Removed SOP support. + * 07-01-16 02.00.29 Added Archclass for 4008 product. + * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED. + * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload + * Request Message. + * Added new defines for the ImageType field of FWUpload + * Request Message. + * Added new values for the RegionType field in the Layout + * Data sections of the FLASH Layout Extended Image Data. + * Added new defines for the ReasonCode field of + * Active Cable Exception Event. + * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and + * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE. + * -------------------------------------------------------------------------- mpi2_raid.h * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. @@ -473,6 +593,9 @@ mpi2_sas.h * Passthrough Request message. * 08-19-13 02.00.08 Made MPI2_SAS_OP_TRANSMIT_PORT_SELECT_SIGNAL obsolete * for anything newer than MPI v2.0. + * 11-18-14 02.00.09 Updated copyright information. + * 03-16-15 02.00.10 Updated for MPI v2.6. + * Added MPI2_SATA_PT_REQ_PT_FLAGS_FPDMA. * -------------------------------------------------------------------------- mpi2_targ.h @@ -490,6 +613,11 @@ mpi2_targ.h * request message structure. * Added AbortType MPI2_TARGET_MODE_ABORT_DEVHANDLE and * MPI2_TARGET_MODE_ABORT_ALL_COMMANDS. + * 06-13-14 02.00.07 Added MinMSIxIndex and MaxMSIxIndex fields to + * MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST. + * 11-18-14 02.00.08 Updated copyright information. + * 03-16-15 02.00.09 Updated for MPI v2.6. + * Added MPI26_TARGET_ASSIST_IOFLAGS_ESCAPE_PASSTHROUGH. * -------------------------------------------------------------------------- mpi2_tool.h @@ -513,14 +641,20 @@ mpi2_tool.h * 07-26-12 02.00.10 Modified MPI2_TOOLBOX_DIAGNOSTIC_CLI_REQUEST so that * it uses MPI Chain SGE as well as MPI Simple SGE. * 08-19-13 02.00.11 Added MPI2_TOOLBOX_TEXT_DISPLAY_TOOL and related info. + * 01-08-14 02.00.12 Added MPI2_TOOLBOX_CLEAN_BIT26_PRODUCT_SPECIFIC. + * 11-18-14 02.00.13 Updated copyright information. + * 08-25-16 02.00.14 Added new values for the Flags field of Toolbox Clean + * Tool Request Message. * -------------------------------------------------------------------------- mpi2_type.h * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. + * 11-18-14 02.00.01 Updated copyright information. * -------------------------------------------------------------------------- mpi2_ra.h * 05-06-09 02.00.00 Initial version. + * 11-18-14 02.00.01 Updated copyright information. * -------------------------------------------------------------------------- mpi2_hbd.h @@ -528,24 +662,63 @@ mpi2_hbd.h * 08-11-10 02.00.01 Removed PortGroups, DmaGroup, and ControlGroup from * HBD Action request, replaced by AdditionalInfo field. * 11-18-11 02.00.02 Incorporating additions for MPI v2.5. + * 11-18-14 02.00.03 Updated copyright information. + * 02-17-16 02.00.04 Added SAS 4 22.5 gbs speed support. * -------------------------------------------------------------------------- +mpi2_pci.h + * 03-16-15 02.00.00 Initial version. + * 02-17-16 02.00.01 Removed AHCI support. + * Removed SOP support. + * 07-01-16 02.00.02 Added MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP to + * NVME Encapsulated Request. + * -------------------------------------------------------------------------- mpi2_history.txt Parts list history -Filename 02.00.33 02.00.32 02.00.31 02.00.30 ----------- -------- -------- -------- -------- -mpi2.h 02.00.33 02.00.32 02.00.31 02.00.30 -mpi2_cnfg.h 02.00.27 02.00.26 02.00.25 02.00.25 -mpi2_init.h 02.00.15 02.00.15 02.00.15 02.00.15 -mpi2_ioc.h 02.00.24 02.00.23 02.00.22 02.00.22 -mpi2_raid.h 02.00.10 02.00.10 02.00.10 02.00.09 -mpi2_sas.h 02.00.08 02.00.08 02.00.07 02.00.07 -mpi2_targ.h 02.00.06 02.00.06 02.00.06 02.00.06 -mpi2_tool.h 02.00.11 02.00.11 02.00.10 02.00.10 -mpi2_type.h 02.00.00 02.00.00 02.00.00 02.00.00 -mpi2_ra.h 02.00.00 02.00.00 02.00.00 02.00.00 -mpi2_hbd.h 02.00.02 02.00.02 02.00.02 02.00.02 +Filename 02.00.46 02.00.45 02.00.44 02.00.43 02.00.42 +---------- -------- -------- -------- -------- -------- +mpi2.h 02.00.46 02.00.45 02.00.44 02.00.43 02.00.42 +mpi2_cnfg.h 02.00.39 02.00.38 02.00.37 02.00.36 02.00.35 +mpi2_init.h 02.00.21 02.00.21 02.00.21 02.00.21 02.00.20 +mpi2_ioc.h 02.00.30 02.00.29 02.00.28 02.00.28 02.00.27 +mpi2_raid.h 02.00.11 02.00.11 02.00.11 02.00.11 02.00.11 +mpi2_sas.h 02.00.10 02.00.10 02.00.10 02.00.10 02.00.10 +mpi2_targ.h 02.00.09 02.00.09 02.00.09 02.00.09 02.00.09 +mpi2_tool.h 02.00.14 02.00.13 02.00.13 02.00.13 02.00.13 +mpi2_type.h 02.00.01 02.00.01 02.00.01 02.00.01 02.00.01 +mpi2_ra.h 02.00.01 02.00.01 02.00.01 02.00.01 02.00.01 +mpi2_hbd.h 02.00.04 02.00.04 02.00.04 02.00.04 02.00.03 +mpi2_pci.h 02.00.02 02.00.02 02.00.01 02.00.01 02.00.00 + +Filename 02.00.41 02.00.40 02.00.39 02.00.38 02.00.37 02.00.36 +---------- -------- -------- -------- -------- -------- -------- +mpi2.h 02.00.41 02.00.40 02.00.39 02.00.38 02.00.37 02.00.36 +mpi2_cnfg.h 02.00.35 02.00.34 02.00.33 02.00.32 02.00.31 02.00.30 +mpi2_init.h 02.00.19 02.00.18 02.00.17 02.00.17 02.00.17 02.00.16 +mpi2_ioc.h 02.00.27 02.00.27 02.00.26 02.00.26 02.00.26 02.00.25 +mpi2_raid.h 02.00.11 02.00.11 02.00.11 02.00.11 02.00.11 02.00.11 +mpi2_sas.h 02.00.10 02.00.10 02.00.10 02.00.10 02.00.10 02.00.09 +mpi2_targ.h 02.00.09 02.00.09 02.00.09 02.00.09 02.00.09 02.00.08 +mpi2_tool.h 02.00.13 02.00.13 02.00.13 02.00.13 02.00.13 02.00.13 +mpi2_type.h 02.00.01 02.00.01 02.00.01 02.00.01 02.00.01 02.00.01 +mpi2_ra.h 02.00.01 02.00.01 02.00.01 02.00.01 02.00.01 02.00.01 +mpi2_hbd.h 02.00.03 02.00.03 02.00.03 02.00.03 02.00.03 02.00.03 +mpi2_pci.h 02.00.00 02.00.00 02.00.00 02.00.00 02.00.00 + +Filename 02.00.35 02.00.34 02.00.33 02.00.32 02.00.31 02.00.30 +---------- -------- -------- -------- -------- -------- -------- +mpi2.h 02.00.35 02.00.34 02.00.33 02.00.32 02.00.31 02.00.30 +mpi2_cnfg.h 02.00.29 02.00.28 02.00.27 02.00.26 02.00.25 02.00.25 +mpi2_init.h 02.00.15 02.00.15 02.00.15 02.00.15 02.00.15 02.00.15 +mpi2_ioc.h 02.00.24 02.00.24 02.00.24 02.00.23 02.00.22 02.00.22 +mpi2_raid.h 02.00.10 02.00.10 02.00.10 02.00.10 02.00.10 02.00.09 +mpi2_sas.h 02.00.08 02.00.08 02.00.08 02.00.08 02.00.07 02.00.07 +mpi2_targ.h 02.00.07 02.00.06 02.00.06 02.00.06 02.00.06 02.00.06 +mpi2_tool.h 02.00.12 02.00.12 02.00.11 02.00.11 02.00.10 02.00.10 +mpi2_type.h 02.00.00 02.00.00 02.00.00 02.00.00 02.00.00 02.00.00 +mpi2_ra.h 02.00.00 02.00.00 02.00.00 02.00.00 02.00.00 02.00.00 +mpi2_hbd.h 02.00.02 02.00.02 02.00.02 02.00.02 02.00.02 02.00.02 Filename 02.00.29 02.00.28 02.00.27 02.00.26 02.00.25 02.00.24 ---------- -------- -------- -------- -------- -------- -------- diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h index 47b8992881..7adb30b4a2 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,14 +29,16 @@ */ /* - * Copyright (c) 2000-2013 LSI Corporation. + * Copyright (c) 2000-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2_init.h * Title: MPI SCSI initiator mode messages and structures * Creation Date: June 23, 2006 * - * mpi2_init.h Version: 02.00.15 + * mpi2_init.h Version: 02.00.21 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -55,7 +58,7 @@ * 05-21-08 02.00.05 Fixed typo in name of Mpi2SepRequest_t. * 10-02-08 02.00.06 Removed Untagged and No Disconnect values from SCSI IO * Control field Task Attribute flags. - * Moved LUN field defines to mpi2.h becasue they are + * Moved LUN field defines to mpi2.h because they are * common to many structures. * 05-06-09 02.00.07 Changed task management type of Query Unit Attention to * Query Asynchronous Event. @@ -75,6 +78,16 @@ * 07-10-12 02.00.14 Added MPI2_SCSIIO_CONTROL_SHIFT_DATADIRECTION. * 04-09-13 02.00.15 Added SCSIStatusQualifier field to MPI2_SCSI_IO_REPLY, * replacing the Reserved4 field. + * 11-18-14 02.00.16 Updated copyright information. + * 03-16-15 02.00.17 Updated for MPI v2.6. + * Added MPI26_SCSIIO_IOFLAGS_ESCAPE_PASSTHROUGH. + * Added MPI2_SEP_REQ_SLOTSTATUS_DEV_OFF and + * MPI2_SEP_REPLY_SLOTSTATUS_DEV_OFF. + * 08-26-15 02.00.18 Added SCSITASKMGMT_MSGFLAGS for Target Reset. + * 12-18-15 02.00.19 Added EEDPObservedValue added to SCSI IO Reply message. + * 01-04-16 02.00.20 Modified EEDP reported values in SCSI IO Reply message. + * 01-21-16 02.00.21 Modified MPI26_SCSITASKMGMT_MSGFLAGS_PCIE* defines to + * be unique within first 32 characters. * -------------------------------------------------------------------------- */ @@ -158,8 +171,9 @@ typedef struct _MPI2_SCSI_IO_REQUEST #define MPI2_SCSIIO_MSGFLAGS_MASK_SENSE_ADDR (0x0C) #define MPI2_SCSIIO_MSGFLAGS_SYSTEM_SENSE_ADDR (0x00) #define MPI2_SCSIIO_MSGFLAGS_IOCDDR_SENSE_ADDR (0x04) -#define MPI2_SCSIIO_MSGFLAGS_IOCPLB_SENSE_ADDR (0x08) -#define MPI2_SCSIIO_MSGFLAGS_IOCPLBNTA_SENSE_ADDR (0x0C) +#define MPI2_SCSIIO_MSGFLAGS_IOCPLB_SENSE_ADDR (0x08) /* for MPI v2.5 and earlier only */ +#define MPI2_SCSIIO_MSGFLAGS_IOCPLBNTA_SENSE_ADDR (0x0C) /* for MPI v2.5 and earlier only */ +#define MPI26_SCSIIO_MSGFLAGS_IOCCTL_SENSE_ADDR (0x08) /* for MPI v2.6 only */ /* SCSI IO SGLFlags bits */ @@ -262,7 +276,7 @@ typedef union _MPI25_SCSI_IO_CDB_UNION } MPI25_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI25_SCSI_IO_CDB_UNION, Mpi25ScsiIoCdb_t, MPI2_POINTER pMpi25ScsiIoCdb_t; -/* MPI v2.5 SCSI IO Request Message */ +/* MPI v2.5/2.6 SCSI IO Request Message */ typedef struct _MPI25_SCSI_IO_REQUEST { U16 DevHandle; /* 0x00 */ @@ -341,8 +355,10 @@ typedef struct _MPI25_SCSI_IO_REQUEST #define MPI25_SCSIIO_IOFLAGS_NORMAL_PATH (0x0000) #define MPI25_SCSIIO_IOFLAGS_FAST_PATH (0x4000) +#define MPI26_SCSIIO_IOFLAGS_ESCAPE_PASSTHROUGH (0x2000) /* MPI v2.6 and later */ #define MPI25_SCSIIO_IOFLAGS_LARGE_CDB (0x1000) #define MPI25_SCSIIO_IOFLAGS_BIDIRECTIONAL (0x0800) +#define MPI26_SCSIIO_IOFLAGS_PORT_REQUEST (0x0400) /* MPI v2.6 and later; IOC use only */ #define MPI25_SCSIIO_IOFLAGS_CDBLENGTH_MASK (0x01FF) /* MPI v2.5 defines for the EEDPFlags bits */ @@ -388,11 +404,19 @@ typedef struct _MPI2_SCSI_IO_REPLY U16 TaskTag; /* 0x20 */ U16 SCSIStatusQualifier; /* 0x22 */ U32 BidirectionalTransferCount; /* 0x24 */ - U32 EEDPErrorOffset; /* 0x28 */ /* MPI 2.5 only; Reserved in MPI 2.0 */ - U32 Reserved6; /* 0x2C */ + U32 EEDPErrorOffset; /* 0x28 */ /* MPI 2.5+ only; Reserved in MPI 2.0 */ + U16 EEDPObservedAppTag; /* 0x2C */ /* MPI 2.5+ only; Reserved in MPI 2.0 */ + U16 EEDPObservedGuard; /* 0x2E */ /* MPI 2.5+ only; Reserved in MPI 2.0 */ + U32 EEDPObservedRefTag; /* 0x30 */ /* MPI 2.5+ only; Reserved in MPI 2.0 */ } MPI2_SCSI_IO_REPLY, MPI2_POINTER PTR_MPI2_SCSI_IO_REPLY, Mpi2SCSIIOReply_t, MPI2_POINTER pMpi2SCSIIOReply_t; +/* SCSI IO Reply MsgFlags bits */ +#define MPI26_SCSIIO_REPLY_MSGFLAGS_REFTAG_OBSERVED_VALID (0x01) +#define MPI26_SCSIIO_REPLY_MSGFLAGS_GUARD_OBSERVED_VALID (0x02) +#define MPI26_SCSIIO_REPLY_MSGFLAGS_APPTAG_OBSERVED_VALID (0x04) + + /* SCSI IO Reply SCSIStatus values (SAM-4 status codes) */ #define MPI2_SCSI_STATUS_GOOD (0x00) @@ -465,14 +489,13 @@ typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION (MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT) /* MsgFlags bits */ - -#define MPI2_SCSITASKMGMT_MSGFLAGS_MASK_TARGET_RESET (0x18) -#define MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET (0x00) -#define MPI2_SCSITASKMGMT_MSGFLAGS_NEXUS_RESET_SRST (0x08) -#define MPI2_SCSITASKMGMT_MSGFLAGS_SAS_HARD_LINK_RESET (0x10) - -#define MPI2_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x01) - +#define MPI2_SCSITASKMGMT_MSGFLAGS_MASK_TARGET_RESET (0x18) +#define MPI26_SCSITASKMGMT_MSGFLAGS_HOT_RESET_PCIE (0x00) +#define MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET (0x00) +#define MPI2_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x01) +#define MPI2_SCSITASKMGMT_MSGFLAGS_NEXUS_RESET_SRST (0x08) +#define MPI2_SCSITASKMGMT_MSGFLAGS_SAS_HARD_LINK_RESET (0x10) +#define MPI26_SCSITASKMGMT_MSGFLAGS_PROTOCOL_LVL_RST_PCIE (0x18) /* SCSI Task Management Reply Message */ @@ -555,6 +578,7 @@ typedef struct _MPI2_SEP_REQUEST #define MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS (0x01) /* SlotStatus defines */ +#define MPI2_SEP_REQ_SLOTSTATUS_DEV_OFF (0x00080000) /* MPI v2.6 and newer */ #define MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000) #define MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) #define MPI2_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200) @@ -592,6 +616,7 @@ typedef struct _MPI2_SEP_REPLY Mpi2SepReply_t, MPI2_POINTER pMpi2SepReply_t; /* SlotStatus defines */ +#define MPI2_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x00080000) /* MPI v2.6 and newer */ #define MPI2_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000) #define MPI2_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) #define MPI2_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200) diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h index fedf35f4f3..100b0d1147 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,14 +29,16 @@ */ /* - * Copyright (c) 2000-2013 LSI Corporation. + * Copyright (c) 2000-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2_ioc.h * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages * Creation Date: October 11, 2006 * - * mpi2_ioc.h Version: 02.00.24 + * mpi2_ioc.h Version: 02.00.30 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -162,6 +165,37 @@ * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY. * Added Encrypted Hash Extended Image. * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS. + * 11-18-14 02.00.25 Updated copyright information. + * 03-16-15 02.00.26 Updated for MPI v2.6. + * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and + * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT. + * Added MPI2_EVENT_PCIE_LINK_COUNTER and + * MPI26_EVENT_DATA_PCIE_LINK_COUNTER. + * Added MPI26_CTRL_OP_SHUTDOWN. + * Added MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG + * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and + * MPI26_FW_HEADER_PID_FAMILY_3516_SAS. + * 08-25-15 02.00.27 Added IC ARCH Class based signature defines. + * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event. + * Added ConigurationFlags field to IOCInit message to + * support NVMe SGL format control. + * Added PCIe SRIOV support. + * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support. + * Added PCIe 4 16.0 GT/sec speec support. + * Removed AHCI support. + * Removed SOP support. + * 07-01-16 02.00.29 Added Archclass for 4008 product. + * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED + * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload + * Request Message. + * Added new defines for the ImageType field of FWUpload + * Request Message. + * Added new values for the RegionType field in the Layout + * Data sections of the FLASH Layout Extended Image Data. + * Added new defines for the ReasonCode field of + * Active Cable Exception Event. + * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and + * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE. * -------------------------------------------------------------------------- */ @@ -194,8 +228,8 @@ typedef struct _MPI2_IOC_INIT_REQUEST U16 MsgVersion; /* 0x0C */ U16 HeaderVersion; /* 0x0E */ U32 Reserved5; /* 0x10 */ - U16 Reserved6; /* 0x14 */ - U8 Reserved7; /* 0x16 */ + U16 ConfigurationFlags; /* 0x14 */ + U8 HostPageSize; /* 0x16 */ U8 HostMSIxVectors; /* 0x17 */ U16 Reserved8; /* 0x18 */ U16 SystemRequestFrameSize; /* 0x1A */ @@ -233,6 +267,9 @@ typedef struct _MPI2_IOC_INIT_REQUEST #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) +/* ConfigurationFlags */ +#define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001) + /* minimum depth for a Reply Descriptor Post Queue */ #define MPI2_RDPQ_DEPTH_MIN (16) @@ -323,7 +360,12 @@ typedef struct _MPI2_IOC_FACTS_REPLY U16 MaxDevHandle; /* 0x38 */ U16 MaxPersistentEntries; /* 0x3A */ U16 MinDevHandle; /* 0x3C */ - U16 Reserved4; /* 0x3E */ + U8 CurrentHostPageSize; /* 0x3E */ + U8 Reserved4; /* 0x3F */ + U8 SGEModifierMask; /* 0x40 */ + U8 SGEModifierValue; /* 0x41 */ + U8 SGEModifierShift; /* 0x42 */ + U8 Reserved5; /* 0x43 */ } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; @@ -340,6 +382,7 @@ typedef struct _MPI2_IOC_FACTS_REPLY #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) /* IOCExceptions */ +#define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400) #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200) #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) @@ -360,6 +403,8 @@ typedef struct _MPI2_IOC_FACTS_REPLY /* ProductID field uses MPI2_FW_HEADER_PID_ */ /* IOCCapabilities */ +#define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000) +#define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000) #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000) #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000) #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) @@ -377,8 +422,9 @@ typedef struct _MPI2_IOC_FACTS_REPLY #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) /* ProtocolFlags */ -#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) +#define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008) /* MPI v2.6 and later */ #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) +#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) /**************************************************************************** @@ -429,6 +475,7 @@ typedef struct _MPI2_PORT_FACTS_REPLY #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) +#define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40) /* MPI v2.6 and later */ /**************************************************************************** @@ -541,6 +588,7 @@ typedef struct _MPI2_EVENT_NOTIFICATION_REPLY #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) +#define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D) /* MPI v2.6 and later */ #define MPI2_EVENT_IR_VOLUME (0x001E) #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) @@ -553,6 +601,11 @@ typedef struct _MPI2_EVENT_NOTIFICATION_REPLY #define MPI2_EVENT_TEMP_THRESHOLD (0x0027) #define MPI2_EVENT_HOST_MESSAGE (0x0028) #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029) +#define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030) /* MPI v2.6 and later */ +#define MPI2_EVENT_PCIE_ENUMERATION (0x0031) /* MPI v2.6 and later */ +#define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032) /* MPI v2.6 and later */ +#define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033) /* MPI v2.6 and later */ +#define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034) /* MPI v2.6 and later */ #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E) #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F) @@ -624,7 +677,7 @@ typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t; -/* Power Performance Change Event */ +/* Power Performance Change Event data */ typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE { @@ -650,6 +703,24 @@ typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE #define MPI2_EVENT_PM_MODE_STANDBY (0x06) +/* Active Cable Exception Event data */ + +typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT +{ + U32 ActiveCablePowerRequirement; /* 0x00 */ + U8 ReasonCode; /* 0x04 */ + U8 ReceptacleID; /* 0x05 */ + U16 Reserved1; /* 0x06 */ +} MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, + MPI2_POINTER PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT, + Mpi26EventDataActiveCableExcept_t, + MPI2_POINTER pMpi26EventDataActiveCableExcept_t; + +/* defines for ReasonCode field */ +#define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00) +#define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01) +#define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02) + /* Hard Reset Received Event data */ typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED @@ -1004,6 +1075,7 @@ typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B) +#define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C) /* values for the PhyStatus field */ #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) @@ -1031,12 +1103,19 @@ typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, Mpi2EventDataSasEnclDevStatusChange_t, - MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; + MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t, + MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE, + MPI2_POINTER PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE, + Mpi26EventDataEnclDevStatusChange_t, + MPI2_POINTER pMpi26EventDataEnclDevStatusChange_t; /* SAS Enclosure Device Status Change event ReasonCode values */ #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) +/* Enclosure Device Status Change event ReasonCode values */ +#define MPI26_EVENT_ENCL_RC_ADDED (0x01) +#define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02) /* SAS PHY Counter Event data */ @@ -1124,6 +1203,166 @@ typedef struct _MPI2_EVENT_DATA_HBD_PHY #define MPI2_EVENT_HBD_DT_SAS (0x01) +/* PCIe Device Status Change Event data (MPI v2.6 and later) */ + +typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE +{ + U16 TaskTag; /* 0x00 */ + U8 ReasonCode; /* 0x02 */ + U8 PhysicalPort; /* 0x03 */ + U8 ASC; /* 0x04 */ + U8 ASCQ; /* 0x05 */ + U16 DevHandle; /* 0x06 */ + U32 Reserved2; /* 0x08 */ + U64 WWID; /* 0x0C */ + U8 LUN[8]; /* 0x14 */ +} MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE, + MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE, + Mpi26EventDataPCIeDeviceStatusChange_t, + MPI2_POINTER pMpi26EventDataPCIeDeviceStatusChange_t; + +/* PCIe Device Status Change Event data ReasonCode values */ +#define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05) +#define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07) +#define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) +#define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) +#define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) +#define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) +#define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) +#define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) +#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) +#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) +#define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10) + + +/* PCIe Enumeration Event data (MPI v2.6 and later) */ + +typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION +{ + U8 Flags; /* 0x00 */ + U8 ReasonCode; /* 0x01 */ + U8 PhysicalPort; /* 0x02 */ + U8 Reserved1; /* 0x03 */ + U32 EnumerationStatus; /* 0x04 */ +} MPI26_EVENT_DATA_PCIE_ENUMERATION, + MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION, + Mpi26EventDataPCIeEnumeration_t, + MPI2_POINTER pMpi26EventDataPCIeEnumeration_t; + +/* PCIe Enumeration Event data Flags values */ +#define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02) +#define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01) + +/* PCIe Enumeration Event data ReasonCode values */ +#define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01) +#define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02) + +/* PCIe Enumeration Event data EnumerationStatus values */ +#define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000) +#define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000) +#define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000) + + +/* PCIe Topology Change List Event data (MPI v2.6 and later) */ + +/* + * Host code (drivers, BIOS, utilities, etc.) should leave this define set to + * one and check NumEntries at runtime. + */ +#ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT +#define MPI26_EVENT_PCIE_TOPO_PORT_COUNT (1) +#endif + +typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY +{ + U16 AttachedDevHandle; /* 0x00 */ + U8 PortStatus; /* 0x02 */ + U8 Reserved1; /* 0x03 */ + U8 CurrentPortInfo; /* 0x04 */ + U8 Reserved2; /* 0x05 */ + U8 PreviousPortInfo; /* 0x06 */ + U8 Reserved3; /* 0x07 */ +} MPI26_EVENT_PCIE_TOPO_PORT_ENTRY, + MPI2_POINTER PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY, + Mpi26EventPCIeTopoPortEntry_t, + MPI2_POINTER pMpi26EventPCIeTopoPortEntry_t; + +/* PCIe Topology Change List Event data PortStatus values */ +#define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01) +#define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02) +#define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03) +#define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04) +#define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05) + +/* PCIe Topology Change List Event data defines for CurrentPortInfo and PreviousPortInfo */ +#define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0) +#define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) +#define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10) +#define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20) +#define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30) +#define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40) + +#define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F) +#define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) +#define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) +#define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) +#define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03) +#define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04) +#define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05) + +typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST +{ + U16 EnclosureHandle; /* 0x00 */ + U16 SwitchDevHandle; /* 0x02 */ + U8 NumPorts; /* 0x04 */ + U8 Reserved1; /* 0x05 */ + U16 Reserved2; /* 0x06 */ + U8 NumEntries; /* 0x08 */ + U8 StartPortNum; /* 0x09 */ + U8 SwitchStatus; /* 0x0A */ + U8 PhysicalPort; /* 0x0B */ + MPI26_EVENT_PCIE_TOPO_PORT_ENTRY PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /* 0x0C */ +} MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, + MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST, + Mpi26EventDataPCIeTopologyChangeList_t, + MPI2_POINTER pMpi26EventDataPCIeTopologyChangeList_t; + +/* PCIe Topology Change List Event data SwitchStatus values */ +#define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00) +#define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01) +#define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02) +#define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03) +#define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04) + +/* PCIe Link Counter Event data (MPI v2.6 and later) */ + +typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER +{ + U64 TimeStamp; /* 0x00 */ + U32 Reserved1; /* 0x08 */ + U8 LinkEventCode; /* 0x0C */ + U8 LinkNum; /* 0x0D */ + U16 Reserved2; /* 0x0E */ + U32 LinkEventInfo; /* 0x10 */ + U8 CounterType; /* 0x14 */ + U8 ThresholdWindow; /* 0x15 */ + U8 TimeUnits; /* 0x16 */ + U8 Reserved3; /* 0x17 */ + U32 EventThreshold; /* 0x18 */ + U16 ThresholdFlags; /* 0x1C */ + U16 Reserved4; /* 0x1E */ +} MPI26_EVENT_DATA_PCIE_LINK_COUNTER, + MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER, + Mpi26EventDataPcieLinkCounter_t, MPI2_POINTER pMpi26EventDataPcieLinkCounter_t; + + +/* use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode field */ + +/* use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ + +/* use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ + +/* use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ /**************************************************************************** * EventAck message @@ -1250,6 +1489,13 @@ typedef struct _MPI2_FW_DOWNLOAD_REQUEST #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) /* MPI v2.5 and newer */ +#define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E) +#define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F) +#define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10) +#define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11) +#define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12) +#define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13) +#define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14) #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) /* MPI v2.0 FWDownload TransactionContext Element */ @@ -1342,6 +1588,14 @@ typedef struct _MPI2_FW_UPLOAD_REQUEST #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) +#define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D) +#define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E) +#define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F) +#define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10) +#define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11) +#define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12) +#define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13) +#define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14) /* MPI v2.0 FWUpload TransactionContext Element */ typedef struct _MPI2_FW_UPLOAD_TCSGE @@ -1430,7 +1684,7 @@ typedef struct _MPI2_FW_IMAGE_HEADER U32 Reserved54; /* 0x54 */ U32 Reserved58; /* 0x58 */ U32 Reserved5C; /* 0x5C */ - U32 Reserved60; /* 0x60 */ + U32 BootFlags; /* 0x60 */ /* reserved in MPI v2.5 and earlier */ U32 FirmwareVersionNameWhat; /* 0x64 */ U8 FirmwareVersionName[32]; /* 0x68 */ U32 VendorNameWhat; /* 0x88 */ @@ -1456,18 +1710,29 @@ typedef struct _MPI2_FW_IMAGE_HEADER #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) #define MPI2_FW_HEADER_SIGNATURE (0xEA000000) +#define MPI26_FW_HEADER_SIGNATURE (0xEB000000) /* Signature0 field */ #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) +#define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500) /* Last byte is defined by architecture */ +#define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A) +#define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00) +#define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01) +#define MPI26_FW_HEADER_SIGNATURE0_ARC_3 (0x02) +#define MPI26_FW_HEADER_SIGNATURE0 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0) // legacy (0x5AEAA55A) +#define MPI26_FW_HEADER_SIGNATURE0_3516 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1) +#define MPI26_FW_HEADER_SIGNATURE0_4008 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_3) /* Signature1 field */ #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) +#define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5) /* Signature2 field */ #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) +#define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA) /* defines for using the ProductID field */ @@ -1485,6 +1750,8 @@ typedef struct _MPI2_FW_IMAGE_HEADER #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021) +#define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028) +#define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031) /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ @@ -1493,6 +1760,7 @@ typedef struct _MPI2_FW_IMAGE_HEADER #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) +#define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60) #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) @@ -1606,7 +1874,16 @@ typedef struct _MPI2_FLASH_LAYOUT_DATA #define MPI2_FLASH_REGION_CONFIG_1 (0x07) #define MPI2_FLASH_REGION_CONFIG_2 (0x08) #define MPI2_FLASH_REGION_MEGARAID (0x09) -#define MPI2_FLASH_REGION_INIT (0x0A) +#define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A) +#define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK) /* older name */ +#define MPI2_FLASH_REGION_CBB_BACKUP (0x0D) +#define MPI2_FLASH_REGION_SBR (0x0E) +#define MPI2_FLASH_REGION_SBR_BACKUP (0x0F) +#define MPI2_FLASH_REGION_HIIM (0x10) +#define MPI2_FLASH_REGION_HIIA (0x11) +#define MPI2_FLASH_REGION_CTLR (0x12) +#define MPI2_FLASH_REGION_IMR_FIRMWARE (0x13) +#define MPI2_FLASH_REGION_MR_NVDATA (0x14) /* ImageRevision */ #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) @@ -1848,5 +2125,93 @@ typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; +/**************************************************************************** +* IO Unit Control messages (MPI v2.6 and later only.) +****************************************************************************/ + +/* IO Unit Control Request Message */ +typedef struct _MPI26_IOUNIT_CONTROL_REQUEST +{ + U8 Operation; /* 0x00 */ + U8 Reserved1; /* 0x01 */ + U8 ChainOffset; /* 0x02 */ + U8 Function; /* 0x03 */ + U16 DevHandle; /* 0x04 */ + U8 IOCParameter; /* 0x06 */ + U8 MsgFlags; /* 0x07 */ + U8 VP_ID; /* 0x08 */ + U8 VF_ID; /* 0x09 */ + U16 Reserved3; /* 0x0A */ + U16 Reserved4; /* 0x0C */ + U8 PhyNum; /* 0x0E */ + U8 PrimFlags; /* 0x0F */ + U32 Primitive; /* 0x10 */ + U8 LookupMethod; /* 0x14 */ + U8 Reserved5; /* 0x15 */ + U16 SlotNumber; /* 0x16 */ + U64 LookupAddress; /* 0x18 */ + U32 IOCParameterValue; /* 0x20 */ + U32 Reserved7; /* 0x24 */ + U32 Reserved8; /* 0x28 */ +} MPI26_IOUNIT_CONTROL_REQUEST, + MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REQUEST, + Mpi26IoUnitControlRequest_t, MPI2_POINTER pMpi26IoUnitControlRequest_t; + +/* values for the Operation field */ +#define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02) +#define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06) +#define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07) +#define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08) +#define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09) +#define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A) +#define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B) +#define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D) +#define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E) +#define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F) +#define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10) +#define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11) +#define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12) +#define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13) +#define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14) +#define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15) +#define MPI26_CTRL_OP_SHUTDOWN (0x16) +#define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17) +#define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18) +#define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19) +#define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A) +#define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B) +#define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80) + +/* values for the PrimFlags field */ +#define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08) +#define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02) +#define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01) + +/* values for the LookupMethod field */ +#define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01) +#define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02) +#define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03) + + +/* IO Unit Control Reply Message */ +typedef struct _MPI26_IOUNIT_CONTROL_REPLY +{ + U8 Operation; /* 0x00 */ + U8 Reserved1; /* 0x01 */ + U8 MsgLength; /* 0x02 */ + U8 Function; /* 0x03 */ + U16 DevHandle; /* 0x04 */ + U8 IOCParameter; /* 0x06 */ + U8 MsgFlags; /* 0x07 */ + U8 VP_ID; /* 0x08 */ + U8 VF_ID; /* 0x09 */ + U16 Reserved3; /* 0x0A */ + U16 Reserved4; /* 0x0C */ + U16 IOCStatus; /* 0x0E */ + U32 IOCLogInfo; /* 0x10 */ +} MPI26_IOUNIT_CONTROL_REPLY, MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REPLY, + Mpi26IoUnitControlReply_t, MPI2_POINTER pMpi26IoUnitControlReply_t; + + #endif diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ra.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ra.h index bf367a64b6..4a6126ebc6 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ra.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_ra.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,14 +29,16 @@ */ /* - * Copyright (c) 2009 LSI Corporation. + * Copyright (c) 2012-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2_ra.h * Title: MPI RAID Accelerator messages and structures * Creation Date: April 13, 2009 * - * mpi2_ra.h Version: 02.00.00 + * mpi2_ra.h Version: 02.00.01 * * Version History * --------------- @@ -43,6 +46,7 @@ * Date Version Description * -------- -------- ------------------------------------------------------ * 05-06-09 02.00.00 Initial version. + * 11-18-14 02.00.01 Updated copyright information. * -------------------------------------------------------------------------- */ diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h index 498e974e7d..ec43f55793 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,14 +29,16 @@ */ /* - * Copyright (c) 2000-2013 LSI Corporation. + * Copyright (c) 2000-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2_raid.h * Title: MPI Integrated RAID messages and structures * Creation Date: April 26, 2007 * - * mpi2_raid.h Version: 02.00.10 + * mpi2_raid.h Version: 02.00.11 * * Version History * --------------- @@ -60,6 +63,7 @@ * 07-26-12 02.00.09 Added ElapsedSeconds field to MPI2_RAID_VOL_INDICATOR. * Added MPI2_RAID_VOL_FLAGS_ELAPSED_SECONDS_VALID define. * 04-17-13 02.00.10 Added MPI25_RAID_ACTION_ADATA_ALLOW_PI. + * 11-18-14 02.00.11 Updated copyright information. * -------------------------------------------------------------------------- */ diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h index 8a24b3fc8b..110b8abe57 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,14 +29,16 @@ */ /* - * Copyright (c) 2000-2013 LSI Corporation. + * Copyright (c) 2000-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2_sas.h * Title: MPI Serial Attached SCSI structures and definitions * Creation Date: February 9, 2007 * - * mpi2_sas.h Version: 02.00.08 + * mpi2_sas.h Version: 02.00.10 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -61,6 +64,9 @@ * Passthrough Request message. * 08-19-13 02.00.08 Made MPI2_SAS_OP_TRANSMIT_PORT_SELECT_SIGNAL obsolete * for anything newer than MPI v2.0. + * 11-18-14 02.00.09 Updated copyright information. + * 03-16-15 02.00.10 Updated for MPI v2.6. + * Added MPI2_SATA_PT_REQ_PT_FLAGS_FPDMA. * -------------------------------------------------------------------------- */ @@ -220,6 +226,7 @@ typedef struct _MPI2_SATA_PASSTHROUGH_REQUEST /* values for PassthroughFlags field */ #define MPI2_SATA_PT_REQ_PT_FLAGS_EXECUTE_DIAG (0x0100) +#define MPI2_SATA_PT_REQ_PT_FLAGS_FPDMA (0x0040) /* MPI v2.6 and newer */ #define MPI2_SATA_PT_REQ_PT_FLAGS_DMA (0x0020) #define MPI2_SATA_PT_REQ_PT_FLAGS_PIO (0x0010) #define MPI2_SATA_PT_REQ_PT_FLAGS_UNSPECIFIED_VU (0x0004) @@ -256,6 +263,8 @@ typedef struct _MPI2_SATA_PASSTHROUGH_REPLY /**************************************************************************** * SAS IO Unit Control messages +* (MPI v2.5 and earlier only. +* Replaced by IO Unit Control messages in MPI v2.6 and later.) ****************************************************************************/ /* SAS IO Unit Control Request Message */ diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_targ.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_targ.h index dbf440a7d7..520adf9ae2 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_targ.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_targ.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,14 +29,16 @@ */ /* - * Copyright (c) 2000-2012 LSI Corporation. + * Copyright (c) 2000-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2_targ.h * Title: MPI Target mode messages and structures * Creation Date: September 8, 2006 * - * mpi2_targ.h Version: 02.00.06 + * mpi2_targ.h Version: 02.00.09 * * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 * prefix are for use only on MPI v2.5 products, and must not be used @@ -61,6 +64,11 @@ * request message structure. * Added AbortType MPI2_TARGET_MODE_ABORT_DEVHANDLE and * MPI2_TARGET_MODE_ABORT_ALL_COMMANDS. + * 06-13-14 02.00.07 Added MinMSIxIndex and MaxMSIxIndex fields to + * MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST. + * 11-18-14 02.00.08 Updated copyright information. + * 03-16-15 02.00.09 Updated for MPI v2.6. + * Added MPI26_TARGET_ASSIST_IOFLAGS_ESCAPE_PASSTHROUGH. * -------------------------------------------------------------------------- */ @@ -92,7 +100,8 @@ typedef struct _MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST U16 Reserved2; /* 0x0A */ U32 Reserved3; /* 0x0C */ U16 CmdBufferLength; /* 0x10 */ - U16 Reserved4; /* 0x12 */ + U8 MinMSIxIndex; /* 0x12 */ /* MPI 2.5 and newer only; Reserved in MPI 2.0 */ + U8 MaxMSIxIndex; /* 0x13 */ /* MPI 2.5 and newer only; Reserved in MPI 2.0 */ U32 BaseAddressLow; /* 0x14 */ U32 BaseAddressHigh; /* 0x18 */ } MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST, @@ -104,8 +113,9 @@ typedef struct _MPI2_TARGET_CMD_BUF_POST_BASE_REQUEST #define MPI2_CMD_BUF_POST_BASE_ADDRESS_SPACE_MASK (0x0C) #define MPI2_CMD_BUF_POST_BASE_SYSTEM_ADDRESS_SPACE (0x00) #define MPI2_CMD_BUF_POST_BASE_IOCDDR_ADDRESS_SPACE (0x04) -#define MPI2_CMD_BUF_POST_BASE_IOCPLB_ADDRESS_SPACE (0x08) -#define MPI2_CMD_BUF_POST_BASE_IOCPLBNTA_ADDRESS_SPACE (0x0C) +#define MPI2_CMD_BUF_POST_BASE_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */ +#define MPI26_CMD_BUF_POST_BASE_IOCCTL_ADDRESS_SPACE (0x08) /* for MPI v2.6 only */ +#define MPI2_CMD_BUF_POST_BASE_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */ #define MPI2_CMD_BUF_POST_BASE_FLAGS_AUTO_POST_ALL (0x01) @@ -400,6 +410,7 @@ typedef struct _MPI25_TARGET_ASSIST_REQUEST #define MPI25_TA_DMAFLAGS_OP_D_H_I_I (0x0F) /* defines for the IoFlags field */ +#define MPI26_TARGET_ASSIST_IOFLAGS_ESCAPE_PASSTHROUGH (0x2000) /* MPI v2.6 and later */ #define MPI25_TARGET_ASSIST_IOFLAGS_BIDIRECTIONAL (0x0800) #define MPI25_TARGET_ASSIST_IOFLAGS_RECEIVE_FIRST (0x0200) diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h index 08669bbf03..fd5bee2ccb 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,14 +29,16 @@ */ /* - * Copyright (c) 2000-2013 LSI Corporation. + * Copyright (c) 2000-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2_tool.h * Title: MPI diagnostic tool structures and definitions * Creation Date: March 26, 2007 * - * mpi2_tool.h Version: 02.00.11 + * mpi2_tool.h Version: 02.00.14 * * Version History * --------------- @@ -62,6 +65,10 @@ * 07-26-12 02.00.10 Modified MPI2_TOOLBOX_DIAGNOSTIC_CLI_REQUEST so that * it uses MPI Chain SGE as well as MPI Simple SGE. * 08-19-13 02.00.11 Added MPI2_TOOLBOX_TEXT_DISPLAY_TOOL and related info. + * 01-08-14 02.00.12 Added MPI2_TOOLBOX_CLEAN_BIT26_PRODUCT_SPECIFIC. + * 11-18-14 02.00.13 Updated copyright information. + * 08-25-16 02.00.14 Added new values for the Flags field of Toolbox Clean + * Tool Request Message. * -------------------------------------------------------------------------- */ @@ -133,8 +140,19 @@ typedef struct _MPI2_TOOLBOX_CLEAN_REQUEST #define MPI2_TOOLBOX_CLEAN_OTHER_PERSIST_PAGES (0x20000000) #define MPI2_TOOLBOX_CLEAN_FW_CURRENT (0x10000000) #define MPI2_TOOLBOX_CLEAN_FW_BACKUP (0x08000000) +#define MPI2_TOOLBOX_CLEAN_BIT26_PRODUCT_SPECIFIC (0x04000000) #define MPI2_TOOLBOX_CLEAN_MEGARAID (0x02000000) #define MPI2_TOOLBOX_CLEAN_INITIALIZATION (0x01000000) +#define MPI2_TOOLBOX_CLEAN_SBR (0x00800000) +#define MPI2_TOOLBOX_CLEAN_SBR_BACKUP (0x00400000) +#define MPI2_TOOLBOX_CLEAN_HIIM (0x00200000) +#define MPI2_TOOLBOX_CLEAN_HIIA (0x00100000) +#define MPI2_TOOLBOX_CLEAN_CTLR (0x00080000) +#define MPI2_TOOLBOX_CLEAN_IMR_FIRMWARE (0x00040000) +#define MPI2_TOOLBOX_CLEAN_MR_NVDATA (0x00020000) +#define MPI2_TOOLBOX_CLEAN_RESERVED_5_16 (0x0001FFE0) +#define MPI2_TOOLBOX_CLEAN_ALL_BUT_MPB (0x00000010) +#define MPI2_TOOLBOX_CLEAN_ENTIRE_FLASH (0x00000008) #define MPI2_TOOLBOX_CLEAN_FLASH (0x00000004) #define MPI2_TOOLBOX_CLEAN_SEEPROM (0x00000002) #define MPI2_TOOLBOX_CLEAN_NVSRAM (0x00000001) diff --git a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h index a07d58394f..8e73fa2b41 100644 --- a/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h +++ b/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h @@ -1,5 +1,6 @@ /*- - * Copyright (c) 2013 LSI Corp. + * Copyright (c) 2012-2015 LSI Corp. + * Copyright (c) 2013-2016 Avago Technologies * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -28,14 +29,16 @@ */ /* - * Copyright (c) 2000-2007 LSI Corporation. + * Copyright (c) 2000-2015 LSI Corporation. + * Copyright (c) 2013-2016 Avago Technologies + * All rights reserved. * * * Name: mpi2_type.h * Title: MPI basic type definitions * Creation Date: August 16, 2006 * - * mpi2_type.h Version: 02.00.00 + * mpi2_type.h Version: 02.00.01 * * Version History * --------------- @@ -43,6 +46,7 @@ * Date Version Description * -------- -------- ------------------------------------------------------ * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. + * 11-18-14 02.00.01 Updated copyright information. * -------------------------------------------------------------------------- */ diff --git a/usr/src/uts/intel/mpt_sas/Makefile b/usr/src/uts/intel/mpt_sas/Makefile index d0d809c3b5..9886d6ccd5 100644 --- a/usr/src/uts/intel/mpt_sas/Makefile +++ b/usr/src/uts/intel/mpt_sas/Makefile @@ -57,9 +57,7 @@ INSTALL_TARGET = $(BINARY) $(ROOTMODULE) $(ROOT_CONFFILE) # include $(UTSBASE)/intel/Makefile.intel -CERRWARN += -_gcc=-Wno-parentheses CERRWARN += -_gcc=-Wno-uninitialized -CERRWARN += -_gcc=-Wno-switch # # Default build targets. |