14041 Dell R650 Xeon Gold 5318Y not booting

Reviewed by: Robert Mustacchi <rm+illumos@fingolfin.org>
Reviewed by: Andy Fiddaman <andy@omnios.org>
Approved by: Dan McDonald <danmcd@mnx.io>

4 files changed, 29 insertions, 3 deletions

diff --git a/usr/src/cmd/mdb/intel/mdb/mdb_x86util.c b/usr/src/cmd/mdb/intel/mdb/mdb_x86util.c
index a01ee6cffb..447b235900 100644
--- a/usr/src/cmd/mdb/intel/mdb/mdb_x86util.c
+++ b/usr/src/cmd/mdb/intel/mdb/mdb_x86util.c
@@ -11,6 +11,7 @@
 
 /*
  * Copyright 2019 Joyent, Inc.
+ * Copyright 2022 Tintri by DDN, Inc. All rights reserved.
  */
 
 /*
@@ -155,6 +156,7 @@ mdb_x86_print_sysregs(struct sysregs *sregs, boolean_t long_mode)
 		{ "OSFXSR",	CR4_OSFXSR,	CR4_OSFXSR },
 		{ "OSXMMEXCPT",	CR4_OSXMMEXCPT,	CR4_OSXMMEXCPT },
 		{ "UMIP",	CR4_UMIP,	CR4_UMIP },
+		{ "LA57",	CR4_LA57,	CR4_LA57 },
 		{ "VMXE",	CR4_VMXE,	CR4_VMXE },
 		{ "SMXE",	CR4_SMXE,	CR4_SMXE },
 		{ "FSGSBASE",	CR4_FSGSBASE,	CR4_FSGSBASE },
diff --git a/usr/src/uts/i86pc/sys/mach_mmu.h b/usr/src/uts/i86pc/sys/mach_mmu.h
index 22c7aac422..934c8895cf 100644
--- a/usr/src/uts/i86pc/sys/mach_mmu.h
+++ b/usr/src/uts/i86pc/sys/mach_mmu.h
@@ -23,6 +23,7 @@
  * Use is subject to license terms.
  *
  * Copyright 2018 Joyent, Inc.
+ * Copyright 2022 Tintri by DDN, Inc. All rights reserved.
  */
 
 #ifndef _SYS_MACH_MMU_H
@@ -59,6 +60,15 @@ extern "C" {
 #define	FOUR_GIG	((uint64_t)4 * ONE_GIG)
 
 #define	MMU_STD_PAGESIZE	4096
+
+/*
+ * Defines for 4 and 5 level Virtual address ranges
+ */
+#define	MMU_NPGOFFBITS		12
+#define	MMU_NPTIXBITS		9
+#define	MMU_MAX4LEVELVABITS	(4 * MMU_NPTIXBITS + MMU_NPGOFFBITS)
+#define	MMU_MAX5LEVELVABITS	(5 * MMU_NPTIXBITS + MMU_NPGOFFBITS)
+
 #ifdef __amd64
 #define	MMU_STD_PAGEMASK	0xFFFFFFFFFFFFF000ULL
 #else
diff --git a/usr/src/uts/i86pc/vm/hat_i86.c b/usr/src/uts/i86pc/vm/hat_i86.c
index 76a6a0575c..7650d28f41 100644
--- a/usr/src/uts/i86pc/vm/hat_i86.c
+++ b/usr/src/uts/i86pc/vm/hat_i86.c
@@ -29,6 +29,7 @@
  * Copyright 2011 Nexenta Systems, Inc.  All rights reserved.
  * Copyright 2018 Joyent, Inc.  All rights reserved.
  * Copyright (c) 2014, 2015 by Delphix. All rights reserved.
+ * Copyright 2022 Tintri by DDN, Inc. All rights reserved.
  */
 
 /*
@@ -850,6 +851,18 @@ mmu_init(void)
 	 */
 	cpuid_get_addrsize(CPU, &pa_bits, &va_bits);
 
+	/*
+	 * Check if 5 level paging is on, we dont support that (yet).
+	 * X86_64 processors that support 5 level paging report
+	 * the number of va bits for 5 level paging even if
+	 * not in 5 level paging mode.  So we need
+	 * to adjust va_bits to max for 4 level paging if not in 5 level mode.
+	 */
+	if ((getcr4() & CR4_LA57) != 0)
+		panic("5 Level paging enabled but not yet supported");
+	else if (va_bits > MMU_MAX4LEVELVABITS)
+		va_bits = MMU_MAX4LEVELVABITS;
+
 	if (va_bits < sizeof (void *) * NBBY) {
 		mmu.hole_start = (1ul << (va_bits - 1));
 		mmu.hole_end = 0ul - mmu.hole_start - 1;
diff --git a/usr/src/uts/intel/sys/controlregs.h b/usr/src/uts/intel/sys/controlregs.h
index 9c02a4b809..22d1f8c766 100644
--- a/usr/src/uts/intel/sys/controlregs.h
+++ b/usr/src/uts/intel/sys/controlregs.h
@@ -21,6 +21,7 @@
 /*
  * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
  * Copyright 2018, Joyent, Inc.
+ * Copyright 2022 Tintri by DDN, Inc. All rights reserved.
  */
 
 #ifndef	_SYS_CONTROLREGS_H
@@ -111,7 +112,7 @@ extern "C" {
 #define	CR4_OSFXSR	0x0200		/* OS fxsave/fxrstor support	*/
 #define	CR4_OSXMMEXCPT	0x0400		/* OS unmasked exception support */
 #define	CR4_UMIP	0x0800		/* user-mode instruction prevention */
-					/* 0x1000 reserved */
+#define	CR4_LA57	0x1000		/* enable 57 bit Logical addressing */
 #define	CR4_VMXE	0x2000		/* VMX enable */
 #define	CR4_SMXE	0x4000		/* SMX enable */
 					/* 0x8000 reserved */
@@ -124,8 +125,8 @@ extern "C" {
 
 #define	FMT_CR4						\
 	"\20\27pke\26smap\25smep\23osxsav"		\
-	"\22pcide\20fsgsbase\17smxe\16vmxe"		\
-	"\14umip\13xmme\12fxsr\11pce\10pge"		\
+	"\22pcide\21fsgsbase\17smxe\16vmxe"		\
+	"\15la57\14umip\13xmme\12fxsr\11pce\10pge"	\
 	"\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
 
 /*