14764 AHCI DEVSLEEP 1.3.1 problematic

Reviewed by: Robert Mustacchi <rm+illumos@fingolfin.org>
Reviewed by: Jerry Jelinek <gjelinek@gmail.com>
Reviewed by: Andrew Stormont <andyjstormont@gmail.com>
Approved by: Gordon Ross <gordon.w.ross@gmail.com>

4 files changed, 30 insertions, 6 deletions

diff --git a/usr/src/uts/common/io/sata/adapters/ahci/ahci.c b/usr/src/uts/common/io/sata/adapters/ahci/ahci.c
index e3b6d2fa8d..ead7433aef 100644
--- a/usr/src/uts/common/io/sata/adapters/ahci/ahci.c
+++ b/usr/src/uts/common/io/sata/adapters/ahci/ahci.c
@@ -24,6 +24,7 @@
  * Copyright 2018 Nexenta Systems, Inc.  All rights reserved.
  * Copyright (c) 2018, Joyent, Inc.
  * Copyright 2018 OmniOS Community Edition (OmniOSce) Association.
+ * Copyright 2021 RackTop Systems, Inc.
  */
 
 /*
@@ -780,6 +781,10 @@ ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
 
 		AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
 		    "hba capabilities extended = 0x%x", cap2_status);
+
+		if (cap2_status & AHCI_HBA_CAP2_SDS) {
+			ahci_ctlp->ahcictl_cap |= AHCI_CAP_SDS;
+		}
 	}
 
 	if (cap_status & AHCI_HBA_CAP_EMS) {
@@ -5934,7 +5939,7 @@ ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
  * According to the spec, to reliably detect hot plug removals, software
  * must disable interface power management. Software should perform the
  * following initialization on a port after a device is attached:
- *   Set PxSCTL.IPM to 3h to disable interface state transitions
+ *   Set PxSCTL.IPM to 3h or 7h to disable interface state transitions
  *   Set PxCMD.ALPE to '0' to disable aggressive power management
  *   Disable device initiated interface power management by SET FEATURE
  *
@@ -5944,10 +5949,16 @@ static void
 ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port)
 {
 	uint32_t port_scontrol, port_cmd_status;
+	uint32_t ipm;
 
 	port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
 	    (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port));
-	SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH);
+	if (ahci_ctlp->ahcictl_cap & AHCI_CAP_SDS) {
+		ipm = SCONTROL_IPM_DISABLE_ALL;
+	} else {
+		ipm = SCONTROL_IPM_DISABLE_BOTH;
+	}
+	SCONTROL_SET_IPM(port_scontrol, ipm);
 	ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
 	    (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol);
 
diff --git a/usr/src/uts/common/sys/sata/adapters/ahci/ahcireg.h b/usr/src/uts/common/sys/sata/adapters/ahci/ahcireg.h
index e738783dfe..1f7c8f71ef 100644
--- a/usr/src/uts/common/sys/sata/adapters/ahci/ahcireg.h
+++ b/usr/src/uts/common/sys/sata/adapters/ahci/ahcireg.h
@@ -25,6 +25,7 @@
  */
 /*
  * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
+ * Copyright 2021 RackTop Systems, Inc.
  */
 
 #ifndef _AHCIREG_H
@@ -68,7 +69,6 @@ extern "C" {
 #define	AHCI_HBA_CAP_FBSS	(0x1 << 16) /* FIS-based switching */
 #define	AHCI_HBA_CAP_SPM	(0x1 << 17) /* port multiplier */
 #define	AHCI_HBA_CAP_SAM	(0x1 << 18) /* AHCI mode only */
-#define	AHCI_HBA_CAP_SNZO	(0x1 << 19) /* non-zero DMA offsets */
 #define	AHCI_HBA_CAP_ISS	(0xf << 20) /* interface speed support */
 #define	AHCI_HBA_CAP_SCLO	(0x1 << 24) /* command list override */
 #define	AHCI_HBA_CAP_SAL	(0x1 << 25) /* activity LED */
@@ -114,6 +114,12 @@ extern "C" {
 #define	AHCI_HBA_EM_CTL_ATTR_ALHD	(0x1 << 26) /* Activity LED HW Driven */
 #define	AHCI_HBA_EM_CTL_ATTR_PM		(0x1 << 27) /* PM Support */
 
+#define	AHCI_HBA_CAP2_BOH	(0x1 << 0) /* BIOS/OS Handoff */
+#define	AHCI_HBA_CAP2_NVMP	(0x1 << 1) /* NVMHCI present */
+#define	AHCI_HBA_CAP2_APST	(0x1 << 2) /* Auto Partial to Slumber */
+#define	AHCI_HBA_CAP2_SDS	(0x1 << 3) /* Device Sleep */
+#define	AHCI_HBA_CAP2_SADM	(0x1 << 4) /* Aggressive Dev Sleep Mgmt */
+#define	AHCI_HBA_CAP2_DESO	(0x1 << 5) /* DevSleep from Slumber Only */
 
 /* global HBA registers definitions */
 #define	AHCI_GLOBAL_OFFSET(ahci_ctlp)	(ahci_ctlp->ahcictl_ahci_addr)
@@ -313,7 +319,7 @@ typedef struct ahci_fis_h2d_register {
 	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= (type & 0xff))
 
 #define	SET_FIS_PMP(fis, pmp)					\
-	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |= 	\
+	(fis->ahcifhr_type_pmp_rsvd_cmddevctl_cmd_features |=	\
 		((pmp & 0xf) << 8))
 
 #define	SET_FIS_CDMDEVCTL(fis, cmddevctl)			\
@@ -396,7 +402,7 @@ typedef struct ahci_fis_h2d_register {
 	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl & 0xff)
 
 #define	SET_FIS_SECTOR_COUNT(fis, sector_count)			\
-	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= 	\
+	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=	\
 		((sector_count & 0xff)))
 
 #define	GET_FIS_SECTOR_COUNT_EXP(fis)				\
@@ -407,7 +413,7 @@ typedef struct ahci_fis_h2d_register {
 		((sector_count_exp & 0xff) << 8))
 
 #define	SET_FIS_DEVCTL(fis, devctl)				\
-	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |= 	\
+	(fis->ahcifhr_sectcount_sectcountexp_rsvd_devctl |=	\
 		((devctl & 0xff) << 24))
 
 	/* offset 0x10 */
diff --git a/usr/src/uts/common/sys/sata/adapters/ahci/ahcivar.h b/usr/src/uts/common/sys/sata/adapters/ahci/ahcivar.h
index 8195242dd3..34bcacc576 100644
--- a/usr/src/uts/common/sys/sata/adapters/ahci/ahcivar.h
+++ b/usr/src/uts/common/sys/sata/adapters/ahci/ahcivar.h
@@ -23,6 +23,7 @@
  * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
  * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
  * Copyright (c) 2018, Joyent, Inc.
+ * Copyright 2021 RackTop Systems, Inc.
  */
 
 
@@ -517,6 +518,8 @@ _NOTE(MUTEX_PROTECTS_DATA(ahci_ctl_t::ahcictl_mutex,
 #define	AHCI_CAP_SRST_NO_HOSTPORT	0x800
 /* Enclosure Management Services available */
 #define	AHCI_CAP_EMS			0x1000
+/* DevSleep Supported */
+#define	AHCI_CAP_SDS			0x2000
 
 /* Flags controlling the restart port behavior */
 #define	AHCI_PORT_RESET		0x0001	/* Reset the port */
diff --git a/usr/src/uts/common/sys/sata/sata_defs.h b/usr/src/uts/common/sys/sata/sata_defs.h
index f3a3a1d481..de7667b770 100644
--- a/usr/src/uts/common/sys/sata/sata_defs.h
+++ b/usr/src/uts/common/sys/sata/sata_defs.h
@@ -23,6 +23,7 @@
  * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
  * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
  * Copyright 2019 Joyent, Inc.
+ * Copyright 2021 RackTop Systems, Inc.
  */
 
 #ifndef _SATA_DEFS_H
@@ -827,10 +828,13 @@ struct mode_acoustic_management {
 	(x = (x & ~SCONTROL_IPM) | \
 	((new_val << SCONTROL_IPM_SHIFT) & SCONTROL_IPM))
 
+/* NB: IPM disable value is a bit-field (though not described) */
 #define	SCONTROL_IPM_NORESTRICT		0 /* No PM limit */
 #define	SCONTROL_IPM_DISABLE_PARTIAL	1 /* Disable partial */
 #define	SCONTROL_IPM_DISABLE_SLUMBER	2 /* Disable slumber */
 #define	SCONTROL_IPM_DISABLE_BOTH	3 /* Disable both */
+#define	SCONTROL_IPM_DISABLE_DEVSLEEP	4 /* Disable devsleep */
+#define	SCONTROL_IPM_DISABLE_ALL	7 /* Disable all PM */
 
 #define	SCONTROL_SPM_NORESTRICT		0 /* No PM limits */
 #define	SCONTROL_SPM_DO_PARTIAL		1 /* Go to partial */