diff options
| author | Jerry Jelinek <jerry.jelinek@joyent.com> | 2016-12-30 13:09:20 +0000 |
|---|---|---|
| committer | Jerry Jelinek <jerry.jelinek@joyent.com> | 2016-12-30 13:09:20 +0000 |
| commit | 5799bf1e75edab0945b880f7e6c9542bd5e243f3 (patch) | |
| tree | 0b7fe6905532dd78e5bfefa21b88352f09ccb05b | |
| parent | 338d6131997ff968ca93a2929b45d5e7776fcc53 (diff) | |
| parent | fee52838cd1191a3efe83b67de7bccdd401af35e (diff) | |
| download | illumos-joyent-5799bf1e75edab0945b880f7e6c9542bd5e243f3.tar.gz | |
[illumos-gate merge]
commit fee52838cd1191a3efe83b67de7bccdd401af35e
7696 procfs lacks adequate access checks for CREAT actions
commit de48325308952b7883679d1687191f3ffe507b19
7539 Chelsio Terminator 5 NIC driver for illumos
28 files changed, 61141 insertions, 1734 deletions
diff --git a/exception_lists/cstyle b/exception_lists/cstyle index dd9bbb02c2..e10642f884 100644 --- a/exception_lists/cstyle +++ b/exception_lists/cstyle @@ -1082,6 +1082,7 @@ usr/src/uts/common/io/bge/bge_kstats.c usr/src/uts/common/io/bge/bge_impl.h usr/src/uts/common/io/bge/bge_send.c usr/src/uts/common/io/bge/bge_hw.h +usr/src/uts/common/io/cxgbe/* usr/src/uts/common/io/e1000api/e1000_80003es2lan.c usr/src/uts/common/io/e1000api/e1000_80003es2lan.h usr/src/uts/common/io/e1000api/e1000_82540.c diff --git a/exception_lists/hdrchk b/exception_lists/hdrchk index 11bbaa0653..7f070c1e00 100644 --- a/exception_lists/hdrchk +++ b/exception_lists/hdrchk @@ -369,6 +369,7 @@ usr/src/uts/common/io/bnxe/bnxe_binding.h usr/src/uts/common/io/bnxe/bnxe_debug.h usr/src/uts/common/io/bnxe/bnxe.h usr/src/uts/common/io/bnxe/version.h +usr/src/uts/common/io/cxgbe/firmware/* usr/src/uts/common/io/e1000api/e1000_80003es2lan.h usr/src/uts/common/io/e1000api/e1000_82541.h usr/src/uts/common/io/e1000api/e1000_82543.h diff --git a/usr/src/pkg/manifests/driver-network-cxgbe.mf b/usr/src/pkg/manifests/driver-network-cxgbe.mf index 2570eb4c17..cb5a219aaa 100644 --- a/usr/src/pkg/manifests/driver-network-cxgbe.mf +++ b/usr/src/pkg/manifests/driver-network-cxgbe.mf @@ -10,14 +10,14 @@ # # -# Copyright (c) 2013 by Chelsio Communications, Inc. All rights reserved. +# Copyright (c) 2016 by Chelsio Communications, Inc. All rights reserved. # <include global_zone_only_component> set name=pkg.fmri value=pkg:/driver/network/cxgbe@$(PKGVERS) set name=pkg.description \ - value="Chelsio Terminator 4 10 Gigabit Ethernet Adapter Driver" -set name=pkg.summary value="Chelsio Terminator 4 10GE NIC Driver" + value="Chelsio T4/T5 10/40 Gigabit Ethernet Adapter Driver" +set name=pkg.summary value="Chelsio T4/T5 10/40GE NIC Driver" set name=info.classification \ value=org.opensolaris.category.2008:Drivers/Networking set name=variant.arch value=i386 @@ -41,7 +41,52 @@ driver name=t4nex clone_perms="t4nex 0666 root sys" \ alias=pciex1425,4409 \ alias=pciex1425,440a \ alias=pciex1425,440d \ - alias=pciex1425,440e + alias=pciex1425,440e \ + alias=pciex1425,5400 \ + alias=pciex1425,5401 \ + alias=pciex1425,5402 \ + alias=pciex1425,5403 \ + alias=pciex1425,5404 \ + alias=pciex1425,5405 \ + alias=pciex1425,5406 \ + alias=pciex1425,5407 \ + alias=pciex1425,5408 \ + alias=pciex1425,5409 \ + alias=pciex1425,540a \ + alias=pciex1425,540b \ + alias=pciex1425,540c \ + alias=pciex1425,540d \ + alias=pciex1425,540e \ + alias=pciex1425,540f \ + alias=pciex1425,5410 \ + alias=pciex1425,5411 \ + alias=pciex1425,5412 \ + alias=pciex1425,5413 \ + alias=pciex1425,5414 \ + alias=pciex1425,5415 \ + alias=pciex1425,5416 \ + alias=pciex1425,5417 \ + alias=pciex1425,5418 \ + alias=pciex1425,5480 \ + alias=pciex1425,5481 \ + alias=pciex1425,5482 \ + alias=pciex1425,5486 \ + alias=pciex1425,5487 \ + alias=pciex1425,5488 \ + alias=pciex1425,5489 \ + alias=pciex1425,5490 \ + alias=pciex1425,5491 \ + alias=pciex1425,5492 \ + alias=pciex1425,5493 \ + alias=pciex1425,5494 \ + alias=pciex1425,5495 \ + alias=pciex1425,5496 \ + alias=pciex1425,5497 \ + alias=pciex1425,5498 \ + alias=pciex1425,5499 \ + alias=pciex1425,549a \ + alias=pciex1425,549b \ + alias=pciex1425,549c file path=kernel/drv/$(ARCH64)/cxgbe group=sys file path=kernel/drv/$(ARCH64)/t4nex group=sys $(i386_ONLY)file path=kernel/drv/cxgbe group=sys diff --git a/usr/src/uts/common/Makefile.files b/usr/src/uts/common/Makefile.files index 47455a470a..ec084abfe5 100644 --- a/usr/src/uts/common/Makefile.files +++ b/usr/src/uts/common/Makefile.files @@ -1979,7 +1979,7 @@ CH_COM_OBJS = ch_mac.o ch_subr.o cspi.o espi.o ixf1010.o mc3.o mc4.o mc5.o \ # # Chelsio Terminator 4 10G NIC nexus driver module # -CXGBE_FW_OBJS = t4_fw.o t4_cfg.o +CXGBE_FW_OBJS = t4_fw.o t4_cfg.o t5_cfg.o t5_fw.o CXGBE_COM_OBJS = t4_hw.o common.o CXGBE_NEX_OBJS = t4_nexus.o t4_sge.o t4_mac.o t4_ioctl.o shared.o \ t4_l2t.o adapter.o osdep.o diff --git a/usr/src/uts/common/io/cxgbe/common/common.c b/usr/src/uts/common/io/cxgbe/common/common.c index 7023a41b56..c5ec511ff2 100644 --- a/usr/src/uts/common/io/cxgbe/common/common.c +++ b/usr/src/uts/common/io/cxgbe/common/common.c @@ -66,6 +66,21 @@ is_bypass(const adapter_t *adap) return (adap->params.bypass); } +int is_t4(enum chip_type chip) +{ + return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4); +} + +int is_t5(enum chip_type chip) +{ + return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); +} + +int is_fpga(enum chip_type chip) +{ + return chip & CHELSIO_CHIP_FPGA; +} + int is_bypass_device(int device) { diff --git a/usr/src/uts/common/io/cxgbe/common/common.h b/usr/src/uts/common/io/cxgbe/common/common.h index fc2007ce00..09e67b14b5 100644 --- a/usr/src/uts/common/io/cxgbe/common/common.h +++ b/usr/src/uts/common/io/cxgbe/common/common.h @@ -25,6 +25,7 @@ #include "shared.h" #include "t4_hw.h" +#include "t4_chip_type.h" #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC | F_EDC0 | \ F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ @@ -39,15 +40,19 @@ enum { MACADDR_LEN = 12, /* MAC Address length */ }; -enum { MEM_EDC0, MEM_EDC1, MEM_MC }; +enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; enum { MEMWIN0_APERTURE = 2048, MEMWIN0_BASE = 0x1b800, MEMWIN1_APERTURE = 32768, MEMWIN1_BASE = 0x28000, - MEMWIN2_APERTURE = 65536, - MEMWIN2_BASE = 0x30000, + + MEMWIN2_APERTURE_T4 = 65536, + MEMWIN2_BASE_T4 = 0x30000, + + MEMWIN2_APERTURE_T5 = 128 * 1024, + MEMWIN2_BASE_T5 = 0x60000, }; enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; @@ -60,6 +65,11 @@ enum { PAUSE_AUTONEG = 1 << 2 }; +struct memwin { + uint32_t base; + uint32_t aperture; +}; + struct port_stats { u64 tx_octets; /* total # of octets in good frames */ u64 tx_frames; /* all good frames */ @@ -194,7 +204,6 @@ struct tp_proxy_stats { struct tp_cpl_stats { u32 req[4]; u32 rsp[4]; - u32 tx_err[4]; }; struct tp_rdma_stats { @@ -221,7 +230,7 @@ struct vpd_params { struct pci_params { unsigned int vpd_cap_addr; - unsigned char speed; + unsigned short speed; unsigned char width; }; @@ -263,7 +272,15 @@ struct adapter_params { unsigned char bypass; + enum chip_type chip; /* chip code */ + unsigned int ofldq_wr_cred; + + unsigned int nsched_cls; /* number of traffic classes */ + + unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ + unsigned int max_ird_adapter; /* Max read depth per adapter */ + bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ }; enum { /* chip revisions */ @@ -335,7 +352,7 @@ int t4_seeprom_wp(struct adapter *adapter, int enable); int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, u32 *data, int byte_oriented); int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); -unsigned int t4_flash_cfg_addr(struct adapter *adapter); +int t4_flash_cfg_addr(struct adapter *adapter); int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); int t4_get_fw_version(struct adapter *adapter, u32 *vers); int t4_get_tp_version(struct adapter *adapter, u32 *vers); @@ -388,7 +405,8 @@ int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); -int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *parity); +int t4_mc_read(struct adapter *adap, int idx, u32 addr, + __be32 *data, u64 *parity); int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, @@ -396,6 +414,9 @@ int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, int t4_mem_win_read(struct adapter *adap, u32 addr, __be32 *data); void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); +void t4_get_port_stats_offset(struct adapter *adap, int idx, + struct port_stats *stats, + struct port_stats *offset); void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); void t4_clr_port_stats(struct adapter *adap, int idx); @@ -436,10 +457,15 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, enum dev_master master, enum dev_state *state); -int t4_fw_initialize(struct adapter *adap, unsigned int mbox); int t4_fw_bye(struct adapter *adap, unsigned int mbox); int t4_early_init(struct adapter *adap, unsigned int mbox); int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); +int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); +int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); +int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, + const u8 *fw_data, unsigned int size, int force); +int t4_fw_initialize(struct adapter *adap, unsigned int mbox); + int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int vf, unsigned int nparams, const u32 *params, u32 *val); int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, @@ -450,6 +476,10 @@ int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, unsigned int rxqi, unsigned int rxq, unsigned int tc, unsigned int vi, unsigned int cmask, unsigned int pmask, unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); +int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, + unsigned int port, unsigned int pf, unsigned int vf, + unsigned int nmac, u8 *mac, unsigned int *rss_size, + unsigned int portfunc, unsigned int idstype); int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, unsigned int *rss_size); @@ -490,7 +520,6 @@ int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, u32 *data); int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); - /* common.c */ int is_offload(const struct adapter *adap); unsigned int core_ticks_per_usec(const struct adapter *adap); @@ -509,4 +538,7 @@ int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, int polarity, int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, int polarity, int attempts, int delay, u32 *valp); +int is_t4(enum chip_type chip); +int is_t5(enum chip_type chip); +int is_fpga(enum chip_type chip); #endif /* __CXGBE_COMMON_H */ diff --git a/usr/src/uts/common/io/cxgbe/common/t4_chip_type.h b/usr/src/uts/common/io/cxgbe/common/t4_chip_type.h new file mode 100644 index 0000000000..790da74e91 --- /dev/null +++ b/usr/src/uts/common/io/cxgbe/common/t4_chip_type.h @@ -0,0 +1,93 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * This file is part of the Chelsio T4/T5 Ethernet driver. + * + * Copyright (C) 2003-2016 Chelsio Communications. All rights reserved. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this + * release for licensing terms and conditions. + */ +#ifndef __T4_CHIP_TYPE_H__ +#define __T4_CHIP_TYPE_H__ + +/* + * All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where: + * + * V = "4" for T4; "5" for T5, etc. or + * = "a" for T4 FPGA; "b" for T4 FPGA, etc. + * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs + * PP = adapter product designation + * + * We use the "version" (V) of the adpater to code the Chip Version above + * but separate out the FPGA as a separate boolean as per above. + */ +#define CHELSIO_PCI_ID_VER(__DeviceID) ((__DeviceID) >> 12) +#define CHELSIO_PCI_ID_FUNC(__DeviceID) (((__DeviceID) >> 8) & 0xf) +#define CHELSIO_PCI_ID_PROD(__DeviceID) ((__DeviceID) & 0xff) + +#define CHELSIO_T4 0x4 +#define CHELSIO_T4_FPGA 0xa +#define CHELSIO_T5 0x5 +#define CHELSIO_T5_FPGA 0xb + +/* + * Translate a PCI Device ID to a base Chelsio Chip Version -- CHELSIO_T4, + * CHELSIO_T5, etc. If it weren't for the screwed up numbering of the FPGAs + * we could do this simply as DeviceID >> 12 (because we know the real + * encoding oc CHELSIO_Tx identifiers). However, the FPGAs _do_ have weird + * Device IDs so we need to do this translation here. Note that only constant + * arithmetic and comparisons can be done here since this is being used to + * initialize static tables, etc. + * + * Finally: This will of course need to be expanded as future chips are + * developed. + */ +#define CHELSIO_PCI_ID_CHIP_VERSION(__DeviceID) \ + (CHELSIO_PCI_ID_VER(__DeviceID) == CHELSIO_T4 || \ + CHELSIO_PCI_ID_VER(__DeviceID) == CHELSIO_T4_FPGA \ + ? CHELSIO_T4 \ + : CHELSIO_T5) + +/* + * Internally we code the Chelsio T4 Family "Chip Code" as a tuple: + * + * (Is FPGA, Chip Version, Chip Revision) + * + * where: + * + * Is FPGA: is 0/1 indicating whether we're working with an FPGA + * Chip Version: is T4, T5, etc. + * Chip Revision: is the FAB "spin" of the Chip Version. + */ +#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision)) +#define CHELSIO_CHIP_FPGA 0x100 +#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf) +#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf) + +enum chip_type { + T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 0), + T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1), + T4_A3 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2), + T4_FIRST_REV = T4_A1, + T4_LAST_REV = T4_A3, + + T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0), + T5_FIRST_REV = T5_A1, + T5_LAST_REV = T5_A1, +}; + + +#endif /* __T4_CHIP_TYPE_H__ */ + diff --git a/usr/src/uts/common/io/cxgbe/common/t4_hw.c b/usr/src/uts/common/io/cxgbe/common/t4_hw.c index 2399b1eea6..e4182ace29 100644 --- a/usr/src/uts/common/io/cxgbe/common/t4_hw.c +++ b/usr/src/uts/common/io/cxgbe/common/t4_hw.c @@ -43,7 +43,7 @@ */ int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, - int polarity, int attempts, int d, u32 *valp) + int polarity, int attempts, int delay, u32 *valp) { int rc = 0; @@ -60,8 +60,8 @@ t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, rc = -EAGAIN; goto done; } - if (d != 0) - udelay(d); + if (delay != 0) + udelay(delay); } done: @@ -135,6 +135,34 @@ t4_write_indirect(struct adapter *adap, unsigned int addr_reg, } /* + * t4_report_fw_error - report firmware error + * @adap: the adapter + * + * The adapter firmware can indicate error conditions to the host. + * This routine prints out the reason for the firmware error (as + * reported by the firmware). + */ +static void t4_report_fw_error(struct adapter *adap) +{ + static const char *reason[] = { + "Crash", /* PCIE_FW_EVAL_CRASH */ + "During Device Preparation", /* PCIE_FW_EVAL_PREP */ + "During Device Configuration", /* PCIE_FW_EVAL_CONF */ + "During Device Initialization", /* PCIE_FW_EVAL_INIT */ + "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ + "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ + "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ + "Reserved", /* reserved */ + }; + u32 pcie_fw; + + pcie_fw = t4_read_reg(adap, A_PCIE_FW); + if (pcie_fw & F_PCIE_FW_ERR) + CH_ERR(adap, "Firmware reports adapter error: %s\n", + reason[G_PCIE_FW_EVAL(pcie_fw)]); +} + +/* * Get the reply to a mailbox command and store it in @rpl in big-endian order. */ static void @@ -153,7 +181,7 @@ fw_asrt(struct adapter *adap, u32 mbox_addr) struct fw_debug_cmd asrt; get_mbox_rpl(adap, (__be64 *)&asrt, sizeof (asrt) / 8, mbox_addr); - CH_ALERT(adap, "FW assertion at %.16s:%u, val0 %x, val1 %x", + CH_ALERT(adap, "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line), ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y)); } @@ -191,7 +219,7 @@ t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, * off to larger delays to a maximum retry delay. */ static const int d[] = { - 1, 1, 3, 5, 10, 10, 20, 50, 100, 200 + 1, 1, 3, 5, 10, 10, 20, 50, 100 }; u32 v; @@ -251,14 +279,22 @@ t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, } } - CH_ERR(adap, "command %x in mailbox %d timed out", + /* + * We timed out waiting for a reply to our mailbox command. Report + * the error and also check to see if the firmware reported any + * errors ... + */ + CH_ERR(adap, "command %#x in mailbox %d timed out\n", *(const u8 *)cmd, mbox); + if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) + t4_report_fw_error(adap); return (-ETIMEDOUT); } /* * t4_mc_read - read from MC through backdoor accesses * @adap: the adapter + * @idx: which MC to access * @addr: address of first byte requested * @data: 64 bytes of data containing the requested address * @ecc: where to store the corresponding 64-bit ECC word @@ -268,25 +304,43 @@ t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, * is assigned the 64-bit ECC word for the read data. */ int -t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc) +t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) { int i; - if (t4_read_reg(adap, A_MC_BIST_CMD) & F_START_BIST) + u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; + u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; + + if (is_t4(adap->params.chip)) { + mc_bist_cmd_reg = A_MC_BIST_CMD; + mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; + mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; + mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; + mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; + } else { + mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); + mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); + mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); + mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, + idx); + mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, + idx); + } + + if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) return (-EBUSY); - t4_write_reg(adap, A_MC_BIST_CMD_ADDR, addr & ~0x3fU); - t4_write_reg(adap, A_MC_BIST_CMD_LEN, 64); - t4_write_reg(adap, A_MC_BIST_DATA_PATTERN, 0xc); - t4_write_reg(adap, A_MC_BIST_CMD, V_BIST_OPCODE(1) | F_START_BIST | - V_BIST_CMD_GAP(1)); - i = t4_wait_op_done(adap, A_MC_BIST_CMD, F_START_BIST, 0, 10, 1); + t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); + t4_write_reg(adap, mc_bist_cmd_len_reg, 64); + t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); + t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | + F_START_BIST | V_BIST_CMD_GAP(1)); + i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); if (i != 0) return (i); -#define MC_DATA(i) MC_BIST_STATUS_REG(A_MC_BIST_STATUS_RDATA, i) - +#define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) for (i = 15; i >= 0; i--) - *data++ = htonl(t4_read_reg(adap, MC_DATA(i))); + *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); if (ecc != NULL) *ecc = t4_read_reg64(adap, MC_DATA(16)); #undef MC_DATA @@ -310,22 +364,49 @@ t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) { int i; - idx *= EDC_STRIDE; - if (t4_read_reg(adap, A_EDC_BIST_CMD + idx) & F_START_BIST) + u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; + u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; + + if (is_t4(adap->params.chip)) { + edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); + edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); + edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); + edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, + idx); + edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, + idx); + } else { +/* + * These macro are missing in t4_regs.h file. + * Added temporarily for testing. + */ +#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) +#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) + edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); + edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); + edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); + edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, + idx); + edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, + idx); +#undef EDC_REG_T5 +#undef EDC_STRIDE_T5 + } + + if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) return (-EBUSY); - t4_write_reg(adap, A_EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU); - t4_write_reg(adap, A_EDC_BIST_CMD_LEN + idx, 64); - t4_write_reg(adap, A_EDC_BIST_DATA_PATTERN + idx, 0xc); - t4_write_reg(adap, A_EDC_BIST_CMD + idx, + t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); + t4_write_reg(adap, edc_bist_cmd_len_reg, 64); + t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); + t4_write_reg(adap, edc_bist_cmd_reg, V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); - i = t4_wait_op_done(adap, A_EDC_BIST_CMD + idx, F_START_BIST, 0, 10, 1); + i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); if (i != 0) return (i); -#define EDC_DATA(i) (EDC_BIST_STATUS_REG(A_EDC_BIST_STATUS_RDATA, i) + idx) - +#define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) for (i = 15; i >= 0; i--) - *data++ = htonl(t4_read_reg(adap, EDC_DATA(i))); + *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); if (ecc != NULL) *ecc = t4_read_reg64(adap, EDC_DATA(16)); #undef EDC_DATA @@ -374,8 +455,8 @@ t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, __be32 *buf) /* * Read the chip's memory block and bail if there's an error. */ - if (mtype == MEM_MC) - ret = t4_mc_read(adap, pos, data, NULL); + if ((mtype == MEM_MC) || (mtype == MEM_MC1)) + ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); else ret = t4_edc_read(adap, mtype, pos, data, NULL); if (ret != 0) @@ -457,8 +538,9 @@ struct t4_vpd_hdr { #define EEPROM_STAT_ADDR 0x7bfc #define VPD_BASE 0x400 #define VPD_BASE_OLD 0 -#define VPD_LEN 512 +#define VPD_LEN 1024 #define VPD_INFO_FLD_HDR_SIZE 3 +#define CHELSIO_VPD_UNIQUE_ID 0x82 /* * t4_seeprom_read - read a serial EEPROM location @@ -487,7 +569,7 @@ t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) } while (!(val & PCI_VPD_ADDR_F) && --attempts); if (!(val & PCI_VPD_ADDR_F)) { - CH_ERR(adapter, "reading EEPROM address 0x%x failed", addr); + CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr); return (-EIO); } t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); @@ -525,7 +607,7 @@ t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) } while ((val & PCI_VPD_ADDR_F) && --attempts); if (val & PCI_VPD_ADDR_F) { - CH_ERR(adapter, "write to EEPROM address %x failed", addr); + CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr); return (-EIO); } return (0); @@ -574,114 +656,6 @@ t4_seeprom_wp(struct adapter *adapter, int enable) return (t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0)); } -/* - * get_vpd_keyword_val - Locates an information field keyword in the VPD - * @v: Pointer to buffered vpd data structure - * @kw: The keyword to search for - * - * Returns the value of the information field keyword or - * -ENOENT otherwise. - */ -static int -get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw) -{ - int i; - unsigned int offset, len; - const u8 *buf = &v->id_tag; - const u8 *vpdr_len = &v->vpdr_tag; - offset = sizeof (struct t4_vpd_hdr); - len = (u16)vpdr_len[1] + ((u16)vpdr_len[2] << 8); - - if (len + sizeof (struct t4_vpd_hdr) > VPD_LEN) { - return (-ENOENT); - } - - for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len; ) { - - if (memcmp(buf + i, kw, 2) == 0) { - i += VPD_INFO_FLD_HDR_SIZE; - return (i); - } - - i += VPD_INFO_FLD_HDR_SIZE + buf[i+2]; - } - - return (-ENOENT); -} - -/* - * get_vpd_params - read VPD parameters from VPD EEPROM - * @adapter: adapter to read - * @p: where to store the parameters - * - * Reads card parameters stored in VPD EEPROM. - */ -static int -get_vpd_params(struct adapter *adapter, struct vpd_params *p) -{ - int i, ret, addr; - int ec, sn, pn, na; - u8 vpd[VPD_LEN], csum; - const struct t4_vpd_hdr *v; - - /* - * Card information normally starts at VPD_BASE but early cards had - * it at 0. - */ - /* LINTED: E_BAD_PTR_CAST_ALIGN */ - ret = t4_seeprom_read(adapter, VPD_BASE, (u32 *)(vpd)); - addr = *vpd == 0x82 ? VPD_BASE : VPD_BASE_OLD; - - for (i = 0; i < sizeof (vpd); i += 4) { - /* LINTED: E_BAD_PTR_CAST_ALIGN */ - ret = t4_seeprom_read(adapter, addr + i, (u32 *)(vpd + i)); - if (ret != 0) - return (ret); - } - v = (const struct t4_vpd_hdr *)vpd; - -#define FIND_VPD_KW(var, name) do { \ - var = get_vpd_keyword_val(v, name); \ - if (var < 0) { \ - CH_ERR(adapter, "missing VPD keyword " name); \ - return (-EINVAL); \ - } \ -} while (0) - - /* LINTED: E_CONSTANT_CONDITION */ - FIND_VPD_KW(i, "RV"); - for (csum = 0; i >= 0; i--) - csum += vpd[i]; - - if (csum != 0) { - CH_ERR(adapter, "corrupted VPD EEPROM, actual csum %u", csum); - return (-EINVAL); - } - /* LINTED: E_CONSTANT_CONDITION */ - FIND_VPD_KW(ec, "EC"); - /* LINTED: E_CONSTANT_CONDITION */ - FIND_VPD_KW(sn, "SN"); - /* LINTED: E_CONSTANT_CONDITION */ - FIND_VPD_KW(pn, "PN"); - /* LINTED: E_CONSTANT_CONDITION */ - FIND_VPD_KW(na, "NA"); -#undef FIND_VPD_KW - - (void) memcpy(p->id, v->id_data, ID_LEN); - (void) strstrip(p->id); - (void) memcpy(p->ec, vpd + ec, EC_LEN); - (void) strstrip(p->ec); - i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; - (void) memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); - (void) strstrip(p->sn); - (void) memcpy(p->pn, vpd + pn, min(i, PN_LEN)); - (void) strstrip(p->pn); - (void) memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); - (void) strstrip(p->na); - - return (0); -} - /* serial flash and firmware constants and flash config file constants */ enum { SF_ATTEMPTS = 10, /* max retries for SF operations */ @@ -833,13 +807,16 @@ t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, * @addr: the start address to write * @n: length of data to write in bytes * @data: the data to write + * @byte_oriented: whether to store data as bytes or as words * * Writes up to a page of data (256 bytes) to the serial flash starting * at the given address. All the data must be written to the same page. + * If @byte_oriented is set the write data is stored as byte stream + * (i.e. matches what on disk), otherwise in big-endian. */ static int t4_write_flash(struct adapter *adapter, unsigned int addr, unsigned int n, - const u8 *data) + const u8 *data, int byte_oriented) { int ret; u32 buf[SF_PAGE_SIZE / 4]; @@ -859,6 +836,9 @@ t4_write_flash(struct adapter *adapter, unsigned int addr, unsigned int n, for (val = 0, i = 0; i < c; ++i) val = (val << 8) + *data++; + if (!byte_oriented) + val = htonl(val); + ret = sf1_write(adapter, c, c != left, 1, val); if (ret != 0) goto unlock; @@ -870,13 +850,14 @@ t4_write_flash(struct adapter *adapter, unsigned int addr, unsigned int n, t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ /* Read the page to verify the write succeeded */ - ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); + ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, + byte_oriented); if (ret != 0) return (ret); if (memcmp(data - n, (u8 *)buf + offset, n)) { CH_ERR(adapter, "failed to correctly write the flash page " - "at %x", addr); + "at %#x\n", addr); return (-EIO); } return (0); @@ -926,32 +907,44 @@ t4_get_tp_version(struct adapter *adapter, u32 *vers) int t4_check_fw_version(struct adapter *adapter) { - u32 api_vers[2]; int ret, major, minor, micro; + int exp_major, exp_minor, exp_micro; ret = t4_get_fw_version(adapter, &adapter->params.fw_vers); if (!ret) ret = t4_get_tp_version(adapter, &adapter->params.tp_vers); - if (!ret) - ret = t4_read_flash(adapter, - FLASH_FW_START + offsetof(struct fw_hdr, intfver_nic), 2, - api_vers, 1); + if (ret != 0) return (ret); major = G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers); minor = G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers); micro = G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers); - (void) memcpy(adapter->params.api_vers, api_vers, - sizeof (adapter->params.api_vers)); - if (major != T4FW_VERSION_MAJOR) { /* major mismatch - fail */ - CH_ERR(adapter, "card FW has major version %u, driver wants %u", - major, T4FW_VERSION_MAJOR); + switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { + case CHELSIO_T4: + exp_major = T4FW_VERSION_MAJOR; + exp_minor = T4FW_VERSION_MINOR; + exp_micro = T4FW_VERSION_MICRO; + break; + case CHELSIO_T5: + exp_major = T5FW_VERSION_MAJOR; + exp_minor = T5FW_VERSION_MINOR; + exp_micro = T5FW_VERSION_MICRO; + break; + default: + CH_ERR(adapter, "Unsupported chip type, %x\n", + adapter->params.chip); return (-EINVAL); } - if (minor == T4FW_VERSION_MINOR && micro == T4FW_VERSION_MICRO) + if (major != exp_major) { /* major mismatch - fail */ + CH_ERR(adapter, "card FW has major version %u, driver wants " + "%u\n", major, exp_major); + return -EINVAL; + } + + if (minor == exp_minor && micro == exp_micro) return (0); /* perfect match */ /* Minor/micro version mismatch. Report it but often it's OK. */ @@ -977,7 +970,7 @@ t4_flash_erase_sectors(struct adapter *adapter, int start, int end) SF_ERASE_SECTOR | (start << 8))) != 0 || (ret = flash_wait_op(adapter, 14, 500)) != 0) { CH_ERR(adapter, "erase of flash sector %d failed, " - "error %d", start, ret); + "error %d\n", start, ret); break; } start++; @@ -991,15 +984,20 @@ t4_flash_erase_sectors(struct adapter *adapter, int start, int end) * @adapter: the adapter * * Return the address within the flash where the Firmware Configuration - * File is stored. + * File is stored, or an error if the device FLASH is too small to contain + * a Firmware Configuration File. */ -unsigned int +int t4_flash_cfg_addr(struct adapter *adapter) { - if (adapter->params.sf_size == 0x100000) - return (FLASH_FPGA_CFG_START); - else - return (FLASH_CFG_START); + /* + * If the device FLASH isn't large enough to hold a Firmware + * Configuration File, return an error. + */ + if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) + return -ENOSPC; + + return FLASH_CFG_START; } /* @@ -1013,21 +1011,20 @@ t4_flash_cfg_addr(struct adapter *adapter) int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) { - int ret, i, n; + int ret, i, n, cfg_addr; unsigned int addr; unsigned int flash_cfg_start_sec; unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; - addr = t4_flash_cfg_addr(adap); - flash_cfg_start_sec = addr / SF_SEC_SIZE; + cfg_addr = t4_flash_cfg_addr(adap); + if (cfg_addr < 0) + return cfg_addr; - if (!size) { - CH_ERR(adap, "cfg file has no data"); - return (-EINVAL); - } + addr = cfg_addr; + flash_cfg_start_sec = addr / SF_SEC_SIZE; if (size > FLASH_CFG_MAX_SIZE) { - CH_ERR(adap, "cfg file too large, max is %u bytes", + CH_ERR(adap, "cfg file too large, max is %u bytes\n", FLASH_CFG_MAX_SIZE); return (-EFBIG); } @@ -1036,16 +1033,20 @@ t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) sf_sec_size); ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, flash_cfg_start_sec + i - 1); - if (ret != 0) + /* + * If size == 0 then we're simply erasing the FLASH sectors associated + * with the on-adapter Firmware Configuration File. + */ + if (ret || size == 0) goto out; /* this will write to the flash up to SF_PAGE_SIZE at a time */ - for (i = 0; i < size; i += SF_PAGE_SIZE) { - if ((size - i) < SF_PAGE_SIZE) + for (i = 0; i< size; i+= SF_PAGE_SIZE) { + if ( (size - i) < SF_PAGE_SIZE) n = size - i; else n = SF_PAGE_SIZE; - ret = t4_write_flash(adap, addr, n, cfg_data); + ret = t4_write_flash(adap, addr, n, cfg_data, 1); if (ret != 0) goto out; @@ -1055,7 +1056,8 @@ t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) out: if (ret != 0) - CH_ERR(adap, "config file download failed %d", ret); + CH_ERR(adap, "config file %s failed %d\n", + (size == 0 ? "clear" : "download"), ret); return (ret); } @@ -1080,36 +1082,56 @@ t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; + unsigned int fw_start_sec; + unsigned int fw_start; + unsigned int fw_size; + + if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { + fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; + fw_start = FLASH_FWBOOTSTRAP_START; + fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; + } else { + fw_start_sec = FLASH_FW_START_SEC; + fw_start = FLASH_FW_START; + fw_size = FLASH_FW_MAX_SIZE; + } + if (!size) { - CH_ERR(adap, "FW image has no data"); + CH_ERR(adap, "FW image has no data\n"); return (-EINVAL); } if (size & 511) { - CH_ERR(adap, "FW image size not multiple of 512 bytes"); + CH_ERR(adap, "FW image size not multiple of 512 bytes\n"); return (-EINVAL); } if (ntohs(hdr->len512) * 512 != size) { - CH_ERR(adap, "FW image size differs from size in FW header"); + CH_ERR(adap, "FW image size differs from size in FW header\n"); return (-EINVAL); } - if (size > FLASH_FW_MAX_SIZE) { - CH_ERR(adap, "FW image too large, max is %u bytes\n", - FLASH_FW_MAX_SIZE); + if (size > fw_size) { + CH_ERR(adap, "FW image too large, max is %u bytes\n", fw_size); return (-EFBIG); } - + if ((is_t4(adap->params.chip) && hdr->chip != FW_HDR_CHIP_T4) || + (is_t5(adap->params.chip) && hdr->chip != FW_HDR_CHIP_T5)) { + CH_ERR(adap, + "FW image (%d) is not suitable for this adapter (%d)\n", + hdr->chip, adap->params.chip); + return -EINVAL; + } + for (csum = 0, i = 0; i < size / sizeof (csum); i++) csum += ntohl(p[i]); if (csum != 0xffffffff) { - CH_ERR(adap, "corrupted firmware image, checksum %x", + CH_ERR(adap, "corrupted firmware image, checksum %x\n", csum); return (-EINVAL); } i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ - ret = t4_flash_erase_sectors(adap, FLASH_FW_START_SEC, - FLASH_FW_START_SEC + i - 1); + ret = t4_flash_erase_sectors(adap, fw_start_sec, + fw_start_sec + i - 1); if (ret != 0) goto out; @@ -1121,25 +1143,24 @@ t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) (void) memcpy(first_page, fw_data, SF_PAGE_SIZE); /* LINTED: E_BAD_PTR_CAST_ALIGN */ ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff); - ret = t4_write_flash(adap, FLASH_FW_START, SF_PAGE_SIZE, first_page); + ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); if (ret != 0) goto out; - addr = FLASH_FW_START; + addr = fw_start; for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { addr += SF_PAGE_SIZE; fw_data += SF_PAGE_SIZE; - ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); + ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); if (ret != 0) goto out; } - ret = t4_write_flash(adap, - FLASH_FW_START + offsetof(struct fw_hdr, fw_ver), - sizeof (hdr->fw_ver), (const u8 *)&hdr->fw_ver); + ret = t4_write_flash(adap, fw_start + offsetof(struct fw_hdr, fw_ver), + sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); out: if (ret != 0) - CH_ERR(adap, "firmware download failed, error %d", ret); + CH_ERR(adap, "firmware download failed, error %d\n", ret); return (ret); } @@ -1157,6 +1178,7 @@ void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) { unsigned int i, v; + int cim_num_obq = is_t4(adap->params.chip) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5; for (i = 0; i < CIM_NUM_IBQ; i++) { t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | @@ -1166,7 +1188,7 @@ t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) *size++ = G_CIMQSIZE(v) * 256; /* value is in 256-byte units */ *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ } - for (i = 0; i < CIM_NUM_OBQ; i++) { + for (i = 0; i < cim_num_obq; i++) { t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | V_QUENUMSELECT(i)); v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); @@ -1193,7 +1215,9 @@ t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) unsigned int addr; const unsigned int nwords = CIM_IBQ_SIZE * 4; - if (qid > 5 || (n & 3)) + int cim_num_obq = is_t4(adap->params.chip) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5; + + if (qid >= cim_num_obq || (n & 3)) return (-EINVAL); addr = qid * nwords; @@ -1203,8 +1227,12 @@ t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) for (i = 0; i < n; i++, addr++) { t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | F_IBQDBGEN); + /* + * It might take 3-10ms before the IBQ debug read access is + * allowed. Wait for 1 Sec with a delay of 1 usec. + */ err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, - 2, 1); + 1000000, 1); if (err != 0) return (err); *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); @@ -1522,8 +1550,8 @@ t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) } #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ - FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG) - + FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \ + FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG) /* * t4_link_start - apply link configuration to MAC/PHY * @phy: the PHY to setup @@ -1623,10 +1651,10 @@ t4_handle_intr_status(struct adapter *adapter, unsigned int reg, continue; if (acts->fatal != 0) { fatal++; - CH_ALERT(adapter, "%s (0x%x)", + CH_ALERT(adapter, "%s (0x%x)\n", acts->msg, status & acts->mask); } else if (acts->msg != NULL) - CH_WARN_RATELIMIT(adapter, "%s (0x%x)", + CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg, status & acts->mask); mask |= acts->mask; } @@ -1697,13 +1725,56 @@ pcie_intr_handler(struct adapter *adapter) { 0 } }; + static struct intr_info t5_pcie_intr_info[] = { + { F_MSTGRPPERR, "Master Response Read Queue parity error", + -1, 1 }, + { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, + { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, + { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, + { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, + { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, + { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, + { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", + -1, 1 }, + { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", + -1, 1 }, + { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, + { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, + { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, + { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, + { F_DREQWRPERR, "PCI DMA channel write request parity error", + -1, 1 }, + { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, + { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, + { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, + { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, + { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, + { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, + { F_FIDPERR, "PCI FID parity error", -1, 1 }, + { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 }, + { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, + { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, + { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error", + -1, 1 }, + { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error", + -1, 1 }, + { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, + { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, + { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, + { F_READRSPERR, "Outbound read error", -1, + 0 }, + { 0 } + }; + int fat; fat = t4_handle_intr_status(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, sysbus_intr_info) + t4_handle_intr_status(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, pcie_port_intr_info) + - t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, pcie_intr_info); + t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, + is_t4(adapter->params.chip) ? + pcie_intr_info : t5_pcie_intr_info); if (fat != 0) t4_fatal_err(adapter); } @@ -1762,7 +1833,7 @@ sge_intr_handler(struct adapter *adapter) v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) | ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32); if (v != 0) { - CH_ALERT(adapter, "SGE parity error (%llx)", + CH_ALERT(adapter, "SGE parity error (%llx)\n", (unsigned long long)v); t4_write_reg(adapter, A_SGE_INT_CAUSE1, v); t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32); @@ -1772,8 +1843,11 @@ sge_intr_handler(struct adapter *adapter) err = t4_read_reg(adapter, A_SGE_ERROR_STATS); if (err & F_ERROR_QID_VALID) { - CH_ERR(adapter, "SGE error for queue %u", G_ERROR_QID(err)); - t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID); + CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err)); + if (err & F_UNCAPTURED_ERROR) + CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n"); + t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID | + F_UNCAPTURED_ERROR); } if (v != 0) @@ -1835,6 +1909,9 @@ cim_intr_handler(struct adapter *adapter) int fat; + if (t4_read_reg(adapter, A_PCIE_FW) & F_PCIE_FW_ERR) + t4_report_fw_error(adapter); + fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, cim_intr_info) + t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE, @@ -2059,23 +2136,28 @@ mem_intr_handler(struct adapter *adapter, int idx) addr = EDC_REG(A_EDC_INT_CAUSE, idx); cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx); } else { - addr = A_MC_INT_CAUSE; - cnt_addr = A_MC_ECC_STATUS; + if (is_t4(adapter->params.chip)) { + addr = A_MC_INT_CAUSE; + cnt_addr = A_MC_ECC_STATUS; + } else { + addr = A_MC_P_INT_CAUSE; + cnt_addr = A_MC_P_ECC_STATUS; + } } v = t4_read_reg(adapter, addr) & MEM_INT_MASK; if (v & F_PERR_INT_CAUSE) - CH_ALERT(adapter, "%s FIFO parity error", name[idx]); + CH_ALERT(adapter, "%s FIFO parity error\n", name[idx]); if (v & F_ECC_CE_INT_CAUSE) { u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr)); t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT)); CH_WARN_RATELIMIT(adapter, - "%u %s correctable ECC data error%s", cnt, name[idx], + "%u %s correctable ECC data error%s\n", cnt, name[idx], cnt > 1 ? "s" : ""); } if (v & F_ECC_UE_INT_CAUSE) - CH_ALERT(adapter, "%s uncorrectable ECC data error", + CH_ALERT(adapter, "%s uncorrectable ECC data error\n", name[idx]); t4_write_reg(adapter, addr, v); @@ -2092,12 +2174,12 @@ ma_intr_handler(struct adapter *adapter) u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE); if (status & F_MEM_PERR_INT_CAUSE) - CH_ALERT(adapter, "MA parity error, parity status %x", + CH_ALERT(adapter, "MA parity error, parity status %x\n", t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS)); if (status & F_MEM_WRAP_INT_CAUSE) { v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS); CH_ALERT(adapter, "MA address wrap-around error by client %u to" - " address %x", G_MEM_WRAP_CLIENT_NUM(v), + " address %x\n", G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4); } t4_write_reg(adapter, A_MA_INT_CAUSE, status); @@ -2145,17 +2227,24 @@ ncsi_intr_handler(struct adapter *adap) static void xgmac_intr_handler(struct adapter *adap, int port) { - u32 v = t4_read_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE)); + u32 v, int_cause_reg; + + if (is_t4(adap->params.chip)) + int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); + else + int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); - v &= F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; + v = t4_read_reg(adap, int_cause_reg); + v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR); + if (!v) return; if (v & F_TXFIFO_PRTY_ERR) - CH_ALERT(adap, "XGMAC %d Tx FIFO parity error", port); + CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", port); if (v & F_RXFIFO_PRTY_ERR) - CH_ALERT(adap, "XGMAC %d Rx FIFO parity error", port); - t4_write_reg(adap, PORT_REG(port, A_XGMAC_PORT_INT_CAUSE), v); + CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", port); + t4_write_reg(adap, int_cause_reg, v); t4_fatal_err(adap); } @@ -2166,12 +2255,19 @@ static void pl_intr_handler(struct adapter *adap) { static struct intr_info pl_intr_info[] = { - { F_FATALPERR, "T4 fatal parity error", -1, 1 }, + { F_FATALPERR, "Fatal parity error", -1, 1 }, { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 }, { 0 } }; - if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, pl_intr_info) != 0) + static struct intr_info t5_pl_intr_info[] = { + { F_PL_BUSPERR, "PL bus parity error", -1, 1 }, + { F_FATALPERR, "Fatal parity error", -1, 1 }, + { 0 } + }; + + if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, + is_t4(adap->params.chip) ? pl_intr_info : t5_pl_intr_info)) t4_fatal_err(adap); } @@ -2306,7 +2402,6 @@ t4_intr_clear(struct adapter *adapter) A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE, - A_MC_INT_CAUSE, A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS, A_MA_INT_CAUSE, A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1), A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE, @@ -2326,6 +2421,10 @@ t4_intr_clear(struct adapter *adapter) for (i = 0; i < ARRAY_SIZE(cause_reg); ++i) t4_write_reg(adapter, cause_reg[i], 0xffffffff); + + t4_write_reg(adapter, is_t4(adapter->params.chip) ? A_MC_INT_CAUSE : + A_MC_P_INT_CAUSE, 0xffffffff); + t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK); (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ } @@ -2388,6 +2487,7 @@ t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, */ while (n > 0) { int nq = min(n, 32); + int nq_packed = 0; __be32 *qp = &cmd.iq0_to_iq2; /* @@ -2409,25 +2509,28 @@ t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, * Ingress Queue ID array and insert them into the command. */ while (nq > 0) { - unsigned int v; /* * Grab up to the next 3 Ingress Queue IDs (wrapping * around the Ingress Queue ID array if necessary) and * insert them into the firmware RSS command at the * current 3-tuple position within the commad. */ - v = V_FW_RSS_IND_TBL_CMD_IQ0(*rsp); - if (++rsp >= rsp_end) - rsp = rspq; - v |= V_FW_RSS_IND_TBL_CMD_IQ1(*rsp); - if (++rsp >= rsp_end) - rsp = rspq; - v |= V_FW_RSS_IND_TBL_CMD_IQ2(*rsp); - if (++rsp >= rsp_end) - rsp = rspq; - - *qp++ = htonl(v); - nq -= 3; + u16 qbuf[3]; + u16 *qbp = qbuf; + int nqbuf = min(3, nq); + + nq -= nqbuf; + qbuf[0] = qbuf[1] = qbuf[2] = 0; + while (nqbuf && nq_packed < 32) { + nqbuf--; + nq_packed++; + *qbp++ = *rsp++; + if (rsp >= rsp_end) + rsp = rspq; + } + *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | + V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | + V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); } /* @@ -2840,8 +2943,6 @@ t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st) { t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->req, 8, A_TP_MIB_CPL_IN_REQ_0); - t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->tx_err, - 4, A_TP_MIB_CPL_OUT_ERR_0); } /* @@ -3285,49 +3386,47 @@ t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, { int i, ofst = idx * 4; u32 data_reg, mask_reg, cfg; - u32 multitrc = F_TRCMULTIFILTER; if (!enable) { t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 0); - goto out; + return 0; } - if (tp->port > 11 || tp->invert > 1 || tp->skip_len > M_TFLENGTH || - tp->skip_ofst > M_TFOFFSET || tp->min_len > M_TFMINPKTSIZE || - tp->snap_len > 9600 || (idx && tp->snap_len > 256)) - return (-EINVAL); - - if (tp->snap_len > 256) { /* must be tracer 0 */ - if ((t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + 4) | - t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + 8) | - t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + 12)) & - F_TFEN) - return (-EINVAL); /* other tracers are enabled */ - multitrc = 0; - } else if (idx != 0) { - i = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B); - if (G_TFCAPTUREMAX(i) > 256 && - (t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A) & F_TFEN)) - return (-EINVAL); + /* + * TODO - After T4 data book is updated, specify the exact + * section below. + * + * See T4 data book - MPS section for a complete description + * of the below if..else handling of A_MPS_TRC_CFG register + * value. + */ + cfg = t4_read_reg(adap, A_MPS_TRC_CFG); + if (cfg & F_TRCMULTIFILTER) { + /* + * If multiple tracers are enabled, then maximum + * capture size is 2.5KB (FIFO size of a single channel) + * minus 2 flits for CPL_TRACE_PKT header. + */ + if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) + return -EINVAL; + } + else { + /* + * If multiple tracers are disabled, to avoid deadlocks + * maximum packet capture size of 9600 bytes is recommended. + * Also in this mode, only trace0 can be enabled and running. + */ + if (tp->snap_len > 9600 || idx) + return -EINVAL; } + if (tp->port > 11 || tp->invert > 1 || tp->skip_len > M_TFLENGTH || + tp->skip_ofst > M_TFOFFSET || tp->min_len > M_TFMINPKTSIZE) + return -EINVAL; + /* stop the tracer we'll be changing */ t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 0); - /* disable tracing globally if running in the wrong single/multi mode */ - cfg = t4_read_reg(adap, A_MPS_TRC_CFG); - if ((cfg & F_TRCEN) && multitrc != (cfg & F_TRCMULTIFILTER)) { - t4_write_reg(adap, A_MPS_TRC_CFG, cfg ^ F_TRCEN); - (void) t4_read_reg(adap, A_MPS_TRC_CFG); /* flush */ - msleep(1); - if (!(t4_read_reg(adap, A_MPS_TRC_CFG) & F_TRCFIFOEMPTY)) - return (-ETIMEDOUT); - } - /* - * At this point either the tracing is enabled and in the right mode or - * disabled. - */ - idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); data_reg = A_MPS_TRC_FILTER0_MATCH + idx; mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; @@ -3340,11 +3439,11 @@ t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, V_TFCAPTUREMAX(tp->snap_len) | V_TFMINPKTSIZE(tp->min_len)); t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | - V_TFPORT(tp->port) | F_TFEN | V_TFINVERTMATCH(tp->invert)); + is_t4(adap->params.chip) ? + V_TFPORT(tp->port) | F_TFEN | V_TFINVERTMATCH(tp->invert) : + V_T5_TFPORT(tp->port) | F_T5_TFEN | + V_T5_TFINVERTMATCH(tp->invert)); - cfg &= ~F_TRCMULTIFILTER; - t4_write_reg(adap, A_MPS_TRC_CFG, cfg | F_TRCEN | multitrc); -out: (void) t4_read_reg(adap, A_MPS_TRC_CFG); /* flush */ return (0); } @@ -3368,13 +3467,18 @@ t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); - *enabled = !!(ctla & F_TFEN); + if (is_t4(adap->params.chip)) { + *enabled = !!(ctla & F_TFEN); + tp->port = G_TFPORT(ctla); + } else { + *enabled = !!(ctla & F_T5_TFEN); + tp->port = G_T5_TFPORT(ctla); + } tp->snap_len = G_TFCAPTUREMAX(ctlb); tp->min_len = G_TFMINPKTSIZE(ctlb); tp->skip_ofst = G_TFOFFSET(ctla); tp->skip_len = G_TFLENGTH(ctla); tp->invert = !!(ctla & F_TFINVERTMATCH); - tp->port = G_TFPORT(ctla); ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; @@ -3398,11 +3502,19 @@ void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) { int i; + u32 data[2]; for (i = 0; i < PM_NSTATS; i++) { t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); - cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); + if (is_t4(adap->params.chip)) + cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); + else { + t4_read_indirect(adap, A_PM_TX_DBG_CTRL, + A_PM_TX_DBG_DATA, data, 2, + A_PM_TX_DBG_STAT_MSB); + cycles[i] = (((u64)data[0] << 32) | data[1]); + } } } @@ -3418,11 +3530,19 @@ void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) { int i; + u32 data[2]; for (i = 0; i < PM_NSTATS; i++) { t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); - cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); + if (is_t4(adap->params.chip)) + cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); + else { + t4_read_indirect(adap, A_PM_RX_DBG_CTRL, + A_PM_RX_DBG_DATA, data, 2, + A_PM_RX_DBG_STAT_MSB); + cycles[i] = (((u64)data[0] << 32) | data[1]); + } } } @@ -3461,9 +3581,12 @@ t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) u32 bgmap = get_mps_bg_map(adap, idx); #define GET_STAT(name) \ - t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)) + t4_read_reg64(adap, \ + (is_t4(adap->params.chip) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ + T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) + p->tx_pause = GET_STAT(TX_PORT_PAUSE); p->tx_octets = GET_STAT(TX_PORT_BYTES); p->tx_frames = GET_STAT(TX_PORT_FRAMES); p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); @@ -3478,7 +3601,6 @@ t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); p->tx_drop = GET_STAT(TX_PORT_DROP); - p->tx_pause = GET_STAT(TX_PORT_PAUSE); p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); @@ -3488,6 +3610,7 @@ t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); + p->rx_pause = GET_STAT(RX_PORT_PAUSE); p->rx_octets = GET_STAT(RX_PORT_BYTES); p->rx_frames = GET_STAT(RX_PORT_FRAMES); p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); @@ -3506,7 +3629,6 @@ t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); - p->rx_pause = GET_STAT(RX_PORT_PAUSE); p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); @@ -3541,13 +3663,20 @@ t4_clr_port_stats(struct adapter *adap, int idx) { unsigned int i; u32 bgmap = get_mps_bg_map(adap, idx); + u32 port_base_addr; + + if (is_t4(adap->params.chip)) + port_base_addr = PORT_BASE(idx); + else + port_base_addr = T5_PORT_BASE(idx); + for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) - t4_write_reg(adap, PORT_REG(idx, i), 0); + t4_write_reg(adap, port_base_addr + i, 0); for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) - t4_write_reg(adap, PORT_REG(idx, i), 0); + t4_write_reg(adap, port_base_addr + i, 0); for (i = 0; i < 4; i++) if (bgmap & (1 << i)) { t4_write_reg(adap, @@ -3571,7 +3700,10 @@ t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) u32 bgmap = get_mps_bg_map(adap, idx); #define GET_STAT(name) \ - t4_read_reg64(adap, PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)) + t4_read_reg64(adap, \ + (is_t4(adap->params.chip) ? \ + PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ + T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) p->octets = GET_STAT(BYTES); @@ -3588,8 +3720,7 @@ t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) p->frames_512_1023 = GET_STAT(512B_1023B); p->frames_1024_1518 = GET_STAT(1024B_1518B); p->frames_1519_max = GET_STAT(1519B_MAX); - p->drop = t4_read_reg(adap, PORT_REG(idx, - A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES)); + p->drop = GET_STAT(DROP_FRAMES); p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; @@ -3646,16 +3777,24 @@ t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, u64 mask0, u64 mask1, unsigned int crc, bool enable) { int i; + u32 port_cfg_reg; + + if (is_t4(adap->params.chip)) + port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); + else + port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); if (!enable) { - t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), - F_PATEN, 0); + t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); return (0); } if (map > 0xff) return (-EINVAL); -#define EPIO_REG(name) PORT_REG(port, A_XGMAC_PORT_EPIO_##name) + +#define EPIO_REG(name) \ + (is_t4(adap->params.chip) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ + T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); t4_write_reg(adap, EPIO_REG(DATA2), mask1); @@ -3681,7 +3820,7 @@ t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, } #undef EPIO_REG - t4_set_reg_field(adap, PORT_REG(port, A_XGMAC_PORT_CFG2), 0, F_PATEN); + t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); return (0); } @@ -3843,14 +3982,14 @@ t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, } /* - * t4_fw_hello - establish communication with FW - * @adap: the adapter - * @mbox: mailbox to use for the FW command - * @evt_mbox: mailbox to receive async FW events - * @master: specifies the caller's willingness to be the device master - * @state: returns the current device state (if non-NULL) - * - * Issues a command to establish communication with FW. Returns either + * t4_fw_hello - establish communication with FW + * @adap: the adapter + * @mbox: mailbox to use for the FW command + * @evt_mbox: mailbox to receive async FW events + * @master: specifies the caller's willingness to be the device master + * @state: returns the current device state (if non-NULL) + + * Issues a command to establish communication with FW. Returns either * an error (negative integer) or the mailbox of the Master PF. */ int @@ -3879,12 +4018,16 @@ retry: /* * Issue the HELLO command to the firmware. If it's not successful * but indicates that we got a "busy" or "timeout" condition, retry - * the HELLO until we exhaust our retry limit. + * the HELLO until we exhaust our retry limit. If we do exceed our + * retry limit, check to see if the firmware left us any error + * information and report that if so ... */ ret = t4_wr_mbox(adap, mbox, &c, sizeof (c), &c); if (ret != FW_SUCCESS) { if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) goto retry; + if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) + t4_report_fw_error(adap); return (ret); } @@ -3929,7 +4072,7 @@ retry: /* * If neither Error nor Initialialized are indicated - * by the firmware keep waiting till we exaust our + * by the firmware keep waiting till we exhaust our * timeout ... and then retry if we haven't exhausted * our retries ... */ @@ -4216,8 +4359,8 @@ t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, V_FW_PARAMS_CMD_VFN(vf)); c.retval_len16 = htonl(FW_LEN16(c)); - for (i = 0; i < nparams; i++, p += 2) - *p = htonl(*params++); + for (i = 0; i < nparams; i++, p += 2, params++) + *p = htonl(*params); ret = t4_wr_mbox(adap, mbox, &c, sizeof (c), &c); if (ret == 0) @@ -4256,8 +4399,10 @@ t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, c.retval_len16 = htonl(FW_LEN16(c)); while (nparams--) { - *p++ = htonl(*params++); - *p++ = htonl(*val++); + *p++ = htonl(*params); + params++; + *p++ = htonl(*val); + val++; } return (t4_wr_mbox(adap, mbox, &c, sizeof (c), NULL)); @@ -4310,7 +4455,7 @@ t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, } /* - * t4_alloc_vi - allocate a virtual interface + * t4_alloc_vi_func - allocate a virtual interface * @adap: the adapter * @mbox: mailbox to use for the FW command * @port: physical port associated with the VI @@ -4327,9 +4472,10 @@ t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, * Returns a negative error number or the non-negative VI id. */ int -t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, - unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, - unsigned int *rss_size) +t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, + unsigned int port, unsigned int pf, unsigned int vf, + unsigned int nmac, u8 *mac, unsigned int *rss_size, + unsigned int portfunc, unsigned int idstype) { int ret; struct fw_vi_cmd c; @@ -4339,6 +4485,8 @@ t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); c.alloc_to_len16 = htonl(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); + c.type_to_viid = htons(V_FW_VI_CMD_TYPE(idstype) | + V_FW_VI_CMD_FUNC(portfunc)); c.portid_pkd = V_FW_VI_CMD_PORTID(port); c.nmac = nmac - 1; @@ -4363,11 +4511,35 @@ t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, } } if (rss_size != NULL) - *rss_size = G_FW_VI_CMD_RSSSIZE(ntohs(c.rsssize_pkd)); - return (G_FW_VI_CMD_VIID(ntohs(c.type_to_viid))); + *rss_size = G_FW_VI_CMD_RSSSIZE(ntohs(c.norss_rsssize)); + return G_FW_VI_CMD_VIID(htons(c.type_to_viid)); } /* + * t4_alloc_vi - allocate an [Ethernet Function] virtual interface + * @adap: the adapter + * @mbox: mailbox to use for the FW command + * @port: physical port associated with the VI + * @pf: the PF owning the VI + * @vf: the VF owning the VI + * @nmac: number of MAC addresses needed (1 to 5) + * @mac: the MAC addresses of the VI + * @rss_size: size of RSS table slice associated with this VI + * + * backwards compatible and convieniance routine to allocate a Virtual + * Interface with a Ethernet Port Application Function and Intrustion + * Detection System disabled. + */ +int +t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, + unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, + unsigned int *rss_size) +{ + return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, + FW_VI_FUNC_ETH, 0); + } + +/* * t4_free_vi - free a virtual interface * @adap: the adapter * @mbox: mailbox to use for the FW command @@ -4469,9 +4641,12 @@ t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, int offset, ret = 0; struct fw_vi_mac_cmd c; unsigned int nfilters = 0; + unsigned int max_naddr = is_t4(adap->params.chip) ? + NUM_MPS_CLS_SRAM_L_INSTANCES : + NUM_MPS_T5_CLS_SRAM_L_INSTANCES; unsigned int rem = naddr; - if (naddr > NUM_MPS_CLS_SRAM_L_INSTANCES) + if (naddr > max_naddr) return (-EINVAL); for (offset = 0; offset < naddr; /* */) { @@ -4513,9 +4688,9 @@ t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, if (idx != NULL) idx[offset+i] = - (index >= NUM_MPS_CLS_SRAM_L_INSTANCES ? + (index >= max_naddr ? 0xffff : index); - if (index < NUM_MPS_CLS_SRAM_L_INSTANCES) + if (index < max_naddr) nfilters++; else if (hash != NULL) *hash |= @@ -4561,6 +4736,10 @@ t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, int ret, mode; struct fw_vi_mac_cmd c; struct fw_vi_mac_exact *p = c.u.exact; + unsigned int max_mac_addr = is_t4(adap->params.chip) ? + NUM_MPS_CLS_SRAM_L_INSTANCES : + NUM_MPS_T5_CLS_SRAM_L_INSTANCES; + if (idx < 0) /* new allocation */ idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; @@ -4577,7 +4756,7 @@ t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, ret = t4_wr_mbox(adap, mbox, &c, sizeof (c), &c); if (ret == 0) { ret = G_FW_VI_MAC_CMD_IDX(ntohs(p->valid_to_idx)); - if (ret >= NUM_MPS_CLS_SRAM_L_INSTANCES) + if (ret >= max_mac_addr) ret = -ENOMEM; } return (ret); @@ -4807,7 +4986,11 @@ t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) { u8 opcode = *(const u8 *)rpl; - if (opcode == FW_PORT_CMD) { /* link/module state change message */ + const struct fw_port_cmd *p = (const void *)rpl; + unsigned int action = G_FW_PORT_CMD_ACTION(ntohl(p->action_to_len16)); + + if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) { + /* link/module state change message */ int i; const struct fw_port_cmd *p = (const void *)rpl; int chan = G_FW_PORT_CMD_PORTID(ntohl(p->op_to_portid)); @@ -4829,6 +5012,8 @@ t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) speed = SPEED_1000; else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) speed = SPEED_10000; + else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) + speed = SPEED_40000; for_each_port(adap, i) { pi = adap2pinfo(adap, i); @@ -4841,6 +5026,7 @@ t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) lc->link_ok = link_ok; lc->speed = speed; lc->fc = fc; + lc->supported = ntohs(p->u.info.pcap); t4_os_link_changed(adap, i, link_ok); } if (mod != pi->mod_type) { @@ -4849,6 +5035,11 @@ t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) t4_os_portmod_changed(adap, i); } } + else { + CH_WARN_RATELIMIT(adap, + "Unknown firmware reply 0x%x (0x%x)\n", opcode, action); + return -EINVAL; + } return (0); } @@ -4900,22 +5091,6 @@ init_link_config(struct link_config *lc, unsigned short caps) } static int __devinit -wait_dev_ready(struct adapter *adap) -{ - u32 whoami; - - whoami = t4_read_reg(adap, A_PL_WHOAMI); - - if (whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS) - return (0); - - msleep(500); - whoami = t4_read_reg(adap, A_PL_WHOAMI); - return ((whoami != 0xffffffff && whoami != X_CIM_PF_NOACCESS ? - 0 : -EIO)); -} - -static int __devinit get_flash_params(struct adapter *adapter) { int ret; @@ -4941,6 +5116,22 @@ get_flash_params(struct adapter *adapter) return (0); } +static void +__devinit set_pcie_completion_timeout(struct adapter *adapter, + u8 range) +{ + u16 val; + u32 pcie_cap; + + pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); + if (pcie_cap) { + t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); + val &= 0xfff0; + val |= range ; + t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); + } +} + /* * t4_prep_adapter - prepare SW and HW for operation * @adapter: the adapter @@ -4953,45 +5144,75 @@ get_flash_params(struct adapter *adapter) int __devinit t4_prep_adapter(struct adapter *adapter) { - int ret; - - ret = wait_dev_ready(adapter); - if (ret < 0) - return (ret); + int ret, ver; + uint16_t device_id; + uint32_t pl_rev; get_pci_mode(adapter, &adapter->params.pci); - adapter->params.rev = t4_read_reg(adapter, A_PL_REV); - if (adapter->params.rev == 1) { + pl_rev = t4_read_reg(adapter, A_PL_REV); + + /* + * WE DON'T NEED adapter->params.chip CODE ONCE PL_REV CONTAINS + * ADAPTER (VERSION << 4 | REVISION) + */ + /* + * Retrieve adapter's device ID + */ + t4_os_pci_read_cfg2(adapter, PCI_CONF_DEVID, &device_id); + ver = CHELSIO_PCI_ID_VER(device_id); + adapter->params.chip = 0; + switch (ver) { + case CHELSIO_T4_FPGA: + adapter->params.chip |= CHELSIO_CHIP_FPGA; + /*FALLTHROUGH*/ + case CHELSIO_T4: + adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); + break; + case CHELSIO_T5_FPGA: + adapter->params.chip |= CHELSIO_CHIP_FPGA; + /*FALLTHROUGH*/ + case CHELSIO_T5: + adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); + break; + default: + CH_ERR(adapter, "Device %d is not supported\n", device_id); + + return (-EINVAL); + } + + /* T4A1 chip is no longer supported */ + if (is_t4(adapter->params.chip) && (pl_rev == 1)) { CH_ALERT(adapter, "T4 rev 1 chip is no longer supported\n"); - return (-EINVAL); + return -EINVAL; } adapter->params.pci.vpd_cap_addr = t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); ret = get_flash_params(adapter); if (ret < 0) - return (ret); - - ret = get_vpd_params(adapter, &adapter->params.vpd); - if (ret < 0) - return (ret); + return ret; - if (t4_read_reg(adapter, A_SGE_PC0_REQ_BIST_CMD) != 0xffffffff) + if (is_fpga(adapter->params.chip)) { + /* FPGA */ adapter->params.cim_la_size = 2 * CIMLA_SIZE; - else + } else { + /* ASIC */ adapter->params.cim_la_size = CIMLA_SIZE; + } init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); /* - * Default port for debugging in case we can't reach FW. + * Default port and clock for debugging in case we can't reach FW. */ adapter->params.nports = 1; adapter->params.portvec = 1; adapter->params.vpd.cclk = 50000; - return (0); + /* Set pci completion timeout value to 4 seconds. */ + set_pcie_completion_timeout(adapter, 0xd); + return 0; } int __devinit diff --git a/usr/src/uts/common/io/cxgbe/common/t4_hw.h b/usr/src/uts/common/io/cxgbe/common/t4_hw.h index 4604597d74..7a6689a1fe 100644 --- a/usr/src/uts/common/io/cxgbe/common/t4_hw.h +++ b/usr/src/uts/common/io/cxgbe/common/t4_hw.h @@ -28,8 +28,8 @@ enum { NCHAN = 4, /* # of HW channels */ MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ - EEPROMSIZE = 17408, /* Serial EEPROM physical size */ - EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ + EEPROMSIZE = 17408,/* Serial EEPROM physical size */ + EEPROMVSIZE = 32768,/* Serial EEPROM virtual address space size */ EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ TCB_SIZE = 128, /* TCB size */ @@ -39,19 +39,24 @@ enum { PM_NSTATS = 5, /* # of PM stats */ MBOX_LEN = 64, /* mailbox size in bytes */ TRACE_LEN = 112, /* length of trace data and mask */ - FILTER_OPT_LEN = 36, /* filter tuple width for optional */ - /* components */ + FILTER_OPT_LEN = 36, /* filter tuple width of optional components */ NWOL_PAT = 8, /* # of WoL patterns */ WOL_PAT_LEN = 128, /* length of WoL patterns */ + UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */ + UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */ + UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */ + UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */ }; enum { CIM_NUM_IBQ = 6, /* # of CIM IBQs */ CIM_NUM_OBQ = 6, /* # of CIM OBQs */ + CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ + CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ }; @@ -73,6 +78,7 @@ enum { SGE_CTXT_SIZE = 24, /* size of SGE context */ SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ + SGE_MAX_IQ_SIZE = 65520, }; struct sge_qstat { /* data written to SGE queue status entries */ @@ -155,10 +161,12 @@ struct pagepod { #define S_PPOD_TAG 6 #define M_PPOD_TAG 0xFFFFFF #define V_PPOD_TAG(x) ((x) << S_PPOD_TAG) +#define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG) #define S_PPOD_PGSZ 30 #define M_PPOD_PGSZ 0x3 #define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ) +#define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ) #define S_PPOD_TID 32 #define M_PPOD_TID 0xFFFFFF @@ -212,11 +220,19 @@ enum { * Location of firmware image in FLASH. */ FLASH_FW_START_SEC = 8, - FLASH_FW_NSECS = 8, + FLASH_FW_NSECS = 16, FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), /* + * Location of bootstrap firmware image in FLASH. + */ + FLASH_FWBOOTSTRAP_START_SEC = 27, + FLASH_FWBOOTSTRAP_NSECS = 1, + FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC), + FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS), + + /* * iSCSI persistent/crash information. */ FLASH_ISCSI_CRASH_START_SEC = 29, diff --git a/usr/src/uts/common/io/cxgbe/common/t4_msg.h b/usr/src/uts/common/io/cxgbe/common/t4_msg.h index f3dc469cd3..f0df1fabaa 100644 --- a/usr/src/uts/common/io/cxgbe/common/t4_msg.h +++ b/usr/src/uts/common/io/cxgbe/common/t4_msg.h @@ -32,7 +32,6 @@ enum { CPL_SET_TCB = 0x4, CPL_SET_TCB_FIELD = 0x5, CPL_GET_TCB = 0x6, - CPL_PCMD = 0x7, CPL_CLOSE_CON_REQ = 0x8, CPL_CLOSE_LISTSRV_REQ = 0x9, CPL_ABORT_REQ = 0xA, @@ -47,9 +46,12 @@ enum { CPL_L2T_READ_REQ = 0x13, CPL_SMT_WRITE_REQ = 0x14, CPL_SMT_READ_REQ = 0x15, + CPL_TAG_WRITE_REQ = 0x16, CPL_BARRIER = 0x18, CPL_TID_RELEASE = 0x1A, - CPL_RX_MPS_PKT = 0x1B, + CPL_TAG_READ_REQ = 0x1B, + CPL_TX_PKT_FSO = 0x1E, + CPL_TX_PKT_ISO = 0x1F, CPL_CLOSE_LISTSRV_RPL = 0x20, CPL_ERROR = 0x21, @@ -61,6 +63,7 @@ enum { CPL_RTE_DELETE_RPL = 0x27, CPL_RTE_WRITE_RPL = 0x28, CPL_RX_URG_PKT = 0x29, + CPL_TAG_WRITE_RPL = 0x2A, CPL_ABORT_REQ_RSS = 0x2B, CPL_RX_URG_NOTIFY = 0x2C, CPL_ABORT_RPL_RSS = 0x2D, @@ -79,7 +82,7 @@ enum { CPL_RX_DATA = 0x39, CPL_SET_TCB_RPL = 0x3A, CPL_RX_PKT = 0x3B, - CPL_PCMD_RPL = 0x3C, + CPL_TAG_READ_RPL = 0x3C, CPL_HIT_NOTIFY = 0x3D, CPL_PKT_NOTIFY = 0x3E, CPL_RX_DDP_COMPLETE = 0x3F, @@ -92,23 +95,36 @@ enum { CPL_RX2TX_PKT = 0x45, CPL_RX_FCOE_DDP = 0x46, CPL_FCOE_HDR = 0x47, - + CPL_T5_TRACE_PKT = 0x48, + CPL_RX_ISCSI_DDP = 0x49, + CPL_RX_FCOE_DIF = 0x4A, + CPL_RX_DATA_DIF = 0x4B, + CPL_ERR_NOTIFY = 0x4D, + CPL_RDMA_READ_REQ = 0x60, + CPL_RX_ISCSI_DIF = 0x60, CPL_SET_LE_REQ = 0x80, CPL_PASS_OPEN_REQ6 = 0x81, CPL_ACT_OPEN_REQ6 = 0x83, - CPL_TX_DMA_ACK = 0xA0, CPL_RDMA_TERMINATE = 0xA2, CPL_RDMA_WRITE = 0xA4, CPL_SGE_EGR_UPDATE = 0xA5, CPL_SET_LE_RPL = 0xA6, CPL_FW2_MSG = 0xA7, CPL_FW2_PLD = 0xA8, + CPL_T5_RDMA_READ_REQ = 0xA9, + CPL_RDMA_ATOMIC_REQ = 0xAA, + CPL_RDMA_ATOMIC_RPL = 0xAB, + CPL_RDMA_IMM_DATA = 0xAC, + CPL_RDMA_IMM_DATA_SE = 0xAD, CPL_TRACE_PKT = 0xB0, + CPL_TRACE_PKT_T5 = 0x48, CPL_RX2TX_DATA = 0xB1, + CPL_ISCSI_DATA = 0xB2, + CPL_FCOE_DATA = 0xB3, CPL_FW4_MSG = 0xC0, CPL_FW4_PLD = 0xC1, @@ -275,13 +291,13 @@ struct tcp_options { #if defined(__LITTLE_ENDIAN_BITFIELD) __u8 :4; __u8 unknown:1; - __u8 :1; + __u8 ecn:1; __u8 sack:1; __u8 tstamp:1; #else __u8 tstamp:1; __u8 sack:1; - __u8 :1; + __u8 ecn:1; __u8 unknown:1; __u8 :4; #endif @@ -459,6 +475,11 @@ struct work_request_hdr { #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) +#define S_FILT_INFO 28 +#define M_FILT_INFO 0xfffffffffULL +#define V_FILT_INFO(x) ((x) << S_FILT_INFO) +#define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) + /* option 2 fields */ #define S_RSS_QUEUE 0 #define M_RSS_QUEUE 0x3FF @@ -533,6 +554,10 @@ struct work_request_hdr { #define V_SACK_EN(x) ((x) << S_SACK_EN) #define F_SACK_EN V_SACK_EN(1U) +#define S_T5_OPT_2_VALID 31 +#define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) +#define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) + struct cpl_pass_open_req { WR_HDR; union opcode_tid ot; @@ -622,7 +647,7 @@ struct cpl_pass_accept_req { #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) #define S_ETH_HDR_LEN 26 -#define M_ETH_HDR_LEN 0x1F +#define M_ETH_HDR_LEN 0x3F #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) @@ -648,6 +673,15 @@ struct cpl_pass_accept_rpl { __be64 opt0; }; +struct cpl_t5_pass_accept_rpl { + WR_HDR; + union opcode_tid ot; + __be32 opt2; + __be64 opt0; + __be32 iss; + __be32 rsvd; +}; + struct cpl_act_open_req { WR_HDR; union opcode_tid ot; @@ -660,6 +694,23 @@ struct cpl_act_open_req { __be32 opt2; }; +#define S_FILTER_TUPLE 24 +#define M_FILTER_TUPLE 0xFFFFFFFFFF +#define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) +#define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) +struct cpl_t5_act_open_req { + WR_HDR; + union opcode_tid ot; + __be16 local_port; + __be16 peer_port; + __be32 local_ip; + __be32 peer_ip; + __be64 opt0; + __be32 iss; + __be32 opt2; + __be64 params; +}; + struct cpl_act_open_req6 { WR_HDR; union opcode_tid ot; @@ -674,6 +725,21 @@ struct cpl_act_open_req6 { __be32 opt2; }; +struct cpl_t5_act_open_req6 { + WR_HDR; + union opcode_tid ot; + __be16 local_port; + __be16 peer_port; + __be64 local_ip_hi; + __be64 local_ip_lo; + __be64 peer_ip_hi; + __be64 peer_ip_lo; + __be64 opt0; + __be32 iss; + __be32 opt2; + __be64 params; +}; + struct cpl_act_open_rpl { RSS_HDR union opcode_tid ot; @@ -747,6 +813,14 @@ struct cpl_set_tcb_field { __be64 val; }; +struct cpl_set_tcb_field_core { + union opcode_tid ot; + __be16 reply_ctrl; + __be16 word_cookie; + __be64 mask; + __be64 val; +}; + /* cpl_set_tcb_field.word_cookie fields */ #define S_WORD 0 #define M_WORD 0x1F @@ -998,6 +1072,12 @@ struct cpl_tx_pkt { #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) +#define S_TXPKT_T5_OVLAN_IDX 12 +#define M_TXPKT_T5_OVLAN_IDX 0x7 +#define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) +#define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ + M_TXPKT_T5_OVLAN_IDX) + #define S_TXPKT_INTF 16 #define M_TXPKT_INTF 0xF #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) @@ -1007,10 +1087,18 @@ struct cpl_tx_pkt { #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) +#define S_TXPKT_T5_FCS_DIS 21 +#define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) +#define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) + #define S_TXPKT_INS_OVLAN 21 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) +#define S_TXPKT_T5_INS_OVLAN 15 +#define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) +#define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) + #define S_TXPKT_STAT_DIS 22 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) @@ -1019,6 +1107,10 @@ struct cpl_tx_pkt { #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) +#define S_TXPKT_TSTAMP 23 +#define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) +#define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) + #define S_TXPKT_OPCODE 24 #define M_TXPKT_OPCODE 0xFF #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) @@ -1081,7 +1173,7 @@ struct cpl_tx_pkt { #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) -struct cpl_tx_pkt_lso { +struct cpl_tx_pkt_lso_core{ __be32 lso_ctrl; __be16 ipid_ofst; __be16 mss; @@ -1090,7 +1182,29 @@ struct cpl_tx_pkt_lso { /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ }; -/* cpl_tx_pkt_lso.lso_ctrl fields */ +struct cpl_tx_pkt_lso { + WR_HDR; + struct cpl_tx_pkt_lso_core c; + /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ +}; + +struct cpl_tx_pkt_ufo_core { + __be16 ethlen; + __be16 iplen; + __be16 udplen; + __be16 mss; + __be32 len; + __be32 r1; + /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ +}; + +struct cpl_tx_pkt_ufo { + WR_HDR; + struct cpl_tx_pkt_ufo_core c; + /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ +}; + +/* cpl_tx_pkt_lso_core.lso_ctrl fields */ #define S_LSO_TCPHDR_LEN 0 #define M_LSO_TCPHDR_LEN 0xF #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) @@ -1127,7 +1241,12 @@ struct cpl_tx_pkt_lso { #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) -/* cpl_tx_pkt_lso.mss fields */ +#define S_LSO_T5_XFER_SIZE 0 +#define M_LSO_T5_XFER_SIZE 0xFFFFFFF +#define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) +#define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) + +/* cpl_tx_pkt_lso_core.mss fields */ #define S_LSO_MSS 0 #define M_LSO_MSS 0x3FFF #define V_LSO_MSS(x) ((x) << S_LSO_MSS) @@ -1137,32 +1256,30 @@ struct cpl_tx_pkt_lso { #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) -struct cpl_tx_pkt_coalesce { - __be32 cntrl; - __be32 len; - __be64 addr; -}; - -struct tx_pkt_coalesce_wr { +struct cpl_tx_pkt_fso { WR_HDR; -#if !(defined C99_NOT_SUPPORTED) - struct cpl_tx_pkt_coalesce cpl[]; -#endif -}; - -struct mngt_pktsched_wr { - __be32 wr_hi; - __be32 wr_lo; - __u8 mngt_opcode; - __u8 rsvd[7]; - __u8 sched; - __u8 idx; - __u8 min; - __u8 max; - __u8 binding; - __u8 rsvd1[3]; -}; - + __be32 fso_ctrl; + __be16 seqcnt_ofst; + __be16 mtu; + __be32 param_offset; + __be32 len; + /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ +}; + +/* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ +#define S_FSO_XCHG_CLASS 21 +#define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) +#define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) + +#define S_FSO_INITIATOR 20 +#define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) +#define F_FSO_INITIATOR V_FSO_INITIATOR(1U) + +#define S_FSO_FCHDR_LEN 12 +#define M_FSO_FCHDR_LEN 0xF +#define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) +#define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) + struct cpl_iscsi_hdr_no_rss { union opcode_tid ot; __be16 pdu_len_ddp; @@ -1173,6 +1290,40 @@ struct cpl_iscsi_hdr_no_rss { __u8 status; }; +struct cpl_tx_data_iso { + WR_HDR; + __be32 iso_ctrl; + __u8 rsvd; + __u8 ahs_len; + __be16 mss; + __be32 burst_size; + __be32 len; + /* encapsulated CPL_TX_DATA follows here */ +}; + +/* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ +#define S_ISO_CPLHDR_LEN 18 +#define M_ISO_CPLHDR_LEN 0xF +#define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN) +#define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN) + +#define S_ISO_HDR_CRC 17 +#define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC) +#define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U) + +#define S_ISO_DATA_CRC 16 +#define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC) +#define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U) + +#define S_ISO_IMD_DATA_EN 15 +#define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN) +#define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U) + +#define S_ISO_PDU_TYPE 13 +#define M_ISO_PDU_TYPE 0x3 +#define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE) +#define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE) + struct cpl_iscsi_hdr { RSS_HDR union opcode_tid ot; @@ -1194,6 +1345,17 @@ struct cpl_iscsi_hdr { #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) #define F_ISCSI_DDP V_ISCSI_DDP(1U) +struct cpl_iscsi_data { + RSS_HDR + union opcode_tid ot; + __u8 rsvd0[2]; + __be16 len; + __be32 seq; + __be16 urg; + __u8 rsvd1; + __u8 status; +}; + struct cpl_rx_data { RSS_HDR union opcode_tid ot; @@ -1233,6 +1395,16 @@ struct cpl_fcoe_hdr { __be32 param; }; +struct cpl_fcoe_data { + RSS_HDR + union opcode_tid ot; + __u8 rsvd0[2]; + __be16 len; + __be32 seq; + __u8 rsvd1[3]; + __u8 status; +}; + struct cpl_rx_urg_notify { RSS_HDR union opcode_tid ot; @@ -1252,6 +1424,11 @@ struct cpl_rx_data_ack { __be32 credit_dack; }; +struct cpl_rx_data_ack_core { + union opcode_tid ot; + __be32 credit_dack; +}; + /* cpl_rx_data_ack.ack_seq fields */ #define S_RX_CREDITS 0 #define M_RX_CREDITS 0x3FFFFFF @@ -1301,6 +1478,8 @@ struct cpl_rx_data_ddp { __be32 ddpvld; }; +#define cpl_rx_iscsi_ddp cpl_rx_data_ddp + struct cpl_rx_fcoe_ddp { RSS_HDR union opcode_tid ot; @@ -1312,7 +1491,49 @@ struct cpl_rx_fcoe_ddp { __be32 ddpvld; }; -/* cpl_rx_{data,fcoe}_ddp.ddpvld fields */ +struct cpl_rx_data_dif { + RSS_HDR + union opcode_tid ot; + __be16 ddp_len; + __be16 msg_len; + __be32 seq; + union { + __be32 nxt_seq; + __be32 ddp_report; + } u; + __be32 err_vec; + __be32 ddpvld; +}; + +struct cpl_rx_iscsi_dif { + RSS_HDR + union opcode_tid ot; + __be16 ddp_len; + __be16 msg_len; + __be32 seq; + union { + __be32 nxt_seq; + __be32 ddp_report; + } u; + __be32 ulp_crc; + __be32 ddpvld; + __u8 rsvd0[8]; + __be32 err_vec; + __u8 rsvd1[4]; +}; + +struct cpl_rx_fcoe_dif { + RSS_HDR + union opcode_tid ot; + __be16 ddp_len; + __be16 msg_len; + __be32 seq; + __be32 ddp_report; + __be32 err_vec; + __be32 ddpvld; +}; + +/* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ #define S_DDP_VALID 15 #define M_DDP_VALID 0x1FFFF #define V_DDP_VALID(x) ((x) << S_DDP_VALID) @@ -1375,7 +1596,7 @@ struct cpl_rx_fcoe_ddp { #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) -/* cpl_rx_{data,fcoe}_ddp.ddp_report fields */ +/* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ #define S_DDP_OFFSET 0 #define M_DDP_OFFSET 0xFFFFFF #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) @@ -1440,16 +1661,31 @@ struct cpl_rx_pkt { #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) +#define S_RX_T5_ETHHDR_LEN 0 +#define M_RX_T5_ETHHDR_LEN 0x3F +#define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) +#define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) + #define S_RX_PKTYPE 5 #define M_RX_PKTYPE 0x7 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) +#define S_RX_T5_DATYPE 6 +#define M_RX_T5_DATYPE 0x3 +#define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) +#define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) + #define S_RX_MACIDX 8 #define M_RX_MACIDX 0x1FF #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) +#define S_RX_T5_PKTYPE 17 +#define M_RX_T5_PKTYPE 0x7 +#define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) +#define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) + #define S_RX_DATYPE 18 #define M_RX_DATYPE 0x3 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) @@ -1582,6 +1818,29 @@ struct cpl_trace_pkt { __be64 tstamp; }; +struct cpl_t5_trace_pkt { + RSS_HDR + __u8 opcode; + __u8 intf; +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 runt:4; + __u8 filter_hit:4; + __u8 :6; + __u8 err:1; + __u8 trunc:1; +#else + __u8 filter_hit:4; + __u8 runt:4; + __u8 trunc:1; + __u8 err:1; + __u8 :6; +#endif + __be16 rsvd; + __be16 len; + __be64 tstamp; + __be64 rsvd1; +}; + struct cpl_rte_delete_req { WR_HDR; union opcode_tid ot; @@ -1685,14 +1944,24 @@ struct cpl_l2t_write_req { #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) #define S_L2T_W_PORT 8 -#define M_L2T_W_PORT 0xF +#define M_L2T_W_PORT 0x3 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) +#define S_L2T_W_LPBK 10 +#define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) +#define F_L2T_W_PKBK V_L2T_W_LPBK(1U) + +#define S_L2T_W_ARPMISS 11 +#define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) +#define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) + #define S_L2T_W_NOREPLY 15 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) +#define CPL_L2T_VLAN_NONE 0xfff + struct cpl_l2t_write_rpl { RSS_HDR union opcode_tid ot; @@ -1732,6 +2001,31 @@ struct cpl_smt_write_req { __u8 src_mac0[6]; }; +struct cpl_smt_write_rpl { + RSS_HDR + union opcode_tid ot; + __u8 status; + __u8 rsvd[3]; +}; + +struct cpl_smt_read_req { + WR_HDR; + union opcode_tid ot; + __be32 params; +}; + +struct cpl_smt_read_rpl { + RSS_HDR + union opcode_tid ot; + __u8 status; + __u8 ovlan_idx; + __be16 rsvd; + __be16 pfvf1; + __u8 src_mac1[6]; + __be16 pfvf0; + __u8 src_mac0[6]; +}; + /* cpl_smt_{read,write}_req.params fields */ #define S_SMTW_OVLAN_IDX 16 #define M_SMTW_OVLAN_IDX 0xF @@ -1762,31 +2056,66 @@ struct cpl_smt_write_req { #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) -struct cpl_smt_write_rpl { +struct cpl_tag_write_req { + WR_HDR; + union opcode_tid ot; + __be32 params; + __be64 tag_val; +}; + +struct cpl_tag_write_rpl { + RSS_HDR union opcode_tid ot; __u8 status; - __u8 rsvd[3]; + __u8 rsvd[2]; + __u8 idx; }; -struct cpl_smt_read_req { +struct cpl_tag_read_req { WR_HDR; union opcode_tid ot; __be32 params; }; -struct cpl_smt_read_rpl { +struct cpl_tag_read_rpl { RSS_HDR union opcode_tid ot; __u8 status; - __u8 ovlan_idx; - __be16 rsvd; - __be16 pfvf1; - __u8 src_mac1[6]; - __be16 pfvf0; - __u8 src_mac0[6]; +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 :4; + __u8 tag_len:1; + __u8 :2; + __u8 ins_enable:1; +#else + __u8 ins_enable:1; + __u8 :2; + __u8 tag_len:1; + __u8 :4; +#endif + __u8 rsvd; + __u8 tag_idx; + __be64 tag_val; }; +/* cpl_tag{read,write}_req.params fields */ +#define S_TAGW_IDX 0 +#define M_TAGW_IDX 0x7F +#define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) +#define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) + +#define S_TAGW_LEN 20 +#define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) +#define F_TAGW_LEN V_TAGW_LEN(1U) + +#define S_TAGW_INS_ENABLE 23 +#define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) +#define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) + +#define S_TAGW_NORPL 31 +#define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) +#define F_TAGW_NORPL V_TAGW_NORPL(1U) + struct cpl_barrier { WR_HDR; __u8 opcode; @@ -1850,6 +2179,16 @@ struct cpl_pkt_notify { #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) +#define S_NTFY_T5_IPHDR_LEN 18 +#define M_NTFY_T5_IPHDR_LEN 0xFF +#define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) +#define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) + +#define S_NTFY_T5_ETHHDR_LEN 26 +#define M_NTFY_T5_ETHHDR_LEN 0x3F +#define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) +#define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) + struct cpl_rdma_terminate { RSS_HDR union opcode_tid ot; @@ -1934,6 +2273,15 @@ struct cpl_sge_egr_update { #define V_EGR_QID(x) ((x) << S_EGR_QID) #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) +/* cpl_fw*.type values */ +enum { + FW_TYPE_CMD_RPL = 0, + FW_TYPE_WR_RPL = 1, + FW_TYPE_CQE = 2, + FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, + FW_TYPE_RSSCPL = 4, +}; + struct cpl_fw2_pld { RSS_HDR u8 opcode; @@ -2002,7 +2350,21 @@ struct cpl_fw6_msg { /* cpl_fw6_msg.type values */ enum { - FW6_TYPE_CMD_RPL = 0, + FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, + FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, + FW6_TYPE_CQE = FW_TYPE_CQE, + FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, + FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, + + NUM_FW6_TYPES +}; + +struct cpl_fw6_msg_ofld_connection_wr_rpl { + __u64 cookie; + __be32 tid; /* or atid in case of active failure */ + __u8 t_state; + __u8 retval; + __u8 rsvd[2]; }; /* ULP_TX opcodes */ @@ -2081,6 +2443,14 @@ struct ulp_mem_io { #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) +#define S_T5_ULP_MEMIO_IMM 23 +#define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) +#define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) + +#define S_T5_ULP_MEMIO_ORDER 22 +#define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) +#define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) + /* ulp_mem_io.lock_addr fields */ #define S_ULP_MEMIO_ADDR 0 #define M_ULP_MEMIO_ADDR 0x7FFFFFF @@ -2095,6 +2465,14 @@ struct ulp_mem_io { #define M_ULP_MEMIO_DATA_LEN 0x1F #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) +/* ULP_TXPKT field values */ +enum { + ULP_TXPKT_DEST_TP = 0, + ULP_TXPKT_DEST_SGE, + ULP_TXPKT_DEST_UP, + ULP_TXPKT_DEST_DEVNULL, +}; + struct ulp_txpkt { __be32 cmd_dest; __be32 len; @@ -2109,4 +2487,8 @@ struct ulp_txpkt { #define M_ULP_TXPKT_FID 0x7ff #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) +#define S_ULP_TXPKT_RO 3 +#define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) +#define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) + #endif /* __CXGBE_T4_MSG_H */ diff --git a/usr/src/uts/common/io/cxgbe/common/t4_regs.h b/usr/src/uts/common/io/cxgbe/common/t4_regs.h index 00409f1cde..933ecc1b67 100644 --- a/usr/src/uts/common/io/cxgbe/common/t4_regs.h +++ b/usr/src/uts/common/io/cxgbe/common/t4_regs.h @@ -28,6 +28,21 @@ #define MYPF_BASE 0x1b000 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr)) +#define VF_SGE_BASE 0x0 +#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr)) + +#define VF_MPS_BASE 0x100 +#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr)) + +#define VF_PL_BASE 0x200 +#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr)) + +#define VF_MBDATA_BASE 0x240 +#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr)) + +#define VF_CIM_BASE 0x300 +#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr)) + #define PF0_BASE 0x1e000 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr)) @@ -75,194 +90,289 @@ #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) -#define VF_SGE_BASE 0x0 -#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr)) +#define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8) +#define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136 -#define VF_MPS_BASE 0x100 -#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr)) +#define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8) +#define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136 -#define VF_PL_BASE 0x200 -#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr)) +#define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_DMA_INSTANCES 4 -#define VF_MBDATA_BASE 0x240 -#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr)) +#define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_CMD_INSTANCES 2 -#define VF_CIM_BASE 0x300 -#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr)) +#define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_HMA_INSTANCES 1 -#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) -#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) +#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_MEM_ACCESS_INSTANCES 8 -#define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8) -#define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136 +#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_MAILBOX_INSTANCES 1 -#define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8) -#define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136 +#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_PCIE_FW_INSTANCES 8 -#define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) -#define NUM_PCIE_DMA_INSTANCES 4 +#define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_FUNC_INSTANCES 256 -#define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) -#define NUM_PCIE_CMD_INSTANCES 2 +#define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4) +#define NUM_PCIE_FID_INSTANCES 2048 -#define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) -#define NUM_PCIE_HMA_INSTANCES 1 +#define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_DMA_BUF_INSTANCES 4 -#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) -#define NUM_PCIE_MEM_ACCESS_INSTANCES 8 +#define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256) +#define NUM_MC_DDR3PHYDATX8_INSTANCES 9 -#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) -#define NUM_PCIE_MAILBOX_INSTANCES 1 +#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_BIST_STATUS_INSTANCES 18 -#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) -#define NUM_PCIE_FW_INSTANCES 8 +#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_EDC_BIST_STATUS_INSTANCES 18 -#define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) -#define NUM_PCIE_FUNC_INSTANCES 256 +#define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4) +#define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16 -#define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4) -#define NUM_PCIE_FID_INSTANCES 2048 +#define MPS_TRC_FILTER_MATCH_CTL_A(idx) \ + (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4) +#define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4 -#define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) -#define NUM_PCIE_DMA_BUF_INSTANCES 4 +#define MPS_TRC_FILTER_MATCH_CTL_B(idx) \ + (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4) +#define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4 -#define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256) -#define NUM_MC_DDR3PHYDATX8_INSTANCES 9 +#define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4) +#define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4 -#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) -#define NUM_MC_BIST_STATUS_INSTANCES 18 +#define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4) +#define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4 -#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) -#define NUM_EDC_BIST_STATUS_INSTANCES 18 +#define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4) +#define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28 -#define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4) -#define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16 +#define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4) +#define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28 -#define MPS_TRC_FILTER_MATCH_CTL_A(idx) \ - (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4) -#define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4 +#define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4) +#define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28 -#define MPS_TRC_FILTER_MATCH_CTL_B(idx) \ - (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4) -#define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4 +#define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4) +#define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28 -#define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4) -#define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4 +#define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4) +#define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28 -#define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4) -#define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4 +#define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4) +#define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28 -#define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4) -#define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28 +#define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4) +#define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28 -#define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4) -#define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28 +#define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4) +#define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28 -#define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4) -#define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28 +#define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4) +#define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65 -#define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4) -#define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28 +#define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4) +#define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9 -#define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4) -#define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28 +#define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8) +#define NUM_MPS_CLS_SRAM_L_INSTANCES 336 -#define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4) -#define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28 +#define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8) +#define NUM_MPS_CLS_SRAM_H_INSTANCES 336 -#define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4) -#define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28 +#define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16) +#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512 -#define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4) -#define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28 +#define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16) +#define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512 -#define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4) -#define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65 +#define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16) +#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512 -#define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4) -#define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9 +#define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16) +#define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512 -#define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8) -#define NUM_MPS_CLS_SRAM_L_INSTANCES 336 +#define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4) +#define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8 -#define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8) -#define NUM_MPS_CLS_SRAM_H_INSTANCES 336 +#define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8) +#define NUM_PL_VF_SLICE_L_INSTANCES 8 -#define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16) -#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512 +#define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8) +#define NUM_PL_VF_SLICE_H_INSTANCES 8 -#define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16) -#define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512 +#define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4) +#define NUM_PL_FLR_VF_STATUS_INSTANCES 4 -#define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16) -#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512 +#define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4) +#define NUM_PL_VFID_MAP_INSTANCES 256 -#define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16) -#define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512 +#define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4) +#define NUM_LE_DB_MASK_IPV4_INSTANCES 17 -#define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4) -#define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8 +#define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4) +#define NUM_LE_DB_MASK_IPV6_INSTANCES 17 -#define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8) -#define NUM_PL_VF_SLICE_L_INSTANCES 8 +#define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4) +#define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17 -#define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8) -#define NUM_PL_VF_SLICE_H_INSTANCES 8 +#define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4) +#define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17 -#define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4) -#define NUM_PL_FLR_VF_STATUS_INSTANCES 4 +#define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4) +#define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17 -#define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4) -#define NUM_PL_VFID_MAP_INSTANCES 256 +#define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4) +#define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17 -#define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4) -#define NUM_LE_DB_MASK_IPV4_INSTANCES 17 +#define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4) +#define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17 -#define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4) -#define NUM_LE_DB_MASK_IPV6_INSTANCES 17 +#define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4) +#define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4 -#define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4) -#define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17 +#define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4) +#define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12 -#define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4) -#define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17 +#define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4) +#define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4 -#define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4) -#define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17 +#define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4) +#define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12 -#define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4) -#define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17 +#define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_UP_TSCH_CHANNEL_INSTANCES 4 -#define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4) -#define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17 +#define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4) +#define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4 -#define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4) -#define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4 +#define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16) +#define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128 -#define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4) -#define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12 +#define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288) +#define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4 -#define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4) -#define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4 +#define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) \ + ((reg_addr) + (idx) * 16) +#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16 -#define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4) -#define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12 +#define T5_MYPORT_BASE 0x2c000 +#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr)) -#define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) -#define NUM_UP_TSCH_CHANNEL_INSTANCES 4 +#define T5_PORT0_BASE 0x30000 +#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr)) -#define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4) -#define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4 +#define T5_PORT1_BASE 0x34000 +#define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr)) -#define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16) -#define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128 +#define T5_PORT2_BASE 0x38000 +#define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr)) -#define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288) -#define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4 +#define T5_PORT3_BASE 0x3c000 +#define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr)) -#define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) \ - ((reg_addr) + (idx) * 16) -#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16 +#define T5_PORT_STRIDE 0x4000 +#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE) +#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg)) + +#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR) +#define MC_REG(reg, idx) (reg + MC_STRIDE * idx) + +#define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_PF_INT_INSTANCES 8 + +#define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8) +#define NUM_PCIE_VF_INT_INSTANCES 128 + +#define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4) +#define NUM_PCIE_FID_VFID_INSTANCES 2048 + +#define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_PCIE_COOKIE_INSTANCES 8 + +#define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_PCIE_T5_DMA_INSTANCES 4 + +#define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_PCIE_T5_CMD_INSTANCES 3 + +#define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16) +#define NUM_PCIE_T5_HMA_INSTANCES 1 + +#define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_PCIE_PHY_PRESET_INSTANCES 11 + +#define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8) +#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512 + +#define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8) +#define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512 + +#define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4) +#define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5 + +#define LE_T5_DB_ACTIVE_MASK_IPV4(idx) \ + (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4) +#define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5 + +#define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4) +#define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5 + +#define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4) +#define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12 + +#define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4) +#define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5 + +#define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4) +#define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12 + +#define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) \ + (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4) +#define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5 + +#define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) \ + (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4) +#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5 + +#define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) \ + (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4) +#define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5 + +#define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512) +#define NUM_MC_ADR_INSTANCES 2 + +#define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512) +#define NUM_MC_DDRPHY_DP18_INSTANCES 5 + +#define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_CE_ERR_DATA_INSTANCES 8 + +#define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_CE_COR_DATA_INSTANCES 8 + +#define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_UE_ERR_DATA_INSTANCES 8 + +#define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_UE_COR_DATA_INSTANCES 8 + +#define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_MC_P_BIST_STATUS_INSTANCES 18 + +#define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_EDC_H_BIST_STATUS_INSTANCES 18 + +#define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4) +#define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16 + +#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR) +#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx) /* registers for module SGE */ #define SGE_BASE_ADDR 0x1000 @@ -284,6 +394,15 @@ #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX) #define A_SGE_VF_KDOORBELL 0x0 +#define S_DBTYPE 13 +#define V_DBTYPE(x) ((x) << S_DBTYPE) +#define F_DBTYPE V_DBTYPE(1U) + +#define S_PIDX_T5 0 +#define M_PIDX_T5 0x1fffU +#define V_PIDX_T5(x) ((x) << S_PIDX_T5) +#define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5) + #define A_SGE_PF_GTS 0x4 #define S_INGRESSQID 16 @@ -306,6 +425,17 @@ #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC) #define A_SGE_VF_GTS 0x4 +#define A_SGE_PF_KTIMESTAMP_LO 0x8 +#define A_SGE_VF_KTIMESTAMP_LO 0x8 +#define A_SGE_PF_KTIMESTAMP_HI 0xc + +#define S_TSTAMPVAL 0 +#define M_TSTAMPVAL 0xfffffffU +#define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL) +#define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL) + +#define A_SGE_VF_KTIMESTAMP_HI 0xc + #define A_SGE_CONTROL 0x1008 #define S_IGRALLCPLTOFL 31 @@ -670,6 +800,10 @@ #define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP) #define F_PERR_EGR_CTXT_MIFRSP V_PERR_EGR_CTXT_MIFRSP(1U) +#define S_PERR_PC_CHPI_RSP2 31 +#define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2) +#define F_PERR_PC_CHPI_RSP2 V_PERR_PC_CHPI_RSP2(1U) + #define A_SGE_INT_ENABLE1 0x1028 #define A_SGE_PERR_ENABLE1 0x102c #define A_SGE_INT_CAUSE2 0x1030 @@ -798,6 +932,22 @@ #define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE) #define F_PERR_BASE_SIZE V_PERR_BASE_SIZE(1U) +#define S_PERR_DBP_HINT_FL_FIFO 24 +#define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO) +#define F_PERR_DBP_HINT_FL_FIFO V_PERR_DBP_HINT_FL_FIFO(1U) + +#define S_PERR_EGR_DBP_TX_COAL 23 +#define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL) +#define F_PERR_EGR_DBP_TX_COAL V_PERR_EGR_DBP_TX_COAL(1U) + +#define S_PERR_DBP_FL_FIFO 22 +#define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO) +#define F_PERR_DBP_FL_FIFO V_PERR_DBP_FL_FIFO(1U) + +#define S_PERR_PC_DBP2 15 +#define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2) +#define F_PERR_PC_DBP2 V_PERR_PC_DBP2(1U) + #define A_SGE_INT_ENABLE2 0x1034 #define A_SGE_PERR_ENABLE2 0x1038 #define A_SGE_INT_CAUSE3 0x103c @@ -1002,6 +1152,11 @@ #define V_NOEDRAM(x) ((x) << S_NOEDRAM) #define F_NOEDRAM V_NOEDRAM(1U) +#define S_CREDITCNTPACKING 2 +#define M_CREDITCNTPACKING 0x3U +#define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING) +#define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING) + #define A_SGE_CONM_CTRL 0x1094 #define S_EGRTHRESHOLD 8 @@ -1022,6 +1177,12 @@ #define V_TP_ENABLE(x) ((x) << S_TP_ENABLE) #define F_TP_ENABLE V_TP_ENABLE(1U) +#define S_EGRTHRESHOLDPACKING 14 +#define M_EGRTHRESHOLDPACKING 0x3fU +#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING) +#define G_EGRTHRESHOLDPACKING(x) \ + (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING) + #define A_SGE_TIMESTAMP_LO 0x1098 #define A_SGE_TIMESTAMP_HI 0x109c @@ -1079,6 +1240,24 @@ #define V_LP_COUNT(x) ((x) << S_LP_COUNT) #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT) +#define S_BAR2VALID 31 +#define V_BAR2VALID(x) ((x) << S_BAR2VALID) +#define F_BAR2VALID V_BAR2VALID(1U) + +#define S_BAR2FULL 30 +#define V_BAR2FULL(x) ((x) << S_BAR2FULL) +#define F_BAR2FULL V_BAR2FULL(1U) + +#define S_LP_INT_THRESH_T5 18 +#define M_LP_INT_THRESH_T5 0xfffU +#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5) +#define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5) + +#define S_LP_COUNT_T5 0 +#define M_LP_COUNT_T5 0x3ffffU +#define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5) +#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5) + #define A_SGE_DOORBELL_CONTROL 0x10a8 #define S_HINTDEPTHCTL 27 @@ -1160,6 +1339,24 @@ #define V_THROTTLE_ENABLE(x) ((x) << S_THROTTLE_ENABLE) #define F_THROTTLE_ENABLE V_THROTTLE_ENABLE(1U) +#define S_BAR2THROTTLECOUNT 16 +#define M_BAR2THROTTLECOUNT 0xffU +#define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT) +#define G_BAR2THROTTLECOUNT(x) \ + (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT) + +#define S_CLRCOALESCEDISABLE 15 +#define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE) +#define F_CLRCOALESCEDISABLE V_CLRCOALESCEDISABLE(1U) + +#define S_OPENBAR2GATEONCE 14 +#define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE) +#define F_OPENBAR2GATEONCE V_OPENBAR2GATEONCE(1U) + +#define S_FORCEOPENBAR2GATE 13 +#define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE) +#define F_FORCEOPENBAR2GATE V_FORCEOPENBAR2GATE(1U) + #define A_SGE_ITP_CONTROL 0x10b4 #define S_CRITICAL_TIME 10 @@ -1314,6 +1511,96 @@ #define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER) #define F_ERR_UNEXPECTED_TIMER V_ERR_UNEXPECTED_TIMER(1U) +#define S_BAR2_EGRESS_LEN_OR_ADDR_ERR 29 +#define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR) +#define F_BAR2_EGRESS_LEN_OR_ADDR_ERR V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U) + +#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1 28 +#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) \ + ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1) +#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1 V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U) + +#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0 27 +#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) \ + ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0) +#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0 V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U) + +#define S_ERR_WR_LEN_TOO_LARGE3 26 +#define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3) +#define F_ERR_WR_LEN_TOO_LARGE3 V_ERR_WR_LEN_TOO_LARGE3(1U) + +#define S_ERR_WR_LEN_TOO_LARGE2 25 +#define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2) +#define F_ERR_WR_LEN_TOO_LARGE2 V_ERR_WR_LEN_TOO_LARGE2(1U) + +#define S_ERR_WR_LEN_TOO_LARGE1 24 +#define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1) +#define F_ERR_WR_LEN_TOO_LARGE1 V_ERR_WR_LEN_TOO_LARGE1(1U) + +#define S_ERR_WR_LEN_TOO_LARGE0 23 +#define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0) +#define F_ERR_WR_LEN_TOO_LARGE0 V_ERR_WR_LEN_TOO_LARGE0(1U) + +#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3 22 +#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) \ + ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3) +#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3 V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U) + +#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2 21 +#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) \ + ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2) +#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2 V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U) + +#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1 20 +#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) \ + ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1) +#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1 V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U) + +#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0 19 +#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) \ + ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0) +#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0 V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U) + +#define S_COAL_WITH_HP_DISABLE_ERR 18 +#define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR) +#define F_COAL_WITH_HP_DISABLE_ERR V_COAL_WITH_HP_DISABLE_ERR(1U) + +#define S_BAR2_EGRESS_COAL0_ERR 17 +#define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR) +#define F_BAR2_EGRESS_COAL0_ERR V_BAR2_EGRESS_COAL0_ERR(1U) + +#define S_BAR2_EGRESS_SIZE_ERR 16 +#define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR) +#define F_BAR2_EGRESS_SIZE_ERR V_BAR2_EGRESS_SIZE_ERR(1U) + +#define S_FLM_PC_RSP_ERR 15 +#define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR) +#define F_FLM_PC_RSP_ERR V_FLM_PC_RSP_ERR(1U) + +#define S_DBFIFO_HP_INT_LOW 14 +#define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW) +#define F_DBFIFO_HP_INT_LOW V_DBFIFO_HP_INT_LOW(1U) + +#define S_DBFIFO_LP_INT_LOW 13 +#define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW) +#define F_DBFIFO_LP_INT_LOW V_DBFIFO_LP_INT_LOW(1U) + +#define S_DBFIFO_FL_INT_LOW 12 +#define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW) +#define F_DBFIFO_FL_INT_LOW V_DBFIFO_FL_INT_LOW(1U) + +#define S_DBFIFO_FL_INT 11 +#define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT) +#define F_DBFIFO_FL_INT V_DBFIFO_FL_INT(1U) + +#define S_ERR_RX_CPL_PACKET_SIZE1 10 +#define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1) +#define F_ERR_RX_CPL_PACKET_SIZE1 V_ERR_RX_CPL_PACKET_SIZE1(1U) + +#define S_ERR_RX_CPL_PACKET_SIZE0 9 +#define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0) +#define F_ERR_RX_CPL_PACKET_SIZE0 V_ERR_RX_CPL_PACKET_SIZE0(1U) + #define A_SGE_INT_ENABLE4 0x10e0 #define A_SGE_STAT_TOTAL 0x10e4 #define A_SGE_STAT_MATCH 0x10e8 @@ -1343,6 +1630,11 @@ #define V_STATSOURCE(x) ((x) << S_STATSOURCE) #define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE) +#define S_STATSOURCE_T5 9 +#define M_STATSOURCE_T5 0xfU +#define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5) +#define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5) + #define A_SGE_HINT_CFG 0x10f0 #define S_HINTSALLOWEDNOHDR 6 @@ -1356,6 +1648,11 @@ #define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR) #define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR) +#define S_UPCUTOFFTHRESHLP 12 +#define M_UPCUTOFFTHRESHLP 0x7ffU +#define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP) +#define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP) + #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8 #define A_SGE_PD_WRR_CONFIG 0x10fc @@ -1380,6 +1677,16 @@ #define V_ERROR_QID(x) ((x) << S_ERROR_QID) #define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID) +#define S_CAUSE_REGISTER 24 +#define M_CAUSE_REGISTER 0x7U +#define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER) +#define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER) + +#define S_CAUSE_BIT 19 +#define M_CAUSE_BIT 0x1fU +#define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT) +#define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT) + #define A_SGE_SHARED_TAG_CHAN_CFG 0x1104 #define S_MINTAG3 24 @@ -1409,6 +1716,417 @@ #define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL) #define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL) +#define A_SGE_INT_CAUSE5 0x110c + +#define S_ERR_T_RXCRC 31 +#define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC) +#define F_ERR_T_RXCRC V_ERR_T_RXCRC(1U) + +#define S_PERR_MC_RSPDATA 30 +#define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA) +#define F_PERR_MC_RSPDATA V_PERR_MC_RSPDATA(1U) + +#define S_PERR_PC_RSPDATA 29 +#define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA) +#define F_PERR_PC_RSPDATA V_PERR_PC_RSPDATA(1U) + +#define S_PERR_PD_RDRSPDATA 28 +#define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA) +#define F_PERR_PD_RDRSPDATA V_PERR_PD_RDRSPDATA(1U) + +#define S_PERR_U_RXDATA 27 +#define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA) +#define F_PERR_U_RXDATA V_PERR_U_RXDATA(1U) + +#define S_PERR_UD_RXDATA 26 +#define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA) +#define F_PERR_UD_RXDATA V_PERR_UD_RXDATA(1U) + +#define S_PERR_UP_DATA 25 +#define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA) +#define F_PERR_UP_DATA V_PERR_UP_DATA(1U) + +#define S_PERR_CIM2SGE_RXDATA 24 +#define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA) +#define F_PERR_CIM2SGE_RXDATA V_PERR_CIM2SGE_RXDATA(1U) + +#define S_PERR_HINT_DELAY_FIFO1_T5 23 +#define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5) +#define F_PERR_HINT_DELAY_FIFO1_T5 V_PERR_HINT_DELAY_FIFO1_T5(1U) + +#define S_PERR_HINT_DELAY_FIFO0_T5 22 +#define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5) +#define F_PERR_HINT_DELAY_FIFO0_T5 V_PERR_HINT_DELAY_FIFO0_T5(1U) + +#define S_PERR_IMSG_PD_FIFO_T5 21 +#define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5) +#define F_PERR_IMSG_PD_FIFO_T5 V_PERR_IMSG_PD_FIFO_T5(1U) + +#define S_PERR_ULPTX_FIFO1_T5 20 +#define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5) +#define F_PERR_ULPTX_FIFO1_T5 V_PERR_ULPTX_FIFO1_T5(1U) + +#define S_PERR_ULPTX_FIFO0_T5 19 +#define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5) +#define F_PERR_ULPTX_FIFO0_T5 V_PERR_ULPTX_FIFO0_T5(1U) + +#define S_PERR_IDMA2IMSG_FIFO1_T5 18 +#define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5) +#define F_PERR_IDMA2IMSG_FIFO1_T5 V_PERR_IDMA2IMSG_FIFO1_T5(1U) + +#define S_PERR_IDMA2IMSG_FIFO0_T5 17 +#define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5) +#define F_PERR_IDMA2IMSG_FIFO0_T5 V_PERR_IDMA2IMSG_FIFO0_T5(1U) + +#define S_PERR_POINTER_DATA_FIFO0 16 +#define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0) +#define F_PERR_POINTER_DATA_FIFO0 V_PERR_POINTER_DATA_FIFO0(1U) + +#define S_PERR_POINTER_DATA_FIFO1 15 +#define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1) +#define F_PERR_POINTER_DATA_FIFO1 V_PERR_POINTER_DATA_FIFO1(1U) + +#define S_PERR_POINTER_HDR_FIFO0 14 +#define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0) +#define F_PERR_POINTER_HDR_FIFO0 V_PERR_POINTER_HDR_FIFO0(1U) + +#define S_PERR_POINTER_HDR_FIFO1 13 +#define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1) +#define F_PERR_POINTER_HDR_FIFO1 V_PERR_POINTER_HDR_FIFO1(1U) + +#define S_PERR_PAYLOAD_FIFO0 12 +#define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0) +#define F_PERR_PAYLOAD_FIFO0 V_PERR_PAYLOAD_FIFO0(1U) + +#define S_PERR_PAYLOAD_FIFO1 11 +#define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1) +#define F_PERR_PAYLOAD_FIFO1 V_PERR_PAYLOAD_FIFO1(1U) + +#define S_PERR_EDMA_INPUT_FIFO3 10 +#define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3) +#define F_PERR_EDMA_INPUT_FIFO3 V_PERR_EDMA_INPUT_FIFO3(1U) + +#define S_PERR_EDMA_INPUT_FIFO2 9 +#define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2) +#define F_PERR_EDMA_INPUT_FIFO2 V_PERR_EDMA_INPUT_FIFO2(1U) + +#define S_PERR_EDMA_INPUT_FIFO1 8 +#define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1) +#define F_PERR_EDMA_INPUT_FIFO1 V_PERR_EDMA_INPUT_FIFO1(1U) + +#define S_PERR_EDMA_INPUT_FIFO0 7 +#define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0) +#define F_PERR_EDMA_INPUT_FIFO0 V_PERR_EDMA_INPUT_FIFO0(1U) + +#define S_PERR_MGT_BAR2_FIFO 6 +#define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO) +#define F_PERR_MGT_BAR2_FIFO V_PERR_MGT_BAR2_FIFO(1U) + +#define S_PERR_HEADERSPLIT_FIFO1_T5 5 +#define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5) +#define F_PERR_HEADERSPLIT_FIFO1_T5 V_PERR_HEADERSPLIT_FIFO1_T5(1U) + +#define S_PERR_HEADERSPLIT_FIFO0_T5 4 +#define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5) +#define F_PERR_HEADERSPLIT_FIFO0_T5 V_PERR_HEADERSPLIT_FIFO0_T5(1U) + +#define S_PERR_CIM_FIFO1 3 +#define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1) +#define F_PERR_CIM_FIFO1 V_PERR_CIM_FIFO1(1U) + +#define S_PERR_CIM_FIFO0 2 +#define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0) +#define F_PERR_CIM_FIFO0 V_PERR_CIM_FIFO0(1U) + +#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1 1 +#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) \ + ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1) +#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1 V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U) + +#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0 0 +#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) \ + ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0) +#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0 V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U) + +#define A_SGE_INT_ENABLE5 0x1110 +#define A_SGE_PERR_ENABLE5 0x1114 +#define A_SGE_DBFIFO_STATUS2 0x1118 + +#define S_FL_INT_THRESH 24 +#define M_FL_INT_THRESH 0xfU +#define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH) +#define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH) + +#define S_FL_COUNT 14 +#define M_FL_COUNT 0x3ffU +#define V_FL_COUNT(x) ((x) << S_FL_COUNT) +#define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT) + +#define S_HP_INT_THRESH_T5 10 +#define M_HP_INT_THRESH_T5 0xfU +#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5) +#define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5) + +#define S_HP_COUNT_T5 0 +#define M_HP_COUNT_T5 0x3ffU +#define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5) +#define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5) + +#define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c + +#define S_FETCHBURSTMAX0 16 +#define M_FETCHBURSTMAX0 0x3ffU +#define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0) +#define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0) + +#define S_FETCHBURSTMAX1 0 +#define M_FETCHBURSTMAX1 0x3ffU +#define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1) +#define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1) + +#define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120 + +#define S_FETCHBURSTMAX2 16 +#define M_FETCHBURSTMAX2 0x3ffU +#define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2) +#define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2) + +#define S_FETCHBURSTMAX3 0 +#define M_FETCHBURSTMAX3 0x3ffU +#define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3) +#define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3) + +#define A_SGE_CONTROL2 0x1124 + +#define S_UPFLCUTOFFDIS 21 +#define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS) +#define F_UPFLCUTOFFDIS V_UPFLCUTOFFDIS(1U) + +#define S_RXCPLSIZEAUTOCORRECT 20 +#define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT) +#define F_RXCPLSIZEAUTOCORRECT V_RXCPLSIZEAUTOCORRECT(1U) + +#define S_IDMAARBROUNDROBIN 19 +#define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN) +#define F_IDMAARBROUNDROBIN V_IDMAARBROUNDROBIN(1U) + +#define S_INGPACKBOUNDARY 16 +#define M_INGPACKBOUNDARY 0x7U +#define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY) +#define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY) + +#define S_CGEN_EGRESS_CONTEXT 15 +#define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT) +#define F_CGEN_EGRESS_CONTEXT V_CGEN_EGRESS_CONTEXT(1U) + +#define S_CGEN_INGRESS_CONTEXT 14 +#define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT) +#define F_CGEN_INGRESS_CONTEXT V_CGEN_INGRESS_CONTEXT(1U) + +#define S_CGEN_IDMA 13 +#define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA) +#define F_CGEN_IDMA V_CGEN_IDMA(1U) + +#define S_CGEN_DBP 12 +#define V_CGEN_DBP(x) ((x) << S_CGEN_DBP) +#define F_CGEN_DBP V_CGEN_DBP(1U) + +#define S_CGEN_EDMA 11 +#define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA) +#define F_CGEN_EDMA V_CGEN_EDMA(1U) + +#define S_VFIFO_ENABLE 10 +#define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE) +#define F_VFIFO_ENABLE V_VFIFO_ENABLE(1U) + +#define S_FLM_RESCHEDULE_MODE 9 +#define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE) +#define F_FLM_RESCHEDULE_MODE V_FLM_RESCHEDULE_MODE(1U) + +#define S_HINTDEPTHCTLFL 4 +#define M_HINTDEPTHCTLFL 0x1fU +#define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL) +#define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL) + +#define S_FORCE_ORDERING 3 +#define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING) +#define F_FORCE_ORDERING V_FORCE_ORDERING(1U) + +#define S_TX_COALESCE_SIZE 2 +#define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE) +#define F_TX_COALESCE_SIZE V_TX_COALESCE_SIZE(1U) + +#define S_COAL_STRICT_CIM_PRI 1 +#define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI) +#define F_COAL_STRICT_CIM_PRI V_COAL_STRICT_CIM_PRI(1U) + +#define S_TX_COALESCE_PRI 0 +#define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI) +#define F_TX_COALESCE_PRI V_TX_COALESCE_PRI(1U) + +#define A_SGE_DEEP_SLEEP 0x1128 + +#define S_IDMA1_SLEEP_STATUS 11 +#define V_IDMA1_SLEEP_STATUS(x) ((x) << S_IDMA1_SLEEP_STATUS) +#define F_IDMA1_SLEEP_STATUS V_IDMA1_SLEEP_STATUS(1U) + +#define S_IDMA0_SLEEP_STATUS 10 +#define V_IDMA0_SLEEP_STATUS(x) ((x) << S_IDMA0_SLEEP_STATUS) +#define F_IDMA0_SLEEP_STATUS V_IDMA0_SLEEP_STATUS(1U) + +#define S_IDMA1_SLEEP_REQ 9 +#define V_IDMA1_SLEEP_REQ(x) ((x) << S_IDMA1_SLEEP_REQ) +#define F_IDMA1_SLEEP_REQ V_IDMA1_SLEEP_REQ(1U) + +#define S_IDMA0_SLEEP_REQ 8 +#define V_IDMA0_SLEEP_REQ(x) ((x) << S_IDMA0_SLEEP_REQ) +#define F_IDMA0_SLEEP_REQ V_IDMA0_SLEEP_REQ(1U) + +#define S_EDMA3_SLEEP_STATUS 7 +#define V_EDMA3_SLEEP_STATUS(x) ((x) << S_EDMA3_SLEEP_STATUS) +#define F_EDMA3_SLEEP_STATUS V_EDMA3_SLEEP_STATUS(1U) + +#define S_EDMA2_SLEEP_STATUS 6 +#define V_EDMA2_SLEEP_STATUS(x) ((x) << S_EDMA2_SLEEP_STATUS) +#define F_EDMA2_SLEEP_STATUS V_EDMA2_SLEEP_STATUS(1U) + +#define S_EDMA1_SLEEP_STATUS 5 +#define V_EDMA1_SLEEP_STATUS(x) ((x) << S_EDMA1_SLEEP_STATUS) +#define F_EDMA1_SLEEP_STATUS V_EDMA1_SLEEP_STATUS(1U) + +#define S_EDMA0_SLEEP_STATUS 4 +#define V_EDMA0_SLEEP_STATUS(x) ((x) << S_EDMA0_SLEEP_STATUS) +#define F_EDMA0_SLEEP_STATUS V_EDMA0_SLEEP_STATUS(1U) + +#define S_EDMA3_SLEEP_REQ 3 +#define V_EDMA3_SLEEP_REQ(x) ((x) << S_EDMA3_SLEEP_REQ) +#define F_EDMA3_SLEEP_REQ V_EDMA3_SLEEP_REQ(1U) + +#define S_EDMA2_SLEEP_REQ 2 +#define V_EDMA2_SLEEP_REQ(x) ((x) << S_EDMA2_SLEEP_REQ) +#define F_EDMA2_SLEEP_REQ V_EDMA2_SLEEP_REQ(1U) + +#define S_EDMA1_SLEEP_REQ 1 +#define V_EDMA1_SLEEP_REQ(x) ((x) << S_EDMA1_SLEEP_REQ) +#define F_EDMA1_SLEEP_REQ V_EDMA1_SLEEP_REQ(1U) + +#define S_EDMA0_SLEEP_REQ 0 +#define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ) +#define F_EDMA0_SLEEP_REQ V_EDMA0_SLEEP_REQ(1U) + +#define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c + +#define S_THROTTLE_THRESHOLD_FL 16 +#define M_THROTTLE_THRESHOLD_FL 0xfU +#define V_THROTTLE_THRESHOLD_FL(x) ((x) << S_THROTTLE_THRESHOLD_FL) +#define G_THROTTLE_THRESHOLD_FL(x) \ + (((x) >> S_THROTTLE_THRESHOLD_FL) & M_THROTTLE_THRESHOLD_FL) + +#define S_THROTTLE_THRESHOLD_HP 12 +#define M_THROTTLE_THRESHOLD_HP 0xfU +#define V_THROTTLE_THRESHOLD_HP(x) ((x) << S_THROTTLE_THRESHOLD_HP) +#define G_THROTTLE_THRESHOLD_HP(x) \ + (((x) >> S_THROTTLE_THRESHOLD_HP) & M_THROTTLE_THRESHOLD_HP) + +#define S_THROTTLE_THRESHOLD_LP 0 +#define M_THROTTLE_THRESHOLD_LP 0xfffU +#define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP) +#define G_THROTTLE_THRESHOLD_LP(x) \ + (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP) + +#define A_SGE_DBP_FETCH_THRESHOLD 0x1130 + +#define S_DBP_FETCH_THRESHOLD_FL 21 +#define M_DBP_FETCH_THRESHOLD_FL 0xfU +#define V_DBP_FETCH_THRESHOLD_FL(x) ((x) << S_DBP_FETCH_THRESHOLD_FL) +#define G_DBP_FETCH_THRESHOLD_FL(x) \ + (((x) >> S_DBP_FETCH_THRESHOLD_FL) & M_DBP_FETCH_THRESHOLD_FL) + +#define S_DBP_FETCH_THRESHOLD_HP 17 +#define M_DBP_FETCH_THRESHOLD_HP 0xfU +#define V_DBP_FETCH_THRESHOLD_HP(x) ((x) << S_DBP_FETCH_THRESHOLD_HP) +#define G_DBP_FETCH_THRESHOLD_HP(x) \ + (((x) >> S_DBP_FETCH_THRESHOLD_HP) & M_DBP_FETCH_THRESHOLD_HP) + +#define S_DBP_FETCH_THRESHOLD_LP 5 +#define M_DBP_FETCH_THRESHOLD_LP 0xfffU +#define V_DBP_FETCH_THRESHOLD_LP(x) ((x) << S_DBP_FETCH_THRESHOLD_LP) +#define G_DBP_FETCH_THRESHOLD_LP(x) \ + (((x) >> S_DBP_FETCH_THRESHOLD_LP) & M_DBP_FETCH_THRESHOLD_LP) + +#define S_DBP_FETCH_THRESHOLD_MODE 4 +#define V_DBP_FETCH_THRESHOLD_MODE(x) ((x) << S_DBP_FETCH_THRESHOLD_MODE) +#define F_DBP_FETCH_THRESHOLD_MODE V_DBP_FETCH_THRESHOLD_MODE(1U) + +#define S_DBP_FETCH_THRESHOLD_EN3 3 +#define V_DBP_FETCH_THRESHOLD_EN3(x) ((x) << S_DBP_FETCH_THRESHOLD_EN3) +#define F_DBP_FETCH_THRESHOLD_EN3 V_DBP_FETCH_THRESHOLD_EN3(1U) + +#define S_DBP_FETCH_THRESHOLD_EN2 2 +#define V_DBP_FETCH_THRESHOLD_EN2(x) ((x) << S_DBP_FETCH_THRESHOLD_EN2) +#define F_DBP_FETCH_THRESHOLD_EN2 V_DBP_FETCH_THRESHOLD_EN2(1U) + +#define S_DBP_FETCH_THRESHOLD_EN1 1 +#define V_DBP_FETCH_THRESHOLD_EN1(x) ((x) << S_DBP_FETCH_THRESHOLD_EN1) +#define F_DBP_FETCH_THRESHOLD_EN1 V_DBP_FETCH_THRESHOLD_EN1(1U) + +#define S_DBP_FETCH_THRESHOLD_EN0 0 +#define V_DBP_FETCH_THRESHOLD_EN0(x) ((x) << S_DBP_FETCH_THRESHOLD_EN0) +#define F_DBP_FETCH_THRESHOLD_EN0 V_DBP_FETCH_THRESHOLD_EN0(1U) + +#define A_SGE_DBP_FETCH_THRESHOLD_QUEUE 0x1134 + +#define S_DBP_FETCH_THRESHOLD_IQ1 16 +#define M_DBP_FETCH_THRESHOLD_IQ1 0xffffU +#define V_DBP_FETCH_THRESHOLD_IQ1(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ1) +#define G_DBP_FETCH_THRESHOLD_IQ1(x) \ + (((x) >> S_DBP_FETCH_THRESHOLD_IQ1) & M_DBP_FETCH_THRESHOLD_IQ1) + +#define S_DBP_FETCH_THRESHOLD_IQ0 0 +#define M_DBP_FETCH_THRESHOLD_IQ0 0xffffU +#define V_DBP_FETCH_THRESHOLD_IQ0(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ0) +#define G_DBP_FETCH_THRESHOLD_IQ0(x) \ + (((x) >> S_DBP_FETCH_THRESHOLD_IQ0) & M_DBP_FETCH_THRESHOLD_IQ0) + +#define A_SGE_DBVFIFO_BADDR 0x1138 +#define A_SGE_DBVFIFO_SIZE 0x113c + +#define S_DBVFIFO_SIZE 6 +#define M_DBVFIFO_SIZE 0xfffU +#define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE) +#define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE) + +#define A_SGE_DBFIFO_STATUS3 0x1140 + +#define S_LP_PTRS_EQUAL 21 +#define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL) +#define F_LP_PTRS_EQUAL V_LP_PTRS_EQUAL(1U) + +#define S_LP_SNAPHOT 20 +#define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT) +#define F_LP_SNAPHOT V_LP_SNAPHOT(1U) + +#define S_FL_INT_THRESH_LOW 16 +#define M_FL_INT_THRESH_LOW 0xfU +#define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW) +#define G_FL_INT_THRESH_LOW(x) \ + (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW) + +#define S_HP_INT_THRESH_LOW 12 +#define M_HP_INT_THRESH_LOW 0xfU +#define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW) +#define G_HP_INT_THRESH_LOW(x) \ + (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW) + +#define S_LP_INT_THRESH_LOW 0 +#define M_LP_INT_THRESH_LOW 0xfffU +#define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW) +#define G_LP_INT_THRESH_LOW(x) \ + (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW) + +#define A_SGE_CHANGESET 0x1144 +#define A_SGE_PC_RSP_ERROR 0x1148 + #define A_SGE_PC0_REQ_BIST_CMD 0x1180 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184 #define A_SGE_PC1_REQ_BIST_CMD 0x1190 @@ -1454,6 +2172,1051 @@ #define A_SGE_CTXT_MASK5 0x1234 #define A_SGE_CTXT_MASK6 0x1238 #define A_SGE_CTXT_MASK7 0x123c +#define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280 + +#define S_CIM_WM 24 +#define M_CIM_WM 0x3U +#define V_CIM_WM(x) ((x) << S_CIM_WM) +#define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM) + +#define S_DEBUG_UP_SOP_CNT 20 +#define M_DEBUG_UP_SOP_CNT 0xfU +#define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT) +#define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT) + +#define S_DEBUG_UP_EOP_CNT 16 +#define M_DEBUG_UP_EOP_CNT 0xfU +#define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT) +#define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT) + +#define S_DEBUG_CIM_SOP1_CNT 12 +#define M_DEBUG_CIM_SOP1_CNT 0xfU +#define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT) +#define G_DEBUG_CIM_SOP1_CNT(x) \ + (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT) + +#define S_DEBUG_CIM_EOP1_CNT 8 +#define M_DEBUG_CIM_EOP1_CNT 0xfU +#define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT) +#define G_DEBUG_CIM_EOP1_CNT(x) \ + (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT) + +#define S_DEBUG_CIM_SOP0_CNT 4 +#define M_DEBUG_CIM_SOP0_CNT 0xfU +#define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT) +#define G_DEBUG_CIM_SOP0_CNT(x) \ + (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT) + +#define S_DEBUG_CIM_EOP0_CNT 0 +#define M_DEBUG_CIM_EOP0_CNT 0xfU +#define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT) +#define G_DEBUG_CIM_EOP0_CNT(x) \ + (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284 + +#define S_DEBUG_T_RX_SOP1_CNT 28 +#define M_DEBUG_T_RX_SOP1_CNT 0xfU +#define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT) +#define G_DEBUG_T_RX_SOP1_CNT(x) \ + (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT) + +#define S_DEBUG_T_RX_EOP1_CNT 24 +#define M_DEBUG_T_RX_EOP1_CNT 0xfU +#define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT) +#define G_DEBUG_T_RX_EOP1_CNT(x) \ + (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT) + +#define S_DEBUG_T_RX_SOP0_CNT 20 +#define M_DEBUG_T_RX_SOP0_CNT 0xfU +#define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT) +#define G_DEBUG_T_RX_SOP0_CNT(x) \ + (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT) + +#define S_DEBUG_T_RX_EOP0_CNT 16 +#define M_DEBUG_T_RX_EOP0_CNT 0xfU +#define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT) +#define G_DEBUG_T_RX_EOP0_CNT(x) \ + (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT) + +#define S_DEBUG_U_RX_SOP1_CNT 12 +#define M_DEBUG_U_RX_SOP1_CNT 0xfU +#define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT) +#define G_DEBUG_U_RX_SOP1_CNT(x) \ + (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT) + +#define S_DEBUG_U_RX_EOP1_CNT 8 +#define M_DEBUG_U_RX_EOP1_CNT 0xfU +#define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT) +#define G_DEBUG_U_RX_EOP1_CNT(x) \ + (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT) + +#define S_DEBUG_U_RX_SOP0_CNT 4 +#define M_DEBUG_U_RX_SOP0_CNT 0xfU +#define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT) +#define G_DEBUG_U_RX_SOP0_CNT(x) \ + (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT) + +#define S_DEBUG_U_RX_EOP0_CNT 0 +#define M_DEBUG_U_RX_EOP0_CNT 0xfU +#define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT) +#define G_DEBUG_U_RX_EOP0_CNT(x) \ + (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288 + +#define S_DEBUG_UD_RX_SOP3_CNT 28 +#define M_DEBUG_UD_RX_SOP3_CNT 0xfU +#define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT) +#define G_DEBUG_UD_RX_SOP3_CNT(x) \ + (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT) + +#define S_DEBUG_UD_RX_EOP3_CNT 24 +#define M_DEBUG_UD_RX_EOP3_CNT 0xfU +#define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT) +#define G_DEBUG_UD_RX_EOP3_CNT(x) \ + (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT) + +#define S_DEBUG_UD_RX_SOP2_CNT 20 +#define M_DEBUG_UD_RX_SOP2_CNT 0xfU +#define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT) +#define G_DEBUG_UD_RX_SOP2_CNT(x) \ + (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT) + +#define S_DEBUG_UD_RX_EOP2_CNT 16 +#define M_DEBUG_UD_RX_EOP2_CNT 0xfU +#define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT) +#define G_DEBUG_UD_RX_EOP2_CNT(x) \ + (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT) + +#define S_DEBUG_UD_RX_SOP1_CNT 12 +#define M_DEBUG_UD_RX_SOP1_CNT 0xfU +#define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT) +#define G_DEBUG_UD_RX_SOP1_CNT(x) \ + (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT) + +#define S_DEBUG_UD_RX_EOP1_CNT 8 +#define M_DEBUG_UD_RX_EOP1_CNT 0xfU +#define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT) +#define G_DEBUG_UD_RX_EOP1_CNT(x) \ + (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT) + +#define S_DEBUG_UD_RX_SOP0_CNT 4 +#define M_DEBUG_UD_RX_SOP0_CNT 0xfU +#define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT) +#define G_DEBUG_UD_RX_SOP0_CNT(x) \ + (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT) + +#define S_DEBUG_UD_RX_EOP0_CNT 0 +#define M_DEBUG_UD_RX_EOP0_CNT 0xfU +#define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT) +#define G_DEBUG_UD_RX_EOP0_CNT(x) \ + (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c + +#define S_DEBUG_U_TX_SOP3_CNT 28 +#define M_DEBUG_U_TX_SOP3_CNT 0xfU +#define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT) +#define G_DEBUG_U_TX_SOP3_CNT(x) \ + (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT) + +#define S_DEBUG_U_TX_EOP3_CNT 24 +#define M_DEBUG_U_TX_EOP3_CNT 0xfU +#define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT) +#define G_DEBUG_U_TX_EOP3_CNT(x) \ + (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT) + +#define S_DEBUG_U_TX_SOP2_CNT 20 +#define M_DEBUG_U_TX_SOP2_CNT 0xfU +#define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT) +#define G_DEBUG_U_TX_SOP2_CNT(x) \ + (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT) + +#define S_DEBUG_U_TX_EOP2_CNT 16 +#define M_DEBUG_U_TX_EOP2_CNT 0xfU +#define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT) +#define G_DEBUG_U_TX_EOP2_CNT(x) \ + (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT) + +#define S_DEBUG_U_TX_SOP1_CNT 12 +#define M_DEBUG_U_TX_SOP1_CNT 0xfU +#define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT) +#define G_DEBUG_U_TX_SOP1_CNT(x) \ + (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT) + +#define S_DEBUG_U_TX_EOP1_CNT 8 +#define M_DEBUG_U_TX_EOP1_CNT 0xfU +#define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT) +#define G_DEBUG_U_TX_EOP1_CNT(x) \ + (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT) + +#define S_DEBUG_U_TX_SOP0_CNT 4 +#define M_DEBUG_U_TX_SOP0_CNT 0xfU +#define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT) +#define G_DEBUG_U_TX_SOP0_CNT(x) \ + (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT) + +#define S_DEBUG_U_TX_EOP0_CNT 0 +#define M_DEBUG_U_TX_EOP0_CNT 0xfU +#define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT) +#define G_DEBUG_U_TX_EOP0_CNT(x) \ + (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290 + +#define S_DEBUG_PC_RSP_SOP1_CNT 28 +#define M_DEBUG_PC_RSP_SOP1_CNT 0xfU +#define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT) +#define G_DEBUG_PC_RSP_SOP1_CNT(x) \ + (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT) + +#define S_DEBUG_PC_RSP_EOP1_CNT 24 +#define M_DEBUG_PC_RSP_EOP1_CNT 0xfU +#define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT) +#define G_DEBUG_PC_RSP_EOP1_CNT(x) \ + (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT) + +#define S_DEBUG_PC_RSP_SOP0_CNT 20 +#define M_DEBUG_PC_RSP_SOP0_CNT 0xfU +#define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT) +#define G_DEBUG_PC_RSP_SOP0_CNT(x) \ + (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT) + +#define S_DEBUG_PC_RSP_EOP0_CNT 16 +#define M_DEBUG_PC_RSP_EOP0_CNT 0xfU +#define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT) +#define G_DEBUG_PC_RSP_EOP0_CNT(x) \ + (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT) + +#define S_DEBUG_PC_REQ_SOP1_CNT 12 +#define M_DEBUG_PC_REQ_SOP1_CNT 0xfU +#define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT) +#define G_DEBUG_PC_REQ_SOP1_CNT(x) \ + (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT) + +#define S_DEBUG_PC_REQ_EOP1_CNT 8 +#define M_DEBUG_PC_REQ_EOP1_CNT 0xfU +#define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT) +#define G_DEBUG_PC_REQ_EOP1_CNT(x) \ + (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT) + +#define S_DEBUG_PC_REQ_SOP0_CNT 4 +#define M_DEBUG_PC_REQ_SOP0_CNT 0xfU +#define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT) +#define G_DEBUG_PC_REQ_SOP0_CNT(x) \ + (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT) + +#define S_DEBUG_PC_REQ_EOP0_CNT 0 +#define M_DEBUG_PC_REQ_EOP0_CNT 0xfU +#define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT) +#define G_DEBUG_PC_REQ_EOP0_CNT(x) \ + (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294 + +#define S_DEBUG_PD_RDREQ_SOP3_CNT 28 +#define M_DEBUG_PD_RDREQ_SOP3_CNT 0xfU +#define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT) +#define G_DEBUG_PD_RDREQ_SOP3_CNT(x) \ + (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT) + +#define S_DEBUG_PD_RDREQ_EOP3_CNT 24 +#define M_DEBUG_PD_RDREQ_EOP3_CNT 0xfU +#define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT) +#define G_DEBUG_PD_RDREQ_EOP3_CNT(x) \ + (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT) + +#define S_DEBUG_PD_RDREQ_SOP2_CNT 20 +#define M_DEBUG_PD_RDREQ_SOP2_CNT 0xfU +#define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT) +#define G_DEBUG_PD_RDREQ_SOP2_CNT(x) \ + (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT) + +#define S_DEBUG_PD_RDREQ_EOP2_CNT 16 +#define M_DEBUG_PD_RDREQ_EOP2_CNT 0xfU +#define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT) +#define G_DEBUG_PD_RDREQ_EOP2_CNT(x) \ + (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT) + +#define S_DEBUG_PD_RDREQ_SOP1_CNT 12 +#define M_DEBUG_PD_RDREQ_SOP1_CNT 0xfU +#define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT) +#define G_DEBUG_PD_RDREQ_SOP1_CNT(x) \ +(((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT) + +#define S_DEBUG_PD_RDREQ_EOP1_CNT 8 +#define M_DEBUG_PD_RDREQ_EOP1_CNT 0xfU +#define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT) +#define G_DEBUG_PD_RDREQ_EOP1_CNT(x) \ + (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT) + +#define S_DEBUG_PD_RDREQ_SOP0_CNT 4 +#define M_DEBUG_PD_RDREQ_SOP0_CNT 0xfU +#define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT) +#define G_DEBUG_PD_RDREQ_SOP0_CNT(x) \ + (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT) + +#define S_DEBUG_PD_RDREQ_EOP0_CNT 0 +#define M_DEBUG_PD_RDREQ_EOP0_CNT 0xfU +#define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT) +#define G_DEBUG_PD_RDREQ_EOP0_CNT(x) \ + (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298 + +#define S_DEBUG_PD_RDRSP_SOP3_CNT 28 +#define M_DEBUG_PD_RDRSP_SOP3_CNT 0xfU +#define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT) +#define G_DEBUG_PD_RDRSP_SOP3_CNT(x) \ + (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT) + +#define S_DEBUG_PD_RDRSP_EOP3_CNT 24 +#define M_DEBUG_PD_RDRSP_EOP3_CNT 0xfU +#define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT) +#define G_DEBUG_PD_RDRSP_EOP3_CNT(x) \ + (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT) + +#define S_DEBUG_PD_RDRSP_SOP2_CNT 20 +#define M_DEBUG_PD_RDRSP_SOP2_CNT 0xfU +#define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT) +#define G_DEBUG_PD_RDRSP_SOP2_CNT(x) \ + (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT) + +#define S_DEBUG_PD_RDRSP_EOP2_CNT 16 +#define M_DEBUG_PD_RDRSP_EOP2_CNT 0xfU +#define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT) +#define G_DEBUG_PD_RDRSP_EOP2_CNT(x) \ + (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT) + +#define S_DEBUG_PD_RDRSP_SOP1_CNT 12 +#define M_DEBUG_PD_RDRSP_SOP1_CNT 0xfU +#define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT) +#define G_DEBUG_PD_RDRSP_SOP1_CNT(x) \ + (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT) + +#define S_DEBUG_PD_RDRSP_EOP1_CNT 8 +#define M_DEBUG_PD_RDRSP_EOP1_CNT 0xfU +#define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT) +#define G_DEBUG_PD_RDRSP_EOP1_CNT(x) \ + (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT) + +#define S_DEBUG_PD_RDRSP_SOP0_CNT 4 +#define M_DEBUG_PD_RDRSP_SOP0_CNT 0xfU +#define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT) +#define G_DEBUG_PD_RDRSP_SOP0_CNT(x) \ + (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT) + +#define S_DEBUG_PD_RDRSP_EOP0_CNT 0 +#define M_DEBUG_PD_RDRSP_EOP0_CNT 0xfU +#define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT) +#define G_DEBUG_PD_RDRSP_EOP0_CNT(x) \ + (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c + +#define S_DEBUG_PD_WRREQ_SOP3_CNT 28 +#define M_DEBUG_PD_WRREQ_SOP3_CNT 0xfU +#define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT) +#define G_DEBUG_PD_WRREQ_SOP3_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT) + +#define S_DEBUG_PD_WRREQ_EOP3_CNT 24 +#define M_DEBUG_PD_WRREQ_EOP3_CNT 0xfU +#define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT) +#define G_DEBUG_PD_WRREQ_EOP3_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT) + +#define S_DEBUG_PD_WRREQ_SOP2_CNT 20 +#define M_DEBUG_PD_WRREQ_SOP2_CNT 0xfU +#define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT) +#define G_DEBUG_PD_WRREQ_SOP2_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT) + +#define S_DEBUG_PD_WRREQ_EOP2_CNT 16 +#define M_DEBUG_PD_WRREQ_EOP2_CNT 0xfU +#define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT) +#define G_DEBUG_PD_WRREQ_EOP2_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT) + +#define S_DEBUG_PD_WRREQ_SOP1_CNT 12 +#define M_DEBUG_PD_WRREQ_SOP1_CNT 0xfU +#define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT) +#define G_DEBUG_PD_WRREQ_SOP1_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT) + +#define S_DEBUG_PD_WRREQ_EOP1_CNT 8 +#define M_DEBUG_PD_WRREQ_EOP1_CNT 0xfU +#define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT) +#define G_DEBUG_PD_WRREQ_EOP1_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT) + +#define S_DEBUG_PD_WRREQ_SOP0_CNT 4 +#define M_DEBUG_PD_WRREQ_SOP0_CNT 0xfU +#define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT) +#define G_DEBUG_PD_WRREQ_SOP0_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT) + +#define S_DEBUG_PD_WRREQ_EOP0_CNT 0 +#define M_DEBUG_PD_WRREQ_EOP0_CNT 0xfU +#define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT) +#define G_DEBUG_PD_WRREQ_EOP0_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0 + +#define S_GLOBALENABLE_OFF 29 +#define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF) +#define F_GLOBALENABLE_OFF V_GLOBALENABLE_OFF(1U) + +#define S_DEBUG_CIM2SGE_RXAFULL_D 27 +#define M_DEBUG_CIM2SGE_RXAFULL_D 0x3U +#define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D) +#define G_DEBUG_CIM2SGE_RXAFULL_D(x) \ + (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D) + +#define S_DEBUG_CPLSW_CIM_TXAFULL_D 25 +#define M_DEBUG_CPLSW_CIM_TXAFULL_D 0x3U +#define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D) +#define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) \ + (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D) + +#define S_DEBUG_UP_FULL 24 +#define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL) +#define F_DEBUG_UP_FULL V_DEBUG_UP_FULL(1U) + +#define S_DEBUG_M_RD_REQ_OUTSTANDING_PC 23 +#define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) \ + ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC) +#define F_DEBUG_M_RD_REQ_OUTSTANDING_PC V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U) + +#define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO 22 +#define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) \ + ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO) +#define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO \ + V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U) + +#define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG 21 +#define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) \ + ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG) +#define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U) + +#define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB 20 +#define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) \ + ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB) +#define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB \ + V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U) + +#define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM 19 +#define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) \ + ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM) +#define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U) + +#define S_DEBUG_M_REQVLD 18 +#define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD) +#define F_DEBUG_M_REQVLD V_DEBUG_M_REQVLD(1U) + +#define S_DEBUG_M_REQRDY 17 +#define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY) +#define F_DEBUG_M_REQRDY V_DEBUG_M_REQRDY(1U) + +#define S_DEBUG_M_RSPVLD 16 +#define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD) +#define F_DEBUG_M_RSPVLD V_DEBUG_M_RSPVLD(1U) + +#define S_DEBUG_PD_WRREQ_INT3_CNT 12 +#define M_DEBUG_PD_WRREQ_INT3_CNT 0xfU +#define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT) +#define G_DEBUG_PD_WRREQ_INT3_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT) + +#define S_DEBUG_PD_WRREQ_INT2_CNT 8 +#define M_DEBUG_PD_WRREQ_INT2_CNT 0xfU +#define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT) +#define G_DEBUG_PD_WRREQ_INT2_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT) + +#define S_DEBUG_PD_WRREQ_INT1_CNT 4 +#define M_DEBUG_PD_WRREQ_INT1_CNT 0xfU +#define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT) +#define G_DEBUG_PD_WRREQ_INT1_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT) + +#define S_DEBUG_PD_WRREQ_INT0_CNT 0 +#define M_DEBUG_PD_WRREQ_INT0_CNT 0xfU +#define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT) +#define G_DEBUG_PD_WRREQ_INT0_CNT(x) \ + (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4 + +#define S_DEBUG_CPLSW_TP_RX_SOP1_CNT 28 +#define M_DEBUG_CPLSW_TP_RX_SOP1_CNT 0xfU +#define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT) +#define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT) + +#define S_DEBUG_CPLSW_TP_RX_EOP1_CNT 24 +#define M_DEBUG_CPLSW_TP_RX_EOP1_CNT 0xfU +#define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT) +#define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT) + +#define S_DEBUG_CPLSW_TP_RX_SOP0_CNT 20 +#define M_DEBUG_CPLSW_TP_RX_SOP0_CNT 0xfU +#define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT) +#define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT) + +#define S_DEBUG_CPLSW_TP_RX_EOP0_CNT 16 +#define M_DEBUG_CPLSW_TP_RX_EOP0_CNT 0xfU +#define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT) +#define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT) + +#define S_DEBUG_CPLSW_CIM_SOP1_CNT 12 +#define M_DEBUG_CPLSW_CIM_SOP1_CNT 0xfU +#define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT) +#define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT) + +#define S_DEBUG_CPLSW_CIM_EOP1_CNT 8 +#define M_DEBUG_CPLSW_CIM_EOP1_CNT 0xfU +#define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT) +#define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT) + +#define S_DEBUG_CPLSW_CIM_SOP0_CNT 4 +#define M_DEBUG_CPLSW_CIM_SOP0_CNT 0xfU +#define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT) +#define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT) + +#define S_DEBUG_CPLSW_CIM_EOP0_CNT 0 +#define M_DEBUG_CPLSW_CIM_EOP0_CNT 0xfU +#define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT) +#define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8 + +#define S_DEBUG_T_RXAFULL_D 30 +#define M_DEBUG_T_RXAFULL_D 0x3U +#define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D) +#define G_DEBUG_T_RXAFULL_D(x) \ + (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D) + +#define S_DEBUG_PD_RDRSPAFULL_D 26 +#define M_DEBUG_PD_RDRSPAFULL_D 0xfU +#define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D) +#define G_DEBUG_PD_RDRSPAFULL_D(x) \ + (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D) + +#define S_DEBUG_PD_RDREQAFULL_D 22 +#define M_DEBUG_PD_RDREQAFULL_D 0xfU +#define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D) +#define G_DEBUG_PD_RDREQAFULL_D(x) \ + (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D) + +#define S_DEBUG_PD_WRREQAFULL_D 18 +#define M_DEBUG_PD_WRREQAFULL_D 0xfU +#define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D) +#define G_DEBUG_PD_WRREQAFULL_D(x) \ + (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D) + +#define S_DEBUG_PC_RSPAFULL_D 15 +#define M_DEBUG_PC_RSPAFULL_D 0x7U +#define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D) +#define G_DEBUG_PC_RSPAFULL_D(x) \ + (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D) + +#define S_DEBUG_PC_REQAFULL_D 12 +#define M_DEBUG_PC_REQAFULL_D 0x7U +#define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D) +#define G_DEBUG_PC_REQAFULL_D(x) \ + (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D) + +#define S_DEBUG_U_TXAFULL_D 8 +#define M_DEBUG_U_TXAFULL_D 0xfU +#define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D) +#define G_DEBUG_U_TXAFULL_D(x) \ + (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D) + +#define S_DEBUG_UD_RXAFULL_D 4 +#define M_DEBUG_UD_RXAFULL_D 0xfU +#define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D) +#define G_DEBUG_UD_RXAFULL_D(x) \ + (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D) + +#define S_DEBUG_U_RXAFULL_D 2 +#define M_DEBUG_U_RXAFULL_D 0x3U +#define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D) +#define G_DEBUG_U_RXAFULL_D(x) \ + (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D) + +#define S_DEBUG_CIM_AFULL_D 0 +#define M_DEBUG_CIM_AFULL_D 0x3U +#define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D) +#define G_DEBUG_CIM_AFULL_D(x) \ + (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac + +#define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE 24 +#define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) \ + ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE) +#define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE \ + V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE 23 +#define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) \ + ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE) +#define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE \ + V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE 22 +#define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) \ + ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE) +#define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE \ + V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE 21 +#define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) \ + ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE) +#define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U) + +#define S_DEBUG_ST_FLM_IDMA1_CACHE 19 +#define M_DEBUG_ST_FLM_IDMA1_CACHE 0x3U +#define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE) +#define G_DEBUG_ST_FLM_IDMA1_CACHE(x) \ + (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE) + +#define S_DEBUG_ST_FLM_IDMA1_CTXT 16 +#define M_DEBUG_ST_FLM_IDMA1_CTXT 0x7U +#define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT) +#define G_DEBUG_ST_FLM_IDMA1_CTXT(x) \ + (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT) + +#define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE 8 +#define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) \ + ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE) +#define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE \ + V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE 7 +#define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) \ + ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE) +#define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE \ + V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE 6 +#define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) \ + ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE) +#define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE \ + V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U) + +#define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE 5 +#define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) \ + ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE) +#define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U) + +#define S_DEBUG_ST_FLM_IDMA0_CACHE 3 +#define M_DEBUG_ST_FLM_IDMA0_CACHE 0x3U +#define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE) +#define G_DEBUG_ST_FLM_IDMA0_CACHE(x) \ + (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE) + +#define S_DEBUG_ST_FLM_IDMA0_CTXT 0 +#define M_DEBUG_ST_FLM_IDMA0_CTXT 0x7U +#define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT) +#define G_DEBUG_ST_FLM_IDMA0_CTXT(x) \ + (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0 + +#define S_DEBUG_CPLSW_SOP1_CNT 28 +#define M_DEBUG_CPLSW_SOP1_CNT 0xfU +#define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT) +#define G_DEBUG_CPLSW_SOP1_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT) + +#define S_DEBUG_CPLSW_EOP1_CNT 24 +#define M_DEBUG_CPLSW_EOP1_CNT 0xfU +#define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT) +#define G_DEBUG_CPLSW_EOP1_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT) + +#define S_DEBUG_CPLSW_SOP0_CNT 20 +#define M_DEBUG_CPLSW_SOP0_CNT 0xfU +#define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT) +#define G_DEBUG_CPLSW_SOP0_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT) + +#define S_DEBUG_CPLSW_EOP0_CNT 16 +#define M_DEBUG_CPLSW_EOP0_CNT 0xfU +#define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT) +#define G_DEBUG_CPLSW_EOP0_CNT(x) \ + (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT) + +#define S_DEBUG_PC_RSP_SOP2_CNT 12 +#define M_DEBUG_PC_RSP_SOP2_CNT 0xfU +#define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT) +#define G_DEBUG_PC_RSP_SOP2_CNT(x) \ + (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT) + +#define S_DEBUG_PC_RSP_EOP2_CNT 8 +#define M_DEBUG_PC_RSP_EOP2_CNT 0xfU +#define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT) +#define G_DEBUG_PC_RSP_EOP2_CNT(x) \ + (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT) + +#define S_DEBUG_PC_REQ_SOP2_CNT 4 +#define M_DEBUG_PC_REQ_SOP2_CNT 0xfU +#define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT) +#define G_DEBUG_PC_REQ_SOP2_CNT(x) \ + (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT) + +#define S_DEBUG_PC_REQ_EOP2_CNT 0 +#define M_DEBUG_PC_REQ_EOP2_CNT 0xfU +#define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT) +#define G_DEBUG_PC_REQ_EOP2_CNT(x) \ + (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT) + +#define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4 +#define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8 +#define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc +#define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0 + +#define S_DEBUG_ST_IDMA1_FLM_REQ 29 +#define M_DEBUG_ST_IDMA1_FLM_REQ 0x7U +#define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ) +#define G_DEBUG_ST_IDMA1_FLM_REQ(x) \ + (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ) + +#define S_DEBUG_ST_IDMA0_FLM_REQ 26 +#define M_DEBUG_ST_IDMA0_FLM_REQ 0x7U +#define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ) +#define G_DEBUG_ST_IDMA0_FLM_REQ(x) \ + (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ) + +#define S_DEBUG_ST_IMSG_CTXT 23 +#define M_DEBUG_ST_IMSG_CTXT 0x7U +#define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT) +#define G_DEBUG_ST_IMSG_CTXT(x) \ + (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT) + +#define S_DEBUG_ST_IMSG 18 +#define M_DEBUG_ST_IMSG 0x1fU +#define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG) +#define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG) + +#define S_DEBUG_ST_IDMA1_IALN 16 +#define M_DEBUG_ST_IDMA1_IALN 0x3U +#define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN) +#define G_DEBUG_ST_IDMA1_IALN(x) \ + (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN) + +#define S_DEBUG_ST_IDMA1_IDMA_SM 9 +#define M_DEBUG_ST_IDMA1_IDMA_SM 0x3fU +#define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM) +#define G_DEBUG_ST_IDMA1_IDMA_SM(x) \ + (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM) + +#define S_DEBUG_ST_IDMA0_IALN 7 +#define M_DEBUG_ST_IDMA0_IALN 0x3U +#define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN) +#define G_DEBUG_ST_IDMA0_IALN(x) \ + (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN) + +#define S_DEBUG_ST_IDMA0_IDMA_SM 0 +#define M_DEBUG_ST_IDMA0_IDMA_SM 0x3fU +#define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM) +#define G_DEBUG_ST_IDMA0_IDMA_SM(x) \ + (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4 + +#define S_DEBUG_ITP_EMPTY 12 +#define M_DEBUG_ITP_EMPTY 0x3fU +#define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY) +#define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY) + +#define S_DEBUG_ITP_EXPIRED 6 +#define M_DEBUG_ITP_EXPIRED 0x3fU +#define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED) +#define G_DEBUG_ITP_EXPIRED(x) \ + (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED) + +#define S_DEBUG_ITP_PAUSE 5 +#define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE) +#define F_DEBUG_ITP_PAUSE V_DEBUG_ITP_PAUSE(1U) + +#define S_DEBUG_ITP_DEL_DONE 4 +#define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE) +#define F_DEBUG_ITP_DEL_DONE V_DEBUG_ITP_DEL_DONE(1U) + +#define S_DEBUG_ITP_ADD_DONE 3 +#define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE) +#define F_DEBUG_ITP_ADD_DONE V_DEBUG_ITP_ADD_DONE(1U) + +#define S_DEBUG_ITP_EVR_STATE 0 +#define M_DEBUG_ITP_EVR_STATE 0x7U +#define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE) +#define G_DEBUG_ITP_EVR_STATE(x) \ + (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8 + +#define S_DEBUG_ST_DBP_THREAD2_CIMFL 25 +#define M_DEBUG_ST_DBP_THREAD2_CIMFL 0x1fU +#define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL) +#define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) \ + (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL) + +#define S_DEBUG_ST_DBP_THREAD2_MAIN 20 +#define M_DEBUG_ST_DBP_THREAD2_MAIN 0x1fU +#define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN) +#define G_DEBUG_ST_DBP_THREAD2_MAIN(x) \ + (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN) + +#define S_DEBUG_ST_DBP_THREAD1_CIMFL 15 +#define M_DEBUG_ST_DBP_THREAD1_CIMFL 0x1fU +#define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL) +#define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) \ + (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL) + +#define S_DEBUG_ST_DBP_THREAD1_MAIN 10 +#define M_DEBUG_ST_DBP_THREAD1_MAIN 0x1fU +#define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN) +#define G_DEBUG_ST_DBP_THREAD1_MAIN(x) \ + (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN) + +#define S_DEBUG_ST_DBP_THREAD0_CIMFL 5 +#define M_DEBUG_ST_DBP_THREAD0_CIMFL 0x1fU +#define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL) +#define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) \ + (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL) + +#define S_DEBUG_ST_DBP_THREAD0_MAIN 0 +#define M_DEBUG_ST_DBP_THREAD0_MAIN 0x1fU +#define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN) +#define G_DEBUG_ST_DBP_THREAD0_MAIN(x) \ + (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc + +#define S_DEBUG_ST_DBP_UPCP_MAIN 14 +#define M_DEBUG_ST_DBP_UPCP_MAIN 0x1fU +#define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN) +#define G_DEBUG_ST_DBP_UPCP_MAIN(x) \ + (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN) + +#define S_DEBUG_ST_DBP_DBFIFO_MAIN 13 +#define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN) +#define F_DEBUG_ST_DBP_DBFIFO_MAIN V_DEBUG_ST_DBP_DBFIFO_MAIN(1U) + +#define S_DEBUG_ST_DBP_CTXT 10 +#define M_DEBUG_ST_DBP_CTXT 0x7U +#define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT) +#define G_DEBUG_ST_DBP_CTXT(x) \ + (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT) + +#define S_DEBUG_ST_DBP_THREAD3_CIMFL 5 +#define M_DEBUG_ST_DBP_THREAD3_CIMFL 0x1fU +#define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL) +#define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) \ + (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL) + +#define S_DEBUG_ST_DBP_THREAD3_MAIN 0 +#define M_DEBUG_ST_DBP_THREAD3_MAIN 0x1fU +#define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN) +#define G_DEBUG_ST_DBP_THREAD3_MAIN(x) \ + (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0 + +#define S_DEBUG_ST_EDMA3_ALIGN_SUB 29 +#define M_DEBUG_ST_EDMA3_ALIGN_SUB 0x7U +#define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB) +#define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) \ + (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB) + +#define S_DEBUG_ST_EDMA3_ALIGN 27 +#define M_DEBUG_ST_EDMA3_ALIGN 0x3U +#define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN) +#define G_DEBUG_ST_EDMA3_ALIGN(x) \ + (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN) + +#define S_DEBUG_ST_EDMA3_REQ 24 +#define M_DEBUG_ST_EDMA3_REQ 0x7U +#define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ) +#define G_DEBUG_ST_EDMA3_REQ(x) \ + (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ) + +#define S_DEBUG_ST_EDMA2_ALIGN_SUB 21 +#define M_DEBUG_ST_EDMA2_ALIGN_SUB 0x7U +#define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB) +#define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) \ + (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB) + +#define S_DEBUG_ST_EDMA2_ALIGN 19 +#define M_DEBUG_ST_EDMA2_ALIGN 0x3U +#define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN) +#define G_DEBUG_ST_EDMA2_ALIGN(x) \ + (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN) + +#define S_DEBUG_ST_EDMA2_REQ 16 +#define M_DEBUG_ST_EDMA2_REQ 0x7U +#define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ) +#define G_DEBUG_ST_EDMA2_REQ(x) \ + (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ) + +#define S_DEBUG_ST_EDMA1_ALIGN_SUB 13 +#define M_DEBUG_ST_EDMA1_ALIGN_SUB 0x7U +#define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB) +#define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) \ + (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB) + +#define S_DEBUG_ST_EDMA1_ALIGN 11 +#define M_DEBUG_ST_EDMA1_ALIGN 0x3U +#define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN) +#define G_DEBUG_ST_EDMA1_ALIGN(x) \ + (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN) + +#define S_DEBUG_ST_EDMA1_REQ 8 +#define M_DEBUG_ST_EDMA1_REQ 0x7U +#define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ) +#define G_DEBUG_ST_EDMA1_REQ(x) \ + (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ) + +#define S_DEBUG_ST_EDMA0_ALIGN_SUB 5 +#define M_DEBUG_ST_EDMA0_ALIGN_SUB 0x7U +#define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB) +#define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) \ + (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB) + +#define S_DEBUG_ST_EDMA0_ALIGN 3 +#define M_DEBUG_ST_EDMA0_ALIGN 0x3U +#define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN) +#define G_DEBUG_ST_EDMA0_ALIGN(x) \ + (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN) + +#define S_DEBUG_ST_EDMA0_REQ 0 +#define M_DEBUG_ST_EDMA0_REQ 0x7U +#define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ) +#define G_DEBUG_ST_EDMA0_REQ(x) \ + (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4 + +#define S_DEBUG_ST_FLM_DBPTR 30 +#define M_DEBUG_ST_FLM_DBPTR 0x3U +#define V_DEBUG_ST_FLM_DBPTR(x) ((x) <<S_DEBUG_ST_FLM_DBPTR) +#define G_DEBUG_ST_FLM_DBPTR(x) \ + (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR) + +#define S_DEBUG_FLM_CACHE_LOCKED_COUNT 23 +#define M_DEBUG_FLM_CACHE_LOCKED_COUNT 0x7fU +#define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) \ + ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT) +#define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) \ + (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT) + +#define S_DEBUG_FLM_CACHE_AGENT 20 +#define M_DEBUG_FLM_CACHE_AGENT 0x7U +#define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT) +#define G_DEBUG_FLM_CACHE_AGENT(x) \ + (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT) + +#define S_DEBUG_ST_FLM_CACHE 16 +#define M_DEBUG_ST_FLM_CACHE 0xfU +#define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE) +#define G_DEBUG_ST_FLM_CACHE(x) \ + (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE) + +#define S_DEBUG_FLM_DBPTR_CIDX_STALL 12 +#define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL) +#define F_DEBUG_FLM_DBPTR_CIDX_STALL V_DEBUG_FLM_DBPTR_CIDX_STALL(1U) + +#define S_DEBUG_FLM_DBPTR_QID 0 +#define M_DEBUG_FLM_DBPTR_QID 0xfffU +#define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID) +#define G_DEBUG_FLM_DBPTR_QID(x) \ + (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8 + +#define S_DEBUG_DBP_THREAD0_QID 0 +#define M_DEBUG_DBP_THREAD0_QID 0x1ffffU +#define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID) +#define G_DEBUG_DBP_THREAD0_QID(x) \ + (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc + +#define S_DEBUG_DBP_THREAD1_QID 0 +#define M_DEBUG_DBP_THREAD1_QID 0x1ffffU +#define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID) +#define G_DEBUG_DBP_THREAD1_QID(x) \ + (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0 + +#define S_DEBUG_DBP_THREAD2_QID 0 +#define M_DEBUG_DBP_THREAD2_QID 0x1ffffU +#define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID) +#define G_DEBUG_DBP_THREAD2_QID(x) \ + (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4 + +#define S_DEBUG_DBP_THREAD3_QID 0 +#define M_DEBUG_DBP_THREAD3_QID 0x1ffffU +#define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID) +#define G_DEBUG_DBP_THREAD3_QID(x) \ + (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8 + +#define S_DEBUG_IMSG_CPL 16 +#define M_DEBUG_IMSG_CPL 0xffU +#define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL) +#define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL) + +#define S_DEBUG_IMSG_QID 0 +#define M_DEBUG_IMSG_QID 0xffffU +#define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID) +#define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec + +#define S_DEBUG_IDMA1_QID 16 +#define M_DEBUG_IDMA1_QID 0xffffU +#define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID) +#define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID) + +#define S_DEBUG_IDMA0_QID 0 +#define M_DEBUG_IDMA0_QID 0xffffU +#define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID) +#define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0 + +#define S_DEBUG_IDMA1_FLM_REQ_QID 16 +#define M_DEBUG_IDMA1_FLM_REQ_QID 0xffffU +#define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID) +#define G_DEBUG_IDMA1_FLM_REQ_QID(x) \ + (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID) + +#define S_DEBUG_IDMA0_FLM_REQ_QID 0 +#define M_DEBUG_IDMA0_FLM_REQ_QID 0xffffU +#define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID) +#define G_DEBUG_IDMA0_FLM_REQ_QID(x) \ + (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID) + +#define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4 +#define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8 +#define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc #define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300 #define S_EGRESS_LOG2SIZE 27 @@ -1478,6 +3241,21 @@ #define G_INGRESS1_LOG2SIZE(x) \ (((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE) +#define S_EGRESS_SIZE 27 +#define M_EGRESS_SIZE 0x1fU +#define V_EGRESS_SIZE(x) ((x) << S_EGRESS_SIZE) +#define G_EGRESS_SIZE(x) (((x) >> S_EGRESS_SIZE) & M_EGRESS_SIZE) + +#define S_INGRESS2_SIZE 5 +#define M_INGRESS2_SIZE 0x1fU +#define V_INGRESS2_SIZE(x) ((x) << S_INGRESS2_SIZE) +#define G_INGRESS2_SIZE(x) (((x) >> S_INGRESS2_SIZE) & M_INGRESS2_SIZE) + +#define S_INGRESS1_SIZE 0 +#define M_INGRESS1_SIZE 0x1fU +#define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE) +#define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE) + #define A_SGE_QUEUE_BASE_MAP_LOW 0x1304 #define S_INGRESS2_BASE 16 @@ -1731,6 +3509,94 @@ #define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR) #define F_MSIADDRLPERR V_MSIADDRLPERR(1U) +#define S_IPGRPPERR 31 +#define V_IPGRPPERR(x) ((x) << S_IPGRPPERR) +#define F_IPGRPPERR V_IPGRPPERR(1U) + +#define S_READRSPERR 29 +#define V_READRSPERR(x) ((x) << S_READRSPERR) +#define F_READRSPERR V_READRSPERR(1U) + +#define S_TRGT1GRPPERR 28 +#define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR) +#define F_TRGT1GRPPERR V_TRGT1GRPPERR(1U) + +#define S_IPSOTPERR 27 +#define V_IPSOTPERR(x) ((x) << S_IPSOTPERR) +#define F_IPSOTPERR V_IPSOTPERR(1U) + +#define S_IPRETRYPERR 26 +#define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR) +#define F_IPRETRYPERR V_IPRETRYPERR(1U) + +#define S_IPRXDATAGRPPERR 25 +#define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR) +#define F_IPRXDATAGRPPERR V_IPRXDATAGRPPERR(1U) + +#define S_IPRXHDRGRPPERR 24 +#define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR) +#define F_IPRXHDRGRPPERR V_IPRXHDRGRPPERR(1U) + +#define S_PIOTAGQPERR 23 +#define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR) +#define F_PIOTAGQPERR V_PIOTAGQPERR(1U) + +#define S_MAGRPPERR 22 +#define V_MAGRPPERR(x) ((x) << S_MAGRPPERR) +#define F_MAGRPPERR V_MAGRPPERR(1U) + +#define S_VFIDPERR 21 +#define V_VFIDPERR(x) ((x) << S_VFIDPERR) +#define F_VFIDPERR V_VFIDPERR(1U) + +#define S_HREQRDPERR 17 +#define V_HREQRDPERR(x) ((x) << S_HREQRDPERR) +#define F_HREQRDPERR V_HREQRDPERR(1U) + +#define S_HREQWRPERR 16 +#define V_HREQWRPERR(x) ((x) << S_HREQWRPERR) +#define F_HREQWRPERR V_HREQWRPERR(1U) + +#define S_DREQRDPERR 14 +#define V_DREQRDPERR(x) ((x) << S_DREQRDPERR) +#define F_DREQRDPERR V_DREQRDPERR(1U) + +#define S_DREQWRPERR 13 +#define V_DREQWRPERR(x) ((x) << S_DREQWRPERR) +#define F_DREQWRPERR V_DREQWRPERR(1U) + +#define S_CREQRDPERR 11 +#define V_CREQRDPERR(x) ((x) << S_CREQRDPERR) +#define F_CREQRDPERR V_CREQRDPERR(1U) + +#define S_MSTTAGQPERR 10 +#define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR) +#define F_MSTTAGQPERR V_MSTTAGQPERR(1U) + +#define S_TGTTAGQPERR 9 +#define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR) +#define F_TGTTAGQPERR V_TGTTAGQPERR(1U) + +#define S_PIOREQGRPPERR 8 +#define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR) +#define F_PIOREQGRPPERR V_PIOREQGRPPERR(1U) + +#define S_PIOCPLGRPPERR 7 +#define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR) +#define F_PIOCPLGRPPERR V_PIOCPLGRPPERR(1U) + +#define S_MSIXSTIPERR 2 +#define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR) +#define F_MSIXSTIPERR V_MSIXSTIPERR(1U) + +#define S_MSTTIMEOUTPERR 1 +#define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR) +#define F_MSTTIMEOUTPERR V_MSTTIMEOUTPERR(1U) + +#define S_MSTGRPPERR 0 +#define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR) +#define F_MSTGRPPERR V_MSTGRPPERR(1U) + #define A_PCIE_INT_CAUSE 0x3004 #define A_PCIE_PERR_ENABLE 0x3008 #define A_PCIE_PERR_INJECT 0x300c @@ -1781,6 +3647,90 @@ #define V_CFGSNP(x) ((x) << S_CFGSNP) #define F_CFGSNP V_CFGSNP(1U) +#define S_MAREQTIMEOUT 29 +#define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT) +#define F_MAREQTIMEOUT V_MAREQTIMEOUT(1U) + +#define S_TRGT1BARTYPEERR 28 +#define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR) +#define F_TRGT1BARTYPEERR V_TRGT1BARTYPEERR(1U) + +#define S_MAEXTRARSPERR 27 +#define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR) +#define F_MAEXTRARSPERR V_MAEXTRARSPERR(1U) + +#define S_MARSPTIMEOUT 26 +#define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT) +#define F_MARSPTIMEOUT V_MARSPTIMEOUT(1U) + +#define S_INTVFALLMSIDISERR 25 +#define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR) +#define F_INTVFALLMSIDISERR V_INTVFALLMSIDISERR(1U) + +#define S_INTVFRANGEERR 24 +#define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR) +#define F_INTVFRANGEERR V_INTVFRANGEERR(1U) + +#define S_INTPLIRSPERR 23 +#define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR) +#define F_INTPLIRSPERR V_INTPLIRSPERR(1U) + +#define S_MEMREQRDTAGERR 22 +#define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR) +#define F_MEMREQRDTAGERR V_MEMREQRDTAGERR(1U) + +#define S_CFGINITDONEERR 21 +#define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR) +#define F_CFGINITDONEERR V_CFGINITDONEERR(1U) + +#define S_BAR2TIMEOUT 20 +#define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT) +#define F_BAR2TIMEOUT V_BAR2TIMEOUT(1U) + +#define S_VPDTIMEOUT 19 +#define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT) +#define F_VPDTIMEOUT V_VPDTIMEOUT(1U) + +#define S_MEMRSPRDTAGERR 18 +#define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR) +#define F_MEMRSPRDTAGERR V_MEMRSPRDTAGERR(1U) + +#define S_MEMRSPWRTAGERR 17 +#define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR) +#define F_MEMRSPWRTAGERR V_MEMRSPWRTAGERR(1U) + +#define S_PIORSPRDTAGERR 16 +#define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR) +#define F_PIORSPRDTAGERR V_PIORSPRDTAGERR(1U) + +#define S_PIORSPWRTAGERR 15 +#define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR) +#define F_PIORSPWRTAGERR V_PIORSPWRTAGERR(1U) + +#define S_DBITIMEOUT 14 +#define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT) +#define F_DBITIMEOUT V_DBITIMEOUT(1U) + +#define S_PIOUNALINDWR 13 +#define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR) +#define F_PIOUNALINDWR V_PIOUNALINDWR(1U) + +#define S_BAR2RDERR 12 +#define V_BAR2RDERR(x) ((x) << S_BAR2RDERR) +#define F_BAR2RDERR V_BAR2RDERR(1U) + +#define S_MAWREOPERR 11 +#define V_MAWREOPERR(x) ((x) << S_MAWREOPERR) +#define F_MAWREOPERR V_MAWREOPERR(1U) + +#define S_MARDEOPERR 10 +#define V_MARDEOPERR(x) ((x) << S_MARDEOPERR) +#define F_MARDEOPERR V_MARDEOPERR(1U) + +#define S_BAR2REQ 2 +#define V_BAR2REQ(x) ((x) << S_BAR2REQ) +#define F_BAR2REQ V_BAR2REQ(1U) + #define A_PCIE_CFG 0x3014 #define S_CFGDMAXPYLDSZRX 26 @@ -1871,12 +3821,80 @@ #define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN) #define F_LINKDNRSTEN V_LINKDNRSTEN(1U) +#define S_DIAGCTRLBUS 28 +#define M_DIAGCTRLBUS 0x7U +#define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS) +#define G_DIAGCTRLBUS(x) (((x) >> S_DIAGCTRLBUS) & M_DIAGCTRLBUS) + +#define S_IPPERREN 27 +#define V_IPPERREN(x) ((x) << S_IPPERREN) +#define F_IPPERREN V_IPPERREN(1U) + +#define S_CFGDEXTTAGEN 26 +#define V_CFGDEXTTAGEN(x) ((x) << S_CFGDEXTTAGEN) +#define F_CFGDEXTTAGEN V_CFGDEXTTAGEN(1U) + +#define S_CFGDMAXPYLDSZ 23 +#define M_CFGDMAXPYLDSZ 0x7U +#define V_CFGDMAXPYLDSZ(x) ((x) << S_CFGDMAXPYLDSZ) +#define G_CFGDMAXPYLDSZ(x) (((x) >> S_CFGDMAXPYLDSZ) & M_CFGDMAXPYLDSZ) + +#define S_DCAEN 17 +#define V_DCAEN(x) ((x) << S_DCAEN) +#define F_DCAEN V_DCAEN(1U) + +#define S_T5CMDREQPRIORITY 16 +#define V_T5CMDREQPRIORITY(x) ((x) << S_T5CMDREQPRIORITY) +#define F_T5CMDREQPRIORITY V_T5CMDREQPRIORITY(1U) + +#define S_T5VPDREQPROTECT 14 +#define M_T5VPDREQPROTECT 0x3U +#define V_T5VPDREQPROTECT(x) ((x) << S_T5VPDREQPROTECT) +#define G_T5VPDREQPROTECT(x) (((x) >> S_T5VPDREQPROTECT) & M_T5VPDREQPROTECT) + +#define S_DROPPEDRDRSPDATA 12 +#define V_DROPPEDRDRSPDATA(x) ((x) << S_DROPPEDRDRSPDATA) +#define F_DROPPEDRDRSPDATA V_DROPPEDRDRSPDATA(1U) + +#define S_AI_INTX_REASSERTEN 11 +#define V_AI_INTX_REASSERTEN(x) ((x) << S_AI_INTX_REASSERTEN) +#define F_AI_INTX_REASSERTEN V_AI_INTX_REASSERTEN(1U) + +#define S_AUTOTXNDISABLE 10 +#define V_AUTOTXNDISABLE(x) ((x) << S_AUTOTXNDISABLE) +#define F_AUTOTXNDISABLE V_AUTOTXNDISABLE(1U) + +#define S_LINKREQRSTPCIECRSTMODE 3 +#define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE) +#define F_LINKREQRSTPCIECRSTMODE V_LINKREQRSTPCIECRSTMODE(1U) + #define A_PCIE_DMA_CTRL 0x3018 #define S_LITTLEENDIAN 7 #define V_LITTLEENDIAN(x) ((x) << S_LITTLEENDIAN) #define F_LITTLEENDIAN V_LITTLEENDIAN(1U) +#define A_PCIE_CFG2 0x3018 + +#define S_VPDTIMER 16 +#define M_VPDTIMER 0xffffU +#define V_VPDTIMER(x) ((x) << S_VPDTIMER) +#define G_VPDTIMER(x) (((x) >> S_VPDTIMER) & M_VPDTIMER) + +#define S_BAR2TIMER 4 +#define M_BAR2TIMER 0xfffU +#define V_BAR2TIMER(x) ((x) << S_BAR2TIMER) +#define G_BAR2TIMER(x) (((x) >> S_BAR2TIMER) & M_BAR2TIMER) + +#define S_MSTREQRDRRASIMPLE 3 +#define V_MSTREQRDRRASIMPLE(x) ((x) << S_MSTREQRDRRASIMPLE) +#define F_MSTREQRDRRASIMPLE V_MSTREQRDRRASIMPLE(1U) + +#define S_TOTMAXTAG 0 +#define M_TOTMAXTAG 0x3U +#define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG) +#define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG) + #define A_PCIE_DMA_CFG 0x301c #define S_MAXPYLDSIZE 28 @@ -1904,6 +3922,29 @@ #define V_MAXTAG(x) ((x) << S_MAXTAG) #define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG) +#define A_PCIE_CFG3 0x301c + +#define S_AUTOPIOCOOKIEMATCH 6 +#define V_AUTOPIOCOOKIEMATCH(x) ((x) << S_AUTOPIOCOOKIEMATCH) +#define F_AUTOPIOCOOKIEMATCH V_AUTOPIOCOOKIEMATCH(1U) + +#define S_FLRPNDCPLMODE 4 +#define M_FLRPNDCPLMODE 0x3U +#define V_FLRPNDCPLMODE(x) ((x) << S_FLRPNDCPLMODE) +#define G_FLRPNDCPLMODE(x) (((x) >> S_FLRPNDCPLMODE) & M_FLRPNDCPLMODE) + +#define S_HMADCASTFIRSTONLY 2 +#define V_HMADCASTFIRSTONLY(x) ((x) << S_HMADCASTFIRSTONLY) +#define F_HMADCASTFIRSTONLY V_HMADCASTFIRSTONLY(1U) + +#define S_CMDDCASTFIRSTONLY 1 +#define V_CMDDCASTFIRSTONLY(x) ((x) << S_CMDDCASTFIRSTONLY) +#define F_CMDDCASTFIRSTONLY V_CMDDCASTFIRSTONLY(1U) + +#define S_DMADCASTFIRSTONLY 0 +#define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY) +#define F_DMADCASTFIRSTONLY V_DMADCASTFIRSTONLY(1U) + #define A_PCIE_DMA_STAT 0x3020 #define S_STATEREQ 28 @@ -1930,6 +3971,60 @@ #define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT) #define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT) +#define A_PCIE_CFG4 0x3020 + +#define S_L1CLKREMOVALEN 17 +#define V_L1CLKREMOVALEN(x) ((x) << S_L1CLKREMOVALEN) +#define F_L1CLKREMOVALEN V_L1CLKREMOVALEN(1U) + +#define S_READYENTERL23 16 +#define V_READYENTERL23(x) ((x) << S_READYENTERL23) +#define F_READYENTERL23 V_READYENTERL23(1U) + +#define S_EXITL1 12 +#define V_EXITL1(x) ((x) << S_EXITL1) +#define F_EXITL1 V_EXITL1(1U) + +#define S_ENTERL1 8 +#define V_ENTERL1(x) ((x) << S_ENTERL1) +#define F_ENTERL1 V_ENTERL1(1U) + +#define S_GENPME 0 +#define M_GENPME 0xffU +#define V_GENPME(x) ((x) << S_GENPME) +#define G_GENPME(x) (((x) >> S_GENPME) & M_GENPME) + +#define A_PCIE_CFG5 0x3024 + +#define S_ENABLESKPPARITYFIX 2 +#define V_ENABLESKPPARITYFIX(x) ((x) << S_ENABLESKPPARITYFIX) +#define F_ENABLESKPPARITYFIX V_ENABLESKPPARITYFIX(1U) + +#define S_ENABLEL2ENTRYINL1 1 +#define V_ENABLEL2ENTRYINL1(x) ((x) << S_ENABLEL2ENTRYINL1) +#define F_ENABLEL2ENTRYINL1 V_ENABLEL2ENTRYINL1(1U) + +#define S_HOLDCPLENTERINGL1 0 +#define V_HOLDCPLENTERINGL1(x) ((x) << S_HOLDCPLENTERINGL1) +#define F_HOLDCPLENTERINGL1 V_HOLDCPLENTERINGL1(1U) + +#define A_PCIE_CFG6 0x3028 + +#define S_PERSTTIMERCOUNT 12 +#define M_PERSTTIMERCOUNT 0x3fffU +#define V_PERSTTIMERCOUNT(x) ((x) << S_PERSTTIMERCOUNT) +#define G_PERSTTIMERCOUNT(x) (((x) >> S_PERSTTIMERCOUNT) & M_PERSTTIMERCOUNT) + +#define S_PERSTTIMEOUT 8 +#define V_PERSTTIMEOUT(x) ((x) << S_PERSTTIMEOUT) +#define F_PERSTTIMEOUT V_PERSTTIMEOUT(1U) + +#define S_PERSTTIMER 0 +#define M_PERSTTIMER 0xfU +#define V_PERSTTIMER(x) ((x) << S_PERSTTIMER) +#define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER) + + #define A_PCIE_CMD_CTRL 0x303c #define A_PCIE_CMD_CFG 0x3040 @@ -2044,6 +4139,29 @@ #define V_REGISTER(x) ((x) << S_REGISTER) #define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER) +#define S_CS2 28 +#define V_CS2(x) ((x) << S_CS2) +#define F_CS2 V_CS2(1U) + +#define S_WRBE 24 +#define M_WRBE 0xfU +#define V_WRBE(x) ((x) << S_WRBE) +#define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE) + +#define S_CFG_SPACE_VFVLD 23 +#define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD) +#define F_CFG_SPACE_VFVLD V_CFG_SPACE_VFVLD(1U) + +#define S_CFG_SPACE_RVF 16 +#define M_CFG_SPACE_RVF 0x7fU +#define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF) +#define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF) + +#define S_CFG_SPACE_PF 12 +#define M_CFG_SPACE_PF 0x7U +#define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF) +#define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF) + #define A_PCIE_CFG_SPACE_DATA 0x3064 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068 @@ -2063,6 +4181,12 @@ #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW) #define A_PCIE_MEM_ACCESS_OFFSET 0x306c + +#define S_MEMOFST 7 +#define M_MEMOFST 0x1ffffffU +#define V_MEMOFST(x) ((x) << S_MEMOFST) +#define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST) + #define A_PCIE_MAILBOX_BASE_WIN 0x30a8 #define S_MBOXPCIEOFST 6 @@ -2116,6 +4240,16 @@ #define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG) #define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG) +#define S_T5_MA_MAXREQCNT 16 +#define M_T5_MA_MAXREQCNT 0x7fU +#define V_T5_MA_MAXREQCNT(x) ((x) << S_T5_MA_MAXREQCNT) +#define G_T5_MA_MAXREQCNT(x) (((x) >> S_T5_MA_MAXREQCNT) & M_T5_MA_MAXREQCNT) + +#define S_MA_MAXREQSIZE 8 +#define M_MA_MAXREQSIZE 0x7U +#define V_MA_MAXREQSIZE(x) ((x) << S_MA_MAXREQSIZE) +#define G_MA_MAXREQSIZE(x) (((x) >> S_MA_MAXREQSIZE) & M_MA_MAXREQSIZE) + #define A_PCIE_MA_SYNC 0x30b4 #define A_PCIE_FW 0x30b8 #define A_PCIE_FW_PF 0x30bc @@ -2125,6 +4259,14 @@ #define V_PIOPAUSEDONE(x) ((x) << S_PIOPAUSEDONE) #define F_PIOPAUSEDONE V_PIOPAUSEDONE(1U) +#define S_MSTPAUSEDONE 30 +#define V_MSTPAUSEDONE(x) ((x) << S_MSTPAUSEDONE) +#define F_MSTPAUSEDONE V_MSTPAUSEDONE(1U) + +#define S_MSTPAUSE 1 +#define V_MSTPAUSE(x) ((x) << S_MSTPAUSE) +#define F_MSTPAUSE V_MSTPAUSE(1U) + #define S_PIOPAUSETIME 4 #define M_PIOPAUSETIME 0xffffffU #define V_PIOPAUSETIME(x) ((x) << S_PIOPAUSETIME) @@ -2135,6 +4277,7 @@ #define F_PIOPAUSE V_PIOPAUSE(1U) #define A_PCIE_SYS_CFG_READY 0x30e0 +#define A_PCIE_MA_STAT 0x30e0 #define A_PCIE_STATIC_CFG1 0x30e4 #define S_LINKDOWN_RESET_EN 26 @@ -2190,6 +4333,22 @@ #define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE) #define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE) +#define S_AUXPOWER_DETECTED 27 +#define V_AUXPOWER_DETECTED(x) ((x) << S_AUXPOWER_DETECTED) +#define F_AUXPOWER_DETECTED V_AUXPOWER_DETECTED(1U) + +#define A_PCIE_STATIC_CFG2 0x30e8 + +#define S_PL_CONTROL 16 +#define M_PL_CONTROL 0xffffU +#define V_PL_CONTROL(x) ((x) << S_PL_CONTROL) +#define G_PL_CONTROL(x) (((x) >> S_PL_CONTROL) & M_PL_CONTROL) + +#define S_STATIC_SPARE3 0 +#define M_STATIC_SPARE3 0x3fffU +#define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3) +#define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3) + #define A_PCIE_DBG_INDIR_REQ 0x30ec #define S_DBGENABLE 31 @@ -2264,6 +4423,75 @@ #define V_PFNUM(x) ((x) << S_PFNUM) #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM) +#define A_PCIE_PF_INT_CFG 0x3140 +#define A_PCIE_PF_INT_CFG2 0x3144 +#define A_PCIE_VF_INT_CFG 0x3180 +#define A_PCIE_VF_INT_CFG2 0x3184 +#define A_PCIE_PF_MSI_EN 0x35a8 + +#define S_PFMSIEN_7_0 0 +#define M_PFMSIEN_7_0 0xffU +#define V_PFMSIEN_7_0(x) ((x) << S_PFMSIEN_7_0) +#define G_PFMSIEN_7_0(x) (((x) >> S_PFMSIEN_7_0) & M_PFMSIEN_7_0) + +#define A_PCIE_VF_MSI_EN_0 0x35ac +#define A_PCIE_VF_MSI_EN_1 0x35b0 +#define A_PCIE_VF_MSI_EN_2 0x35b4 +#define A_PCIE_VF_MSI_EN_3 0x35b8 +#define A_PCIE_PF_MSIX_EN 0x35bc + +#define S_PFMSIXEN_7_0 0 +#define M_PFMSIXEN_7_0 0xffU +#define V_PFMSIXEN_7_0(x) ((x) << S_PFMSIXEN_7_0) +#define G_PFMSIXEN_7_0(x) (((x) >> S_PFMSIXEN_7_0) & M_PFMSIXEN_7_0) + +#define A_PCIE_VF_MSIX_EN_0 0x35c0 +#define A_PCIE_VF_MSIX_EN_1 0x35c4 +#define A_PCIE_VF_MSIX_EN_2 0x35c8 +#define A_PCIE_VF_MSIX_EN_3 0x35cc +#define A_PCIE_FID_VFID_SEL 0x35ec + +#define S_FID_VFID_SEL_SELECT 0 +#define M_FID_VFID_SEL_SELECT 0x3U +#define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT) +#define G_FID_VFID_SEL_SELECT(x) \ + (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT) + +#define A_PCIE_FID_VFID 0x3600 + +#define S_FID_VFID_SELECT 30 +#define M_FID_VFID_SELECT 0x3U +#define V_FID_VFID_SELECT(x) ((x) << S_FID_VFID_SELECT) +#define G_FID_VFID_SELECT(x) (((x) >> S_FID_VFID_SELECT) & M_FID_VFID_SELECT) + +#define S_IDO 24 +#define V_IDO(x) ((x) << S_IDO) +#define F_IDO V_IDO(1U) + +#define S_FID_VFID_VFID 16 +#define M_FID_VFID_VFID 0xffU +#define V_FID_VFID_VFID(x) ((x) << S_FID_VFID_VFID) +#define G_FID_VFID_VFID(x) (((x) >> S_FID_VFID_VFID) & M_FID_VFID_VFID) + +#define S_FID_VFID_TC 11 +#define M_FID_VFID_TC 0x7U +#define V_FID_VFID_TC(x) ((x) << S_FID_VFID_TC) +#define G_FID_VFID_TC(x) (((x) >> S_FID_VFID_TC) & M_FID_VFID_TC) + +#define S_FID_VFID_VFVLD 10 +#define V_FID_VFID_VFVLD(x) ((x) << S_FID_VFID_VFVLD) +#define F_FID_VFID_VFVLD V_FID_VFID_VFVLD(1U) + +#define S_FID_VFID_PF 7 +#define M_FID_VFID_PF 0x7U +#define V_FID_VFID_PF(x) ((x) << S_FID_VFID_PF) +#define G_FID_VFID_PF(x) (((x) >> S_FID_VFID_PF) & M_FID_VFID_PF) + +#define S_FID_VFID_RVF 0 +#define M_FID_VFID_RVF 0x7fU +#define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF) +#define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF) + #define A_PCIE_FID 0x3900 #define S_PAD 11 @@ -2280,6 +4508,716 @@ #define V_FUNC(x) ((x) << S_FUNC) #define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC) +#define A_PCIE_COOKIE_STAT 0x5600 + +#define S_COOKIEB 16 +#define M_COOKIEB 0x3ffU +#define V_COOKIEB(x) ((x) << S_COOKIEB) +#define G_COOKIEB(x) (((x) >> S_COOKIEB) & M_COOKIEB) + +#define S_COOKIEA 0 +#define M_COOKIEA 0x3ffU +#define V_COOKIEA(x) ((x) << S_COOKIEA) +#define G_COOKIEA(x) (((x) >> S_COOKIEA) & M_COOKIEA) + +#define A_PCIE_FLR_PIO 0x5620 + +#define S_RCVDBAR2COOKIE 24 +#define M_RCVDBAR2COOKIE 0xffU +#define V_RCVDBAR2COOKIE(x) ((x) << S_RCVDBAR2COOKIE) +#define G_RCVDBAR2COOKIE(x) (((x) >> S_RCVDBAR2COOKIE) & M_RCVDBAR2COOKIE) + +#define S_RCVDMARSPCOOKIE 16 +#define M_RCVDMARSPCOOKIE 0xffU +#define V_RCVDMARSPCOOKIE(x) ((x) << S_RCVDMARSPCOOKIE) +#define G_RCVDMARSPCOOKIE(x) (((x) >> S_RCVDMARSPCOOKIE) & M_RCVDMARSPCOOKIE) + +#define S_RCVDPIORSPCOOKIE 8 +#define M_RCVDPIORSPCOOKIE 0xffU +#define V_RCVDPIORSPCOOKIE(x) ((x) << S_RCVDPIORSPCOOKIE) +#define G_RCVDPIORSPCOOKIE(x) (((x) >> S_RCVDPIORSPCOOKIE) & M_RCVDPIORSPCOOKIE) + +#define S_EXPDCOOKIE 0 +#define M_EXPDCOOKIE 0xffU +#define V_EXPDCOOKIE(x) ((x) << S_EXPDCOOKIE) +#define G_EXPDCOOKIE(x) (((x) >> S_EXPDCOOKIE) & M_EXPDCOOKIE) + +#define A_PCIE_FLR_PIO2 0x5624 + +#define S_RCVDMAREQCOOKIE 16 +#define M_RCVDMAREQCOOKIE 0xffU +#define V_RCVDMAREQCOOKIE(x) ((x) << S_RCVDMAREQCOOKIE) +#define G_RCVDMAREQCOOKIE(x) (((x) >> S_RCVDMAREQCOOKIE) & M_RCVDMAREQCOOKIE) + +#define S_RCVDPIOREQCOOKIE 8 +#define M_RCVDPIOREQCOOKIE 0xffU +#define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE) +#define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE) + +#define A_PCIE_VC0_CDTS0 0x56cc + +#define S_CPLD0 20 +#define M_CPLD0 0xfffU +#define V_CPLD0(x) ((x) << S_CPLD0) +#define G_CPLD0(x) (((x) >> S_CPLD0) & M_CPLD0) + +#define S_PH0 12 +#define M_PH0 0xffU +#define V_PH0(x) ((x) << S_PH0) +#define G_PH0(x) (((x) >> S_PH0) & M_PH0) + +#define S_PD0 0 +#define M_PD0 0xfffU +#define V_PD0(x) ((x) << S_PD0) +#define G_PD0(x) (((x) >> S_PD0) & M_PD0) + +#define A_PCIE_VC0_CDTS1 0x56d0 + +#define S_CPLH0 20 +#define M_CPLH0 0xffU +#define V_CPLH0(x) ((x) << S_CPLH0) +#define G_CPLH0(x) (((x) >> S_CPLH0) & M_CPLH0) + +#define S_NPH0 12 +#define M_NPH0 0xffU +#define V_NPH0(x) ((x) << S_NPH0) +#define G_NPH0(x) (((x) >> S_NPH0) & M_NPH0) + +#define S_NPD0 0 +#define M_NPD0 0xfffU +#define V_NPD0(x) ((x) << S_NPD0) +#define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0) + +#define A_PCIE_VC1_CDTS0 0x56d4 + +#define S_CPLD1 20 +#define M_CPLD1 0xfffU +#define V_CPLD1(x) ((x) << S_CPLD1) +#define G_CPLD1(x) (((x) >> S_CPLD1) & M_CPLD1) + +#define S_PH1 12 +#define M_PH1 0xffU +#define V_PH1(x) ((x) << S_PH1) +#define G_PH1(x) (((x) >> S_PH1) & M_PH1) + +#define S_PD1 0 +#define M_PD1 0xfffU +#define V_PD1(x) ((x) << S_PD1) +#define G_PD1(x) (((x) >> S_PD1) & M_PD1) + +#define A_PCIE_VC1_CDTS1 0x56d8 + +#define S_CPLH1 20 +#define M_CPLH1 0xffU +#define V_CPLH1(x) ((x) << S_CPLH1) +#define G_CPLH1(x) (((x) >> S_CPLH1) & M_CPLH1) + +#define S_NPH1 12 +#define M_NPH1 0xffU +#define V_NPH1(x) ((x) << S_NPH1) +#define G_NPH1(x) (((x) >> S_NPH1) & M_NPH1) + +#define S_NPD1 0 +#define M_NPD1 0xfffU +#define V_NPD1(x) ((x) << S_NPD1) +#define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1) + +#define A_PCIE_FLR_PF_STATUS 0x56dc +#define A_PCIE_FLR_VF0_STATUS 0x56e0 +#define A_PCIE_FLR_VF1_STATUS 0x56e4 +#define A_PCIE_FLR_VF2_STATUS 0x56e8 +#define A_PCIE_FLR_VF3_STATUS 0x56ec +#define A_PCIE_STAT 0x56f4 + +#define S_PM_STATUS 24 +#define M_PM_STATUS 0xffU +#define V_PM_STATUS(x) ((x) << S_PM_STATUS) +#define G_PM_STATUS(x) (((x) >> S_PM_STATUS) & M_PM_STATUS) + +#define S_PM_CURRENTSTATE 20 +#define M_PM_CURRENTSTATE 0x7U +#define V_PM_CURRENTSTATE(x) ((x) << S_PM_CURRENTSTATE) +#define G_PM_CURRENTSTATE(x) (((x) >> S_PM_CURRENTSTATE) & M_PM_CURRENTSTATE) + +#define S_LTSSMENABLE 12 +#define V_LTSSMENABLE(x) ((x) << S_LTSSMENABLE) +#define F_LTSSMENABLE V_LTSSMENABLE(1U) + +#define S_STATECFGINITF 4 +#define M_STATECFGINITF 0x7fU +#define V_STATECFGINITF(x) ((x) << S_STATECFGINITF) +#define G_STATECFGINITF(x) (((x) >> S_STATECFGINITF) & M_STATECFGINITF) + +#define S_STATECFGINIT 0 +#define M_STATECFGINIT 0xfU +#define V_STATECFGINIT(x) ((x) << S_STATECFGINIT) +#define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT) + +#define A_PCIE_CRS 0x56f8 + +#define S_CRS_ENABLE 0 +#define V_CRS_ENABLE(x) ((x) << S_CRS_ENABLE) +#define F_CRS_ENABLE V_CRS_ENABLE(1U) + +#define A_PCIE_LTSSM 0x56fc + +#define S_LTSSM_ENABLE 0 +#define V_LTSSM_ENABLE(x) ((x) << S_LTSSM_ENABLE) +#define F_LTSSM_ENABLE V_LTSSM_ENABLE(1U) + +#define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700 + +#define S_REPLAY_TIME_LIMIT 16 +#define M_REPLAY_TIME_LIMIT 0xffffU +#define V_REPLAY_TIME_LIMIT(x) ((x) << S_REPLAY_TIME_LIMIT) +#define G_REPLAY_TIME_LIMIT(x) \ + (((x) >> S_REPLAY_TIME_LIMIT) & M_REPLAY_TIME_LIMIT) + +#define S_ACK_LATENCY_TIMER_LIMIT 0 +#define M_ACK_LATENCY_TIMER_LIMIT 0xffffU +#define V_ACK_LATENCY_TIMER_LIMIT(x) ((x) << S_ACK_LATENCY_TIMER_LIMIT) +#define G_ACK_LATENCY_TIMER_LIMIT(x) \ + (((x) >> S_ACK_LATENCY_TIMER_LIMIT) & M_ACK_LATENCY_TIMER_LIMIT) + +#define A_PCIE_CORE_VENDOR_SPECIFIC_DLLP 0x5704 +#define A_PCIE_CORE_PORT_FORCE_LINK 0x5708 + +#define S_LOW_POWER_ENTRANCE_COUNT 24 +#define M_LOW_POWER_ENTRANCE_COUNT 0xffU +#define V_LOW_POWER_ENTRANCE_COUNT(x) ((x) << S_LOW_POWER_ENTRANCE_COUNT) +#define G_LOW_POWER_ENTRANCE_COUNT(x) \ + (((x) >> S_LOW_POWER_ENTRANCE_COUNT) & M_LOW_POWER_ENTRANCE_COUNT) + +#define S_LINK_STATE 16 +#define M_LINK_STATE 0x3fU +#define V_LINK_STATE(x) ((x) << S_LINK_STATE) +#define G_LINK_STATE(x) (((x) >> S_LINK_STATE) & M_LINK_STATE) + +#define S_FORCE_LINK 15 +#define V_FORCE_LINK(x) ((x) << S_FORCE_LINK) +#define F_FORCE_LINK V_FORCE_LINK(1U) + +#define S_LINK_NUMBER 0 +#define M_LINK_NUMBER 0xffU +#define V_LINK_NUMBER(x) ((x) << S_LINK_NUMBER) +#define G_LINK_NUMBER(x) (((x) >> S_LINK_NUMBER) & M_LINK_NUMBER) + +#define A_PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x570c + +#define S_ENTER_ASPM_L1_WO_L0S 30 +#define V_ENTER_ASPM_L1_WO_L0S(x) ((x) << S_ENTER_ASPM_L1_WO_L0S) +#define F_ENTER_ASPM_L1_WO_L0S V_ENTER_ASPM_L1_WO_L0S(1U) + +#define S_L1_ENTRANCE_LATENCY 27 +#define M_L1_ENTRANCE_LATENCY 0x7U +#define V_L1_ENTRANCE_LATENCY(x) ((x) << S_L1_ENTRANCE_LATENCY) +#define G_L1_ENTRANCE_LATENCY(x) \ + (((x) >> S_L1_ENTRANCE_LATENCY) & M_L1_ENTRANCE_LATENCY) + +#define S_L0S_ENTRANCE_LATENCY 24 +#define M_L0S_ENTRANCE_LATENCY 0x7U +#define V_L0S_ENTRANCE_LATENCY(x) ((x) << S_L0S_ENTRANCE_LATENCY) +#define G_L0S_ENTRANCE_LATENCY(x) \ + (((x) >> S_L0S_ENTRANCE_LATENCY) & M_L0S_ENTRANCE_LATENCY) + +#define S_COMMON_CLOCK_N_FTS 16 +#define M_COMMON_CLOCK_N_FTS 0xffU +#define V_COMMON_CLOCK_N_FTS(x) ((x) << S_COMMON_CLOCK_N_FTS) +#define G_COMMON_CLOCK_N_FTS(x) \ + (((x) >> S_COMMON_CLOCK_N_FTS) & M_COMMON_CLOCK_N_FTS) + +#define S_N_FTS 8 +#define M_N_FTS 0xffU +#define V_N_FTS(x) ((x) << S_N_FTS) +#define G_N_FTS(x) (((x) >> S_N_FTS) & M_N_FTS) + +#define S_ACK_FREQUENCY 0 +#define M_ACK_FREQUENCY 0xffU +#define V_ACK_FREQUENCY(x) ((x) << S_ACK_FREQUENCY) +#define G_ACK_FREQUENCY(x) (((x) >> S_ACK_FREQUENCY) & M_ACK_FREQUENCY) + +#define A_PCIE_CORE_PORT_LINK_CONTROL 0x5710 + +#define S_CROSSLINK_ACTIVE 23 +#define V_CROSSLINK_ACTIVE(x) ((x) << S_CROSSLINK_ACTIVE) +#define F_CROSSLINK_ACTIVE V_CROSSLINK_ACTIVE(1U) + +#define S_CROSSLINK_ENABLE 22 +#define V_CROSSLINK_ENABLE(x) ((x) << S_CROSSLINK_ENABLE) +#define F_CROSSLINK_ENABLE V_CROSSLINK_ENABLE(1U) + +#define S_LINK_MODE_ENABLE 16 +#define M_LINK_MODE_ENABLE 0x3fU +#define V_LINK_MODE_ENABLE(x) ((x) << S_LINK_MODE_ENABLE) +#define G_LINK_MODE_ENABLE(x) (((x) >> S_LINK_MODE_ENABLE) & M_LINK_MODE_ENABLE) + +#define S_FAST_LINK_MODE 7 +#define V_FAST_LINK_MODE(x) ((x) << S_FAST_LINK_MODE) +#define F_FAST_LINK_MODE V_FAST_LINK_MODE(1U) + +#define S_DLL_LINK_ENABLE 5 +#define V_DLL_LINK_ENABLE(x) ((x) << S_DLL_LINK_ENABLE) +#define F_DLL_LINK_ENABLE V_DLL_LINK_ENABLE(1U) + +#define S_RESET_ASSERT 3 +#define V_RESET_ASSERT(x) ((x) << S_RESET_ASSERT) +#define F_RESET_ASSERT V_RESET_ASSERT(1U) + +#define S_LOOPBACK_ENABLE 2 +#define V_LOOPBACK_ENABLE(x) ((x) << S_LOOPBACK_ENABLE) +#define F_LOOPBACK_ENABLE V_LOOPBACK_ENABLE(1U) + +#define S_SCRAMBLE_DISABLE 1 +#define V_SCRAMBLE_DISABLE(x) ((x) << S_SCRAMBLE_DISABLE) +#define F_SCRAMBLE_DISABLE V_SCRAMBLE_DISABLE(1U) + +#define S_VENDOR_SPECIFIC_DLLP_REQUEST 0 +#define V_VENDOR_SPECIFIC_DLLP_REQUEST(x) \ + ((x) << S_VENDOR_SPECIFIC_DLLP_REQUEST) +#define F_VENDOR_SPECIFIC_DLLP_REQUEST V_VENDOR_SPECIFIC_DLLP_REQUEST(1U) + +#define A_PCIE_CORE_LANE_SKEW 0x5714 + +#define S_DISABLE_DESKEW 31 +#define V_DISABLE_DESKEW(x) ((x) << S_DISABLE_DESKEW) +#define F_DISABLE_DESKEW V_DISABLE_DESKEW(1U) + +#define S_ACK_NAK_DISABLE 25 +#define V_ACK_NAK_DISABLE(x) ((x) << S_ACK_NAK_DISABLE) +#define F_ACK_NAK_DISABLE V_ACK_NAK_DISABLE(1U) + +#define S_FLOW_CONTROL_DISABLE 24 +#define V_FLOW_CONTROL_DISABLE(x) ((x) << S_FLOW_CONTROL_DISABLE) +#define F_FLOW_CONTROL_DISABLE V_FLOW_CONTROL_DISABLE(1U) + +#define S_INSERT_TXSKEW 0 +#define M_INSERT_TXSKEW 0xffffffU +#define V_INSERT_TXSKEW(x) ((x) << S_INSERT_TXSKEW) +#define G_INSERT_TXSKEW(x) (((x) >> S_INSERT_TXSKEW) & M_INSERT_TXSKEW) + +#define A_PCIE_CORE_SYMBOL_NUMBER 0x5718 + +#define S_FLOW_CONTROL_TIMER_MODIFIER 24 +#define M_FLOW_CONTROL_TIMER_MODIFIER 0x1fU +#define V_FLOW_CONTROL_TIMER_MODIFIER(x) ((x) << S_FLOW_CONTROL_TIMER_MODIFIER) +#define G_FLOW_CONTROL_TIMER_MODIFIER(x) \ + (((x) >> S_FLOW_CONTROL_TIMER_MODIFIER) & M_FLOW_CONTROL_TIMER_MODIFIER) + +#define S_ACK_NAK_TIMER_MODIFIER 19 +#define M_ACK_NAK_TIMER_MODIFIER 0x1fU +#define V_ACK_NAK_TIMER_MODIFIER(x) ((x) << S_ACK_NAK_TIMER_MODIFIER) +#define G_ACK_NAK_TIMER_MODIFIER(x) \ + (((x) >> S_ACK_NAK_TIMER_MODIFIER) & M_ACK_NAK_TIMER_MODIFIER) + +#define S_REPLAY_TIMER_MODIFIER 14 +#define M_REPLAY_TIMER_MODIFIER 0x1fU +#define V_REPLAY_TIMER_MODIFIER(x) ((x) << S_REPLAY_TIMER_MODIFIER) +#define G_REPLAY_TIMER_MODIFIER(x) \ + (((x) >> S_REPLAY_TIMER_MODIFIER) & M_REPLAY_TIMER_MODIFIER) + +#define S_MAXFUNC 0 +#define M_MAXFUNC 0x7U +#define V_MAXFUNC(x) ((x) << S_MAXFUNC) +#define G_MAXFUNC(x) (((x) >> S_MAXFUNC) & M_MAXFUNC) + +#define A_PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 0x571c + +#define S_MASK_RADM_FILTER 16 +#define M_MASK_RADM_FILTER 0xffffU +#define V_MASK_RADM_FILTER(x) ((x) << S_MASK_RADM_FILTER) +#define G_MASK_RADM_FILTER(x) (((x) >> S_MASK_RADM_FILTER) & M_MASK_RADM_FILTER) + +#define S_DISABLE_FC_WATCHDOG 15 +#define V_DISABLE_FC_WATCHDOG(x) ((x) << S_DISABLE_FC_WATCHDOG) +#define F_DISABLE_FC_WATCHDOG V_DISABLE_FC_WATCHDOG(1U) + +#define S_SKP_INTERVAL 0 +#define M_SKP_INTERVAL 0x7ffU +#define V_SKP_INTERVAL(x) ((x) << S_SKP_INTERVAL) +#define G_SKP_INTERVAL(x) (((x) >> S_SKP_INTERVAL) & M_SKP_INTERVAL) + +#define A_PCIE_CORE_FILTER_MASK2 0x5720 +#define A_PCIE_CORE_DEBUG_0 0x5728 +#define A_PCIE_CORE_DEBUG_1 0x572c +#define A_PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x5730 + +#define S_TXPH_FC 12 +#define M_TXPH_FC 0xffU +#define V_TXPH_FC(x) ((x) << S_TXPH_FC) +#define G_TXPH_FC(x) (((x) >> S_TXPH_FC) & M_TXPH_FC) + +#define S_TXPD_FC 0 +#define M_TXPD_FC 0xfffU +#define V_TXPD_FC(x) ((x) << S_TXPD_FC) +#define G_TXPD_FC(x) (((x) >> S_TXPD_FC) & M_TXPD_FC) + +#define A_PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x5734 + +#define S_TXNPH_FC 12 +#define M_TXNPH_FC 0xffU +#define V_TXNPH_FC(x) ((x) << S_TXNPH_FC) +#define G_TXNPH_FC(x) (((x) >> S_TXNPH_FC) & M_TXNPH_FC) + +#define S_TXNPD_FC 0 +#define M_TXNPD_FC 0xfffU +#define V_TXNPD_FC(x) ((x) << S_TXNPD_FC) +#define G_TXNPD_FC(x) (((x) >> S_TXNPD_FC) & M_TXNPD_FC) + +#define A_PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x5738 + +#define S_TXCPLH_FC 12 +#define M_TXCPLH_FC 0xffU +#define V_TXCPLH_FC(x) ((x) << S_TXCPLH_FC) +#define G_TXCPLH_FC(x) (((x) >> S_TXCPLH_FC) & M_TXCPLH_FC) + +#define S_TXCPLD_FC 0 +#define M_TXCPLD_FC 0xfffU +#define V_TXCPLD_FC(x) ((x) << S_TXCPLD_FC) +#define G_TXCPLD_FC(x) (((x) >> S_TXCPLD_FC) & M_TXCPLD_FC) + +#define A_PCIE_CORE_QUEUE_STATUS 0x573c + +#define S_RXQUEUE_NOT_EMPTY 2 +#define V_RXQUEUE_NOT_EMPTY(x) ((x) << S_RXQUEUE_NOT_EMPTY) +#define F_RXQUEUE_NOT_EMPTY V_RXQUEUE_NOT_EMPTY(1U) + +#define S_TXRETRYBUF_NOT_EMPTY 1 +#define V_TXRETRYBUF_NOT_EMPTY(x) ((x) << S_TXRETRYBUF_NOT_EMPTY) +#define F_TXRETRYBUF_NOT_EMPTY V_TXRETRYBUF_NOT_EMPTY(1U) + +#define S_RXTLP_FC_NOT_RETURNED 0 +#define V_RXTLP_FC_NOT_RETURNED(x) ((x) << S_RXTLP_FC_NOT_RETURNED) +#define F_RXTLP_FC_NOT_RETURNED V_RXTLP_FC_NOT_RETURNED(1U) + +#define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 0x5740 + +#define S_VC3_WRR 24 +#define M_VC3_WRR 0xffU +#define V_VC3_WRR(x) ((x) << S_VC3_WRR) +#define G_VC3_WRR(x) (((x) >> S_VC3_WRR) & M_VC3_WRR) + +#define S_VC2_WRR 16 +#define M_VC2_WRR 0xffU +#define V_VC2_WRR(x) ((x) << S_VC2_WRR) +#define G_VC2_WRR(x) (((x) >> S_VC2_WRR) & M_VC2_WRR) + +#define S_VC1_WRR 8 +#define M_VC1_WRR 0xffU +#define V_VC1_WRR(x) ((x) << S_VC1_WRR) +#define G_VC1_WRR(x) (((x) >> S_VC1_WRR) & M_VC1_WRR) + +#define S_VC0_WRR 0 +#define M_VC0_WRR 0xffU +#define V_VC0_WRR(x) ((x) << S_VC0_WRR) +#define G_VC0_WRR(x) (((x) >> S_VC0_WRR) & M_VC0_WRR) + +#define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 0x5744 + +#define S_VC7_WRR 24 +#define M_VC7_WRR 0xffU +#define V_VC7_WRR(x) ((x) << S_VC7_WRR) +#define G_VC7_WRR(x) (((x) >> S_VC7_WRR) & M_VC7_WRR) + +#define S_VC6_WRR 16 +#define M_VC6_WRR 0xffU +#define V_VC6_WRR(x) ((x) << S_VC6_WRR) +#define G_VC6_WRR(x) (((x) >> S_VC6_WRR) & M_VC6_WRR) + +#define S_VC5_WRR 8 +#define M_VC5_WRR 0xffU +#define V_VC5_WRR(x) ((x) << S_VC5_WRR) +#define G_VC5_WRR(x) (((x) >> S_VC5_WRR) & M_VC5_WRR) + +#define S_VC4_WRR 0 +#define M_VC4_WRR 0xffU +#define V_VC4_WRR(x) ((x) << S_VC4_WRR) +#define G_VC4_WRR(x) (((x) >> S_VC4_WRR) & M_VC4_WRR) + +#define A_PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x5748 + +#define S_VC0_RX_ORDERING 31 +#define V_VC0_RX_ORDERING(x) ((x) << S_VC0_RX_ORDERING) +#define F_VC0_RX_ORDERING V_VC0_RX_ORDERING(1U) + +#define S_VC0_TLP_ORDERING 30 +#define V_VC0_TLP_ORDERING(x) ((x) << S_VC0_TLP_ORDERING) +#define F_VC0_TLP_ORDERING V_VC0_TLP_ORDERING(1U) + +#define S_VC0_PTLP_QUEUE_MODE 21 +#define M_VC0_PTLP_QUEUE_MODE 0x7U +#define V_VC0_PTLP_QUEUE_MODE(x) ((x) << S_VC0_PTLP_QUEUE_MODE) +#define G_VC0_PTLP_QUEUE_MODE(x) \ + (((x) >> S_VC0_PTLP_QUEUE_MODE) & M_VC0_PTLP_QUEUE_MODE) + +#define S_VC0_PH_CREDITS 12 +#define M_VC0_PH_CREDITS 0xffU +#define V_VC0_PH_CREDITS(x) ((x) << S_VC0_PH_CREDITS) +#define G_VC0_PH_CREDITS(x) (((x) >> S_VC0_PH_CREDITS) & M_VC0_PH_CREDITS) + +#define S_VC0_PD_CREDITS 0 +#define M_VC0_PD_CREDITS 0xfffU +#define V_VC0_PD_CREDITS(x) ((x) << S_VC0_PD_CREDITS) +#define G_VC0_PD_CREDITS(x) (((x) >> S_VC0_PD_CREDITS) & M_VC0_PD_CREDITS) + +#define A_PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x574c + +#define S_VC0_NPTLP_QUEUE_MODE 21 +#define M_VC0_NPTLP_QUEUE_MODE 0x7U +#define V_VC0_NPTLP_QUEUE_MODE(x) ((x) << S_VC0_NPTLP_QUEUE_MODE) +#define G_VC0_NPTLP_QUEUE_MODE(x) \ + (((x) >> S_VC0_NPTLP_QUEUE_MODE) & M_VC0_NPTLP_QUEUE_MODE) + +#define S_VC0_NPH_CREDITS 12 +#define M_VC0_NPH_CREDITS 0xffU +#define V_VC0_NPH_CREDITS(x) ((x) << S_VC0_NPH_CREDITS) +#define G_VC0_NPH_CREDITS(x) (((x) >> S_VC0_NPH_CREDITS) & M_VC0_NPH_CREDITS) + +#define S_VC0_NPD_CREDITS 0 +#define M_VC0_NPD_CREDITS 0xfffU +#define V_VC0_NPD_CREDITS(x) ((x) << S_VC0_NPD_CREDITS) +#define G_VC0_NPD_CREDITS(x) (((x) >> S_VC0_NPD_CREDITS) & M_VC0_NPD_CREDITS) + +#define A_PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x5750 + +#define S_VC0_CPLTLP_QUEUE_MODE 21 +#define M_VC0_CPLTLP_QUEUE_MODE 0x7U +#define V_VC0_CPLTLP_QUEUE_MODE(x) ((x) << S_VC0_CPLTLP_QUEUE_MODE) +#define G_VC0_CPLTLP_QUEUE_MODE(x) \ + (((x) >> S_VC0_CPLTLP_QUEUE_MODE) & M_VC0_CPLTLP_QUEUE_MODE) + +#define S_VC0_CPLH_CREDITS 12 +#define M_VC0_CPLH_CREDITS 0xffU +#define V_VC0_CPLH_CREDITS(x) ((x) << S_VC0_CPLH_CREDITS) +#define G_VC0_CPLH_CREDITS(x) (((x) >> S_VC0_CPLH_CREDITS) & M_VC0_CPLH_CREDITS) + +#define S_VC0_CPLD_CREDITS 0 +#define M_VC0_CPLD_CREDITS 0xfffU +#define V_VC0_CPLD_CREDITS(x) ((x) << S_VC0_CPLD_CREDITS) +#define G_VC0_CPLD_CREDITS(x) (((x) >> S_VC0_CPLD_CREDITS) & M_VC0_CPLD_CREDITS) + +#define A_PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x5754 + +#define S_VC1_TLP_ORDERING 30 +#define V_VC1_TLP_ORDERING(x) ((x) << S_VC1_TLP_ORDERING) +#define F_VC1_TLP_ORDERING V_VC1_TLP_ORDERING(1U) + +#define S_VC1_PTLP_QUEUE_MODE 21 +#define M_VC1_PTLP_QUEUE_MODE 0x7U +#define V_VC1_PTLP_QUEUE_MODE(x) ((x) << S_VC1_PTLP_QUEUE_MODE) +#define G_VC1_PTLP_QUEUE_MODE(x) \ + (((x) >> S_VC1_PTLP_QUEUE_MODE) & M_VC1_PTLP_QUEUE_MODE) + +#define S_VC1_PH_CREDITS 12 +#define M_VC1_PH_CREDITS 0xffU +#define V_VC1_PH_CREDITS(x) ((x) << S_VC1_PH_CREDITS) +#define G_VC1_PH_CREDITS(x) (((x) >> S_VC1_PH_CREDITS) & M_VC1_PH_CREDITS) + +#define S_VC1_PD_CREDITS 0 +#define M_VC1_PD_CREDITS 0xfffU +#define V_VC1_PD_CREDITS(x) ((x) << S_VC1_PD_CREDITS) +#define G_VC1_PD_CREDITS(x) (((x) >> S_VC1_PD_CREDITS) & M_VC1_PD_CREDITS) + +#define A_PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x5758 + +#define S_VC1_NPTLP_QUEUE_MODE 21 +#define M_VC1_NPTLP_QUEUE_MODE 0x7U +#define V_VC1_NPTLP_QUEUE_MODE(x) ((x) << S_VC1_NPTLP_QUEUE_MODE) +#define G_VC1_NPTLP_QUEUE_MODE(x) \ + (((x) >> S_VC1_NPTLP_QUEUE_MODE) & M_VC1_NPTLP_QUEUE_MODE) + +#define S_VC1_NPH_CREDITS 12 +#define M_VC1_NPH_CREDITS 0xffU +#define V_VC1_NPH_CREDITS(x) ((x) << S_VC1_NPH_CREDITS) +#define G_VC1_NPH_CREDITS(x) (((x) >> S_VC1_NPH_CREDITS) & M_VC1_NPH_CREDITS) + +#define S_VC1_NPD_CREDITS 0 +#define M_VC1_NPD_CREDITS 0xfffU +#define V_VC1_NPD_CREDITS(x) ((x) << S_VC1_NPD_CREDITS) +#define G_VC1_NPD_CREDITS(x) (((x) >> S_VC1_NPD_CREDITS) & M_VC1_NPD_CREDITS) + +#define A_PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x575c + +#define S_VC1_CPLTLP_QUEUE_MODE 21 +#define M_VC1_CPLTLP_QUEUE_MODE 0x7U +#define V_VC1_CPLTLP_QUEUE_MODE(x) ((x) << S_VC1_CPLTLP_QUEUE_MODE) +#define G_VC1_CPLTLP_QUEUE_MODE(x) \ + (((x) >> S_VC1_CPLTLP_QUEUE_MODE) & M_VC1_CPLTLP_QUEUE_MODE) + +#define S_VC1_CPLH_CREDITS 12 +#define M_VC1_CPLH_CREDITS 0xffU +#define V_VC1_CPLH_CREDITS(x) ((x) << S_VC1_CPLH_CREDITS) +#define G_VC1_CPLH_CREDITS(x) (((x) >> S_VC1_CPLH_CREDITS) & M_VC1_CPLH_CREDITS) + +#define S_VC1_CPLD_CREDITS 0 +#define M_VC1_CPLD_CREDITS 0xfffU +#define V_VC1_CPLD_CREDITS(x) ((x) << S_VC1_CPLD_CREDITS) +#define G_VC1_CPLD_CREDITS(x) (((x) >> S_VC1_CPLD_CREDITS) & M_VC1_CPLD_CREDITS) + +#define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c + +#define S_SEL_DEEMPHASIS 20 +#define V_SEL_DEEMPHASIS(x) ((x) << S_SEL_DEEMPHASIS) +#define F_SEL_DEEMPHASIS V_SEL_DEEMPHASIS(1U) + +#define S_TXCMPLRCV 19 +#define V_TXCMPLRCV(x) ((x) << S_TXCMPLRCV) +#define F_TXCMPLRCV V_TXCMPLRCV(1U) + +#define S_PHYTXSWING 18 +#define V_PHYTXSWING(x) ((x) << S_PHYTXSWING) +#define F_PHYTXSWING V_PHYTXSWING(1U) + +#define S_DIRSPDCHANGE 17 +#define V_DIRSPDCHANGE(x) ((x) << S_DIRSPDCHANGE) +#define F_DIRSPDCHANGE V_DIRSPDCHANGE(1U) + +#define S_NUM_LANES 8 +#define M_NUM_LANES 0x1ffU +#define V_NUM_LANES(x) ((x) << S_NUM_LANES) +#define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES) + +#define S_NFTS_GEN2_3 0 +#define M_NFTS_GEN2_3 0xffU +#define V_NFTS_GEN2_3(x) ((x) << S_NFTS_GEN2_3) +#define G_NFTS_GEN2_3(x) (((x) >> S_NFTS_GEN2_3) & M_NFTS_GEN2_3) + +#define A_PCIE_CORE_PHY_STATUS 0x5810 +#define A_PCIE_CORE_PHY_CONTROL 0x5814 +#define A_PCIE_CORE_GEN3_CONTROL 0x5890 + +#define S_DC_BALANCE_DISABLE 18 +#define V_DC_BALANCE_DISABLE(x) ((x) << S_DC_BALANCE_DISABLE) +#define F_DC_BALANCE_DISABLE V_DC_BALANCE_DISABLE(1U) + +#define S_DLLP_DELAY_DISABLE 17 +#define V_DLLP_DELAY_DISABLE(x) ((x) << S_DLLP_DELAY_DISABLE) +#define F_DLLP_DELAY_DISABLE V_DLLP_DELAY_DISABLE(1U) + +#define S_EQL_DISABLE 16 +#define V_EQL_DISABLE(x) ((x) << S_EQL_DISABLE) +#define F_EQL_DISABLE V_EQL_DISABLE(1U) + +#define S_EQL_REDO_DISABLE 11 +#define V_EQL_REDO_DISABLE(x) ((x) << S_EQL_REDO_DISABLE) +#define F_EQL_REDO_DISABLE V_EQL_REDO_DISABLE(1U) + +#define S_EQL_EIEOS_CNTRST_DISABLE 10 +#define V_EQL_EIEOS_CNTRST_DISABLE(x) ((x) << S_EQL_EIEOS_CNTRST_DISABLE) +#define F_EQL_EIEOS_CNTRST_DISABLE V_EQL_EIEOS_CNTRST_DISABLE(1U) + +#define S_EQL_PH2_PH3_DISABLE 9 +#define V_EQL_PH2_PH3_DISABLE(x) ((x) << S_EQL_PH2_PH3_DISABLE) +#define F_EQL_PH2_PH3_DISABLE V_EQL_PH2_PH3_DISABLE(1U) + +#define S_DISABLE_SCRAMBLER 8 +#define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER) +#define F_DISABLE_SCRAMBLER V_DISABLE_SCRAMBLER(1U) + +#define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894 + +#define S_FULL_SWING 6 +#define M_FULL_SWING 0x3fU +#define V_FULL_SWING(x) ((x) << S_FULL_SWING) +#define G_FULL_SWING(x) (((x) >> S_FULL_SWING) & M_FULL_SWING) + +#define S_LOW_FREQUENCY 0 +#define M_LOW_FREQUENCY 0x3fU +#define V_LOW_FREQUENCY(x) ((x) << S_LOW_FREQUENCY) +#define G_LOW_FREQUENCY(x) (((x) >> S_LOW_FREQUENCY) & M_LOW_FREQUENCY) + +#define A_PCIE_CORE_GEN3_EQ_PRESET_COEFF 0x5898 + +#define S_POSTCURSOR 12 +#define M_POSTCURSOR 0x3fU +#define V_POSTCURSOR(x) ((x) << S_POSTCURSOR) +#define G_POSTCURSOR(x) (((x) >> S_POSTCURSOR) & M_POSTCURSOR) + +#define S_CURSOR 6 +#define M_CURSOR 0x3fU +#define V_CURSOR(x) ((x) << S_CURSOR) +#define G_CURSOR(x) (((x) >> S_CURSOR) & M_CURSOR) + +#define S_PRECURSOR 0 +#define M_PRECURSOR 0x3fU +#define V_PRECURSOR(x) ((x) << S_PRECURSOR) +#define G_PRECURSOR(x) (((x) >> S_PRECURSOR) & M_PRECURSOR) + +#define A_PCIE_CORE_GEN3_EQ_PRESET_INDEX 0x589c + +#define S_INDEX 0 +#define M_INDEX 0xfU +#define V_INDEX(x) ((x) << S_INDEX) +#define G_INDEX(x) (((x) >> S_INDEX) & M_INDEX) + +#define A_PCIE_CORE_GEN3_EQ_STATUS 0x58a4 + +#define S_LEGALITY_STATUS 0 +#define V_LEGALITY_STATUS(x) ((x) << S_LEGALITY_STATUS) +#define F_LEGALITY_STATUS V_LEGALITY_STATUS(1U) + +#define A_PCIE_CORE_GEN3_EQ_CONTROL 0x58a8 + +#define S_INCLUDE_INITIAL_FOM 24 +#define V_INCLUDE_INITIAL_FOM(x) ((x) << S_INCLUDE_INITIAL_FOM) +#define F_INCLUDE_INITIAL_FOM V_INCLUDE_INITIAL_FOM(1U) + +#define S_PRESET_REQUEST_VECTOR 8 +#define M_PRESET_REQUEST_VECTOR 0xffffU +#define V_PRESET_REQUEST_VECTOR(x) ((x) << S_PRESET_REQUEST_VECTOR) +#define G_PRESET_REQUEST_VECTOR(x) \ + (((x) >> S_PRESET_REQUEST_VECTOR) & M_PRESET_REQUEST_VECTOR) + +#define S_PHASE23_2MS_TIMEOUT_DISABLE 5 +#define V_PHASE23_2MS_TIMEOUT_DISABLE(x) ((x) << S_PHASE23_2MS_TIMEOUT_DISABLE) +#define F_PHASE23_2MS_TIMEOUT_DISABLE V_PHASE23_2MS_TIMEOUT_DISABLE(1U) + +#define S_AFTER24MS 4 +#define V_AFTER24MS(x) ((x) << S_AFTER24MS) +#define F_AFTER24MS V_AFTER24MS(1U) + +#define S_FEEDBACK_MODE 0 +#define M_FEEDBACK_MODE 0xfU +#define V_FEEDBACK_MODE(x) ((x) << S_FEEDBACK_MODE) +#define G_FEEDBACK_MODE(x) (((x) >> S_FEEDBACK_MODE) & M_FEEDBACK_MODE) + +#define A_PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x58ac + +#define S_WINAPERTURE_CPLUS1 14 +#define M_WINAPERTURE_CPLUS1 0xfU +#define V_WINAPERTURE_CPLUS1(x) ((x) << S_WINAPERTURE_CPLUS1) +#define G_WINAPERTURE_CPLUS1(x) \ + (((x) >> S_WINAPERTURE_CPLUS1) & M_WINAPERTURE_CPLUS1) + +#define S_WINAPERTURE_CMINS1 10 +#define M_WINAPERTURE_CMINS1 0xfU +#define V_WINAPERTURE_CMINS1(x) ((x) << S_WINAPERTURE_CMINS1) +#define G_WINAPERTURE_CMINS1(x) \ + (((x) >> S_WINAPERTURE_CMINS1) & M_WINAPERTURE_CMINS1) + +#define S_CONVERGENCE_WINDEPTH 5 +#define M_CONVERGENCE_WINDEPTH 0x1fU +#define V_CONVERGENCE_WINDEPTH(x) ((x) << S_CONVERGENCE_WINDEPTH) +#define G_CONVERGENCE_WINDEPTH(x) \ + (((x) >> S_CONVERGENCE_WINDEPTH) & M_CONVERGENCE_WINDEPTH) + +#define S_EQMASTERPHASE_MINTIME 0 +#define M_EQMASTERPHASE_MINTIME 0x1fU +#define V_EQMASTERPHASE_MINTIME(x) ((x) << S_EQMASTERPHASE_MINTIME) +#define G_EQMASTERPHASE_MINTIME(x) \ + (((x) >> S_EQMASTERPHASE_MINTIME) & M_EQMASTERPHASE_MINTIME) + +#define A_PCIE_CORE_PIPE_CONTROL 0x58b8 + +#define S_PIPE_LOOPBACK_EN 0 +#define V_PIPE_LOOPBACK_EN(x) ((x) << S_PIPE_LOOPBACK_EN) +#define F_PIPE_LOOPBACK_EN V_PIPE_LOOPBACK_EN(1U) + +#define A_PCIE_CORE_DBI_RO_WE 0x58bc + +#define S_READONLY_WRITEEN 0 +#define V_READONLY_WRITEEN(x) ((x) << S_READONLY_WRITEEN) +#define F_READONLY_WRITEEN V_READONLY_WRITEEN(1U) + #define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900 #define S_SMTD 27 @@ -2499,6 +5437,106 @@ #define V_BRVN(x) ((x) << S_BRVN) #define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN) +#define A_PCIE_T5_DMA_CFG 0x5940 + +#define S_T5_DMA_MAXREQCNT 20 +#define M_T5_DMA_MAXREQCNT 0xffU +#define V_T5_DMA_MAXREQCNT(x) ((x) << S_T5_DMA_MAXREQCNT) +#define G_T5_DMA_MAXREQCNT(x) (((x) >> S_T5_DMA_MAXREQCNT) & M_T5_DMA_MAXREQCNT) + +#define S_T5_DMA_MAXRDREQSIZE 17 +#define M_T5_DMA_MAXRDREQSIZE 0x7U +#define V_T5_DMA_MAXRDREQSIZE(x) ((x) << S_T5_DMA_MAXRDREQSIZE) +#define G_T5_DMA_MAXRDREQSIZE(x) \ + (((x) >> S_T5_DMA_MAXRDREQSIZE) & M_T5_DMA_MAXRDREQSIZE) + +#define S_T5_DMA_MAXRSPCNT 8 +#define M_T5_DMA_MAXRSPCNT 0x1ffU +#define V_T5_DMA_MAXRSPCNT(x) ((x) << S_T5_DMA_MAXRSPCNT) +#define G_T5_DMA_MAXRSPCNT(x) (((x) >> S_T5_DMA_MAXRSPCNT) & M_T5_DMA_MAXRSPCNT) + +#define S_SEQCHKDIS 7 +#define V_SEQCHKDIS(x) ((x) << S_SEQCHKDIS) +#define F_SEQCHKDIS V_SEQCHKDIS(1U) + +#define S_MINTAG 0 +#define M_MINTAG 0x7fU +#define V_MINTAG(x) ((x) << S_MINTAG) +#define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG) + +#define A_PCIE_T5_DMA_STAT 0x5944 + +#define S_DMA_RESPCNT 20 +#define M_DMA_RESPCNT 0xfffU +#define V_DMA_RESPCNT(x) ((x) << S_DMA_RESPCNT) +#define G_DMA_RESPCNT(x) (((x) >> S_DMA_RESPCNT) & M_DMA_RESPCNT) + +#define S_DMA_RDREQCNT 12 +#define M_DMA_RDREQCNT 0xffU +#define V_DMA_RDREQCNT(x) ((x) << S_DMA_RDREQCNT) +#define G_DMA_RDREQCNT(x) (((x) >> S_DMA_RDREQCNT) & M_DMA_RDREQCNT) + +#define S_DMA_WRREQCNT 0 +#define M_DMA_WRREQCNT 0x7ffU +#define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT) +#define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT) + +#define A_PCIE_T5_DMA_STAT2 0x5948 + +#define S_COOKIECNT 24 +#define M_COOKIECNT 0xfU +#define V_COOKIECNT(x) ((x) << S_COOKIECNT) +#define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT) + +#define S_RDSEQNUMUPDCNT 20 +#define M_RDSEQNUMUPDCNT 0xfU +#define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT) +#define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT) + +#define S_SIREQCNT 16 +#define M_SIREQCNT 0xfU +#define V_SIREQCNT(x) ((x) << S_SIREQCNT) +#define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT) + +#define S_WREOPMATCHSOP 12 +#define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP) +#define F_WREOPMATCHSOP V_WREOPMATCHSOP(1U) + +#define S_WRSOPCNT 8 +#define M_WRSOPCNT 0xfU +#define V_WRSOPCNT(x) ((x) << S_WRSOPCNT) +#define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT) + +#define S_RDSOPCNT 0 +#define M_RDSOPCNT 0xffU +#define V_RDSOPCNT(x) ((x) << S_RDSOPCNT) +#define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT) + +#define A_PCIE_T5_DMA_STAT3 0x594c + +#define S_ATMREQSOPCNT 24 +#define M_ATMREQSOPCNT 0xffU +#define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT) +#define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT) + +#define S_ATMEOPMATCHSOP 17 +#define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP) +#define F_ATMEOPMATCHSOP V_ATMEOPMATCHSOP(1U) + +#define S_RSPEOPMATCHSOP 16 +#define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP) +#define F_RSPEOPMATCHSOP V_RSPEOPMATCHSOP(1U) + +#define S_RSPERRCNT 8 +#define M_RSPERRCNT 0xffU +#define V_RSPERRCNT(x) ((x) << S_RSPERRCNT) +#define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT) + +#define S_RSPSOPCNT 0 +#define M_RSPSOPCNT 0xffU +#define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT) +#define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT) + #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960 #define S_OP0H 24 @@ -2609,6 +5647,35 @@ #define V_ON3H(x) ((x) << S_ON3H) #define G_ON3H(x) (((x) >> S_ON3H) & M_ON3H) +#define A_PCIE_T5_CMD_CFG 0x5980 + +#define S_T5_CMD_MAXRDREQSIZE 17 +#define M_T5_CMD_MAXRDREQSIZE 0x7U +#define V_T5_CMD_MAXRDREQSIZE(x) ((x) << S_T5_CMD_MAXRDREQSIZE) +#define G_T5_CMD_MAXRDREQSIZE(x) \ + (((x) >> S_T5_CMD_MAXRDREQSIZE) & M_T5_CMD_MAXRDREQSIZE) + +#define S_T5_CMD_MAXRSPCNT 8 +#define M_T5_CMD_MAXRSPCNT 0xffU +#define V_T5_CMD_MAXRSPCNT(x) ((x) << S_T5_CMD_MAXRSPCNT) +#define G_T5_CMD_MAXRSPCNT(x) (((x) >> S_T5_CMD_MAXRSPCNT) & M_T5_CMD_MAXRSPCNT) + +#define S_USECMDPOOL 7 +#define V_USECMDPOOL(x) ((x) << S_USECMDPOOL) +#define F_USECMDPOOL V_USECMDPOOL(1U) + +#define A_PCIE_T5_CMD_STAT 0x5984 + +#define S_T5_STAT_RSPCNT 20 +#define M_T5_STAT_RSPCNT 0x7ffU +#define V_T5_STAT_RSPCNT(x) ((x) << S_T5_STAT_RSPCNT) +#define G_T5_STAT_RSPCNT(x) (((x) >> S_T5_STAT_RSPCNT) & M_T5_STAT_RSPCNT) + +#define S_RDREQCNT 12 +#define M_RDREQCNT 0x1fU +#define V_RDREQCNT(x) ((x) << S_RDREQCNT) +#define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT) + #define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988 #define S_IN0H 24 @@ -2631,6 +5698,9 @@ #define V_IN3H(x) ((x) << S_IN3H) #define G_IN3H(x) (((x) >> S_IN3H) & M_IN3H) +#define A_PCIE_T5_CMD_STAT2 0x5988 +#define A_PCIE_T5_CMD_STAT3 0x598c + #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990 #define S_OC0T 24 @@ -2914,6 +5984,24 @@ #define V_CRSE(x) ((x) << S_CRSE) #define F_CRSE V_CRSE(1U) +#define A_PCIE_T5_HMA_CFG 0x59b0 + +#define S_HMA_MAXREQCNT 20 +#define M_HMA_MAXREQCNT 0x1fU +#define V_HMA_MAXREQCNT(x) ((x) << S_HMA_MAXREQCNT) +#define G_HMA_MAXREQCNT(x) (((x) >> S_HMA_MAXREQCNT) & M_HMA_MAXREQCNT) + +#define S_T5_HMA_MAXRDREQSIZE 17 +#define M_T5_HMA_MAXRDREQSIZE 0x7U +#define V_T5_HMA_MAXRDREQSIZE(x) ((x) << S_T5_HMA_MAXRDREQSIZE) +#define G_T5_HMA_MAXRDREQSIZE(x) \ + (((x) >> S_T5_HMA_MAXRDREQSIZE) & M_T5_HMA_MAXRDREQSIZE) + +#define S_T5_HMA_MAXRSPCNT 8 +#define M_T5_HMA_MAXRSPCNT 0x1fU +#define V_T5_HMA_MAXRSPCNT(x) ((x) << S_T5_HMA_MAXRSPCNT) +#define G_T5_HMA_MAXRSPCNT(x) (((x) >> S_T5_HMA_MAXRSPCNT) & M_T5_HMA_MAXRSPCNT) + #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4 #define S_RLCS 31 @@ -2960,6 +6048,23 @@ #define V_CRSS(x) ((x) << S_CRSS) #define F_CRSS V_CRSS(1U) +#define A_PCIE_T5_HMA_STAT 0x59b4 + +#define S_HMA_RESPCNT 20 +#define M_HMA_RESPCNT 0x1ffU +#define V_HMA_RESPCNT(x) ((x) << S_HMA_RESPCNT) +#define G_HMA_RESPCNT(x) (((x) >> S_HMA_RESPCNT) & M_HMA_RESPCNT) + +#define S_HMA_RDREQCNT 12 +#define M_HMA_RDREQCNT 0x3fU +#define V_HMA_RDREQCNT(x) ((x) << S_HMA_RDREQCNT) +#define G_HMA_RDREQCNT(x) (((x) >> S_HMA_RDREQCNT) & M_HMA_RDREQCNT) + +#define S_HMA_WRREQCNT 0 +#define M_HMA_WRREQCNT 0x1ffU +#define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT) +#define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT) + #define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8 #define S_RLCI 31 @@ -3006,6 +6111,7 @@ #define V_CRSI(x) ((x) << S_CRSI) #define F_CRSI V_CRSI(1U) +#define A_PCIE_T5_HMA_STAT2 0x59b8 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc #define S_PTOM 31 @@ -3048,6 +6154,7 @@ #define V_PMC7(x) ((x) << S_PMC7) #define F_PMC7 V_PMC7(1U) +#define A_PCIE_T5_HMA_STAT3 0x59bc #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0 #define S_PTOS 31 @@ -3122,6 +6229,84 @@ #define V_PME7(x) ((x) << S_PME7) #define F_PME7 V_PME7(1U) +#define A_PCIE_CGEN 0x59c0 + +#define S_VPD_DYNAMIC_CGEN 26 +#define V_VPD_DYNAMIC_CGEN(x) ((x) << S_VPD_DYNAMIC_CGEN) +#define F_VPD_DYNAMIC_CGEN V_VPD_DYNAMIC_CGEN(1U) + +#define S_MA_DYNAMIC_CGEN 25 +#define V_MA_DYNAMIC_CGEN(x) ((x) << S_MA_DYNAMIC_CGEN) +#define F_MA_DYNAMIC_CGEN V_MA_DYNAMIC_CGEN(1U) + +#define S_TAGQ_DYNAMIC_CGEN 24 +#define V_TAGQ_DYNAMIC_CGEN(x) ((x) << S_TAGQ_DYNAMIC_CGEN) +#define F_TAGQ_DYNAMIC_CGEN V_TAGQ_DYNAMIC_CGEN(1U) + +#define S_REQCTL_DYNAMIC_CGEN 23 +#define V_REQCTL_DYNAMIC_CGEN(x) ((x) << S_REQCTL_DYNAMIC_CGEN) +#define F_REQCTL_DYNAMIC_CGEN V_REQCTL_DYNAMIC_CGEN(1U) + +#define S_RSPDATAPROC_DYNAMIC_CGEN 22 +#define V_RSPDATAPROC_DYNAMIC_CGEN(x) ((x) << S_RSPDATAPROC_DYNAMIC_CGEN) +#define F_RSPDATAPROC_DYNAMIC_CGEN V_RSPDATAPROC_DYNAMIC_CGEN(1U) + +#define S_RSPRDQ_DYNAMIC_CGEN 21 +#define V_RSPRDQ_DYNAMIC_CGEN(x) ((x) << S_RSPRDQ_DYNAMIC_CGEN) +#define F_RSPRDQ_DYNAMIC_CGEN V_RSPRDQ_DYNAMIC_CGEN(1U) + +#define S_RSPIPIF_DYNAMIC_CGEN 20 +#define V_RSPIPIF_DYNAMIC_CGEN(x) ((x) << S_RSPIPIF_DYNAMIC_CGEN) +#define F_RSPIPIF_DYNAMIC_CGEN V_RSPIPIF_DYNAMIC_CGEN(1U) + +#define S_HMA_STATIC_CGEN 19 +#define V_HMA_STATIC_CGEN(x) ((x) << S_HMA_STATIC_CGEN) +#define F_HMA_STATIC_CGEN V_HMA_STATIC_CGEN(1U) + +#define S_HMA_DYNAMIC_CGEN 18 +#define V_HMA_DYNAMIC_CGEN(x) ((x) << S_HMA_DYNAMIC_CGEN) +#define F_HMA_DYNAMIC_CGEN V_HMA_DYNAMIC_CGEN(1U) + +#define S_CMD_STATIC_CGEN 16 +#define V_CMD_STATIC_CGEN(x) ((x) << S_CMD_STATIC_CGEN) +#define F_CMD_STATIC_CGEN V_CMD_STATIC_CGEN(1U) + +#define S_CMD_DYNAMIC_CGEN 15 +#define V_CMD_DYNAMIC_CGEN(x) ((x) << S_CMD_DYNAMIC_CGEN) +#define F_CMD_DYNAMIC_CGEN V_CMD_DYNAMIC_CGEN(1U) + +#define S_DMA_STATIC_CGEN 13 +#define V_DMA_STATIC_CGEN(x) ((x) << S_DMA_STATIC_CGEN) +#define F_DMA_STATIC_CGEN V_DMA_STATIC_CGEN(1U) + +#define S_DMA_DYNAMIC_CGEN 12 +#define V_DMA_DYNAMIC_CGEN(x) ((x) << S_DMA_DYNAMIC_CGEN) +#define F_DMA_DYNAMIC_CGEN V_DMA_DYNAMIC_CGEN(1U) + +#define S_VFID_SLEEPSTATUS 10 +#define V_VFID_SLEEPSTATUS(x) ((x) << S_VFID_SLEEPSTATUS) +#define F_VFID_SLEEPSTATUS V_VFID_SLEEPSTATUS(1U) + +#define S_VC1_SLEEPSTATUS 9 +#define V_VC1_SLEEPSTATUS(x) ((x) << S_VC1_SLEEPSTATUS) +#define F_VC1_SLEEPSTATUS V_VC1_SLEEPSTATUS(1U) + +#define S_STI_SLEEPSTATUS 8 +#define V_STI_SLEEPSTATUS(x) ((x) << S_STI_SLEEPSTATUS) +#define F_STI_SLEEPSTATUS V_STI_SLEEPSTATUS(1U) + +#define S_VFID_SLEEPREQ 2 +#define V_VFID_SLEEPREQ(x) ((x) << S_VFID_SLEEPREQ) +#define F_VFID_SLEEPREQ V_VFID_SLEEPREQ(1U) + +#define S_VC1_SLEEPREQ 1 +#define V_VC1_SLEEPREQ(x) ((x) << S_VC1_SLEEPREQ) +#define F_VC1_SLEEPREQ V_VC1_SLEEPREQ(1U) + +#define S_STI_SLEEPREQ 0 +#define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ) +#define F_STI_SLEEPREQ V_STI_SLEEPREQ(1U) + #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4 #define S_PTOI 31 @@ -3164,6 +6349,21 @@ #define V_PC7I(x) ((x) << S_PC7I) #define F_PC7I V_PC7I(1U) +#define A_PCIE_MA_RSP 0x59c4 + +#define S_TIMERVALUE 8 +#define M_TIMERVALUE 0xffffffU +#define V_TIMERVALUE(x) ((x) << S_TIMERVALUE) +#define G_TIMERVALUE(x) (((x) >> S_TIMERVALUE) & M_TIMERVALUE) + +#define S_MAREQTIMEREN 1 +#define V_MAREQTIMEREN(x) ((x) << S_MAREQTIMEREN) +#define F_MAREQTIMEREN V_MAREQTIMEREN(1U) + +#define S_MARSPTIMEREN 0 +#define V_MARSPTIMEREN(x) ((x) << S_MARSPTIMEREN) +#define F_MARSPTIMEREN V_MARSPTIMEREN(1U) + #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8 #define S_TOAK 31 @@ -3186,6 +6386,59 @@ #define V_ALET(x) ((x) << S_ALET) #define F_ALET V_ALET(1U) +#define A_PCIE_HPRD 0x59c8 + +#define S_NPH_CREDITSAVAILVC0 19 +#define M_NPH_CREDITSAVAILVC0 0x3U +#define V_NPH_CREDITSAVAILVC0(x) ((x) << S_NPH_CREDITSAVAILVC0) +#define G_NPH_CREDITSAVAILVC0(x) \ + (((x) >> S_NPH_CREDITSAVAILVC0) & M_NPH_CREDITSAVAILVC0) + +#define S_NPD_CREDITSAVAILVC0 17 +#define M_NPD_CREDITSAVAILVC0 0x3U +#define V_NPD_CREDITSAVAILVC0(x) ((x) << S_NPD_CREDITSAVAILVC0) +#define G_NPD_CREDITSAVAILVC0(x) \ + (((x) >> S_NPD_CREDITSAVAILVC0) & M_NPD_CREDITSAVAILVC0) + +#define S_NPH_CREDITSAVAILVC1 15 +#define M_NPH_CREDITSAVAILVC1 0x3U +#define V_NPH_CREDITSAVAILVC1(x) ((x) << S_NPH_CREDITSAVAILVC1) +#define G_NPH_CREDITSAVAILVC1(x) \ + (((x) >> S_NPH_CREDITSAVAILVC1) & M_NPH_CREDITSAVAILVC1) + +#define S_NPD_CREDITSAVAILVC1 13 +#define M_NPD_CREDITSAVAILVC1 0x3U +#define V_NPD_CREDITSAVAILVC1(x) ((x) << S_NPD_CREDITSAVAILVC1) +#define G_NPD_CREDITSAVAILVC1(x) \ + (((x) >> S_NPD_CREDITSAVAILVC1) & M_NPD_CREDITSAVAILVC1) + +#define S_NPH_CREDITSREQUIRED 11 +#define M_NPH_CREDITSREQUIRED 0x3U +#define V_NPH_CREDITSREQUIRED(x) ((x) << S_NPH_CREDITSREQUIRED) +#define G_NPH_CREDITSREQUIRED(x) \ + (((x) >> S_NPH_CREDITSREQUIRED) & M_NPH_CREDITSREQUIRED) + +#define S_NPD_CREDITSREQUIRED 9 +#define M_NPD_CREDITSREQUIRED 0x3U +#define V_NPD_CREDITSREQUIRED(x) ((x) << S_NPD_CREDITSREQUIRED) +#define G_NPD_CREDITSREQUIRED(x) \ + (((x) >> S_NPD_CREDITSREQUIRED) & M_NPD_CREDITSREQUIRED) + +#define S_REQBURSTCOUNT 5 +#define M_REQBURSTCOUNT 0xfU +#define V_REQBURSTCOUNT(x) ((x) << S_REQBURSTCOUNT) +#define G_REQBURSTCOUNT(x) (((x) >> S_REQBURSTCOUNT) & M_REQBURSTCOUNT) + +#define S_REQBURSTFREQUENCY 1 +#define M_REQBURSTFREQUENCY 0xfU +#define V_REQBURSTFREQUENCY(x) ((x) << S_REQBURSTFREQUENCY) +#define G_REQBURSTFREQUENCY(x) \ + (((x) >> S_REQBURSTFREQUENCY) & M_REQBURSTFREQUENCY) + +#define S_ENABLEVC1 0 +#define V_ENABLEVC1(x) ((x) << S_ENABLEVC1) +#define F_ENABLEVC1 V_ENABLEVC1(1U) + #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc #define S_CPM0 30 @@ -3269,7 +6522,205 @@ #define G_OPM7(x) (((x) >> S_OPM7) & M_OPM7) #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0 +#define A_PCIE_PERR_GROUP 0x59d0 + +#define S_MST_DATAPATHPERR 25 +#define V_MST_DATAPATHPERR(x) ((x) << S_MST_DATAPATHPERR) +#define F_MST_DATAPATHPERR V_MST_DATAPATHPERR(1U) + +#define S_MST_RSPRDQPERR 24 +#define V_MST_RSPRDQPERR(x) ((x) << S_MST_RSPRDQPERR) +#define F_MST_RSPRDQPERR V_MST_RSPRDQPERR(1U) + +#define S_IP_RXPERR 23 +#define V_IP_RXPERR(x) ((x) << S_IP_RXPERR) +#define F_IP_RXPERR V_IP_RXPERR(1U) + +#define S_IP_BACKTXPERR 22 +#define V_IP_BACKTXPERR(x) ((x) << S_IP_BACKTXPERR) +#define F_IP_BACKTXPERR V_IP_BACKTXPERR(1U) + +#define S_IP_FRONTTXPERR 21 +#define V_IP_FRONTTXPERR(x) ((x) << S_IP_FRONTTXPERR) +#define F_IP_FRONTTXPERR V_IP_FRONTTXPERR(1U) + +#define S_TRGT1_FIDLKUPHDRPERR 20 +#define V_TRGT1_FIDLKUPHDRPERR(x) ((x) << S_TRGT1_FIDLKUPHDRPERR) +#define F_TRGT1_FIDLKUPHDRPERR V_TRGT1_FIDLKUPHDRPERR(1U) + +#define S_TRGT1_ALINDDATAPERR 19 +#define V_TRGT1_ALINDDATAPERR(x) ((x) << S_TRGT1_ALINDDATAPERR) +#define F_TRGT1_ALINDDATAPERR V_TRGT1_ALINDDATAPERR(1U) + +#define S_TRGT1_UNALINDATAPERR 18 +#define V_TRGT1_UNALINDATAPERR(x) ((x) << S_TRGT1_UNALINDATAPERR) +#define F_TRGT1_UNALINDATAPERR V_TRGT1_UNALINDATAPERR(1U) + +#define S_TRGT1_REQDATAPERR 17 +#define V_TRGT1_REQDATAPERR(x) ((x) << S_TRGT1_REQDATAPERR) +#define F_TRGT1_REQDATAPERR V_TRGT1_REQDATAPERR(1U) + +#define S_TRGT1_REQHDRPERR 16 +#define V_TRGT1_REQHDRPERR(x) ((x) << S_TRGT1_REQHDRPERR) +#define F_TRGT1_REQHDRPERR V_TRGT1_REQHDRPERR(1U) + +#define S_IPRXDATA_VC1PERR 15 +#define V_IPRXDATA_VC1PERR(x) ((x) << S_IPRXDATA_VC1PERR) +#define F_IPRXDATA_VC1PERR V_IPRXDATA_VC1PERR(1U) + +#define S_IPRXDATA_VC0PERR 14 +#define V_IPRXDATA_VC0PERR(x) ((x) << S_IPRXDATA_VC0PERR) +#define F_IPRXDATA_VC0PERR V_IPRXDATA_VC0PERR(1U) + +#define S_IPRXHDR_VC1PERR 13 +#define V_IPRXHDR_VC1PERR(x) ((x) << S_IPRXHDR_VC1PERR) +#define F_IPRXHDR_VC1PERR V_IPRXHDR_VC1PERR(1U) + +#define S_IPRXHDR_VC0PERR 12 +#define V_IPRXHDR_VC0PERR(x) ((x) << S_IPRXHDR_VC0PERR) +#define F_IPRXHDR_VC0PERR V_IPRXHDR_VC0PERR(1U) + +#define S_MA_RSPDATAPERR 11 +#define V_MA_RSPDATAPERR(x) ((x) << S_MA_RSPDATAPERR) +#define F_MA_RSPDATAPERR V_MA_RSPDATAPERR(1U) + +#define S_MA_CPLTAGQPERR 10 +#define V_MA_CPLTAGQPERR(x) ((x) << S_MA_CPLTAGQPERR) +#define F_MA_CPLTAGQPERR V_MA_CPLTAGQPERR(1U) + +#define S_MA_REQTAGQPERR 9 +#define V_MA_REQTAGQPERR(x) ((x) << S_MA_REQTAGQPERR) +#define F_MA_REQTAGQPERR V_MA_REQTAGQPERR(1U) + +#define S_PIOREQ_BAR2CTLPERR 8 +#define V_PIOREQ_BAR2CTLPERR(x) ((x) << S_PIOREQ_BAR2CTLPERR) +#define F_PIOREQ_BAR2CTLPERR V_PIOREQ_BAR2CTLPERR(1U) + +#define S_PIOREQ_MEMCTLPERR 7 +#define V_PIOREQ_MEMCTLPERR(x) ((x) << S_PIOREQ_MEMCTLPERR) +#define F_PIOREQ_MEMCTLPERR V_PIOREQ_MEMCTLPERR(1U) + +#define S_PIOREQ_PLMCTLPERR 6 +#define V_PIOREQ_PLMCTLPERR(x) ((x) << S_PIOREQ_PLMCTLPERR) +#define F_PIOREQ_PLMCTLPERR V_PIOREQ_PLMCTLPERR(1U) + +#define S_PIOREQ_BAR2DATAPERR 5 +#define V_PIOREQ_BAR2DATAPERR(x) ((x) << S_PIOREQ_BAR2DATAPERR) +#define F_PIOREQ_BAR2DATAPERR V_PIOREQ_BAR2DATAPERR(1U) + +#define S_PIOREQ_MEMDATAPERR 4 +#define V_PIOREQ_MEMDATAPERR(x) ((x) << S_PIOREQ_MEMDATAPERR) +#define F_PIOREQ_MEMDATAPERR V_PIOREQ_MEMDATAPERR(1U) + +#define S_PIOREQ_PLMDATAPERR 3 +#define V_PIOREQ_PLMDATAPERR(x) ((x) << S_PIOREQ_PLMDATAPERR) +#define F_PIOREQ_PLMDATAPERR V_PIOREQ_PLMDATAPERR(1U) + +#define S_PIOCPL_CTLPERR 2 +#define V_PIOCPL_CTLPERR(x) ((x) << S_PIOCPL_CTLPERR) +#define F_PIOCPL_CTLPERR V_PIOCPL_CTLPERR(1U) + +#define S_PIOCPL_DATAPERR 1 +#define V_PIOCPL_DATAPERR(x) ((x) << S_PIOCPL_DATAPERR) +#define F_PIOCPL_DATAPERR V_PIOCPL_DATAPERR(1U) + +#define S_PIOCPL_PLMRSPPERR 0 +#define V_PIOCPL_PLMRSPPERR(x) ((x) << S_PIOCPL_PLMRSPPERR) +#define F_PIOCPL_PLMRSPPERR V_PIOCPL_PLMRSPPERR(1U) + #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4 +#define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4 + +#define S_CPLSTATUSINTEN 12 +#define V_CPLSTATUSINTEN(x) ((x) << S_CPLSTATUSINTEN) +#define F_CPLSTATUSINTEN V_CPLSTATUSINTEN(1U) + +#define S_REQTIMEOUTINTEN 11 +#define V_REQTIMEOUTINTEN(x) ((x) << S_REQTIMEOUTINTEN) +#define F_REQTIMEOUTINTEN V_REQTIMEOUTINTEN(1U) + +#define S_DISABLEDINTEN 10 +#define V_DISABLEDINTEN(x) ((x) << S_DISABLEDINTEN) +#define F_DISABLEDINTEN V_DISABLEDINTEN(1U) + +#define S_RSPDROPFLRINTEN 9 +#define V_RSPDROPFLRINTEN(x) ((x) << S_RSPDROPFLRINTEN) +#define F_RSPDROPFLRINTEN V_RSPDROPFLRINTEN(1U) + +#define S_REQUNDERFLRINTEN 8 +#define V_REQUNDERFLRINTEN(x) ((x) << S_REQUNDERFLRINTEN) +#define F_REQUNDERFLRINTEN V_REQUNDERFLRINTEN(1U) + +#define S_CPLSTATUSLOGEN 4 +#define V_CPLSTATUSLOGEN(x) ((x) << S_CPLSTATUSLOGEN) +#define F_CPLSTATUSLOGEN V_CPLSTATUSLOGEN(1U) + +#define S_TIMEOUTLOGEN 3 +#define V_TIMEOUTLOGEN(x) ((x) << S_TIMEOUTLOGEN) +#define F_TIMEOUTLOGEN V_TIMEOUTLOGEN(1U) + +#define S_DISABLEDLOGEN 2 +#define V_DISABLEDLOGEN(x) ((x) << S_DISABLEDLOGEN) +#define F_DISABLEDLOGEN V_DISABLEDLOGEN(1U) + +#define S_RSPDROPFLRLOGEN 1 +#define V_RSPDROPFLRLOGEN(x) ((x) << S_RSPDROPFLRLOGEN) +#define F_RSPDROPFLRLOGEN V_RSPDROPFLRLOGEN(1U) + +#define S_REQUNDERFLRLOGEN 0 +#define V_REQUNDERFLRLOGEN(x) ((x) << S_REQUNDERFLRLOGEN) +#define F_REQUNDERFLRLOGEN V_REQUNDERFLRLOGEN(1U) + +#define A_PCIE_RSP_ERR_LOG1 0x59d8 + +#define S_REQTAG 25 +#define M_REQTAG 0x7fU +#define V_REQTAG(x) ((x) << S_REQTAG) +#define G_REQTAG(x) (((x) >> S_REQTAG) & M_REQTAG) + +#define S_CID 22 +#define M_CID 0x7U +#define V_CID(x) ((x) << S_CID) +#define G_CID(x) (((x) >> S_CID) & M_CID) + +#define S_CHNUM 19 +#define M_CHNUM 0x7U +#define V_CHNUM(x) ((x) << S_CHNUM) +#define G_CHNUM(x) (((x) >> S_CHNUM) & M_CHNUM) + +#define S_BYTELEN 6 +#define M_BYTELEN 0x1fffU +#define V_BYTELEN(x) ((x) << S_BYTELEN) +#define G_BYTELEN(x) (((x) >> S_BYTELEN) & M_BYTELEN) + +#define S_REASON 3 +#define M_REASON 0x7U +#define V_REASON(x) ((x) << S_REASON) +#define G_REASON(x) (((x) >> S_REASON) & M_REASON) + +#define S_CPLSTATUS 0 +#define M_CPLSTATUS 0x7U +#define V_CPLSTATUS(x) ((x) << S_CPLSTATUS) +#define G_CPLSTATUS(x) (((x) >> S_CPLSTATUS) & M_CPLSTATUS) + +#define A_PCIE_RSP_ERR_LOG2 0x59dc + +#define S_LOGVALID 31 +#define V_LOGVALID(x) ((x) << S_LOGVALID) +#define F_LOGVALID V_LOGVALID(1U) + +#define S_ADDR10B 8 +#define M_ADDR10B 0x3ffU +#define V_ADDR10B(x) ((x) << S_ADDR10B) +#define G_ADDR10B(x) (((x) >> S_ADDR10B) & M_ADDR10B) + +#define S_REQVFID 0 +#define M_REQVFID 0xffU +#define V_REQVFID(x) ((x) << S_REQVFID) +#define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID) + +#define A_PCIE_CHANGESET 0x59fc + #define A_PCIE_REVISION 0x5a00 #define A_PCIE_PDEBUG_INDEX 0x5a04 @@ -3412,6 +6863,12 @@ #define A_PCIE_BUS_MST_STAT_2 0x5a68 #define A_PCIE_BUS_MST_STAT_3 0x5a6c #define A_PCIE_BUS_MST_STAT_4 0x5a70 + +#define S_BUSMST_135_128 0 +#define M_BUSMST_135_128 0xffU +#define V_BUSMST_135_128(x) ((x) << S_BUSMST_135_128) +#define G_BUSMST_135_128(x) (((x) >> S_BUSMST_135_128) & M_BUSMST_135_128) + #define A_PCIE_BUS_MST_STAT_5 0x5a74 #define A_PCIE_BUS_MST_STAT_6 0x5a78 #define A_PCIE_BUS_MST_STAT_7 0x5a7c @@ -3420,9 +6877,54 @@ #define A_PCIE_RSP_ERR_STAT_2 0x5a88 #define A_PCIE_RSP_ERR_STAT_3 0x5a8c #define A_PCIE_RSP_ERR_STAT_4 0x5a90 + +#define S_RSPERR_135_128 0 +#define M_RSPERR_135_128 0xffU +#define V_RSPERR_135_128(x) ((x) << S_RSPERR_135_128) +#define G_RSPERR_135_128(x) (((x) >> S_RSPERR_135_128) & M_RSPERR_135_128) + #define A_PCIE_RSP_ERR_STAT_5 0x5a94 +#define A_PCIE_DBI_TIMEOUT_CTL 0x5a94 + +#define S_DBI_TIMER 0 +#define M_DBI_TIMER 0xffffU +#define V_DBI_TIMER(x) ((x) << S_DBI_TIMER) +#define G_DBI_TIMER(x) (((x) >> S_DBI_TIMER) & M_DBI_TIMER) + #define A_PCIE_RSP_ERR_STAT_6 0x5a98 +#define A_PCIE_DBI_TIMEOUT_STATUS0 0x5a98 #define A_PCIE_RSP_ERR_STAT_7 0x5a9c +#define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c +#define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c + +#define S_SOURCE 16 +#define M_SOURCE 0x3U +#define V_SOURCE(x) ((x) << S_SOURCE) +#define G_SOURCE(x) (((x) >> S_SOURCE) & M_SOURCE) + +#define S_DBI_WRITE 12 +#define M_DBI_WRITE 0xfU +#define V_DBI_WRITE(x) ((x) << S_DBI_WRITE) +#define G_DBI_WRITE(x) (((x) >> S_DBI_WRITE) & M_DBI_WRITE) + +#define S_DBI_CS2 11 +#define V_DBI_CS2(x) ((x) << S_DBI_CS2) +#define F_DBI_CS2 V_DBI_CS2(1U) + +#define S_DBI_PF 8 +#define M_DBI_PF 0x7U +#define V_DBI_PF(x) ((x) << S_DBI_PF) +#define G_DBI_PF(x) (((x) >> S_DBI_PF) & M_DBI_PF) + +#define S_PL_TOVFVLD 7 +#define V_PL_TOVFVLD(x) ((x) << S_PL_TOVFVLD) +#define F_PL_TOVFVLD V_PL_TOVFVLD(1U) + +#define S_PL_TOVF 0 +#define M_PL_TOVF 0x7fU +#define V_PL_TOVF(x) ((x) << S_PL_TOVF) +#define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF) + #define A_PCIE_MSI_EN_0 0x5aa0 #define A_PCIE_MSI_EN_1 0x5aa4 #define A_PCIE_MSI_EN_2 0x5aa8 @@ -3456,6 +6958,388 @@ #define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ) #define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ) +#define A_PCIE_PB_CTL 0x5b94 + +#define S_PB_SEL 16 +#define M_PB_SEL 0xffU +#define V_PB_SEL(x) ((x) << S_PB_SEL) +#define G_PB_SEL(x) (((x) >> S_PB_SEL) & M_PB_SEL) + +#define S_PB_SELREG 8 +#define M_PB_SELREG 0xffU +#define V_PB_SELREG(x) ((x) << S_PB_SELREG) +#define G_PB_SELREG(x) (((x) >> S_PB_SELREG) & M_PB_SELREG) + +#define S_PB_FUNC 0 +#define M_PB_FUNC 0x7U +#define V_PB_FUNC(x) ((x) << S_PB_FUNC) +#define G_PB_FUNC(x) (((x) >> S_PB_FUNC) & M_PB_FUNC) + +#define A_PCIE_PB_DATA 0x5b98 +#define A_PCIE_CUR_LINK 0x5b9c + +#define S_CFGINITCOEFFDONESEEN 22 +#define V_CFGINITCOEFFDONESEEN(x) ((x) << S_CFGINITCOEFFDONESEEN) +#define F_CFGINITCOEFFDONESEEN V_CFGINITCOEFFDONESEEN(1U) + +#define S_CFGINITCOEFFDONE 21 +#define V_CFGINITCOEFFDONE(x) ((x) << S_CFGINITCOEFFDONE) +#define F_CFGINITCOEFFDONE V_CFGINITCOEFFDONE(1U) + +#define S_XMLH_LINK_UP 20 +#define V_XMLH_LINK_UP(x) ((x) << S_XMLH_LINK_UP) +#define F_XMLH_LINK_UP V_XMLH_LINK_UP(1U) + +#define S_PM_LINKST_IN_L0S 19 +#define V_PM_LINKST_IN_L0S(x) ((x) << S_PM_LINKST_IN_L0S) +#define F_PM_LINKST_IN_L0S V_PM_LINKST_IN_L0S(1U) + +#define S_PM_LINKST_IN_L1 18 +#define V_PM_LINKST_IN_L1(x) ((x) << S_PM_LINKST_IN_L1) +#define F_PM_LINKST_IN_L1 V_PM_LINKST_IN_L1(1U) + +#define S_PM_LINKST_IN_L2 17 +#define V_PM_LINKST_IN_L2(x) ((x) << S_PM_LINKST_IN_L2) +#define F_PM_LINKST_IN_L2 V_PM_LINKST_IN_L2(1U) + +#define S_PM_LINKST_L2_EXIT 16 +#define V_PM_LINKST_L2_EXIT(x) ((x) << S_PM_LINKST_L2_EXIT) +#define F_PM_LINKST_L2_EXIT V_PM_LINKST_L2_EXIT(1U) + +#define S_XMLH_IN_RL0S 15 +#define V_XMLH_IN_RL0S(x) ((x) << S_XMLH_IN_RL0S) +#define F_XMLH_IN_RL0S V_XMLH_IN_RL0S(1U) + +#define S_XMLH_LTSSM_STATE_RCVRY_EQ 14 +#define V_XMLH_LTSSM_STATE_RCVRY_EQ(x) ((x) << S_XMLH_LTSSM_STATE_RCVRY_EQ) +#define F_XMLH_LTSSM_STATE_RCVRY_EQ V_XMLH_LTSSM_STATE_RCVRY_EQ(1U) + +#define S_NEGOTIATEDWIDTH 8 +#define M_NEGOTIATEDWIDTH 0x3fU +#define V_NEGOTIATEDWIDTH(x) ((x) << S_NEGOTIATEDWIDTH) +#define G_NEGOTIATEDWIDTH(x) (((x) >> S_NEGOTIATEDWIDTH) & M_NEGOTIATEDWIDTH) + +#define S_ACTIVELANES 0 +#define M_ACTIVELANES 0xffU +#define V_ACTIVELANES(x) ((x) << S_ACTIVELANES) +#define G_ACTIVELANES(x) (((x) >> S_ACTIVELANES) & M_ACTIVELANES) + +#define A_PCIE_PHY_REQRXPWR 0x5ba0 + +#define S_LNH_RXSTATEDONE 31 +#define V_LNH_RXSTATEDONE(x) ((x) << S_LNH_RXSTATEDONE) +#define F_LNH_RXSTATEDONE V_LNH_RXSTATEDONE(1U) + +#define S_LNH_RXSTATEREQ 30 +#define V_LNH_RXSTATEREQ(x) ((x) << S_LNH_RXSTATEREQ) +#define F_LNH_RXSTATEREQ V_LNH_RXSTATEREQ(1U) + +#define S_LNH_RXPWRSTATE 28 +#define M_LNH_RXPWRSTATE 0x3U +#define V_LNH_RXPWRSTATE(x) ((x) << S_LNH_RXPWRSTATE) +#define G_LNH_RXPWRSTATE(x) (((x) >> S_LNH_RXPWRSTATE) & M_LNH_RXPWRSTATE) + +#define S_LNG_RXSTATEDONE 27 +#define V_LNG_RXSTATEDONE(x) ((x) << S_LNG_RXSTATEDONE) +#define F_LNG_RXSTATEDONE V_LNG_RXSTATEDONE(1U) + +#define S_LNG_RXSTATEREQ 26 +#define V_LNG_RXSTATEREQ(x) ((x) << S_LNG_RXSTATEREQ) +#define F_LNG_RXSTATEREQ V_LNG_RXSTATEREQ(1U) + +#define S_LNG_RXPWRSTATE 24 +#define M_LNG_RXPWRSTATE 0x3U +#define V_LNG_RXPWRSTATE(x) ((x) << S_LNG_RXPWRSTATE) +#define G_LNG_RXPWRSTATE(x) (((x) >> S_LNG_RXPWRSTATE) & M_LNG_RXPWRSTATE) + +#define S_LNF_RXSTATEDONE 23 +#define V_LNF_RXSTATEDONE(x) ((x) << S_LNF_RXSTATEDONE) +#define F_LNF_RXSTATEDONE V_LNF_RXSTATEDONE(1U) + +#define S_LNF_RXSTATEREQ 22 +#define V_LNF_RXSTATEREQ(x) ((x) << S_LNF_RXSTATEREQ) +#define F_LNF_RXSTATEREQ V_LNF_RXSTATEREQ(1U) + +#define S_LNF_RXPWRSTATE 20 +#define M_LNF_RXPWRSTATE 0x3U +#define V_LNF_RXPWRSTATE(x) ((x) << S_LNF_RXPWRSTATE) +#define G_LNF_RXPWRSTATE(x) (((x) >> S_LNF_RXPWRSTATE) & M_LNF_RXPWRSTATE) + +#define S_LNE_RXSTATEDONE 19 +#define V_LNE_RXSTATEDONE(x) ((x) << S_LNE_RXSTATEDONE) +#define F_LNE_RXSTATEDONE V_LNE_RXSTATEDONE(1U) + +#define S_LNE_RXSTATEREQ 18 +#define V_LNE_RXSTATEREQ(x) ((x) << S_LNE_RXSTATEREQ) +#define F_LNE_RXSTATEREQ V_LNE_RXSTATEREQ(1U) + +#define S_LNE_RXPWRSTATE 16 +#define M_LNE_RXPWRSTATE 0x3U +#define V_LNE_RXPWRSTATE(x) ((x) << S_LNE_RXPWRSTATE) +#define G_LNE_RXPWRSTATE(x) (((x) >> S_LNE_RXPWRSTATE) & M_LNE_RXPWRSTATE) + +#define S_LND_RXSTATEDONE 15 +#define V_LND_RXSTATEDONE(x) ((x) << S_LND_RXSTATEDONE) +#define F_LND_RXSTATEDONE V_LND_RXSTATEDONE(1U) + +#define S_LND_RXSTATEREQ 14 +#define V_LND_RXSTATEREQ(x) ((x) << S_LND_RXSTATEREQ) +#define F_LND_RXSTATEREQ V_LND_RXSTATEREQ(1U) + +#define S_LND_RXPWRSTATE 12 +#define M_LND_RXPWRSTATE 0x3U +#define V_LND_RXPWRSTATE(x) ((x) << S_LND_RXPWRSTATE) +#define G_LND_RXPWRSTATE(x) (((x) >> S_LND_RXPWRSTATE) & M_LND_RXPWRSTATE) + +#define S_LNC_RXSTATEDONE 11 +#define V_LNC_RXSTATEDONE(x) ((x) << S_LNC_RXSTATEDONE) +#define F_LNC_RXSTATEDONE V_LNC_RXSTATEDONE(1U) + +#define S_LNC_RXSTATEREQ 10 +#define V_LNC_RXSTATEREQ(x) ((x) << S_LNC_RXSTATEREQ) +#define F_LNC_RXSTATEREQ V_LNC_RXSTATEREQ(1U) + +#define S_LNC_RXPWRSTATE 8 +#define M_LNC_RXPWRSTATE 0x3U +#define V_LNC_RXPWRSTATE(x) ((x) << S_LNC_RXPWRSTATE) +#define G_LNC_RXPWRSTATE(x) (((x) >> S_LNC_RXPWRSTATE) & M_LNC_RXPWRSTATE) + +#define S_LNB_RXSTATEDONE 7 +#define V_LNB_RXSTATEDONE(x) ((x) << S_LNB_RXSTATEDONE) +#define F_LNB_RXSTATEDONE V_LNB_RXSTATEDONE(1U) + +#define S_LNB_RXSTATEREQ 6 +#define V_LNB_RXSTATEREQ(x) ((x) << S_LNB_RXSTATEREQ) +#define F_LNB_RXSTATEREQ V_LNB_RXSTATEREQ(1U) + +#define S_LNB_RXPWRSTATE 4 +#define M_LNB_RXPWRSTATE 0x3U +#define V_LNB_RXPWRSTATE(x) ((x) << S_LNB_RXPWRSTATE) +#define G_LNB_RXPWRSTATE(x) (((x) >> S_LNB_RXPWRSTATE) & M_LNB_RXPWRSTATE) + +#define S_LNA_RXSTATEDONE 3 +#define V_LNA_RXSTATEDONE(x) ((x) << S_LNA_RXSTATEDONE) +#define F_LNA_RXSTATEDONE V_LNA_RXSTATEDONE(1U) + +#define S_LNA_RXSTATEREQ 2 +#define V_LNA_RXSTATEREQ(x) ((x) << S_LNA_RXSTATEREQ) +#define F_LNA_RXSTATEREQ V_LNA_RXSTATEREQ(1U) + +#define S_LNA_RXPWRSTATE 0 +#define M_LNA_RXPWRSTATE 0x3U +#define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE) +#define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE) + +#define A_PCIE_PHY_CURRXPWR 0x5ba4 +#define A_PCIE_PHY_GEN3_AE0 0x5ba8 + +#define S_LND_STAT 28 +#define M_LND_STAT 0x7U +#define V_LND_STAT(x) ((x) << S_LND_STAT) +#define G_LND_STAT(x) (((x) >> S_LND_STAT) & M_LND_STAT) + +#define S_LND_CMD 24 +#define M_LND_CMD 0x7U +#define V_LND_CMD(x) ((x) << S_LND_CMD) +#define G_LND_CMD(x) (((x) >> S_LND_CMD) & M_LND_CMD) + +#define S_LNC_STAT 20 +#define M_LNC_STAT 0x7U +#define V_LNC_STAT(x) ((x) << S_LNC_STAT) +#define G_LNC_STAT(x) (((x) >> S_LNC_STAT) & M_LNC_STAT) + +#define S_LNC_CMD 16 +#define M_LNC_CMD 0x7U +#define V_LNC_CMD(x) ((x) << S_LNC_CMD) +#define G_LNC_CMD(x) (((x) >> S_LNC_CMD) & M_LNC_CMD) + +#define S_LNB_STAT 12 +#define M_LNB_STAT 0x7U +#define V_LNB_STAT(x) ((x) << S_LNB_STAT) +#define G_LNB_STAT(x) (((x) >> S_LNB_STAT) & M_LNB_STAT) + +#define S_LNB_CMD 8 +#define M_LNB_CMD 0x7U +#define V_LNB_CMD(x) ((x) << S_LNB_CMD) +#define G_LNB_CMD(x) (((x) >> S_LNB_CMD) & M_LNB_CMD) + +#define S_LNA_STAT 4 +#define M_LNA_STAT 0x7U +#define V_LNA_STAT(x) ((x) << S_LNA_STAT) +#define G_LNA_STAT(x) (((x) >> S_LNA_STAT) & M_LNA_STAT) + +#define S_LNA_CMD 0 +#define M_LNA_CMD 0x7U +#define V_LNA_CMD(x) ((x) << S_LNA_CMD) +#define G_LNA_CMD(x) (((x) >> S_LNA_CMD) & M_LNA_CMD) + +#define A_PCIE_PHY_GEN3_AE1 0x5bac + +#define S_LNH_STAT 28 +#define M_LNH_STAT 0x7U +#define V_LNH_STAT(x) ((x) << S_LNH_STAT) +#define G_LNH_STAT(x) (((x) >> S_LNH_STAT) & M_LNH_STAT) + +#define S_LNH_CMD 24 +#define M_LNH_CMD 0x7U +#define V_LNH_CMD(x) ((x) << S_LNH_CMD) +#define G_LNH_CMD(x) (((x) >> S_LNH_CMD) & M_LNH_CMD) + +#define S_LNG_STAT 20 +#define M_LNG_STAT 0x7U +#define V_LNG_STAT(x) ((x) << S_LNG_STAT) +#define G_LNG_STAT(x) (((x) >> S_LNG_STAT) & M_LNG_STAT) + +#define S_LNG_CMD 16 +#define M_LNG_CMD 0x7U +#define V_LNG_CMD(x) ((x) << S_LNG_CMD) +#define G_LNG_CMD(x) (((x) >> S_LNG_CMD) & M_LNG_CMD) + +#define S_LNF_STAT 12 +#define M_LNF_STAT 0x7U +#define V_LNF_STAT(x) ((x) << S_LNF_STAT) +#define G_LNF_STAT(x) (((x) >> S_LNF_STAT) & M_LNF_STAT) + +#define S_LNF_CMD 8 +#define M_LNF_CMD 0x7U +#define V_LNF_CMD(x) ((x) << S_LNF_CMD) +#define G_LNF_CMD(x) (((x) >> S_LNF_CMD) & M_LNF_CMD) + +#define S_LNE_STAT 4 +#define M_LNE_STAT 0x7U +#define V_LNE_STAT(x) ((x) << S_LNE_STAT) +#define G_LNE_STAT(x) (((x) >> S_LNE_STAT) & M_LNE_STAT) + +#define S_LNE_CMD 0 +#define M_LNE_CMD 0x7U +#define V_LNE_CMD(x) ((x) << S_LNE_CMD) +#define G_LNE_CMD(x) (((x) >> S_LNE_CMD) & M_LNE_CMD) + +#define A_PCIE_PHY_FS_LF0 0x5bb0 + +#define S_LANE1LF 24 +#define M_LANE1LF 0x3fU +#define V_LANE1LF(x) ((x) << S_LANE1LF) +#define G_LANE1LF(x) (((x) >> S_LANE1LF) & M_LANE1LF) + +#define S_LANE1FS 16 +#define M_LANE1FS 0x3fU +#define V_LANE1FS(x) ((x) << S_LANE1FS) +#define G_LANE1FS(x) (((x) >> S_LANE1FS) & M_LANE1FS) + +#define S_LANE0LF 8 +#define M_LANE0LF 0x3fU +#define V_LANE0LF(x) ((x) << S_LANE0LF) +#define G_LANE0LF(x) (((x) >> S_LANE0LF) & M_LANE0LF) + +#define S_LANE0FS 0 +#define M_LANE0FS 0x3fU +#define V_LANE0FS(x) ((x) << S_LANE0FS) +#define G_LANE0FS(x) (((x) >> S_LANE0FS) & M_LANE0FS) + +#define A_PCIE_PHY_FS_LF1 0x5bb4 + +#define S_LANE3LF 24 +#define M_LANE3LF 0x3fU +#define V_LANE3LF(x) ((x) << S_LANE3LF) +#define G_LANE3LF(x) (((x) >> S_LANE3LF) & M_LANE3LF) + +#define S_LANE3FS 16 +#define M_LANE3FS 0x3fU +#define V_LANE3FS(x) ((x) << S_LANE3FS) +#define G_LANE3FS(x) (((x) >> S_LANE3FS) & M_LANE3FS) + +#define S_LANE2LF 8 +#define M_LANE2LF 0x3fU +#define V_LANE2LF(x) ((x) << S_LANE2LF) +#define G_LANE2LF(x) (((x) >> S_LANE2LF) & M_LANE2LF) + +#define S_LANE2FS 0 +#define M_LANE2FS 0x3fU +#define V_LANE2FS(x) ((x) << S_LANE2FS) +#define G_LANE2FS(x) (((x) >> S_LANE2FS) & M_LANE2FS) + +#define A_PCIE_PHY_FS_LF2 0x5bb8 + +#define S_LANE5LF 24 +#define M_LANE5LF 0x3fU +#define V_LANE5LF(x) ((x) << S_LANE5LF) +#define G_LANE5LF(x) (((x) >> S_LANE5LF) & M_LANE5LF) + +#define S_LANE5FS 16 +#define M_LANE5FS 0x3fU +#define V_LANE5FS(x) ((x) << S_LANE5FS) +#define G_LANE5FS(x) (((x) >> S_LANE5FS) & M_LANE5FS) + +#define S_LANE4LF 8 +#define M_LANE4LF 0x3fU +#define V_LANE4LF(x) ((x) << S_LANE4LF) +#define G_LANE4LF(x) (((x) >> S_LANE4LF) & M_LANE4LF) + +#define S_LANE4FS 0 +#define M_LANE4FS 0x3fU +#define V_LANE4FS(x) ((x) << S_LANE4FS) +#define G_LANE4FS(x) (((x) >> S_LANE4FS) & M_LANE4FS) + +#define A_PCIE_PHY_FS_LF3 0x5bbc + +#define S_LANE7LF 24 +#define M_LANE7LF 0x3fU +#define V_LANE7LF(x) ((x) << S_LANE7LF) +#define G_LANE7LF(x) (((x) >> S_LANE7LF) & M_LANE7LF) + +#define S_LANE7FS 16 +#define M_LANE7FS 0x3fU +#define V_LANE7FS(x) ((x) << S_LANE7FS) +#define G_LANE7FS(x) (((x) >> S_LANE7FS) & M_LANE7FS) + +#define S_LANE6LF 8 +#define M_LANE6LF 0x3fU +#define V_LANE6LF(x) ((x) << S_LANE6LF) +#define G_LANE6LF(x) (((x) >> S_LANE6LF) & M_LANE6LF) + +#define S_LANE6FS 0 +#define M_LANE6FS 0x3fU +#define V_LANE6FS(x) ((x) << S_LANE6FS) +#define G_LANE6FS(x) (((x) >> S_LANE6FS) & M_LANE6FS) + +#define A_PCIE_PHY_PRESET_REQ 0x5bc0 + +#define S_COEFFDONE 16 +#define V_COEFFDONE(x) ((x) << S_COEFFDONE) +#define F_COEFFDONE V_COEFFDONE(1U) + +#define S_COEFFLANE 8 +#define M_COEFFLANE 0x7U +#define V_COEFFLANE(x) ((x) << S_COEFFLANE) +#define G_COEFFLANE(x) (((x) >> S_COEFFLANE) & M_COEFFLANE) + +#define S_COEFFSTART 0 +#define V_COEFFSTART(x) ((x) << S_COEFFSTART) +#define F_COEFFSTART V_COEFFSTART(1U) + +#define A_PCIE_PHY_PRESET_COEFF 0x5bc4 + +#define S_COEFF 0 +#define M_COEFF 0x3ffffU +#define V_COEFF(x) ((x) << S_COEFF) +#define G_COEFF(x) (((x) >> S_COEFF) & M_COEFF) + +#define A_PCIE_PHY_INDIR_REQ 0x5bf0 + +#define S_PHYENABLE 31 +#define V_PHYENABLE(x) ((x) << S_PHYENABLE) +#define F_PHYENABLE V_PHYENABLE(1U) + +#define S_PCIE_PHY_REGADDR 0 +#define M_PCIE_PHY_REGADDR 0xffffU +#define V_PCIE_PHY_REGADDR(x) ((x) << S_PCIE_PHY_REGADDR) +#define G_PCIE_PHY_REGADDR(x) (((x) >> S_PCIE_PHY_REGADDR) & M_PCIE_PHY_REGADDR) + +#define A_PCIE_PHY_INDIR_DATA 0x5bf4 +#define A_PCIE_STATIC_SPARE1 0x5bf8 +#define A_PCIE_STATIC_SPARE2 0x5bfc + /* registers for module DBG */ #define DBG_BASE_ADDR 0x6000 @@ -3500,6 +7384,11 @@ #define A_DBG_DBG1_CFG 0x6008 #define A_DBG_DBG1_EN 0x600c + +#define S_CLK_EN_ON_DBG1 20 +#define V_CLK_EN_ON_DBG1(x) ((x) << S_CLK_EN_ON_DBG1) +#define F_CLK_EN_ON_DBG1 V_CLK_EN_ON_DBG1(1U) + #define A_DBG_GPIO_EN 0x6010 #define S_GPIO15_OEN 31 @@ -3866,6 +7755,22 @@ #define V_GPIO0(x) ((x) << S_GPIO0) #define F_GPIO0 V_GPIO0(1U) +#define S_GPIO19 29 +#define V_GPIO19(x) ((x) << S_GPIO19) +#define F_GPIO19 V_GPIO19(1U) + +#define S_GPIO18 28 +#define V_GPIO18(x) ((x) << S_GPIO18) +#define F_GPIO18 V_GPIO18(1U) + +#define S_GPIO17 27 +#define V_GPIO17(x) ((x) << S_GPIO17) +#define F_GPIO17 V_GPIO17(1U) + +#define S_GPIO16 26 +#define V_GPIO16(x) ((x) << S_GPIO16) +#define F_GPIO16 V_GPIO16(1U) + #define A_DBG_INT_CAUSE 0x601c #define S_IBM_FDL_FAIL_INT_CAUSE 25 @@ -4039,6 +7944,22 @@ #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW) #define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U) +#define S_GPIO19_ACT_LOW 25 +#define V_GPIO19_ACT_LOW(x) ((x) << S_GPIO19_ACT_LOW) +#define F_GPIO19_ACT_LOW V_GPIO19_ACT_LOW(1U) + +#define S_GPIO18_ACT_LOW 24 +#define V_GPIO18_ACT_LOW(x) ((x) << S_GPIO18_ACT_LOW) +#define F_GPIO18_ACT_LOW V_GPIO18_ACT_LOW(1U) + +#define S_GPIO17_ACT_LOW 23 +#define V_GPIO17_ACT_LOW(x) ((x) << S_GPIO17_ACT_LOW) +#define F_GPIO17_ACT_LOW V_GPIO17_ACT_LOW(1U) + +#define S_GPIO16_ACT_LOW 22 +#define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW) +#define F_GPIO16_ACT_LOW V_GPIO16_ACT_LOW(1U) + #define A_DBG_EFUSE_BYTE0_3 0x6034 #define A_DBG_EFUSE_BYTE4_7 0x6038 #define A_DBG_EFUSE_BYTE8_11 0x603c @@ -4322,6 +8243,11 @@ #define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL) #define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL) +#define S_T5_P_OCLK_MUXSEL 13 +#define M_T5_P_OCLK_MUXSEL 0xfU +#define V_T5_P_OCLK_MUXSEL(x) ((x) << S_T5_P_OCLK_MUXSEL) +#define G_T5_P_OCLK_MUXSEL(x) (((x) >> S_T5_P_OCLK_MUXSEL) & M_T5_P_OCLK_MUXSEL) + #define A_DBG_TRACE0_CONF_COMPREG0 0x6060 #define A_DBG_TRACE0_CONF_COMPREG1 0x6064 #define A_DBG_TRACE1_CONF_COMPREG0 0x6068 @@ -4411,6 +8337,571 @@ #define A_DBG_TRACE0_DATA_OUT 0x6094 #define A_DBG_TRACE1_DATA_OUT 0x6098 +#define A_DBG_FUSE_SENSE_DONE 0x609c + +#define S_STATIC_JTAG_VERSIONNR 5 +#define M_STATIC_JTAG_VERSIONNR 0xfU +#define V_STATIC_JTAG_VERSIONNR(x) ((x) << S_STATIC_JTAG_VERSIONNR) +#define G_STATIC_JTAG_VERSIONNR(x) \ + (((x) >> S_STATIC_JTAG_VERSIONNR) & M_STATIC_JTAG_VERSIONNR) + +#define S_UNQ0 1 +#define M_UNQ0 0xfU +#define V_UNQ0(x) ((x) << S_UNQ0) +#define G_UNQ0(x) (((x) >> S_UNQ0) & M_UNQ0) + +#define S_FUSE_DONE_SENSE 0 +#define V_FUSE_DONE_SENSE(x) ((x) << S_FUSE_DONE_SENSE) +#define F_FUSE_DONE_SENSE V_FUSE_DONE_SENSE(1U) + +#define A_DBG_TVSENSE_EN 0x60a8 + +#define S_MCIMPED1_OUT 29 +#define V_MCIMPED1_OUT(x) ((x) << S_MCIMPED1_OUT) +#define F_MCIMPED1_OUT V_MCIMPED1_OUT(1U) + +#define S_MCIMPED2_OUT 28 +#define V_MCIMPED2_OUT(x) ((x) << S_MCIMPED2_OUT) +#define F_MCIMPED2_OUT V_MCIMPED2_OUT(1U) + +#define S_TVSENSE_SNSOUT 17 +#define M_TVSENSE_SNSOUT 0x1ffU +#define V_TVSENSE_SNSOUT(x) ((x) << S_TVSENSE_SNSOUT) +#define G_TVSENSE_SNSOUT(x) (((x) >> S_TVSENSE_SNSOUT) & M_TVSENSE_SNSOUT) + +#define S_TVSENSE_OUTPUTVALID 16 +#define V_TVSENSE_OUTPUTVALID(x) ((x) << S_TVSENSE_OUTPUTVALID) +#define F_TVSENSE_OUTPUTVALID V_TVSENSE_OUTPUTVALID(1U) + +#define S_TVSENSE_SLEEP 10 +#define V_TVSENSE_SLEEP(x) ((x) << S_TVSENSE_SLEEP) +#define F_TVSENSE_SLEEP V_TVSENSE_SLEEP(1U) + +#define S_TVSENSE_SENSV 9 +#define V_TVSENSE_SENSV(x) ((x) << S_TVSENSE_SENSV) +#define F_TVSENSE_SENSV V_TVSENSE_SENSV(1U) + +#define S_TVSENSE_RST 8 +#define V_TVSENSE_RST(x) ((x) << S_TVSENSE_RST) +#define F_TVSENSE_RST V_TVSENSE_RST(1U) + +#define S_TVSENSE_RATIO 0 +#define M_TVSENSE_RATIO 0xffU +#define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO) +#define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO) + +#define A_DBG_CUST_EFUSE_OUT_EN 0x60ac +#define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0 +#define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4 + +#define S_DBG_FEENABLE 29 +#define V_DBG_FEENABLE(x) ((x) << S_DBG_FEENABLE) +#define F_DBG_FEENABLE V_DBG_FEENABLE(1U) + +#define S_DBG_FEF 23 +#define M_DBG_FEF 0x3fU +#define V_DBG_FEF(x) ((x) << S_DBG_FEF) +#define G_DBG_FEF(x) (((x) >> S_DBG_FEF) & M_DBG_FEF) + +#define S_DBG_FEMIMICN 22 +#define V_DBG_FEMIMICN(x) ((x) << S_DBG_FEMIMICN) +#define F_DBG_FEMIMICN V_DBG_FEMIMICN(1U) + +#define S_DBG_FEGATEC 21 +#define V_DBG_FEGATEC(x) ((x) << S_DBG_FEGATEC) +#define F_DBG_FEGATEC V_DBG_FEGATEC(1U) + +#define S_DBG_FEPROGP 20 +#define V_DBG_FEPROGP(x) ((x) << S_DBG_FEPROGP) +#define F_DBG_FEPROGP V_DBG_FEPROGP(1U) + +#define S_DBG_FEREADCLK 19 +#define V_DBG_FEREADCLK(x) ((x) << S_DBG_FEREADCLK) +#define F_DBG_FEREADCLK V_DBG_FEREADCLK(1U) + +#define S_DBG_FERSEL 3 +#define M_DBG_FERSEL 0xffffU +#define V_DBG_FERSEL(x) ((x) << S_DBG_FERSEL) +#define G_DBG_FERSEL(x) (((x) >> S_DBG_FERSEL) & M_DBG_FERSEL) + +#define S_DBG_FETIME 0 +#define M_DBG_FETIME 0x7U +#define V_DBG_FETIME(x) ((x) << S_DBG_FETIME) +#define G_DBG_FETIME(x) (((x) >> S_DBG_FETIME) & M_DBG_FETIME) + +#define A_DBG_T5_STATIC_M_PLL_CONF1 0x60b8 + +#define S_T5_STATIC_M_PLL_MULTFRAC 8 +#define M_T5_STATIC_M_PLL_MULTFRAC 0xffffffU +#define V_T5_STATIC_M_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_M_PLL_MULTFRAC) +#define G_T5_STATIC_M_PLL_MULTFRAC(x) \ + (((x) >> S_T5_STATIC_M_PLL_MULTFRAC) & M_T5_STATIC_M_PLL_MULTFRAC) + +#define S_T5_STATIC_M_PLL_FFSLEWRATE 0 +#define M_T5_STATIC_M_PLL_FFSLEWRATE 0xffU +#define V_T5_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_M_PLL_FFSLEWRATE) +#define G_T5_STATIC_M_PLL_FFSLEWRATE(x) \ + (((x) >> S_T5_STATIC_M_PLL_FFSLEWRATE) & M_T5_STATIC_M_PLL_FFSLEWRATE) + +#define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc + +#define S_T5_STATIC_M_PLL_DCO_BYPASS 23 +#define V_T5_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_DCO_BYPASS) +#define F_T5_STATIC_M_PLL_DCO_BYPASS V_T5_STATIC_M_PLL_DCO_BYPASS(1U) + +#define S_T5_STATIC_M_PLL_SDORDER 21 +#define M_T5_STATIC_M_PLL_SDORDER 0x3U +#define V_T5_STATIC_M_PLL_SDORDER(x) ((x) << S_T5_STATIC_M_PLL_SDORDER) +#define G_T5_STATIC_M_PLL_SDORDER(x) \ + (((x) >> S_T5_STATIC_M_PLL_SDORDER) & M_T5_STATIC_M_PLL_SDORDER) + +#define S_T5_STATIC_M_PLL_FFENABLE 20 +#define V_T5_STATIC_M_PLL_FFENABLE(x) ((x) << S_T5_STATIC_M_PLL_FFENABLE) +#define F_T5_STATIC_M_PLL_FFENABLE V_T5_STATIC_M_PLL_FFENABLE(1U) + +#define S_T5_STATIC_M_PLL_STOPCLKB 19 +#define V_T5_STATIC_M_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKB) +#define F_T5_STATIC_M_PLL_STOPCLKB V_T5_STATIC_M_PLL_STOPCLKB(1U) + +#define S_T5_STATIC_M_PLL_STOPCLKA 18 +#define V_T5_STATIC_M_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKA) +#define F_T5_STATIC_M_PLL_STOPCLKA V_T5_STATIC_M_PLL_STOPCLKA(1U) + +#define S_T5_STATIC_M_PLL_SLEEP 17 +#define V_T5_STATIC_M_PLL_SLEEP(x) ((x) << S_T5_STATIC_M_PLL_SLEEP) +#define F_T5_STATIC_M_PLL_SLEEP V_T5_STATIC_M_PLL_SLEEP(1U) + +#define S_T5_STATIC_M_PLL_BYPASS 16 +#define V_T5_STATIC_M_PLL_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_BYPASS) +#define F_T5_STATIC_M_PLL_BYPASS V_T5_STATIC_M_PLL_BYPASS(1U) + +#define S_T5_STATIC_M_PLL_LOCKTUNE 0 +#define M_T5_STATIC_M_PLL_LOCKTUNE 0xffffU +#define V_T5_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_M_PLL_LOCKTUNE) +#define G_T5_STATIC_M_PLL_LOCKTUNE(x) \ + (((x) >> S_T5_STATIC_M_PLL_LOCKTUNE) & M_T5_STATIC_M_PLL_LOCKTUNE) + +#define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0 + +#define S_T5_STATIC_M_PLL_MULTPRE 30 +#define M_T5_STATIC_M_PLL_MULTPRE 0x3U +#define V_T5_STATIC_M_PLL_MULTPRE(x) ((x) << S_T5_STATIC_M_PLL_MULTPRE) +#define G_T5_STATIC_M_PLL_MULTPRE(x) \ + (((x) >> S_T5_STATIC_M_PLL_MULTPRE) & M_T5_STATIC_M_PLL_MULTPRE) + +#define S_T5_STATIC_M_PLL_LOCKSEL 28 +#define M_T5_STATIC_M_PLL_LOCKSEL 0x3U +#define V_T5_STATIC_M_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_M_PLL_LOCKSEL) +#define G_T5_STATIC_M_PLL_LOCKSEL(x) \ + (((x) >> S_T5_STATIC_M_PLL_LOCKSEL) & M_T5_STATIC_M_PLL_LOCKSEL) + +#define S_T5_STATIC_M_PLL_FFTUNE 12 +#define M_T5_STATIC_M_PLL_FFTUNE 0xffffU +#define V_T5_STATIC_M_PLL_FFTUNE(x) ((x) << S_T5_STATIC_M_PLL_FFTUNE) +#define G_T5_STATIC_M_PLL_FFTUNE(x) \ + (((x) >> S_T5_STATIC_M_PLL_FFTUNE) & M_T5_STATIC_M_PLL_FFTUNE) + +#define S_T5_STATIC_M_PLL_RANGEPRE 10 +#define M_T5_STATIC_M_PLL_RANGEPRE 0x3U +#define V_T5_STATIC_M_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_M_PLL_RANGEPRE) +#define G_T5_STATIC_M_PLL_RANGEPRE(x) \ + (((x) >> S_T5_STATIC_M_PLL_RANGEPRE) & M_T5_STATIC_M_PLL_RANGEPRE) + +#define S_T5_STATIC_M_PLL_RANGEB 5 +#define M_T5_STATIC_M_PLL_RANGEB 0x1fU +#define V_T5_STATIC_M_PLL_RANGEB(x) ((x) << S_T5_STATIC_M_PLL_RANGEB) +#define G_T5_STATIC_M_PLL_RANGEB(x) \ + (((x) >> S_T5_STATIC_M_PLL_RANGEB) & M_T5_STATIC_M_PLL_RANGEB) + +#define S_T5_STATIC_M_PLL_RANGEA 0 +#define M_T5_STATIC_M_PLL_RANGEA 0x1fU +#define V_T5_STATIC_M_PLL_RANGEA(x) ((x) << S_T5_STATIC_M_PLL_RANGEA) +#define G_T5_STATIC_M_PLL_RANGEA(x) \ + (((x) >> S_T5_STATIC_M_PLL_RANGEA) & M_T5_STATIC_M_PLL_RANGEA) + +#define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4 +#define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8 + +#define S_T5_STATIC_M_PLL_VCVTUNE 24 +#define M_T5_STATIC_M_PLL_VCVTUNE 0x7U +#define V_T5_STATIC_M_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_M_PLL_VCVTUNE) +#define G_T5_STATIC_M_PLL_VCVTUNE(x) \ + (((x) >> S_T5_STATIC_M_PLL_VCVTUNE) & M_T5_STATIC_M_PLL_VCVTUNE) + +#define S_T5_STATIC_M_PLL_RESET 23 +#define V_T5_STATIC_M_PLL_RESET(x) ((x) << S_T5_STATIC_M_PLL_RESET) +#define F_T5_STATIC_M_PLL_RESET V_T5_STATIC_M_PLL_RESET(1U) + +#define S_T5_STATIC_MPLL_REFCLK_SEL 22 +#define V_T5_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_T5_STATIC_MPLL_REFCLK_SEL) +#define F_T5_STATIC_MPLL_REFCLK_SEL V_T5_STATIC_MPLL_REFCLK_SEL(1U) + +#define S_T5_STATIC_M_PLL_LFTUNE_32_40 13 +#define M_T5_STATIC_M_PLL_LFTUNE_32_40 0x1ffU +#define V_T5_STATIC_M_PLL_LFTUNE_32_40(x) \ + ((x) << S_T5_STATIC_M_PLL_LFTUNE_32_40) +#define G_T5_STATIC_M_PLL_LFTUNE_32_40(x) \ + (((x) >> S_T5_STATIC_M_PLL_LFTUNE_32_40) & \ + M_T5_STATIC_M_PLL_LFTUNE_32_40) + +#define S_T5_STATIC_M_PLL_PREDIV 8 +#define M_T5_STATIC_M_PLL_PREDIV 0x1fU +#define V_T5_STATIC_M_PLL_PREDIV(x) ((x) << S_T5_STATIC_M_PLL_PREDIV) +#define G_T5_STATIC_M_PLL_PREDIV(x) \ + (((x) >> S_T5_STATIC_M_PLL_PREDIV) & M_T5_STATIC_M_PLL_PREDIV) + +#define S_T5_STATIC_M_PLL_MULT 0 +#define M_T5_STATIC_M_PLL_MULT 0xffU +#define V_T5_STATIC_M_PLL_MULT(x) ((x) << S_T5_STATIC_M_PLL_MULT) +#define G_T5_STATIC_M_PLL_MULT(x) \ + (((x) >> S_T5_STATIC_M_PLL_MULT) & M_T5_STATIC_M_PLL_MULT) + +#define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc + +#define S_T5_STATIC_PHY0RECRST_ 5 +#define V_T5_STATIC_PHY0RECRST_(x) ((x) << S_T5_STATIC_PHY0RECRST_) +#define F_T5_STATIC_PHY0RECRST_ V_T5_STATIC_PHY0RECRST_(1U) + +#define S_T5_STATIC_PHY1RECRST_ 4 +#define V_T5_STATIC_PHY1RECRST_(x) ((x) << S_T5_STATIC_PHY1RECRST_) +#define F_T5_STATIC_PHY1RECRST_ V_T5_STATIC_PHY1RECRST_(1U) + +#define S_T5_STATIC_SWMC0RST_ 3 +#define V_T5_STATIC_SWMC0RST_(x) ((x) << S_T5_STATIC_SWMC0RST_) +#define F_T5_STATIC_SWMC0RST_ V_T5_STATIC_SWMC0RST_(1U) + +#define S_T5_STATIC_SWMC0CFGRST_ 2 +#define V_T5_STATIC_SWMC0CFGRST_(x) ((x) << S_T5_STATIC_SWMC0CFGRST_) +#define F_T5_STATIC_SWMC0CFGRST_ V_T5_STATIC_SWMC0CFGRST_(1U) + +#define S_T5_STATIC_SWMC1RST_ 1 +#define V_T5_STATIC_SWMC1RST_(x) ((x) << S_T5_STATIC_SWMC1RST_) +#define F_T5_STATIC_SWMC1RST_ V_T5_STATIC_SWMC1RST_(1U) + +#define S_T5_STATIC_SWMC1CFGRST_ 0 +#define V_T5_STATIC_SWMC1CFGRST_(x) ((x) << S_T5_STATIC_SWMC1CFGRST_) +#define F_T5_STATIC_SWMC1CFGRST_ V_T5_STATIC_SWMC1CFGRST_(1U) + +#define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0 + +#define S_T5_STATIC_C_PLL_MULTFRAC 8 +#define M_T5_STATIC_C_PLL_MULTFRAC 0xffffffU +#define V_T5_STATIC_C_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_C_PLL_MULTFRAC) +#define G_T5_STATIC_C_PLL_MULTFRAC(x) \ + (((x) >> S_T5_STATIC_C_PLL_MULTFRAC) & M_T5_STATIC_C_PLL_MULTFRAC) + +#define S_T5_STATIC_C_PLL_FFSLEWRATE 0 +#define M_T5_STATIC_C_PLL_FFSLEWRATE 0xffU +#define V_T5_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_C_PLL_FFSLEWRATE) +#define G_T5_STATIC_C_PLL_FFSLEWRATE(x) \ + (((x) >> S_T5_STATIC_C_PLL_FFSLEWRATE) & M_T5_STATIC_C_PLL_FFSLEWRATE) + +#define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4 + +#define S_T5_STATIC_C_PLL_DCO_BYPASS 23 +#define V_T5_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_DCO_BYPASS) +#define F_T5_STATIC_C_PLL_DCO_BYPASS V_T5_STATIC_C_PLL_DCO_BYPASS(1U) + +#define S_T5_STATIC_C_PLL_SDORDER 21 +#define M_T5_STATIC_C_PLL_SDORDER 0x3U +#define V_T5_STATIC_C_PLL_SDORDER(x) ((x) << S_T5_STATIC_C_PLL_SDORDER) +#define G_T5_STATIC_C_PLL_SDORDER(x) \ + (((x) >> S_T5_STATIC_C_PLL_SDORDER) & M_T5_STATIC_C_PLL_SDORDER) + +#define S_T5_STATIC_C_PLL_FFENABLE 20 +#define V_T5_STATIC_C_PLL_FFENABLE(x) ((x) << S_T5_STATIC_C_PLL_FFENABLE) +#define F_T5_STATIC_C_PLL_FFENABLE V_T5_STATIC_C_PLL_FFENABLE(1U) + +#define S_T5_STATIC_C_PLL_STOPCLKB 19 +#define V_T5_STATIC_C_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKB) +#define F_T5_STATIC_C_PLL_STOPCLKB V_T5_STATIC_C_PLL_STOPCLKB(1U) + +#define S_T5_STATIC_C_PLL_STOPCLKA 18 +#define V_T5_STATIC_C_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKA) +#define F_T5_STATIC_C_PLL_STOPCLKA V_T5_STATIC_C_PLL_STOPCLKA(1U) + +#define S_T5_STATIC_C_PLL_SLEEP 17 +#define V_T5_STATIC_C_PLL_SLEEP(x) ((x) << S_T5_STATIC_C_PLL_SLEEP) +#define F_T5_STATIC_C_PLL_SLEEP V_T5_STATIC_C_PLL_SLEEP(1U) + +#define S_T5_STATIC_C_PLL_BYPASS 16 +#define V_T5_STATIC_C_PLL_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_BYPASS) +#define F_T5_STATIC_C_PLL_BYPASS V_T5_STATIC_C_PLL_BYPASS(1U) + +#define S_T5_STATIC_C_PLL_LOCKTUNE 0 +#define M_T5_STATIC_C_PLL_LOCKTUNE 0xffffU +#define V_T5_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_C_PLL_LOCKTUNE) +#define G_T5_STATIC_C_PLL_LOCKTUNE(x) \ + (((x) >> S_T5_STATIC_C_PLL_LOCKTUNE) & M_T5_STATIC_C_PLL_LOCKTUNE) + +#define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8 + +#define S_T5_STATIC_C_PLL_MULTPRE 30 +#define M_T5_STATIC_C_PLL_MULTPRE 0x3U +#define V_T5_STATIC_C_PLL_MULTPRE(x) ((x) << S_T5_STATIC_C_PLL_MULTPRE) +#define G_T5_STATIC_C_PLL_MULTPRE(x) \ + (((x) >> S_T5_STATIC_C_PLL_MULTPRE) & M_T5_STATIC_C_PLL_MULTPRE) + +#define S_T5_STATIC_C_PLL_LOCKSEL 28 +#define M_T5_STATIC_C_PLL_LOCKSEL 0x3U +#define V_T5_STATIC_C_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_C_PLL_LOCKSEL) +#define G_T5_STATIC_C_PLL_LOCKSEL(x) \ + (((x) >> S_T5_STATIC_C_PLL_LOCKSEL) & M_T5_STATIC_C_PLL_LOCKSEL) + +#define S_T5_STATIC_C_PLL_FFTUNE 12 +#define M_T5_STATIC_C_PLL_FFTUNE 0xffffU +#define V_T5_STATIC_C_PLL_FFTUNE(x) ((x) << S_T5_STATIC_C_PLL_FFTUNE) +#define G_T5_STATIC_C_PLL_FFTUNE(x) \ + (((x) >> S_T5_STATIC_C_PLL_FFTUNE) & M_T5_STATIC_C_PLL_FFTUNE) + +#define S_T5_STATIC_C_PLL_RANGEPRE 10 +#define M_T5_STATIC_C_PLL_RANGEPRE 0x3U +#define V_T5_STATIC_C_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_C_PLL_RANGEPRE) +#define G_T5_STATIC_C_PLL_RANGEPRE(x) \ + (((x) >> S_T5_STATIC_C_PLL_RANGEPRE) & M_T5_STATIC_C_PLL_RANGEPRE) + +#define S_T5_STATIC_C_PLL_RANGEB 5 +#define M_T5_STATIC_C_PLL_RANGEB 0x1fU +#define V_T5_STATIC_C_PLL_RANGEB(x) ((x) << S_T5_STATIC_C_PLL_RANGEB) +#define G_T5_STATIC_C_PLL_RANGEB(x) \ + (((x) >> S_T5_STATIC_C_PLL_RANGEB) & M_T5_STATIC_C_PLL_RANGEB) + +#define S_T5_STATIC_C_PLL_RANGEA 0 +#define M_T5_STATIC_C_PLL_RANGEA 0x1fU +#define V_T5_STATIC_C_PLL_RANGEA(x) ((x) << S_T5_STATIC_C_PLL_RANGEA) +#define G_T5_STATIC_C_PLL_RANGEA(x) \ + (((x) >> S_T5_STATIC_C_PLL_RANGEA) & M_T5_STATIC_C_PLL_RANGEA) + +#define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc +#define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0 + +#define S_T5_STATIC_C_PLL_VCVTUNE 22 +#define M_T5_STATIC_C_PLL_VCVTUNE 0x7U +#define V_T5_STATIC_C_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_C_PLL_VCVTUNE) +#define G_T5_STATIC_C_PLL_VCVTUNE(x) \ + (((x) >> S_T5_STATIC_C_PLL_VCVTUNE) & M_T5_STATIC_C_PLL_VCVTUNE) + +#define S_T5_STATIC_C_PLL_LFTUNE_32_40 13 +#define M_T5_STATIC_C_PLL_LFTUNE_32_40 0x1ffU +#define V_T5_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_C_PLL_LFTUNE_32_40) +#define G_T5_STATIC_C_PLL_LFTUNE_32_40(x) \ + (((x) >> S_T5_STATIC_C_PLL_LFTUNE_32_40) & \ + M_T5_STATIC_C_PLL_LFTUNE_32_40) + +#define S_T5_STATIC_C_PLL_PREDIV 8 +#define M_T5_STATIC_C_PLL_PREDIV 0x1fU +#define V_T5_STATIC_C_PLL_PREDIV(x) ((x) << S_T5_STATIC_C_PLL_PREDIV) +#define G_T5_STATIC_C_PLL_PREDIV(x) \ + (((x) >> S_T5_STATIC_C_PLL_PREDIV) & M_T5_STATIC_C_PLL_PREDIV) + +#define S_T5_STATIC_C_PLL_MULT 0 +#define M_T5_STATIC_C_PLL_MULT 0xffU +#define V_T5_STATIC_C_PLL_MULT(x) ((x) << S_T5_STATIC_C_PLL_MULT) +#define G_T5_STATIC_C_PLL_MULT(x) \ + (((x) >> S_T5_STATIC_C_PLL_MULT) & M_T5_STATIC_C_PLL_MULT) + +#define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4 + +#define S_T5_STATIC_U_PLL_MULTFRAC 8 +#define M_T5_STATIC_U_PLL_MULTFRAC 0xffffffU +#define V_T5_STATIC_U_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_U_PLL_MULTFRAC) +#define G_T5_STATIC_U_PLL_MULTFRAC(x) \ + (((x) >> S_T5_STATIC_U_PLL_MULTFRAC) & M_T5_STATIC_U_PLL_MULTFRAC) + +#define S_T5_STATIC_U_PLL_FFSLEWRATE 0 +#define M_T5_STATIC_U_PLL_FFSLEWRATE 0xffU +#define V_T5_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_U_PLL_FFSLEWRATE) +#define G_T5_STATIC_U_PLL_FFSLEWRATE(x) \ + (((x) >> S_T5_STATIC_U_PLL_FFSLEWRATE) & M_T5_STATIC_U_PLL_FFSLEWRATE) + +#define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8 + +#define S_T5_STATIC_U_PLL_DCO_BYPASS 23 +#define V_T5_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_DCO_BYPASS) +#define F_T5_STATIC_U_PLL_DCO_BYPASS V_T5_STATIC_U_PLL_DCO_BYPASS(1U) + +#define S_T5_STATIC_U_PLL_SDORDER 21 +#define M_T5_STATIC_U_PLL_SDORDER 0x3U +#define V_T5_STATIC_U_PLL_SDORDER(x) ((x) << S_T5_STATIC_U_PLL_SDORDER) +#define G_T5_STATIC_U_PLL_SDORDER(x) \ + (((x) >> S_T5_STATIC_U_PLL_SDORDER) & M_T5_STATIC_U_PLL_SDORDER) + +#define S_T5_STATIC_U_PLL_FFENABLE 20 +#define V_T5_STATIC_U_PLL_FFENABLE(x) ((x) << S_T5_STATIC_U_PLL_FFENABLE) +#define F_T5_STATIC_U_PLL_FFENABLE V_T5_STATIC_U_PLL_FFENABLE(1U) + +#define S_T5_STATIC_U_PLL_STOPCLKB 19 +#define V_T5_STATIC_U_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKB) +#define F_T5_STATIC_U_PLL_STOPCLKB V_T5_STATIC_U_PLL_STOPCLKB(1U) + +#define S_T5_STATIC_U_PLL_STOPCLKA 18 +#define V_T5_STATIC_U_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKA) +#define F_T5_STATIC_U_PLL_STOPCLKA V_T5_STATIC_U_PLL_STOPCLKA(1U) + +#define S_T5_STATIC_U_PLL_SLEEP 17 +#define V_T5_STATIC_U_PLL_SLEEP(x) ((x) << S_T5_STATIC_U_PLL_SLEEP) +#define F_T5_STATIC_U_PLL_SLEEP V_T5_STATIC_U_PLL_SLEEP(1U) + +#define S_T5_STATIC_U_PLL_BYPASS 16 +#define V_T5_STATIC_U_PLL_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_BYPASS) +#define F_T5_STATIC_U_PLL_BYPASS V_T5_STATIC_U_PLL_BYPASS(1U) + +#define S_T5_STATIC_U_PLL_LOCKTUNE 0 +#define M_T5_STATIC_U_PLL_LOCKTUNE 0xffffU +#define V_T5_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_U_PLL_LOCKTUNE) +#define G_T5_STATIC_U_PLL_LOCKTUNE(x) \ + (((x) >> S_T5_STATIC_U_PLL_LOCKTUNE) & M_T5_STATIC_U_PLL_LOCKTUNE) + +#define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec + +#define S_T5_STATIC_U_PLL_MULTPRE 30 +#define M_T5_STATIC_U_PLL_MULTPRE 0x3U +#define V_T5_STATIC_U_PLL_MULTPRE(x) ((x) << S_T5_STATIC_U_PLL_MULTPRE) +#define G_T5_STATIC_U_PLL_MULTPRE(x) \ + (((x) >> S_T5_STATIC_U_PLL_MULTPRE) & M_T5_STATIC_U_PLL_MULTPRE) + +#define S_T5_STATIC_U_PLL_LOCKSEL 28 +#define M_T5_STATIC_U_PLL_LOCKSEL 0x3U +#define V_T5_STATIC_U_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_U_PLL_LOCKSEL) +#define G_T5_STATIC_U_PLL_LOCKSEL(x) \ + (((x) >> S_T5_STATIC_U_PLL_LOCKSEL) & M_T5_STATIC_U_PLL_LOCKSEL) + +#define S_T5_STATIC_U_PLL_FFTUNE 12 +#define M_T5_STATIC_U_PLL_FFTUNE 0xffffU +#define V_T5_STATIC_U_PLL_FFTUNE(x) ((x) << S_T5_STATIC_U_PLL_FFTUNE) +#define G_T5_STATIC_U_PLL_FFTUNE(x) \ + (((x) >> S_T5_STATIC_U_PLL_FFTUNE) & M_T5_STATIC_U_PLL_FFTUNE) + +#define S_T5_STATIC_U_PLL_RANGEPRE 10 +#define M_T5_STATIC_U_PLL_RANGEPRE 0x3U +#define V_T5_STATIC_U_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_U_PLL_RANGEPRE) +#define G_T5_STATIC_U_PLL_RANGEPRE(x) \ + (((x) >> S_T5_STATIC_U_PLL_RANGEPRE) & M_T5_STATIC_U_PLL_RANGEPRE) + +#define S_T5_STATIC_U_PLL_RANGEB 5 +#define M_T5_STATIC_U_PLL_RANGEB 0x1fU +#define V_T5_STATIC_U_PLL_RANGEB(x) ((x) << S_T5_STATIC_U_PLL_RANGEB) +#define G_T5_STATIC_U_PLL_RANGEB(x) \ + (((x) >> S_T5_STATIC_U_PLL_RANGEB) & M_T5_STATIC_U_PLL_RANGEB) + +#define S_T5_STATIC_U_PLL_RANGEA 0 +#define M_T5_STATIC_U_PLL_RANGEA 0x1fU +#define V_T5_STATIC_U_PLL_RANGEA(x) ((x) << S_T5_STATIC_U_PLL_RANGEA) +#define G_T5_STATIC_U_PLL_RANGEA(x) \ + (((x) >> S_T5_STATIC_U_PLL_RANGEA) & M_T5_STATIC_U_PLL_RANGEA) + +#define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0 +#define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4 + +#define S_T5_STATIC_U_PLL_VCVTUNE 22 +#define M_T5_STATIC_U_PLL_VCVTUNE 0x7U +#define V_T5_STATIC_U_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_U_PLL_VCVTUNE) +#define G_T5_STATIC_U_PLL_VCVTUNE(x) \ + (((x) >> S_T5_STATIC_U_PLL_VCVTUNE) & M_T5_STATIC_U_PLL_VCVTUNE) + +#define S_T5_STATIC_U_PLL_LFTUNE_32_40 13 +#define M_T5_STATIC_U_PLL_LFTUNE_32_40 0x1ffU +#define V_T5_STATIC_U_PLL_LFTUNE_32_40(x) \ + ((x) << S_T5_STATIC_U_PLL_LFTUNE_32_40) +#define G_T5_STATIC_U_PLL_LFTUNE_32_40(x) \ + (((x) >> S_T5_STATIC_U_PLL_LFTUNE_32_40) & \ + M_T5_STATIC_U_PLL_LFTUNE_32_40) + +#define S_T5_STATIC_U_PLL_PREDIV 8 +#define M_T5_STATIC_U_PLL_PREDIV 0x1fU +#define V_T5_STATIC_U_PLL_PREDIV(x) ((x) << S_T5_STATIC_U_PLL_PREDIV) +#define G_T5_STATIC_U_PLL_PREDIV(x) \ + (((x) >> S_T5_STATIC_U_PLL_PREDIV) & M_T5_STATIC_U_PLL_PREDIV) + +#define S_T5_STATIC_U_PLL_MULT 0 +#define M_T5_STATIC_U_PLL_MULT 0xffU +#define V_T5_STATIC_U_PLL_MULT(x) ((x) << S_T5_STATIC_U_PLL_MULT) +#define G_T5_STATIC_U_PLL_MULT(x) \ + (((x) >> S_T5_STATIC_U_PLL_MULT) & M_T5_STATIC_U_PLL_MULT) + +#define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8 + +#define S_T5_STATIC_KR_PLL_BYPASS 30 +#define V_T5_STATIC_KR_PLL_BYPASS(x) ((x) << S_T5_STATIC_KR_PLL_BYPASS) +#define F_T5_STATIC_KR_PLL_BYPASS V_T5_STATIC_KR_PLL_BYPASS(1U) + +#define S_T5_STATIC_KR_PLL_VBOOSTDIV 27 +#define M_T5_STATIC_KR_PLL_VBOOSTDIV 0x7U +#define V_T5_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KR_PLL_VBOOSTDIV) +#define G_T5_STATIC_KR_PLL_VBOOSTDIV(x) \ + (((x) >> S_T5_STATIC_KR_PLL_VBOOSTDIV) & M_T5_STATIC_KR_PLL_VBOOSTDIV) + +#define S_T5_STATIC_KR_PLL_CPISEL 24 +#define M_T5_STATIC_KR_PLL_CPISEL 0x7U +#define V_T5_STATIC_KR_PLL_CPISEL(x) ((x) << S_T5_STATIC_KR_PLL_CPISEL) +#define G_T5_STATIC_KR_PLL_CPISEL(x) \ + (((x) >> S_T5_STATIC_KR_PLL_CPISEL) & M_T5_STATIC_KR_PLL_CPISEL) + +#define S_T5_STATIC_KR_PLL_CCALMETHOD 23 +#define V_T5_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KR_PLL_CCALMETHOD) +#define F_T5_STATIC_KR_PLL_CCALMETHOD V_T5_STATIC_KR_PLL_CCALMETHOD(1U) + +#define S_T5_STATIC_KR_PLL_CCALLOAD 22 +#define V_T5_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KR_PLL_CCALLOAD) +#define F_T5_STATIC_KR_PLL_CCALLOAD V_T5_STATIC_KR_PLL_CCALLOAD(1U) + +#define S_T5_STATIC_KR_PLL_CCALFMIN 21 +#define V_T5_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMIN) +#define F_T5_STATIC_KR_PLL_CCALFMIN V_T5_STATIC_KR_PLL_CCALFMIN(1U) + +#define S_T5_STATIC_KR_PLL_CCALFMAX 20 +#define V_T5_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMAX) +#define F_T5_STATIC_KR_PLL_CCALFMAX V_T5_STATIC_KR_PLL_CCALFMAX(1U) + +#define S_T5_STATIC_KR_PLL_CCALCVHOLD 19 +#define V_T5_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KR_PLL_CCALCVHOLD) +#define F_T5_STATIC_KR_PLL_CCALCVHOLD V_T5_STATIC_KR_PLL_CCALCVHOLD(1U) + +#define S_T5_STATIC_KR_PLL_CCALBANDSEL 15 +#define M_T5_STATIC_KR_PLL_CCALBANDSEL 0xfU +#define V_T5_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KR_PLL_CCALBANDSEL) +#define G_T5_STATIC_KR_PLL_CCALBANDSEL(x) \ + (((x) >> S_T5_STATIC_KR_PLL_CCALBANDSEL) & \ + M_T5_STATIC_KR_PLL_CCALBANDSEL) + +#define S_T5_STATIC_KR_PLL_BGOFFSET 11 +#define M_T5_STATIC_KR_PLL_BGOFFSET 0xfU +#define V_T5_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KR_PLL_BGOFFSET) +#define G_T5_STATIC_KR_PLL_BGOFFSET(x) \ + (((x) >> S_T5_STATIC_KR_PLL_BGOFFSET) & M_T5_STATIC_KR_PLL_BGOFFSET) + +#define S_T5_STATIC_KR_PLL_P 8 +#define M_T5_STATIC_KR_PLL_P 0x7U +#define V_T5_STATIC_KR_PLL_P(x) ((x) << S_T5_STATIC_KR_PLL_P) +#define G_T5_STATIC_KR_PLL_P(x) \ + (((x) >> S_T5_STATIC_KR_PLL_P) & M_T5_STATIC_KR_PLL_P) + +#define S_T5_STATIC_KR_PLL_N2 4 +#define M_T5_STATIC_KR_PLL_N2 0xfU +#define V_T5_STATIC_KR_PLL_N2(x) ((x) << S_T5_STATIC_KR_PLL_N2) +#define G_T5_STATIC_KR_PLL_N2(x) \ + (((x) >> S_T5_STATIC_KR_PLL_N2) & M_T5_STATIC_KR_PLL_N2) + +#define S_T5_STATIC_KR_PLL_N1 0 +#define M_T5_STATIC_KR_PLL_N1 0xfU +#define V_T5_STATIC_KR_PLL_N1(x) ((x) << S_T5_STATIC_KR_PLL_N1) +#define G_T5_STATIC_KR_PLL_N1(x) \ + (((x) >> S_T5_STATIC_KR_PLL_N1) & M_T5_STATIC_KR_PLL_N1) + +#define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc + +#define S_T5_STATIC_KR_PLL_M 11 +#define M_T5_STATIC_KR_PLL_M 0x1ffU +#define V_T5_STATIC_KR_PLL_M(x) ((x) << S_T5_STATIC_KR_PLL_M) +#define G_T5_STATIC_KR_PLL_M(x) \ + (((x) >> S_T5_STATIC_KR_PLL_M) & M_T5_STATIC_KR_PLL_M) + +#define S_T5_STATIC_KR_PLL_ANALOGTUNE 0 +#define M_T5_STATIC_KR_PLL_ANALOGTUNE 0x7ffU +#define V_T5_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KR_PLL_ANALOGTUNE) +#define G_T5_STATIC_KR_PLL_ANALOGTUNE(x) \ + (((x) >> S_T5_STATIC_KR_PLL_ANALOGTUNE) & M_T5_STATIC_KR_PLL_ANALOGTUNE) + #define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100 #define S_HALT_CALIBRATE 1 @@ -4421,6 +8912,40 @@ #define V_RESET_CALIBRATE(x) ((x) << S_RESET_CALIBRATE) #define F_RESET_CALIBRATE V_RESET_CALIBRATE(1U) +#define A_DBG_GPIO_EN_NEW 0x6100 + +#define S_GPIO16_OEN 7 +#define V_GPIO16_OEN(x) ((x) << S_GPIO16_OEN) +#define F_GPIO16_OEN V_GPIO16_OEN(1U) + +#define S_GPIO17_OEN 6 +#define V_GPIO17_OEN(x) ((x) << S_GPIO17_OEN) +#define F_GPIO17_OEN V_GPIO17_OEN(1U) + +#define S_GPIO18_OEN 5 +#define V_GPIO18_OEN(x) ((x) << S_GPIO18_OEN) +#define F_GPIO18_OEN V_GPIO18_OEN(1U) + +#define S_GPIO19_OEN 4 +#define V_GPIO19_OEN(x) ((x) << S_GPIO19_OEN) +#define F_GPIO19_OEN V_GPIO19_OEN(1U) + +#define S_GPIO16_OUT_VAL 3 +#define V_GPIO16_OUT_VAL(x) ((x) << S_GPIO16_OUT_VAL) +#define F_GPIO16_OUT_VAL V_GPIO16_OUT_VAL(1U) + +#define S_GPIO17_OUT_VAL 2 +#define V_GPIO17_OUT_VAL(x) ((x) << S_GPIO17_OUT_VAL) +#define F_GPIO17_OUT_VAL V_GPIO17_OUT_VAL(1U) + +#define S_GPIO18_OUT_VAL 1 +#define V_GPIO18_OUT_VAL(x) ((x) << S_GPIO18_OUT_VAL) +#define F_GPIO18_OUT_VAL V_GPIO18_OUT_VAL(1U) + +#define S_GPIO19_OUT_VAL 0 +#define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL) +#define F_GPIO19_OUT_VAL V_GPIO19_OUT_VAL(1U) + #define A_DBG_PVT_REG_UPDATE_CTL 0x6104 #define S_FAST_UPDATE 8 @@ -4435,6 +8960,40 @@ #define V_HALT_UPDATE(x) ((x) << S_HALT_UPDATE) #define F_HALT_UPDATE V_HALT_UPDATE(1U) +#define A_DBG_GPIO_IN_NEW 0x6104 + +#define S_GPIO16_CHG_DET 7 +#define V_GPIO16_CHG_DET(x) ((x) << S_GPIO16_CHG_DET) +#define F_GPIO16_CHG_DET V_GPIO16_CHG_DET(1U) + +#define S_GPIO17_CHG_DET 6 +#define V_GPIO17_CHG_DET(x) ((x) << S_GPIO17_CHG_DET) +#define F_GPIO17_CHG_DET V_GPIO17_CHG_DET(1U) + +#define S_GPIO18_CHG_DET 5 +#define V_GPIO18_CHG_DET(x) ((x) << S_GPIO18_CHG_DET) +#define F_GPIO18_CHG_DET V_GPIO18_CHG_DET(1U) + +#define S_GPIO19_CHG_DET 4 +#define V_GPIO19_CHG_DET(x) ((x) << S_GPIO19_CHG_DET) +#define F_GPIO19_CHG_DET V_GPIO19_CHG_DET(1U) + +#define S_GPIO16_IN 3 +#define V_GPIO16_IN(x) ((x) << S_GPIO16_IN) +#define F_GPIO16_IN V_GPIO16_IN(1U) + +#define S_GPIO17_IN 2 +#define V_GPIO17_IN(x) ((x) << S_GPIO17_IN) +#define F_GPIO17_IN V_GPIO17_IN(1U) + +#define S_GPIO18_IN 1 +#define V_GPIO18_IN(x) ((x) << S_GPIO18_IN) +#define F_GPIO18_IN V_GPIO18_IN(1U) + +#define S_GPIO19_IN 0 +#define V_GPIO19_IN(x) ((x) << S_GPIO19_IN) +#define F_GPIO19_IN V_GPIO19_IN(1U) + #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108 #define S_LAST_MEASUREMENT_SELECT 8 @@ -4459,6 +9018,76 @@ (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & \ M_LAST_MEASUREMENT_RESULT_BANK_A) +#define A_DBG_T5_STATIC_KX_PLL_CONF1 0x6108 + +#define S_T5_STATIC_KX_PLL_BYPASS 30 +#define V_T5_STATIC_KX_PLL_BYPASS(x) ((x) << S_T5_STATIC_KX_PLL_BYPASS) +#define F_T5_STATIC_KX_PLL_BYPASS V_T5_STATIC_KX_PLL_BYPASS(1U) + +#define S_T5_STATIC_KX_PLL_VBOOSTDIV 27 +#define M_T5_STATIC_KX_PLL_VBOOSTDIV 0x7U +#define V_T5_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KX_PLL_VBOOSTDIV) +#define G_T5_STATIC_KX_PLL_VBOOSTDIV(x) \ + (((x) >> S_T5_STATIC_KX_PLL_VBOOSTDIV) & M_T5_STATIC_KX_PLL_VBOOSTDIV) + +#define S_T5_STATIC_KX_PLL_CPISEL 24 +#define M_T5_STATIC_KX_PLL_CPISEL 0x7U +#define V_T5_STATIC_KX_PLL_CPISEL(x) ((x) << S_T5_STATIC_KX_PLL_CPISEL) +#define G_T5_STATIC_KX_PLL_CPISEL(x) \ + (((x) >> S_T5_STATIC_KX_PLL_CPISEL) & M_T5_STATIC_KX_PLL_CPISEL) + +#define S_T5_STATIC_KX_PLL_CCALMETHOD 23 +#define V_T5_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KX_PLL_CCALMETHOD) +#define F_T5_STATIC_KX_PLL_CCALMETHOD V_T5_STATIC_KX_PLL_CCALMETHOD(1U) + +#define S_T5_STATIC_KX_PLL_CCALLOAD 22 +#define V_T5_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KX_PLL_CCALLOAD) +#define F_T5_STATIC_KX_PLL_CCALLOAD V_T5_STATIC_KX_PLL_CCALLOAD(1U) + +#define S_T5_STATIC_KX_PLL_CCALFMIN 21 +#define V_T5_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMIN) +#define F_T5_STATIC_KX_PLL_CCALFMIN V_T5_STATIC_KX_PLL_CCALFMIN(1U) + +#define S_T5_STATIC_KX_PLL_CCALFMAX 20 +#define V_T5_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMAX) +#define F_T5_STATIC_KX_PLL_CCALFMAX V_T5_STATIC_KX_PLL_CCALFMAX(1U) + +#define S_T5_STATIC_KX_PLL_CCALCVHOLD 19 +#define V_T5_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KX_PLL_CCALCVHOLD) +#define F_T5_STATIC_KX_PLL_CCALCVHOLD V_T5_STATIC_KX_PLL_CCALCVHOLD(1U) + +#define S_T5_STATIC_KX_PLL_CCALBANDSEL 15 +#define M_T5_STATIC_KX_PLL_CCALBANDSEL 0xfU +#define V_T5_STATIC_KX_PLL_CCALBANDSEL(x) \ + ((x) << S_T5_STATIC_KX_PLL_CCALBANDSEL) +#define G_T5_STATIC_KX_PLL_CCALBANDSEL(x) \ + (((x) >> S_T5_STATIC_KX_PLL_CCALBANDSEL) & \ + M_T5_STATIC_KX_PLL_CCALBANDSEL) + +#define S_T5_STATIC_KX_PLL_BGOFFSET 11 +#define M_T5_STATIC_KX_PLL_BGOFFSET 0xfU +#define V_T5_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KX_PLL_BGOFFSET) +#define G_T5_STATIC_KX_PLL_BGOFFSET(x) \ + (((x) >> S_T5_STATIC_KX_PLL_BGOFFSET) & M_T5_STATIC_KX_PLL_BGOFFSET) + +#define S_T5_STATIC_KX_PLL_P 8 +#define M_T5_STATIC_KX_PLL_P 0x7U +#define V_T5_STATIC_KX_PLL_P(x) ((x) << S_T5_STATIC_KX_PLL_P) +#define G_T5_STATIC_KX_PLL_P(x) \ + (((x) >> S_T5_STATIC_KX_PLL_P) & M_T5_STATIC_KX_PLL_P) + +#define S_T5_STATIC_KX_PLL_N2 4 +#define M_T5_STATIC_KX_PLL_N2 0xfU +#define V_T5_STATIC_KX_PLL_N2(x) ((x) << S_T5_STATIC_KX_PLL_N2) +#define G_T5_STATIC_KX_PLL_N2(x) \ + (((x) >> S_T5_STATIC_KX_PLL_N2) & M_T5_STATIC_KX_PLL_N2) + +#define S_T5_STATIC_KX_PLL_N1 0 +#define M_T5_STATIC_KX_PLL_N1 0xfU +#define V_T5_STATIC_KX_PLL_N1(x) ((x) << S_T5_STATIC_KX_PLL_N1) +#define G_T5_STATIC_KX_PLL_N1(x) \ + (((x) >> S_T5_STATIC_KX_PLL_N1) & M_T5_STATIC_KX_PLL_N1) + #define A_DBG_PVT_REG_DRVN 0x610c #define S_PVT_REG_DRVN_EN 8 @@ -4475,6 +9104,20 @@ #define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A) #define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A) +#define A_DBG_T5_STATIC_KX_PLL_CONF2 0x610c + +#define S_T5_STATIC_KX_PLL_M 11 +#define M_T5_STATIC_KX_PLL_M 0x1ffU +#define V_T5_STATIC_KX_PLL_M(x) ((x) << S_T5_STATIC_KX_PLL_M) +#define G_T5_STATIC_KX_PLL_M(x) \ + (((x) >> S_T5_STATIC_KX_PLL_M) & M_T5_STATIC_KX_PLL_M) + +#define S_T5_STATIC_KX_PLL_ANALOGTUNE 0 +#define M_T5_STATIC_KX_PLL_ANALOGTUNE 0x7ffU +#define V_T5_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KX_PLL_ANALOGTUNE) +#define G_T5_STATIC_KX_PLL_ANALOGTUNE(x) \ + (((x) >> S_T5_STATIC_KX_PLL_ANALOGTUNE) & M_T5_STATIC_KX_PLL_ANALOGTUNE) + #define A_DBG_PVT_REG_DRVP 0x6110 #define S_PVT_REG_DRVP_EN 8 @@ -4491,6 +9134,32 @@ #define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A) #define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A) +#define A_DBG_T5_STATIC_C_DFS_CONF 0x6110 + +#define S_STATIC_C_DFS_RANGEA 8 +#define M_STATIC_C_DFS_RANGEA 0x1fU +#define V_STATIC_C_DFS_RANGEA(x) ((x) << S_STATIC_C_DFS_RANGEA) +#define G_STATIC_C_DFS_RANGEA(x) \ + (((x) >> S_STATIC_C_DFS_RANGEA) & M_STATIC_C_DFS_RANGEA) + +#define S_STATIC_C_DFS_RANGEB 3 +#define M_STATIC_C_DFS_RANGEB 0x1fU +#define V_STATIC_C_DFS_RANGEB(x) ((x) << S_STATIC_C_DFS_RANGEB) +#define G_STATIC_C_DFS_RANGEB(x) \ + (((x) >> S_STATIC_C_DFS_RANGEB) & M_STATIC_C_DFS_RANGEB) + +#define S_STATIC_C_DFS_FFTUNE4 2 +#define V_STATIC_C_DFS_FFTUNE4(x) ((x) << S_STATIC_C_DFS_FFTUNE4) +#define F_STATIC_C_DFS_FFTUNE4 V_STATIC_C_DFS_FFTUNE4(1U) + +#define S_STATIC_C_DFS_FFTUNE5 1 +#define V_STATIC_C_DFS_FFTUNE5(x) ((x) << S_STATIC_C_DFS_FFTUNE5) +#define F_STATIC_C_DFS_FFTUNE5 V_STATIC_C_DFS_FFTUNE5(1U) + +#define S_STATIC_C_DFS_ENABLE 0 +#define V_STATIC_C_DFS_ENABLE(x) ((x) << S_STATIC_C_DFS_ENABLE) +#define F_STATIC_C_DFS_ENABLE V_STATIC_C_DFS_ENABLE(1U) + #define A_DBG_PVT_REG_TERMN 0x6114 #define S_PVT_REG_TERMN_EN 8 @@ -4507,6 +9176,32 @@ #define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A) #define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A) +#define A_DBG_T5_STATIC_U_DFS_CONF 0x6114 + +#define S_STATIC_U_DFS_RANGEA 8 +#define M_STATIC_U_DFS_RANGEA 0x1fU +#define V_STATIC_U_DFS_RANGEA(x) ((x) << S_STATIC_U_DFS_RANGEA) +#define G_STATIC_U_DFS_RANGEA(x) \ + (((x) >> S_STATIC_U_DFS_RANGEA) & M_STATIC_U_DFS_RANGEA) + +#define S_STATIC_U_DFS_RANGEB 3 +#define M_STATIC_U_DFS_RANGEB 0x1fU +#define V_STATIC_U_DFS_RANGEB(x) ((x) << S_STATIC_U_DFS_RANGEB) +#define G_STATIC_U_DFS_RANGEB(x) \ + (((x) >> S_STATIC_U_DFS_RANGEB) & M_STATIC_U_DFS_RANGEB) + +#define S_STATIC_U_DFS_FFTUNE4 2 +#define V_STATIC_U_DFS_FFTUNE4(x) ((x) << S_STATIC_U_DFS_FFTUNE4) +#define F_STATIC_U_DFS_FFTUNE4 V_STATIC_U_DFS_FFTUNE4(1U) + +#define S_STATIC_U_DFS_FFTUNE5 1 +#define V_STATIC_U_DFS_FFTUNE5(x) ((x) << S_STATIC_U_DFS_FFTUNE5) +#define F_STATIC_U_DFS_FFTUNE5 V_STATIC_U_DFS_FFTUNE5(1U) + +#define S_STATIC_U_DFS_ENABLE 0 +#define V_STATIC_U_DFS_ENABLE(x) ((x) << S_STATIC_U_DFS_ENABLE) +#define F_STATIC_U_DFS_ENABLE V_STATIC_U_DFS_ENABLE(1U) + #define A_DBG_PVT_REG_TERMP 0x6118 #define S_PVT_REG_TERMP_EN 8 @@ -4523,6 +9218,170 @@ #define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A) #define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A) +#define A_DBG_GPIO_PE_EN 0x6118 + +#define S_GPIO19_PE_EN 19 +#define V_GPIO19_PE_EN(x) ((x) << S_GPIO19_PE_EN) +#define F_GPIO19_PE_EN V_GPIO19_PE_EN(1U) + +#define S_GPIO18_PE_EN 18 +#define V_GPIO18_PE_EN(x) ((x) << S_GPIO18_PE_EN) +#define F_GPIO18_PE_EN V_GPIO18_PE_EN(1U) + +#define S_GPIO17_PE_EN 17 +#define V_GPIO17_PE_EN(x) ((x) << S_GPIO17_PE_EN) +#define F_GPIO17_PE_EN V_GPIO17_PE_EN(1U) + +#define S_GPIO16_PE_EN 16 +#define V_GPIO16_PE_EN(x) ((x) << S_GPIO16_PE_EN) +#define F_GPIO16_PE_EN V_GPIO16_PE_EN(1U) + +#define S_GPIO15_PE_EN 15 +#define V_GPIO15_PE_EN(x) ((x) << S_GPIO15_PE_EN) +#define F_GPIO15_PE_EN V_GPIO15_PE_EN(1U) + +#define S_GPIO14_PE_EN 14 +#define V_GPIO14_PE_EN(x) ((x) << S_GPIO14_PE_EN) +#define F_GPIO14_PE_EN V_GPIO14_PE_EN(1U) + +#define S_GPIO13_PE_EN 13 +#define V_GPIO13_PE_EN(x) ((x) << S_GPIO13_PE_EN) +#define F_GPIO13_PE_EN V_GPIO13_PE_EN(1U) + +#define S_GPIO12_PE_EN 12 +#define V_GPIO12_PE_EN(x) ((x) << S_GPIO12_PE_EN) +#define F_GPIO12_PE_EN V_GPIO12_PE_EN(1U) + +#define S_GPIO11_PE_EN 11 +#define V_GPIO11_PE_EN(x) ((x) << S_GPIO11_PE_EN) +#define F_GPIO11_PE_EN V_GPIO11_PE_EN(1U) + +#define S_GPIO10_PE_EN 10 +#define V_GPIO10_PE_EN(x) ((x) << S_GPIO10_PE_EN) +#define F_GPIO10_PE_EN V_GPIO10_PE_EN(1U) + +#define S_GPIO9_PE_EN 9 +#define V_GPIO9_PE_EN(x) ((x) << S_GPIO9_PE_EN) +#define F_GPIO9_PE_EN V_GPIO9_PE_EN(1U) + +#define S_GPIO8_PE_EN 8 +#define V_GPIO8_PE_EN(x) ((x) << S_GPIO8_PE_EN) +#define F_GPIO8_PE_EN V_GPIO8_PE_EN(1U) + +#define S_GPIO7_PE_EN 7 +#define V_GPIO7_PE_EN(x) ((x) << S_GPIO7_PE_EN) +#define F_GPIO7_PE_EN V_GPIO7_PE_EN(1U) + +#define S_GPIO6_PE_EN 6 +#define V_GPIO6_PE_EN(x) ((x) << S_GPIO6_PE_EN) +#define F_GPIO6_PE_EN V_GPIO6_PE_EN(1U) + +#define S_GPIO5_PE_EN 5 +#define V_GPIO5_PE_EN(x) ((x) << S_GPIO5_PE_EN) +#define F_GPIO5_PE_EN V_GPIO5_PE_EN(1U) + +#define S_GPIO4_PE_EN 4 +#define V_GPIO4_PE_EN(x) ((x) << S_GPIO4_PE_EN) +#define F_GPIO4_PE_EN V_GPIO4_PE_EN(1U) + +#define S_GPIO3_PE_EN 3 +#define V_GPIO3_PE_EN(x) ((x) << S_GPIO3_PE_EN) +#define F_GPIO3_PE_EN V_GPIO3_PE_EN(1U) + +#define S_GPIO2_PE_EN 2 +#define V_GPIO2_PE_EN(x) ((x) << S_GPIO2_PE_EN) +#define F_GPIO2_PE_EN V_GPIO2_PE_EN(1U) + +#define S_GPIO1_PE_EN 1 +#define V_GPIO1_PE_EN(x) ((x) << S_GPIO1_PE_EN) +#define F_GPIO1_PE_EN V_GPIO1_PE_EN(1U) + +#define S_GPIO0_PE_EN 0 +#define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN) +#define F_GPIO0_PE_EN V_GPIO0_PE_EN(1U) + +#define A_DBG_GPIO_PS_EN 0x611c + +#define S_GPIO19_PS_EN 19 +#define V_GPIO19_PS_EN(x) ((x) << S_GPIO19_PS_EN) +#define F_GPIO19_PS_EN V_GPIO19_PS_EN(1U) + +#define S_GPIO18_PS_EN 18 +#define V_GPIO18_PS_EN(x) ((x) << S_GPIO18_PS_EN) +#define F_GPIO18_PS_EN V_GPIO18_PS_EN(1U) + +#define S_GPIO17_PS_EN 17 +#define V_GPIO17_PS_EN(x) ((x) << S_GPIO17_PS_EN) +#define F_GPIO17_PS_EN V_GPIO17_PS_EN(1U) + +#define S_GPIO16_PS_EN 16 +#define V_GPIO16_PS_EN(x) ((x) << S_GPIO16_PS_EN) +#define F_GPIO16_PS_EN V_GPIO16_PS_EN(1U) + +#define S_GPIO15_PS_EN 15 +#define V_GPIO15_PS_EN(x) ((x) << S_GPIO15_PS_EN) +#define F_GPIO15_PS_EN V_GPIO15_PS_EN(1U) + +#define S_GPIO14_PS_EN 14 +#define V_GPIO14_PS_EN(x) ((x) << S_GPIO14_PS_EN) +#define F_GPIO14_PS_EN V_GPIO14_PS_EN(1U) + +#define S_GPIO13_PS_EN 13 +#define V_GPIO13_PS_EN(x) ((x) << S_GPIO13_PS_EN) +#define F_GPIO13_PS_EN V_GPIO13_PS_EN(1U) + +#define S_GPIO12_PS_EN 12 +#define V_GPIO12_PS_EN(x) ((x) << S_GPIO12_PS_EN) +#define F_GPIO12_PS_EN V_GPIO12_PS_EN(1U) + +#define S_GPIO11_PS_EN 11 +#define V_GPIO11_PS_EN(x) ((x) << S_GPIO11_PS_EN) +#define F_GPIO11_PS_EN V_GPIO11_PS_EN(1U) + +#define S_GPIO10_PS_EN 10 +#define V_GPIO10_PS_EN(x) ((x) << S_GPIO10_PS_EN) +#define F_GPIO10_PS_EN V_GPIO10_PS_EN(1U) + +#define S_GPIO9_PS_EN 9 +#define V_GPIO9_PS_EN(x) ((x) << S_GPIO9_PS_EN) +#define F_GPIO9_PS_EN V_GPIO9_PS_EN(1U) + +#define S_GPIO8_PS_EN 8 +#define V_GPIO8_PS_EN(x) ((x) << S_GPIO8_PS_EN) +#define F_GPIO8_PS_EN V_GPIO8_PS_EN(1U) + +#define S_GPIO7_PS_EN 7 +#define V_GPIO7_PS_EN(x) ((x) << S_GPIO7_PS_EN) +#define F_GPIO7_PS_EN V_GPIO7_PS_EN(1U) + +#define S_GPIO6_PS_EN 6 +#define V_GPIO6_PS_EN(x) ((x) << S_GPIO6_PS_EN) +#define F_GPIO6_PS_EN V_GPIO6_PS_EN(1U) + +#define S_GPIO5_PS_EN 5 +#define V_GPIO5_PS_EN(x) ((x) << S_GPIO5_PS_EN) +#define F_GPIO5_PS_EN V_GPIO5_PS_EN(1U) + +#define S_GPIO4_PS_EN 4 +#define V_GPIO4_PS_EN(x) ((x) << S_GPIO4_PS_EN) +#define F_GPIO4_PS_EN V_GPIO4_PS_EN(1U) + +#define S_GPIO3_PS_EN 3 +#define V_GPIO3_PS_EN(x) ((x) << S_GPIO3_PS_EN) +#define F_GPIO3_PS_EN V_GPIO3_PS_EN(1U) + +#define S_GPIO2_PS_EN 2 +#define V_GPIO2_PS_EN(x) ((x) << S_GPIO2_PS_EN) +#define F_GPIO2_PS_EN V_GPIO2_PS_EN(1U) + +#define S_GPIO1_PS_EN 1 +#define V_GPIO1_PS_EN(x) ((x) << S_GPIO1_PS_EN) +#define F_GPIO1_PS_EN V_GPIO1_PS_EN(1U) + +#define S_GPIO0_PS_EN 0 +#define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN) +#define F_GPIO0_PS_EN V_GPIO0_PS_EN(1U) + #define A_DBG_PVT_REG_THRESHOLD 0x611c #define S_PVT_CALIBRATION_DONE 8 @@ -4561,6 +9420,88 @@ #define V_THRESHOLD_DRVN_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVN_MIN_SYNC) #define F_THRESHOLD_DRVN_MIN_SYNC V_THRESHOLD_DRVN_MIN_SYNC(1U) +#define A_DBG_GPIO_PS_EN 0x611c + +#define S_GPIO19_PS_EN 19 +#define V_GPIO19_PS_EN(x) ((x) << S_GPIO19_PS_EN) +#define F_GPIO19_PS_EN V_GPIO19_PS_EN(1U) + +#define S_GPIO18_PS_EN 18 +#define V_GPIO18_PS_EN(x) ((x) << S_GPIO18_PS_EN) +#define F_GPIO18_PS_EN V_GPIO18_PS_EN(1U) + +#define S_GPIO17_PS_EN 17 +#define V_GPIO17_PS_EN(x) ((x) << S_GPIO17_PS_EN) +#define F_GPIO17_PS_EN V_GPIO17_PS_EN(1U) + +#define S_GPIO16_PS_EN 16 +#define V_GPIO16_PS_EN(x) ((x) << S_GPIO16_PS_EN) +#define F_GPIO16_PS_EN V_GPIO16_PS_EN(1U) + +#define S_GPIO15_PS_EN 15 +#define V_GPIO15_PS_EN(x) ((x) << S_GPIO15_PS_EN) +#define F_GPIO15_PS_EN V_GPIO15_PS_EN(1U) + +#define S_GPIO14_PS_EN 14 +#define V_GPIO14_PS_EN(x) ((x) << S_GPIO14_PS_EN) +#define F_GPIO14_PS_EN V_GPIO14_PS_EN(1U) + +#define S_GPIO13_PS_EN 13 +#define V_GPIO13_PS_EN(x) ((x) << S_GPIO13_PS_EN) +#define F_GPIO13_PS_EN V_GPIO13_PS_EN(1U) + +#define S_GPIO12_PS_EN 12 +#define V_GPIO12_PS_EN(x) ((x) << S_GPIO12_PS_EN) +#define F_GPIO12_PS_EN V_GPIO12_PS_EN(1U) + +#define S_GPIO11_PS_EN 11 +#define V_GPIO11_PS_EN(x) ((x) << S_GPIO11_PS_EN) +#define F_GPIO11_PS_EN V_GPIO11_PS_EN(1U) + +#define S_GPIO10_PS_EN 10 +#define V_GPIO10_PS_EN(x) ((x) << S_GPIO10_PS_EN) +#define F_GPIO10_PS_EN V_GPIO10_PS_EN(1U) + +#define S_GPIO9_PS_EN 9 +#define V_GPIO9_PS_EN(x) ((x) << S_GPIO9_PS_EN) +#define F_GPIO9_PS_EN V_GPIO9_PS_EN(1U) + +#define S_GPIO8_PS_EN 8 +#define V_GPIO8_PS_EN(x) ((x) << S_GPIO8_PS_EN) +#define F_GPIO8_PS_EN V_GPIO8_PS_EN(1U) + +#define S_GPIO7_PS_EN 7 +#define V_GPIO7_PS_EN(x) ((x) << S_GPIO7_PS_EN) +#define F_GPIO7_PS_EN V_GPIO7_PS_EN(1U) + +#define S_GPIO6_PS_EN 6 +#define V_GPIO6_PS_EN(x) ((x) << S_GPIO6_PS_EN) +#define F_GPIO6_PS_EN V_GPIO6_PS_EN(1U) + +#define S_GPIO5_PS_EN 5 +#define V_GPIO5_PS_EN(x) ((x) << S_GPIO5_PS_EN) +#define F_GPIO5_PS_EN V_GPIO5_PS_EN(1U) + +#define S_GPIO4_PS_EN 4 +#define V_GPIO4_PS_EN(x) ((x) << S_GPIO4_PS_EN) +#define F_GPIO4_PS_EN V_GPIO4_PS_EN(1U) + +#define S_GPIO3_PS_EN 3 +#define V_GPIO3_PS_EN(x) ((x) << S_GPIO3_PS_EN) +#define F_GPIO3_PS_EN V_GPIO3_PS_EN(1U) + +#define S_GPIO2_PS_EN 2 +#define V_GPIO2_PS_EN(x) ((x) << S_GPIO2_PS_EN) +#define F_GPIO2_PS_EN V_GPIO2_PS_EN(1U) + +#define S_GPIO1_PS_EN 1 +#define V_GPIO1_PS_EN(x) ((x) << S_GPIO1_PS_EN) +#define F_GPIO1_PS_EN V_GPIO1_PS_EN(1U) + +#define S_GPIO0_PS_EN 0 +#define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN) +#define F_GPIO0_PS_EN V_GPIO0_PS_EN(1U) + #define A_DBG_PVT_REG_IN_TERMP 0x6120 #define S_REG_IN_TERMP_B 4 @@ -4573,6 +9514,7 @@ #define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A) #define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A) +#define A_DBG_EFUSE_BYTE16_19 0x6120 #define A_DBG_PVT_REG_IN_TERMN 0x6124 #define S_REG_IN_TERMN_B 4 @@ -4585,6 +9527,7 @@ #define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A) #define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A) +#define A_DBG_EFUSE_BYTE20_23 0x6124 #define A_DBG_PVT_REG_IN_DRVP 0x6128 #define S_REG_IN_DRVP_B 4 @@ -4597,6 +9540,7 @@ #define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A) #define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A) +#define A_DBG_EFUSE_BYTE24_27 0x6128 #define A_DBG_PVT_REG_IN_DRVN 0x612c #define S_REG_IN_DRVN_B 4 @@ -4609,6 +9553,7 @@ #define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A) #define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A) +#define A_DBG_EFUSE_BYTE28_31 0x612c #define A_DBG_PVT_REG_OUT_TERMP 0x6130 #define S_REG_OUT_TERMP_B 4 @@ -4621,6 +9566,7 @@ #define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A) #define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A) +#define A_DBG_EFUSE_BYTE32_35 0x6130 #define A_DBG_PVT_REG_OUT_TERMN 0x6134 #define S_REG_OUT_TERMN_B 4 @@ -4633,6 +9579,7 @@ #define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A) #define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A) +#define A_DBG_EFUSE_BYTE36_39 0x6134 #define A_DBG_PVT_REG_OUT_DRVP 0x6138 #define S_REG_OUT_DRVP_B 4 @@ -4645,6 +9592,7 @@ #define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A) #define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A) +#define A_DBG_EFUSE_BYTE40_43 0x6138 #define A_DBG_PVT_REG_OUT_DRVN 0x613c #define S_REG_OUT_DRVN_B 4 @@ -4657,6 +9605,7 @@ #define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A) #define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A) +#define A_DBG_EFUSE_BYTE44_47 0x613c #define A_DBG_PVT_REG_HISTORY_TERMP 0x6140 #define S_TERMP_B_HISTORY 4 @@ -4669,6 +9618,7 @@ #define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY) #define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY) +#define A_DBG_EFUSE_BYTE48_51 0x6140 #define A_DBG_PVT_REG_HISTORY_TERMN 0x6144 #define S_TERMN_B_HISTORY 4 @@ -4681,6 +9631,7 @@ #define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY) #define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY) +#define A_DBG_EFUSE_BYTE52_55 0x6144 #define A_DBG_PVT_REG_HISTORY_DRVP 0x6148 #define S_DRVP_B_HISTORY 4 @@ -4693,6 +9644,7 @@ #define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY) #define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY) +#define A_DBG_EFUSE_BYTE56_59 0x6148 #define A_DBG_PVT_REG_HISTORY_DRVN 0x614c #define S_DRVN_B_HISTORY 4 @@ -4705,6 +9657,7 @@ #define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY) #define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY) +#define A_DBG_EFUSE_BYTE60_63 0x614c #define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150 #define S_SAMPLE_WAIT_CLKS 0 @@ -6553,6 +11506,18 @@ #define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE) #define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE) +#define A_MA_EXT_MEMORY0_BAR 0x77c8 + +#define S_EXT_MEM0_BASE 16 +#define M_EXT_MEM0_BASE 0xfffU +#define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE) +#define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE) + +#define S_EXT_MEM0_SIZE 0 +#define M_EXT_MEM0_SIZE 0xfffU +#define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE) +#define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE) + #define A_MA_HOST_MEMORY_BAR 0x77cc #define S_HMA_BASE 16 @@ -6577,6 +11542,16 @@ #define G_EXT_MEM_PAGE_SIZE(x) \ (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE) +#define S_BRC_MODE1 6 +#define V_BRC_MODE1(x) ((x) << S_BRC_MODE1) +#define F_BRC_MODE1 V_BRC_MODE1(1U) + +#define S_EXT_MEM_PAGE_SIZE1 4 +#define M_EXT_MEM_PAGE_SIZE1 0x3U +#define V_EXT_MEM_PAGE_SIZE1(x) ((x) << S_EXT_MEM_PAGE_SIZE1) +#define G_EXT_MEM_PAGE_SIZE1(x) \ + (((x) >> S_EXT_MEM_PAGE_SIZE1) & M_EXT_MEM_PAGE_SIZE1) + #define A_MA_ARB_CTRL 0x77d4 #define S_DIS_PAGE_HINT 1 @@ -6587,6 +11562,10 @@ #define V_DIS_ADV_ARB(x) ((x) << S_DIS_ADV_ARB) #define F_DIS_ADV_ARB V_DIS_ADV_ARB(1U) +#define S_DIS_BANK_FAIR 2 +#define V_DIS_BANK_FAIR(x) ((x) << S_DIS_BANK_FAIR) +#define F_DIS_BANK_FAIR V_DIS_BANK_FAIR(1U) + #define A_MA_TARGET_MEM_ENABLE 0x77d8 #define S_HMA_ENABLE 3 @@ -6605,6 +11584,18 @@ #define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE) #define F_EDRAM0_ENABLE V_EDRAM0_ENABLE(1U) +#define S_HMA_MUX 5 +#define V_HMA_MUX(x) ((x) << S_HMA_MUX) +#define F_HMA_MUX V_HMA_MUX(1U) + +#define S_EXT_MEM1_ENABLE 4 +#define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE) +#define F_EXT_MEM1_ENABLE V_EXT_MEM1_ENABLE(1U) + +#define S_EXT_MEM0_ENABLE 2 +#define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE) +#define F_EXT_MEM0_ENABLE V_EXT_MEM0_ENABLE(1U) + #define A_MA_INT_ENABLE 0x77dc #define S_MEM_PERR_INT_ENABLE 1 @@ -6615,6 +11606,10 @@ #define V_MEM_WRAP_INT_ENABLE(x) ((x) << S_MEM_WRAP_INT_ENABLE) #define F_MEM_WRAP_INT_ENABLE V_MEM_WRAP_INT_ENABLE(1U) +#define S_MEM_TO_INT_ENABLE 2 +#define V_MEM_TO_INT_ENABLE(x) ((x) << S_MEM_TO_INT_ENABLE) +#define F_MEM_TO_INT_ENABLE V_MEM_TO_INT_ENABLE(1U) + #define A_MA_INT_CAUSE 0x77e0 #define S_MEM_PERR_INT_CAUSE 1 @@ -6625,6 +11620,10 @@ #define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE) #define F_MEM_WRAP_INT_CAUSE V_MEM_WRAP_INT_CAUSE(1U) +#define S_MEM_TO_INT_CAUSE 2 +#define V_MEM_TO_INT_CAUSE(x) ((x) << S_MEM_TO_INT_CAUSE) +#define F_MEM_TO_INT_CAUSE V_MEM_TO_INT_CAUSE(1U) + #define A_MA_INT_WRAP_STATUS 0x77e4 #define S_MEM_WRAP_ADDRESS 4 @@ -6782,6 +11781,7 @@ #define V_CL0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR_EN) #define F_CL0_PAR_RDQUEUE_ERROR_EN V_CL0_PAR_RDQUEUE_ERROR_EN(1U) +#define A_MA_PARITY_ERROR_ENABLE1 0x77f0 #define A_MA_PARITY_ERROR_STATUS 0x77f4 #define S_TP_DMARBT_PAR_ERROR 31 @@ -6912,6 +11912,7 @@ #define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR) #define F_CL0_PAR_RDQUEUE_ERROR V_CL0_PAR_RDQUEUE_ERROR(1U) +#define A_MA_PARITY_ERROR_STATUS1 0x77f4 #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8 #define S_BONUS_REG 6 @@ -6941,6 +11942,734 @@ #define V_UE_ENABLE(x) ((x) << S_UE_ENABLE) #define F_UE_ENABLE V_UE_ENABLE(1U) +#define S_FUTURE_EXPANSION 1 +#define M_FUTURE_EXPANSION 0x7fffffffU +#define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION) +#define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION) + +#define A_MA_PARITY_ERROR_ENABLE2 0x7800 + +#define S_ARB4_PAR_WRQUEUE_ERROR_EN 1 +#define V_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR_EN) +#define F_ARB4_PAR_WRQUEUE_ERROR_EN V_ARB4_PAR_WRQUEUE_ERROR_EN(1U) + +#define S_ARB4_PAR_RDQUEUE_ERROR_EN 0 +#define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN) +#define F_ARB4_PAR_RDQUEUE_ERROR_EN V_ARB4_PAR_RDQUEUE_ERROR_EN(1U) + +#define A_MA_PARITY_ERROR_STATUS2 0x7804 + +#define S_ARB4_PAR_WRQUEUE_ERROR 1 +#define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR) +#define F_ARB4_PAR_WRQUEUE_ERROR V_ARB4_PAR_WRQUEUE_ERROR(1U) + +#define S_ARB4_PAR_RDQUEUE_ERROR 0 +#define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR) +#define F_ARB4_PAR_RDQUEUE_ERROR V_ARB4_PAR_RDQUEUE_ERROR(1U) + +#define A_MA_EXT_MEMORY1_BAR 0x7808 + +#define S_EXT_MEM1_BASE 16 +#define M_EXT_MEM1_BASE 0xfffU +#define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE) +#define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE) + +#define S_EXT_MEM1_SIZE 0 +#define M_EXT_MEM1_SIZE 0xfffU +#define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE) +#define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE) + +#define A_MA_PMTX_THROTTLE 0x780c + +#define S_FL_ENABLE 31 +#define V_FL_ENABLE(x) ((x) << S_FL_ENABLE) +#define F_FL_ENABLE V_FL_ENABLE(1U) + +#define S_FL_LIMIT 0 +#define M_FL_LIMIT 0xffU +#define V_FL_LIMIT(x) ((x) << S_FL_LIMIT) +#define G_FL_LIMIT(x) (((x) >> S_FL_LIMIT) & M_FL_LIMIT) + +#define A_MA_PMRX_THROTTLE 0x7810 +#define A_MA_SGE_TH0_WRDATA_CNT 0x7814 +#define A_MA_SGE_TH1_WRDATA_CNT 0x7818 +#define A_MA_ULPTX_WRDATA_CNT 0x781c +#define A_MA_ULPRX_WRDATA_CNT 0x7820 +#define A_MA_ULPTXRX_WRDATA_CNT 0x7824 +#define A_MA_TP_TH0_WRDATA_CNT 0x7828 +#define A_MA_TP_TH1_WRDATA_CNT 0x782c +#define A_MA_LE_WRDATA_CNT 0x7830 +#define A_MA_CIM_WRDATA_CNT 0x7834 +#define A_MA_PCIE_WRDATA_CNT 0x7838 +#define A_MA_PMTX_WRDATA_CNT 0x783c +#define A_MA_PMRX_WRDATA_CNT 0x7840 +#define A_MA_HMA_WRDATA_CNT 0x7844 +#define A_MA_SGE_TH0_RDDATA_CNT 0x7848 +#define A_MA_SGE_TH1_RDDATA_CNT 0x784c +#define A_MA_ULPTX_RDDATA_CNT 0x7850 +#define A_MA_ULPRX_RDDATA_CNT 0x7854 +#define A_MA_ULPTXRX_RDDATA_CNT 0x7858 +#define A_MA_TP_TH0_RDDATA_CNT 0x785c +#define A_MA_TP_TH1_RDDATA_CNT 0x7860 +#define A_MA_LE_RDDATA_CNT 0x7864 +#define A_MA_CIM_RDDATA_CNT 0x7868 +#define A_MA_PCIE_RDDATA_CNT 0x786c +#define A_MA_PMTX_RDDATA_CNT 0x7870 +#define A_MA_PMRX_RDDATA_CNT 0x7874 +#define A_MA_HMA_RDDATA_CNT 0x7878 +#define A_MA_EDRAM0_WRDATA_CNT1 0x787c +#define A_MA_EDRAM0_WRDATA_CNT0 0x7880 +#define A_MA_EDRAM1_WRDATA_CNT1 0x7884 +#define A_MA_EDRAM1_WRDATA_CNT0 0x7888 +#define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c +#define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890 +#define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894 +#define A_MA_HOST_MEMORY_WRDATA_CNT0 0x7898 +#define A_MA_EXT_MEMORY1_WRDATA_CNT1 0x789c +#define A_MA_EXT_MEMORY1_WRDATA_CNT0 0x78a0 +#define A_MA_EDRAM0_RDDATA_CNT1 0x78a4 +#define A_MA_EDRAM0_RDDATA_CNT0 0x78a8 +#define A_MA_EDRAM1_RDDATA_CNT1 0x78ac +#define A_MA_EDRAM1_RDDATA_CNT0 0x78b0 +#define A_MA_EXT_MEMORY0_RDDATA_CNT1 0x78b4 +#define A_MA_EXT_MEMORY0_RDDATA_CNT0 0x78b8 +#define A_MA_HOST_MEMORY_RDDATA_CNT1 0x78bc +#define A_MA_HOST_MEMORY_RDDATA_CNT0 0x78c0 +#define A_MA_EXT_MEMORY1_RDDATA_CNT1 0x78c4 +#define A_MA_EXT_MEMORY1_RDDATA_CNT0 0x78c8 +#define A_MA_TIMEOUT_CFG 0x78cc + +#define S_CLR 31 +#define V_CLR(x) ((x) << S_CLR) +#define F_CLR V_CLR(1U) + +#define S_CNT_LOCK 30 +#define V_CNT_LOCK(x) ((x) << S_CNT_LOCK) +#define F_CNT_LOCK V_CNT_LOCK(1U) + +#define S_WRN 24 +#define V_WRN(x) ((x) << S_WRN) +#define F_WRN V_WRN(1U) + +#define S_DIR 23 +#define V_DIR(x) ((x) << S_DIR) +#define F_DIR V_DIR(1U) + +#define S_TO_BUS 22 +#define V_TO_BUS(x) ((x) << S_TO_BUS) +#define F_TO_BUS V_TO_BUS(1U) + +#define S_CLIENT 16 +#define M_CLIENT 0xfU +#define V_CLIENT(x) ((x) << S_CLIENT) +#define G_CLIENT(x) (((x) >> S_CLIENT) & M_CLIENT) + +#define A_MA_TIMEOUT_CNT 0x78d0 + +#define S_CNT_VAL 0 +#define M_CNT_VAL 0xffffU +#define V_CNT_VAL(x) ((x) << S_CNT_VAL) +#define G_CNT_VAL(x) (((x) >> S_CNT_VAL) & M_CNT_VAL) + +#define A_MA_WRITE_TIMEOUT_ERROR_ENABLE 0x78d4 + +#define S_FUTURE_CEXPANSION 29 +#define M_FUTURE_CEXPANSION 0x7U +#define V_FUTURE_CEXPANSION(x) ((x) << S_FUTURE_CEXPANSION) +#define G_FUTURE_CEXPANSION(x) \ + (((x) >> S_FUTURE_CEXPANSION) & M_FUTURE_CEXPANSION) + +#define S_CL12_WR_CMD_TO_EN 28 +#define V_CL12_WR_CMD_TO_EN(x) ((x) << S_CL12_WR_CMD_TO_EN) +#define F_CL12_WR_CMD_TO_EN V_CL12_WR_CMD_TO_EN(1U) + +#define S_CL11_WR_CMD_TO_EN 27 +#define V_CL11_WR_CMD_TO_EN(x) ((x) << S_CL11_WR_CMD_TO_EN) +#define F_CL11_WR_CMD_TO_EN V_CL11_WR_CMD_TO_EN(1U) + +#define S_CL10_WR_CMD_TO_EN 26 +#define V_CL10_WR_CMD_TO_EN(x) ((x) << S_CL10_WR_CMD_TO_EN) +#define F_CL10_WR_CMD_TO_EN V_CL10_WR_CMD_TO_EN(1U) + +#define S_CL9_WR_CMD_TO_EN 25 +#define V_CL9_WR_CMD_TO_EN(x) ((x) << S_CL9_WR_CMD_TO_EN) +#define F_CL9_WR_CMD_TO_EN V_CL9_WR_CMD_TO_EN(1U) + +#define S_CL8_WR_CMD_TO_EN 24 +#define V_CL8_WR_CMD_TO_EN(x) ((x) << S_CL8_WR_CMD_TO_EN) +#define F_CL8_WR_CMD_TO_EN V_CL8_WR_CMD_TO_EN(1U) + +#define S_CL7_WR_CMD_TO_EN 23 +#define V_CL7_WR_CMD_TO_EN(x) ((x) << S_CL7_WR_CMD_TO_EN) +#define F_CL7_WR_CMD_TO_EN V_CL7_WR_CMD_TO_EN(1U) + +#define S_CL6_WR_CMD_TO_EN 22 +#define V_CL6_WR_CMD_TO_EN(x) ((x) << S_CL6_WR_CMD_TO_EN) +#define F_CL6_WR_CMD_TO_EN V_CL6_WR_CMD_TO_EN(1U) + +#define S_CL5_WR_CMD_TO_EN 21 +#define V_CL5_WR_CMD_TO_EN(x) ((x) << S_CL5_WR_CMD_TO_EN) +#define F_CL5_WR_CMD_TO_EN V_CL5_WR_CMD_TO_EN(1U) + +#define S_CL4_WR_CMD_TO_EN 20 +#define V_CL4_WR_CMD_TO_EN(x) ((x) << S_CL4_WR_CMD_TO_EN) +#define F_CL4_WR_CMD_TO_EN V_CL4_WR_CMD_TO_EN(1U) + +#define S_CL3_WR_CMD_TO_EN 19 +#define V_CL3_WR_CMD_TO_EN(x) ((x) << S_CL3_WR_CMD_TO_EN) +#define F_CL3_WR_CMD_TO_EN V_CL3_WR_CMD_TO_EN(1U) + +#define S_CL2_WR_CMD_TO_EN 18 +#define V_CL2_WR_CMD_TO_EN(x) ((x) << S_CL2_WR_CMD_TO_EN) +#define F_CL2_WR_CMD_TO_EN V_CL2_WR_CMD_TO_EN(1U) + +#define S_CL1_WR_CMD_TO_EN 17 +#define V_CL1_WR_CMD_TO_EN(x) ((x) << S_CL1_WR_CMD_TO_EN) +#define F_CL1_WR_CMD_TO_EN V_CL1_WR_CMD_TO_EN(1U) + +#define S_CL0_WR_CMD_TO_EN 16 +#define V_CL0_WR_CMD_TO_EN(x) ((x) << S_CL0_WR_CMD_TO_EN) +#define F_CL0_WR_CMD_TO_EN V_CL0_WR_CMD_TO_EN(1U) + +#define S_FUTURE_DEXPANSION 13 +#define M_FUTURE_DEXPANSION 0x7U +#define V_FUTURE_DEXPANSION(x) ((x) << S_FUTURE_DEXPANSION) +#define G_FUTURE_DEXPANSION(x) \ + (((x) >> S_FUTURE_DEXPANSION) & M_FUTURE_DEXPANSION) + +#define S_CL12_WR_DATA_TO_EN 12 +#define V_CL12_WR_DATA_TO_EN(x) ((x) << S_CL12_WR_DATA_TO_EN) +#define F_CL12_WR_DATA_TO_EN V_CL12_WR_DATA_TO_EN(1U) + +#define S_CL11_WR_DATA_TO_EN 11 +#define V_CL11_WR_DATA_TO_EN(x) ((x) << S_CL11_WR_DATA_TO_EN) +#define F_CL11_WR_DATA_TO_EN V_CL11_WR_DATA_TO_EN(1U) + +#define S_CL10_WR_DATA_TO_EN 10 +#define V_CL10_WR_DATA_TO_EN(x) ((x) << S_CL10_WR_DATA_TO_EN) +#define F_CL10_WR_DATA_TO_EN V_CL10_WR_DATA_TO_EN(1U) + +#define S_CL9_WR_DATA_TO_EN 9 +#define V_CL9_WR_DATA_TO_EN(x) ((x) << S_CL9_WR_DATA_TO_EN) +#define F_CL9_WR_DATA_TO_EN V_CL9_WR_DATA_TO_EN(1U) + +#define S_CL8_WR_DATA_TO_EN 8 +#define V_CL8_WR_DATA_TO_EN(x) ((x) << S_CL8_WR_DATA_TO_EN) +#define F_CL8_WR_DATA_TO_EN V_CL8_WR_DATA_TO_EN(1U) + +#define S_CL7_WR_DATA_TO_EN 7 +#define V_CL7_WR_DATA_TO_EN(x) ((x) << S_CL7_WR_DATA_TO_EN) +#define F_CL7_WR_DATA_TO_EN V_CL7_WR_DATA_TO_EN(1U) + +#define S_CL6_WR_DATA_TO_EN 6 +#define V_CL6_WR_DATA_TO_EN(x) ((x) << S_CL6_WR_DATA_TO_EN) +#define F_CL6_WR_DATA_TO_EN V_CL6_WR_DATA_TO_EN(1U) + +#define S_CL5_WR_DATA_TO_EN 5 +#define V_CL5_WR_DATA_TO_EN(x) ((x) << S_CL5_WR_DATA_TO_EN) +#define F_CL5_WR_DATA_TO_EN V_CL5_WR_DATA_TO_EN(1U) + +#define S_CL4_WR_DATA_TO_EN 4 +#define V_CL4_WR_DATA_TO_EN(x) ((x) << S_CL4_WR_DATA_TO_EN) +#define F_CL4_WR_DATA_TO_EN V_CL4_WR_DATA_TO_EN(1U) + +#define S_CL3_WR_DATA_TO_EN 3 +#define V_CL3_WR_DATA_TO_EN(x) ((x) << S_CL3_WR_DATA_TO_EN) +#define F_CL3_WR_DATA_TO_EN V_CL3_WR_DATA_TO_EN(1U) + +#define S_CL2_WR_DATA_TO_EN 2 +#define V_CL2_WR_DATA_TO_EN(x) ((x) << S_CL2_WR_DATA_TO_EN) +#define F_CL2_WR_DATA_TO_EN V_CL2_WR_DATA_TO_EN(1U) + +#define S_CL1_WR_DATA_TO_EN 1 +#define V_CL1_WR_DATA_TO_EN(x) ((x) << S_CL1_WR_DATA_TO_EN) +#define F_CL1_WR_DATA_TO_EN V_CL1_WR_DATA_TO_EN(1U) + +#define S_CL0_WR_DATA_TO_EN 0 +#define V_CL0_WR_DATA_TO_EN(x) ((x) << S_CL0_WR_DATA_TO_EN) +#define F_CL0_WR_DATA_TO_EN V_CL0_WR_DATA_TO_EN(1U) + +#define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8 + +#define S_CL12_WR_CMD_TO_ERROR 28 +#define V_CL12_WR_CMD_TO_ERROR(x) ((x) << S_CL12_WR_CMD_TO_ERROR) +#define F_CL12_WR_CMD_TO_ERROR V_CL12_WR_CMD_TO_ERROR(1U) + +#define S_CL11_WR_CMD_TO_ERROR 27 +#define V_CL11_WR_CMD_TO_ERROR(x) ((x) << S_CL11_WR_CMD_TO_ERROR) +#define F_CL11_WR_CMD_TO_ERROR V_CL11_WR_CMD_TO_ERROR(1U) + +#define S_CL10_WR_CMD_TO_ERROR 26 +#define V_CL10_WR_CMD_TO_ERROR(x) ((x) << S_CL10_WR_CMD_TO_ERROR) +#define F_CL10_WR_CMD_TO_ERROR V_CL10_WR_CMD_TO_ERROR(1U) + +#define S_CL9_WR_CMD_TO_ERROR 25 +#define V_CL9_WR_CMD_TO_ERROR(x) ((x) << S_CL9_WR_CMD_TO_ERROR) +#define F_CL9_WR_CMD_TO_ERROR V_CL9_WR_CMD_TO_ERROR(1U) + +#define S_CL8_WR_CMD_TO_ERROR 24 +#define V_CL8_WR_CMD_TO_ERROR(x) ((x) << S_CL8_WR_CMD_TO_ERROR) +#define F_CL8_WR_CMD_TO_ERROR V_CL8_WR_CMD_TO_ERROR(1U) + +#define S_CL7_WR_CMD_TO_ERROR 23 +#define V_CL7_WR_CMD_TO_ERROR(x) ((x) << S_CL7_WR_CMD_TO_ERROR) +#define F_CL7_WR_CMD_TO_ERROR V_CL7_WR_CMD_TO_ERROR(1U) + +#define S_CL6_WR_CMD_TO_ERROR 22 +#define V_CL6_WR_CMD_TO_ERROR(x) ((x) << S_CL6_WR_CMD_TO_ERROR) +#define F_CL6_WR_CMD_TO_ERROR V_CL6_WR_CMD_TO_ERROR(1U) + +#define S_CL5_WR_CMD_TO_ERROR 21 +#define V_CL5_WR_CMD_TO_ERROR(x) ((x) << S_CL5_WR_CMD_TO_ERROR) +#define F_CL5_WR_CMD_TO_ERROR V_CL5_WR_CMD_TO_ERROR(1U) + +#define S_CL4_WR_CMD_TO_ERROR 20 +#define V_CL4_WR_CMD_TO_ERROR(x) ((x) << S_CL4_WR_CMD_TO_ERROR) +#define F_CL4_WR_CMD_TO_ERROR V_CL4_WR_CMD_TO_ERROR(1U) + +#define S_CL3_WR_CMD_TO_ERROR 19 +#define V_CL3_WR_CMD_TO_ERROR(x) ((x) << S_CL3_WR_CMD_TO_ERROR) +#define F_CL3_WR_CMD_TO_ERROR V_CL3_WR_CMD_TO_ERROR(1U) + +#define S_CL2_WR_CMD_TO_ERROR 18 +#define V_CL2_WR_CMD_TO_ERROR(x) ((x) << S_CL2_WR_CMD_TO_ERROR) +#define F_CL2_WR_CMD_TO_ERROR V_CL2_WR_CMD_TO_ERROR(1U) + +#define S_CL1_WR_CMD_TO_ERROR 17 +#define V_CL1_WR_CMD_TO_ERROR(x) ((x) << S_CL1_WR_CMD_TO_ERROR) +#define F_CL1_WR_CMD_TO_ERROR V_CL1_WR_CMD_TO_ERROR(1U) + +#define S_CL0_WR_CMD_TO_ERROR 16 +#define V_CL0_WR_CMD_TO_ERROR(x) ((x) << S_CL0_WR_CMD_TO_ERROR) +#define F_CL0_WR_CMD_TO_ERROR V_CL0_WR_CMD_TO_ERROR(1U) + +#define S_CL12_WR_DATA_TO_ERROR 12 +#define V_CL12_WR_DATA_TO_ERROR(x) ((x) << S_CL12_WR_DATA_TO_ERROR) +#define F_CL12_WR_DATA_TO_ERROR V_CL12_WR_DATA_TO_ERROR(1U) + +#define S_CL11_WR_DATA_TO_ERROR 11 +#define V_CL11_WR_DATA_TO_ERROR(x) ((x) << S_CL11_WR_DATA_TO_ERROR) +#define F_CL11_WR_DATA_TO_ERROR V_CL11_WR_DATA_TO_ERROR(1U) + +#define S_CL10_WR_DATA_TO_ERROR 10 +#define V_CL10_WR_DATA_TO_ERROR(x) ((x) << S_CL10_WR_DATA_TO_ERROR) +#define F_CL10_WR_DATA_TO_ERROR V_CL10_WR_DATA_TO_ERROR(1U) + +#define S_CL9_WR_DATA_TO_ERROR 9 +#define V_CL9_WR_DATA_TO_ERROR(x) ((x) << S_CL9_WR_DATA_TO_ERROR) +#define F_CL9_WR_DATA_TO_ERROR V_CL9_WR_DATA_TO_ERROR(1U) + +#define S_CL8_WR_DATA_TO_ERROR 8 +#define V_CL8_WR_DATA_TO_ERROR(x) ((x) << S_CL8_WR_DATA_TO_ERROR) +#define F_CL8_WR_DATA_TO_ERROR V_CL8_WR_DATA_TO_ERROR(1U) + +#define S_CL7_WR_DATA_TO_ERROR 7 +#define V_CL7_WR_DATA_TO_ERROR(x) ((x) << S_CL7_WR_DATA_TO_ERROR) +#define F_CL7_WR_DATA_TO_ERROR V_CL7_WR_DATA_TO_ERROR(1U) + +#define S_CL6_WR_DATA_TO_ERROR 6 +#define V_CL6_WR_DATA_TO_ERROR(x) ((x) << S_CL6_WR_DATA_TO_ERROR) +#define F_CL6_WR_DATA_TO_ERROR V_CL6_WR_DATA_TO_ERROR(1U) + +#define S_CL5_WR_DATA_TO_ERROR 5 +#define V_CL5_WR_DATA_TO_ERROR(x) ((x) << S_CL5_WR_DATA_TO_ERROR) +#define F_CL5_WR_DATA_TO_ERROR V_CL5_WR_DATA_TO_ERROR(1U) + +#define S_CL4_WR_DATA_TO_ERROR 4 +#define V_CL4_WR_DATA_TO_ERROR(x) ((x) << S_CL4_WR_DATA_TO_ERROR) +#define F_CL4_WR_DATA_TO_ERROR V_CL4_WR_DATA_TO_ERROR(1U) + +#define S_CL3_WR_DATA_TO_ERROR 3 +#define V_CL3_WR_DATA_TO_ERROR(x) ((x) << S_CL3_WR_DATA_TO_ERROR) +#define F_CL3_WR_DATA_TO_ERROR V_CL3_WR_DATA_TO_ERROR(1U) + +#define S_CL2_WR_DATA_TO_ERROR 2 +#define V_CL2_WR_DATA_TO_ERROR(x) ((x) << S_CL2_WR_DATA_TO_ERROR) +#define F_CL2_WR_DATA_TO_ERROR V_CL2_WR_DATA_TO_ERROR(1U) + +#define S_CL1_WR_DATA_TO_ERROR 1 +#define V_CL1_WR_DATA_TO_ERROR(x) ((x) << S_CL1_WR_DATA_TO_ERROR) +#define F_CL1_WR_DATA_TO_ERROR V_CL1_WR_DATA_TO_ERROR(1U) + +#define S_CL0_WR_DATA_TO_ERROR 0 +#define V_CL0_WR_DATA_TO_ERROR(x) ((x) << S_CL0_WR_DATA_TO_ERROR) +#define F_CL0_WR_DATA_TO_ERROR V_CL0_WR_DATA_TO_ERROR(1U) + +#define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc + +#define S_CL12_RD_CMD_TO_EN 28 +#define V_CL12_RD_CMD_TO_EN(x) ((x) << S_CL12_RD_CMD_TO_EN) +#define F_CL12_RD_CMD_TO_EN V_CL12_RD_CMD_TO_EN(1U) + +#define S_CL11_RD_CMD_TO_EN 27 +#define V_CL11_RD_CMD_TO_EN(x) ((x) << S_CL11_RD_CMD_TO_EN) +#define F_CL11_RD_CMD_TO_EN V_CL11_RD_CMD_TO_EN(1U) + +#define S_CL10_RD_CMD_TO_EN 26 +#define V_CL10_RD_CMD_TO_EN(x) ((x) << S_CL10_RD_CMD_TO_EN) +#define F_CL10_RD_CMD_TO_EN V_CL10_RD_CMD_TO_EN(1U) + +#define S_CL9_RD_CMD_TO_EN 25 +#define V_CL9_RD_CMD_TO_EN(x) ((x) << S_CL9_RD_CMD_TO_EN) +#define F_CL9_RD_CMD_TO_EN V_CL9_RD_CMD_TO_EN(1U) + +#define S_CL8_RD_CMD_TO_EN 24 +#define V_CL8_RD_CMD_TO_EN(x) ((x) << S_CL8_RD_CMD_TO_EN) +#define F_CL8_RD_CMD_TO_EN V_CL8_RD_CMD_TO_EN(1U) + +#define S_CL7_RD_CMD_TO_EN 23 +#define V_CL7_RD_CMD_TO_EN(x) ((x) << S_CL7_RD_CMD_TO_EN) +#define F_CL7_RD_CMD_TO_EN V_CL7_RD_CMD_TO_EN(1U) + +#define S_CL6_RD_CMD_TO_EN 22 +#define V_CL6_RD_CMD_TO_EN(x) ((x) << S_CL6_RD_CMD_TO_EN) +#define F_CL6_RD_CMD_TO_EN V_CL6_RD_CMD_TO_EN(1U) + +#define S_CL5_RD_CMD_TO_EN 21 +#define V_CL5_RD_CMD_TO_EN(x) ((x) << S_CL5_RD_CMD_TO_EN) +#define F_CL5_RD_CMD_TO_EN V_CL5_RD_CMD_TO_EN(1U) + +#define S_CL4_RD_CMD_TO_EN 20 +#define V_CL4_RD_CMD_TO_EN(x) ((x) << S_CL4_RD_CMD_TO_EN) +#define F_CL4_RD_CMD_TO_EN V_CL4_RD_CMD_TO_EN(1U) + +#define S_CL3_RD_CMD_TO_EN 19 +#define V_CL3_RD_CMD_TO_EN(x) ((x) << S_CL3_RD_CMD_TO_EN) +#define F_CL3_RD_CMD_TO_EN V_CL3_RD_CMD_TO_EN(1U) + +#define S_CL2_RD_CMD_TO_EN 18 +#define V_CL2_RD_CMD_TO_EN(x) ((x) << S_CL2_RD_CMD_TO_EN) +#define F_CL2_RD_CMD_TO_EN V_CL2_RD_CMD_TO_EN(1U) + +#define S_CL1_RD_CMD_TO_EN 17 +#define V_CL1_RD_CMD_TO_EN(x) ((x) << S_CL1_RD_CMD_TO_EN) +#define F_CL1_RD_CMD_TO_EN V_CL1_RD_CMD_TO_EN(1U) + +#define S_CL0_RD_CMD_TO_EN 16 +#define V_CL0_RD_CMD_TO_EN(x) ((x) << S_CL0_RD_CMD_TO_EN) +#define F_CL0_RD_CMD_TO_EN V_CL0_RD_CMD_TO_EN(1U) + +#define S_CL12_RD_DATA_TO_EN 12 +#define V_CL12_RD_DATA_TO_EN(x) ((x) << S_CL12_RD_DATA_TO_EN) +#define F_CL12_RD_DATA_TO_EN V_CL12_RD_DATA_TO_EN(1U) + +#define S_CL11_RD_DATA_TO_EN 11 +#define V_CL11_RD_DATA_TO_EN(x) ((x) << S_CL11_RD_DATA_TO_EN) +#define F_CL11_RD_DATA_TO_EN V_CL11_RD_DATA_TO_EN(1U) + +#define S_CL10_RD_DATA_TO_EN 10 +#define V_CL10_RD_DATA_TO_EN(x) ((x) << S_CL10_RD_DATA_TO_EN) +#define F_CL10_RD_DATA_TO_EN V_CL10_RD_DATA_TO_EN(1U) + +#define S_CL9_RD_DATA_TO_EN 9 +#define V_CL9_RD_DATA_TO_EN(x) ((x) << S_CL9_RD_DATA_TO_EN) +#define F_CL9_RD_DATA_TO_EN V_CL9_RD_DATA_TO_EN(1U) + +#define S_CL8_RD_DATA_TO_EN 8 +#define V_CL8_RD_DATA_TO_EN(x) ((x) << S_CL8_RD_DATA_TO_EN) +#define F_CL8_RD_DATA_TO_EN V_CL8_RD_DATA_TO_EN(1U) + +#define S_CL7_RD_DATA_TO_EN 7 +#define V_CL7_RD_DATA_TO_EN(x) ((x) << S_CL7_RD_DATA_TO_EN) +#define F_CL7_RD_DATA_TO_EN V_CL7_RD_DATA_TO_EN(1U) + +#define S_CL6_RD_DATA_TO_EN 6 +#define V_CL6_RD_DATA_TO_EN(x) ((x) << S_CL6_RD_DATA_TO_EN) +#define F_CL6_RD_DATA_TO_EN V_CL6_RD_DATA_TO_EN(1U) + +#define S_CL5_RD_DATA_TO_EN 5 +#define V_CL5_RD_DATA_TO_EN(x) ((x) << S_CL5_RD_DATA_TO_EN) +#define F_CL5_RD_DATA_TO_EN V_CL5_RD_DATA_TO_EN(1U) + +#define S_CL4_RD_DATA_TO_EN 4 +#define V_CL4_RD_DATA_TO_EN(x) ((x) << S_CL4_RD_DATA_TO_EN) +#define F_CL4_RD_DATA_TO_EN V_CL4_RD_DATA_TO_EN(1U) + +#define S_CL3_RD_DATA_TO_EN 3 +#define V_CL3_RD_DATA_TO_EN(x) ((x) << S_CL3_RD_DATA_TO_EN) +#define F_CL3_RD_DATA_TO_EN V_CL3_RD_DATA_TO_EN(1U) + +#define S_CL2_RD_DATA_TO_EN 2 +#define V_CL2_RD_DATA_TO_EN(x) ((x) << S_CL2_RD_DATA_TO_EN) +#define F_CL2_RD_DATA_TO_EN V_CL2_RD_DATA_TO_EN(1U) + +#define S_CL1_RD_DATA_TO_EN 1 +#define V_CL1_RD_DATA_TO_EN(x) ((x) << S_CL1_RD_DATA_TO_EN) +#define F_CL1_RD_DATA_TO_EN V_CL1_RD_DATA_TO_EN(1U) + +#define S_CL0_RD_DATA_TO_EN 0 +#define V_CL0_RD_DATA_TO_EN(x) ((x) << S_CL0_RD_DATA_TO_EN) +#define F_CL0_RD_DATA_TO_EN V_CL0_RD_DATA_TO_EN(1U) + +#define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0 + +#define S_CL12_RD_CMD_TO_ERROR 28 +#define V_CL12_RD_CMD_TO_ERROR(x) ((x) << S_CL12_RD_CMD_TO_ERROR) +#define F_CL12_RD_CMD_TO_ERROR V_CL12_RD_CMD_TO_ERROR(1U) + +#define S_CL11_RD_CMD_TO_ERROR 27 +#define V_CL11_RD_CMD_TO_ERROR(x) ((x) << S_CL11_RD_CMD_TO_ERROR) +#define F_CL11_RD_CMD_TO_ERROR V_CL11_RD_CMD_TO_ERROR(1U) + +#define S_CL10_RD_CMD_TO_ERROR 26 +#define V_CL10_RD_CMD_TO_ERROR(x) ((x) << S_CL10_RD_CMD_TO_ERROR) +#define F_CL10_RD_CMD_TO_ERROR V_CL10_RD_CMD_TO_ERROR(1U) + +#define S_CL9_RD_CMD_TO_ERROR 25 +#define V_CL9_RD_CMD_TO_ERROR(x) ((x) << S_CL9_RD_CMD_TO_ERROR) +#define F_CL9_RD_CMD_TO_ERROR V_CL9_RD_CMD_TO_ERROR(1U) + +#define S_CL8_RD_CMD_TO_ERROR 24 +#define V_CL8_RD_CMD_TO_ERROR(x) ((x) << S_CL8_RD_CMD_TO_ERROR) +#define F_CL8_RD_CMD_TO_ERROR V_CL8_RD_CMD_TO_ERROR(1U) + +#define S_CL7_RD_CMD_TO_ERROR 23 +#define V_CL7_RD_CMD_TO_ERROR(x) ((x) << S_CL7_RD_CMD_TO_ERROR) +#define F_CL7_RD_CMD_TO_ERROR V_CL7_RD_CMD_TO_ERROR(1U) + +#define S_CL6_RD_CMD_TO_ERROR 22 +#define V_CL6_RD_CMD_TO_ERROR(x) ((x) << S_CL6_RD_CMD_TO_ERROR) +#define F_CL6_RD_CMD_TO_ERROR V_CL6_RD_CMD_TO_ERROR(1U) + +#define S_CL5_RD_CMD_TO_ERROR 21 +#define V_CL5_RD_CMD_TO_ERROR(x) ((x) << S_CL5_RD_CMD_TO_ERROR) +#define F_CL5_RD_CMD_TO_ERROR V_CL5_RD_CMD_TO_ERROR(1U) + +#define S_CL4_RD_CMD_TO_ERROR 20 +#define V_CL4_RD_CMD_TO_ERROR(x) ((x) << S_CL4_RD_CMD_TO_ERROR) +#define F_CL4_RD_CMD_TO_ERROR V_CL4_RD_CMD_TO_ERROR(1U) + +#define S_CL3_RD_CMD_TO_ERROR 19 +#define V_CL3_RD_CMD_TO_ERROR(x) ((x) << S_CL3_RD_CMD_TO_ERROR) +#define F_CL3_RD_CMD_TO_ERROR V_CL3_RD_CMD_TO_ERROR(1U) + +#define S_CL2_RD_CMD_TO_ERROR 18 +#define V_CL2_RD_CMD_TO_ERROR(x) ((x) << S_CL2_RD_CMD_TO_ERROR) +#define F_CL2_RD_CMD_TO_ERROR V_CL2_RD_CMD_TO_ERROR(1U) + +#define S_CL1_RD_CMD_TO_ERROR 17 +#define V_CL1_RD_CMD_TO_ERROR(x) ((x) << S_CL1_RD_CMD_TO_ERROR) +#define F_CL1_RD_CMD_TO_ERROR V_CL1_RD_CMD_TO_ERROR(1U) + +#define S_CL0_RD_CMD_TO_ERROR 16 +#define V_CL0_RD_CMD_TO_ERROR(x) ((x) << S_CL0_RD_CMD_TO_ERROR) +#define F_CL0_RD_CMD_TO_ERROR V_CL0_RD_CMD_TO_ERROR(1U) + +#define S_CL12_RD_DATA_TO_ERROR 12 +#define V_CL12_RD_DATA_TO_ERROR(x) ((x) << S_CL12_RD_DATA_TO_ERROR) +#define F_CL12_RD_DATA_TO_ERROR V_CL12_RD_DATA_TO_ERROR(1U) + +#define S_CL11_RD_DATA_TO_ERROR 11 +#define V_CL11_RD_DATA_TO_ERROR(x) ((x) << S_CL11_RD_DATA_TO_ERROR) +#define F_CL11_RD_DATA_TO_ERROR V_CL11_RD_DATA_TO_ERROR(1U) + +#define S_CL10_RD_DATA_TO_ERROR 10 +#define V_CL10_RD_DATA_TO_ERROR(x) ((x) << S_CL10_RD_DATA_TO_ERROR) +#define F_CL10_RD_DATA_TO_ERROR V_CL10_RD_DATA_TO_ERROR(1U) + +#define S_CL9_RD_DATA_TO_ERROR 9 +#define V_CL9_RD_DATA_TO_ERROR(x) ((x) << S_CL9_RD_DATA_TO_ERROR) +#define F_CL9_RD_DATA_TO_ERROR V_CL9_RD_DATA_TO_ERROR(1U) + +#define S_CL8_RD_DATA_TO_ERROR 8 +#define V_CL8_RD_DATA_TO_ERROR(x) ((x) << S_CL8_RD_DATA_TO_ERROR) +#define F_CL8_RD_DATA_TO_ERROR V_CL8_RD_DATA_TO_ERROR(1U) + +#define S_CL7_RD_DATA_TO_ERROR 7 +#define V_CL7_RD_DATA_TO_ERROR(x) ((x) << S_CL7_RD_DATA_TO_ERROR) +#define F_CL7_RD_DATA_TO_ERROR V_CL7_RD_DATA_TO_ERROR(1U) + +#define S_CL6_RD_DATA_TO_ERROR 6 +#define V_CL6_RD_DATA_TO_ERROR(x) ((x) << S_CL6_RD_DATA_TO_ERROR) +#define F_CL6_RD_DATA_TO_ERROR V_CL6_RD_DATA_TO_ERROR(1U) + +#define S_CL5_RD_DATA_TO_ERROR 5 +#define V_CL5_RD_DATA_TO_ERROR(x) ((x) << S_CL5_RD_DATA_TO_ERROR) +#define F_CL5_RD_DATA_TO_ERROR V_CL5_RD_DATA_TO_ERROR(1U) + +#define S_CL4_RD_DATA_TO_ERROR 4 +#define V_CL4_RD_DATA_TO_ERROR(x) ((x) << S_CL4_RD_DATA_TO_ERROR) +#define F_CL4_RD_DATA_TO_ERROR V_CL4_RD_DATA_TO_ERROR(1U) + +#define S_CL3_RD_DATA_TO_ERROR 3 +#define V_CL3_RD_DATA_TO_ERROR(x) ((x) << S_CL3_RD_DATA_TO_ERROR) +#define F_CL3_RD_DATA_TO_ERROR V_CL3_RD_DATA_TO_ERROR(1U) + +#define S_CL2_RD_DATA_TO_ERROR 2 +#define V_CL2_RD_DATA_TO_ERROR(x) ((x) << S_CL2_RD_DATA_TO_ERROR) +#define F_CL2_RD_DATA_TO_ERROR V_CL2_RD_DATA_TO_ERROR(1U) + +#define S_CL1_RD_DATA_TO_ERROR 1 +#define V_CL1_RD_DATA_TO_ERROR(x) ((x) << S_CL1_RD_DATA_TO_ERROR) +#define F_CL1_RD_DATA_TO_ERROR V_CL1_RD_DATA_TO_ERROR(1U) + +#define S_CL0_RD_DATA_TO_ERROR 0 +#define V_CL0_RD_DATA_TO_ERROR(x) ((x) << S_CL0_RD_DATA_TO_ERROR) +#define F_CL0_RD_DATA_TO_ERROR V_CL0_RD_DATA_TO_ERROR(1U) + +#define A_MA_BKP_CNT_SEL 0x78e4 + +#define S_BKP_CNT_TYPE 30 +#define M_BKP_CNT_TYPE 0x3U +#define V_BKP_CNT_TYPE(x) ((x) << S_BKP_CNT_TYPE) +#define G_BKP_CNT_TYPE(x) (((x) >> S_BKP_CNT_TYPE) & M_BKP_CNT_TYPE) + +#define S_BKP_CLIENT 24 +#define M_BKP_CLIENT 0xfU +#define V_BKP_CLIENT(x) ((x) << S_BKP_CLIENT) +#define G_BKP_CLIENT(x) (((x) >> S_BKP_CLIENT) & M_BKP_CLIENT) + +#define A_MA_BKP_CNT 0x78e8 +#define A_MA_WRT_ARB 0x78ec + +#define S_WRT_EN 31 +#define V_WRT_EN(x) ((x) << S_WRT_EN) +#define F_WRT_EN V_WRT_EN(1U) + +#define S_WR_TIM 16 +#define M_WR_TIM 0xffU +#define V_WR_TIM(x) ((x) << S_WR_TIM) +#define G_WR_TIM(x) (((x) >> S_WR_TIM) & M_WR_TIM) + +#define S_RD_WIN 8 +#define M_RD_WIN 0xffU +#define V_RD_WIN(x) ((x) << S_RD_WIN) +#define G_RD_WIN(x) (((x) >> S_RD_WIN) & M_RD_WIN) + +#define S_WR_WIN 0 +#define M_WR_WIN 0xffU +#define V_WR_WIN(x) ((x) << S_WR_WIN) +#define G_WR_WIN(x) (((x) >> S_WR_WIN) & M_WR_WIN) + +#define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0 + +#define S_CL12_IF_PAR_EN 12 +#define V_CL12_IF_PAR_EN(x) ((x) << S_CL12_IF_PAR_EN) +#define F_CL12_IF_PAR_EN V_CL12_IF_PAR_EN(1U) + +#define S_CL11_IF_PAR_EN 11 +#define V_CL11_IF_PAR_EN(x) ((x) << S_CL11_IF_PAR_EN) +#define F_CL11_IF_PAR_EN V_CL11_IF_PAR_EN(1U) + +#define S_CL10_IF_PAR_EN 10 +#define V_CL10_IF_PAR_EN(x) ((x) << S_CL10_IF_PAR_EN) +#define F_CL10_IF_PAR_EN V_CL10_IF_PAR_EN(1U) + +#define S_CL9_IF_PAR_EN 9 +#define V_CL9_IF_PAR_EN(x) ((x) << S_CL9_IF_PAR_EN) +#define F_CL9_IF_PAR_EN V_CL9_IF_PAR_EN(1U) + +#define S_CL8_IF_PAR_EN 8 +#define V_CL8_IF_PAR_EN(x) ((x) << S_CL8_IF_PAR_EN) +#define F_CL8_IF_PAR_EN V_CL8_IF_PAR_EN(1U) + +#define S_CL7_IF_PAR_EN 7 +#define V_CL7_IF_PAR_EN(x) ((x) << S_CL7_IF_PAR_EN) +#define F_CL7_IF_PAR_EN V_CL7_IF_PAR_EN(1U) + +#define S_CL6_IF_PAR_EN 6 +#define V_CL6_IF_PAR_EN(x) ((x) << S_CL6_IF_PAR_EN) +#define F_CL6_IF_PAR_EN V_CL6_IF_PAR_EN(1U) + +#define S_CL5_IF_PAR_EN 5 +#define V_CL5_IF_PAR_EN(x) ((x) << S_CL5_IF_PAR_EN) +#define F_CL5_IF_PAR_EN V_CL5_IF_PAR_EN(1U) + +#define S_CL4_IF_PAR_EN 4 +#define V_CL4_IF_PAR_EN(x) ((x) << S_CL4_IF_PAR_EN) +#define F_CL4_IF_PAR_EN V_CL4_IF_PAR_EN(1U) + +#define S_CL3_IF_PAR_EN 3 +#define V_CL3_IF_PAR_EN(x) ((x) << S_CL3_IF_PAR_EN) +#define F_CL3_IF_PAR_EN V_CL3_IF_PAR_EN(1U) + +#define S_CL2_IF_PAR_EN 2 +#define V_CL2_IF_PAR_EN(x) ((x) << S_CL2_IF_PAR_EN) +#define F_CL2_IF_PAR_EN V_CL2_IF_PAR_EN(1U) + +#define S_CL1_IF_PAR_EN 1 +#define V_CL1_IF_PAR_EN(x) ((x) << S_CL1_IF_PAR_EN) +#define F_CL1_IF_PAR_EN V_CL1_IF_PAR_EN(1U) + +#define S_CL0_IF_PAR_EN 0 +#define V_CL0_IF_PAR_EN(x) ((x) << S_CL0_IF_PAR_EN) +#define F_CL0_IF_PAR_EN V_CL0_IF_PAR_EN(1U) + +#define A_MA_IF_PARITY_ERROR_STATUS 0x78f4 + +#define S_CL12_IF_PAR_ERROR 12 +#define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR) +#define F_CL12_IF_PAR_ERROR V_CL12_IF_PAR_ERROR(1U) + +#define S_CL11_IF_PAR_ERROR 11 +#define V_CL11_IF_PAR_ERROR(x) ((x) << S_CL11_IF_PAR_ERROR) +#define F_CL11_IF_PAR_ERROR V_CL11_IF_PAR_ERROR(1U) + +#define S_CL10_IF_PAR_ERROR 10 +#define V_CL10_IF_PAR_ERROR(x) ((x) << S_CL10_IF_PAR_ERROR) +#define F_CL10_IF_PAR_ERROR V_CL10_IF_PAR_ERROR(1U) + +#define S_CL9_IF_PAR_ERROR 9 +#define V_CL9_IF_PAR_ERROR(x) ((x) << S_CL9_IF_PAR_ERROR) +#define F_CL9_IF_PAR_ERROR V_CL9_IF_PAR_ERROR(1U) + +#define S_CL8_IF_PAR_ERROR 8 +#define V_CL8_IF_PAR_ERROR(x) ((x) << S_CL8_IF_PAR_ERROR) +#define F_CL8_IF_PAR_ERROR V_CL8_IF_PAR_ERROR(1U) + +#define S_CL7_IF_PAR_ERROR 7 +#define V_CL7_IF_PAR_ERROR(x) ((x) << S_CL7_IF_PAR_ERROR) +#define F_CL7_IF_PAR_ERROR V_CL7_IF_PAR_ERROR(1U) + +#define S_CL6_IF_PAR_ERROR 6 +#define V_CL6_IF_PAR_ERROR(x) ((x) << S_CL6_IF_PAR_ERROR) +#define F_CL6_IF_PAR_ERROR V_CL6_IF_PAR_ERROR(1U) + +#define S_CL5_IF_PAR_ERROR 5 +#define V_CL5_IF_PAR_ERROR(x) ((x) << S_CL5_IF_PAR_ERROR) +#define F_CL5_IF_PAR_ERROR V_CL5_IF_PAR_ERROR(1U) + +#define S_CL4_IF_PAR_ERROR 4 +#define V_CL4_IF_PAR_ERROR(x) ((x) << S_CL4_IF_PAR_ERROR) +#define F_CL4_IF_PAR_ERROR V_CL4_IF_PAR_ERROR(1U) + +#define S_CL3_IF_PAR_ERROR 3 +#define V_CL3_IF_PAR_ERROR(x) ((x) << S_CL3_IF_PAR_ERROR) +#define F_CL3_IF_PAR_ERROR V_CL3_IF_PAR_ERROR(1U) + +#define S_CL2_IF_PAR_ERROR 2 +#define V_CL2_IF_PAR_ERROR(x) ((x) << S_CL2_IF_PAR_ERROR) +#define F_CL2_IF_PAR_ERROR V_CL2_IF_PAR_ERROR(1U) + +#define S_CL1_IF_PAR_ERROR 1 +#define V_CL1_IF_PAR_ERROR(x) ((x) << S_CL1_IF_PAR_ERROR) +#define F_CL1_IF_PAR_ERROR V_CL1_IF_PAR_ERROR(1U) + +#define S_CL0_IF_PAR_ERROR 0 +#define V_CL0_IF_PAR_ERROR(x) ((x) << S_CL0_IF_PAR_ERROR) +#define F_CL0_IF_PAR_ERROR V_CL0_IF_PAR_ERROR(1U) + +#define A_MA_LOCAL_DEBUG_CFG 0x78f8 + +#define S_DEBUG_OR 15 +#define V_DEBUG_OR(x) ((x) << S_DEBUG_OR) +#define F_DEBUG_OR V_DEBUG_OR(1U) + +#define S_DEBUG_HI 14 +#define V_DEBUG_HI(x) ((x) << S_DEBUG_HI) +#define F_DEBUG_HI V_DEBUG_HI(1U) + +#define S_DEBUG_RPT 13 +#define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT) +#define F_DEBUG_RPT V_DEBUG_RPT(1U) + +#define S_DEBUGPAGE 10 +#define M_DEBUGPAGE 0x7U +#define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE) +#define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE) + +#define A_MA_LOCAL_DEBUG_RPT 0x78fc + /* registers for module EDC_0 */ #define EDC_0_BASE_ADDR 0x7900 @@ -7061,6 +12790,7 @@ #define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT) #define F_MBMSGRDYINT V_MBMSGRDYINT(1U) +#define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290 #define A_CIM_BOOT_CFG 0x7b00 #define S_BOOTADDR 8 @@ -7230,6 +12960,38 @@ #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN) #define F_PREFDROPINTEN V_PREFDROPINTEN(1U) +#define S_MA_CIM_INTFPERR 28 +#define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR) +#define F_MA_CIM_INTFPERR V_MA_CIM_INTFPERR(1U) + +#define S_PLCIM_MSTRSPDATAPARERR 27 +#define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR) +#define F_PLCIM_MSTRSPDATAPARERR V_PLCIM_MSTRSPDATAPARERR(1U) + +#define S_NCSI2CIMINTFPARERR 26 +#define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR) +#define F_NCSI2CIMINTFPARERR V_NCSI2CIMINTFPARERR(1U) + +#define S_SGE2CIMINTFPARERR 25 +#define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR) +#define F_SGE2CIMINTFPARERR V_SGE2CIMINTFPARERR(1U) + +#define S_ULP2CIMINTFPARERR 24 +#define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR) +#define F_ULP2CIMINTFPARERR V_ULP2CIMINTFPARERR(1U) + +#define S_TP2CIMINTFPARERR 23 +#define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR) +#define F_TP2CIMINTFPARERR V_TP2CIMINTFPARERR(1U) + +#define S_OBQSGERX1PARERR 22 +#define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR) +#define F_OBQSGERX1PARERR V_OBQSGERX1PARERR(1U) + +#define S_OBQSGERX0PARERR 21 +#define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR) +#define F_OBQSGERX0PARERR V_OBQSGERX0PARERR(1U) + #define A_CIM_HOST_INT_CAUSE 0x7b2c #define S_TIEQOUTPARERRINT 20 @@ -7788,6 +13550,11 @@ #define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK) #define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK) +#define S_T5_DPIFHOSTMASK 0 +#define M_T5_DPIFHOSTMASK 0x1fffffffU +#define V_T5_DPIFHOSTMASK(x) ((x) << S_T5_DPIFHOSTMASK) +#define G_T5_DPIFHOSTMASK(x) (((x) >> S_T5_DPIFHOSTMASK) & M_T5_DPIFHOSTMASK) + #define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14 #define S_DPIFHUPAMASK 0 @@ -7802,6 +13569,11 @@ #define V_DUPMASK(x) ((x) << S_DUPMASK) #define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK) +#define S_T5_DUPMASK 0 +#define M_T5_DUPMASK 0x1fffffffU +#define V_T5_DUPMASK(x) ((x) << S_T5_DUPMASK) +#define G_T5_DUPMASK(x) (((x) >> S_T5_DUPMASK) & M_T5_DUPMASK) + #define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c #define S_DUPUACCMASK 0 @@ -7817,6 +13589,11 @@ #define V_PERREN(x) ((x) << S_PERREN) #define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN) +#define S_T5_PERREN 0 +#define M_T5_PERREN 0x1fffffffU +#define V_T5_PERREN(x) ((x) << S_T5_PERREN) +#define G_T5_PERREN(x) (((x) >> S_T5_PERREN) & M_T5_PERREN) + #define A_CIM_EEPROM_BUSY_BIT 0x7c28 #define S_EEPROMBUSY 0 @@ -7838,6 +13615,75 @@ #define A_CIM_CIM_DEBUG_SPARE 0x7c34 #define A_CIM_UP_OPERATION_FREQ 0x7c38 +#define A_CIM_CIM_IBQ_ERR_CODE 0x7c3c + +#define S_CIM_ULP_TX_PKT_ERR_CODE 16 +#define M_CIM_ULP_TX_PKT_ERR_CODE 0xffU +#define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE) +#define G_CIM_ULP_TX_PKT_ERR_CODE(x) \ + (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE) + +#define S_CIM_SGE1_PKT_ERR_CODE 8 +#define M_CIM_SGE1_PKT_ERR_CODE 0xffU +#define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE) +#define G_CIM_SGE1_PKT_ERR_CODE(x) \ + (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE) + +#define S_CIM_SGE0_PKT_ERR_CODE 0 +#define M_CIM_SGE0_PKT_ERR_CODE 0xffU +#define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE) +#define G_CIM_SGE0_PKT_ERR_CODE(x) \ + (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE) + +#define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40 +#define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44 + +#define S_PIO_UP_MST_CFG_SEL 0 +#define V_PIO_UP_MST_CFG_SEL(x) ((x) << S_PIO_UP_MST_CFG_SEL) +#define F_PIO_UP_MST_CFG_SEL V_PIO_UP_MST_CFG_SEL(1U) + +#define A_CIM_CGEN 0x7c48 + +#define S_TSCH_CGEN 0 +#define V_TSCH_CGEN(x) ((x) << S_TSCH_CGEN) +#define F_TSCH_CGEN V_TSCH_CGEN(1U) + +#define A_CIM_QUEUE_FEATURE_DISABLE 0x7c4c + +#define S_OBQ_THROUTTLE_ON_EOP 4 +#define V_OBQ_THROUTTLE_ON_EOP(x) ((x) << S_OBQ_THROUTTLE_ON_EOP) +#define F_OBQ_THROUTTLE_ON_EOP V_OBQ_THROUTTLE_ON_EOP(1U) + +#define S_OBQ_READ_CTL_PERF_MODE_DISABLE 3 +#define V_OBQ_READ_CTL_PERF_MODE_DISABLE(x) \ + ((x) << S_OBQ_READ_CTL_PERF_MODE_DISABLE) +#define F_OBQ_READ_CTL_PERF_MODE_DISABLE V_OBQ_READ_CTL_PERF_MODE_DISABLE(1U) + +#define S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE 2 +#define V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(x) \ + ((x) << S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE) +#define F_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(1U) + +#define S_IBQ_RRA_DSBL 1 +#define V_IBQ_RRA_DSBL(x) ((x) << S_IBQ_RRA_DSBL) +#define F_IBQ_RRA_DSBL V_IBQ_RRA_DSBL(1U) + +#define S_IBQ_SKID_FIFO_EOP_FLSH_DSBL 0 +#define V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(x) ((x) << S_IBQ_SKID_FIFO_EOP_FLSH_DSBL) +#define F_IBQ_SKID_FIFO_EOP_FLSH_DSBL V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(1U) + +#define A_CIM_CGEN_GLOBAL 0x7c50 + +#define S_CGEN_GLOBAL 0 +#define V_CGEN_GLOBAL(x) ((x) << S_CGEN_GLOBAL) +#define F_CGEN_GLOBAL V_CGEN_GLOBAL(1U) + +#define A_CIM_DPSLP_EN 0x7c54 + +#define S_PIFDBGLA_DPSLP_EN 0 +#define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN) +#define F_PIFDBGLA_DPSLP_EN V_PIFDBGLA_DPSLP_EN(1U) + /* registers for module TP */ #define TP_BASE_ADDR 0x7d00 @@ -7947,6 +13793,58 @@ #define V_CTUNNEL(x) ((x) << S_CTUNNEL) #define F_CTUNNEL V_CTUNNEL(1U) +#define S_VLANEXTENPORT3 31 +#define V_VLANEXTENPORT3(x) ((x) << S_VLANEXTENPORT3) +#define F_VLANEXTENPORT3 V_VLANEXTENPORT3(1U) + +#define S_VLANEXTENPORT2 30 +#define V_VLANEXTENPORT2(x) ((x) << S_VLANEXTENPORT2) +#define F_VLANEXTENPORT2 V_VLANEXTENPORT2(1U) + +#define S_VLANEXTENPORT1 29 +#define V_VLANEXTENPORT1(x) ((x) << S_VLANEXTENPORT1) +#define F_VLANEXTENPORT1 V_VLANEXTENPORT1(1U) + +#define S_VLANEXTENPORT0 28 +#define V_VLANEXTENPORT0(x) ((x) << S_VLANEXTENPORT0) +#define F_VLANEXTENPORT0 V_VLANEXTENPORT0(1U) + +#define S_VNTAGDEFAULTVAL 13 +#define V_VNTAGDEFAULTVAL(x) ((x) << S_VNTAGDEFAULTVAL) +#define F_VNTAGDEFAULTVAL V_VNTAGDEFAULTVAL(1U) + +#define S_ECHECKUDPLEN 12 +#define V_ECHECKUDPLEN(x) ((x) << S_ECHECKUDPLEN) +#define F_ECHECKUDPLEN V_ECHECKUDPLEN(1U) + +#define S_FCOEFPMA 10 +#define V_FCOEFPMA(x) ((x) << S_FCOEFPMA) +#define F_FCOEFPMA V_FCOEFPMA(1U) + +#define S_VNTAGETHENABLE 8 +#define V_VNTAGETHENABLE(x) ((x) << S_VNTAGETHENABLE) +#define F_VNTAGETHENABLE V_VNTAGETHENABLE(1U) + +#define S_IP_CCSM 7 +#define V_IP_CCSM(x) ((x) << S_IP_CCSM) +#define F_IP_CCSM V_IP_CCSM(1U) + +#define S_CCHECKSUMCHECKUDP 6 +#define V_CCHECKSUMCHECKUDP(x) ((x) << S_CCHECKSUMCHECKUDP) +#define F_CCHECKSUMCHECKUDP V_CCHECKSUMCHECKUDP(1U) + +#define S_TCP_CCSM 5 +#define V_TCP_CCSM(x) ((x) << S_TCP_CCSM) +#define F_TCP_CCSM V_TCP_CCSM(1U) + +#define S_CDEMUX 3 +#define V_CDEMUX(x) ((x) << S_CDEMUX) +#define F_CDEMUX V_CDEMUX(1U) + +#define S_ETHUPEN 2 +#define V_ETHUPEN(x) ((x) << S_ETHUPEN) +#define F_ETHUPEN V_ETHUPEN(1U) + #define A_TP_OUT_CONFIG 0x7d04 #define S_PORTQFCEN 28 @@ -8038,6 +13936,10 @@ #define V_CETHERNET(x) ((x) << S_CETHERNET) #define F_CETHERNET V_CETHERNET(1U) +#define S_EVNTAGEN 9 +#define V_EVNTAGEN(x) ((x) << S_EVNTAGEN) +#define F_EVNTAGEN V_EVNTAGEN(1U) + #define A_TP_GLOBAL_CONFIG 0x7d08 #define S_SYNCOOKIEPARAMS 26 @@ -8116,6 +14018,14 @@ #define V_IPTTL(x) ((x) << S_IPTTL) #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL) +#define S_RSSSYNSTEERENABLE 12 +#define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE) +#define F_RSSSYNSTEERENABLE V_RSSSYNSTEERENABLE(1U) + +#define S_ISSFROMCPLENABLE 11 +#define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE) +#define F_ISSFROMCPLENABLE V_ISSFROMCPLENABLE(1U) + #define A_TP_DB_CONFIG 0x7d0c #define S_DBMAXOPCNT 24 @@ -8396,6 +14306,10 @@ #define V_TXDATAACKPAGEENABLE(x) ((x) << S_TXDATAACKPAGEENABLE) #define F_TXDATAACKPAGEENABLE V_TXDATAACKPAGEENABLE(1U) +#define S_ENABLEFILTERNAT 5 +#define V_ENABLEFILTERNAT(x) ((x) << S_ENABLEFILTERNAT) +#define F_ENABLEFILTERNAT V_ENABLEFILTERNAT(1U) + #define A_TP_PC_CONFIG2 0x7d4c #define S_ENABLEMTUVFMODE 31 @@ -8526,6 +14440,10 @@ #define V_ENABLETNLOFDCLOSED(x) ((x) << S_ENABLETNLOFDCLOSED) #define F_ENABLETNLOFDCLOSED V_ENABLETNLOFDCLOSED(1U) +#define S_ENABLEFINDDPOFF 14 +#define V_ENABLEFINDDPOFF(x) ((x) << S_ENABLEFINDDPOFF) +#define F_ENABLEFINDDPOFF V_ENABLEFINDDPOFF(1U) + #define A_TP_TCP_BACKOFF_REG0 0x7d50 #define S_TIMERBACKOFFINDEX3 24 @@ -8692,6 +14610,19 @@ #define V_SWSTIMER(x) ((x) << S_SWSTIMER) #define F_SWSTIMER V_SWSTIMER(1U) +#define S_LIMTXTHRESH 28 +#define M_LIMTXTHRESH 0xfU +#define V_LIMTXTHRESH(x) ((x) << S_LIMTXTHRESH) +#define G_LIMTXTHRESH(x) (((x) >> S_LIMTXTHRESH) & M_LIMTXTHRESH) + +#define S_CHNERRENABLE 14 +#define V_CHNERRENABLE(x) ((x) << S_CHNERRENABLE) +#define F_CHNERRENABLE V_CHNERRENABLE(1U) + +#define S_SETTIMEENABLE 13 +#define V_SETTIMEENABLE(x) ((x) << S_SETTIMEENABLE) +#define F_SETTIMEENABLE V_SETTIMEENABLE(1U) + #define A_TP_PARA_REG1 0x7d64 #define S_INITRWND 16 @@ -8843,6 +14774,75 @@ #define V_RENOCFG(x) ((x) << S_RENOCFG) #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG) +#define S_IDLECWNDHIGHSPEED 28 +#define V_IDLECWNDHIGHSPEED(x) ((x) << S_IDLECWNDHIGHSPEED) +#define F_IDLECWNDHIGHSPEED V_IDLECWNDHIGHSPEED(1U) + +#define S_RXMTCWNDHIGHSPEED 27 +#define V_RXMTCWNDHIGHSPEED(x) ((x) << S_RXMTCWNDHIGHSPEED) +#define F_RXMTCWNDHIGHSPEED V_RXMTCWNDHIGHSPEED(1U) + +#define S_OVERDRIVEHIGHSPEED 25 +#define M_OVERDRIVEHIGHSPEED 0x3U +#define V_OVERDRIVEHIGHSPEED(x) ((x) << S_OVERDRIVEHIGHSPEED) +#define G_OVERDRIVEHIGHSPEED(x) \ + (((x) >> S_OVERDRIVEHIGHSPEED) & M_OVERDRIVEHIGHSPEED) + +#define S_BYTECOUNTHIGHSPEED 24 +#define V_BYTECOUNTHIGHSPEED(x) ((x) << S_BYTECOUNTHIGHSPEED) +#define F_BYTECOUNTHIGHSPEED V_BYTECOUNTHIGHSPEED(1U) + +#define S_IDLECWNDNEWRENO 20 +#define V_IDLECWNDNEWRENO(x) ((x) << S_IDLECWNDNEWRENO) +#define F_IDLECWNDNEWRENO V_IDLECWNDNEWRENO(1U) + +#define S_RXMTCWNDNEWRENO 19 +#define V_RXMTCWNDNEWRENO(x) ((x) << S_RXMTCWNDNEWRENO) +#define F_RXMTCWNDNEWRENO V_RXMTCWNDNEWRENO(1U) + +#define S_OVERDRIVENEWRENO 17 +#define M_OVERDRIVENEWRENO 0x3U +#define V_OVERDRIVENEWRENO(x) ((x) << S_OVERDRIVENEWRENO) +#define G_OVERDRIVENEWRENO(x) (((x) >> S_OVERDRIVENEWRENO) & M_OVERDRIVENEWRENO) + +#define S_BYTECOUNTNEWRENO 16 +#define V_BYTECOUNTNEWRENO(x) ((x) << S_BYTECOUNTNEWRENO) +#define F_BYTECOUNTNEWRENO V_BYTECOUNTNEWRENO(1U) + +#define S_IDLECWNDTAHOE 12 +#define V_IDLECWNDTAHOE(x) ((x) << S_IDLECWNDTAHOE) +#define F_IDLECWNDTAHOE V_IDLECWNDTAHOE(1U) + +#define S_RXMTCWNDTAHOE 11 +#define V_RXMTCWNDTAHOE(x) ((x) << S_RXMTCWNDTAHOE) +#define F_RXMTCWNDTAHOE V_RXMTCWNDTAHOE(1U) + +#define S_OVERDRIVETAHOE 9 +#define M_OVERDRIVETAHOE 0x3U +#define V_OVERDRIVETAHOE(x) ((x) << S_OVERDRIVETAHOE) +#define G_OVERDRIVETAHOE(x) (((x) >> S_OVERDRIVETAHOE) & M_OVERDRIVETAHOE) + +#define S_BYTECOUNTTAHOE 8 +#define V_BYTECOUNTTAHOE(x) ((x) << S_BYTECOUNTTAHOE) +#define F_BYTECOUNTTAHOE V_BYTECOUNTTAHOE(1U) + +#define S_IDLECWNDRENO 4 +#define V_IDLECWNDRENO(x) ((x) << S_IDLECWNDRENO) +#define F_IDLECWNDRENO V_IDLECWNDRENO(1U) + +#define S_RXMTCWNDRENO 3 +#define V_RXMTCWNDRENO(x) ((x) << S_RXMTCWNDRENO) +#define F_RXMTCWNDRENO V_RXMTCWNDRENO(1U) + +#define S_OVERDRIVERENO 1 +#define M_OVERDRIVERENO 0x3U +#define V_OVERDRIVERENO(x) ((x) << S_OVERDRIVERENO) +#define G_OVERDRIVERENO(x) (((x) >> S_OVERDRIVERENO) & M_OVERDRIVERENO) + +#define S_BYTECOUNTRENO 0 +#define V_BYTECOUNTRENO(x) ((x) << S_BYTECOUNTRENO) +#define F_BYTECOUNTRENO V_BYTECOUNTRENO(1U) + #define A_TP_PARA_REG5 0x7d74 #define S_INDICATESIZE 16 @@ -8891,6 +14891,18 @@ #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE) #define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U) +#define S_ENABLEXOFFPDU 7 +#define V_ENABLEXOFFPDU(x) ((x) << S_ENABLEXOFFPDU) +#define F_ENABLEXOFFPDU V_ENABLEXOFFPDU(1U) + +#define S_ENABLENEWFAR 6 +#define V_ENABLENEWFAR(x) ((x) << S_ENABLENEWFAR) +#define F_ENABLENEWFAR V_ENABLENEWFAR(1U) + +#define S_ENABLEFRAGCHECK 5 +#define V_ENABLEFRAGCHECK(x) ((x) << S_ENABLEFRAGCHECK) +#define F_ENABLEFRAGCHECK V_ENABLEFRAGCHECK(1U) + #define A_TP_PARA_REG6 0x7d78 #define S_TXPDUSIZEADJ 24 @@ -8983,6 +14995,10 @@ #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT) #define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U) +#define S_DISABLEPDUACK 20 +#define V_DISABLEPDUACK(x) ((x) << S_DISABLEPDUACK) +#define F_DISABLEPDUACK V_DISABLEPDUACK(1U) + #define A_TP_PARA_REG7 0x7d7c #define S_PMMAXXFERLEN1 16 @@ -9144,6 +15160,14 @@ #define V_DROPERRORANY(x) ((x) << S_DROPERRORANY) #define F_DROPERRORANY V_DROPERRORANY(1U) +#define S_TNLERRORFPMA 31 +#define V_TNLERRORFPMA(x) ((x) << S_TNLERRORFPMA) +#define F_TNLERRORFPMA V_TNLERRORFPMA(1U) + +#define S_DROPERRORFPMA 15 +#define V_DROPERRORFPMA(x) ((x) << S_DROPERRORFPMA) +#define F_DROPERRORFPMA V_DROPERRORFPMA(1U) + #define A_TP_TIMER_RESOLUTION 0x7d90 #define S_TIMERRESOLUTION 16 @@ -9523,6 +15547,18 @@ #define V_DISABLE(x) ((x) << S_DISABLE) #define F_DISABLE V_DISABLE(1U) +#define S_TNLFCOEMODE 23 +#define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE) +#define F_TNLFCOEMODE V_TNLFCOEMODE(1U) + +#define S_TNLFCOEEN 21 +#define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN) +#define F_TNLFCOEEN V_TNLFCOEEN(1U) + +#define S_HASHXOR 20 +#define V_HASHXOR(x) ((x) << S_HASHXOR) +#define F_HASHXOR V_HASHXOR(1U) + #define A_TP_RSS_CONFIG_TNL 0x7df4 #define S_MASKSIZE 28 @@ -9550,6 +15586,11 @@ #define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH) #define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH) +#define S_FRMWRQUEMASK 12 +#define M_FRMWRQUEMASK 0xfU +#define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK) +#define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK) + #define A_TP_RSS_CONFIG_SYN 0x7dfc #define A_TP_RSS_CONFIG_VRT 0x7e00 @@ -9605,6 +15646,14 @@ #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR) #define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR) +#define S_VFVLANEN 21 +#define V_VFVLANEN(x) ((x) << S_VFVLANEN) +#define F_VFVLANEN V_VFVLANEN(1U) + +#define S_VFFWEN 20 +#define V_VFFWEN(x) ((x) << S_VFFWEN) +#define F_VFFWEN V_VFFWEN(1U) + #define A_TP_RSS_CONFIG_CNG 0x7e04 #define S_CHNCOUNT3 31 @@ -9989,6 +16038,10 @@ #define V_DELINVFIFOPERR(x) ((x) << S_DELINVFIFOPERR) #define F_DELINVFIFOPERR V_DELINVFIFOPERR(1U) +#define S_CTPOUTPLDFIFOPERR 7 +#define V_CTPOUTPLDFIFOPERR(x) ((x) << S_CTPOUTPLDFIFOPERR) +#define F_CTPOUTPLDFIFOPERR V_CTPOUTPLDFIFOPERR(1U) + #define A_TP_INT_CAUSE 0x7e74 #define A_TP_PER_ENABLE 0x7e78 #define A_TP_FLM_FREE_PS_CNT 0x7e80 @@ -10038,6 +16091,7 @@ #define V_DISABLETIMEFREEZE(x) ((x) << S_DISABLETIMEFREEZE) #define F_DISABLETIMEFREEZE V_DISABLETIMEFREEZE(1U) +#define A_TP_STAMP_TIME 0x7ea8 #define A_TP_DEBUG_FLAGS 0x7eac #define S_RXTIMERDACKFIRST 26 @@ -10132,6 +16186,18 @@ #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS) #define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U) +#define S_RXTIMERCOMPBUFFER 27 +#define V_RXTIMERCOMPBUFFER(x) ((x) << S_RXTIMERCOMPBUFFER) +#define F_RXTIMERCOMPBUFFER V_RXTIMERCOMPBUFFER(1U) + +#define S_TXDFRFAST 13 +#define V_TXDFRFAST(x) ((x) << S_TXDFRFAST) +#define F_TXDFRFAST V_TXDFRFAST(1U) + +#define S_TXRXMMISC 12 +#define V_TXRXMMISC(x) ((x) << S_TXRXMMISC) +#define F_TXRXMMISC V_TXRXMMISC(1U) + #define A_TP_RX_SCHED 0x7eb0 #define S_RXCOMMITRESET1 31 @@ -10957,6 +17023,28 @@ #define V_TXPPPENPORT0(x) ((x) << S_TXPPPENPORT0) #define G_TXPPPENPORT0(x) (((x) >> S_TXPPPENPORT0) & M_TXPPPENPORT0) +#define A_TP_RX_SCHED_FIFO 0x2b + +#define S_COMMITLIMIT1H 24 +#define M_COMMITLIMIT1H 0xffU +#define V_COMMITLIMIT1H(x) ((x) << S_COMMITLIMIT1H) +#define G_COMMITLIMIT1H(x) (((x) >> S_COMMITLIMIT1H) & M_COMMITLIMIT1H) + +#define S_COMMITLIMIT1L 16 +#define M_COMMITLIMIT1L 0xffU +#define V_COMMITLIMIT1L(x) ((x) << S_COMMITLIMIT1L) +#define G_COMMITLIMIT1L(x) (((x) >> S_COMMITLIMIT1L) & M_COMMITLIMIT1L) + +#define S_COMMITLIMIT0H 8 +#define M_COMMITLIMIT0H 0xffU +#define V_COMMITLIMIT0H(x) ((x) << S_COMMITLIMIT0H) +#define G_COMMITLIMIT0H(x) (((x) >> S_COMMITLIMIT0H) & M_COMMITLIMIT0H) + +#define S_COMMITLIMIT0L 0 +#define M_COMMITLIMIT0L 0xffU +#define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L) +#define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L) + #define A_TP_IPMI_CFG1 0x2e #define S_VLANENABLE 31 @@ -11225,6 +17313,90 @@ #define V_IPV4TYPE(x) ((x) << S_IPV4TYPE) #define G_IPV4TYPE(x) (((x) >> S_IPV4TYPE) & M_IPV4TYPE) +#define A_TP_ETHER_TYPE_FW 0x52 + +#define S_ETHTYPE1 16 +#define M_ETHTYPE1 0xffffU +#define V_ETHTYPE1(x) ((x) << S_ETHTYPE1) +#define G_ETHTYPE1(x) (((x) >> S_ETHTYPE1) & M_ETHTYPE1) + +#define S_ETHTYPE0 0 +#define M_ETHTYPE0 0xffffU +#define V_ETHTYPE0(x) ((x) << S_ETHTYPE0) +#define G_ETHTYPE0(x) (((x) >> S_ETHTYPE0) & M_ETHTYPE0) + +#define A_TP_CORE_POWER 0x54 + +#define S_SLEEPRDYVNT 12 +#define V_SLEEPRDYVNT(x) ((x) << S_SLEEPRDYVNT) +#define F_SLEEPRDYVNT V_SLEEPRDYVNT(1U) + +#define S_SLEEPRDYTBL 11 +#define V_SLEEPRDYTBL(x) ((x) << S_SLEEPRDYTBL) +#define F_SLEEPRDYTBL V_SLEEPRDYTBL(1U) + +#define S_SLEEPRDYMIB 10 +#define V_SLEEPRDYMIB(x) ((x) << S_SLEEPRDYMIB) +#define F_SLEEPRDYMIB V_SLEEPRDYMIB(1U) + +#define S_SLEEPRDYARP 9 +#define V_SLEEPRDYARP(x) ((x) << S_SLEEPRDYARP) +#define F_SLEEPRDYARP V_SLEEPRDYARP(1U) + +#define S_SLEEPRDYRSS 8 +#define V_SLEEPRDYRSS(x) ((x) << S_SLEEPRDYRSS) +#define F_SLEEPRDYRSS V_SLEEPRDYRSS(1U) + +#define S_SLEEPREQVNT 4 +#define V_SLEEPREQVNT(x) ((x) << S_SLEEPREQVNT) +#define F_SLEEPREQVNT V_SLEEPREQVNT(1U) + +#define S_SLEEPREQTBL 3 +#define V_SLEEPREQTBL(x) ((x) << S_SLEEPREQTBL) +#define F_SLEEPREQTBL V_SLEEPREQTBL(1U) + +#define S_SLEEPREQMIB 2 +#define V_SLEEPREQMIB(x) ((x) << S_SLEEPREQMIB) +#define F_SLEEPREQMIB V_SLEEPREQMIB(1U) + +#define S_SLEEPREQARP 1 +#define V_SLEEPREQARP(x) ((x) << S_SLEEPREQARP) +#define F_SLEEPREQARP V_SLEEPREQARP(1U) + +#define S_SLEEPREQRSS 0 +#define V_SLEEPREQRSS(x) ((x) << S_SLEEPREQRSS) +#define F_SLEEPREQRSS V_SLEEPREQRSS(1U) + +#define A_TP_CORE_RDMA 0x55 + +#define S_IMMEDIATEOP 20 +#define M_IMMEDIATEOP 0xfU +#define V_IMMEDIATEOP(x) ((x) << S_IMMEDIATEOP) +#define G_IMMEDIATEOP(x) (((x) >> S_IMMEDIATEOP) & M_IMMEDIATEOP) + +#define S_IMMEDIATESE 16 +#define M_IMMEDIATESE 0xfU +#define V_IMMEDIATESE(x) ((x) << S_IMMEDIATESE) +#define G_IMMEDIATESE(x) (((x) >> S_IMMEDIATESE) & M_IMMEDIATESE) + +#define S_ATOMICREQOP 12 +#define M_ATOMICREQOP 0xfU +#define V_ATOMICREQOP(x) ((x) << S_ATOMICREQOP) +#define G_ATOMICREQOP(x) (((x) >> S_ATOMICREQOP) & M_ATOMICREQOP) + +#define S_ATOMICRSPOP 8 +#define M_ATOMICRSPOP 0xfU +#define V_ATOMICRSPOP(x) ((x) << S_ATOMICRSPOP) +#define G_ATOMICRSPOP(x) (((x) >> S_ATOMICRSPOP) & M_ATOMICRSPOP) + +#define S_IMMEDIASEEN 1 +#define V_IMMEDIASEEN(x) ((x) << S_IMMEDIASEEN) +#define F_IMMEDIASEEN V_IMMEDIASEEN(1U) + +#define S_IMMEDIATEEN 0 +#define V_IMMEDIATEEN(x) ((x) << S_IMMEDIATEEN) +#define F_IMMEDIATEEN V_IMMEDIATEEN(1U) + #define A_TP_DBG_CLEAR 0x60 #define A_TP_DBG_CORE_HDR0 0x61 @@ -11344,16 +17516,16 @@ #define V_SRAMFATAL(x) ((x) << S_SRAMFATAL) #define F_SRAMFATAL V_SRAMFATAL(1U) -#define S_EPCMDCONG 24 -#define M_EPCMDCONG 0xfU +#define S_CPCMDCONG 24 +#define M_CPCMDCONG 0xfU +#define V_CPCMDCONG(x) ((x) << S_CPCMDCONG) +#define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG) + +#define S_EPCMDCONG 22 +#define M_EPCMDCONG 0x3U #define V_EPCMDCONG(x) ((x) << S_EPCMDCONG) #define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG) -#define S_CPCMDCONG 22 -#define M_CPCMDCONG 0x3U -#define V_CPCMDCONG(x) ((x) << S_CPCMDCONG) -#define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG) - #define S_CPCMDLENFATAL 21 #define V_CPCMDLENFATAL(x) ((x) << S_CPCMDLENFATAL) #define F_CPCMDLENFATAL V_CPCMDLENFATAL(1U) @@ -11400,6 +17572,14 @@ #define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT) #define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT) +#define S_CPCMDTTLFATAL 6 +#define V_CPCMDTTLFATAL(x) ((x) << S_CPCMDTTLFATAL) +#define F_CPCMDTTLFATAL V_CPCMDTTLFATAL(1U) + +#define S_CDATACHNFATAL 5 +#define V_CDATACHNFATAL(x) ((x) << S_CDATACHNFATAL) +#define F_CDATACHNFATAL V_CDATACHNFATAL(1U) + #define A_TP_DBG_CORE_OUT 0x64 #define S_CCPLENC 26 @@ -11490,6 +17670,46 @@ #define V_EPLDTXZEROPDRDY(x) ((x) << S_EPLDTXZEROPDRDY) #define F_EPLDTXZEROPDRDY V_EPLDTXZEROPDRDY(1U) +#define S_CRXBUSYOUT 31 +#define V_CRXBUSYOUT(x) ((x) << S_CRXBUSYOUT) +#define F_CRXBUSYOUT V_CRXBUSYOUT(1U) + +#define S_CTXBUSYOUT 30 +#define V_CTXBUSYOUT(x) ((x) << S_CTXBUSYOUT) +#define F_CTXBUSYOUT V_CTXBUSYOUT(1U) + +#define S_CRDCPLPKT 29 +#define V_CRDCPLPKT(x) ((x) << S_CRDCPLPKT) +#define F_CRDCPLPKT V_CRDCPLPKT(1U) + +#define S_CRDTCPPKT 28 +#define V_CRDTCPPKT(x) ((x) << S_CRDTCPPKT) +#define F_CRDTCPPKT V_CRDTCPPKT(1U) + +#define S_CNEWMSG 27 +#define V_CNEWMSG(x) ((x) << S_CNEWMSG) +#define F_CNEWMSG V_CNEWMSG(1U) + +#define S_ERXBUSYOUT 15 +#define V_ERXBUSYOUT(x) ((x) << S_ERXBUSYOUT) +#define F_ERXBUSYOUT V_ERXBUSYOUT(1U) + +#define S_ETXBUSYOUT 14 +#define V_ETXBUSYOUT(x) ((x) << S_ETXBUSYOUT) +#define F_ETXBUSYOUT V_ETXBUSYOUT(1U) + +#define S_ERDCPLPKT 13 +#define V_ERDCPLPKT(x) ((x) << S_ERDCPLPKT) +#define F_ERDCPLPKT V_ERDCPLPKT(1U) + +#define S_ERDTCPPKT 12 +#define V_ERDTCPPKT(x) ((x) << S_ERDTCPPKT) +#define F_ERDTCPPKT V_ERDTCPPKT(1U) + +#define S_ENEWMSG 11 +#define V_ENEWMSG(x) ((x) << S_ENEWMSG) +#define F_ENEWMSG V_ENEWMSG(1U) + #define A_TP_DBG_CORE_TID 0x65 #define S_LINENUMBER 24 @@ -11510,6 +17730,11 @@ #define V_TIDVALUE(x) ((x) << S_TIDVALUE) #define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE) +#define S_SRC 21 +#define M_SRC 0x3U +#define V_SRC(x) ((x) << S_SRC) +#define G_SRC(x) (((x) >> S_SRC) & M_SRC) + #define A_TP_DBG_ENG_RES0 0x66 #define S_RESOURCESREADY 31 @@ -11607,14 +17832,23 @@ #define V_CPCMDBUSY(x) ((x) << S_CPCMDBUSY) #define F_CPCMDBUSY V_CPCMDBUSY(1U) -#define S_ETXBUSY 1 +#define S_EPCMDBUSY 1 +#define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY) +#define F_EPCMDBUSY V_EPCMDBUSY(1U) + +#define S_ETXBUSY 0 #define V_ETXBUSY(x) ((x) << S_ETXBUSY) #define F_ETXBUSY V_ETXBUSY(1U) -#define S_EPCMDBUSY 0 -#define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY) -#define F_EPCMDBUSY V_EPCMDBUSY(1U) +#define S_EFFOPCODEOUT 16 +#define M_EFFOPCODEOUT 0xfU +#define V_EFFOPCODEOUT(x) ((x) << S_EFFOPCODEOUT) +#define G_EFFOPCODEOUT(x) (((x) >> S_EFFOPCODEOUT) & M_EFFOPCODEOUT) +#define S_DELDRDY 14 +#define V_DELDRDY(x) ((x) << S_DELDRDY) +#define F_DELDRDY V_DELDRDY(1U) + #define A_TP_DBG_ENG_RES1 0x67 #define S_RXCPLSRDY 31 @@ -11865,6 +18099,49 @@ #define V_RXMODXOFF(x) ((x) << S_RXMODXOFF) #define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF) +#define A_TP_DBG_ERROR_CNT 0x6c +#define A_TP_MIB_DEBUG 0x6f + +#define S_SRC3 31 +#define V_SRC3(x) ((x) << S_SRC3) +#define F_SRC3 V_SRC3(1U) + +#define S_LINENUM3 24 +#define M_LINENUM3 0x7fU +#define V_LINENUM3(x) ((x) << S_LINENUM3) +#define G_LINENUM3(x) (((x) >> S_LINENUM3) & M_LINENUM3) + +#define S_SRC2 23 +#define V_SRC2(x) ((x) << S_SRC2) +#define F_SRC2 V_SRC2(1U) + +#define S_LINENUM2 16 +#define M_LINENUM2 0x7fU +#define V_LINENUM2(x) ((x) << S_LINENUM2) +#define G_LINENUM2(x) (((x) >> S_LINENUM2) & M_LINENUM2) + +#define S_SRC1 15 +#define V_SRC1(x) ((x) << S_SRC1) +#define F_SRC1 V_SRC1(1U) + +#define S_LINENUM1 8 +#define M_LINENUM1 0x7fU +#define V_LINENUM1(x) ((x) << S_LINENUM1) +#define G_LINENUM1(x) (((x) >> S_LINENUM1) & M_LINENUM1) + +#define S_SRC0 7 +#define V_SRC0(x) ((x) << S_SRC0) +#define F_SRC0 V_SRC0(1U) + +#define S_LINENUM0 0 +#define M_LINENUM0 0x7fU +#define V_LINENUM0(x) ((x) << S_LINENUM0) +#define G_LINENUM0(x) (((x) >> S_LINENUM0) & M_LINENUM0) + +#define A_TP_T5_TX_DROP_CNT_CH0 0x120 +#define A_TP_T5_TX_DROP_CNT_CH1 0x121 +#define A_TP_TX_DROP_CNT_CH2 0x122 +#define A_TP_TX_DROP_CNT_CH3 0x123 #define A_TP_TX_DROP_CFG_CH0 0x12b #define S_TIMERENABLED 31 @@ -12447,6 +18724,18 @@ #define V_FCOE(x) ((x) << S_FCOE) #define F_FCOE V_FCOE(1U) +#define S_FILTERMODE 15 +#define V_FILTERMODE(x) ((x) << S_FILTERMODE) +#define F_FILTERMODE V_FILTERMODE(1U) + +#define S_FCOEMASK 14 +#define V_FCOEMASK(x) ((x) << S_FCOEMASK) +#define F_FCOEMASK V_FCOEMASK(1U) + +#define S_SRVRSRAM 13 +#define V_SRVRSRAM(x) ((x) << S_SRVRSRAM) +#define F_SRVRSRAM V_SRVRSRAM(1U) + #define A_TP_INGRESS_CONFIG 0x141 #define S_OPAQUE_TYPE 16 @@ -12492,6 +18781,10 @@ #define G_IPV6_EXT_HDR_SKIP(x) \ (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP) +#define S_FRAG_LEN_MOD8_COMPAT 12 +#define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT) +#define F_FRAG_LEN_MOD8_COMPAT V_FRAG_LEN_MOD8_COMPAT(1U) + #define A_TP_TX_DROP_CFG_CH2 0x142 #define A_TP_TX_DROP_CFG_CH3 0x143 #define A_TP_EGRESS_CONFIG 0x145 @@ -12500,6 +18793,34 @@ #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE) #define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U) +#define A_TP_INGRESS_CONFIG2 0x145 + +#define S_IPV6_UDP_CSUM_COMPAT 31 +#define V_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_IPV6_UDP_CSUM_COMPAT) +#define F_IPV6_UDP_CSUM_COMPAT V_IPV6_UDP_CSUM_COMPAT(1U) + +#define S_VNTAGPLDENABLE 30 +#define V_VNTAGPLDENABLE(x) ((x) << S_VNTAGPLDENABLE) +#define F_VNTAGPLDENABLE V_VNTAGPLDENABLE(1U) + +#define S_TCP_PLD_FILTER_OFFSET 20 +#define M_TCP_PLD_FILTER_OFFSET 0x3ffU +#define V_TCP_PLD_FILTER_OFFSET(x) ((x) << S_TCP_PLD_FILTER_OFFSET) +#define G_TCP_PLD_FILTER_OFFSET(x) \ + (((x) >> S_TCP_PLD_FILTER_OFFSET) & M_TCP_PLD_FILTER_OFFSET) + +#define S_UDP_PLD_FILTER_OFFSET 10 +#define M_UDP_PLD_FILTER_OFFSET 0x3ffU +#define V_UDP_PLD_FILTER_OFFSET(x) ((x) << S_UDP_PLD_FILTER_OFFSET) +#define G_UDP_PLD_FILTER_OFFSET(x) \ + (((x) >> S_UDP_PLD_FILTER_OFFSET) & M_UDP_PLD_FILTER_OFFSET) + +#define S_TNL_PLD_FILTER_OFFSET 0 +#define M_TNL_PLD_FILTER_OFFSET 0x3ffU +#define V_TNL_PLD_FILTER_OFFSET(x) ((x) << S_TNL_PLD_FILTER_OFFSET) +#define G_TNL_PLD_FILTER_OFFSET(x) \ + (((x) >> S_TNL_PLD_FILTER_OFFSET) & M_TNL_PLD_FILTER_OFFSET) + #define A_TP_EHDR_CONFIG_LO 0x146 #define S_CPLLIMIT 24 @@ -12760,6 +19081,237 @@ #define V_RX_PKT_ATTR_DRDY(x) ((x) << S_RX_PKT_ATTR_DRDY) #define F_RX_PKT_ATTR_DRDY V_RX_PKT_ATTR_DRDY(1U) +#define S_RXRUNT 25 +#define V_RXRUNT(x) ((x) << S_RXRUNT) +#define F_RXRUNT V_RXRUNT(1U) + +#define S_RXRUNTPARSER 24 +#define V_RXRUNTPARSER(x) ((x) << S_RXRUNTPARSER) +#define F_RXRUNTPARSER V_RXRUNTPARSER(1U) + +#define S_ERROR_SRDY 5 +#define V_ERROR_SRDY(x) ((x) << S_ERROR_SRDY) +#define F_ERROR_SRDY V_ERROR_SRDY(1U) + +#define S_ERROR_DRDY 4 +#define V_ERROR_DRDY(x) ((x) << S_ERROR_DRDY) +#define F_ERROR_DRDY V_ERROR_DRDY(1U) + +#define A_TP_DBG_ESIDE_OP 0x154 + +#define S_OPT_PARSER_FATAL_CHANNEL0 29 +#define V_OPT_PARSER_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL0) +#define F_OPT_PARSER_FATAL_CHANNEL0 V_OPT_PARSER_FATAL_CHANNEL0(1U) + +#define S_OPT_PARSER_BUSY_CHANNEL0 28 +#define V_OPT_PARSER_BUSY_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL0) +#define F_OPT_PARSER_BUSY_CHANNEL0 V_OPT_PARSER_BUSY_CHANNEL0(1U) + +#define S_OPT_PARSER_ITCP_STATE_CHANNEL0 26 +#define M_OPT_PARSER_ITCP_STATE_CHANNEL0 0x3U +#define V_OPT_PARSER_ITCP_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL0) +#define G_OPT_PARSER_ITCP_STATE_CHANNEL0(x) \ + (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL0) & \ + M_OPT_PARSER_ITCP_STATE_CHANNEL0) + +#define S_OPT_PARSER_OTK_STATE_CHANNEL0 24 +#define M_OPT_PARSER_OTK_STATE_CHANNEL0 0x3U +#define V_OPT_PARSER_OTK_STATE_CHANNEL0(x) \ + ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL0) +#define G_OPT_PARSER_OTK_STATE_CHANNEL0(x) \ + (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL0) & \ + M_OPT_PARSER_OTK_STATE_CHANNEL0) + +#define S_OPT_PARSER_FATAL_CHANNEL1 21 +#define V_OPT_PARSER_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL1) +#define F_OPT_PARSER_FATAL_CHANNEL1 V_OPT_PARSER_FATAL_CHANNEL1(1U) + +#define S_OPT_PARSER_BUSY_CHANNEL1 20 +#define V_OPT_PARSER_BUSY_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL1) +#define F_OPT_PARSER_BUSY_CHANNEL1 V_OPT_PARSER_BUSY_CHANNEL1(1U) + +#define S_OPT_PARSER_ITCP_STATE_CHANNEL1 18 +#define M_OPT_PARSER_ITCP_STATE_CHANNEL1 0x3U +#define V_OPT_PARSER_ITCP_STATE_CHANNEL1(x) \ + ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL1) +#define G_OPT_PARSER_ITCP_STATE_CHANNEL1(x) \ + (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL1) & \ + M_OPT_PARSER_ITCP_STATE_CHANNEL1) + +#define S_OPT_PARSER_OTK_STATE_CHANNEL1 16 +#define M_OPT_PARSER_OTK_STATE_CHANNEL1 0x3U +#define V_OPT_PARSER_OTK_STATE_CHANNEL1(x) \ + ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL1) +#define G_OPT_PARSER_OTK_STATE_CHANNEL1(x) \ + (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL1) & \ + M_OPT_PARSER_OTK_STATE_CHANNEL1) + +#define S_OPT_PARSER_FATAL_CHANNEL2 13 +#define V_OPT_PARSER_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL2) +#define F_OPT_PARSER_FATAL_CHANNEL2 V_OPT_PARSER_FATAL_CHANNEL2(1U) + +#define S_OPT_PARSER_BUSY_CHANNEL2 12 +#define V_OPT_PARSER_BUSY_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL2) +#define F_OPT_PARSER_BUSY_CHANNEL2 V_OPT_PARSER_BUSY_CHANNEL2(1U) + +#define S_OPT_PARSER_ITCP_STATE_CHANNEL2 10 +#define M_OPT_PARSER_ITCP_STATE_CHANNEL2 0x3U +#define V_OPT_PARSER_ITCP_STATE_CHANNEL2(x) \ + ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL2) +#define G_OPT_PARSER_ITCP_STATE_CHANNEL2(x) \ + (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL2) & \ + M_OPT_PARSER_ITCP_STATE_CHANNEL2) + +#define S_OPT_PARSER_OTK_STATE_CHANNEL2 8 +#define M_OPT_PARSER_OTK_STATE_CHANNEL2 0x3U +#define V_OPT_PARSER_OTK_STATE_CHANNEL2(x) \ + ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL2) +#define G_OPT_PARSER_OTK_STATE_CHANNEL2(x) \ + (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL2) & \ + M_OPT_PARSER_OTK_STATE_CHANNEL2) + +#define S_OPT_PARSER_FATAL_CHANNEL3 5 +#define V_OPT_PARSER_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL3) +#define F_OPT_PARSER_FATAL_CHANNEL3 V_OPT_PARSER_FATAL_CHANNEL3(1U) + +#define S_OPT_PARSER_BUSY_CHANNEL3 4 +#define V_OPT_PARSER_BUSY_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL3) +#define F_OPT_PARSER_BUSY_CHANNEL3 V_OPT_PARSER_BUSY_CHANNEL3(1U) + +#define S_OPT_PARSER_ITCP_STATE_CHANNEL3 2 +#define M_OPT_PARSER_ITCP_STATE_CHANNEL3 0x3U +#define V_OPT_PARSER_ITCP_STATE_CHANNEL3(x) \ + ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL3) +#define G_OPT_PARSER_ITCP_STATE_CHANNEL3(x) \ + (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL3) & \ + M_OPT_PARSER_ITCP_STATE_CHANNEL3) + +#define S_OPT_PARSER_OTK_STATE_CHANNEL3 0 +#define M_OPT_PARSER_OTK_STATE_CHANNEL3 0x3U +#define V_OPT_PARSER_OTK_STATE_CHANNEL3(x) \ + ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL3) +#define G_OPT_PARSER_OTK_STATE_CHANNEL3(x) \ + (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL3) & \ + M_OPT_PARSER_OTK_STATE_CHANNEL3) + +#define A_TP_DBG_ESIDE_OP_ALT 0x155 + +#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL0 29 +#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(x) \ + ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL0) +#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL0 \ + V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(1U) + +#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0 24 +#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0 0x1fU +#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) \ + ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) +#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) \ + (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) & \ + M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) + +#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL1 21 +#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(x) \ + ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL1) +#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL1 \ + V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(1U) + +#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1 16 +#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1 0x1fU +#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) \ + ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) +#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) \ + (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) & \ + M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) + +#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL2 13 +#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(x) \ + ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL2) +#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL2 \ + V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(1U) + +#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2 8 +#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2 0x1fU +#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) \ + ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) +#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) \ + (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) & \ + M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) + +#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL3 5 +#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(x) \ + ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL3) +#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL3 \ + V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(1U) + +#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3 0 +#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3 0x1fU +#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) \ + ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) +#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) \ + (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) & \ + M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) + +#define A_TP_DBG_ESIDE_OP_BUSY 0x156 + +#define S_OPT_PARSER_BUSY_VEC_CHANNEL3 24 +#define M_OPT_PARSER_BUSY_VEC_CHANNEL3 0xffU +#define V_OPT_PARSER_BUSY_VEC_CHANNEL3(x) \ + ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL3) +#define G_OPT_PARSER_BUSY_VEC_CHANNEL3(x) \ + (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL3) & \ + M_OPT_PARSER_BUSY_VEC_CHANNEL3) + +#define S_OPT_PARSER_BUSY_VEC_CHANNEL2 16 +#define M_OPT_PARSER_BUSY_VEC_CHANNEL2 0xffU +#define V_OPT_PARSER_BUSY_VEC_CHANNEL2(x) \ + ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL2) +#define G_OPT_PARSER_BUSY_VEC_CHANNEL2(x) \ + (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL2) & \ + M_OPT_PARSER_BUSY_VEC_CHANNEL2) + +#define S_OPT_PARSER_BUSY_VEC_CHANNEL1 8 +#define M_OPT_PARSER_BUSY_VEC_CHANNEL1 0xffU +#define V_OPT_PARSER_BUSY_VEC_CHANNEL1(x) \ + ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL1) +#define G_OPT_PARSER_BUSY_VEC_CHANNEL1(x) \ + (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL1) & \ + M_OPT_PARSER_BUSY_VEC_CHANNEL1) + +#define S_OPT_PARSER_BUSY_VEC_CHANNEL0 0 +#define M_OPT_PARSER_BUSY_VEC_CHANNEL0 0xffU +#define V_OPT_PARSER_BUSY_VEC_CHANNEL0(x) \ + ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL0) +#define G_OPT_PARSER_BUSY_VEC_CHANNEL0(x) \ + (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL0) & \ + M_OPT_PARSER_BUSY_VEC_CHANNEL0) + +#define A_TP_DBG_ESIDE_OP_COOKIE 0x157 + +#define S_OPT_PARSER_COOKIE_CHANNEL3 24 +#define M_OPT_PARSER_COOKIE_CHANNEL3 0xffU +#define V_OPT_PARSER_COOKIE_CHANNEL3(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL3) +#define G_OPT_PARSER_COOKIE_CHANNEL3(x) \ + (((x) >> S_OPT_PARSER_COOKIE_CHANNEL3) & M_OPT_PARSER_COOKIE_CHANNEL3) + +#define S_OPT_PARSER_COOKIE_CHANNEL2 16 +#define M_OPT_PARSER_COOKIE_CHANNEL2 0xffU +#define V_OPT_PARSER_COOKIE_CHANNEL2(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL2) +#define G_OPT_PARSER_COOKIE_CHANNEL2(x) \ + (((x) >> S_OPT_PARSER_COOKIE_CHANNEL2) & M_OPT_PARSER_COOKIE_CHANNEL2) + +#define S_OPT_PARSER_COOKIE_CHANNEL1 8 +#define M_OPT_PARSER_COOKIE_CHANNEL1 0xffU +#define V_OPT_PARSER_COOKIE_CHANNEL1(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL1) +#define G_OPT_PARSER_COOKIE_CHANNEL1(x) \ + (((x) >> S_OPT_PARSER_COOKIE_CHANNEL1) & M_OPT_PARSER_COOKIE_CHANNEL1) + +#define S_OPT_PARSER_COOKIE_CHANNEL0 0 +#define M_OPT_PARSER_COOKIE_CHANNEL0 0xffU +#define V_OPT_PARSER_COOKIE_CHANNEL0(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL0) +#define G_OPT_PARSER_COOKIE_CHANNEL0(x) \ + (((x) >> S_OPT_PARSER_COOKIE_CHANNEL0) & M_OPT_PARSER_COOKIE_CHANNEL0) + #define A_TP_DBG_ESIDE_IN1 0x14b #define A_TP_DBG_ESIDE_IN2 0x14c #define A_TP_DBG_ESIDE_IN3 0x14d @@ -13274,6 +19826,50 @@ #define V_CMD_SEL(x) ((x) << S_CMD_SEL) #define F_CMD_SEL V_CMD_SEL(1U) +#define S_CPL5RXFULL 26 +#define V_CPL5RXFULL(x) ((x) << S_CPL5RXFULL) +#define F_CPL5RXFULL V_CPL5RXFULL(1U) + +#define S_PLD2XRXVALID 23 +#define V_PLD2XRXVALID(x) ((x) << S_PLD2XRXVALID) +#define F_PLD2XRXVALID V_PLD2XRXVALID(1U) + +#define S_DDPSTATE 16 +#define M_DDPSTATE 0x1fU +#define V_DDPSTATE(x) ((x) << S_DDPSTATE) +#define G_DDPSTATE(x) (((x) >> S_DDPSTATE) & M_DDPSTATE) + +#define S_DDPMSGCODE 12 +#define M_DDPMSGCODE 0xfU +#define V_DDPMSGCODE(x) ((x) << S_DDPMSGCODE) +#define G_DDPMSGCODE(x) (((x) >> S_DDPMSGCODE) & M_DDPMSGCODE) + +#define S_CPL5SOCPCNT 8 +#define M_CPL5SOCPCNT 0xfU +#define V_CPL5SOCPCNT(x) ((x) << S_CPL5SOCPCNT) +#define G_CPL5SOCPCNT(x) (((x) >> S_CPL5SOCPCNT) & M_CPL5SOCPCNT) + +#define S_PLDRXZEROPCNT 4 +#define M_PLDRXZEROPCNT 0xfU +#define V_PLDRXZEROPCNT(x) ((x) << S_PLDRXZEROPCNT) +#define G_PLDRXZEROPCNT(x) (((x) >> S_PLDRXZEROPCNT) & M_PLDRXZEROPCNT) + +#define S_TXFRMERR2 3 +#define V_TXFRMERR2(x) ((x) << S_TXFRMERR2) +#define F_TXFRMERR2 V_TXFRMERR2(1U) + +#define S_TXFRMERR1 2 +#define V_TXFRMERR1(x) ((x) << S_TXFRMERR1) +#define F_TXFRMERR1 V_TXFRMERR1(1U) + +#define S_TXVALID2X 1 +#define V_TXVALID2X(x) ((x) << S_TXVALID2X) +#define F_TXVALID2X V_TXVALID2X(1U) + +#define S_TXFULL2X 0 +#define V_TXFULL2X(x) ((x) << S_TXFULL2X) +#define F_TXFULL2X V_TXFULL2X(1U) + #define A_TP_DBG_CSIDE_DISP1 0x23b #define A_TP_DBG_CSIDE_DDP0 0x23c @@ -13473,6 +20069,48 @@ #define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP) #define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP) +#define S_STARTSKIPPLD 7 +#define V_STARTSKIPPLD(x) ((x) << S_STARTSKIPPLD) +#define F_STARTSKIPPLD V_STARTSKIPPLD(1U) + +#define S_ATOMICCMDEN 5 +#define V_ATOMICCMDEN(x) ((x) << S_ATOMICCMDEN) +#define F_ATOMICCMDEN V_ATOMICCMDEN(1U) + +#define A_TP_CSPI_POWER 0x243 + +#define S_GATECHNTX3 11 +#define V_GATECHNTX3(x) ((x) << S_GATECHNTX3) +#define F_GATECHNTX3 V_GATECHNTX3(1U) + +#define S_GATECHNTX2 10 +#define V_GATECHNTX2(x) ((x) << S_GATECHNTX2) +#define F_GATECHNTX2 V_GATECHNTX2(1U) + +#define S_GATECHNTX1 9 +#define V_GATECHNTX1(x) ((x) << S_GATECHNTX1) +#define F_GATECHNTX1 V_GATECHNTX1(1U) + +#define S_GATECHNTX0 8 +#define V_GATECHNTX0(x) ((x) << S_GATECHNTX0) +#define F_GATECHNTX0 V_GATECHNTX0(1U) + +#define S_GATECHNRX1 7 +#define V_GATECHNRX1(x) ((x) << S_GATECHNRX1) +#define F_GATECHNRX1 V_GATECHNRX1(1U) + +#define S_GATECHNRX0 6 +#define V_GATECHNRX0(x) ((x) << S_GATECHNRX0) +#define F_GATECHNRX0 V_GATECHNRX0(1U) + +#define S_SLEEPRDYUTRN 4 +#define V_SLEEPRDYUTRN(x) ((x) << S_SLEEPRDYUTRN) +#define F_SLEEPRDYUTRN V_SLEEPRDYUTRN(1U) + +#define S_SLEEPREQUTRN 0 +#define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN) +#define F_SLEEPREQUTRN V_SLEEPREQUTRN(1U) + #define A_TP_TRC_CONFIG 0x244 #define S_TRCRR 1 @@ -13512,6 +20150,70 @@ #define V_CPRSSTATE0(x) ((x) << S_CPRSSTATE0) #define G_CPRSSTATE0(x) (((x) >> S_CPRSSTATE0) & M_CPRSSTATE0) +#define S_C4TUPBUSY3 31 +#define V_C4TUPBUSY3(x) ((x) << S_C4TUPBUSY3) +#define F_C4TUPBUSY3 V_C4TUPBUSY3(1U) + +#define S_CDBVALID3 30 +#define V_CDBVALID3(x) ((x) << S_CDBVALID3) +#define F_CDBVALID3 V_CDBVALID3(1U) + +#define S_CRXVALID3 29 +#define V_CRXVALID3(x) ((x) << S_CRXVALID3) +#define F_CRXVALID3 V_CRXVALID3(1U) + +#define S_CRXFULL3 28 +#define V_CRXFULL3(x) ((x) << S_CRXFULL3) +#define F_CRXFULL3 V_CRXFULL3(1U) + +#define S_C4TUPBUSY2 23 +#define V_C4TUPBUSY2(x) ((x) << S_C4TUPBUSY2) +#define F_C4TUPBUSY2 V_C4TUPBUSY2(1U) + +#define S_CDBVALID2 22 +#define V_CDBVALID2(x) ((x) << S_CDBVALID2) +#define F_CDBVALID2 V_CDBVALID2(1U) + +#define S_CRXVALID2 21 +#define V_CRXVALID2(x) ((x) << S_CRXVALID2) +#define F_CRXVALID2 V_CRXVALID2(1U) + +#define S_CRXFULL2 20 +#define V_CRXFULL2(x) ((x) << S_CRXFULL2) +#define F_CRXFULL2 V_CRXFULL2(1U) + +#define S_C4TUPBUSY1 15 +#define V_C4TUPBUSY1(x) ((x) << S_C4TUPBUSY1) +#define F_C4TUPBUSY1 V_C4TUPBUSY1(1U) + +#define S_CDBVALID1 14 +#define V_CDBVALID1(x) ((x) << S_CDBVALID1) +#define F_CDBVALID1 V_CDBVALID1(1U) + +#define S_CRXVALID1 13 +#define V_CRXVALID1(x) ((x) << S_CRXVALID1) +#define F_CRXVALID1 V_CRXVALID1(1U) + +#define S_CRXFULL1 12 +#define V_CRXFULL1(x) ((x) << S_CRXFULL1) +#define F_CRXFULL1 V_CRXFULL1(1U) + +#define S_C4TUPBUSY0 7 +#define V_C4TUPBUSY0(x) ((x) << S_C4TUPBUSY0) +#define F_C4TUPBUSY0 V_C4TUPBUSY0(1U) + +#define S_CDBVALID0 6 +#define V_CDBVALID0(x) ((x) << S_CDBVALID0) +#define F_CDBVALID0 V_CDBVALID0(1U) + +#define S_CRXVALID0 5 +#define V_CRXVALID0(x) ((x) << S_CRXVALID0) +#define F_CRXVALID0 V_CRXVALID0(1U) + +#define S_CRXFULL0 4 +#define V_CRXFULL0(x) ((x) << S_CRXFULL0) +#define F_CRXFULL0 V_CRXFULL0(1U) + #define A_TP_DBG_CSIDE_DEMUX 0x247 #define S_CALLDONE 28 @@ -13554,6 +20256,151 @@ #define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE) #define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE) +#define S_CARBVALID 28 +#define M_CARBVALID 0xfU +#define V_CARBVALID(x) ((x) << S_CARBVALID) +#define G_CARBVALID(x) (((x) >> S_CARBVALID) & M_CARBVALID) + +#define S_CCPL5DONE 24 +#define M_CCPL5DONE 0xfU +#define V_CCPL5DONE(x) ((x) << S_CCPL5DONE) +#define G_CCPL5DONE(x) (((x) >> S_CCPL5DONE) & M_CCPL5DONE) + +#define S_CTCPOPDONE 12 +#define M_CTCPOPDONE 0xfU +#define V_CTCPOPDONE(x) ((x) << S_CTCPOPDONE) +#define G_CTCPOPDONE(x) (((x) >> S_CTCPOPDONE) & M_CTCPOPDONE) + +#define A_TP_DBG_CSIDE_ARBIT 0x248 + +#define S_CPLVALID3 31 +#define V_CPLVALID3(x) ((x) << S_CPLVALID3) +#define F_CPLVALID3 V_CPLVALID3(1U) + +#define S_PLDVALID3 30 +#define V_PLDVALID3(x) ((x) << S_PLDVALID3) +#define F_PLDVALID3 V_PLDVALID3(1U) + +#define S_CRCVALID3 29 +#define V_CRCVALID3(x) ((x) << S_CRCVALID3) +#define F_CRCVALID3 V_CRCVALID3(1U) + +#define S_ISSVALID3 28 +#define V_ISSVALID3(x) ((x) << S_ISSVALID3) +#define F_ISSVALID3 V_ISSVALID3(1U) + +#define S_DBVALID3 27 +#define V_DBVALID3(x) ((x) << S_DBVALID3) +#define F_DBVALID3 V_DBVALID3(1U) + +#define S_CHKVALID3 26 +#define V_CHKVALID3(x) ((x) << S_CHKVALID3) +#define F_CHKVALID3 V_CHKVALID3(1U) + +#define S_ZRPVALID3 25 +#define V_ZRPVALID3(x) ((x) << S_ZRPVALID3) +#define F_ZRPVALID3 V_ZRPVALID3(1U) + +#define S_ERRVALID3 24 +#define V_ERRVALID3(x) ((x) << S_ERRVALID3) +#define F_ERRVALID3 V_ERRVALID3(1U) + +#define S_CPLVALID2 23 +#define V_CPLVALID2(x) ((x) << S_CPLVALID2) +#define F_CPLVALID2 V_CPLVALID2(1U) + +#define S_PLDVALID2 22 +#define V_PLDVALID2(x) ((x) << S_PLDVALID2) +#define F_PLDVALID2 V_PLDVALID2(1U) + +#define S_CRCVALID2 21 +#define V_CRCVALID2(x) ((x) << S_CRCVALID2) +#define F_CRCVALID2 V_CRCVALID2(1U) + +#define S_ISSVALID2 20 +#define V_ISSVALID2(x) ((x) << S_ISSVALID2) +#define F_ISSVALID2 V_ISSVALID2(1U) + +#define S_DBVALID2 19 +#define V_DBVALID2(x) ((x) << S_DBVALID2) +#define F_DBVALID2 V_DBVALID2(1U) + +#define S_CHKVALID2 18 +#define V_CHKVALID2(x) ((x) << S_CHKVALID2) +#define F_CHKVALID2 V_CHKVALID2(1U) + +#define S_ZRPVALID2 17 +#define V_ZRPVALID2(x) ((x) << S_ZRPVALID2) +#define F_ZRPVALID2 V_ZRPVALID2(1U) + +#define S_ERRVALID2 16 +#define V_ERRVALID2(x) ((x) << S_ERRVALID2) +#define F_ERRVALID2 V_ERRVALID2(1U) + +#define S_CPLVALID1 15 +#define V_CPLVALID1(x) ((x) << S_CPLVALID1) +#define F_CPLVALID1 V_CPLVALID1(1U) + +#define S_PLDVALID1 14 +#define V_PLDVALID1(x) ((x) << S_PLDVALID1) +#define F_PLDVALID1 V_PLDVALID1(1U) + +#define S_CRCVALID1 13 +#define V_CRCVALID1(x) ((x) << S_CRCVALID1) +#define F_CRCVALID1 V_CRCVALID1(1U) + +#define S_ISSVALID1 12 +#define V_ISSVALID1(x) ((x) << S_ISSVALID1) +#define F_ISSVALID1 V_ISSVALID1(1U) + +#define S_DBVALID1 11 +#define V_DBVALID1(x) ((x) << S_DBVALID1) +#define F_DBVALID1 V_DBVALID1(1U) + +#define S_CHKVALID1 10 +#define V_CHKVALID1(x) ((x) << S_CHKVALID1) +#define F_CHKVALID1 V_CHKVALID1(1U) + +#define S_ZRPVALID1 9 +#define V_ZRPVALID1(x) ((x) << S_ZRPVALID1) +#define F_ZRPVALID1 V_ZRPVALID1(1U) + +#define S_ERRVALID1 8 +#define V_ERRVALID1(x) ((x) << S_ERRVALID1) +#define F_ERRVALID1 V_ERRVALID1(1U) + +#define S_CPLVALID0 7 +#define V_CPLVALID0(x) ((x) << S_CPLVALID0) +#define F_CPLVALID0 V_CPLVALID0(1U) + +#define S_PLDVALID0 6 +#define V_PLDVALID0(x) ((x) << S_PLDVALID0) +#define F_PLDVALID0 V_PLDVALID0(1U) + +#define S_CRCVALID0 5 +#define V_CRCVALID0(x) ((x) << S_CRCVALID0) +#define F_CRCVALID0 V_CRCVALID0(1U) + +#define S_ISSVALID0 4 +#define V_ISSVALID0(x) ((x) << S_ISSVALID0) +#define F_ISSVALID0 V_ISSVALID0(1U) + +#define S_DBVALID0 3 +#define V_DBVALID0(x) ((x) << S_DBVALID0) +#define F_DBVALID0 V_DBVALID0(1U) + +#define S_CHKVALID0 2 +#define V_CHKVALID0(x) ((x) << S_CHKVALID0) +#define F_CHKVALID0 V_CHKVALID0(1U) + +#define S_ZRPVALID0 1 +#define V_ZRPVALID0(x) ((x) << S_ZRPVALID0) +#define F_ZRPVALID0 V_ZRPVALID0(1U) + +#define S_ERRVALID0 0 +#define V_ERRVALID0(x) ((x) << S_ERRVALID0) +#define F_ERRVALID0 V_ERRVALID0(1U) + #define A_TP_FIFO_CONFIG 0x8c0 #define S_CH1_OUTPUT 27 @@ -13681,13 +20528,17 @@ #define A_TP_MIB_TID_INV 0x61 #define A_TP_MIB_TID_ACT 0x62 #define A_TP_MIB_TID_PAS 0x63 -#define A_TP_MIB_RQE_DFR_MOD 0x64 -#define A_TP_MIB_RQE_DFR_PKT 0x65 +#define A_TP_MIB_RQE_DFR_PKT 0x64 +#define A_TP_MIB_RQE_DFR_MOD 0x65 #define A_TP_MIB_CPL_OUT_ERR_0 0x68 #define A_TP_MIB_CPL_OUT_ERR_1 0x69 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a #define A_TP_MIB_CPL_OUT_ERR_3 0x6b - +#define A_TP_MIB_ENG_LINE_0 0x6c +#define A_TP_MIB_ENG_LINE_1 0x6d +#define A_TP_MIB_ENG_LINE_2 0x6e +#define A_TP_MIB_ENG_LINE_3 0x6f + /* registers for module ULP_TX */ #define ULP_TX_BASE_ADDR 0x8dc0 @@ -13705,6 +20556,30 @@ #define V_EXTRA_TAG_INSERTION_ENABLE(x) ((x) << S_EXTRA_TAG_INSERTION_ENABLE) #define F_EXTRA_TAG_INSERTION_ENABLE V_EXTRA_TAG_INSERTION_ENABLE(1U) +#define S_PHYS_ADDR_RESP_EN 6 +#define V_PHYS_ADDR_RESP_EN(x) ((x) << S_PHYS_ADDR_RESP_EN) +#define F_PHYS_ADDR_RESP_EN V_PHYS_ADDR_RESP_EN(1U) + +#define S_ENDIANESS_CHANGE 5 +#define V_ENDIANESS_CHANGE(x) ((x) << S_ENDIANESS_CHANGE) +#define F_ENDIANESS_CHANGE V_ENDIANESS_CHANGE(1U) + +#define S_ERR_RTAG_EN 4 +#define V_ERR_RTAG_EN(x) ((x) << S_ERR_RTAG_EN) +#define F_ERR_RTAG_EN V_ERR_RTAG_EN(1U) + +#define S_TSO_ETHLEN_EN 3 +#define V_TSO_ETHLEN_EN(x) ((x) << S_TSO_ETHLEN_EN) +#define F_TSO_ETHLEN_EN V_TSO_ETHLEN_EN(1U) + +#define S_EMSG_MORE_INFO 2 +#define V_EMSG_MORE_INFO(x) ((x) << S_EMSG_MORE_INFO) +#define F_EMSG_MORE_INFO V_EMSG_MORE_INFO(1U) + +#define S_LOSDR 1 +#define V_LOSDR(x) ((x) << S_LOSDR) +#define F_LOSDR V_LOSDR(1U) + #define A_ULP_TX_PERR_INJECT 0x8dc4 #define A_ULP_TX_INT_ENABLE 0x8dc8 @@ -13921,25 +20796,196 @@ #define V_ERR_CNT3(x) ((x) << S_ERR_CNT3) #define G_ERR_CNT3(x) (((x) >> S_ERR_CNT3) & M_ERR_CNT3) +#define A_ULP_TX_FC_SOF 0x8e20 + +#define S_SOF_FS3 24 +#define M_SOF_FS3 0xffU +#define V_SOF_FS3(x) ((x) << S_SOF_FS3) +#define G_SOF_FS3(x) (((x) >> S_SOF_FS3) & M_SOF_FS3) + +#define S_SOF_FS2 16 +#define M_SOF_FS2 0xffU +#define V_SOF_FS2(x) ((x) << S_SOF_FS2) +#define G_SOF_FS2(x) (((x) >> S_SOF_FS2) & M_SOF_FS2) + +#define S_SOF_3 8 +#define M_SOF_3 0xffU +#define V_SOF_3(x) ((x) << S_SOF_3) +#define G_SOF_3(x) (((x) >> S_SOF_3) & M_SOF_3) + +#define S_SOF_2 0 +#define M_SOF_2 0xffU +#define V_SOF_2(x) ((x) << S_SOF_2) +#define G_SOF_2(x) (((x) >> S_SOF_2) & M_SOF_2) + +#define A_ULP_TX_FC_EOF 0x8e24 + +#define S_EOF_LS3 24 +#define M_EOF_LS3 0xffU +#define V_EOF_LS3(x) ((x) << S_EOF_LS3) +#define G_EOF_LS3(x) (((x) >> S_EOF_LS3) & M_EOF_LS3) + +#define S_EOF_LS2 16 +#define M_EOF_LS2 0xffU +#define V_EOF_LS2(x) ((x) << S_EOF_LS2) +#define G_EOF_LS2(x) (((x) >> S_EOF_LS2) & M_EOF_LS2) + +#define S_EOF_3 8 +#define M_EOF_3 0xffU +#define V_EOF_3(x) ((x) << S_EOF_3) +#define G_EOF_3(x) (((x) >> S_EOF_3) & M_EOF_3) + +#define S_EOF_2 0 +#define M_EOF_2 0xffU +#define V_EOF_2(x) ((x) << S_EOF_2) +#define G_EOF_2(x) (((x) >> S_EOF_2) & M_EOF_2) + +#define A_ULP_TX_CGEN_GLOBAL 0x8e28 + +#define S_ULP_TX_GLOBAL_CGEN 0 +#define V_ULP_TX_GLOBAL_CGEN(x) ((x) << S_ULP_TX_GLOBAL_CGEN) +#define F_ULP_TX_GLOBAL_CGEN V_ULP_TX_GLOBAL_CGEN(1U) + +#define A_ULP_TX_CGEN 0x8e2c + +#define S_ULP_TX_CGEN_STORAGE 8 +#define M_ULP_TX_CGEN_STORAGE 0xfU +#define V_ULP_TX_CGEN_STORAGE(x) ((x) << S_ULP_TX_CGEN_STORAGE) +#define G_ULP_TX_CGEN_STORAGE(x) \ + (((x) >> S_ULP_TX_CGEN_STORAGE) & M_ULP_TX_CGEN_STORAGE) + +#define S_ULP_TX_CGEN_RDMA 4 +#define M_ULP_TX_CGEN_RDMA 0xfU +#define V_ULP_TX_CGEN_RDMA(x) ((x) << S_ULP_TX_CGEN_RDMA) +#define G_ULP_TX_CGEN_RDMA(x) (((x) >> S_ULP_TX_CGEN_RDMA) & M_ULP_TX_CGEN_RDMA) + +#define S_ULP_TX_CGEN_CHANNEL 0 +#define M_ULP_TX_CGEN_CHANNEL 0xfU +#define V_ULP_TX_CGEN_CHANNEL(x) ((x) << S_ULP_TX_CGEN_CHANNEL) +#define G_ULP_TX_CGEN_CHANNEL(x) \ + (((x) >> S_ULP_TX_CGEN_CHANNEL) & M_ULP_TX_CGEN_CHANNEL) + #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30 +#define A_ULP_TX_MEM_CFG 0x8e30 + +#define S_WRREQ_SZ 0 +#define M_WRREQ_SZ 0x7U +#define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ) +#define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ) + #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34 +#define A_ULP_TX_PERR_INJECT_2 0x8e34 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38 +#define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38 +#define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38 + +#define S_CHANNEL_SEL 12 +#define M_CHANNEL_SEL 0x3U +#define V_CHANNEL_SEL(x) ((x) << S_CHANNEL_SEL) +#define G_CHANNEL_SEL(x) (((x) >> S_CHANNEL_SEL) & M_CHANNEL_SEL) + +#define S_INTF_SEL 4 +#define M_INTF_SEL 0xfU +#define V_INTF_SEL(x) ((x) << S_INTF_SEL) +#define G_INTF_SEL(x) (((x) >> S_INTF_SEL) & M_INTF_SEL) + +#define S_NUM_FLITS 1 +#define M_NUM_FLITS 0x7U +#define V_NUM_FLITS(x) ((x) << S_NUM_FLITS) +#define G_NUM_FLITS(x) (((x) >> S_NUM_FLITS) & M_NUM_FLITS) + +#define S_CMD_GEN_EN 0 +#define V_CMD_GEN_EN(x) ((x) << S_CMD_GEN_EN) +#define F_CMD_GEN_EN V_CMD_GEN_EN(1U) + #define A_ULP_TX_FPGA_CMD_0 0x8e3c +#define A_ULP_TX_T5_FPGA_CMD_0 0x8e3c #define A_ULP_TX_FPGA_CMD_1 0x8e40 +#define A_ULP_TX_T5_FPGA_CMD_1 0x8e40 #define A_ULP_TX_FPGA_CMD_2 0x8e44 +#define A_ULP_TX_T5_FPGA_CMD_2 0x8e44 #define A_ULP_TX_FPGA_CMD_3 0x8e48 +#define A_ULP_TX_T5_FPGA_CMD_3 0x8e48 #define A_ULP_TX_FPGA_CMD_4 0x8e4c +#define A_ULP_TX_T5_FPGA_CMD_4 0x8e4c #define A_ULP_TX_FPGA_CMD_5 0x8e50 +#define A_ULP_TX_T5_FPGA_CMD_5 0x8e50 #define A_ULP_TX_FPGA_CMD_6 0x8e54 +#define A_ULP_TX_T5_FPGA_CMD_6 0x8e54 #define A_ULP_TX_FPGA_CMD_7 0x8e58 +#define A_ULP_TX_T5_FPGA_CMD_7 0x8e58 #define A_ULP_TX_FPGA_CMD_8 0x8e5c +#define A_ULP_TX_T5_FPGA_CMD_8 0x8e5c #define A_ULP_TX_FPGA_CMD_9 0x8e60 +#define A_ULP_TX_T5_FPGA_CMD_9 0x8e60 #define A_ULP_TX_FPGA_CMD_10 0x8e64 +#define A_ULP_TX_T5_FPGA_CMD_10 0x8e64 #define A_ULP_TX_FPGA_CMD_11 0x8e68 +#define A_ULP_TX_T5_FPGA_CMD_11 0x8e68 #define A_ULP_TX_FPGA_CMD_12 0x8e6c +#define A_ULP_TX_T5_FPGA_CMD_12 0x8e6c #define A_ULP_TX_FPGA_CMD_13 0x8e70 +#define A_ULP_TX_T5_FPGA_CMD_13 0x8e70 #define A_ULP_TX_FPGA_CMD_14 0x8e74 +#define A_ULP_TX_T5_FPGA_CMD_14 0x8e74 #define A_ULP_TX_FPGA_CMD_15 0x8e78 +#define A_ULP_TX_T5_FPGA_CMD_15 0x8e78 +#define A_ULP_TX_INT_ENABLE_2 0x8e7c + +#define S_SMARBT2ULP_DATA_PERR_SET 12 +#define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET) +#define F_SMARBT2ULP_DATA_PERR_SET V_SMARBT2ULP_DATA_PERR_SET(1U) + +#define S_ULP2TP_DATA_PERR_SET 11 +#define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET) +#define F_ULP2TP_DATA_PERR_SET V_ULP2TP_DATA_PERR_SET(1U) + +#define S_MA2ULP_DATA_PERR_SET 10 +#define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET) +#define F_MA2ULP_DATA_PERR_SET V_MA2ULP_DATA_PERR_SET(1U) + +#define S_SGE2ULP_DATA_PERR_SET 9 +#define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET) +#define F_SGE2ULP_DATA_PERR_SET V_SGE2ULP_DATA_PERR_SET(1U) + +#define S_CIM2ULP_DATA_PERR_SET 8 +#define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET) +#define F_CIM2ULP_DATA_PERR_SET V_CIM2ULP_DATA_PERR_SET(1U) + +#define S_FSO_HDR_SRAM_PERR_SET3 7 +#define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3) +#define F_FSO_HDR_SRAM_PERR_SET3 V_FSO_HDR_SRAM_PERR_SET3(1U) + +#define S_FSO_HDR_SRAM_PERR_SET2 6 +#define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2) +#define F_FSO_HDR_SRAM_PERR_SET2 V_FSO_HDR_SRAM_PERR_SET2(1U) + +#define S_FSO_HDR_SRAM_PERR_SET1 5 +#define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1) +#define F_FSO_HDR_SRAM_PERR_SET1 V_FSO_HDR_SRAM_PERR_SET1(1U) + +#define S_FSO_HDR_SRAM_PERR_SET0 4 +#define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0) +#define F_FSO_HDR_SRAM_PERR_SET0 V_FSO_HDR_SRAM_PERR_SET0(1U) + +#define S_T10_PI_SRAM_PERR_SET3 3 +#define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3) +#define F_T10_PI_SRAM_PERR_SET3 V_T10_PI_SRAM_PERR_SET3(1U) + +#define S_T10_PI_SRAM_PERR_SET2 2 +#define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2) +#define F_T10_PI_SRAM_PERR_SET2 V_T10_PI_SRAM_PERR_SET2(1U) + +#define S_T10_PI_SRAM_PERR_SET1 1 +#define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1) +#define F_T10_PI_SRAM_PERR_SET1 V_T10_PI_SRAM_PERR_SET1(1U) + +#define S_T10_PI_SRAM_PERR_SET0 0 +#define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0) +#define F_T10_PI_SRAM_PERR_SET0 V_T10_PI_SRAM_PERR_SET0(1U) + +#define A_ULP_TX_INT_CAUSE_2 0x8e80 +#define A_ULP_TX_PERR_ENABLE_2 0x8e84 #define A_ULP_TX_SE_CNT_ERR 0x8ea0 #define S_ERR_CH3 12 @@ -13962,6 +21008,7 @@ #define V_ERR_CH0(x) ((x) << S_ERR_CH0) #define G_ERR_CH0(x) (((x) >> S_ERR_CH0) & M_ERR_CH0) +#define A_ULP_TX_T5_SE_CNT_ERR 0x8ea0 #define A_ULP_TX_SE_CNT_CLR 0x8ea4 #define S_CLR_DROP 16 @@ -13989,6 +21036,7 @@ #define V_CLR_CH0(x) ((x) << S_CLR_CH0) #define G_CLR_CH0(x) (((x) >> S_CLR_CH0) & M_CLR_CH0) +#define A_ULP_TX_T5_SE_CNT_CLR 0x8ea4 #define A_ULP_TX_SE_CNT_CH0 0x8ea8 #define S_SOP_CNT_ULP2TP 28 @@ -14031,9 +21079,13 @@ #define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP) #define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP) +#define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8 #define A_ULP_TX_SE_CNT_CH1 0x8eac +#define A_ULP_TX_T5_SE_CNT_CH1 0x8eac #define A_ULP_TX_SE_CNT_CH2 0x8eb0 +#define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0 #define A_ULP_TX_SE_CNT_CH3 0x8eb4 +#define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4 #define A_ULP_TX_DROP_CNT 0x8eb8 #define S_DROP_CH3 12 @@ -14056,6 +21108,9 @@ #define V_DROP_CH0(x) ((x) << S_DROP_CH0) #define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0) + +#define A_ULP_TX_T5_DROP_CNT 0x8eb8 +#define A_ULP_TX_CSU_REVISION 0x8ebc #define A_ULP_TX_LA_RDPTR_0 0x8ec0 #define A_ULP_TX_LA_RDDATA_0 0x8ec4 #define A_ULP_TX_LA_WRPTR_0 0x8ec8 @@ -14100,6 +21155,17 @@ #define A_ULP_TX_LA_RDDATA_10 0x8f64 #define A_ULP_TX_LA_WRPTR_10 0x8f68 #define A_ULP_TX_LA_RESERVED_10 0x8f6c +#define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70 + +#define S_LA_WR0 0 +#define V_LA_WR0(x) ((x) << S_LA_WR0) +#define F_LA_WR0 V_LA_WR0(1U) + +#define A_ULP_TX_ASIC_DEBUG_0 0x8f74 +#define A_ULP_TX_ASIC_DEBUG_1 0x8f78 +#define A_ULP_TX_ASIC_DEBUG_2 0x8f7c +#define A_ULP_TX_ASIC_DEBUG_3 0x8f80 +#define A_ULP_TX_ASIC_DEBUG_4 0x8f84 /* registers for module PM_RX */ #define PM_RX_BASE_ADDR 0x8fc0 @@ -14127,7 +21193,25 @@ #define A_PM_RX_STAT_CONFIG 0x8fc8 #define A_PM_RX_STAT_COUNT 0x8fcc #define A_PM_RX_STAT_LSB 0x8fd0 +#define A_PM_RX_DBG_CTRL 0x8fd0 + +#define S_OSPIWRBUSY_T5 21 +#define M_OSPIWRBUSY_T5 0x3U +#define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5) +#define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5) + +#define S_ISPIWRBUSY 17 +#define M_ISPIWRBUSY 0xfU +#define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY) +#define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY) + +#define S_PMDBGADDR 0 +#define M_PMDBGADDR 0x1ffffU +#define V_PMDBGADDR(x) ((x) << S_PMDBGADDR) +#define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR) + #define A_PM_RX_STAT_MSB 0x8fd4 +#define A_PM_RX_DBG_DATA 0x8fd4 #define A_PM_RX_INT_ENABLE 0x8fd8 #define S_ZERO_E_CMD_ERROR 22 @@ -14230,8 +21314,593 @@ #define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR) #define F_E_PCMD_PAR_ERROR V_E_PCMD_PAR_ERROR(1U) +#define S_OSPI_OVERFLOW1 28 +#define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1) +#define F_OSPI_OVERFLOW1 V_OSPI_OVERFLOW1(1U) + +#define S_OSPI_OVERFLOW0 27 +#define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0) +#define F_OSPI_OVERFLOW0 V_OSPI_OVERFLOW0(1U) + +#define S_MA_INTF_SDC_ERR 26 +#define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR) +#define F_MA_INTF_SDC_ERR V_MA_INTF_SDC_ERR(1U) + +#define S_BUNDLE_LEN_PARERR 25 +#define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR) +#define F_BUNDLE_LEN_PARERR V_BUNDLE_LEN_PARERR(1U) + +#define S_BUNDLE_LEN_OVFL 24 +#define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL) +#define F_BUNDLE_LEN_OVFL V_BUNDLE_LEN_OVFL(1U) + +#define S_SDC_ERR 23 +#define V_SDC_ERR(x) ((x) << S_SDC_ERR) +#define F_SDC_ERR V_SDC_ERR(1U) + #define A_PM_RX_INT_CAUSE 0x8fdc +#define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000 +#define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001 +#define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002 +#define A_PM_RX_ISPI_DBG_4B_DATA3 0x10003 +#define A_PM_RX_ISPI_DBG_4B_DATA4 0x10004 +#define A_PM_RX_ISPI_DBG_4B_DATA5 0x10005 +#define A_PM_RX_ISPI_DBG_4B_DATA6 0x10006 +#define A_PM_RX_ISPI_DBG_4B_DATA7 0x10007 +#define A_PM_RX_ISPI_DBG_4B_DATA8 0x10008 +#define A_PM_RX_OSPI_DBG_4B_DATA0 0x10009 +#define A_PM_RX_OSPI_DBG_4B_DATA1 0x1000a +#define A_PM_RX_OSPI_DBG_4B_DATA2 0x1000b +#define A_PM_RX_OSPI_DBG_4B_DATA3 0x1000c +#define A_PM_RX_OSPI_DBG_4B_DATA4 0x1000d +#define A_PM_RX_OSPI_DBG_4B_DATA5 0x1000e +#define A_PM_RX_OSPI_DBG_4B_DATA6 0x1000f +#define A_PM_RX_OSPI_DBG_4B_DATA7 0x10010 +#define A_PM_RX_OSPI_DBG_4B_DATA8 0x10011 +#define A_PM_RX_OSPI_DBG_4B_DATA9 0x10012 +#define A_PM_RX_DBG_STAT_MSB 0x10013 +#define A_PM_RX_DBG_STAT_LSB 0x10014 +#define A_PM_RX_DBG_RSVD_FLIT_CNT 0x10015 + +#define S_I_TO_O_PATH_RSVD_FLIT_BACKUP 12 +#define M_I_TO_O_PATH_RSVD_FLIT_BACKUP 0xfU +#define V_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT_BACKUP) +#define G_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) \ + (((x) >> S_I_TO_O_PATH_RSVD_FLIT_BACKUP) & \ + M_I_TO_O_PATH_RSVD_FLIT_BACKUP) + +#define S_I_TO_O_PATH_RSVD_FLIT 8 +#define M_I_TO_O_PATH_RSVD_FLIT 0xfU +#define V_I_TO_O_PATH_RSVD_FLIT(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT) +#define G_I_TO_O_PATH_RSVD_FLIT(x) \ + (((x) >> S_I_TO_O_PATH_RSVD_FLIT) & \ + M_I_TO_O_PATH_RSVD_FLIT) + +#define S_PRFCH_RSVD_FLIT 4 +#define M_PRFCH_RSVD_FLIT 0xfU +#define V_PRFCH_RSVD_FLIT(x) ((x) << S_PRFCH_RSVD_FLIT) +#define G_PRFCH_RSVD_FLIT(x) (((x) >> S_PRFCH_RSVD_FLIT) & M_PRFCH_RSVD_FLIT) + +#define S_OSPI_RSVD_FLIT 0 +#define M_OSPI_RSVD_FLIT 0xfU +#define V_OSPI_RSVD_FLIT(x) ((x) << S_OSPI_RSVD_FLIT) +#define G_OSPI_RSVD_FLIT(x) (((x) >> S_OSPI_RSVD_FLIT) & M_OSPI_RSVD_FLIT) + +#define A_PM_RX_SDC_EN 0x10016 + +#define S_SDC_EN 0 +#define V_SDC_EN(x) ((x) << S_SDC_EN) +#define F_SDC_EN V_SDC_EN(1U) + +#define A_PM_RX_INOUT_FIFO_DBG_CHNL_SEL 0x10017 + +#define S_CHNL_3_SEL 3 +#define V_CHNL_3_SEL(x) ((x) << S_CHNL_3_SEL) +#define F_CHNL_3_SEL V_CHNL_3_SEL(1U) + +#define S_CHNL_2_SEL 2 +#define V_CHNL_2_SEL(x) ((x) << S_CHNL_2_SEL) +#define F_CHNL_2_SEL V_CHNL_2_SEL(1U) + +#define S_CHNL_1_SEL 1 +#define V_CHNL_1_SEL(x) ((x) << S_CHNL_1_SEL) +#define F_CHNL_1_SEL V_CHNL_1_SEL(1U) + +#define S_CHNL_0_SEL 0 +#define V_CHNL_0_SEL(x) ((x) << S_CHNL_0_SEL) +#define F_CHNL_0_SEL V_CHNL_0_SEL(1U) + +#define A_PM_RX_INOUT_FIFO_DBG_WR 0x10018 + +#define S_O_FIFO_WRITE 3 +#define V_O_FIFO_WRITE(x) ((x) << S_O_FIFO_WRITE) +#define F_O_FIFO_WRITE V_O_FIFO_WRITE(1U) + +#define S_I_FIFO_WRITE 2 +#define V_I_FIFO_WRITE(x) ((x) << S_I_FIFO_WRITE) +#define F_I_FIFO_WRITE V_I_FIFO_WRITE(1U) + +#define S_O_FIFO_READ 1 +#define V_O_FIFO_READ(x) ((x) << S_O_FIFO_READ) +#define F_O_FIFO_READ V_O_FIFO_READ(1U) + +#define S_I_FIFO_READ 0 +#define V_I_FIFO_READ(x) ((x) << S_I_FIFO_READ) +#define F_I_FIFO_READ V_I_FIFO_READ(1U) + +#define A_PM_RX_INPUT_FIFO_STR_FWD_EN 0x10019 + +#define S_ISPI_STR_FWD_EN 0 +#define V_ISPI_STR_FWD_EN(x) ((x) << S_ISPI_STR_FWD_EN) +#define F_ISPI_STR_FWD_EN V_ISPI_STR_FWD_EN(1U) + +#define A_PM_RX_PRFTCH_ACROSS_BNDLE_EN 0x1001a + +#define S_PRFTCH_ACROSS_BNDLE_EN 0 +#define V_PRFTCH_ACROSS_BNDLE_EN(x) ((x) << S_PRFTCH_ACROSS_BNDLE_EN) +#define F_PRFTCH_ACROSS_BNDLE_EN V_PRFTCH_ACROSS_BNDLE_EN(1U) + +#define A_PM_RX_PRFTCH_WRR_ENABLE 0x1001b + +#define S_PRFTCH_WRR_ENABLE 0 +#define V_PRFTCH_WRR_ENABLE(x) ((x) << S_PRFTCH_WRR_ENABLE) +#define F_PRFTCH_WRR_ENABLE V_PRFTCH_WRR_ENABLE(1U) + +#define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT 0x1001c + +#define S_CHNL1_MAX_DEFICIT_CNT 16 +#define M_CHNL1_MAX_DEFICIT_CNT 0xffffU +#define V_CHNL1_MAX_DEFICIT_CNT(x) ((x) << S_CHNL1_MAX_DEFICIT_CNT) +#define G_CHNL1_MAX_DEFICIT_CNT(x) \ + (((x) >> S_CHNL1_MAX_DEFICIT_CNT) & M_CHNL1_MAX_DEFICIT_CNT) + +#define S_CHNL0_MAX_DEFICIT_CNT 0 +#define M_CHNL0_MAX_DEFICIT_CNT 0xffffU +#define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT) +#define G_CHNL0_MAX_DEFICIT_CNT(x) \ + (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT) + +#define A_PM_RX_FEATURE_EN 0x1001d + +#define S_PIO_CH_DEFICIT_CTL_EN_RX 0 +#define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX) +#define F_PIO_CH_DEFICIT_CTL_EN_RX V_PIO_CH_DEFICIT_CTL_EN_RX(1U) + +#define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e + +#define S_CH0_OSPI_DEFICIT_THRSHLD 0 +#define M_CH0_OSPI_DEFICIT_THRSHLD 0xfffU +#define V_CH0_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH0_OSPI_DEFICIT_THRSHLD) +#define G_CH0_OSPI_DEFICIT_THRSHLD(x) \ + (((x) >> S_CH0_OSPI_DEFICIT_THRSHLD) & M_CH0_OSPI_DEFICIT_THRSHLD) + +#define A_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x1001f + +#define S_CH1_OSPI_DEFICIT_THRSHLD 0 +#define M_CH1_OSPI_DEFICIT_THRSHLD 0xfffU +#define V_CH1_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH1_OSPI_DEFICIT_THRSHLD) +#define G_CH1_OSPI_DEFICIT_THRSHLD(x) \ + (((x) >> S_CH1_OSPI_DEFICIT_THRSHLD) & M_CH1_OSPI_DEFICIT_THRSHLD) +#define A_PM_RX_INT_CAUSE_MASK_HALT 0x10020 +#define A_PM_RX_DBG_STAT0 0x10021 + +#define S_RX_RD_I_BUSY 29 +#define V_RX_RD_I_BUSY(x) ((x) << S_RX_RD_I_BUSY) +#define F_RX_RD_I_BUSY V_RX_RD_I_BUSY(1U) + +#define S_RX_WR_TO_O_BUSY 28 +#define V_RX_WR_TO_O_BUSY(x) ((x) << S_RX_WR_TO_O_BUSY) +#define F_RX_WR_TO_O_BUSY V_RX_WR_TO_O_BUSY(1U) + +#define S_RX_M_TO_O_BUSY 27 +#define V_RX_M_TO_O_BUSY(x) ((x) << S_RX_M_TO_O_BUSY) +#define F_RX_M_TO_O_BUSY V_RX_M_TO_O_BUSY(1U) + +#define S_RX_I_TO_M_BUSY 26 +#define V_RX_I_TO_M_BUSY(x) ((x) << S_RX_I_TO_M_BUSY) +#define F_RX_I_TO_M_BUSY V_RX_I_TO_M_BUSY(1U) + +#define S_RX_PCMD_FB_ONLY 25 +#define V_RX_PCMD_FB_ONLY(x) ((x) << S_RX_PCMD_FB_ONLY) +#define F_RX_PCMD_FB_ONLY V_RX_PCMD_FB_ONLY(1U) + +#define S_RX_PCMD_MEM 24 +#define V_RX_PCMD_MEM(x) ((x) << S_RX_PCMD_MEM) +#define F_RX_PCMD_MEM V_RX_PCMD_MEM(1U) + +#define S_RX_PCMD_BYPASS 23 +#define V_RX_PCMD_BYPASS(x) ((x) << S_RX_PCMD_BYPASS) +#define F_RX_PCMD_BYPASS V_RX_PCMD_BYPASS(1U) + +#define S_RX_PCMD_EOP 22 +#define V_RX_PCMD_EOP(x) ((x) << S_RX_PCMD_EOP) +#define F_RX_PCMD_EOP V_RX_PCMD_EOP(1U) + +#define S_RX_DUMPLICATE_PCMD_EOP 21 +#define V_RX_DUMPLICATE_PCMD_EOP(x) ((x) << S_RX_DUMPLICATE_PCMD_EOP) +#define F_RX_DUMPLICATE_PCMD_EOP V_RX_DUMPLICATE_PCMD_EOP(1U) + +#define S_RX_PCMD_EOB 20 +#define V_RX_PCMD_EOB(x) ((x) << S_RX_PCMD_EOB) +#define F_RX_PCMD_EOB V_RX_PCMD_EOB(1U) + +#define S_RX_PCMD_FB 16 +#define M_RX_PCMD_FB 0xfU +#define V_RX_PCMD_FB(x) ((x) << S_RX_PCMD_FB) +#define G_RX_PCMD_FB(x) (((x) >> S_RX_PCMD_FB) & M_RX_PCMD_FB) + +#define S_RX_PCMD_LEN 0 +#define M_RX_PCMD_LEN 0xffffU +#define V_RX_PCMD_LEN(x) ((x) << S_RX_PCMD_LEN) +#define G_RX_PCMD_LEN(x) (((x) >> S_RX_PCMD_LEN) & M_RX_PCMD_LEN) + +#define A_PM_RX_DBG_STAT1 0x10022 + +#define S_RX_PCMD0_MEM 30 +#define V_RX_PCMD0_MEM(x) ((x) << S_RX_PCMD0_MEM) +#define F_RX_PCMD0_MEM V_RX_PCMD0_MEM(1U) + +#define S_RX_FREE_OSPI_CNT0 18 +#define M_RX_FREE_OSPI_CNT0 0xfffU +#define V_RX_FREE_OSPI_CNT0(x) ((x) << S_RX_FREE_OSPI_CNT0) +#define G_RX_FREE_OSPI_CNT0(x) \ + (((x) >> S_RX_FREE_OSPI_CNT0) & M_RX_FREE_OSPI_CNT0) + +#define S_RX_PCMD0_FLIT_LEN 6 +#define M_RX_PCMD0_FLIT_LEN 0xfffU +#define V_RX_PCMD0_FLIT_LEN(x) ((x) << S_RX_PCMD0_FLIT_LEN) +#define G_RX_PCMD0_FLIT_LEN(x) \ + (((x) >> S_RX_PCMD0_FLIT_LEN) & M_RX_PCMD0_FLIT_LEN) + +#define S_RX_PCMD0_CMD 2 +#define M_RX_PCMD0_CMD 0xfU +#define V_RX_PCMD0_CMD(x) ((x) << S_RX_PCMD0_CMD) +#define G_RX_PCMD0_CMD(x) (((x) >> S_RX_PCMD0_CMD) & M_RX_PCMD0_CMD) + +#define S_RX_OFIFO_FULL0 1 +#define V_RX_OFIFO_FULL0(x) ((x) << S_RX_OFIFO_FULL0) +#define F_RX_OFIFO_FULL0 V_RX_OFIFO_FULL0(1U) + +#define S_RX_PCMD0_BYPASS 0 +#define V_RX_PCMD0_BYPASS(x) ((x) << S_RX_PCMD0_BYPASS) +#define F_RX_PCMD0_BYPASS V_RX_PCMD0_BYPASS(1U) + +#define A_PM_RX_DBG_STAT2 0x10023 + +#define S_RX_PCMD1_MEM 30 +#define V_RX_PCMD1_MEM(x) ((x) << S_RX_PCMD1_MEM) +#define F_RX_PCMD1_MEM V_RX_PCMD1_MEM(1U) + +#define S_RX_FREE_OSPI_CNT1 18 +#define M_RX_FREE_OSPI_CNT1 0xfffU +#define V_RX_FREE_OSPI_CNT1(x) ((x) << S_RX_FREE_OSPI_CNT1) +#define G_RX_FREE_OSPI_CNT1(x) \ + (((x) >> S_RX_FREE_OSPI_CNT1) & M_RX_FREE_OSPI_CNT1) + +#define S_RX_PCMD1_FLIT_LEN 6 +#define M_RX_PCMD1_FLIT_LEN 0xfffU +#define V_RX_PCMD1_FLIT_LEN(x) ((x) << S_RX_PCMD1_FLIT_LEN) +#define G_RX_PCMD1_FLIT_LEN(x) \ + (((x) >> S_RX_PCMD1_FLIT_LEN) & M_RX_PCMD1_FLIT_LEN) + +#define S_RX_PCMD1_CMD 2 +#define M_RX_PCMD1_CMD 0xfU +#define V_RX_PCMD1_CMD(x) ((x) << S_RX_PCMD1_CMD) +#define G_RX_PCMD1_CMD(x) (((x) >> S_RX_PCMD1_CMD) & M_RX_PCMD1_CMD) + +#define S_RX_OFIFO_FULL1 1 +#define V_RX_OFIFO_FULL1(x) ((x) << S_RX_OFIFO_FULL1) +#define F_RX_OFIFO_FULL1 V_RX_OFIFO_FULL1(1U) + +#define S_RX_PCMD1_BYPASS 0 +#define V_RX_PCMD1_BYPASS(x) ((x) << S_RX_PCMD1_BYPASS) +#define F_RX_PCMD1_BYPASS V_RX_PCMD1_BYPASS(1U) + +#define A_PM_RX_DBG_STAT3 0x10024 + +#define S_RX_SET_PCMD_RES_RDY_RD 10 +#define M_RX_SET_PCMD_RES_RDY_RD 0x3U +#define V_RX_SET_PCMD_RES_RDY_RD(x) ((x) << S_RX_SET_PCMD_RES_RDY_RD) +#define G_RX_SET_PCMD_RES_RDY_RD(x) \ + (((x) >> S_RX_SET_PCMD_RES_RDY_RD) & M_RX_SET_PCMD_RES_RDY_RD) + +#define S_RX_ISSUED_PREFETCH_RD_E_CLR 8 +#define M_RX_ISSUED_PREFETCH_RD_E_CLR 0x3U +#define V_RX_ISSUED_PREFETCH_RD_E_CLR(x) ((x) << S_RX_ISSUED_PREFETCH_RD_E_CLR) +#define G_RX_ISSUED_PREFETCH_RD_E_CLR(x) \ + (((x) >> S_RX_ISSUED_PREFETCH_RD_E_CLR) & M_RX_ISSUED_PREFETCH_RD_E_CLR) + +#define S_RX_ISSUED_PREFETCH_RD 6 +#define M_RX_ISSUED_PREFETCH_RD 0x3U +#define V_RX_ISSUED_PREFETCH_RD(x) ((x) << S_RX_ISSUED_PREFETCH_RD) +#define G_RX_ISSUED_PREFETCH_RD(x) \ + (((x) >> S_RX_ISSUED_PREFETCH_RD) & M_RX_ISSUED_PREFETCH_RD) + +#define S_RX_PCMD_RES_RDY 4 +#define M_RX_PCMD_RES_RDY 0x3U +#define V_RX_PCMD_RES_RDY(x) ((x) << S_RX_PCMD_RES_RDY) +#define G_RX_PCMD_RES_RDY(x) (((x) >> S_RX_PCMD_RES_RDY) & M_RX_PCMD_RES_RDY) + +#define S_RX_DB_VLD 3 +#define V_RX_DB_VLD(x) ((x) << S_RX_DB_VLD) +#define F_RX_DB_VLD V_RX_DB_VLD(1U) + +#define S_RX_FIRST_BUNDLE 1 +#define M_RX_FIRST_BUNDLE 0x3U +#define V_RX_FIRST_BUNDLE(x) ((x) << S_RX_FIRST_BUNDLE) +#define G_RX_FIRST_BUNDLE(x) (((x) >> S_RX_FIRST_BUNDLE) & M_RX_FIRST_BUNDLE) + +#define S_RX_SDC_DRDY 0 +#define V_RX_SDC_DRDY(x) ((x) << S_RX_SDC_DRDY) +#define F_RX_SDC_DRDY V_RX_SDC_DRDY(1U) + +#define A_PM_RX_DBG_STAT4 0x10025 + +#define S_RX_PCMD_VLD 26 +#define V_RX_PCMD_VLD(x) ((x) << S_RX_PCMD_VLD) +#define F_RX_PCMD_VLD V_RX_PCMD_VLD(1U) + +#define S_RX_PCMD_TO_CH 25 +#define V_RX_PCMD_TO_CH(x) ((x) << S_RX_PCMD_TO_CH) +#define F_RX_PCMD_TO_CH V_RX_PCMD_TO_CH(1U) + +#define S_RX_PCMD_FROM_CH 23 +#define M_RX_PCMD_FROM_CH 0x3U +#define V_RX_PCMD_FROM_CH(x) ((x) << S_RX_PCMD_FROM_CH) +#define G_RX_PCMD_FROM_CH(x) (((x) >> S_RX_PCMD_FROM_CH) & M_RX_PCMD_FROM_CH) + +#define S_RX_LINE 18 +#define M_RX_LINE 0x1fU +#define V_RX_LINE(x) ((x) << S_RX_LINE) +#define G_RX_LINE(x) (((x) >> S_RX_LINE) & M_RX_LINE) + +#define S_RX_IESPI_TXVALID 14 +#define M_RX_IESPI_TXVALID 0xfU +#define V_RX_IESPI_TXVALID(x) ((x) << S_RX_IESPI_TXVALID) +#define G_RX_IESPI_TXVALID(x) (((x) >> S_RX_IESPI_TXVALID) & M_RX_IESPI_TXVALID) + +#define S_RX_IESPI_TXFULL 10 +#define M_RX_IESPI_TXFULL 0xfU +#define V_RX_IESPI_TXFULL(x) ((x) << S_RX_IESPI_TXFULL) +#define G_RX_IESPI_TXFULL(x) (((x) >> S_RX_IESPI_TXFULL) & M_RX_IESPI_TXFULL) + +#define S_RX_PCMD_SRDY 8 +#define M_RX_PCMD_SRDY 0x3U +#define V_RX_PCMD_SRDY(x) ((x) << S_RX_PCMD_SRDY) +#define G_RX_PCMD_SRDY(x) (((x) >> S_RX_PCMD_SRDY) & M_RX_PCMD_SRDY) + +#define S_RX_PCMD_DRDY 6 +#define M_RX_PCMD_DRDY 0x3U +#define V_RX_PCMD_DRDY(x) ((x) << S_RX_PCMD_DRDY) +#define G_RX_PCMD_DRDY(x) (((x) >> S_RX_PCMD_DRDY) & M_RX_PCMD_DRDY) + +#define S_RX_PCMD_CMD 2 +#define M_RX_PCMD_CMD 0xfU +#define V_RX_PCMD_CMD(x) ((x) << S_RX_PCMD_CMD) +#define G_RX_PCMD_CMD(x) (((x) >> S_RX_PCMD_CMD) & M_RX_PCMD_CMD) + +#define S_DUPLICATE 0 +#define M_DUPLICATE 0x3U +#define V_DUPLICATE(x) ((x) << S_DUPLICATE) +#define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE) + +#define A_PM_RX_DBG_STAT5 0x10026 + +#define S_RX_ATLST_1_PCMD_CH1 29 +#define V_RX_ATLST_1_PCMD_CH1(x) ((x) << S_RX_ATLST_1_PCMD_CH1) +#define F_RX_ATLST_1_PCMD_CH1 V_RX_ATLST_1_PCMD_CH1(1U) + +#define S_RX_ATLST_1_PCMD_CH0 28 +#define V_RX_ATLST_1_PCMD_CH0(x) ((x) << S_RX_ATLST_1_PCMD_CH0) +#define F_RX_ATLST_1_PCMD_CH0 V_RX_ATLST_1_PCMD_CH0(1U) + +#define S_RX_ISPI_TXVALID 20 +#define M_RX_ISPI_TXVALID 0xfU +#define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID) +#define G_RX_ISPI_TXVALID(x) (((x) >> S_RX_ISPI_TXVALID) & M_RX_ISPI_TXVALID) + +#define S_RX_ISPI_FULL 16 +#define M_RX_ISPI_FULL 0xfU +#define V_RX_ISPI_FULL(x) ((x) << S_RX_ISPI_FULL) +#define G_RX_ISPI_FULL(x) (((x) >> S_RX_ISPI_FULL) & M_RX_ISPI_FULL) + +#define S_RX_OSPI_TXVALID 14 +#define M_RX_OSPI_TXVALID 0x3U +#define V_RX_OSPI_TXVALID(x) ((x) << S_RX_OSPI_TXVALID) +#define G_RX_OSPI_TXVALID(x) (((x) >> S_RX_OSPI_TXVALID) & M_RX_OSPI_TXVALID) + +#define S_RX_OSPI_FULL 12 +#define M_RX_OSPI_FULL 0x3U +#define V_RX_OSPI_FULL(x) ((x) << S_RX_OSPI_FULL) +#define G_RX_OSPI_FULL(x) (((x) >> S_RX_OSPI_FULL) & M_RX_OSPI_FULL) + +#define S_RX_E_RXVALID 8 +#define M_RX_E_RXVALID 0xfU +#define V_RX_E_RXVALID(x) ((x) << S_RX_E_RXVALID) +#define G_RX_E_RXVALID(x) (((x) >> S_RX_E_RXVALID) & M_RX_E_RXVALID) + +#define S_RX_E_RXAFULL 4 +#define M_RX_E_RXAFULL 0xfU +#define V_RX_E_RXAFULL(x) ((x) << S_RX_E_RXAFULL) +#define G_RX_E_RXAFULL(x) (((x) >> S_RX_E_RXAFULL) & M_RX_E_RXAFULL) + +#define S_RX_C_TXVALID 2 +#define M_RX_C_TXVALID 0x3U +#define V_RX_C_TXVALID(x) ((x) << S_RX_C_TXVALID) +#define G_RX_C_TXVALID(x) (((x) >> S_RX_C_TXVALID) & M_RX_C_TXVALID) + +#define S_RX_C_TXAFULL 0 +#define M_RX_C_TXAFULL 0x3U +#define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL) +#define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL) + +#define A_PM_RX_DBG_STAT6 0x10027 + +#define S_RX_M_INTRNL_FIFO_CNT 4 +#define M_RX_M_INTRNL_FIFO_CNT 0x3U +#define V_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_RX_M_INTRNL_FIFO_CNT) +#define G_RX_M_INTRNL_FIFO_CNT(x) \ + (((x) >> S_RX_M_INTRNL_FIFO_CNT) & M_RX_M_INTRNL_FIFO_CNT) + +#define S_RX_M_REQADDRRDY 3 +#define V_RX_M_REQADDRRDY(x) ((x) << S_RX_M_REQADDRRDY) +#define F_RX_M_REQADDRRDY V_RX_M_REQADDRRDY(1U) + +#define S_RX_M_REQWRITE 2 +#define V_RX_M_REQWRITE(x) ((x) << S_RX_M_REQWRITE) +#define F_RX_M_REQWRITE V_RX_M_REQWRITE(1U) + +#define S_RX_M_REQDATAVLD 1 +#define V_RX_M_REQDATAVLD(x) ((x) << S_RX_M_REQDATAVLD) +#define F_RX_M_REQDATAVLD V_RX_M_REQDATAVLD(1U) + +#define S_RX_M_REQDATARDY 0 +#define V_RX_M_REQDATARDY(x) ((x) << S_RX_M_REQDATARDY) +#define F_RX_M_REQDATARDY V_RX_M_REQDATARDY(1U) + +#define A_PM_RX_DBG_STAT7 0x10028 + +#define S_RX_PCMD1_FREE_CNT 7 +#define M_RX_PCMD1_FREE_CNT 0x7fU +#define V_RX_PCMD1_FREE_CNT(x) ((x) << S_RX_PCMD1_FREE_CNT) +#define G_RX_PCMD1_FREE_CNT(x) \ + (((x) >> S_RX_PCMD1_FREE_CNT) & M_RX_PCMD1_FREE_CNT) + +#define S_RX_PCMD0_FREE_CNT 0 +#define M_RX_PCMD0_FREE_CNT 0x7fU +#define V_RX_PCMD0_FREE_CNT(x) ((x) << S_RX_PCMD0_FREE_CNT) +#define G_RX_PCMD0_FREE_CNT(x) \ + (((x) >> S_RX_PCMD0_FREE_CNT) & M_RX_PCMD0_FREE_CNT) + +#define A_PM_RX_DBG_STAT8 0x10029 + +#define S_RX_IN_EOP_CNT3 28 +#define M_RX_IN_EOP_CNT3 0xfU +#define V_RX_IN_EOP_CNT3(x) ((x) << S_RX_IN_EOP_CNT3) +#define G_RX_IN_EOP_CNT3(x) (((x) >> S_RX_IN_EOP_CNT3) & M_RX_IN_EOP_CNT3) + +#define S_RX_IN_EOP_CNT2 24 +#define M_RX_IN_EOP_CNT2 0xfU +#define V_RX_IN_EOP_CNT2(x) ((x) << S_RX_IN_EOP_CNT2) +#define G_RX_IN_EOP_CNT2(x) (((x) >> S_RX_IN_EOP_CNT2) & M_RX_IN_EOP_CNT2) + +#define S_RX_IN_EOP_CNT1 20 +#define M_RX_IN_EOP_CNT1 0xfU +#define V_RX_IN_EOP_CNT1(x) ((x) << S_RX_IN_EOP_CNT1) +#define G_RX_IN_EOP_CNT1(x) (((x) >> S_RX_IN_EOP_CNT1) & M_RX_IN_EOP_CNT1) + +#define S_RX_IN_EOP_CNT0 16 +#define M_RX_IN_EOP_CNT0 0xfU +#define V_RX_IN_EOP_CNT0(x) ((x) << S_RX_IN_EOP_CNT0) +#define G_RX_IN_EOP_CNT0(x) (((x) >> S_RX_IN_EOP_CNT0) & M_RX_IN_EOP_CNT0) + +#define S_RX_IN_SOP_CNT3 12 +#define M_RX_IN_SOP_CNT3 0xfU +#define V_RX_IN_SOP_CNT3(x) ((x) << S_RX_IN_SOP_CNT3) +#define G_RX_IN_SOP_CNT3(x) (((x) >> S_RX_IN_SOP_CNT3) & M_RX_IN_SOP_CNT3) + +#define S_RX_IN_SOP_CNT2 8 +#define M_RX_IN_SOP_CNT2 0xfU +#define V_RX_IN_SOP_CNT2(x) ((x) << S_RX_IN_SOP_CNT2) +#define G_RX_IN_SOP_CNT2(x) (((x) >> S_RX_IN_SOP_CNT2) & M_RX_IN_SOP_CNT2) + +#define S_RX_IN_SOP_CNT1 4 +#define M_RX_IN_SOP_CNT1 0xfU +#define V_RX_IN_SOP_CNT1(x) ((x) << S_RX_IN_SOP_CNT1) +#define G_RX_IN_SOP_CNT1(x) (((x) >> S_RX_IN_SOP_CNT1) & M_RX_IN_SOP_CNT1) + +#define S_RX_IN_SOP_CNT0 0 +#define M_RX_IN_SOP_CNT0 0xfU +#define V_RX_IN_SOP_CNT0(x) ((x) << S_RX_IN_SOP_CNT0) +#define G_RX_IN_SOP_CNT0(x) (((x) >> S_RX_IN_SOP_CNT0) & M_RX_IN_SOP_CNT0) + +#define A_PM_RX_DBG_STAT9 0x1002a + +#define S_RX_RSVD0 28 +#define M_RX_RSVD0 0xfU +#define V_RX_RSVD0(x) ((x) << S_RX_RSVD0) +#define G_RX_RSVD0(x) (((x) >> S_RX_RSVD0) & M_RX_RSVD0) + +#define S_RX_RSVD1 24 +#define M_RX_RSVD1 0xfU +#define V_RX_RSVD1(x) ((x) << S_RX_RSVD1) +#define G_RX_RSVD1(x) (((x) >> S_RX_RSVD1) & M_RX_RSVD1) + +#define S_RX_OUT_EOP_CNT1 20 +#define M_RX_OUT_EOP_CNT1 0xfU +#define V_RX_OUT_EOP_CNT1(x) ((x) << S_RX_OUT_EOP_CNT1) +#define G_RX_OUT_EOP_CNT1(x) (((x) >> S_RX_OUT_EOP_CNT1) & M_RX_OUT_EOP_CNT1) + +#define S_RX_OUT_EOP_CNT0 16 +#define M_RX_OUT_EOP_CNT0 0xfU +#define V_RX_OUT_EOP_CNT0(x) ((x) << S_RX_OUT_EOP_CNT0) +#define G_RX_OUT_EOP_CNT0(x) (((x) >> S_RX_OUT_EOP_CNT0) & M_RX_OUT_EOP_CNT0) + +#define S_RX_RSVD2 12 +#define M_RX_RSVD2 0xfU +#define V_RX_RSVD2(x) ((x) << S_RX_RSVD2) +#define G_RX_RSVD2(x) (((x) >> S_RX_RSVD2) & M_RX_RSVD2) + +#define S_RX_RSVD3 8 +#define M_RX_RSVD3 0xfU +#define V_RX_RSVD3(x) ((x) << S_RX_RSVD3) +#define G_RX_RSVD3(x) (((x) >> S_RX_RSVD3) & M_RX_RSVD3) + +#define S_RX_OUT_SOP_CNT1 4 +#define M_RX_OUT_SOP_CNT1 0xfU +#define V_RX_OUT_SOP_CNT1(x) ((x) << S_RX_OUT_SOP_CNT1) +#define G_RX_OUT_SOP_CNT1(x) (((x) >> S_RX_OUT_SOP_CNT1) & M_RX_OUT_SOP_CNT1) + +#define S_RX_OUT_SOP_CNT0 0 +#define M_RX_OUT_SOP_CNT0 0xfU +#define V_RX_OUT_SOP_CNT0(x) ((x) << S_RX_OUT_SOP_CNT0) +#define G_RX_OUT_SOP_CNT0(x) (((x) >> S_RX_OUT_SOP_CNT0) & M_RX_OUT_SOP_CNT0) + +#define A_PM_RX_DBG_STAT10 0x1002b + +#define S_RX_CH_DEFICIT_BLOWED 24 +#define V_RX_CH_DEFICIT_BLOWED(x) ((x) << S_RX_CH_DEFICIT_BLOWED) +#define F_RX_CH_DEFICIT_BLOWED V_RX_CH_DEFICIT_BLOWED(1U) + +#define S_RX_CH1_DEFICIT 12 +#define M_RX_CH1_DEFICIT 0xfffU +#define V_RX_CH1_DEFICIT(x) ((x) << S_RX_CH1_DEFICIT) +#define G_RX_CH1_DEFICIT(x) (((x) >> S_RX_CH1_DEFICIT) & M_RX_CH1_DEFICIT) + +#define S_RX_CH0_DEFICIT 0 +#define M_RX_CH0_DEFICIT 0xfffU +#define V_RX_CH0_DEFICIT(x) ((x) << S_RX_CH0_DEFICIT) +#define G_RX_CH0_DEFICIT(x) (((x) >> S_RX_CH0_DEFICIT) & M_RX_CH0_DEFICIT) + +#define A_PM_RX_DBG_STAT11 0x1002c + +#define S_RX_BUNDLE_LEN_SRDY 30 +#define M_RX_BUNDLE_LEN_SRDY 0x3U +#define V_RX_BUNDLE_LEN_SRDY(x) ((x) << S_RX_BUNDLE_LEN_SRDY) +#define G_RX_BUNDLE_LEN_SRDY(x) \ + (((x) >> S_RX_BUNDLE_LEN_SRDY) & M_RX_BUNDLE_LEN_SRDY) + +#define S_RX_RSVD11_1 28 +#define M_RX_RSVD11_1 0x3U +#define V_RX_RSVD11_1(x) ((x) << S_RX_RSVD11_1) +#define G_RX_RSVD11_1(x) (((x) >> S_RX_RSVD11_1) & M_RX_RSVD11_1) + +#define S_RX_BUNDLE_LEN1 16 +#define M_RX_BUNDLE_LEN1 0xfffU +#define V_RX_BUNDLE_LEN1(x) ((x) << S_RX_BUNDLE_LEN1) +#define G_RX_BUNDLE_LEN1(x) (((x) >> S_RX_BUNDLE_LEN1) & M_RX_BUNDLE_LEN1) + +#define S_RX_RSVD11 12 +#define M_RX_RSVD11 0xfU +#define V_RX_RSVD11(x) ((x) << S_RX_RSVD11) +#define G_RX_RSVD11(x) (((x) >> S_RX_RSVD11) & M_RX_RSVD11) + +#define S_RX_BUNDLE_LEN0 0 +#define M_RX_BUNDLE_LEN0 0xfffU +#define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0) +#define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0) + /* registers for module PM_TX */ #define PM_TX_BASE_ADDR 0x8fe0 @@ -14276,7 +21945,15 @@ #define A_PM_TX_STAT_CONFIG 0x8fe8 #define A_PM_TX_STAT_COUNT 0x8fec #define A_PM_TX_STAT_LSB 0x8ff0 +#define A_PM_TX_DBG_CTRL 0x8ff0 + +#define S_OSPIWRBUSY 21 +#define M_OSPIWRBUSY 0xfU +#define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY) +#define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY) + #define A_PM_TX_STAT_MSB 0x8ff4 +#define A_PM_TX_DBG_DATA 0x8ff4 #define A_PM_TX_INT_ENABLE 0x8ff8 #define S_PCMD_LEN_OVFL0 31 @@ -14421,6 +22098,642 @@ #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR) #define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U) +#define S_OSPI_OR_BUNDLE_LEN_PAR_ERR 3 +#define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR) +#define F_OSPI_OR_BUNDLE_LEN_PAR_ERR V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U) + +#define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000 +#define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001 +#define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002 +#define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003 +#define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004 +#define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005 +#define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006 +#define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007 +#define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008 +#define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009 +#define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a +#define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b +#define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c +#define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d +#define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e +#define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f +#define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010 +#define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011 +#define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012 +#define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013 +#define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014 +#define A_PM_TX_OSPI_DBG_4B_DATA12 0x10015 +#define A_PM_TX_OSPI_DBG_4B_DATA13 0x10016 +#define A_PM_TX_OSPI_DBG_4B_DATA14 0x10017 +#define A_PM_TX_OSPI_DBG_4B_DATA15 0x10018 +#define A_PM_TX_OSPI_DBG_4B_DATA16 0x10019 +#define A_PM_TX_DBG_STAT_MSB 0x1001a +#define A_PM_TX_DBG_STAT_LSB 0x1001b +#define A_PM_TX_DBG_RSVD_FLIT_CNT 0x1001c +#define A_PM_TX_SDC_EN 0x1001d +#define A_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x1001e +#define A_PM_TX_INOUT_FIFO_DBG_WR 0x1001f +#define A_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10020 +#define A_PM_TX_FEATURE_EN 0x10021 + +#define S_PIO_CH_DEFICIT_CTL_EN 2 +#define V_PIO_CH_DEFICIT_CTL_EN(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN) +#define F_PIO_CH_DEFICIT_CTL_EN V_PIO_CH_DEFICIT_CTL_EN(1U) + +#define S_PIO_WRR_BASED_PRFTCH_EN 1 +#define V_PIO_WRR_BASED_PRFTCH_EN(x) ((x) << S_PIO_WRR_BASED_PRFTCH_EN) +#define F_PIO_WRR_BASED_PRFTCH_EN V_PIO_WRR_BASED_PRFTCH_EN(1U) + +#define A_PM_TX_T5_PM_TX_INT_ENABLE 0x10022 + +#define S_OSPI_OVERFLOW3 7 +#define V_OSPI_OVERFLOW3(x) ((x) << S_OSPI_OVERFLOW3) +#define F_OSPI_OVERFLOW3 V_OSPI_OVERFLOW3(1U) + +#define S_OSPI_OVERFLOW2 6 +#define V_OSPI_OVERFLOW2(x) ((x) << S_OSPI_OVERFLOW2) +#define F_OSPI_OVERFLOW2 V_OSPI_OVERFLOW2(1U) + +#define S_M_INTFPERREN 3 +#define V_M_INTFPERREN(x) ((x) << S_M_INTFPERREN) +#define F_M_INTFPERREN V_M_INTFPERREN(1U) + +#define S_BUNDLE_LEN_PARERR_EN 2 +#define V_BUNDLE_LEN_PARERR_EN(x) ((x) << S_BUNDLE_LEN_PARERR_EN) +#define F_BUNDLE_LEN_PARERR_EN V_BUNDLE_LEN_PARERR_EN(1U) + +#define S_BUNDLE_LEN_OVFL_EN 1 +#define V_BUNDLE_LEN_OVFL_EN(x) ((x) << S_BUNDLE_LEN_OVFL_EN) +#define F_BUNDLE_LEN_OVFL_EN V_BUNDLE_LEN_OVFL_EN(1U) + +#define S_SDC_ERR_EN 0 +#define V_SDC_ERR_EN(x) ((x) << S_SDC_ERR_EN) +#define F_SDC_ERR_EN V_SDC_ERR_EN(1U) + +#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023 +#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024 +#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025 +#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026 +#define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027 +#define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028 +#define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029 + +#define S_CH2_OSPI_DEFICIT_THRSHLD 0 +#define M_CH2_OSPI_DEFICIT_THRSHLD 0xfffU +#define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD) +#define G_CH2_OSPI_DEFICIT_THRSHLD(x) \ + (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD) + +#define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a + +#define S_CH3_OSPI_DEFICIT_THRSHLD 0 +#define M_CH3_OSPI_DEFICIT_THRSHLD 0xfffU +#define V_CH3_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH3_OSPI_DEFICIT_THRSHLD) +#define G_CH3_OSPI_DEFICIT_THRSHLD(x) \ + (((x) >> S_CH3_OSPI_DEFICIT_THRSHLD) & M_CH3_OSPI_DEFICIT_THRSHLD) + +#define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b +#define A_PM_TX_DBG_STAT0 0x1002c + +#define S_RD_I_BUSY 28 +#define V_RD_I_BUSY(x) ((x) << S_RD_I_BUSY) +#define F_RD_I_BUSY V_RD_I_BUSY(1U) + +#define S_WR_O_ONLY 27 +#define V_WR_O_ONLY(x) ((x) << S_WR_O_ONLY) +#define F_WR_O_ONLY V_WR_O_ONLY(1U) + +#define S_M_TO_BUSY 26 +#define V_M_TO_BUSY(x) ((x) << S_M_TO_BUSY) +#define F_M_TO_BUSY V_M_TO_BUSY(1U) + +#define S_I_TO_M_BUSY 25 +#define V_I_TO_M_BUSY(x) ((x) << S_I_TO_M_BUSY) +#define F_I_TO_M_BUSY V_I_TO_M_BUSY(1U) + +#define S_PCMD_FB_ONLY 24 +#define V_PCMD_FB_ONLY(x) ((x) << S_PCMD_FB_ONLY) +#define F_PCMD_FB_ONLY V_PCMD_FB_ONLY(1U) + +#define S_PCMD_MEM 23 +#define V_PCMD_MEM(x) ((x) << S_PCMD_MEM) +#define F_PCMD_MEM V_PCMD_MEM(1U) + +#define S_PCMD_BYPASS 22 +#define V_PCMD_BYPASS(x) ((x) << S_PCMD_BYPASS) +#define F_PCMD_BYPASS V_PCMD_BYPASS(1U) + +#define S_PCMD_EOP 21 +#define V_PCMD_EOP(x) ((x) << S_PCMD_EOP) +#define F_PCMD_EOP V_PCMD_EOP(1U) + +#define S_PCMD_END_BUNDLE 20 +#define V_PCMD_END_BUNDLE(x) ((x) << S_PCMD_END_BUNDLE) +#define F_PCMD_END_BUNDLE V_PCMD_END_BUNDLE(1U) + +#define S_PCMD_FB_CMD 16 +#define M_PCMD_FB_CMD 0xfU +#define V_PCMD_FB_CMD(x) ((x) << S_PCMD_FB_CMD) +#define G_PCMD_FB_CMD(x) (((x) >> S_PCMD_FB_CMD) & M_PCMD_FB_CMD) + +#define S_CUR_PCMD_LEN 0 +#define M_CUR_PCMD_LEN 0xffffU +#define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN) +#define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN) + +#define A_PM_TX_DBG_STAT1 0x1002d + +#define S_PCMD_MEM0 31 +#define V_PCMD_MEM0(x) ((x) << S_PCMD_MEM0) +#define F_PCMD_MEM0 V_PCMD_MEM0(1U) + +#define S_FREE_OESPI_CNT0 19 +#define M_FREE_OESPI_CNT0 0xfffU +#define V_FREE_OESPI_CNT0(x) ((x) << S_FREE_OESPI_CNT0) +#define G_FREE_OESPI_CNT0(x) (((x) >> S_FREE_OESPI_CNT0) & M_FREE_OESPI_CNT0) + +#define S_PCMD_FLIT_LEN0 7 +#define M_PCMD_FLIT_LEN0 0xfffU +#define V_PCMD_FLIT_LEN0(x) ((x) << S_PCMD_FLIT_LEN0) +#define G_PCMD_FLIT_LEN0(x) (((x) >> S_PCMD_FLIT_LEN0) & M_PCMD_FLIT_LEN0) + +#define S_PCMD_CMD0 3 +#define M_PCMD_CMD0 0xfU +#define V_PCMD_CMD0(x) ((x) << S_PCMD_CMD0) +#define G_PCMD_CMD0(x) (((x) >> S_PCMD_CMD0) & M_PCMD_CMD0) + +#define S_OFIFO_FULL0 2 +#define V_OFIFO_FULL0(x) ((x) << S_OFIFO_FULL0) +#define F_OFIFO_FULL0 V_OFIFO_FULL0(1U) + +#define S_GCSUM_DRDY0 1 +#define V_GCSUM_DRDY0(x) ((x) << S_GCSUM_DRDY0) +#define F_GCSUM_DRDY0 V_GCSUM_DRDY0(1U) + +#define S_BYPASS0 0 +#define V_BYPASS0(x) ((x) << S_BYPASS0) +#define F_BYPASS0 V_BYPASS0(1U) + +#define A_PM_TX_DBG_STAT2 0x1002e + +#define S_PCMD_MEM1 31 +#define V_PCMD_MEM1(x) ((x) << S_PCMD_MEM1) +#define F_PCMD_MEM1 V_PCMD_MEM1(1U) + +#define S_FREE_OESPI_CNT1 19 +#define M_FREE_OESPI_CNT1 0xfffU +#define V_FREE_OESPI_CNT1(x) ((x) << S_FREE_OESPI_CNT1) +#define G_FREE_OESPI_CNT1(x) (((x) >> S_FREE_OESPI_CNT1) & M_FREE_OESPI_CNT1) + +#define S_PCMD_FLIT_LEN1 7 +#define M_PCMD_FLIT_LEN1 0xfffU +#define V_PCMD_FLIT_LEN1(x) ((x) << S_PCMD_FLIT_LEN1) +#define G_PCMD_FLIT_LEN1(x) (((x) >> S_PCMD_FLIT_LEN1) & M_PCMD_FLIT_LEN1) + +#define S_PCMD_CMD1 3 +#define M_PCMD_CMD1 0xfU +#define V_PCMD_CMD1(x) ((x) << S_PCMD_CMD1) +#define G_PCMD_CMD1(x) (((x) >> S_PCMD_CMD1) & M_PCMD_CMD1) + +#define S_OFIFO_FULL1 2 +#define V_OFIFO_FULL1(x) ((x) << S_OFIFO_FULL1) +#define F_OFIFO_FULL1 V_OFIFO_FULL1(1U) + +#define S_GCSUM_DRDY1 1 +#define V_GCSUM_DRDY1(x) ((x) << S_GCSUM_DRDY1) +#define F_GCSUM_DRDY1 V_GCSUM_DRDY1(1U) + +#define S_BYPASS1 0 +#define V_BYPASS1(x) ((x) << S_BYPASS1) +#define F_BYPASS1 V_BYPASS1(1U) + +#define A_PM_TX_DBG_STAT3 0x1002f + +#define S_PCMD_MEM2 31 +#define V_PCMD_MEM2(x) ((x) << S_PCMD_MEM2) +#define F_PCMD_MEM2 V_PCMD_MEM2(1U) + +#define S_FREE_OESPI_CNT2 19 +#define M_FREE_OESPI_CNT2 0xfffU +#define V_FREE_OESPI_CNT2(x) ((x) << S_FREE_OESPI_CNT2) +#define G_FREE_OESPI_CNT2(x) (((x) >> S_FREE_OESPI_CNT2) & M_FREE_OESPI_CNT2) + +#define S_PCMD_FLIT_LEN2 7 +#define M_PCMD_FLIT_LEN2 0xfffU +#define V_PCMD_FLIT_LEN2(x) ((x) << S_PCMD_FLIT_LEN2) +#define G_PCMD_FLIT_LEN2(x) (((x) >> S_PCMD_FLIT_LEN2) & M_PCMD_FLIT_LEN2) + +#define S_PCMD_CMD2 3 +#define M_PCMD_CMD2 0xfU +#define V_PCMD_CMD2(x) ((x) << S_PCMD_CMD2) +#define G_PCMD_CMD2(x) (((x) >> S_PCMD_CMD2) & M_PCMD_CMD2) + +#define S_OFIFO_FULL2 2 +#define V_OFIFO_FULL2(x) ((x) << S_OFIFO_FULL2) +#define F_OFIFO_FULL2 V_OFIFO_FULL2(1U) + +#define S_GCSUM_DRDY2 1 +#define V_GCSUM_DRDY2(x) ((x) << S_GCSUM_DRDY2) +#define F_GCSUM_DRDY2 V_GCSUM_DRDY2(1U) + +#define S_BYPASS2 0 +#define V_BYPASS2(x) ((x) << S_BYPASS2) +#define F_BYPASS2 V_BYPASS2(1U) + +#define A_PM_TX_DBG_STAT4 0x10030 + +#define S_PCMD_MEM3 31 +#define V_PCMD_MEM3(x) ((x) << S_PCMD_MEM3) +#define F_PCMD_MEM3 V_PCMD_MEM3(1U) + +#define S_FREE_OESPI_CNT3 19 +#define M_FREE_OESPI_CNT3 0xfffU +#define V_FREE_OESPI_CNT3(x) ((x) << S_FREE_OESPI_CNT3) +#define G_FREE_OESPI_CNT3(x) (((x) >> S_FREE_OESPI_CNT3) & M_FREE_OESPI_CNT3) + +#define S_PCMD_FLIT_LEN3 7 +#define M_PCMD_FLIT_LEN3 0xfffU +#define V_PCMD_FLIT_LEN3(x) ((x) << S_PCMD_FLIT_LEN3) +#define G_PCMD_FLIT_LEN3(x) (((x) >> S_PCMD_FLIT_LEN3) & M_PCMD_FLIT_LEN3) + +#define S_PCMD_CMD3 3 +#define M_PCMD_CMD3 0xfU +#define V_PCMD_CMD3(x) ((x) << S_PCMD_CMD3) +#define G_PCMD_CMD3(x) (((x) >> S_PCMD_CMD3) & M_PCMD_CMD3) + +#define S_OFIFO_FULL3 2 +#define V_OFIFO_FULL3(x) ((x) << S_OFIFO_FULL3) +#define F_OFIFO_FULL3 V_OFIFO_FULL3(1U) + +#define S_GCSUM_DRDY3 1 +#define V_GCSUM_DRDY3(x) ((x) << S_GCSUM_DRDY3) +#define F_GCSUM_DRDY3 V_GCSUM_DRDY3(1U) + +#define S_BYPASS3 0 +#define V_BYPASS3(x) ((x) << S_BYPASS3) +#define F_BYPASS3 V_BYPASS3(1U) + +#define A_PM_TX_DBG_STAT5 0x10031 + +#define S_SET_PCMD_RES_RDY_RD 24 +#define M_SET_PCMD_RES_RDY_RD 0xfU +#define V_SET_PCMD_RES_RDY_RD(x) ((x) << S_SET_PCMD_RES_RDY_RD) +#define G_SET_PCMD_RES_RDY_RD(x) \ + (((x) >> S_SET_PCMD_RES_RDY_RD) & M_SET_PCMD_RES_RDY_RD) + +#define S_ISSUED_PREF_RD_ER_CLR 20 +#define M_ISSUED_PREF_RD_ER_CLR 0xfU +#define V_ISSUED_PREF_RD_ER_CLR(x) ((x) << S_ISSUED_PREF_RD_ER_CLR) +#define G_ISSUED_PREF_RD_ER_CLR(x) \ + (((x) >> S_ISSUED_PREF_RD_ER_CLR) & M_ISSUED_PREF_RD_ER_CLR) + +#define S_ISSUED_PREF_RD 16 +#define M_ISSUED_PREF_RD 0xfU +#define V_ISSUED_PREF_RD(x) ((x) << S_ISSUED_PREF_RD) +#define G_ISSUED_PREF_RD(x) (((x) >> S_ISSUED_PREF_RD) & M_ISSUED_PREF_RD) + +#define S_PCMD_RES_RDY 12 +#define M_PCMD_RES_RDY 0xfU +#define V_PCMD_RES_RDY(x) ((x) << S_PCMD_RES_RDY) +#define G_PCMD_RES_RDY(x) (((x) >> S_PCMD_RES_RDY) & M_PCMD_RES_RDY) + +#define S_DB_VLD 11 +#define V_DB_VLD(x) ((x) << S_DB_VLD) +#define F_DB_VLD V_DB_VLD(1U) + +#define S_INJECT0_DRDY 10 +#define V_INJECT0_DRDY(x) ((x) << S_INJECT0_DRDY) +#define F_INJECT0_DRDY V_INJECT0_DRDY(1U) + +#define S_INJECT1_DRDY 9 +#define V_INJECT1_DRDY(x) ((x) << S_INJECT1_DRDY) +#define F_INJECT1_DRDY V_INJECT1_DRDY(1U) + +#define S_FIRST_BUNDLE 5 +#define M_FIRST_BUNDLE 0xfU +#define V_FIRST_BUNDLE(x) ((x) << S_FIRST_BUNDLE) +#define G_FIRST_BUNDLE(x) (((x) >> S_FIRST_BUNDLE) & M_FIRST_BUNDLE) + +#define S_GCSUM_MORE_THAN_2_LEFT 1 +#define M_GCSUM_MORE_THAN_2_LEFT 0xfU +#define V_GCSUM_MORE_THAN_2_LEFT(x) ((x) << S_GCSUM_MORE_THAN_2_LEFT) +#define G_GCSUM_MORE_THAN_2_LEFT(x) \ + (((x) >> S_GCSUM_MORE_THAN_2_LEFT) & M_GCSUM_MORE_THAN_2_LEFT) + +#define S_SDC_DRDY 0 +#define V_SDC_DRDY(x) ((x) << S_SDC_DRDY) +#define F_SDC_DRDY V_SDC_DRDY(1U) + +#define A_PM_TX_DBG_STAT6 0x10032 + +#define S_PCMD_VLD 31 +#define V_PCMD_VLD(x) ((x) << S_PCMD_VLD) +#define F_PCMD_VLD V_PCMD_VLD(1U) + +#define S_PCMD_CH 29 +#define M_PCMD_CH 0x3U +#define V_PCMD_CH(x) ((x) << S_PCMD_CH) +#define G_PCMD_CH(x) (((x) >> S_PCMD_CH) & M_PCMD_CH) + +#define S_STATE_MACHINE_LOC 24 +#define M_STATE_MACHINE_LOC 0x1fU +#define V_STATE_MACHINE_LOC(x) ((x) << S_STATE_MACHINE_LOC) +#define G_STATE_MACHINE_LOC(x) \ + (((x) >> S_STATE_MACHINE_LOC) & M_STATE_MACHINE_LOC) + +#define S_ICSPI_TXVALID 20 +#define M_ICSPI_TXVALID 0xfU +#define V_ICSPI_TXVALID(x) ((x) << S_ICSPI_TXVALID) +#define G_ICSPI_TXVALID(x) (((x) >> S_ICSPI_TXVALID) & M_ICSPI_TXVALID) + +#define S_ICSPI_TXFULL 16 +#define M_ICSPI_TXFULL 0xfU +#define V_ICSPI_TXFULL(x) ((x) << S_ICSPI_TXFULL) +#define G_ICSPI_TXFULL(x) (((x) >> S_ICSPI_TXFULL) & M_ICSPI_TXFULL) + +#define S_PCMD_SRDY 12 +#define M_PCMD_SRDY 0xfU +#define V_PCMD_SRDY(x) ((x) << S_PCMD_SRDY) +#define G_PCMD_SRDY(x) (((x) >> S_PCMD_SRDY) & M_PCMD_SRDY) + +#define S_PCMD_DRDY 8 +#define M_PCMD_DRDY 0xfU +#define V_PCMD_DRDY(x) ((x) << S_PCMD_DRDY) +#define G_PCMD_DRDY(x) (((x) >> S_PCMD_DRDY) & M_PCMD_DRDY) + +#define S_PCMD_CMD 4 +#define M_PCMD_CMD 0xfU +#define V_PCMD_CMD(x) ((x) << S_PCMD_CMD) +#define G_PCMD_CMD(x) (((x) >> S_PCMD_CMD) & M_PCMD_CMD) + +#define S_OEFIFO_FULL3 3 +#define V_OEFIFO_FULL3(x) ((x) << S_OEFIFO_FULL3) +#define F_OEFIFO_FULL3 V_OEFIFO_FULL3(1U) + +#define S_OEFIFO_FULL2 2 +#define V_OEFIFO_FULL2(x) ((x) << S_OEFIFO_FULL2) +#define F_OEFIFO_FULL2 V_OEFIFO_FULL2(1U) + +#define S_OEFIFO_FULL1 1 +#define V_OEFIFO_FULL1(x) ((x) << S_OEFIFO_FULL1) +#define F_OEFIFO_FULL1 V_OEFIFO_FULL1(1U) + +#define S_OEFIFO_FULL0 0 +#define V_OEFIFO_FULL0(x) ((x) << S_OEFIFO_FULL0) +#define F_OEFIFO_FULL0 V_OEFIFO_FULL0(1U) + +#define A_PM_TX_DBG_STAT7 0x10033 + +#define S_ICSPI_RXVALID 28 +#define M_ICSPI_RXVALID 0xfU +#define V_ICSPI_RXVALID(x) ((x) << S_ICSPI_RXVALID) +#define G_ICSPI_RXVALID(x) (((x) >> S_ICSPI_RXVALID) & M_ICSPI_RXVALID) + +#define S_ICSPI_RXFULL 24 +#define M_ICSPI_RXFULL 0xfU +#define V_ICSPI_RXFULL(x) ((x) << S_ICSPI_RXFULL) +#define G_ICSPI_RXFULL(x) (((x) >> S_ICSPI_RXFULL) & M_ICSPI_RXFULL) + +#define S_OESPI_VALID 20 +#define M_OESPI_VALID 0xfU +#define V_OESPI_VALID(x) ((x) << S_OESPI_VALID) +#define G_OESPI_VALID(x) (((x) >> S_OESPI_VALID) & M_OESPI_VALID) + +#define S_OESPI_FULL 16 +#define M_OESPI_FULL 0xfU +#define V_OESPI_FULL(x) ((x) << S_OESPI_FULL) +#define G_OESPI_FULL(x) (((x) >> S_OESPI_FULL) & M_OESPI_FULL) + +#define S_C_RXVALID 12 +#define M_C_RXVALID 0xfU +#define V_C_RXVALID(x) ((x) << S_C_RXVALID) +#define G_C_RXVALID(x) (((x) >> S_C_RXVALID) & M_C_RXVALID) + +#define S_C_RXAFULL 8 +#define M_C_RXAFULL 0xfU +#define V_C_RXAFULL(x) ((x) << S_C_RXAFULL) +#define G_C_RXAFULL(x) (((x) >> S_C_RXAFULL) & M_C_RXAFULL) + +#define S_E_TXVALID3 7 +#define V_E_TXVALID3(x) ((x) << S_E_TXVALID3) +#define F_E_TXVALID3 V_E_TXVALID3(1U) + +#define S_E_TXVALID2 6 +#define V_E_TXVALID2(x) ((x) << S_E_TXVALID2) +#define F_E_TXVALID2 V_E_TXVALID2(1U) + +#define S_E_TXVALID1 5 +#define V_E_TXVALID1(x) ((x) << S_E_TXVALID1) +#define F_E_TXVALID1 V_E_TXVALID1(1U) + +#define S_E_TXVALID0 4 +#define V_E_TXVALID0(x) ((x) << S_E_TXVALID0) +#define F_E_TXVALID0 V_E_TXVALID0(1U) + +#define S_E_TXFULL3 3 +#define V_E_TXFULL3(x) ((x) << S_E_TXFULL3) +#define F_E_TXFULL3 V_E_TXFULL3(1U) + +#define S_E_TXFULL2 2 +#define V_E_TXFULL2(x) ((x) << S_E_TXFULL2) +#define F_E_TXFULL2 V_E_TXFULL2(1U) + +#define S_E_TXFULL1 1 +#define V_E_TXFULL1(x) ((x) << S_E_TXFULL1) +#define F_E_TXFULL1 V_E_TXFULL1(1U) + +#define S_E_TXFULL0 0 +#define V_E_TXFULL0(x) ((x) << S_E_TXFULL0) +#define F_E_TXFULL0 V_E_TXFULL0(1U) + +#define A_PM_TX_DBG_STAT8 0x10034 + +#define S_MC_RSP_FIFO_CNT 24 +#define M_MC_RSP_FIFO_CNT 0x3U +#define V_MC_RSP_FIFO_CNT(x) ((x) << S_MC_RSP_FIFO_CNT) +#define G_MC_RSP_FIFO_CNT(x) (((x) >> S_MC_RSP_FIFO_CNT) & M_MC_RSP_FIFO_CNT) + +#define S_PCMD_FREE_CNT0 14 +#define M_PCMD_FREE_CNT0 0x3ffU +#define V_PCMD_FREE_CNT0(x) ((x) << S_PCMD_FREE_CNT0) +#define G_PCMD_FREE_CNT0(x) (((x) >> S_PCMD_FREE_CNT0) & M_PCMD_FREE_CNT0) + +#define S_PCMD_FREE_CNT1 4 +#define M_PCMD_FREE_CNT1 0x3ffU +#define V_PCMD_FREE_CNT1(x) ((x) << S_PCMD_FREE_CNT1) +#define G_PCMD_FREE_CNT1(x) (((x) >> S_PCMD_FREE_CNT1) & M_PCMD_FREE_CNT1) + +#define S_M_REQADDRRDY 3 +#define V_M_REQADDRRDY(x) ((x) << S_M_REQADDRRDY) +#define F_M_REQADDRRDY V_M_REQADDRRDY(1U) + +#define S_M_REQWRITE 2 +#define V_M_REQWRITE(x) ((x) << S_M_REQWRITE) +#define F_M_REQWRITE V_M_REQWRITE(1U) + +#define S_M_REQDATAVLD 1 +#define V_M_REQDATAVLD(x) ((x) << S_M_REQDATAVLD) +#define F_M_REQDATAVLD V_M_REQDATAVLD(1U) + +#define S_M_REQDATARDY 0 +#define V_M_REQDATARDY(x) ((x) << S_M_REQDATARDY) +#define F_M_REQDATARDY V_M_REQDATARDY(1U) + +#define A_PM_TX_DBG_STAT9 0x10035 + +#define S_PCMD_FREE_CNT2 10 +#define M_PCMD_FREE_CNT2 0x3ffU +#define V_PCMD_FREE_CNT2(x) ((x) << S_PCMD_FREE_CNT2) +#define G_PCMD_FREE_CNT2(x) (((x) >> S_PCMD_FREE_CNT2) & M_PCMD_FREE_CNT2) + +#define S_PCMD_FREE_CNT3 0 +#define M_PCMD_FREE_CNT3 0x3ffU +#define V_PCMD_FREE_CNT3(x) ((x) << S_PCMD_FREE_CNT3) +#define G_PCMD_FREE_CNT3(x) (((x) >> S_PCMD_FREE_CNT3) & M_PCMD_FREE_CNT3) + +#define A_PM_TX_DBG_STAT10 0x10036 + +#define S_IN_EOP_CNT3 28 +#define M_IN_EOP_CNT3 0xfU +#define V_IN_EOP_CNT3(x) ((x) << S_IN_EOP_CNT3) +#define G_IN_EOP_CNT3(x) (((x) >> S_IN_EOP_CNT3) & M_IN_EOP_CNT3) + +#define S_IN_EOP_CNT2 24 +#define M_IN_EOP_CNT2 0xfU +#define V_IN_EOP_CNT2(x) ((x) << S_IN_EOP_CNT2) +#define G_IN_EOP_CNT2(x) (((x) >> S_IN_EOP_CNT2) & M_IN_EOP_CNT2) + +#define S_IN_EOP_CNT1 20 +#define M_IN_EOP_CNT1 0xfU +#define V_IN_EOP_CNT1(x) ((x) << S_IN_EOP_CNT1) +#define G_IN_EOP_CNT1(x) (((x) >> S_IN_EOP_CNT1) & M_IN_EOP_CNT1) + +#define S_IN_EOP_CNT0 16 +#define M_IN_EOP_CNT0 0xfU +#define V_IN_EOP_CNT0(x) ((x) << S_IN_EOP_CNT0) +#define G_IN_EOP_CNT0(x) (((x) >> S_IN_EOP_CNT0) & M_IN_EOP_CNT0) + +#define S_IN_SOP_CNT3 12 +#define M_IN_SOP_CNT3 0xfU +#define V_IN_SOP_CNT3(x) ((x) << S_IN_SOP_CNT3) +#define G_IN_SOP_CNT3(x) (((x) >> S_IN_SOP_CNT3) & M_IN_SOP_CNT3) + +#define S_IN_SOP_CNT2 8 +#define M_IN_SOP_CNT2 0xfU +#define V_IN_SOP_CNT2(x) ((x) << S_IN_SOP_CNT2) +#define G_IN_SOP_CNT2(x) (((x) >> S_IN_SOP_CNT2) & M_IN_SOP_CNT2) + +#define S_IN_SOP_CNT1 4 +#define M_IN_SOP_CNT1 0xfU +#define V_IN_SOP_CNT1(x) ((x) << S_IN_SOP_CNT1) +#define G_IN_SOP_CNT1(x) (((x) >> S_IN_SOP_CNT1) & M_IN_SOP_CNT1) + +#define S_IN_SOP_CNT0 0 +#define M_IN_SOP_CNT0 0xfU +#define V_IN_SOP_CNT0(x) ((x) << S_IN_SOP_CNT0) +#define G_IN_SOP_CNT0(x) (((x) >> S_IN_SOP_CNT0) & M_IN_SOP_CNT0) + +#define A_PM_TX_DBG_STAT11 0x10037 + +#define S_OUT_EOP_CNT3 28 +#define M_OUT_EOP_CNT3 0xfU +#define V_OUT_EOP_CNT3(x) ((x) << S_OUT_EOP_CNT3) +#define G_OUT_EOP_CNT3(x) (((x) >> S_OUT_EOP_CNT3) & M_OUT_EOP_CNT3) + +#define S_OUT_EOP_CNT2 24 +#define M_OUT_EOP_CNT2 0xfU +#define V_OUT_EOP_CNT2(x) ((x) << S_OUT_EOP_CNT2) +#define G_OUT_EOP_CNT2(x) (((x) >> S_OUT_EOP_CNT2) & M_OUT_EOP_CNT2) + +#define S_OUT_EOP_CNT1 20 +#define M_OUT_EOP_CNT1 0xfU +#define V_OUT_EOP_CNT1(x) ((x) << S_OUT_EOP_CNT1) +#define G_OUT_EOP_CNT1(x) (((x) >> S_OUT_EOP_CNT1) & M_OUT_EOP_CNT1) + +#define S_OUT_EOP_CNT0 16 +#define M_OUT_EOP_CNT0 0xfU +#define V_OUT_EOP_CNT0(x) ((x) << S_OUT_EOP_CNT0) +#define G_OUT_EOP_CNT0(x) (((x) >> S_OUT_EOP_CNT0) & M_OUT_EOP_CNT0) + +#define S_OUT_SOP_CNT3 12 +#define M_OUT_SOP_CNT3 0xfU +#define V_OUT_SOP_CNT3(x) ((x) << S_OUT_SOP_CNT3) +#define G_OUT_SOP_CNT3(x) (((x) >> S_OUT_SOP_CNT3) & M_OUT_SOP_CNT3) + +#define S_OUT_SOP_CNT2 8 +#define M_OUT_SOP_CNT2 0xfU +#define V_OUT_SOP_CNT2(x) ((x) << S_OUT_SOP_CNT2) +#define G_OUT_SOP_CNT2(x) (((x) >> S_OUT_SOP_CNT2) & M_OUT_SOP_CNT2) + +#define S_OUT_SOP_CNT1 4 +#define M_OUT_SOP_CNT1 0xfU +#define V_OUT_SOP_CNT1(x) ((x) << S_OUT_SOP_CNT1) +#define G_OUT_SOP_CNT1(x) (((x) >> S_OUT_SOP_CNT1) & M_OUT_SOP_CNT1) + +#define S_OUT_SOP_CNT0 0 +#define M_OUT_SOP_CNT0 0xfU +#define V_OUT_SOP_CNT0(x) ((x) << S_OUT_SOP_CNT0) +#define G_OUT_SOP_CNT0(x) (((x) >> S_OUT_SOP_CNT0) & M_OUT_SOP_CNT0) + +#define A_PM_TX_DBG_STAT12 0x10038 +#define A_PM_TX_DBG_STAT13 0x10039 + +#define S_CH_DEFICIT_BLOWED 31 +#define V_CH_DEFICIT_BLOWED(x) ((x) << S_CH_DEFICIT_BLOWED) +#define F_CH_DEFICIT_BLOWED V_CH_DEFICIT_BLOWED(1U) + +#define S_CH1_DEFICIT 16 +#define M_CH1_DEFICIT 0xfffU +#define V_CH1_DEFICIT(x) ((x) << S_CH1_DEFICIT) +#define G_CH1_DEFICIT(x) (((x) >> S_CH1_DEFICIT) & M_CH1_DEFICIT) + +#define S_CH0_DEFICIT 0 +#define M_CH0_DEFICIT 0xfffU +#define V_CH0_DEFICIT(x) ((x) << S_CH0_DEFICIT) +#define G_CH0_DEFICIT(x) (((x) >> S_CH0_DEFICIT) & M_CH0_DEFICIT) + +#define A_PM_TX_DBG_STAT14 0x1003a + +#define S_CH3_DEFICIT 16 +#define M_CH3_DEFICIT 0xfffU +#define V_CH3_DEFICIT(x) ((x) << S_CH3_DEFICIT) +#define G_CH3_DEFICIT(x) (((x) >> S_CH3_DEFICIT) & M_CH3_DEFICIT) + +#define S_CH2_DEFICIT 0 +#define M_CH2_DEFICIT 0xfffU +#define V_CH2_DEFICIT(x) ((x) << S_CH2_DEFICIT) +#define G_CH2_DEFICIT(x) (((x) >> S_CH2_DEFICIT) & M_CH2_DEFICIT) + +#define A_PM_TX_DBG_STAT15 0x1003b + +#define S_BUNDLE_LEN_SRDY 28 +#define M_BUNDLE_LEN_SRDY 0xfU +#define V_BUNDLE_LEN_SRDY(x) ((x) << S_BUNDLE_LEN_SRDY) +#define G_BUNDLE_LEN_SRDY(x) (((x) >> S_BUNDLE_LEN_SRDY) & M_BUNDLE_LEN_SRDY) + +#define S_BUNDLE_LEN1 16 +#define M_BUNDLE_LEN1 0xfffU +#define V_BUNDLE_LEN1(x) ((x) << S_BUNDLE_LEN1) +#define G_BUNDLE_LEN1(x) (((x) >> S_BUNDLE_LEN1) & M_BUNDLE_LEN1) + +#define S_BUNDLE_LEN0 0 +#define M_BUNDLE_LEN0 0xfffU +#define V_BUNDLE_LEN0(x) ((x) << S_BUNDLE_LEN0) +#define G_BUNDLE_LEN0(x) (((x) >> S_BUNDLE_LEN0) & M_BUNDLE_LEN0) + +#define A_PM_TX_DBG_STAT16 0x1003c + +#define S_BUNDLE_LEN3 16 +#define M_BUNDLE_LEN3 0xfffU +#define V_BUNDLE_LEN3(x) ((x) << S_BUNDLE_LEN3) +#define G_BUNDLE_LEN3(x) (((x) >> S_BUNDLE_LEN3) & M_BUNDLE_LEN3) + +#define S_BUNDLE_LEN2 0 +#define M_BUNDLE_LEN2 0xfffU +#define V_BUNDLE_LEN2(x) ((x) << S_BUNDLE_LEN2) +#define G_BUNDLE_LEN2(x) (((x) >> S_BUNDLE_LEN2) & M_BUNDLE_LEN2) + /* registers for module MPS */ #define MPS_BASE_ADDR 0x9000 @@ -14584,6 +22897,48 @@ #define V_PRTY0(x) ((x) << S_PRTY0) #define G_PRTY0(x) (((x) >> S_PRTY0) & M_PRTY0) +#define A_MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP 0x30 + +#define S_TXPRTY7 28 +#define M_TXPRTY7 0xfU +#define V_TXPRTY7(x) ((x) << S_TXPRTY7) +#define G_TXPRTY7(x) (((x) >> S_TXPRTY7) & M_TXPRTY7) + +#define S_TXPRTY6 24 +#define M_TXPRTY6 0xfU +#define V_TXPRTY6(x) ((x) << S_TXPRTY6) +#define G_TXPRTY6(x) (((x) >> S_TXPRTY6) & M_TXPRTY6) + +#define S_TXPRTY5 20 +#define M_TXPRTY5 0xfU +#define V_TXPRTY5(x) ((x) << S_TXPRTY5) +#define G_TXPRTY5(x) (((x) >> S_TXPRTY5) & M_TXPRTY5) + +#define S_TXPRTY4 16 +#define M_TXPRTY4 0xfU +#define V_TXPRTY4(x) ((x) << S_TXPRTY4) +#define G_TXPRTY4(x) (((x) >> S_TXPRTY4) & M_TXPRTY4) + +#define S_TXPRTY3 12 +#define M_TXPRTY3 0xfU +#define V_TXPRTY3(x) ((x) << S_TXPRTY3) +#define G_TXPRTY3(x) (((x) >> S_TXPRTY3) & M_TXPRTY3) + +#define S_TXPRTY2 8 +#define M_TXPRTY2 0xfU +#define V_TXPRTY2(x) ((x) << S_TXPRTY2) +#define G_TXPRTY2(x) (((x) >> S_TXPRTY2) & M_TXPRTY2) + +#define S_TXPRTY1 4 +#define M_TXPRTY1 0xfU +#define V_TXPRTY1(x) ((x) << S_TXPRTY1) +#define G_TXPRTY1(x) (((x) >> S_TXPRTY1) & M_TXPRTY1) + +#define S_TXPRTY0 0 +#define M_TXPRTY0 0xfU +#define V_TXPRTY0(x) ((x) << S_TXPRTY0) +#define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0) + #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88 @@ -14699,6 +23054,10 @@ #define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0) #define F_OVLAN_EN0 V_OVLAN_EN0(1U) +#define S_PTP_FWD_UP 21 +#define V_PTP_FWD_UP(x) ((x) << S_PTP_FWD_UP) +#define F_PTP_FWD_UP V_PTP_FWD_UP(1U) + #define A_MPS_PORT_RX_MTU 0x104 #define A_MPS_PORT_RX_PF_MAP 0x108 #define A_MPS_PORT_RX_VF_MAP0 0x10c @@ -14769,6 +23128,8 @@ #define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF) #define A_MPS_PORT_RX_SPARE 0x13c +#define A_MPS_PORT_RX_PTP_RSS_HASH 0x140 +#define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190 #define S_CREDIT 0 @@ -14802,6 +23163,23 @@ #define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT) #define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8 + +#define S_FPGAPAUSEEN 0 +#define V_FPGAPAUSEEN(x) ((x) << S_FPGAPAUSEEN) +#define F_FPGAPAUSEEN V_FPGAPAUSEEN(1U) + +#define A_MPS_PORT_TX_PAUSE_PENDING_STATUS 0x1d0 + +#define S_OFF_PENDING 8 +#define M_OFF_PENDING 0xffU +#define V_OFF_PENDING(x) ((x) << S_OFF_PENDING) +#define G_OFF_PENDING(x) (((x) >> S_OFF_PENDING) & M_OFF_PENDING) + +#define S_ON_PENDING 0 +#define M_ON_PENDING 0xffU +#define V_ON_PENDING(x) ((x) << S_ON_PENDING) +#define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING) + #define A_MPS_PORT_CLS_HASH_SRAM 0x200 #define S_VALID 20 @@ -14917,6 +23295,52 @@ #define V_PF_VLAN_SEL(x) ((x) << S_PF_VLAN_SEL) #define F_PF_VLAN_SEL V_PF_VLAN_SEL(1U) +#define S_LPBK_TCAM1_HIT_PRIORITY 14 +#define V_LPBK_TCAM1_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM1_HIT_PRIORITY) +#define F_LPBK_TCAM1_HIT_PRIORITY V_LPBK_TCAM1_HIT_PRIORITY(1U) + +#define S_LPBK_TCAM0_HIT_PRIORITY 13 +#define V_LPBK_TCAM0_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM0_HIT_PRIORITY) +#define F_LPBK_TCAM0_HIT_PRIORITY V_LPBK_TCAM0_HIT_PRIORITY(1U) + +#define S_LPBK_TCAM_PRIORITY 12 +#define V_LPBK_TCAM_PRIORITY(x) ((x) << S_LPBK_TCAM_PRIORITY) +#define F_LPBK_TCAM_PRIORITY V_LPBK_TCAM_PRIORITY(1U) + +#define S_LPBK_SMAC_TCAM_SEL 10 +#define M_LPBK_SMAC_TCAM_SEL 0x3U +#define V_LPBK_SMAC_TCAM_SEL(x) ((x) << S_LPBK_SMAC_TCAM_SEL) +#define G_LPBK_SMAC_TCAM_SEL(x) \ + (((x) >> S_LPBK_SMAC_TCAM_SEL) & M_LPBK_SMAC_TCAM_SEL) + +#define S_LPBK_DMAC_TCAM_SEL 8 +#define M_LPBK_DMAC_TCAM_SEL 0x3U +#define V_LPBK_DMAC_TCAM_SEL(x) ((x) << S_LPBK_DMAC_TCAM_SEL) +#define G_LPBK_DMAC_TCAM_SEL(x) \ + (((x) >> S_LPBK_DMAC_TCAM_SEL) & M_LPBK_DMAC_TCAM_SEL) + +#define S_TCAM1_HIT_PRIORITY 7 +#define V_TCAM1_HIT_PRIORITY(x) ((x) << S_TCAM1_HIT_PRIORITY) +#define F_TCAM1_HIT_PRIORITY V_TCAM1_HIT_PRIORITY(1U) + +#define S_TCAM0_HIT_PRIORITY 6 +#define V_TCAM0_HIT_PRIORITY(x) ((x) << S_TCAM0_HIT_PRIORITY) +#define F_TCAM0_HIT_PRIORITY V_TCAM0_HIT_PRIORITY(1U) + +#define S_TCAM_PRIORITY 5 +#define V_TCAM_PRIORITY(x) ((x) << S_TCAM_PRIORITY) +#define F_TCAM_PRIORITY V_TCAM_PRIORITY(1U) + +#define S_SMAC_TCAM_SEL 3 +#define M_SMAC_TCAM_SEL 0x3U +#define V_SMAC_TCAM_SEL(x) ((x) << S_SMAC_TCAM_SEL) +#define G_SMAC_TCAM_SEL(x) (((x) >> S_SMAC_TCAM_SEL) & M_SMAC_TCAM_SEL) + +#define S_DMAC_TCAM_SEL 1 +#define M_DMAC_TCAM_SEL 0x3U +#define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL) +#define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL) + #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324 @@ -15017,6 +23441,8 @@ #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528 +#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528 +#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548 @@ -15071,6 +23497,8 @@ #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 +#define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618 +#define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c #define A_MPS_CMN_CTL 0x9000 #define S_DETECT8023 3 @@ -15086,6 +23514,10 @@ #define V_NUMPORTS(x) ((x) << S_NUMPORTS) #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS) +#define S_LPBKCRDTCTRL 4 +#define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL) +#define F_LPBKCRDTCTRL V_LPBKCRDTCTRL(1U) + #define A_MPS_INT_ENABLE 0x9004 #define S_STATINTENB 5 @@ -15112,6 +23544,12 @@ #define V_PLINTENB(x) ((x) << S_PLINTENB) #define F_PLINTENB V_PLINTENB(1U) +#define A_MPS_CGEN_GLOBAL 0x900c + +#define S_MPS_GLOBAL_CGEN 0 +#define V_MPS_GLOBAL_CGEN(x) ((x) << S_MPS_GLOBAL_CGEN) +#define F_MPS_GLOBAL_CGEN V_MPS_GLOBAL_CGEN(1U) + #define A_MPS_INT_CAUSE 0x9008 #define S_STATINT 5 @@ -15200,6 +23638,11 @@ #define V_CH_MAP0(x) ((x) << S_CH_MAP0) #define G_CH_MAP0(x) (((x) >> S_CH_MAP0) & M_CH_MAP0) +#define S_FPGA_PTP_PORT 9 +#define M_FPGA_PTP_PORT 0x3U +#define V_FPGA_PTP_PORT(x) ((x) << S_FPGA_PTP_PORT) +#define G_FPGA_PTP_PORT(x) (((x) >> S_FPGA_PTP_PORT) & M_FPGA_PTP_PORT) + #define A_MPS_DEBUG_CTL 0x9068 #define S_DBGMODECTL_H 11 @@ -15224,16 +23667,11 @@ #define A_MPS_DEBUG_DATA_REG_H 0x9070 #define A_MPS_TOP_SPARE 0x9074 -#define S_TOPSPARE 12 -#define M_TOPSPARE 0xfffffU +#define S_TOPSPARE 8 +#define M_TOPSPARE 0xffffffU #define V_TOPSPARE(x) ((x) << S_TOPSPARE) #define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE) -#define S_CHIKN_14463 8 -#define M_CHIKN_14463 0xfU -#define V_CHIKN_14463(x) ((x) << S_CHIKN_14463) -#define G_CHIKN_14463(x) (((x) >> S_CHIKN_14463) & M_CHIKN_14463) - #define S_OVLANSELLPBK3 7 #define V_OVLANSELLPBK3(x) ((x) << S_OVLANSELLPBK3) #define F_OVLANSELLPBK3 V_OVLANSELLPBK3(1U) @@ -15265,7 +23703,44 @@ #define S_OVLANSELMAC0 0 #define V_OVLANSELMAC0(x) ((x) << S_OVLANSELMAC0) #define F_OVLANSELMAC0 V_OVLANSELMAC0(1U) - +#define S_T5_TOPSPARE 8 +#define M_T5_TOPSPARE 0xffffffU +#define V_T5_TOPSPARE(x) ((x) << S_T5_TOPSPARE) +#define G_T5_TOPSPARE(x) (((x) >> S_T5_TOPSPARE) & M_T5_TOPSPARE) + +#define A_MPS_T5_BUILD_REVISION 0x9078 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 0x908c +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 0x9090 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 0x9094 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 0x9098 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 0x909c +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 0x90a0 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 0x90a4 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 0x90a8 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 0x90ac +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 0x90b0 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 0x90b4 +#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 0x90b8 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 0x90bc +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 0x90c0 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 0x90c4 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 0x90c8 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 0x90cc +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 0x90d0 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 0x90d4 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 0x90d8 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 0x90dc +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 0x90e0 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 0x90e4 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 0x90e8 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 0x90ec +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 0x90f0 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4 +#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8 #define A_MPS_BUILD_REVISION 0x90fc #define A_MPS_TX_PRTY_SEL 0x9400 @@ -15378,6 +23853,15 @@ #define V_BUBBLECLR(x) ((x) << S_BUBBLECLR) #define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR) +#define S_NCSISECNT 20 +#define V_NCSISECNT(x) ((x) << S_NCSISECNT) +#define F_NCSISECNT V_NCSISECNT(1U) + +#define S_LPBKSECNT 16 +#define M_LPBKSECNT 0xfU +#define V_LPBKSECNT(x) ((x) << S_LPBKSECNT) +#define G_LPBKSECNT(x) (((x) >> S_LPBKSECNT) & M_LPBKSECNT) + #define A_MPS_TX_PORT_ERR 0x9430 #define S_LPBKPT3 7 @@ -15680,6 +24164,13 @@ #define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR) #define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR) +#define A_MPS_T5_TX_SGE_CH_PAUSE_IGNR 0x9454 + +#define S_T5SGEPAUSEIGNR 0 +#define M_T5SGEPAUSEIGNR 0xffffU +#define V_T5SGEPAUSEIGNR(x) ((x) << S_T5SGEPAUSEIGNR) +#define G_T5SGEPAUSEIGNR(x) (((x) >> S_T5SGEPAUSEIGNR) & M_T5SGEPAUSEIGNR) + #define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458 #define S_SUBPRTH 11 @@ -15702,6 +24193,182 @@ #define V_PORTL(x) ((x) << S_PORTL) #define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL) +#define A_MPS_TX_PAD_CTL 0x945c + +#define S_LPBKPADENPT3 7 +#define V_LPBKPADENPT3(x) ((x) << S_LPBKPADENPT3) +#define F_LPBKPADENPT3 V_LPBKPADENPT3(1U) + +#define S_LPBKPADENPT2 6 +#define V_LPBKPADENPT2(x) ((x) << S_LPBKPADENPT2) +#define F_LPBKPADENPT2 V_LPBKPADENPT2(1U) + +#define S_LPBKPADENPT1 5 +#define V_LPBKPADENPT1(x) ((x) << S_LPBKPADENPT1) +#define F_LPBKPADENPT1 V_LPBKPADENPT1(1U) + +#define S_LPBKPADENPT0 4 +#define V_LPBKPADENPT0(x) ((x) << S_LPBKPADENPT0) +#define F_LPBKPADENPT0 V_LPBKPADENPT0(1U) + +#define S_MACPADENPT3 3 +#define V_MACPADENPT3(x) ((x) << S_MACPADENPT3) +#define F_MACPADENPT3 V_MACPADENPT3(1U) + +#define S_MACPADENPT2 2 +#define V_MACPADENPT2(x) ((x) << S_MACPADENPT2) +#define F_MACPADENPT2 V_MACPADENPT2(1U) + +#define S_MACPADENPT1 1 +#define V_MACPADENPT1(x) ((x) << S_MACPADENPT1) +#define F_MACPADENPT1 V_MACPADENPT1(1U) + +#define S_MACPADENPT0 0 +#define V_MACPADENPT0(x) ((x) << S_MACPADENPT0) +#define F_MACPADENPT0 V_MACPADENPT0(1U) + +#define A_MPS_TX_PFVF_PORT_DROP_TP 0x9460 + +#define S_TP2MPS_CH3 24 +#define M_TP2MPS_CH3 0xffU +#define V_TP2MPS_CH3(x) ((x) << S_TP2MPS_CH3) +#define G_TP2MPS_CH3(x) (((x) >> S_TP2MPS_CH3) & M_TP2MPS_CH3) + +#define S_TP2MPS_CH2 16 +#define M_TP2MPS_CH2 0xffU +#define V_TP2MPS_CH2(x) ((x) << S_TP2MPS_CH2) +#define G_TP2MPS_CH2(x) (((x) >> S_TP2MPS_CH2) & M_TP2MPS_CH2) + +#define S_TP2MPS_CH1 8 +#define M_TP2MPS_CH1 0xffU +#define V_TP2MPS_CH1(x) ((x) << S_TP2MPS_CH1) +#define G_TP2MPS_CH1(x) (((x) >> S_TP2MPS_CH1) & M_TP2MPS_CH1) + +#define S_TP2MPS_CH0 0 +#define M_TP2MPS_CH0 0xffU +#define V_TP2MPS_CH0(x) ((x) << S_TP2MPS_CH0) +#define G_TP2MPS_CH0(x) (((x) >> S_TP2MPS_CH0) & M_TP2MPS_CH0) + +#define A_MPS_TX_PFVF_PORT_DROP_NCSI 0x9464 + +#define S_NCSI_CH4 0 +#define M_NCSI_CH4 0xffU +#define V_NCSI_CH4(x) ((x) << S_NCSI_CH4) +#define G_NCSI_CH4(x) (((x) >> S_NCSI_CH4) & M_NCSI_CH4) + +#define A_MPS_TX_PFVF_PORT_DROP_CTL 0x9468 + +#define S_PFNOVFDROP 5 +#define V_PFNOVFDROP(x) ((x) << S_PFNOVFDROP) +#define F_PFNOVFDROP V_PFNOVFDROP(1U) + +#define S_NCSI_CH4_CLR 4 +#define V_NCSI_CH4_CLR(x) ((x) << S_NCSI_CH4_CLR) +#define F_NCSI_CH4_CLR V_NCSI_CH4_CLR(1U) + +#define S_TP2MPS_CH3_CLR 3 +#define V_TP2MPS_CH3_CLR(x) ((x) << S_TP2MPS_CH3_CLR) +#define F_TP2MPS_CH3_CLR V_TP2MPS_CH3_CLR(1U) + +#define S_TP2MPS_CH2_CLR 2 +#define V_TP2MPS_CH2_CLR(x) ((x) << S_TP2MPS_CH2_CLR) +#define F_TP2MPS_CH2_CLR V_TP2MPS_CH2_CLR(1U) + +#define S_TP2MPS_CH1_CLR 1 +#define V_TP2MPS_CH1_CLR(x) ((x) << S_TP2MPS_CH1_CLR) +#define F_TP2MPS_CH1_CLR V_TP2MPS_CH1_CLR(1U) + +#define S_TP2MPS_CH0_CLR 0 +#define V_TP2MPS_CH0_CLR(x) ((x) << S_TP2MPS_CH0_CLR) +#define F_TP2MPS_CH0_CLR V_TP2MPS_CH0_CLR(1U) + +#define A_MPS_TX_CGEN 0x946c + +#define S_TXOUTLPBK3_CGEN 31 +#define V_TXOUTLPBK3_CGEN(x) ((x) << S_TXOUTLPBK3_CGEN) +#define F_TXOUTLPBK3_CGEN V_TXOUTLPBK3_CGEN(1U) + +#define S_TXOUTLPBK2_CGEN 30 +#define V_TXOUTLPBK2_CGEN(x) ((x) << S_TXOUTLPBK2_CGEN) +#define F_TXOUTLPBK2_CGEN V_TXOUTLPBK2_CGEN(1U) + +#define S_TXOUTLPBK1_CGEN 29 +#define V_TXOUTLPBK1_CGEN(x) ((x) << S_TXOUTLPBK1_CGEN) +#define F_TXOUTLPBK1_CGEN V_TXOUTLPBK1_CGEN(1U) + +#define S_TXOUTLPBK0_CGEN 28 +#define V_TXOUTLPBK0_CGEN(x) ((x) << S_TXOUTLPBK0_CGEN) +#define F_TXOUTLPBK0_CGEN V_TXOUTLPBK0_CGEN(1U) + +#define S_TXOUTMAC3_CGEN 27 +#define V_TXOUTMAC3_CGEN(x) ((x) << S_TXOUTMAC3_CGEN) +#define F_TXOUTMAC3_CGEN V_TXOUTMAC3_CGEN(1U) + +#define S_TXOUTMAC2_CGEN 26 +#define V_TXOUTMAC2_CGEN(x) ((x) << S_TXOUTMAC2_CGEN) +#define F_TXOUTMAC2_CGEN V_TXOUTMAC2_CGEN(1U) + +#define S_TXOUTMAC1_CGEN 25 +#define V_TXOUTMAC1_CGEN(x) ((x) << S_TXOUTMAC1_CGEN) +#define F_TXOUTMAC1_CGEN V_TXOUTMAC1_CGEN(1U) + +#define S_TXOUTMAC0_CGEN 24 +#define V_TXOUTMAC0_CGEN(x) ((x) << S_TXOUTMAC0_CGEN) +#define F_TXOUTMAC0_CGEN V_TXOUTMAC0_CGEN(1U) + +#define S_TXSCHLPBK3_CGEN 23 +#define V_TXSCHLPBK3_CGEN(x) ((x) << S_TXSCHLPBK3_CGEN) +#define F_TXSCHLPBK3_CGEN V_TXSCHLPBK3_CGEN(1U) + +#define S_TXSCHLPBK2_CGEN 22 +#define V_TXSCHLPBK2_CGEN(x) ((x) << S_TXSCHLPBK2_CGEN) +#define F_TXSCHLPBK2_CGEN V_TXSCHLPBK2_CGEN(1U) + +#define S_TXSCHLPBK1_CGEN 21 +#define V_TXSCHLPBK1_CGEN(x) ((x) << S_TXSCHLPBK1_CGEN) +#define F_TXSCHLPBK1_CGEN V_TXSCHLPBK1_CGEN(1U) + +#define S_TXSCHLPBK0_CGEN 20 +#define V_TXSCHLPBK0_CGEN(x) ((x) << S_TXSCHLPBK0_CGEN) +#define F_TXSCHLPBK0_CGEN V_TXSCHLPBK0_CGEN(1U) + +#define S_TXSCHMAC3_CGEN 19 +#define V_TXSCHMAC3_CGEN(x) ((x) << S_TXSCHMAC3_CGEN) +#define F_TXSCHMAC3_CGEN V_TXSCHMAC3_CGEN(1U) + +#define S_TXSCHMAC2_CGEN 18 +#define V_TXSCHMAC2_CGEN(x) ((x) << S_TXSCHMAC2_CGEN) +#define F_TXSCHMAC2_CGEN V_TXSCHMAC2_CGEN(1U) + +#define S_TXSCHMAC1_CGEN 17 +#define V_TXSCHMAC1_CGEN(x) ((x) << S_TXSCHMAC1_CGEN) +#define F_TXSCHMAC1_CGEN V_TXSCHMAC1_CGEN(1U) + +#define S_TXSCHMAC0_CGEN 16 +#define V_TXSCHMAC0_CGEN(x) ((x) << S_TXSCHMAC0_CGEN) +#define F_TXSCHMAC0_CGEN V_TXSCHMAC0_CGEN(1U) + +#define S_TXINCH4_CGEN 15 +#define V_TXINCH4_CGEN(x) ((x) << S_TXINCH4_CGEN) +#define F_TXINCH4_CGEN V_TXINCH4_CGEN(1U) + +#define S_TXINCH3_CGEN 14 +#define V_TXINCH3_CGEN(x) ((x) << S_TXINCH3_CGEN) +#define F_TXINCH3_CGEN V_TXINCH3_CGEN(1U) + +#define S_TXINCH2_CGEN 13 +#define V_TXINCH2_CGEN(x) ((x) << S_TXINCH2_CGEN) +#define F_TXINCH2_CGEN V_TXINCH2_CGEN(1U) + +#define S_TXINCH1_CGEN 12 +#define V_TXINCH1_CGEN(x) ((x) << S_TXINCH1_CGEN) +#define F_TXINCH1_CGEN V_TXINCH1_CGEN(1U) + +#define S_TXINCH0_CGEN 11 +#define V_TXINCH0_CGEN(x) ((x) << S_TXINCH0_CGEN) +#define F_TXINCH0_CGEN V_TXINCH0_CGEN(1U) + +#define A_MPS_TX_CGEN_DYNAMIC 0x9470 #define A_MPS_STAT_CTL 0x9600 #define S_COUNTVFINPF 1 @@ -15712,6 +24379,42 @@ #define V_LPBKERRSTAT(x) ((x) << S_LPBKERRSTAT) #define F_LPBKERRSTAT V_LPBKERRSTAT(1U) +#define S_STATSTOPCTRL 10 +#define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL) +#define F_STATSTOPCTRL V_STATSTOPCTRL(1U) + +#define S_STOPSTAT 9 +#define V_STOPSTAT(x) ((x) << S_STOPSTAT) +#define F_STOPSTAT V_STOPSTAT(1U) + +#define S_STATWRITECTRL 8 +#define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL) +#define F_STATWRITECTRL V_STATWRITECTRL(1U) + +#define S_COUNTLBPF 7 +#define V_COUNTLBPF(x) ((x) << S_COUNTLBPF) +#define F_COUNTLBPF V_COUNTLBPF(1U) + +#define S_COUNTLBVF 6 +#define V_COUNTLBVF(x) ((x) << S_COUNTLBVF) +#define F_COUNTLBVF V_COUNTLBVF(1U) + +#define S_COUNTPAUSEMCRX 5 +#define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX) +#define F_COUNTPAUSEMCRX V_COUNTPAUSEMCRX(1U) + +#define S_COUNTPAUSESTATRX 4 +#define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX) +#define F_COUNTPAUSESTATRX V_COUNTPAUSESTATRX(1U) + +#define S_COUNTPAUSEMCTX 3 +#define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX) +#define F_COUNTPAUSEMCTX V_COUNTPAUSEMCTX(1U) + +#define S_COUNTPAUSESTATTX 2 +#define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX) +#define F_COUNTPAUSESTATTX V_COUNTPAUSESTATTX(1U) + #define A_MPS_STAT_INT_ENABLE 0x9608 #define S_PLREADSYNCERR 0 @@ -15760,6 +24463,36 @@ #define V_TXPORT(x) ((x) << S_TXPORT) #define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT) +#define S_T5_RXBG 27 +#define M_T5_RXBG 0x3U +#define V_T5_RXBG(x) ((x) << S_T5_RXBG) +#define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG) + +#define S_T5_RXPF 22 +#define M_T5_RXPF 0x1fU +#define V_T5_RXPF(x) ((x) << S_T5_RXPF) +#define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF) + +#define S_T5_TXPF 18 +#define M_T5_TXPF 0xfU +#define V_T5_TXPF(x) ((x) << S_T5_TXPF) +#define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF) + +#define S_T5_RXPORT 11 +#define M_T5_RXPORT 0x7fU +#define V_T5_RXPORT(x) ((x) << S_T5_RXPORT) +#define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT) + +#define S_T5_LBPORT 6 +#define M_T5_LBPORT 0x1fU +#define V_T5_LBPORT(x) ((x) << S_T5_LBPORT) +#define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT) + +#define S_T5_TXPORT 0 +#define M_T5_TXPORT 0x3fU +#define V_T5_TXPORT(x) ((x) << S_T5_TXPORT) +#define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT) + #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 #define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618 #define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c @@ -15779,6 +24512,11 @@ #define V_DROP(x) ((x) << S_DROP) #define G_DROP(x) (((x) >> S_DROP) & M_DROP) +#define S_TXCH 20 +#define M_TXCH 0xfU +#define V_TXCH(x) ((x) << S_TXCH) +#define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH) + #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 #define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624 #define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628 @@ -15818,6 +24556,22 @@ #define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL) #define A_MPS_STAT_DEBUG_SUB_SEL 0x9638 + +#define S_STATSSUBPRTH 5 +#define M_STATSSUBPRTH 0x1fU +#define V_STATSSUBPRTH(x) ((x) << S_STATSSUBPRTH) +#define G_STATSSUBPRTH(x) (((x) >> S_STATSSUBPRTH) & M_STATSSUBPRTH) + +#define S_STATSSUBPRTL 0 +#define M_STATSSUBPRTL 0x1fU +#define V_STATSSUBPRTL(x) ((x) << S_STATSSUBPRTL) +#define G_STATSSUBPRTL(x) (((x) >> S_STATSSUBPRTL) & M_STATSSUBPRTL) + +#define S_STATSUBPRTH 5 +#define M_STATSUBPRTH 0x1fU +#define V_STATSUBPRTH(x) ((x) << S_STATSUBPRTH) +#define G_STATSUBPRTH(x) (((x) >> S_STATSUBPRTH) & M_STATSUBPRTH) + #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648 @@ -15850,6 +24604,65 @@ #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc +#define A_MPS_STAT_PERR_INT_ENABLE_SRAM1 0x96c0 + +#define S_T5_RXVF 5 +#define M_T5_RXVF 0x7U +#define V_T5_RXVF(x) ((x) << S_T5_RXVF) +#define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF) + +#define S_T5_TXVF 0 +#define M_T5_TXVF 0x1fU +#define V_T5_TXVF(x) ((x) << S_T5_TXVF) +#define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF) + +#define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4 +#define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8 +#define A_MPS_STAT_STOP_UPD_BG 0x96cc + +#define S_BGRX 0 +#define M_BGRX 0xfU +#define V_BGRX(x) ((x) << S_BGRX) +#define G_BGRX(x) (((x) >> S_BGRX) & M_BGRX) + +#define A_MPS_STAT_STOP_UPD_PORT 0x96d0 + +#define S_PTLPBK 8 +#define M_PTLPBK 0xfU +#define V_PTLPBK(x) ((x) << S_PTLPBK) +#define G_PTLPBK(x) (((x) >> S_PTLPBK) & M_PTLPBK) + +#define S_PTTX 4 +#define M_PTTX 0xfU +#define V_PTTX(x) ((x) << S_PTTX) +#define G_PTTX(x) (((x) >> S_PTTX) & M_PTTX) + +#define S_PTRX 0 +#define M_PTRX 0xfU +#define V_PTRX(x) ((x) << S_PTRX) +#define G_PTRX(x) (((x) >> S_PTRX) & M_PTRX) + +#define A_MPS_STAT_STOP_UPD_PF 0x96d4 + +#define S_PFTX 8 +#define M_PFTX 0xffU +#define V_PFTX(x) ((x) << S_PFTX) +#define G_PFTX(x) (((x) >> S_PFTX) & M_PFTX) + +#define S_PFRX 0 +#define M_PFRX 0xffU +#define V_PFRX(x) ((x) << S_PFRX) +#define G_PFRX(x) (((x) >> S_PFRX) & M_PFRX) + +#define A_MPS_STAT_STOP_UPD_TX_VF_0_31 0x96d8 +#define A_MPS_STAT_STOP_UPD_TX_VF_32_63 0x96dc +#define A_MPS_STAT_STOP_UPD_TX_VF_64_95 0x96e0 +#define A_MPS_STAT_STOP_UPD_TX_VF_96_127 0x96e4 +#define A_MPS_STAT_STOP_UPD_RX_VF_0_31 0x96e8 +#define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec +#define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0 +#define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4 + #define A_MPS_TRC_CFG 0x9800 #define S_TRCFIFOEMPTY 4 @@ -15872,7 +24685,12 @@ #define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER) #define F_TRCMULTIFILTER V_TRCMULTIFILTER(1U) +#define S_TRCMULTIRSSFILTER 5 +#define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER) +#define F_TRCMULTIRSSFILTER V_TRCMULTIRSSFILTER(1U) + #define A_MPS_TRC_RSS_HASH 0x9804 +#define A_MPS_TRC_FILTER0_RSS_HASH 0x9804 #define A_MPS_TRC_RSS_CONTROL 0x9808 #define S_RSSCONTROL 16 @@ -15885,6 +24703,7 @@ #define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER) #define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER) +#define A_MPS_TRC_FILTER0_RSS_CONTROL 0x9808 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810 #define S_TFINVERTMATCH 24 @@ -15922,6 +24741,31 @@ #define V_TFOFFSET(x) ((x) << S_TFOFFSET) #define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET) +#define S_TFINSERTACTLEN 27 +#define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN) +#define F_TFINSERTACTLEN V_TFINSERTACTLEN(1U) + +#define S_TFINSERTTIMER 26 +#define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER) +#define F_TFINSERTTIMER V_TFINSERTTIMER(1U) + +#define S_T5_TFINVERTMATCH 25 +#define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH) +#define F_T5_TFINVERTMATCH V_T5_TFINVERTMATCH(1U) + +#define S_T5_TFPKTTOOLARGE 24 +#define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE) +#define F_T5_TFPKTTOOLARGE V_T5_TFPKTTOOLARGE(1U) + +#define S_T5_TFEN 23 +#define V_T5_TFEN(x) ((x) << S_T5_TFEN) +#define F_T5_TFEN V_T5_TFEN(1U) + +#define S_T5_TFPORT 18 +#define M_T5_TFPORT 0x1fU +#define V_T5_TFPORT(x) ((x) << S_T5_TFPORT) +#define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT) + #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820 #define S_TFMINPKTSIZE 16 @@ -15994,6 +24838,64 @@ #define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80 #define A_MPS_TRC_FILTER3_MATCH 0x9f00 #define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80 +#define A_MPS_TRC_FILTER1_RSS_HASH 0x9ff0 +#define A_MPS_TRC_FILTER1_RSS_CONTROL 0x9ff4 +#define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8 +#define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc +#define A_MPS_TRC_FILTER3_RSS_HASH 0xa000 +#define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004 +#define A_MPS_T5_TRC_RSS_HASH 0xa008 +#define A_MPS_T5_TRC_RSS_CONTROL 0xa00c +#define A_MPS_TRC_VF_OFF_FILTER_0 0xa010 + +#define S_TRCMPS2TP_MACONLY 20 +#define V_TRCMPS2TP_MACONLY(x) ((x) << S_TRCMPS2TP_MACONLY) +#define F_TRCMPS2TP_MACONLY V_TRCMPS2TP_MACONLY(1U) + +#define S_TRCALLMPS2TP 19 +#define V_TRCALLMPS2TP(x) ((x) << S_TRCALLMPS2TP) +#define F_TRCALLMPS2TP V_TRCALLMPS2TP(1U) + +#define S_TRCALLTP2MPS 18 +#define V_TRCALLTP2MPS(x) ((x) << S_TRCALLTP2MPS) +#define F_TRCALLTP2MPS V_TRCALLTP2MPS(1U) + +#define S_TRCALLVF 17 +#define V_TRCALLVF(x) ((x) << S_TRCALLVF) +#define F_TRCALLVF V_TRCALLVF(1U) + +#define S_TRC_OFLD_EN 16 +#define V_TRC_OFLD_EN(x) ((x) << S_TRC_OFLD_EN) +#define F_TRC_OFLD_EN V_TRC_OFLD_EN(1U) + +#define S_VFFILTEN 15 +#define V_VFFILTEN(x) ((x) << S_VFFILTEN) +#define F_VFFILTEN V_VFFILTEN(1U) + +#define S_VFFILTMASK 8 +#define M_VFFILTMASK 0x7fU +#define V_VFFILTMASK(x) ((x) << S_VFFILTMASK) +#define G_VFFILTMASK(x) (((x) >> S_VFFILTMASK) & M_VFFILTMASK) + +#define S_VFFILTVALID 7 +#define V_VFFILTVALID(x) ((x) << S_VFFILTVALID) +#define F_VFFILTVALID V_VFFILTVALID(1U) + +#define S_VFFILTDATA 0 +#define M_VFFILTDATA 0x7fU +#define V_VFFILTDATA(x) ((x) << S_VFFILTDATA) +#define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA) + +#define A_MPS_TRC_VF_OFF_FILTER_1 0xa014 +#define A_MPS_TRC_VF_OFF_FILTER_2 0xa018 +#define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c +#define A_MPS_TRC_CGEN 0xa020 + +#define S_MPSTRCCGEN 0 +#define M_MPSTRCCGEN 0xfU +#define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN) +#define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN) + #define A_MPS_CLS_CTL 0xd000 #define S_MEMWRITEFAULT 4 @@ -16171,6 +25073,7 @@ #define V_SRAM_VLD(x) ((x) << S_SRAM_VLD) #define F_SRAM_VLD V_SRAM_VLD(1U) +#define A_MPS_T5_CLS_SRAM_L 0xe000 #define A_MPS_CLS_SRAM_H 0xe004 #define S_MACPARITY1 9 @@ -16192,6 +25095,7 @@ #define V_PORTMAP(x) ((x) << S_PORTMAP) #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP) +#define A_MPS_T5_CLS_SRAM_H 0xe004 #define A_MPS_CLS_TCAM_Y_L 0xf000 #define A_MPS_CLS_TCAM_Y_H 0xf004 @@ -16287,6 +25191,16 @@ #define V_ALLOC(x) ((x) << S_ALLOC) #define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC) +#define S_T5_USED 16 +#define M_T5_USED 0xfffU +#define V_T5_USED(x) ((x) << S_T5_USED) +#define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED) + +#define S_T5_ALLOC 0 +#define M_T5_ALLOC 0xfffU +#define V_T5_ALLOC(x) ((x) << S_T5_ALLOC) +#define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC) + #define A_MPS_RX_PG_RSV1 0x11014 #define A_MPS_RX_PG_RSV2 0x11018 #define A_MPS_RX_PG_RSV3 0x1101c @@ -16314,6 +25228,16 @@ #define V_BORW(x) ((x) << S_BORW) #define G_BORW(x) (((x) >> S_BORW) & M_BORW) +#define S_T5_MAX 16 +#define M_T5_MAX 0xfffU +#define V_T5_MAX(x) ((x) << S_T5_MAX) +#define G_T5_MAX(x) (((x) >> S_T5_MAX) & M_T5_MAX) + +#define S_T5_BORW 0 +#define M_T5_BORW 0xfffU +#define V_T5_BORW(x) ((x) << S_T5_BORW) +#define G_T5_BORW(x) (((x) >> S_T5_BORW) & M_T5_BORW) + #define A_MPS_RX_PG_SHR_BG1 0x11034 #define A_MPS_RX_PG_SHR_BG2 0x11038 #define A_MPS_RX_PG_SHR_BG3 0x1103c @@ -16329,6 +25253,16 @@ #define V_SHR_USED(x) ((x) << S_SHR_USED) #define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED) +#define S_T5_QUOTA 16 +#define M_T5_QUOTA 0xfffU +#define V_T5_QUOTA(x) ((x) << S_T5_QUOTA) +#define G_T5_QUOTA(x) (((x) >> S_T5_QUOTA) & M_T5_QUOTA) + +#define S_T5_SHR_USED 0 +#define M_T5_SHR_USED 0xfffU +#define V_T5_SHR_USED(x) ((x) << S_T5_SHR_USED) +#define G_T5_SHR_USED(x) (((x) >> S_T5_SHR_USED) & M_T5_SHR_USED) + #define A_MPS_RX_PG_SHR1 0x11044 #define A_MPS_RX_PG_HYST_BG0 0x11048 @@ -16337,6 +25271,11 @@ #define V_TH(x) ((x) << S_TH) #define G_TH(x) (((x) >> S_TH) & M_TH) +#define S_T5_TH 0 +#define M_T5_TH 0xfffU +#define V_T5_TH(x) ((x) << S_T5_TH) +#define G_T5_TH(x) (((x) >> S_T5_TH) & M_T5_TH) + #define A_MPS_RX_PG_HYST_BG1 0x1104c #define A_MPS_RX_PG_HYST_BG2 0x11050 #define A_MPS_RX_PG_HYST_BG3 0x11054 @@ -16362,11 +25301,6 @@ #define V_OCH_DROP(x) ((x) << S_OCH_DROP) #define G_OCH_DROP(x) (((x) >> S_OCH_DROP) & M_OCH_DROP) -#define S_STOP 0 -#define M_STOP_ 0x1fU -#define V_STOP(x) ((x) << S_STOP) -#define G_STOP(x) (((x) >> S_STOP) & M_STOP_) - #define A_MPS_RX_LPBK_BP0 0x1105c #define S_THRESH 0 @@ -16525,6 +25459,34 @@ #define V_PG_TH_INT0(x) ((x) << S_PG_TH_INT0) #define F_PG_TH_INT0 V_PG_TH_INT0(1U) +#define S_MTU_ERR_INT3 19 +#define V_MTU_ERR_INT3(x) ((x) << S_MTU_ERR_INT3) +#define F_MTU_ERR_INT3 V_MTU_ERR_INT3(1U) + +#define S_MTU_ERR_INT2 18 +#define V_MTU_ERR_INT2(x) ((x) << S_MTU_ERR_INT2) +#define F_MTU_ERR_INT2 V_MTU_ERR_INT2(1U) + +#define S_MTU_ERR_INT1 17 +#define V_MTU_ERR_INT1(x) ((x) << S_MTU_ERR_INT1) +#define F_MTU_ERR_INT1 V_MTU_ERR_INT1(1U) + +#define S_MTU_ERR_INT0 16 +#define V_MTU_ERR_INT0(x) ((x) << S_MTU_ERR_INT0) +#define F_MTU_ERR_INT0 V_MTU_ERR_INT0(1U) + +#define S_SE_CNT_ERR_INT 15 +#define V_SE_CNT_ERR_INT(x) ((x) << S_SE_CNT_ERR_INT) +#define F_SE_CNT_ERR_INT V_SE_CNT_ERR_INT(1U) + +#define S_FRM_ERR_INT 14 +#define V_FRM_ERR_INT(x) ((x) << S_FRM_ERR_INT) +#define F_FRM_ERR_INT V_FRM_ERR_INT(1U) + +#define S_LEN_ERR_INT 13 +#define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT) +#define F_LEN_ERR_INT V_LEN_ERR_INT(1U) + #define A_MPS_RX_FUNC_INT_ENABLE 0x11088 #define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c @@ -16882,6 +25844,125 @@ #define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3) #define A_MPS_RX_SPARE 0x11190 +#define A_MPS_RX_PTP_ETYPE 0x11194 + +#define S_PETYPE2 16 +#define M_PETYPE2 0xffffU +#define V_PETYPE2(x) ((x) << S_PETYPE2) +#define G_PETYPE2(x) (((x) >> S_PETYPE2) & M_PETYPE2) + +#define S_PETYPE1 0 +#define M_PETYPE1 0xffffU +#define V_PETYPE1(x) ((x) << S_PETYPE1) +#define G_PETYPE1(x) (((x) >> S_PETYPE1) & M_PETYPE1) + +#define A_MPS_RX_PTP_TCP 0x11198 + +#define S_PTCPORT2 16 +#define M_PTCPORT2 0xffffU +#define V_PTCPORT2(x) ((x) << S_PTCPORT2) +#define G_PTCPORT2(x) (((x) >> S_PTCPORT2) & M_PTCPORT2) + +#define S_PTCPORT1 0 +#define M_PTCPORT1 0xffffU +#define V_PTCPORT1(x) ((x) << S_PTCPORT1) +#define G_PTCPORT1(x) (((x) >> S_PTCPORT1) & M_PTCPORT1) + +#define A_MPS_RX_PTP_UDP 0x1119c + +#define S_PUDPORT2 16 +#define M_PUDPORT2 0xffffU +#define V_PUDPORT2(x) ((x) << S_PUDPORT2) +#define G_PUDPORT2(x) (((x) >> S_PUDPORT2) & M_PUDPORT2) + +#define S_PUDPORT1 0 +#define M_PUDPORT1 0xffffU +#define V_PUDPORT1(x) ((x) << S_PUDPORT1) +#define G_PUDPORT1(x) (((x) >> S_PUDPORT1) & M_PUDPORT1) + +#define A_MPS_RX_PTP_CTL 0x111a0 + +#define S_MIN_PTP_SPACE 24 +#define M_MIN_PTP_SPACE 0x7fU +#define V_MIN_PTP_SPACE(x) ((x) << S_MIN_PTP_SPACE) +#define G_MIN_PTP_SPACE(x) (((x) >> S_MIN_PTP_SPACE) & M_MIN_PTP_SPACE) + +#define S_PUDP2EN 20 +#define M_PUDP2EN 0xfU +#define V_PUDP2EN(x) ((x) << S_PUDP2EN) +#define G_PUDP2EN(x) (((x) >> S_PUDP2EN) & M_PUDP2EN) + +#define S_PUDP1EN 16 +#define M_PUDP1EN 0xfU +#define V_PUDP1EN(x) ((x) << S_PUDP1EN) +#define G_PUDP1EN(x) (((x) >> S_PUDP1EN) & M_PUDP1EN) + +#define S_PTCP2EN 12 +#define M_PTCP2EN 0xfU +#define V_PTCP2EN(x) ((x) << S_PTCP2EN) +#define G_PTCP2EN(x) (((x) >> S_PTCP2EN) & M_PTCP2EN) + +#define S_PTCP1EN 8 +#define M_PTCP1EN 0xfU +#define V_PTCP1EN(x) ((x) << S_PTCP1EN) +#define G_PTCP1EN(x) (((x) >> S_PTCP1EN) & M_PTCP1EN) + +#define S_PETYPE2EN 4 +#define M_PETYPE2EN 0xfU +#define V_PETYPE2EN(x) ((x) << S_PETYPE2EN) +#define G_PETYPE2EN(x) (((x) >> S_PETYPE2EN) & M_PETYPE2EN) + +#define S_PETYPE1EN 0 +#define M_PETYPE1EN 0xfU +#define V_PETYPE1EN(x) ((x) << S_PETYPE1EN) +#define G_PETYPE1EN(x) (((x) >> S_PETYPE1EN) & M_PETYPE1EN) + +#define A_MPS_RX_PAUSE_GEN_TH_0_0 0x111a4 +#define A_MPS_RX_PAUSE_GEN_TH_0_1 0x111a8 +#define A_MPS_RX_PAUSE_GEN_TH_0_2 0x111ac +#define A_MPS_RX_PAUSE_GEN_TH_0_3 0x111b0 +#define A_MPS_RX_PAUSE_GEN_TH_1_0 0x111b4 +#define A_MPS_RX_PAUSE_GEN_TH_1_1 0x111b8 +#define A_MPS_RX_PAUSE_GEN_TH_1_2 0x111bc +#define A_MPS_RX_PAUSE_GEN_TH_1_3 0x111c0 +#define A_MPS_RX_PAUSE_GEN_TH_2_0 0x111c4 +#define A_MPS_RX_PAUSE_GEN_TH_2_1 0x111c8 +#define A_MPS_RX_PAUSE_GEN_TH_2_2 0x111cc +#define A_MPS_RX_PAUSE_GEN_TH_2_3 0x111d0 +#define A_MPS_RX_PAUSE_GEN_TH_3_0 0x111d4 +#define A_MPS_RX_PAUSE_GEN_TH_3_1 0x111d8 +#define A_MPS_RX_PAUSE_GEN_TH_3_2 0x111dc +#define A_MPS_RX_PAUSE_GEN_TH_3_3 0x111e0 +#define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4 +#define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8 +#define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec +#define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0 +#define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4 +#define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8 +#define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc +#define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200 +#define A_MPS_RX_CGEN 0x11204 + +#define S_MPS_RX_CGEN_NCSI 12 +#define V_MPS_RX_CGEN_NCSI(x) ((x) << S_MPS_RX_CGEN_NCSI) +#define F_MPS_RX_CGEN_NCSI V_MPS_RX_CGEN_NCSI(1U) + +#define S_MPS_RX_CGEN_OUT 8 +#define M_MPS_RX_CGEN_OUT 0xfU +#define V_MPS_RX_CGEN_OUT(x) ((x) << S_MPS_RX_CGEN_OUT) +#define G_MPS_RX_CGEN_OUT(x) (((x) >> S_MPS_RX_CGEN_OUT) & M_MPS_RX_CGEN_OUT) + +#define S_MPS_RX_CGEN_LPBK_IN 4 +#define M_MPS_RX_CGEN_LPBK_IN 0xfU +#define V_MPS_RX_CGEN_LPBK_IN(x) ((x) << S_MPS_RX_CGEN_LPBK_IN) +#define G_MPS_RX_CGEN_LPBK_IN(x) \ + (((x) >> S_MPS_RX_CGEN_LPBK_IN) & M_MPS_RX_CGEN_LPBK_IN) + +#define S_MPS_RX_CGEN_MAC_IN 0 +#define M_MPS_RX_CGEN_MAC_IN 0xfU +#define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN) +#define G_MPS_RX_CGEN_MAC_IN(x) \ + (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN) /* registers for module CPL_SWITCH */ #define CPL_SWITCH_BASE_ADDR 0x19040 @@ -16917,6 +25998,10 @@ #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE) #define F_CIM_ENABLE V_CIM_ENABLE(1U) +#define S_CIM_SPLIT_ENABLE 6 +#define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE) +#define F_CIM_SPLIT_ENABLE V_CIM_SPLIT_ENABLE(1U) + #define A_CPL_SWITCH_TBL_IDX 0x19044 #define S_SWITCH_TBL_IDX 0 @@ -16963,6 +26048,14 @@ #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR) #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U) +#define S_PERR_CPL_128TO128_1 7 +#define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1) +#define F_PERR_CPL_128TO128_1 V_PERR_CPL_128TO128_1(1U) + +#define S_PERR_CPL_128TO128_0 6 +#define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0) +#define F_PERR_CPL_128TO128_0 V_PERR_CPL_128TO128_0(1U) + #define A_CPL_INTR_CAUSE 0x19054 #define A_CPL_MAP_TBL_IDX 0x19058 @@ -16971,6 +26064,10 @@ #define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX) #define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX) +#define S_CIM_SPLIT_OPCODE_PROGRAM 8 +#define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM) +#define F_CIM_SPLIT_OPCODE_PROGRAM V_CIM_SPLIT_OPCODE_PROGRAM(1U) + #define A_CPL_MAP_TBL_DATA 0x1905c #define S_MAP_TBL_DATA 0 @@ -17324,6 +26421,18 @@ #define V_SLVFIFOPERREN(x) ((x) << S_SLVFIFOPERREN) #define F_SLVFIFOPERREN V_SLVFIFOPERREN(1U) +#define S_MSTTXFIFO 21 +#define V_MSTTXFIFO(x) ((x) << S_MSTTXFIFO) +#define F_MSTTXFIFO V_MSTTXFIFO(1U) + +#define S_MSTRXFIFO 19 +#define V_MSTRXFIFO(x) ((x) << S_MSTRXFIFO) +#define F_MSTRXFIFO V_MSTRXFIFO(1U) + +#define S_SLVFIFO 18 +#define V_SLVFIFO(x) ((x) << S_SLVFIFO) +#define F_SLVFIFO V_SLVFIFO(1U) + #define A_SMB_PERR_INJ 0x1909c #define S_MSTTXINJDATAERR 3 @@ -17521,6 +26630,20 @@ #define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG) #define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG) +#define A_SMB_CTL_STATUS 0x190e8 + +#define S_MSTBUSBUSY 2 +#define V_MSTBUSBUSY(x) ((x) << S_MSTBUSBUSY) +#define F_MSTBUSBUSY V_MSTBUSBUSY(1U) + +#define S_SLVBUSBUSY 1 +#define V_SLVBUSBUSY(x) ((x) << S_SLVBUSBUSY) +#define F_SLVBUSBUSY V_SLVBUSBUSY(1U) + +#define S_BUSBUSY 0 +#define V_BUSBUSY(x) ((x) << S_BUSBUSY) +#define F_BUSBUSY V_BUSBUSY(1U) + /* registers for module I2CM */ #define I2CM_BASE_ADDR 0x190f0 @@ -17531,6 +26654,11 @@ #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV) #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV) +#define S_I2C_CLKDIV16B 0 +#define M_I2C_CLKDIV16B 0xffffU +#define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B) +#define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B) + #define A_I2CM_DATA 0x190f4 #define S_I2C_DATA 0 @@ -17676,6 +26804,46 @@ #define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE) #define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE) +#define S_SGE_PART_CGEN 19 +#define V_SGE_PART_CGEN(x) ((x) << S_SGE_PART_CGEN) +#define F_SGE_PART_CGEN V_SGE_PART_CGEN(1U) + +#define S_PDP_PART_CGEN 18 +#define V_PDP_PART_CGEN(x) ((x) << S_PDP_PART_CGEN) +#define F_PDP_PART_CGEN V_PDP_PART_CGEN(1U) + +#define S_TP_PART_CGEN 17 +#define V_TP_PART_CGEN(x) ((x) << S_TP_PART_CGEN) +#define F_TP_PART_CGEN V_TP_PART_CGEN(1U) + +#define S_EDC0_PART_CGEN 16 +#define V_EDC0_PART_CGEN(x) ((x) << S_EDC0_PART_CGEN) +#define F_EDC0_PART_CGEN V_EDC0_PART_CGEN(1U) + +#define S_EDC1_PART_CGEN 15 +#define V_EDC1_PART_CGEN(x) ((x) << S_EDC1_PART_CGEN) +#define F_EDC1_PART_CGEN V_EDC1_PART_CGEN(1U) + +#define S_LE_PART_CGEN 14 +#define V_LE_PART_CGEN(x) ((x) << S_LE_PART_CGEN) +#define F_LE_PART_CGEN V_LE_PART_CGEN(1U) + +#define S_MA_PART_CGEN 13 +#define V_MA_PART_CGEN(x) ((x) << S_MA_PART_CGEN) +#define F_MA_PART_CGEN V_MA_PART_CGEN(1U) + +#define S_MC0_PART_CGEN 12 +#define V_MC0_PART_CGEN(x) ((x) << S_MC0_PART_CGEN) +#define F_MC0_PART_CGEN V_MC0_PART_CGEN(1U) + +#define S_MC1_PART_CGEN 11 +#define V_MC1_PART_CGEN(x) ((x) << S_MC1_PART_CGEN) +#define F_MC1_PART_CGEN V_MC1_PART_CGEN(1U) + +#define S_PCIE_PART_CGEN 10 +#define V_PCIE_PART_CGEN(x) ((x) << S_PCIE_PART_CGEN) +#define F_PCIE_PART_CGEN V_PCIE_PART_CGEN(1U) + #define A_PMU_SLEEPMODE_WAKEUP 0x19124 #define S_HWWAKEUPEN 5 @@ -17702,6 +26870,10 @@ #define V_WAKEUP(x) ((x) << S_WAKEUP) #define F_WAKEUP V_WAKEUP(1U) +#define S_GLOBALDEEPSLEEPEN 6 +#define V_GLOBALDEEPSLEEPEN(x) ((x) << S_GLOBALDEEPSLEEPEN) +#define F_GLOBALDEEPSLEEPEN V_GLOBALDEEPSLEEPEN(1U) + /* registers for module ULP_RX */ #define ULP_RX_BASE_ADDR 0x19150 @@ -17797,78 +26969,86 @@ #define V_ENABLE_AF_0(x) ((x) << S_ENABLE_AF_0) #define F_ENABLE_AF_0 V_ENABLE_AF_0(1U) -#define S_ENABLE_PCMDF_1 17 -#define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1) -#define F_ENABLE_PCMDF_1 V_ENABLE_PCMDF_1(1U) +#define S_ENABLE_DDPDF_1 17 +#define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1) +#define F_ENABLE_DDPDF_1 V_ENABLE_DDPDF_1(1U) -#define S_ENABLE_MPARC_1 16 -#define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1) -#define F_ENABLE_MPARC_1 V_ENABLE_MPARC_1(1U) +#define S_ENABLE_DDPMF_1 16 +#define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1) +#define F_ENABLE_DDPMF_1 V_ENABLE_DDPMF_1(1U) -#define S_ENABLE_MPARF_1 15 -#define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1) -#define F_ENABLE_MPARF_1 V_ENABLE_MPARF_1(1U) +#define S_ENABLE_MEMRF_1 15 +#define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1) +#define F_ENABLE_MEMRF_1 V_ENABLE_MEMRF_1(1U) -#define S_ENABLE_DDPCF_1 14 -#define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1) -#define F_ENABLE_DDPCF_1 V_ENABLE_DDPCF_1(1U) +#define S_ENABLE_PRSDF_1 14 +#define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1) +#define F_ENABLE_PRSDF_1 V_ENABLE_PRSDF_1(1U) -#define S_ENABLE_TPTCF_1 13 -#define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1) -#define F_ENABLE_TPTCF_1 V_ENABLE_TPTCF_1(1U) +#define S_ENABLE_DDPDF_0 13 +#define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0) +#define F_ENABLE_DDPDF_0 V_ENABLE_DDPDF_0(1U) -#define S_ENABLE_PCMDF_0 12 -#define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0) -#define F_ENABLE_PCMDF_0 V_ENABLE_PCMDF_0(1U) +#define S_ENABLE_DDPMF_0 12 +#define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0) +#define F_ENABLE_DDPMF_0 V_ENABLE_DDPMF_0(1U) -#define S_ENABLE_MPARC_0 11 -#define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0) -#define F_ENABLE_MPARC_0 V_ENABLE_MPARC_0(1U) +#define S_ENABLE_MEMRF_0 11 +#define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0) +#define F_ENABLE_MEMRF_0 V_ENABLE_MEMRF_0(1U) -#define S_ENABLE_MPARF_0 10 -#define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0) -#define F_ENABLE_MPARF_0 V_ENABLE_MPARF_0(1U) +#define S_ENABLE_PRSDF_0 10 +#define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0) +#define F_ENABLE_PRSDF_0 V_ENABLE_PRSDF_0(1U) -#define S_ENABLE_DDPCF_0 9 -#define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0) -#define F_ENABLE_DDPCF_0 V_ENABLE_DDPCF_0(1U) +#define S_ENABLE_PCMDF_1 9 +#define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1) +#define F_ENABLE_PCMDF_1 V_ENABLE_PCMDF_1(1U) -#define S_ENABLE_TPTCF_0 8 -#define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0) -#define F_ENABLE_TPTCF_0 V_ENABLE_TPTCF_0(1U) +#define S_ENABLE_TPTCF_1 8 +#define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1) +#define F_ENABLE_TPTCF_1 V_ENABLE_TPTCF_1(1U) -#define S_ENABLE_DDPDF_1 7 -#define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1) -#define F_ENABLE_DDPDF_1 V_ENABLE_DDPDF_1(1U) +#define S_ENABLE_DDPCF_1 7 +#define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1) +#define F_ENABLE_DDPCF_1 V_ENABLE_DDPCF_1(1U) -#define S_ENABLE_DDPMF_1 6 -#define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1) -#define F_ENABLE_DDPMF_1 V_ENABLE_DDPMF_1(1U) +#define S_ENABLE_MPARF_1 6 +#define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1) +#define F_ENABLE_MPARF_1 V_ENABLE_MPARF_1(1U) -#define S_ENABLE_MEMRF_1 5 -#define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1) -#define F_ENABLE_MEMRF_1 V_ENABLE_MEMRF_1(1U) +#define S_ENABLE_MPARC_1 5 +#define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1) +#define F_ENABLE_MPARC_1 V_ENABLE_MPARC_1(1U) -#define S_ENABLE_PRSDF_1 4 -#define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1) -#define F_ENABLE_PRSDF_1 V_ENABLE_PRSDF_1(1U) +#define S_ENABLE_PCMDF_0 4 +#define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0) +#define F_ENABLE_PCMDF_0 V_ENABLE_PCMDF_0(1U) + +#define S_ENABLE_TPTCF_0 3 +#define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0) +#define F_ENABLE_TPTCF_0 V_ENABLE_TPTCF_0(1U) -#define S_ENABLE_DDPDF_0 3 -#define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0) -#define F_ENABLE_DDPDF_0 V_ENABLE_DDPDF_0(1U) +#define S_ENABLE_DDPCF_0 2 +#define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0) +#define F_ENABLE_DDPCF_0 V_ENABLE_DDPCF_0(1U) -#define S_ENABLE_DDPMF_0 2 -#define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0) -#define F_ENABLE_DDPMF_0 V_ENABLE_DDPMF_0(1U) +#define S_ENABLE_MPARF_0 1 +#define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0) +#define F_ENABLE_MPARF_0 V_ENABLE_MPARF_0(1U) -#define S_ENABLE_MEMRF_0 1 -#define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0) -#define F_ENABLE_MEMRF_0 V_ENABLE_MEMRF_0(1U) +#define S_ENABLE_MPARC_0 0 +#define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0) +#define F_ENABLE_MPARC_0 V_ENABLE_MPARC_0(1U) -#define S_ENABLE_PRSDF_0 0 -#define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0) -#define F_ENABLE_PRSDF_0 V_ENABLE_PRSDF_0(1U) +#define S_SE_CNT_MISMATCH_1 26 +#define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1) +#define F_SE_CNT_MISMATCH_1 V_SE_CNT_MISMATCH_1(1U) +#define S_SE_CNT_MISMATCH_0 25 +#define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0) +#define F_SE_CNT_MISMATCH_0 V_SE_CNT_MISMATCH_0(1U) + #define A_ULP_RX_INT_CAUSE 0x19158 #define S_CAUSE_CTX_1 24 @@ -17899,77 +27079,77 @@ #define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0) #define F_CAUSE_AF_0 V_CAUSE_AF_0(1U) -#define S_CAUSE_PCMDF_1 17 -#define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1) -#define F_CAUSE_PCMDF_1 V_CAUSE_PCMDF_1(1U) +#define S_CAUSE_DDPDF_1 17 +#define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1) +#define F_CAUSE_DDPDF_1 V_CAUSE_DDPDF_1(1U) -#define S_CAUSE_MPARC_1 16 -#define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1) -#define F_CAUSE_MPARC_1 V_CAUSE_MPARC_1(1U) +#define S_CAUSE_DDPMF_1 16 +#define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1) +#define F_CAUSE_DDPMF_1 V_CAUSE_DDPMF_1(1U) -#define S_CAUSE_MPARF_1 15 -#define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1) -#define F_CAUSE_MPARF_1 V_CAUSE_MPARF_1(1U) +#define S_CAUSE_MEMRF_1 15 +#define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1) +#define F_CAUSE_MEMRF_1 V_CAUSE_MEMRF_1(1U) -#define S_CAUSE_DDPCF_1 14 -#define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1) -#define F_CAUSE_DDPCF_1 V_CAUSE_DDPCF_1(1U) +#define S_CAUSE_PRSDF_1 14 +#define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1) +#define F_CAUSE_PRSDF_1 V_CAUSE_PRSDF_1(1U) -#define S_CAUSE_TPTCF_1 13 -#define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1) -#define F_CAUSE_TPTCF_1 V_CAUSE_TPTCF_1(1U) +#define S_CAUSE_DDPDF_0 13 +#define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0) +#define F_CAUSE_DDPDF_0 V_CAUSE_DDPDF_0(1U) -#define S_CAUSE_PCMDF_0 12 -#define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0) -#define F_CAUSE_PCMDF_0 V_CAUSE_PCMDF_0(1U) +#define S_CAUSE_DDPMF_0 12 +#define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0) +#define F_CAUSE_DDPMF_0 V_CAUSE_DDPMF_0(1U) -#define S_CAUSE_MPARC_0 11 -#define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0) -#define F_CAUSE_MPARC_0 V_CAUSE_MPARC_0(1U) +#define S_CAUSE_MEMRF_0 11 +#define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0) +#define F_CAUSE_MEMRF_0 V_CAUSE_MEMRF_0(1U) -#define S_CAUSE_MPARF_0 10 -#define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0) -#define F_CAUSE_MPARF_0 V_CAUSE_MPARF_0(1U) +#define S_CAUSE_PRSDF_0 10 +#define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0) +#define F_CAUSE_PRSDF_0 V_CAUSE_PRSDF_0(1U) -#define S_CAUSE_DDPCF_0 9 -#define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0) -#define F_CAUSE_DDPCF_0 V_CAUSE_DDPCF_0(1U) +#define S_CAUSE_PCMDF_1 9 +#define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1) +#define F_CAUSE_PCMDF_1 V_CAUSE_PCMDF_1(1U) -#define S_CAUSE_TPTCF_0 8 -#define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0) -#define F_CAUSE_TPTCF_0 V_CAUSE_TPTCF_0(1U) +#define S_CAUSE_TPTCF_1 8 +#define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1) +#define F_CAUSE_TPTCF_1 V_CAUSE_TPTCF_1(1U) -#define S_CAUSE_DDPDF_1 7 -#define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1) -#define F_CAUSE_DDPDF_1 V_CAUSE_DDPDF_1(1U) +#define S_CAUSE_DDPCF_1 7 +#define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1) +#define F_CAUSE_DDPCF_1 V_CAUSE_DDPCF_1(1U) -#define S_CAUSE_DDPMF_1 6 -#define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1) -#define F_CAUSE_DDPMF_1 V_CAUSE_DDPMF_1(1U) +#define S_CAUSE_MPARF_1 6 +#define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1) +#define F_CAUSE_MPARF_1 V_CAUSE_MPARF_1(1U) -#define S_CAUSE_MEMRF_1 5 -#define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1) -#define F_CAUSE_MEMRF_1 V_CAUSE_MEMRF_1(1U) +#define S_CAUSE_MPARC_1 5 +#define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1) +#define F_CAUSE_MPARC_1 V_CAUSE_MPARC_1(1U) -#define S_CAUSE_PRSDF_1 4 -#define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1) -#define F_CAUSE_PRSDF_1 V_CAUSE_PRSDF_1(1U) +#define S_CAUSE_PCMDF_0 4 +#define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0) +#define F_CAUSE_PCMDF_0 V_CAUSE_PCMDF_0(1U) -#define S_CAUSE_DDPDF_0 3 -#define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0) -#define F_CAUSE_DDPDF_0 V_CAUSE_DDPDF_0(1U) +#define S_CAUSE_TPTCF_0 3 +#define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0) +#define F_CAUSE_TPTCF_0 V_CAUSE_TPTCF_0(1U) -#define S_CAUSE_DDPMF_0 2 -#define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0) -#define F_CAUSE_DDPMF_0 V_CAUSE_DDPMF_0(1U) +#define S_CAUSE_DDPCF_0 2 +#define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0) +#define F_CAUSE_DDPCF_0 V_CAUSE_DDPCF_0(1U) -#define S_CAUSE_MEMRF_0 1 -#define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0) -#define F_CAUSE_MEMRF_0 V_CAUSE_MEMRF_0(1U) +#define S_CAUSE_MPARF_0 1 +#define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0) +#define F_CAUSE_MPARF_0 V_CAUSE_MPARF_0(1U) -#define S_CAUSE_PRSDF_0 0 -#define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0) -#define F_CAUSE_PRSDF_0 V_CAUSE_PRSDF_0(1U) +#define S_CAUSE_MPARC_0 0 +#define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0) +#define F_CAUSE_MPARC_0 V_CAUSE_MPARC_0(1U) #define A_ULP_RX_ISCSI_LLIMIT 0x1915c @@ -18044,6 +27224,115 @@ #define A_ULP_RX_PBL_ULIMIT 0x19190 #define A_ULP_RX_CTX_BASE 0x19194 #define A_ULP_RX_PERR_ENABLE 0x1919c + +#define S_PERR_ENABLE_FF 22 +#define V_PERR_ENABLE_FF(x) ((x) << S_PERR_ENABLE_FF) +#define F_PERR_ENABLE_FF V_PERR_ENABLE_FF(1U) + +#define S_PERR_ENABLE_APF_1 21 +#define V_PERR_ENABLE_APF_1(x) ((x) << S_PERR_ENABLE_APF_1) +#define F_PERR_ENABLE_APF_1 V_PERR_ENABLE_APF_1(1U) + +#define S_PERR_ENABLE_APF_0 20 +#define V_PERR_ENABLE_APF_0(x) ((x) << S_PERR_ENABLE_APF_0) +#define F_PERR_ENABLE_APF_0 V_PERR_ENABLE_APF_0(1U) + +#define S_PERR_ENABLE_AF_1 19 +#define V_PERR_ENABLE_AF_1(x) ((x) << S_PERR_ENABLE_AF_1) +#define F_PERR_ENABLE_AF_1 V_PERR_ENABLE_AF_1(1U) + +#define S_PERR_ENABLE_AF_0 18 +#define V_PERR_ENABLE_AF_0(x) ((x) << S_PERR_ENABLE_AF_0) +#define F_PERR_ENABLE_AF_0 V_PERR_ENABLE_AF_0(1U) + +#define S_PERR_ENABLE_DDPDF_1 17 +#define V_PERR_ENABLE_DDPDF_1(x) ((x) << S_PERR_ENABLE_DDPDF_1) +#define F_PERR_ENABLE_DDPDF_1 V_PERR_ENABLE_DDPDF_1(1U) + +#define S_PERR_ENABLE_DDPMF_1 16 +#define V_PERR_ENABLE_DDPMF_1(x) ((x) << S_PERR_ENABLE_DDPMF_1) +#define F_PERR_ENABLE_DDPMF_1 V_PERR_ENABLE_DDPMF_1(1U) + +#define S_PERR_ENABLE_MEMRF_1 15 +#define V_PERR_ENABLE_MEMRF_1(x) ((x) << S_PERR_ENABLE_MEMRF_1) +#define F_PERR_ENABLE_MEMRF_1 V_PERR_ENABLE_MEMRF_1(1U) + +#define S_PERR_ENABLE_PRSDF_1 14 +#define V_PERR_ENABLE_PRSDF_1(x) ((x) << S_PERR_ENABLE_PRSDF_1) +#define F_PERR_ENABLE_PRSDF_1 V_PERR_ENABLE_PRSDF_1(1U) + +#define S_PERR_ENABLE_DDPDF_0 13 +#define V_PERR_ENABLE_DDPDF_0(x) ((x) << S_PERR_ENABLE_DDPDF_0) +#define F_PERR_ENABLE_DDPDF_0 V_PERR_ENABLE_DDPDF_0(1U) + +#define S_PERR_ENABLE_DDPMF_0 12 +#define V_PERR_ENABLE_DDPMF_0(x) ((x) << S_PERR_ENABLE_DDPMF_0) +#define F_PERR_ENABLE_DDPMF_0 V_PERR_ENABLE_DDPMF_0(1U) + +#define S_PERR_ENABLE_MEMRF_0 11 +#define V_PERR_ENABLE_MEMRF_0(x) ((x) << S_PERR_ENABLE_MEMRF_0) +#define F_PERR_ENABLE_MEMRF_0 V_PERR_ENABLE_MEMRF_0(1U) + +#define S_PERR_ENABLE_PRSDF_0 10 +#define V_PERR_ENABLE_PRSDF_0(x) ((x) << S_PERR_ENABLE_PRSDF_0) +#define F_PERR_ENABLE_PRSDF_0 V_PERR_ENABLE_PRSDF_0(1U) + +#define S_PERR_ENABLE_PCMDF_1 9 +#define V_PERR_ENABLE_PCMDF_1(x) ((x) << S_PERR_ENABLE_PCMDF_1) +#define F_PERR_ENABLE_PCMDF_1 V_PERR_ENABLE_PCMDF_1(1U) + +#define S_PERR_ENABLE_TPTCF_1 8 +#define V_PERR_ENABLE_TPTCF_1(x) ((x) << S_PERR_ENABLE_TPTCF_1) +#define F_PERR_ENABLE_TPTCF_1 V_PERR_ENABLE_TPTCF_1(1U) + +#define S_PERR_ENABLE_DDPCF_1 7 +#define V_PERR_ENABLE_DDPCF_1(x) ((x) << S_PERR_ENABLE_DDPCF_1) +#define F_PERR_ENABLE_DDPCF_1 V_PERR_ENABLE_DDPCF_1(1U) + +#define S_PERR_ENABLE_MPARF_1 6 +#define V_PERR_ENABLE_MPARF_1(x) ((x) << S_PERR_ENABLE_MPARF_1) +#define F_PERR_ENABLE_MPARF_1 V_PERR_ENABLE_MPARF_1(1U) + +#define S_PERR_ENABLE_MPARC_1 5 +#define V_PERR_ENABLE_MPARC_1(x) ((x) << S_PERR_ENABLE_MPARC_1) +#define F_PERR_ENABLE_MPARC_1 V_PERR_ENABLE_MPARC_1(1U) + +#define S_PERR_ENABLE_PCMDF_0 4 +#define V_PERR_ENABLE_PCMDF_0(x) ((x) << S_PERR_ENABLE_PCMDF_0) +#define F_PERR_ENABLE_PCMDF_0 V_PERR_ENABLE_PCMDF_0(1U) + +#define S_PERR_ENABLE_TPTCF_0 3 +#define V_PERR_ENABLE_TPTCF_0(x) ((x) << S_PERR_ENABLE_TPTCF_0) +#define F_PERR_ENABLE_TPTCF_0 V_PERR_ENABLE_TPTCF_0(1U) + +#define S_PERR_ENABLE_DDPCF_0 2 +#define V_PERR_ENABLE_DDPCF_0(x) ((x) << S_PERR_ENABLE_DDPCF_0) +#define F_PERR_ENABLE_DDPCF_0 V_PERR_ENABLE_DDPCF_0(1U) + +#define S_PERR_ENABLE_MPARF_0 1 +#define V_PERR_ENABLE_MPARF_0(x) ((x) << S_PERR_ENABLE_MPARF_0) +#define F_PERR_ENABLE_MPARF_0 V_PERR_ENABLE_MPARF_0(1U) + +#define S_PERR_ENABLE_MPARC_0 0 +#define V_PERR_ENABLE_MPARC_0(x) ((x) << S_PERR_ENABLE_MPARC_0) +#define F_PERR_ENABLE_MPARC_0 V_PERR_ENABLE_MPARC_0(1U) + +#define S_PERR_SE_CNT_MISMATCH_1 26 +#define V_PERR_SE_CNT_MISMATCH_1(x) ((x) << S_PERR_SE_CNT_MISMATCH_1) +#define F_PERR_SE_CNT_MISMATCH_1 V_PERR_SE_CNT_MISMATCH_1(1U) + +#define S_PERR_SE_CNT_MISMATCH_0 25 +#define V_PERR_SE_CNT_MISMATCH_0(x) ((x) << S_PERR_SE_CNT_MISMATCH_0) +#define F_PERR_SE_CNT_MISMATCH_0 V_PERR_SE_CNT_MISMATCH_0(1U) + +#define S_PERR_RSVD0 24 +#define V_PERR_RSVD0(x) ((x) << S_PERR_RSVD0) +#define F_PERR_RSVD0 V_PERR_RSVD0(1U) + +#define S_PERR_RSVD1 23 +#define V_PERR_RSVD1(x) ((x) << S_PERR_RSVD1) +#define F_PERR_RSVD1 V_PERR_RSVD1(1U) + #define A_ULP_RX_PERR_INJECT 0x191a0 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8 @@ -18210,6 +27499,266 @@ #define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR) #define A_ULP_RX_LA_RESERVED 0x1924c +#define A_ULP_RX_CQE_GEN_EN 0x19250 + +#define S_TERMIMATE_MSG 1 +#define V_TERMIMATE_MSG(x) ((x) << S_TERMIMATE_MSG) +#define F_TERMIMATE_MSG V_TERMIMATE_MSG(1U) + +#define S_TERMINATE_WITH_ERR 0 +#define V_TERMINATE_WITH_ERR(x) ((x) << S_TERMINATE_WITH_ERR) +#define F_TERMINATE_WITH_ERR V_TERMINATE_WITH_ERR(1U) + +#define A_ULP_RX_ATOMIC_OPCODES 0x19254 + +#define S_ATOMIC_REQ_QNO 22 +#define M_ATOMIC_REQ_QNO 0x3U +#define V_ATOMIC_REQ_QNO(x) ((x) << S_ATOMIC_REQ_QNO) +#define G_ATOMIC_REQ_QNO(x) (((x) >> S_ATOMIC_REQ_QNO) & M_ATOMIC_REQ_QNO) + +#define S_ATOMIC_RSP_QNO 20 +#define M_ATOMIC_RSP_QNO 0x3U +#define V_ATOMIC_RSP_QNO(x) ((x) << S_ATOMIC_RSP_QNO) +#define G_ATOMIC_RSP_QNO(x) (((x) >> S_ATOMIC_RSP_QNO) & M_ATOMIC_RSP_QNO) + +#define S_IMMEDIATE_QNO 18 +#define M_IMMEDIATE_QNO 0x3U +#define V_IMMEDIATE_QNO(x) ((x) << S_IMMEDIATE_QNO) +#define G_IMMEDIATE_QNO(x) (((x) >> S_IMMEDIATE_QNO) & M_IMMEDIATE_QNO) + +#define S_IMMEDIATE_WITH_SE_QNO 16 +#define M_IMMEDIATE_WITH_SE_QNO 0x3U +#define V_IMMEDIATE_WITH_SE_QNO(x) ((x) << S_IMMEDIATE_WITH_SE_QNO) +#define G_IMMEDIATE_WITH_SE_QNO(x) \ + (((x) >> S_IMMEDIATE_WITH_SE_QNO) & M_IMMEDIATE_WITH_SE_QNO) + +#define S_ATOMIC_WR_OPCODE 12 +#define M_ATOMIC_WR_OPCODE 0xfU +#define V_ATOMIC_WR_OPCODE(x) ((x) << S_ATOMIC_WR_OPCODE) +#define G_ATOMIC_WR_OPCODE(x) (((x) >> S_ATOMIC_WR_OPCODE) & M_ATOMIC_WR_OPCODE) + +#define S_ATOMIC_RD_OPCODE 8 +#define M_ATOMIC_RD_OPCODE 0xfU +#define V_ATOMIC_RD_OPCODE(x) ((x) << S_ATOMIC_RD_OPCODE) +#define G_ATOMIC_RD_OPCODE(x) (((x) >> S_ATOMIC_RD_OPCODE) & M_ATOMIC_RD_OPCODE) + +#define S_IMMEDIATE_OPCODE 4 +#define M_IMMEDIATE_OPCODE 0xfU +#define V_IMMEDIATE_OPCODE(x) ((x) << S_IMMEDIATE_OPCODE) +#define G_IMMEDIATE_OPCODE(x) (((x) >> S_IMMEDIATE_OPCODE) & M_IMMEDIATE_OPCODE) + +#define S_IMMEDIATE_WITH_SE_OPCODE 0 +#define M_IMMEDIATE_WITH_SE_OPCODE 0xfU +#define V_IMMEDIATE_WITH_SE_OPCODE(x) ((x) << S_IMMEDIATE_WITH_SE_OPCODE) +#define G_IMMEDIATE_WITH_SE_OPCODE(x) \ + (((x) >> S_IMMEDIATE_WITH_SE_OPCODE) & M_IMMEDIATE_WITH_SE_OPCODE) + +#define A_ULP_RX_T10_CRC_ENDIAN_SWITCHING 0x19258 + +#define S_EN_ORIG_DATA 0 +#define V_EN_ORIG_DATA(x) ((x) << S_EN_ORIG_DATA) +#define F_EN_ORIG_DATA V_EN_ORIG_DATA(1U) + +#define A_ULP_RX_MISC_FEATURE_ENABLE 0x1925c + +#define S_TERMINATE_STATUS_EN 4 +#define V_TERMINATE_STATUS_EN(x) ((x) << S_TERMINATE_STATUS_EN) +#define F_TERMINATE_STATUS_EN V_TERMINATE_STATUS_EN(1U) + +#define S_MULTIPLE_PREF_ENABLE 3 +#define V_MULTIPLE_PREF_ENABLE(x) ((x) << S_MULTIPLE_PREF_ENABLE) +#define F_MULTIPLE_PREF_ENABLE V_MULTIPLE_PREF_ENABLE(1U) + +#define S_UMUDP_PBL_PREF_ENABLE 2 +#define V_UMUDP_PBL_PREF_ENABLE(x) ((x) << S_UMUDP_PBL_PREF_ENABLE) +#define F_UMUDP_PBL_PREF_ENABLE V_UMUDP_PBL_PREF_ENABLE(1U) + +#define S_RDMA_PBL_PREF_EN 1 +#define V_RDMA_PBL_PREF_EN(x) ((x) << S_RDMA_PBL_PREF_EN) +#define F_RDMA_PBL_PREF_EN V_RDMA_PBL_PREF_EN(1U) + +#define S_SDC_CRC_PROT_EN 0 +#define V_SDC_CRC_PROT_EN(x) ((x) << S_SDC_CRC_PROT_EN) +#define F_SDC_CRC_PROT_EN V_SDC_CRC_PROT_EN(1U) + +#define A_ULP_RX_CH0_CGEN 0x19260 + +#define S_BYPASS_CGEN 7 +#define V_BYPASS_CGEN(x) ((x) << S_BYPASS_CGEN) +#define F_BYPASS_CGEN V_BYPASS_CGEN(1U) + +#define S_TDDP_CGEN 6 +#define V_TDDP_CGEN(x) ((x) << S_TDDP_CGEN) +#define F_TDDP_CGEN V_TDDP_CGEN(1U) + +#define S_ISCSI_CGEN 5 +#define V_ISCSI_CGEN(x) ((x) << S_ISCSI_CGEN) +#define F_ISCSI_CGEN V_ISCSI_CGEN(1U) + +#define S_RDMA_CGEN 4 +#define V_RDMA_CGEN(x) ((x) << S_RDMA_CGEN) +#define F_RDMA_CGEN V_RDMA_CGEN(1U) + +#define S_CHANNEL_CGEN 3 +#define V_CHANNEL_CGEN(x) ((x) << S_CHANNEL_CGEN) +#define F_CHANNEL_CGEN V_CHANNEL_CGEN(1U) + +#define S_ALL_DATAPATH_CGEN 2 +#define V_ALL_DATAPATH_CGEN(x) ((x) << S_ALL_DATAPATH_CGEN) +#define F_ALL_DATAPATH_CGEN V_ALL_DATAPATH_CGEN(1U) + +#define S_T10DIFF_DATAPATH_CGEN 1 +#define V_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T10DIFF_DATAPATH_CGEN) +#define F_T10DIFF_DATAPATH_CGEN V_T10DIFF_DATAPATH_CGEN(1U) + +#define S_RDMA_DATAPATH_CGEN 0 +#define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN) +#define F_RDMA_DATAPATH_CGEN V_RDMA_DATAPATH_CGEN(1U) + +#define A_ULP_RX_CH1_CGEN 0x19264 +#define A_ULP_RX_RFE_DISABLE 0x19268 + +#define S_RQE_LIM_CHECK_RFE_DISABLE 0 +#define V_RQE_LIM_CHECK_RFE_DISABLE(x) ((x) << S_RQE_LIM_CHECK_RFE_DISABLE) +#define F_RQE_LIM_CHECK_RFE_DISABLE V_RQE_LIM_CHECK_RFE_DISABLE(1U) + +#define A_ULP_RX_INT_ENABLE_2 0x1926c + +#define S_ULPRX2MA_INTFPERR 8 +#define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR) +#define F_ULPRX2MA_INTFPERR V_ULPRX2MA_INTFPERR(1U) + +#define S_ALN_SDC_ERR_1 7 +#define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1) +#define F_ALN_SDC_ERR_1 V_ALN_SDC_ERR_1(1U) + +#define S_ALN_SDC_ERR_0 6 +#define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0) +#define F_ALN_SDC_ERR_0 V_ALN_SDC_ERR_0(1U) + +#define S_PF_UNTAGGED_TPT_1 5 +#define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1) +#define F_PF_UNTAGGED_TPT_1 V_PF_UNTAGGED_TPT_1(1U) + +#define S_PF_UNTAGGED_TPT_0 4 +#define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0) +#define F_PF_UNTAGGED_TPT_0 V_PF_UNTAGGED_TPT_0(1U) + +#define S_PF_PBL_1 3 +#define V_PF_PBL_1(x) ((x) << S_PF_PBL_1) +#define F_PF_PBL_1 V_PF_PBL_1(1U) + +#define S_PF_PBL_0 2 +#define V_PF_PBL_0(x) ((x) << S_PF_PBL_0) +#define F_PF_PBL_0 V_PF_PBL_0(1U) + +#define S_DDP_HINT_1 1 +#define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1) +#define F_DDP_HINT_1 V_DDP_HINT_1(1U) + +#define S_DDP_HINT_0 0 +#define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0) +#define F_DDP_HINT_0 V_DDP_HINT_0(1U) + +#define A_ULP_RX_INT_CAUSE_2 0x19270 +#define A_ULP_RX_PERR_ENABLE_2 0x19274 + +#define S_ENABLE_ULPRX2MA_INTFPERR 8 +#define V_ENABLE_ULPRX2MA_INTFPERR(x) ((x) << S_ENABLE_ULPRX2MA_INTFPERR) +#define F_ENABLE_ULPRX2MA_INTFPERR V_ENABLE_ULPRX2MA_INTFPERR(1U) + +#define S_ENABLE_ALN_SDC_ERR_1 7 +#define V_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_ENABLE_ALN_SDC_ERR_1) +#define F_ENABLE_ALN_SDC_ERR_1 V_ENABLE_ALN_SDC_ERR_1(1U) + +#define S_ENABLE_ALN_SDC_ERR_0 6 +#define V_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_ENABLE_ALN_SDC_ERR_0) +#define F_ENABLE_ALN_SDC_ERR_0 V_ENABLE_ALN_SDC_ERR_0(1U) + +#define S_ENABLE_PF_UNTAGGED_TPT_1 5 +#define V_ENABLE_PF_UNTAGGED_TPT_1(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_1) +#define F_ENABLE_PF_UNTAGGED_TPT_1 V_ENABLE_PF_UNTAGGED_TPT_1(1U) + +#define S_ENABLE_PF_UNTAGGED_TPT_0 4 +#define V_ENABLE_PF_UNTAGGED_TPT_0(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_0) +#define F_ENABLE_PF_UNTAGGED_TPT_0 V_ENABLE_PF_UNTAGGED_TPT_0(1U) + +#define S_ENABLE_PF_PBL_1 3 +#define V_ENABLE_PF_PBL_1(x) ((x) << S_ENABLE_PF_PBL_1) +#define F_ENABLE_PF_PBL_1 V_ENABLE_PF_PBL_1(1U) + +#define S_ENABLE_PF_PBL_0 2 +#define V_ENABLE_PF_PBL_0(x) ((x) << S_ENABLE_PF_PBL_0) +#define F_ENABLE_PF_PBL_0 V_ENABLE_PF_PBL_0(1U) + +#define S_ENABLE_DDP_HINT_1 1 +#define V_ENABLE_DDP_HINT_1(x) ((x) << S_ENABLE_DDP_HINT_1) +#define F_ENABLE_DDP_HINT_1 V_ENABLE_DDP_HINT_1(1U) + +#define S_ENABLE_DDP_HINT_0 0 +#define V_ENABLE_DDP_HINT_0(x) ((x) << S_ENABLE_DDP_HINT_0) +#define F_ENABLE_DDP_HINT_0 V_ENABLE_DDP_HINT_0(1U) + +#define A_ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT 0x19278 + +#define S_PIO_RQE_PBL_MULTIPLE_CNT 0 +#define M_PIO_RQE_PBL_MULTIPLE_CNT 0xfU +#define V_PIO_RQE_PBL_MULTIPLE_CNT(x) ((x) << S_PIO_RQE_PBL_MULTIPLE_CNT) +#define G_PIO_RQE_PBL_MULTIPLE_CNT(x) \ + (((x) >> S_PIO_RQE_PBL_MULTIPLE_CNT) & M_PIO_RQE_PBL_MULTIPLE_CNT) + +#define A_ULP_RX_ATOMIC_LEN 0x1927c + +#define S_ATOMIC_RPL_LEN 16 +#define M_ATOMIC_RPL_LEN 0xffU +#define V_ATOMIC_RPL_LEN(x) ((x) << S_ATOMIC_RPL_LEN) +#define G_ATOMIC_RPL_LEN(x) (((x) >> S_ATOMIC_RPL_LEN) & M_ATOMIC_RPL_LEN) + +#define S_ATOMIC_REQ_LEN 8 +#define M_ATOMIC_REQ_LEN 0xffU +#define V_ATOMIC_REQ_LEN(x) ((x) << S_ATOMIC_REQ_LEN) +#define G_ATOMIC_REQ_LEN(x) (((x) >> S_ATOMIC_REQ_LEN) & M_ATOMIC_REQ_LEN) + +#define S_ATOMIC_IMMEDIATE_LEN 0 +#define M_ATOMIC_IMMEDIATE_LEN 0xffU +#define V_ATOMIC_IMMEDIATE_LEN(x) ((x) << S_ATOMIC_IMMEDIATE_LEN) +#define G_ATOMIC_IMMEDIATE_LEN(x) \ + (((x) >> S_ATOMIC_IMMEDIATE_LEN) & M_ATOMIC_IMMEDIATE_LEN) + +#define A_ULP_RX_CGEN_GLOBAL 0x19280 +#define A_ULP_RX_CTX_SKIP_MA_REQ 0x19284 + +#define S_CLEAR_CTX_ERR_CNT1 3 +#define V_CLEAR_CTX_ERR_CNT1(x) ((x) << S_CLEAR_CTX_ERR_CNT1) +#define F_CLEAR_CTX_ERR_CNT1 V_CLEAR_CTX_ERR_CNT1(1U) + +#define S_CLEAR_CTX_ERR_CNT0 2 +#define V_CLEAR_CTX_ERR_CNT0(x) ((x) << S_CLEAR_CTX_ERR_CNT0) +#define F_CLEAR_CTX_ERR_CNT0 V_CLEAR_CTX_ERR_CNT0(1U) + +#define S_SKIP_MA_REQ_EN1 1 +#define V_SKIP_MA_REQ_EN1(x) ((x) << S_SKIP_MA_REQ_EN1) +#define F_SKIP_MA_REQ_EN1 V_SKIP_MA_REQ_EN1(1U) + +#define S_SKIP_MA_REQ_EN0 0 +#define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0) +#define F_SKIP_MA_REQ_EN0 V_SKIP_MA_REQ_EN0(1U) + +#define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288 +#define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c +#define A_ULP_RX_MSN_CHECK_ENABLE 0x19290 + +#define S_RD_OR_TERM_MSN_CHECK_ENABLE 2 +#define V_RD_OR_TERM_MSN_CHECK_ENABLE(x) ((x) << S_RD_OR_TERM_MSN_CHECK_ENABLE) +#define F_RD_OR_TERM_MSN_CHECK_ENABLE V_RD_OR_TERM_MSN_CHECK_ENABLE(1U) + +#define S_ATOMIC_OP_MSN_CHECK_ENABLE 1 +#define V_ATOMIC_OP_MSN_CHECK_ENABLE(x) ((x) << S_ATOMIC_OP_MSN_CHECK_ENABLE) +#define F_ATOMIC_OP_MSN_CHECK_ENABLE V_ATOMIC_OP_MSN_CHECK_ENABLE(1U) + +#define S_SEND_MSN_CHECK_ENABLE 0 +#define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE) +#define F_SEND_MSN_CHECK_ENABLE V_SEND_MSN_CHECK_ENABLE(1U) /* registers for module SF */ #define SF_BASE_ADDR 0x193f8 @@ -18259,6 +27808,14 @@ #define V_VFID(x) ((x) << S_VFID) #define G_VFID(x) (((x) >> S_VFID) & M_VFID) +#define A_PL_VF_REV 0x4 + +#define S_CHIPID 4 +#define M_CHIPID 0xfU +#define V_CHIPID(x) ((x) << S_CHIPID) +#define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID) + +#define A_PL_VF_REVISION 0x8 #define A_PL_PF_INT_CAUSE 0x3c0 #define S_PFSW 3 @@ -18403,6 +27960,18 @@ #define V_CIM(x) ((x) << S_CIM) #define F_CIM V_CIM(1U) +#define S_MC1 31 +#define V_MC1(x) ((x) << S_MC1) +#define F_MC1 V_MC1(1U) + +#define S_MC0 15 +#define V_MC0(x) ((x) << S_MC0) +#define F_MC0 V_MC0(1U) + +#define S_ANYMAC 9 +#define V_ANYMAC(x) ((x) << S_ANYMAC) +#define F_ANYMAC V_ANYMAC(1U) + #define A_PL_PERR_ENABLE 0x19408 #define A_PL_INT_CAUSE 0x1940c @@ -18414,6 +27983,22 @@ #define V_SW_CIM(x) ((x) << S_SW_CIM) #define F_SW_CIM V_SW_CIM(1U) +#define S_MAC3 12 +#define V_MAC3(x) ((x) << S_MAC3) +#define F_MAC3 V_MAC3(1U) + +#define S_MAC2 11 +#define V_MAC2(x) ((x) << S_MAC2) +#define F_MAC2 V_MAC2(1U) + +#define S_MAC1 10 +#define V_MAC1(x) ((x) << S_MAC1) +#define F_MAC1 V_MAC1(1U) + +#define S_MAC0 9 +#define V_MAC0(x) ((x) << S_MAC0) +#define F_MAC0 V_MAC0(1U) + #define A_PL_INT_ENABLE 0x19410 #define A_PL_INT_MAP0 0x19414 @@ -18439,6 +28024,16 @@ #define V_MAPXGMAC0(x) ((x) << S_MAPXGMAC0) #define G_MAPXGMAC0(x) (((x) >> S_MAPXGMAC0) & M_MAPXGMAC0) +#define S_MAPMAC1 16 +#define M_MAPMAC1 0x1ffU +#define V_MAPMAC1(x) ((x) << S_MAPMAC1) +#define G_MAPMAC1(x) (((x) >> S_MAPMAC1) & M_MAPMAC1) + +#define S_MAPMAC0 0 +#define M_MAPMAC0 0x1ffU +#define V_MAPMAC0(x) ((x) << S_MAPMAC0) +#define G_MAPMAC0(x) (((x) >> S_MAPMAC0) & M_MAPMAC0) + #define A_PL_INT_MAP2 0x1941c #define S_MAPXGMAC_KR1 16 @@ -18451,6 +28046,16 @@ #define V_MAPXGMAC_KR0(x) ((x) << S_MAPXGMAC_KR0) #define G_MAPXGMAC_KR0(x) (((x) >> S_MAPXGMAC_KR0) & M_MAPXGMAC_KR0) +#define S_MAPMAC3 16 +#define M_MAPMAC3 0x1ffU +#define V_MAPMAC3(x) ((x) << S_MAPMAC3) +#define G_MAPMAC3(x) (((x) >> S_MAPMAC3) & M_MAPMAC3) + +#define S_MAPMAC2 0 +#define M_MAPMAC2 0x1ffU +#define V_MAPMAC2(x) ((x) << S_MAPMAC2) +#define G_MAPMAC2(x) (((x) >> S_MAPMAC2) & M_MAPMAC2) + #define A_PL_INT_MAP3 0x19420 #define S_MAPMI 16 @@ -18493,6 +28098,10 @@ #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE) #define F_PIORSTMODE V_PIORSTMODE(1U) +#define S_AUTOPCIEPAUSE 4 +#define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE) +#define F_AUTOPCIEPAUSE V_AUTOPCIEPAUSE(1U) + #define A_PL_PL_PERR_INJECT 0x1942c #define S_PL_MEMSEL 1 @@ -18525,6 +28134,10 @@ #define V_PERRVFID(x) ((x) << S_PERRVFID) #define F_PERRVFID V_PERRVFID(1U) +#define S_PL_BUSPERR 6 +#define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR) +#define F_PL_BUSPERR V_PL_BUSPERR(1U) + #define A_PL_PL_INT_ENABLE 0x19434 #define A_PL_PL_PERR_ENABLE 0x19438 #define A_PL_REV 0x1943c @@ -18534,6 +28147,40 @@ #define V_REV(x) ((x) << S_REV) #define G_REV(x) (((x) >> S_REV) & M_REV) +#define A_PL_PCIE_LINK 0x19440 + +#define S_LN0_AESTAT 26 +#define M_LN0_AESTAT 0x7U +#define V_LN0_AESTAT(x) ((x) << S_LN0_AESTAT) +#define G_LN0_AESTAT(x) (((x) >> S_LN0_AESTAT) & M_LN0_AESTAT) + +#define S_LN0_AECMD 23 +#define M_LN0_AECMD 0x7U +#define V_LN0_AECMD(x) ((x) << S_LN0_AECMD) +#define G_LN0_AECMD(x) (((x) >> S_LN0_AECMD) & M_LN0_AECMD) + +#define S_PCIE_SPEED 8 +#define M_PCIE_SPEED 0x3U +#define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED) +#define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED) + +#define S_LTSSM 0 +#define M_LTSSM 0x3fU +#define V_LTSSM(x) ((x) << S_LTSSM) +#define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM) + +#define A_PL_PCIE_CTL_STAT 0x19444 + +#define S_PCIE_STATUS 16 +#define M_PCIE_STATUS 0xffffU +#define V_PCIE_STATUS(x) ((x) << S_PCIE_STATUS) +#define G_PCIE_STATUS(x) (((x) >> S_PCIE_STATUS) & M_PCIE_STATUS) + +#define S_PCIE_CONTROL 0 +#define M_PCIE_CONTROL 0xffffU +#define V_PCIE_CONTROL(x) ((x) << S_PCIE_CONTROL) +#define G_PCIE_CONTROL(x) (((x) >> S_PCIE_CONTROL) & M_PCIE_CONTROL) + #define A_PL_SEMAPHORE_CTL 0x1944c #define S_LOCKSTATUS 16 @@ -18654,6 +28301,10 @@ #define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT) #define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT) +#define S_PERRCAPTURE 16 +#define V_PERRCAPTURE(x) ((x) << S_PERRCAPTURE) +#define F_PERRCAPTURE V_PERRCAPTURE(1U) + #define A_PL_TIMEOUT_STATUS0 0x194f4 #define S_PL_TOADDR 2 @@ -18690,6 +28341,15 @@ #define V_PL_TORID(x) ((x) << S_PL_TORID) #define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID) +#define S_VALIDPERR 30 +#define V_VALIDPERR(x) ((x) << S_VALIDPERR) +#define F_VALIDPERR V_VALIDPERR(1U) + +#define S_PL_TOVFID 0 +#define M_PL_TOVFID 0xffU +#define V_PL_TOVFID(x) ((x) << S_PL_TOVFID) +#define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID) + #define A_PL_VFID_MAP 0x19800 #define S_VFID_VLD 7 @@ -18755,6 +28415,58 @@ #define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS) #define F_CMDOVERLAPDIS V_CMDOVERLAPDIS(1U) +#define S_MASKCMDOLAPDIS 26 +#define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS) +#define F_MASKCMDOLAPDIS V_MASKCMDOLAPDIS(1U) + +#define S_IPV4HASHSIZEEN 25 +#define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN) +#define F_IPV4HASHSIZEEN V_IPV4HASHSIZEEN(1U) + +#define S_PROTOCOLMASKEN 24 +#define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN) +#define F_PROTOCOLMASKEN V_PROTOCOLMASKEN(1U) + +#define S_TUPLESIZEEN 23 +#define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN) +#define F_TUPLESIZEEN V_TUPLESIZEEN(1U) + +#define S_SRVRSRAMEN 22 +#define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN) +#define F_SRVRSRAMEN V_SRVRSRAMEN(1U) + +#define S_ASBOTHSRCHENPR 19 +#define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR) +#define F_ASBOTHSRCHENPR V_ASBOTHSRCHENPR(1U) + +#define S_POCLIPTID0 15 +#define V_POCLIPTID0(x) ((x) << S_POCLIPTID0) +#define F_POCLIPTID0 V_POCLIPTID0(1U) + +#define S_TCAMARBOFF 14 +#define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF) +#define F_TCAMARBOFF V_TCAMARBOFF(1U) + +#define S_ACCNTFULLEN 13 +#define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN) +#define F_ACCNTFULLEN V_ACCNTFULLEN(1U) + +#define S_FILTERRWNOCLIP 12 +#define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP) +#define F_FILTERRWNOCLIP V_FILTERRWNOCLIP(1U) + +#define S_CRCHASH 10 +#define V_CRCHASH(x) ((x) << S_CRCHASH) +#define F_CRCHASH V_CRCHASH(1U) + +#define S_COMPTID 9 +#define V_COMPTID(x) ((x) << S_COMPTID) +#define F_COMPTID V_COMPTID(1U) + +#define S_SINGLETHREAD 6 +#define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD) +#define F_SINGLETHREAD V_SINGLETHREAD(1U) + #define A_LE_MISC 0x19c08 #define S_CMPUNVAIL 0 @@ -18762,6 +28474,38 @@ #define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL) #define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL) +#define S_SRAMDEEPSLEEP_STAT 11 +#define V_SRAMDEEPSLEEP_STAT(x) ((x) << S_SRAMDEEPSLEEP_STAT) +#define F_SRAMDEEPSLEEP_STAT V_SRAMDEEPSLEEP_STAT(1U) + +#define S_TCAMDEEPSLEEP1_STAT 10 +#define V_TCAMDEEPSLEEP1_STAT(x) ((x) << S_TCAMDEEPSLEEP1_STAT) +#define F_TCAMDEEPSLEEP1_STAT V_TCAMDEEPSLEEP1_STAT(1U) + +#define S_TCAMDEEPSLEEP0_STAT 9 +#define V_TCAMDEEPSLEEP0_STAT(x) ((x) << S_TCAMDEEPSLEEP0_STAT) +#define F_TCAMDEEPSLEEP0_STAT V_TCAMDEEPSLEEP0_STAT(1U) + +#define S_SRAMDEEPSLEEP 8 +#define V_SRAMDEEPSLEEP(x) ((x) << S_SRAMDEEPSLEEP) +#define F_SRAMDEEPSLEEP V_SRAMDEEPSLEEP(1U) + +#define S_TCAMDEEPSLEEP1 7 +#define V_TCAMDEEPSLEEP1(x) ((x) << S_TCAMDEEPSLEEP1) +#define F_TCAMDEEPSLEEP1 V_TCAMDEEPSLEEP1(1U) + +#define S_TCAMDEEPSLEEP0 6 +#define V_TCAMDEEPSLEEP0(x) ((x) << S_TCAMDEEPSLEEP0) +#define F_TCAMDEEPSLEEP0 V_TCAMDEEPSLEEP0(1U) + +#define S_SRVRAMCLKOFF 5 +#define V_SRVRAMCLKOFF(x) ((x) << S_SRVRAMCLKOFF) +#define F_SRVRAMCLKOFF V_SRVRAMCLKOFF(1U) + +#define S_HASHCLKOFF 4 +#define V_HASHCLKOFF(x) ((x) << S_HASHCLKOFF) +#define F_HASHCLKOFF V_HASHCLKOFF(1U) + #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10 #define S_RTINDX 7 @@ -18890,6 +28634,30 @@ #define V_SERVERHIT(x) ((x) << S_SERVERHIT) #define F_SERVERHIT V_SERVERHIT(1U) +#define S_ACTCNTIPV6TZERO 21 +#define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO) +#define F_ACTCNTIPV6TZERO V_ACTCNTIPV6TZERO(1U) + +#define S_ACTCNTIPV4TZERO 20 +#define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO) +#define F_ACTCNTIPV4TZERO V_ACTCNTIPV4TZERO(1U) + +#define S_ACTCNTIPV6ZERO 19 +#define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO) +#define F_ACTCNTIPV6ZERO V_ACTCNTIPV6ZERO(1U) + +#define S_ACTCNTIPV4ZERO 18 +#define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO) +#define F_ACTCNTIPV4ZERO V_ACTCNTIPV4ZERO(1U) + +#define S_MARSPPARERR 17 +#define V_MARSPPARERR(x) ((x) << S_MARSPPARERR) +#define F_MARSPPARERR V_MARSPPARERR(1U) + +#define S_VFPARERR 14 +#define V_VFPARERR(x) ((x) << S_VFPARERR) +#define F_VFPARERR V_VFPARERR(1U) + #define A_LE_DB_INT_CAUSE 0x19c3c #define A_LE_DB_INT_TID 0x19c40 @@ -18920,8 +28688,29 @@ #define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD) #define A_LE_DB_MASK_IPV4 0x19c50 +#define A_LE_T5_DB_MASK_IPV4 0x19c50 +#define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94 +#define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98 +#define A_LE_ACT_CNT_THRSH 0x19c9c + +#define S_ACT_CNT_THRSH 0 +#define M_ACT_CNT_THRSH 0x1fffffU +#define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH) +#define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH) + #define A_LE_DB_MASK_IPV6 0x19ca0 #define A_LE_DB_REQ_RSP_CNT 0x19ce4 + +#define S_RSPCNTLE 16 +#define M_RSPCNTLE 0xffffU +#define V_RSPCNTLE(x) ((x) << S_RSPCNTLE) +#define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE) + +#define S_REQCNTLE 0 +#define M_REQCNTLE 0xffffU +#define V_REQCNTLE(x) ((x) << S_REQCNTLE) +#define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE) + #define A_LE_DB_DBGI_CONFIG 0x19cf0 #define S_DBGICMDPERR 31 @@ -19001,6 +28790,22 @@ #define V_TCAM(x) ((x) << S_TCAM) #define F_TCAM V_TCAM(1U) +#define S_MARSPPARERRLE 17 +#define V_MARSPPARERRLE(x) ((x) << S_MARSPPARERRLE) +#define F_MARSPPARERRLE V_MARSPPARERRLE(1U) + +#define S_REQQUEUELE 16 +#define V_REQQUEUELE(x) ((x) << S_REQQUEUELE) +#define F_REQQUEUELE V_REQQUEUELE(1U) + +#define S_VFPARERRLE 14 +#define V_VFPARERRLE(x) ((x) << S_VFPARERRLE) +#define F_VFPARERRLE V_VFPARERRLE(1U) + +#define S_TCAMLE 6 +#define V_TCAMLE(x) ((x) << S_TCAMLE) +#define F_TCAMLE V_TCAMLE(1U) + #define A_LE_SPARE 0x19cfc #define A_LE_DB_DBGI_REQ_DATA 0x19d00 #define A_LE_DB_DBGI_REQ_MASK 0x19d50 @@ -19093,16 +28898,76 @@ #define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL) #define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00 +#define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00 #define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50 #define A_LE_HASH_MASK_GEN_IPV4 0x19ea0 +#define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0 +#define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0 +#define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4 #define A_LE_HASH_MASK_CMP_IPV6 0x19ef0 +#define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8 #define A_LE_DEBUG_LA_CONFIG 0x19f20 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30 +#define A_LE_DEBUG_LA_SELECTOR 0x19f34 +#define A_LE_SRVR_SRAM_INIT 0x19f34 + +#define S_SRVRSRAMBASE 2 +#define M_SRVRSRAMBASE 0xfffffU +#define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE) +#define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE) + +#define S_SRVRINITBUSY 1 +#define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY) +#define F_SRVRINITBUSY V_SRVRINITBUSY(1U) + +#define S_SRVRINIT 0 +#define V_SRVRINIT(x) ((x) << S_SRVRINIT) +#define F_SRVRINIT V_SRVRINIT(1U) + +#define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38 +#define A_LE_SRVR_VF_SRCH_TABLE 0x19f38 + +#define S_RDWR 21 +#define V_RDWR(x) ((x) << S_RDWR) +#define F_RDWR V_RDWR(1U) + +#define S_VFINDEX 14 +#define M_VFINDEX 0x7fU +#define V_VFINDEX(x) ((x) << S_VFINDEX) +#define G_VFINDEX(x) (((x) >> S_VFINDEX) & M_VFINDEX) + +#define S_SRCHHADDR 7 +#define M_SRCHHADDR 0x7fU +#define V_SRCHHADDR(x) ((x) << S_SRCHHADDR) +#define G_SRCHHADDR(x) (((x) >> S_SRCHHADDR) & M_SRCHHADDR) + +#define S_SRCHLADDR 0 +#define M_SRCHLADDR 0x7fU +#define V_SRCHLADDR(x) ((x) << S_SRCHLADDR) +#define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR) + +#define A_LE_MA_DEBUG_LA_DATA 0x19f3c +#define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40 +#define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40 +#define A_LE_HASH_DEBUG_LA_DATA 0x19f44 +#define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48 +#define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c +#define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90 +#define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4 +#define A_LE_HASH_COLLISION 0x19fc4 +#define A_LE_GLOBAL_COLLISION 0x19fc8 +#define A_LE_FULL_CNT_COLLISION 0x19fcc +#define A_LE_DEBUG_LA_CONFIGT5 0x19fd0 +#define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4 +#define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8 +#define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc +#define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0 +#define A_LE_DEBUG_LA_SEL_DATA 0x19fe4 /* registers for module NCSI */ #define NCSI_BASE_ADDR 0x1a000 @@ -19447,12 +29312,26 @@ #define V_DEBUGSEL(x) ((x) << S_DEBUGSEL) #define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL) +#define S_TXFIFO_EMPTY 4 +#define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY) +#define F_TXFIFO_EMPTY V_TXFIFO_EMPTY(1U) + +#define S_TXFIFO_FULL 3 +#define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL) +#define F_TXFIFO_FULL V_TXFIFO_FULL(1U) + +#define S_PKG_ID 0 +#define M_PKG_ID 0x7U +#define V_PKG_ID(x) ((x) << S_PKG_ID) +#define G_PKG_ID(x) (((x) >> S_PKG_ID) & M_PKG_ID) + #define A_NCSI_PERR_INJECT 0x1a0f4 #define S_MCSIMELSEL 1 #define V_MCSIMELSEL(x) ((x) << S_MCSIMELSEL) #define F_MCSIMELSEL V_MCSIMELSEL(1U) +#define A_NCSI_PERR_ENABLE 0x1a0f8 #define A_NCSI_MACB_NETWORK_CTRL 0x1a100 #define S_TXSNDZEROPAUSE 12 @@ -21090,11 +30969,6 @@ #define V_RESRV(x) ((x) << S_RESRV) #define G_RESRV(x) (((x) >> S_RESRV) & M_RESRV) -#define S_DATA 0 -#define M_DATA_ 0xffffU -#define V_DATA(x) ((x) << S_DATA) -#define G_DATA(x) (((x) >> S_DATA) & M_DATA_) - #define A_XGMAC_PORT_XGM_MODULE_ID 0x12fc #define S_MODULEID 16 @@ -23472,6 +33346,16 @@ #define V_OBQFULL(x) ((x) << S_OBQFULL) #define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL) +#define S_T5_OBQGEN 8 +#define M_T5_OBQGEN 0xffffffU +#define V_T5_OBQGEN(x) ((x) << S_T5_OBQGEN) +#define G_T5_OBQGEN(x) (((x) >> S_T5_OBQGEN) & M_T5_OBQGEN) + +#define S_T5_OBQFULL 0 +#define M_T5_OBQFULL 0xffU +#define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL) +#define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL) + #define A_UP_IBQ_0_RDADDR 0x10 #define S_QUEID 13 @@ -23690,6 +33574,10 @@ #define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN) #define F_UPDBGLAEN V_UPDBGLAEN(1U) +#define S_UPDBGLABUSY 14 +#define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY) +#define F_UPDBGLABUSY V_UPDBGLABUSY(1U) + #define A_UP_UP_DBG_LA_DATA 0x144 #define A_UP_PIO_MST_CONFIG 0x148 @@ -23721,6 +33609,15 @@ #define V_UPRID(x) ((x) << S_UPRID) #define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID) +#define S_REQVFVLD 27 +#define V_REQVFVLD(x) ((x) << S_REQVFVLD) +#define F_REQVFVLD V_REQVFVLD(1U) + +#define S_T5_UPRID 0 +#define M_T5_UPRID 0xffU +#define V_T5_UPRID(x) ((x) << S_T5_UPRID) +#define G_T5_UPRID(x) (((x) >> S_T5_UPRID) & M_T5_UPRID) + #define A_UP_UP_SELF_CONTROL 0x14c #define S_UPSELFRESET 0 @@ -23736,6 +33633,20 @@ #define A_UP_MAILBOX_PF6_CTL 0x1e0 #define A_UP_MAILBOX_PF7_CTL 0x1f0 #define A_UP_TSCH_CHNLN_CLASS_RDY 0x200 + +#define S_ECO_15444_SGE_DB_BUSY 31 +#define V_ECO_15444_SGE_DB_BUSY(x) ((x) << S_ECO_15444_SGE_DB_BUSY) +#define F_ECO_15444_SGE_DB_BUSY V_ECO_15444_SGE_DB_BUSY(1U) + +#define S_ECO_15444_PL_INTF_BUSY 30 +#define V_ECO_15444_PL_INTF_BUSY(x) ((x) << S_ECO_15444_PL_INTF_BUSY) +#define F_ECO_15444_PL_INTF_BUSY V_ECO_15444_PL_INTF_BUSY(1U) + +#define S_TSCHCHNLCRDY 0 +#define M_TSCHCHNLCRDY 0x3fffffffU +#define V_TSCHCHNLCRDY(x) ((x) << S_TSCHCHNLCRDY) +#define G_TSCHCHNLCRDY(x) (((x) >> S_TSCHCHNLCRDY) & M_TSCHCHNLCRDY) + #define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204 #define S_TSCHWRRLIMIT 16 @@ -23780,6 +33691,90 @@ #define A_UP_UPLADBGPCCHKMASK_2 0x264 #define A_UP_UPLADBGPCCHKDATA_3 0x270 #define A_UP_UPLADBGPCCHKMASK_3 0x274 +#define A_UP_IBQ_0_SHADOW_RDADDR 0x280 +#define A_UP_IBQ_0_SHADOW_WRADDR 0x284 +#define A_UP_IBQ_0_SHADOW_STATUS 0x288 +#define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c +#define A_UP_IBQ_1_SHADOW_RDADDR 0x290 +#define A_UP_IBQ_1_SHADOW_WRADDR 0x294 +#define A_UP_IBQ_1_SHADOW_STATUS 0x298 +#define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c +#define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0 +#define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4 +#define A_UP_IBQ_2_SHADOW_STATUS 0x2a8 +#define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac +#define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0 +#define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4 +#define A_UP_IBQ_3_SHADOW_STATUS 0x2b8 +#define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc +#define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0 +#define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4 +#define A_UP_IBQ_4_SHADOW_STATUS 0x2c8 +#define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc +#define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0 +#define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4 +#define A_UP_IBQ_5_SHADOW_STATUS 0x2d8 +#define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc +#define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0 +#define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4 +#define A_UP_OBQ_0_SHADOW_STATUS 0x2e8 +#define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec +#define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0 +#define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4 +#define A_UP_OBQ_1_SHADOW_STATUS 0x2f8 +#define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc +#define A_UP_OBQ_2_SHADOW_RDADDR 0x300 +#define A_UP_OBQ_2_SHADOW_WRADDR 0x304 +#define A_UP_OBQ_2_SHADOW_STATUS 0x308 +#define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c +#define A_UP_OBQ_3_SHADOW_RDADDR 0x310 +#define A_UP_OBQ_3_SHADOW_WRADDR 0x314 +#define A_UP_OBQ_3_SHADOW_STATUS 0x318 +#define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c +#define A_UP_OBQ_4_SHADOW_RDADDR 0x320 +#define A_UP_OBQ_4_SHADOW_WRADDR 0x324 +#define A_UP_OBQ_4_SHADOW_STATUS 0x328 +#define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c +#define A_UP_OBQ_5_SHADOW_RDADDR 0x330 +#define A_UP_OBQ_5_SHADOW_WRADDR 0x334 +#define A_UP_OBQ_5_SHADOW_STATUS 0x338 +#define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c +#define A_UP_OBQ_6_SHADOW_RDADDR 0x340 +#define A_UP_OBQ_6_SHADOW_WRADDR 0x344 +#define A_UP_OBQ_6_SHADOW_STATUS 0x348 +#define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c +#define A_UP_OBQ_7_SHADOW_RDADDR 0x350 +#define A_UP_OBQ_7_SHADOW_WRADDR 0x354 +#define A_UP_OBQ_7_SHADOW_STATUS 0x358 +#define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c +#define A_UP_IBQ_0_SHADOW_CONFIG 0x360 +#define A_UP_IBQ_0_SHADOW_REALADDR 0x364 +#define A_UP_IBQ_1_SHADOW_CONFIG 0x368 +#define A_UP_IBQ_1_SHADOW_REALADDR 0x36c +#define A_UP_IBQ_2_SHADOW_CONFIG 0x370 +#define A_UP_IBQ_2_SHADOW_REALADDR 0x374 +#define A_UP_IBQ_3_SHADOW_CONFIG 0x378 +#define A_UP_IBQ_3_SHADOW_REALADDR 0x37c +#define A_UP_IBQ_4_SHADOW_CONFIG 0x380 +#define A_UP_IBQ_4_SHADOW_REALADDR 0x384 +#define A_UP_IBQ_5_SHADOW_CONFIG 0x388 +#define A_UP_IBQ_5_SHADOW_REALADDR 0x38c +#define A_UP_OBQ_0_SHADOW_CONFIG 0x390 +#define A_UP_OBQ_0_SHADOW_REALADDR 0x394 +#define A_UP_OBQ_1_SHADOW_CONFIG 0x398 +#define A_UP_OBQ_1_SHADOW_REALADDR 0x39c +#define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0 +#define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4 +#define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8 +#define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac +#define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0 +#define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4 +#define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8 +#define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc +#define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0 +#define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4 +#define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8 +#define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc /* registers for module CIM_CTL */ #define CIM_CTL_BASE_ADDR 0x0 @@ -24090,6 +34085,17 @@ #define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT) #define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT) +#define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_LIMITER 0x920 + +#define S_TSCCLRATENEG 31 +#define V_TSCCLRATENEG(x) ((x) << S_TSCCLRATENEG) +#define F_TSCCLRATENEG V_TSCCLRATENEG(1U) + +#define S_TSCCLRATEL 0 +#define M_TSCCLRATEL 0xffffffU +#define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL) +#define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL) + #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924 #define S_TSCCLRMAX 16 @@ -24120,4 +34126,8976 @@ #define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT) #define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT) +#define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84 +#define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88 +#define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c +#define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90 +#define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94 +#define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98 +#define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c +#define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0 +#define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4 + +#define S_PF7_OWNER_PL 15 +#define V_PF7_OWNER_PL(x) ((x) << S_PF7_OWNER_PL) +#define F_PF7_OWNER_PL V_PF7_OWNER_PL(1U) + +#define S_PF6_OWNER_PL 14 +#define V_PF6_OWNER_PL(x) ((x) << S_PF6_OWNER_PL) +#define F_PF6_OWNER_PL V_PF6_OWNER_PL(1U) + +#define S_PF5_OWNER_PL 13 +#define V_PF5_OWNER_PL(x) ((x) << S_PF5_OWNER_PL) +#define F_PF5_OWNER_PL V_PF5_OWNER_PL(1U) + +#define S_PF4_OWNER_PL 12 +#define V_PF4_OWNER_PL(x) ((x) << S_PF4_OWNER_PL) +#define F_PF4_OWNER_PL V_PF4_OWNER_PL(1U) + +#define S_PF3_OWNER_PL 11 +#define V_PF3_OWNER_PL(x) ((x) << S_PF3_OWNER_PL) +#define F_PF3_OWNER_PL V_PF3_OWNER_PL(1U) + +#define S_PF2_OWNER_PL 10 +#define V_PF2_OWNER_PL(x) ((x) << S_PF2_OWNER_PL) +#define F_PF2_OWNER_PL V_PF2_OWNER_PL(1U) + +#define S_PF1_OWNER_PL 9 +#define V_PF1_OWNER_PL(x) ((x) << S_PF1_OWNER_PL) +#define F_PF1_OWNER_PL V_PF1_OWNER_PL(1U) + +#define S_PF0_OWNER_PL 8 +#define V_PF0_OWNER_PL(x) ((x) << S_PF0_OWNER_PL) +#define F_PF0_OWNER_PL V_PF0_OWNER_PL(1U) + +#define S_PF7_OWNER_UP 7 +#define V_PF7_OWNER_UP(x) ((x) << S_PF7_OWNER_UP) +#define F_PF7_OWNER_UP V_PF7_OWNER_UP(1U) + +#define S_PF6_OWNER_UP 6 +#define V_PF6_OWNER_UP(x) ((x) << S_PF6_OWNER_UP) +#define F_PF6_OWNER_UP V_PF6_OWNER_UP(1U) + +#define S_PF5_OWNER_UP 5 +#define V_PF5_OWNER_UP(x) ((x) << S_PF5_OWNER_UP) +#define F_PF5_OWNER_UP V_PF5_OWNER_UP(1U) + +#define S_PF4_OWNER_UP 4 +#define V_PF4_OWNER_UP(x) ((x) << S_PF4_OWNER_UP) +#define F_PF4_OWNER_UP V_PF4_OWNER_UP(1U) + +#define S_PF3_OWNER_UP 3 +#define V_PF3_OWNER_UP(x) ((x) << S_PF3_OWNER_UP) +#define F_PF3_OWNER_UP V_PF3_OWNER_UP(1U) + +#define S_PF2_OWNER_UP 2 +#define V_PF2_OWNER_UP(x) ((x) << S_PF2_OWNER_UP) +#define F_PF2_OWNER_UP V_PF2_OWNER_UP(1U) + +#define S_PF1_OWNER_UP 1 +#define V_PF1_OWNER_UP(x) ((x) << S_PF1_OWNER_UP) +#define F_PF1_OWNER_UP V_PF1_OWNER_UP(1U) + +#define S_PF0_OWNER_UP 0 +#define V_PF0_OWNER_UP(x) ((x) << S_PF0_OWNER_UP) +#define F_PF0_OWNER_UP V_PF0_OWNER_UP(1U) + +#define A_CIM_CTL_PIO_MST_CONFIG 0xda8 + +#define S_T5_CTLRID 0 +#define M_T5_CTLRID 0xffU +#define V_T5_CTLRID(x) ((x) << S_T5_CTLRID) +#define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID) + +/* registers for module MAC */ +#define MAC_BASE_ADDR 0x0 + +#define A_MAC_PORT_CFG 0x800 + +#define S_MAC_CLK_SEL 29 +#define M_MAC_CLK_SEL 0x7U +#define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL) +#define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL) + +#define S_SMUXTXSEL 9 +#define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL) +#define F_SMUXTXSEL V_SMUXTXSEL(1U) + +#define S_SMUXRXSEL 8 +#define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL) +#define F_SMUXRXSEL V_SMUXRXSEL(1U) + +#define S_PORTSPEED 4 +#define M_PORTSPEED 0x3U +#define V_PORTSPEED(x) ((x) << S_PORTSPEED) +#define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED) + +#define A_MAC_PORT_RESET_CTRL 0x804 + +#define S_TWGDSK_HSSC16B 31 +#define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B) +#define F_TWGDSK_HSSC16B V_TWGDSK_HSSC16B(1U) + +#define S_EEE_RESET 30 +#define V_EEE_RESET(x) ((x) << S_EEE_RESET) +#define F_EEE_RESET V_EEE_RESET(1U) + +#define S_PTP_TIMER 29 +#define V_PTP_TIMER(x) ((x) << S_PTP_TIMER) +#define F_PTP_TIMER V_PTP_TIMER(1U) + +#define S_MTIPREFRESET 28 +#define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET) +#define F_MTIPREFRESET V_MTIPREFRESET(1U) + +#define S_MTIPTXFFRESET 27 +#define V_MTIPTXFFRESET(x) ((x) << S_MTIPTXFFRESET) +#define F_MTIPTXFFRESET V_MTIPTXFFRESET(1U) + +#define S_MTIPRXFFRESET 26 +#define V_MTIPRXFFRESET(x) ((x) << S_MTIPRXFFRESET) +#define F_MTIPRXFFRESET V_MTIPRXFFRESET(1U) + +#define S_MTIPREGRESET 25 +#define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET) +#define F_MTIPREGRESET V_MTIPREGRESET(1U) + +#define S_AEC3RESET 23 +#define V_AEC3RESET(x) ((x) << S_AEC3RESET) +#define F_AEC3RESET V_AEC3RESET(1U) + +#define S_AEC2RESET 22 +#define V_AEC2RESET(x) ((x) << S_AEC2RESET) +#define F_AEC2RESET V_AEC2RESET(1U) + +#define S_AEC1RESET 21 +#define V_AEC1RESET(x) ((x) << S_AEC1RESET) +#define F_AEC1RESET V_AEC1RESET(1U) + +#define S_AEC0RESET 20 +#define V_AEC0RESET(x) ((x) << S_AEC0RESET) +#define F_AEC0RESET V_AEC0RESET(1U) + +#define S_AET3RESET 19 +#define V_AET3RESET(x) ((x) << S_AET3RESET) +#define F_AET3RESET V_AET3RESET(1U) + +#define S_AET2RESET 18 +#define V_AET2RESET(x) ((x) << S_AET2RESET) +#define F_AET2RESET V_AET2RESET(1U) + +#define S_AET1RESET 17 +#define V_AET1RESET(x) ((x) << S_AET1RESET) +#define F_AET1RESET V_AET1RESET(1U) + +#define S_AET0RESET 16 +#define V_AET0RESET(x) ((x) << S_AET0RESET) +#define F_AET0RESET V_AET0RESET(1U) + +#define S_TXIF_RESET 12 +#define V_TXIF_RESET(x) ((x) << S_TXIF_RESET) +#define F_TXIF_RESET V_TXIF_RESET(1U) + +#define S_RXIF_RESET 11 +#define V_RXIF_RESET(x) ((x) << S_RXIF_RESET) +#define F_RXIF_RESET V_RXIF_RESET(1U) + +#define S_MTIPSD3TXRST 9 +#define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST) +#define F_MTIPSD3TXRST V_MTIPSD3TXRST(1U) + +#define S_MTIPSD2TXRST 8 +#define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST) +#define F_MTIPSD2TXRST V_MTIPSD2TXRST(1U) + +#define S_MTIPSD1TXRST 7 +#define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST) +#define F_MTIPSD1TXRST V_MTIPSD1TXRST(1U) + +#define S_MTIPSD0TXRST 6 +#define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST) +#define F_MTIPSD0TXRST V_MTIPSD0TXRST(1U) + +#define S_MTIPSD3RXRST 5 +#define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST) +#define F_MTIPSD3RXRST V_MTIPSD3RXRST(1U) + +#define S_MTIPSD2RXRST 4 +#define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST) +#define F_MTIPSD2RXRST V_MTIPSD2RXRST(1U) + +#define S_MTIPSD1RXRST 3 +#define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST) +#define F_MTIPSD1RXRST V_MTIPSD1RXRST(1U) + +#define S_MTIPSD0RXRST 1 +#define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST) +#define F_MTIPSD0RXRST V_MTIPSD0RXRST(1U) + +#define A_MAC_PORT_LED_CFG 0x808 +#define A_MAC_PORT_LED_COUNTHI 0x80c +#define A_MAC_PORT_LED_COUNTLO 0x810 +#define A_MAC_PORT_CFG3 0x814 + +#define S_FCSDISCTRL 25 +#define V_FCSDISCTRL(x) ((x) << S_FCSDISCTRL) +#define F_FCSDISCTRL V_FCSDISCTRL(1U) + +#define S_SIGDETCTRL 24 +#define V_SIGDETCTRL(x) ((x) << S_SIGDETCTRL) +#define F_SIGDETCTRL V_SIGDETCTRL(1U) + +#define S_TX_LANE 23 +#define V_TX_LANE(x) ((x) << S_TX_LANE) +#define F_TX_LANE V_TX_LANE(1U) + +#define S_RX_LANE 22 +#define V_RX_LANE(x) ((x) << S_RX_LANE) +#define F_RX_LANE V_RX_LANE(1U) + +#define S_SE_CLR 21 +#define V_SE_CLR(x) ((x) << S_SE_CLR) +#define F_SE_CLR V_SE_CLR(1U) + +#define S_AN_ENA 17 +#define M_AN_ENA 0xfU +#define V_AN_ENA(x) ((x) << S_AN_ENA) +#define G_AN_ENA(x) (((x) >> S_AN_ENA) & M_AN_ENA) + +#define S_SD_RX_CLK_ENA 13 +#define M_SD_RX_CLK_ENA 0xfU +#define V_SD_RX_CLK_ENA(x) ((x) << S_SD_RX_CLK_ENA) +#define G_SD_RX_CLK_ENA(x) (((x) >> S_SD_RX_CLK_ENA) & M_SD_RX_CLK_ENA) + +#define S_SD_TX_CLK_ENA 9 +#define M_SD_TX_CLK_ENA 0xfU +#define V_SD_TX_CLK_ENA(x) ((x) << S_SD_TX_CLK_ENA) +#define G_SD_TX_CLK_ENA(x) (((x) >> S_SD_TX_CLK_ENA) & M_SD_TX_CLK_ENA) + +#define S_SGMIISEL 8 +#define V_SGMIISEL(x) ((x) << S_SGMIISEL) +#define F_SGMIISEL V_SGMIISEL(1U) + +#define S_HSSPLLSEL 4 +#define M_HSSPLLSEL 0xfU +#define V_HSSPLLSEL(x) ((x) << S_HSSPLLSEL) +#define G_HSSPLLSEL(x) (((x) >> S_HSSPLLSEL) & M_HSSPLLSEL) + +#define S_HSSC16C20SEL 0 +#define M_HSSC16C20SEL 0xfU +#define V_HSSC16C20SEL(x) ((x) << S_HSSC16C20SEL) +#define G_HSSC16C20SEL(x) (((x) >> S_HSSC16C20SEL) & M_HSSC16C20SEL) + +#define A_MAC_PORT_CFG2 0x818 + +#define S_T5_AEC_PMA_TX_READY 4 +#define M_T5_AEC_PMA_TX_READY 0xfU +#define V_T5_AEC_PMA_TX_READY(x) ((x) << S_T5_AEC_PMA_TX_READY) +#define G_T5_AEC_PMA_TX_READY(x) \ + (((x) >> S_T5_AEC_PMA_TX_READY) & M_T5_AEC_PMA_TX_READY) + +#define S_T5_AEC_PMA_RX_READY 0 +#define M_T5_AEC_PMA_RX_READY 0xfU +#define V_T5_AEC_PMA_RX_READY(x) ((x) << S_T5_AEC_PMA_RX_READY) +#define G_T5_AEC_PMA_RX_READY(x) \ + (((x) >> S_T5_AEC_PMA_RX_READY) & M_T5_AEC_PMA_RX_READY) + +#define A_MAC_PORT_PKT_COUNT 0x81c +#define A_MAC_PORT_CFG4 0x820 + +#define S_AEC3_RX_WIDTH 14 +#define M_AEC3_RX_WIDTH 0x3U +#define V_AEC3_RX_WIDTH(x) ((x) << S_AEC3_RX_WIDTH) +#define G_AEC3_RX_WIDTH(x) (((x) >> S_AEC3_RX_WIDTH) & M_AEC3_RX_WIDTH) + +#define S_AEC2_RX_WIDTH 12 +#define M_AEC2_RX_WIDTH 0x3U +#define V_AEC2_RX_WIDTH(x) ((x) << S_AEC2_RX_WIDTH) +#define G_AEC2_RX_WIDTH(x) (((x) >> S_AEC2_RX_WIDTH) & M_AEC2_RX_WIDTH) + +#define S_AEC1_RX_WIDTH 10 +#define M_AEC1_RX_WIDTH 0x3U +#define V_AEC1_RX_WIDTH(x) ((x) << S_AEC1_RX_WIDTH) +#define G_AEC1_RX_WIDTH(x) (((x) >> S_AEC1_RX_WIDTH) & M_AEC1_RX_WIDTH) + +#define S_AEC0_RX_WIDTH 8 +#define M_AEC0_RX_WIDTH 0x3U +#define V_AEC0_RX_WIDTH(x) ((x) << S_AEC0_RX_WIDTH) +#define G_AEC0_RX_WIDTH(x) (((x) >> S_AEC0_RX_WIDTH) & M_AEC0_RX_WIDTH) + +#define S_AEC3_TX_WIDTH 6 +#define M_AEC3_TX_WIDTH 0x3U +#define V_AEC3_TX_WIDTH(x) ((x) << S_AEC3_TX_WIDTH) +#define G_AEC3_TX_WIDTH(x) (((x) >> S_AEC3_TX_WIDTH) & M_AEC3_TX_WIDTH) + +#define S_AEC2_TX_WIDTH 4 +#define M_AEC2_TX_WIDTH 0x3U +#define V_AEC2_TX_WIDTH(x) ((x) << S_AEC2_TX_WIDTH) +#define G_AEC2_TX_WIDTH(x) (((x) >> S_AEC2_TX_WIDTH) & M_AEC2_TX_WIDTH) + +#define S_AEC1_TX_WIDTH 2 +#define M_AEC1_TX_WIDTH 0x3U +#define V_AEC1_TX_WIDTH(x) ((x) << S_AEC1_TX_WIDTH) +#define G_AEC1_TX_WIDTH(x) (((x) >> S_AEC1_TX_WIDTH) & M_AEC1_TX_WIDTH) + +#define S_AEC0_TX_WIDTH 0 +#define M_AEC0_TX_WIDTH 0x3U +#define V_AEC0_TX_WIDTH(x) ((x) << S_AEC0_TX_WIDTH) +#define G_AEC0_TX_WIDTH(x) (((x) >> S_AEC0_TX_WIDTH) & M_AEC0_TX_WIDTH) + +#define A_MAC_PORT_MAGIC_MACID_LO 0x824 +#define A_MAC_PORT_MAGIC_MACID_HI 0x828 +#define A_MAC_PORT_LINK_STATUS 0x834 + +#define S_AN_DONE 6 +#define V_AN_DONE(x) ((x) << S_AN_DONE) +#define F_AN_DONE V_AN_DONE(1U) + +#define S_ALIGN_DONE 5 +#define V_ALIGN_DONE(x) ((x) << S_ALIGN_DONE) +#define F_ALIGN_DONE V_ALIGN_DONE(1U) + +#define S_BLOCK_LOCK 4 +#define V_BLOCK_LOCK(x) ((x) << S_BLOCK_LOCK) +#define F_BLOCK_LOCK V_BLOCK_LOCK(1U) + +#define A_MAC_PORT_EPIO_DATA0 0x8c0 +#define A_MAC_PORT_EPIO_DATA1 0x8c4 +#define A_MAC_PORT_EPIO_DATA2 0x8c8 +#define A_MAC_PORT_EPIO_DATA3 0x8cc +#define A_MAC_PORT_EPIO_OP 0x8d0 +#define A_MAC_PORT_WOL_STATUS 0x8d4 +#define A_MAC_PORT_INT_EN 0x8d8 + +#define S_TX_TS_AVAIL 29 +#define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL) +#define F_TX_TS_AVAIL V_TX_TS_AVAIL(1U) + +#define S_AN_PAGE_RCVD 2 +#define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD) +#define F_AN_PAGE_RCVD V_AN_PAGE_RCVD(1U) + +#define A_MAC_PORT_INT_CAUSE 0x8dc +#define A_MAC_PORT_PERR_INT_EN 0x8e0 + +#define S_PERR_PKT_RAM 24 +#define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM) +#define F_PERR_PKT_RAM V_PERR_PKT_RAM(1U) + +#define S_PERR_MASK_RAM 23 +#define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM) +#define F_PERR_MASK_RAM V_PERR_MASK_RAM(1U) + +#define S_PERR_CRC_RAM 22 +#define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM) +#define F_PERR_CRC_RAM V_PERR_CRC_RAM(1U) + +#define S_RX_DFF_SEG0 21 +#define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0) +#define F_RX_DFF_SEG0 V_RX_DFF_SEG0(1U) + +#define S_RX_SFF_SEG0 20 +#define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0) +#define F_RX_SFF_SEG0 V_RX_SFF_SEG0(1U) + +#define S_RX_DFF_MAC10 19 +#define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10) +#define F_RX_DFF_MAC10 V_RX_DFF_MAC10(1U) + +#define S_RX_SFF_MAC10 18 +#define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10) +#define F_RX_SFF_MAC10 V_RX_SFF_MAC10(1U) + +#define S_TX_DFF_SEG0 17 +#define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0) +#define F_TX_DFF_SEG0 V_TX_DFF_SEG0(1U) + +#define S_TX_SFF_SEG0 16 +#define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0) +#define F_TX_SFF_SEG0 V_TX_SFF_SEG0(1U) + +#define S_TX_DFF_MAC10 15 +#define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10) +#define F_TX_DFF_MAC10 V_TX_DFF_MAC10(1U) + +#define S_TX_SFF_MAC10 14 +#define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10) +#define F_TX_SFF_MAC10 V_TX_SFF_MAC10(1U) + +#define S_RX_STATS 13 +#define V_RX_STATS(x) ((x) << S_RX_STATS) +#define F_RX_STATS V_RX_STATS(1U) + +#define S_TX_STATS 12 +#define V_TX_STATS(x) ((x) << S_TX_STATS) +#define F_TX_STATS V_TX_STATS(1U) + +#define S_PERR3_RX_MIX 11 +#define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX) +#define F_PERR3_RX_MIX V_PERR3_RX_MIX(1U) + +#define S_PERR3_RX_SD 10 +#define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD) +#define F_PERR3_RX_SD V_PERR3_RX_SD(1U) + +#define S_PERR3_TX 9 +#define V_PERR3_TX(x) ((x) << S_PERR3_TX) +#define F_PERR3_TX V_PERR3_TX(1U) + +#define S_PERR2_RX_MIX 8 +#define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX) +#define F_PERR2_RX_MIX V_PERR2_RX_MIX(1U) + +#define S_PERR2_RX_SD 7 +#define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD) +#define F_PERR2_RX_SD V_PERR2_RX_SD(1U) + +#define S_PERR2_TX 6 +#define V_PERR2_TX(x) ((x) << S_PERR2_TX) +#define F_PERR2_TX V_PERR2_TX(1U) + +#define S_PERR1_RX_MIX 5 +#define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX) +#define F_PERR1_RX_MIX V_PERR1_RX_MIX(1U) + +#define S_PERR1_RX_SD 4 +#define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD) +#define F_PERR1_RX_SD V_PERR1_RX_SD(1U) + +#define S_PERR1_TX 3 +#define V_PERR1_TX(x) ((x) << S_PERR1_TX) +#define F_PERR1_TX V_PERR1_TX(1U) + +#define S_PERR0_RX_MIX 2 +#define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX) +#define F_PERR0_RX_MIX V_PERR0_RX_MIX(1U) + +#define S_PERR0_RX_SD 1 +#define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD) +#define F_PERR0_RX_SD V_PERR0_RX_SD(1U) + +#define S_PERR0_TX 0 +#define V_PERR0_TX(x) ((x) << S_PERR0_TX) +#define F_PERR0_TX V_PERR0_TX(1U) + +#define A_MAC_PORT_PERR_INT_CAUSE 0x8e4 +#define A_MAC_PORT_PERR_ENABLE 0x8e8 +#define A_MAC_PORT_PERR_INJECT 0x8ec +#define A_MAC_PORT_HSS_CFG0 0x8f0 + +#define S_HSSREFCLKVALIDA 20 +#define V_HSSREFCLKVALIDA(x) ((x) << S_HSSREFCLKVALIDA) +#define F_HSSREFCLKVALIDA V_HSSREFCLKVALIDA(1U) + +#define S_HSSREFCLKVALIDB 19 +#define V_HSSREFCLKVALIDB(x) ((x) << S_HSSREFCLKVALIDB) +#define F_HSSREFCLKVALIDB V_HSSREFCLKVALIDB(1U) + +#define S_HSSRESYNCA 18 +#define V_HSSRESYNCA(x) ((x) << S_HSSRESYNCA) +#define F_HSSRESYNCA V_HSSRESYNCA(1U) + +#define S_HSSRESYNCB 16 +#define V_HSSRESYNCB(x) ((x) << S_HSSRESYNCB) +#define F_HSSRESYNCB V_HSSRESYNCB(1U) + +#define S_HSSRECCALA 15 +#define V_HSSRECCALA(x) ((x) << S_HSSRECCALA) +#define F_HSSRECCALA V_HSSRECCALA(1U) + +#define S_HSSRECCALB 13 +#define V_HSSRECCALB(x) ((x) << S_HSSRECCALB) +#define F_HSSRECCALB V_HSSRECCALB(1U) + +#define S_HSSPLLBYPA 12 +#define V_HSSPLLBYPA(x) ((x) << S_HSSPLLBYPA) +#define F_HSSPLLBYPA V_HSSPLLBYPA(1U) + +#define S_HSSPLLBYPB 11 +#define V_HSSPLLBYPB(x) ((x) << S_HSSPLLBYPB) +#define F_HSSPLLBYPB V_HSSPLLBYPB(1U) + +#define S_HSSPDWNPLLA 10 +#define V_HSSPDWNPLLA(x) ((x) << S_HSSPDWNPLLA) +#define F_HSSPDWNPLLA V_HSSPDWNPLLA(1U) + +#define S_HSSPDWNPLLB 9 +#define V_HSSPDWNPLLB(x) ((x) << S_HSSPDWNPLLB) +#define F_HSSPDWNPLLB V_HSSPDWNPLLB(1U) + +#define S_HSSVCOSELA 8 +#define V_HSSVCOSELA(x) ((x) << S_HSSVCOSELA) +#define F_HSSVCOSELA V_HSSVCOSELA(1U) + +#define S_HSSVCOSELB 7 +#define V_HSSVCOSELB(x) ((x) << S_HSSVCOSELB) +#define F_HSSVCOSELB V_HSSVCOSELB(1U) + +#define S_HSSCALCOMP 6 +#define V_HSSCALCOMP(x) ((x) << S_HSSCALCOMP) +#define F_HSSCALCOMP V_HSSCALCOMP(1U) + +#define S_HSSCALENAB 5 +#define V_HSSCALENAB(x) ((x) << S_HSSCALENAB) +#define F_HSSCALENAB V_HSSCALENAB(1U) + +#define A_MAC_PORT_HSS_CFG1 0x8f4 + +#define S_RXACONFIGSEL 30 +#define M_RXACONFIGSEL 0x3U +#define V_RXACONFIGSEL(x) ((x) << S_RXACONFIGSEL) +#define G_RXACONFIGSEL(x) (((x) >> S_RXACONFIGSEL) & M_RXACONFIGSEL) + +#define S_RXAQUIET 29 +#define V_RXAQUIET(x) ((x) << S_RXAQUIET) +#define F_RXAQUIET V_RXAQUIET(1U) + +#define S_RXAREFRESH 28 +#define V_RXAREFRESH(x) ((x) << S_RXAREFRESH) +#define F_RXAREFRESH V_RXAREFRESH(1U) + +#define S_RXBCONFIGSEL 26 +#define M_RXBCONFIGSEL 0x3U +#define V_RXBCONFIGSEL(x) ((x) << S_RXBCONFIGSEL) +#define G_RXBCONFIGSEL(x) (((x) >> S_RXBCONFIGSEL) & M_RXBCONFIGSEL) + +#define S_RXBQUIET 25 +#define V_RXBQUIET(x) ((x) << S_RXBQUIET) +#define F_RXBQUIET V_RXBQUIET(1U) + +#define S_RXBREFRESH 24 +#define V_RXBREFRESH(x) ((x) << S_RXBREFRESH) +#define F_RXBREFRESH V_RXBREFRESH(1U) + +#define S_RXCCONFIGSEL 22 +#define M_RXCCONFIGSEL 0x3U +#define V_RXCCONFIGSEL(x) ((x) << S_RXCCONFIGSEL) +#define G_RXCCONFIGSEL(x) (((x) >> S_RXCCONFIGSEL) & M_RXCCONFIGSEL) + +#define S_RXCQUIET 21 +#define V_RXCQUIET(x) ((x) << S_RXCQUIET) +#define F_RXCQUIET V_RXCQUIET(1U) + +#define S_RXCREFRESH 20 +#define V_RXCREFRESH(x) ((x) << S_RXCREFRESH) +#define F_RXCREFRESH V_RXCREFRESH(1U) + +#define S_RXDCONFIGSEL 18 +#define M_RXDCONFIGSEL 0x3U +#define V_RXDCONFIGSEL(x) ((x) << S_RXDCONFIGSEL) +#define G_RXDCONFIGSEL(x) (((x) >> S_RXDCONFIGSEL) & M_RXDCONFIGSEL) + +#define S_RXDQUIET 17 +#define V_RXDQUIET(x) ((x) << S_RXDQUIET) +#define F_RXDQUIET V_RXDQUIET(1U) + +#define S_RXDREFRESH 16 +#define V_RXDREFRESH(x) ((x) << S_RXDREFRESH) +#define F_RXDREFRESH V_RXDREFRESH(1U) + +#define S_TXACONFIGSEL 14 +#define M_TXACONFIGSEL 0x3U +#define V_TXACONFIGSEL(x) ((x) << S_TXACONFIGSEL) +#define G_TXACONFIGSEL(x) (((x) >> S_TXACONFIGSEL) & M_TXACONFIGSEL) + +#define S_TXAQUIET 13 +#define V_TXAQUIET(x) ((x) << S_TXAQUIET) +#define F_TXAQUIET V_TXAQUIET(1U) + +#define S_TXAREFRESH 12 +#define V_TXAREFRESH(x) ((x) << S_TXAREFRESH) +#define F_TXAREFRESH V_TXAREFRESH(1U) + +#define S_TXBCONFIGSEL 10 +#define M_TXBCONFIGSEL 0x3U +#define V_TXBCONFIGSEL(x) ((x) << S_TXBCONFIGSEL) +#define G_TXBCONFIGSEL(x) (((x) >> S_TXBCONFIGSEL) & M_TXBCONFIGSEL) + +#define S_TXBQUIET 9 +#define V_TXBQUIET(x) ((x) << S_TXBQUIET) +#define F_TXBQUIET V_TXBQUIET(1U) + +#define S_TXBREFRESH 8 +#define V_TXBREFRESH(x) ((x) << S_TXBREFRESH) +#define F_TXBREFRESH V_TXBREFRESH(1U) + +#define S_TXCCONFIGSEL 6 +#define M_TXCCONFIGSEL 0x3U +#define V_TXCCONFIGSEL(x) ((x) << S_TXCCONFIGSEL) +#define G_TXCCONFIGSEL(x) (((x) >> S_TXCCONFIGSEL) & M_TXCCONFIGSEL) + +#define S_TXCQUIET 5 +#define V_TXCQUIET(x) ((x) << S_TXCQUIET) +#define F_TXCQUIET V_TXCQUIET(1U) + +#define S_TXCREFRESH 4 +#define V_TXCREFRESH(x) ((x) << S_TXCREFRESH) +#define F_TXCREFRESH V_TXCREFRESH(1U) + +#define S_TXDCONFIGSEL 2 +#define M_TXDCONFIGSEL 0x3U +#define V_TXDCONFIGSEL(x) ((x) << S_TXDCONFIGSEL) +#define G_TXDCONFIGSEL(x) (((x) >> S_TXDCONFIGSEL) & M_TXDCONFIGSEL) + +#define S_TXDQUIET 1 +#define V_TXDQUIET(x) ((x) << S_TXDQUIET) +#define F_TXDQUIET V_TXDQUIET(1U) + +#define S_TXDREFRESH 0 +#define V_TXDREFRESH(x) ((x) << S_TXDREFRESH) +#define F_TXDREFRESH V_TXDREFRESH(1U) + +#define A_MAC_PORT_HSS_CFG2 0x8f8 + +#define S_RXAASSTCLK 31 +#define V_RXAASSTCLK(x) ((x) << S_RXAASSTCLK) +#define F_RXAASSTCLK V_RXAASSTCLK(1U) + +#define S_T5RXAPRBSRST 30 +#define V_T5RXAPRBSRST(x) ((x) << S_T5RXAPRBSRST) +#define F_T5RXAPRBSRST V_T5RXAPRBSRST(1U) + +#define S_RXBASSTCLK 29 +#define V_RXBASSTCLK(x) ((x) << S_RXBASSTCLK) +#define F_RXBASSTCLK V_RXBASSTCLK(1U) + +#define S_T5RXBPRBSRST 28 +#define V_T5RXBPRBSRST(x) ((x) << S_T5RXBPRBSRST) +#define F_T5RXBPRBSRST V_T5RXBPRBSRST(1U) + +#define S_RXCASSTCLK 27 +#define V_RXCASSTCLK(x) ((x) << S_RXCASSTCLK) +#define F_RXCASSTCLK V_RXCASSTCLK(1U) + +#define S_T5RXCPRBSRST 26 +#define V_T5RXCPRBSRST(x) ((x) << S_T5RXCPRBSRST) +#define F_T5RXCPRBSRST V_T5RXCPRBSRST(1U) + +#define S_RXDASSTCLK 25 +#define V_RXDASSTCLK(x) ((x) << S_RXDASSTCLK) +#define F_RXDASSTCLK V_RXDASSTCLK(1U) + +#define S_T5RXDPRBSRST 24 +#define V_T5RXDPRBSRST(x) ((x) << S_T5RXDPRBSRST) +#define F_T5RXDPRBSRST V_T5RXDPRBSRST(1U) + +#define A_MAC_PORT_HSS_CFG3 0x8fc + +#define S_HSSCALSSTN 25 +#define M_HSSCALSSTN 0x7U +#define V_HSSCALSSTN(x) ((x) << S_HSSCALSSTN) +#define G_HSSCALSSTN(x) (((x) >> S_HSSCALSSTN) & M_HSSCALSSTN) + +#define S_HSSCALSSTP 22 +#define M_HSSCALSSTP 0x7U +#define V_HSSCALSSTP(x) ((x) << S_HSSCALSSTP) +#define G_HSSCALSSTP(x) (((x) >> S_HSSCALSSTP) & M_HSSCALSSTP) + +#define S_HSSVBOOSTDIVB 19 +#define M_HSSVBOOSTDIVB 0x7U +#define V_HSSVBOOSTDIVB(x) ((x) << S_HSSVBOOSTDIVB) +#define G_HSSVBOOSTDIVB(x) (((x) >> S_HSSVBOOSTDIVB) & M_HSSVBOOSTDIVB) + +#define S_HSSVBOOSTDIVA 16 +#define M_HSSVBOOSTDIVA 0x7U +#define V_HSSVBOOSTDIVA(x) ((x) << S_HSSVBOOSTDIVA) +#define G_HSSVBOOSTDIVA(x) (((x) >> S_HSSVBOOSTDIVA) & M_HSSVBOOSTDIVA) + +#define S_HSSPLLCONFIGB 8 +#define M_HSSPLLCONFIGB 0xffU +#define V_HSSPLLCONFIGB(x) ((x) << S_HSSPLLCONFIGB) +#define G_HSSPLLCONFIGB(x) (((x) >> S_HSSPLLCONFIGB) & M_HSSPLLCONFIGB) + +#define S_HSSPLLCONFIGA 0 +#define M_HSSPLLCONFIGA 0xffU +#define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA) +#define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA) + +#define A_MAC_PORT_HSS_CFG4 0x900 + +#define S_HSSDIVSELA 9 +#define M_HSSDIVSELA 0x1ffU +#define V_HSSDIVSELA(x) ((x) << S_HSSDIVSELA) +#define G_HSSDIVSELA(x) (((x) >> S_HSSDIVSELA) & M_HSSDIVSELA) + +#define S_HSSDIVSELB 0 +#define M_HSSDIVSELB 0x1ffU +#define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB) +#define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB) + +#define A_MAC_PORT_HSS_STATUS 0x904 + +#define S_HSSPLLLOCKB 3 +#define V_HSSPLLLOCKB(x) ((x) << S_HSSPLLLOCKB) +#define F_HSSPLLLOCKB V_HSSPLLLOCKB(1U) + +#define S_HSSPLLLOCKA 2 +#define V_HSSPLLLOCKA(x) ((x) << S_HSSPLLLOCKA) +#define F_HSSPLLLOCKA V_HSSPLLLOCKA(1U) + +#define S_HSSPRTREADYB 1 +#define V_HSSPRTREADYB(x) ((x) << S_HSSPRTREADYB) +#define F_HSSPRTREADYB V_HSSPRTREADYB(1U) + +#define S_HSSPRTREADYA 0 +#define V_HSSPRTREADYA(x) ((x) << S_HSSPRTREADYA) +#define F_HSSPRTREADYA V_HSSPRTREADYA(1U) + +#define A_MAC_PORT_HSS_EEE_STATUS 0x908 + +#define S_RXAQUIET_STATUS 15 +#define V_RXAQUIET_STATUS(x) ((x) << S_RXAQUIET_STATUS) +#define F_RXAQUIET_STATUS V_RXAQUIET_STATUS(1U) + +#define S_RXAREFRESH_STATUS 14 +#define V_RXAREFRESH_STATUS(x) ((x) << S_RXAREFRESH_STATUS) +#define F_RXAREFRESH_STATUS V_RXAREFRESH_STATUS(1U) + +#define S_RXBQUIET_STATUS 13 +#define V_RXBQUIET_STATUS(x) ((x) << S_RXBQUIET_STATUS) +#define F_RXBQUIET_STATUS V_RXBQUIET_STATUS(1U) + +#define S_RXBREFRESH_STATUS 12 +#define V_RXBREFRESH_STATUS(x) ((x) << S_RXBREFRESH_STATUS) +#define F_RXBREFRESH_STATUS V_RXBREFRESH_STATUS(1U) + +#define S_RXCQUIET_STATUS 11 +#define V_RXCQUIET_STATUS(x) ((x) << S_RXCQUIET_STATUS) +#define F_RXCQUIET_STATUS V_RXCQUIET_STATUS(1U) + +#define S_RXCREFRESH_STATUS 10 +#define V_RXCREFRESH_STATUS(x) ((x) << S_RXCREFRESH_STATUS) +#define F_RXCREFRESH_STATUS V_RXCREFRESH_STATUS(1U) + +#define S_RXDQUIET_STATUS 9 +#define V_RXDQUIET_STATUS(x) ((x) << S_RXDQUIET_STATUS) +#define F_RXDQUIET_STATUS V_RXDQUIET_STATUS(1U) + +#define S_RXDREFRESH_STATUS 8 +#define V_RXDREFRESH_STATUS(x) ((x) << S_RXDREFRESH_STATUS) +#define F_RXDREFRESH_STATUS V_RXDREFRESH_STATUS(1U) + +#define S_TXAQUIET_STATUS 7 +#define V_TXAQUIET_STATUS(x) ((x) << S_TXAQUIET_STATUS) +#define F_TXAQUIET_STATUS V_TXAQUIET_STATUS(1U) + +#define S_TXAREFRESH_STATUS 6 +#define V_TXAREFRESH_STATUS(x) ((x) << S_TXAREFRESH_STATUS) +#define F_TXAREFRESH_STATUS V_TXAREFRESH_STATUS(1U) + +#define S_TXBQUIET_STATUS 5 +#define V_TXBQUIET_STATUS(x) ((x) << S_TXBQUIET_STATUS) +#define F_TXBQUIET_STATUS V_TXBQUIET_STATUS(1U) + +#define S_TXBREFRESH_STATUS 4 +#define V_TXBREFRESH_STATUS(x) ((x) << S_TXBREFRESH_STATUS) +#define F_TXBREFRESH_STATUS V_TXBREFRESH_STATUS(1U) + +#define S_TXCQUIET_STATUS 3 +#define V_TXCQUIET_STATUS(x) ((x) << S_TXCQUIET_STATUS) +#define F_TXCQUIET_STATUS V_TXCQUIET_STATUS(1U) + +#define S_TXCREFRESH_STATUS 2 +#define V_TXCREFRESH_STATUS(x) ((x) << S_TXCREFRESH_STATUS) +#define F_TXCREFRESH_STATUS V_TXCREFRESH_STATUS(1U) + +#define S_TXDQUIET_STATUS 1 +#define V_TXDQUIET_STATUS(x) ((x) << S_TXDQUIET_STATUS) +#define F_TXDQUIET_STATUS V_TXDQUIET_STATUS(1U) + +#define S_TXDREFRESH_STATUS 0 +#define V_TXDREFRESH_STATUS(x) ((x) << S_TXDREFRESH_STATUS) +#define F_TXDREFRESH_STATUS V_TXDREFRESH_STATUS(1U) + +#define A_MAC_PORT_HSS_SIGDET_STATUS 0x90c +#define A_MAC_PORT_HSS_PL_CTL 0x910 + +#define S_TOV 16 +#define M_TOV 0xffU +#define V_TOV(x) ((x) << S_TOV) +#define G_TOV(x) (((x) >> S_TOV) & M_TOV) + +#define S_TSU 8 +#define M_TSU 0xffU +#define V_TSU(x) ((x) << S_TSU) +#define G_TSU(x) (((x) >> S_TSU) & M_TSU) + +#define S_IPW 0 +#define M_IPW 0xffU +#define V_IPW(x) ((x) << S_IPW) +#define G_IPW(x) (((x) >> S_IPW) & M_IPW) + +#define A_MAC_PORT_RUNT_FRAME 0x914 + +#define S_RUNTCLEAR 16 +#define V_RUNTCLEAR(x) ((x) << S_RUNTCLEAR) +#define F_RUNTCLEAR V_RUNTCLEAR(1U) + +#define S_RUNT 0 +#define M_RUNT 0xffffU +#define V_RUNT(x) ((x) << S_RUNT) +#define G_RUNT(x) (((x) >> S_RUNT) & M_RUNT) + +#define A_MAC_PORT_EEE_STATUS 0x918 + +#define S_EEE_TX_10G_STATE 10 +#define M_EEE_TX_10G_STATE 0x3U +#define V_EEE_TX_10G_STATE(x) ((x) << S_EEE_TX_10G_STATE) +#define G_EEE_TX_10G_STATE(x) (((x) >> S_EEE_TX_10G_STATE) & M_EEE_TX_10G_STATE) + +#define S_EEE_RX_10G_STATE 8 +#define M_EEE_RX_10G_STATE 0x3U +#define V_EEE_RX_10G_STATE(x) ((x) << S_EEE_RX_10G_STATE) +#define G_EEE_RX_10G_STATE(x) (((x) >> S_EEE_RX_10G_STATE) & M_EEE_RX_10G_STATE) + +#define S_EEE_TX_1G_STATE 6 +#define M_EEE_TX_1G_STATE 0x3U +#define V_EEE_TX_1G_STATE(x) ((x) << S_EEE_TX_1G_STATE) +#define G_EEE_TX_1G_STATE(x) (((x) >> S_EEE_TX_1G_STATE) & M_EEE_TX_1G_STATE) + +#define S_EEE_RX_1G_STATE 4 +#define M_EEE_RX_1G_STATE 0x3U +#define V_EEE_RX_1G_STATE(x) ((x) << S_EEE_RX_1G_STATE) +#define G_EEE_RX_1G_STATE(x) (((x) >> S_EEE_RX_1G_STATE) & M_EEE_RX_1G_STATE) + +#define S_PMA_RX_REFRESH 3 +#define V_PMA_RX_REFRESH(x) ((x) << S_PMA_RX_REFRESH) +#define F_PMA_RX_REFRESH V_PMA_RX_REFRESH(1U) + +#define S_PMA_RX_QUIET 2 +#define V_PMA_RX_QUIET(x) ((x) << S_PMA_RX_QUIET) +#define F_PMA_RX_QUIET V_PMA_RX_QUIET(1U) + +#define S_PMA_TX_REFRESH 1 +#define V_PMA_TX_REFRESH(x) ((x) << S_PMA_TX_REFRESH) +#define F_PMA_TX_REFRESH V_PMA_TX_REFRESH(1U) + +#define S_PMA_TX_QUIET 0 +#define V_PMA_TX_QUIET(x) ((x) << S_PMA_TX_QUIET) +#define F_PMA_TX_QUIET V_PMA_TX_QUIET(1U) + +#define A_MAC_PORT_CGEN 0x91c + +#define S_CGEN 8 +#define V_CGEN(x) ((x) << S_CGEN) +#define F_CGEN V_CGEN(1U) + +#define S_SD7_CGEN 7 +#define V_SD7_CGEN(x) ((x) << S_SD7_CGEN) +#define F_SD7_CGEN V_SD7_CGEN(1U) + +#define S_SD6_CGEN 6 +#define V_SD6_CGEN(x) ((x) << S_SD6_CGEN) +#define F_SD6_CGEN V_SD6_CGEN(1U) + +#define S_SD5_CGEN 5 +#define V_SD5_CGEN(x) ((x) << S_SD5_CGEN) +#define F_SD5_CGEN V_SD5_CGEN(1U) + +#define S_SD4_CGEN 4 +#define V_SD4_CGEN(x) ((x) << S_SD4_CGEN) +#define F_SD4_CGEN V_SD4_CGEN(1U) + +#define S_SD3_CGEN 3 +#define V_SD3_CGEN(x) ((x) << S_SD3_CGEN) +#define F_SD3_CGEN V_SD3_CGEN(1U) + +#define S_SD2_CGEN 2 +#define V_SD2_CGEN(x) ((x) << S_SD2_CGEN) +#define F_SD2_CGEN V_SD2_CGEN(1U) + +#define S_SD1_CGEN 1 +#define V_SD1_CGEN(x) ((x) << S_SD1_CGEN) +#define F_SD1_CGEN V_SD1_CGEN(1U) + +#define S_SD0_CGEN 0 +#define V_SD0_CGEN(x) ((x) << S_SD0_CGEN) +#define F_SD0_CGEN V_SD0_CGEN(1U) + +#define A_MAC_PORT_CGEN_MTIP 0x920 + +#define S_MACSEG5_CGEN 11 +#define V_MACSEG5_CGEN(x) ((x) << S_MACSEG5_CGEN) +#define F_MACSEG5_CGEN V_MACSEG5_CGEN(1U) + +#define S_PCSSEG5_CGEN 10 +#define V_PCSSEG5_CGEN(x) ((x) << S_PCSSEG5_CGEN) +#define F_PCSSEG5_CGEN V_PCSSEG5_CGEN(1U) + +#define S_MACSEG4_CGEN 9 +#define V_MACSEG4_CGEN(x) ((x) << S_MACSEG4_CGEN) +#define F_MACSEG4_CGEN V_MACSEG4_CGEN(1U) + +#define S_PCSSEG4_CGEN 8 +#define V_PCSSEG4_CGEN(x) ((x) << S_PCSSEG4_CGEN) +#define F_PCSSEG4_CGEN V_PCSSEG4_CGEN(1U) + +#define S_MACSEG3_CGEN 7 +#define V_MACSEG3_CGEN(x) ((x) << S_MACSEG3_CGEN) +#define F_MACSEG3_CGEN V_MACSEG3_CGEN(1U) + +#define S_PCSSEG3_CGEN 6 +#define V_PCSSEG3_CGEN(x) ((x) << S_PCSSEG3_CGEN) +#define F_PCSSEG3_CGEN V_PCSSEG3_CGEN(1U) + +#define S_MACSEG2_CGEN 5 +#define V_MACSEG2_CGEN(x) ((x) << S_MACSEG2_CGEN) +#define F_MACSEG2_CGEN V_MACSEG2_CGEN(1U) + +#define S_PCSSEG2_CGEN 4 +#define V_PCSSEG2_CGEN(x) ((x) << S_PCSSEG2_CGEN) +#define F_PCSSEG2_CGEN V_PCSSEG2_CGEN(1U) + +#define S_MACSEG1_CGEN 3 +#define V_MACSEG1_CGEN(x) ((x) << S_MACSEG1_CGEN) +#define F_MACSEG1_CGEN V_MACSEG1_CGEN(1U) + +#define S_PCSSEG1_CGEN 2 +#define V_PCSSEG1_CGEN(x) ((x) << S_PCSSEG1_CGEN) +#define F_PCSSEG1_CGEN V_PCSSEG1_CGEN(1U) + +#define S_MACSEG0_CGEN 1 +#define V_MACSEG0_CGEN(x) ((x) << S_MACSEG0_CGEN) +#define F_MACSEG0_CGEN V_MACSEG0_CGEN(1U) + +#define S_PCSSEG0_CGEN 0 +#define V_PCSSEG0_CGEN(x) ((x) << S_PCSSEG0_CGEN) +#define F_PCSSEG0_CGEN V_PCSSEG0_CGEN(1U) + +#define A_MAC_PORT_TX_TS_ID 0x924 + +#define S_TS_ID 0 +#define M_TS_ID 0x7U +#define V_TS_ID(x) ((x) << S_TS_ID) +#define G_TS_ID(x) (((x) >> S_TS_ID) & M_TS_ID) + +#define A_MAC_PORT_TX_TS_VAL_LO 0x928 +#define A_MAC_PORT_TX_TS_VAL_HI 0x92c +#define A_MAC_PORT_EEE_CTL 0x930 + +#define S_EEE_CTRL 2 +#define M_EEE_CTRL 0x3fffffffU +#define V_EEE_CTRL(x) ((x) << S_EEE_CTRL) +#define G_EEE_CTRL(x) (((x) >> S_EEE_CTRL) & M_EEE_CTRL) + +#define S_TICK_START 1 +#define V_TICK_START(x) ((x) << S_TICK_START) +#define F_TICK_START V_TICK_START(1U) + +#define S_EEE_ENABLE 0 +#define V_EEE_ENABLE(x) ((x) << S_EEE_ENABLE) +#define F_EEE_ENABLE V_EEE_ENABLE(1U) + +#define A_MAC_PORT_EEE_TX_CTL 0x934 + +#define S_WAKE_TIMER 16 +#define M_WAKE_TIMER 0xffffU +#define V_WAKE_TIMER(x) ((x) << S_WAKE_TIMER) +#define G_WAKE_TIMER(x) (((x) >> S_WAKE_TIMER) & M_WAKE_TIMER) + +#define S_HSS_TIMER 5 +#define M_HSS_TIMER 0xfU +#define V_HSS_TIMER(x) ((x) << S_HSS_TIMER) +#define G_HSS_TIMER(x) (((x) >> S_HSS_TIMER) & M_HSS_TIMER) + +#define S_HSS_CTL 4 +#define V_HSS_CTL(x) ((x) << S_HSS_CTL) +#define F_HSS_CTL V_HSS_CTL(1U) + +#define S_LPI_ACTIVE 3 +#define V_LPI_ACTIVE(x) ((x) << S_LPI_ACTIVE) +#define F_LPI_ACTIVE V_LPI_ACTIVE(1U) + +#define S_LPI_TXHOLD 2 +#define V_LPI_TXHOLD(x) ((x) << S_LPI_TXHOLD) +#define F_LPI_TXHOLD V_LPI_TXHOLD(1U) + +#define S_LPI_REQ 1 +#define V_LPI_REQ(x) ((x) << S_LPI_REQ) +#define F_LPI_REQ V_LPI_REQ(1U) + +#define S_EEE_TX_RESET 0 +#define V_EEE_TX_RESET(x) ((x) << S_EEE_TX_RESET) +#define F_EEE_TX_RESET V_EEE_TX_RESET(1U) + +#define A_MAC_PORT_EEE_RX_CTL 0x938 + +#define S_LPI_IND 1 +#define V_LPI_IND(x) ((x) << S_LPI_IND) +#define F_LPI_IND V_LPI_IND(1U) + +#define S_EEE_RX_RESET 0 +#define V_EEE_RX_RESET(x) ((x) << S_EEE_RX_RESET) +#define F_EEE_RX_RESET V_EEE_RX_RESET(1U) + +#define A_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x93c +#define A_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x940 +#define A_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x944 +#define A_MAC_PORT_EEE_TX_1G_SLEEP_TIMER 0x948 +#define A_MAC_PORT_EEE_TX_1G_QUIET_TIMER 0x94c +#define A_MAC_PORT_EEE_TX_1G_REFRESH_TIMER 0x950 +#define A_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x954 +#define A_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x958 +#define A_MAC_PORT_EEE_RX_10G_WF_TIMER 0x95c +#define A_MAC_PORT_EEE_RX_1G_QUIET_TIMER 0x960 +#define A_MAC_PORT_EEE_RX_1G_WAKE_TIMER 0x964 +#define A_MAC_PORT_EEE_WF_COUNT 0x968 + +#define S_WAKE_CNT_CLR 16 +#define V_WAKE_CNT_CLR(x) ((x) << S_WAKE_CNT_CLR) +#define F_WAKE_CNT_CLR V_WAKE_CNT_CLR(1U) + +#define S_WAKE_CNT 0 +#define M_WAKE_CNT 0xffffU +#define V_WAKE_CNT(x) ((x) << S_WAKE_CNT) +#define G_WAKE_CNT(x) (((x) >> S_WAKE_CNT) & M_WAKE_CNT) + +#define A_MAC_PORT_PTP_TIMER_RD0_LO 0x96c +#define A_MAC_PORT_PTP_TIMER_RD0_HI 0x970 +#define A_MAC_PORT_PTP_TIMER_RD1_LO 0x974 +#define A_MAC_PORT_PTP_TIMER_RD1_HI 0x978 +#define A_MAC_PORT_PTP_TIMER_WR_LO 0x97c +#define A_MAC_PORT_PTP_TIMER_WR_HI 0x980 +#define A_MAC_PORT_PTP_TIMER_OFFSET_0 0x984 +#define A_MAC_PORT_PTP_TIMER_OFFSET_1 0x988 +#define A_MAC_PORT_PTP_TIMER_OFFSET_2 0x98c + +#define S_PTP_OFFSET 0 +#define M_PTP_OFFSET 0xffU +#define V_PTP_OFFSET(x) ((x) << S_PTP_OFFSET) +#define G_PTP_OFFSET(x) (((x) >> S_PTP_OFFSET) & M_PTP_OFFSET) + +#define A_MAC_PORT_PTP_SUM_LO 0x990 +#define A_MAC_PORT_PTP_SUM_HI 0x994 +#define A_MAC_PORT_PTP_TIMER_INCR0 0x998 + +#define S_Y 16 +#define M_Y 0xffffU +#define V_Y(x) ((x) << S_Y) +#define G_Y(x) (((x) >> S_Y) & M_Y) + +#define S_X 0 +#define M_X 0xffffU +#define V_X(x) ((x) << S_X) +#define G_X(x) (((x) >> S_X) & M_X) + +#define A_MAC_PORT_PTP_TIMER_INCR1 0x99c + +#define S_Y_TICK 16 +#define M_Y_TICK 0xffffU +#define V_Y_TICK(x) ((x) << S_Y_TICK) +#define G_Y_TICK(x) (((x) >> S_Y_TICK) & M_Y_TICK) + +#define S_X_TICK 0 +#define M_X_TICK 0xffffU +#define V_X_TICK(x) ((x) << S_X_TICK) +#define G_X_TICK(x) (((x) >> S_X_TICK) & M_X_TICK) + +#define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0 +#define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4 + +#define S_B 16 +#define M_B 0xffffU +#define V_B(x) ((x) << S_B) +#define G_B(x) (((x) >> S_B) & M_B) + +#define S_A 0 +#define M_A 0xffffU +#define V_A(x) ((x) << S_A) +#define G_A(x) (((x) >> S_A) & M_A) + +#define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8 +#define A_MAC_PORT_PTP_CFG 0x9ac + +#define S_FRZ 18 +#define V_FRZ(x) ((x) << S_FRZ) +#define F_FRZ V_FRZ(1U) + +#define S_OFFSER_ADJUST_SIGN 17 +#define V_OFFSER_ADJUST_SIGN(x) ((x) << S_OFFSER_ADJUST_SIGN) +#define F_OFFSER_ADJUST_SIGN V_OFFSER_ADJUST_SIGN(1U) + +#define S_ADD_OFFSET 16 +#define V_ADD_OFFSET(x) ((x) << S_ADD_OFFSET) +#define F_ADD_OFFSET V_ADD_OFFSET(1U) + +#define S_CYCLE1 8 +#define M_CYCLE1 0xffU +#define V_CYCLE1(x) ((x) << S_CYCLE1) +#define G_CYCLE1(x) (((x) >> S_CYCLE1) & M_CYCLE1) + +#define S_Q 0 +#define M_Q 0xffU +#define V_Q(x) ((x) << S_Q) +#define G_Q(x) (((x) >> S_Q) & M_Q) + +#define A_MAC_PORT_MTIP_REVISION 0xa00 + +#define S_CUSTREV 16 +#define M_CUSTREV 0xffffU +#define V_CUSTREV(x) ((x) << S_CUSTREV) +#define G_CUSTREV(x) (((x) >> S_CUSTREV) & M_CUSTREV) + +#define S_VER 8 +#define M_VER 0xffU +#define V_VER(x) ((x) << S_VER) +#define G_VER(x) (((x) >> S_VER) & M_VER) + +#define S_MTIP_REV 0 +#define M_MTIP_REV 0xffU +#define V_MTIP_REV(x) ((x) << S_MTIP_REV) +#define G_MTIP_REV(x) (((x) >> S_MTIP_REV) & M_MTIP_REV) + +#define A_MAC_PORT_MTIP_SCRATCH 0xa04 +#define A_MAC_PORT_MTIP_COMMAND_CONFIG 0xa08 + +#define S_TX_FLUSH_ENABLE 22 +#define V_TX_FLUSH_ENABLE(x) ((x) << S_TX_FLUSH_ENABLE) +#define F_TX_FLUSH_ENABLE V_TX_FLUSH_ENABLE(1U) + +#define S_RX_SFD_ANY 21 +#define V_RX_SFD_ANY(x) ((x) << S_RX_SFD_ANY) +#define F_RX_SFD_ANY V_RX_SFD_ANY(1U) + +#define S_PAUSE_PFC_COMP 20 +#define V_PAUSE_PFC_COMP(x) ((x) << S_PAUSE_PFC_COMP) +#define F_PAUSE_PFC_COMP V_PAUSE_PFC_COMP(1U) + +#define S_PFC_MODE 19 +#define V_PFC_MODE(x) ((x) << S_PFC_MODE) +#define F_PFC_MODE V_PFC_MODE(1U) + +#define S_RS_COL_CNT_EXT 18 +#define V_RS_COL_CNT_EXT(x) ((x) << S_RS_COL_CNT_EXT) +#define F_RS_COL_CNT_EXT V_RS_COL_CNT_EXT(1U) + +#define S_NO_LGTH_CHECK 17 +#define V_NO_LGTH_CHECK(x) ((x) << S_NO_LGTH_CHECK) +#define F_NO_LGTH_CHECK V_NO_LGTH_CHECK(1U) + +#define S_SEND_IDLE 16 +#define V_SEND_IDLE(x) ((x) << S_SEND_IDLE) +#define F_SEND_IDLE V_SEND_IDLE(1U) + +#define S_PHY_TXENA 15 +#define V_PHY_TXENA(x) ((x) << S_PHY_TXENA) +#define F_PHY_TXENA V_PHY_TXENA(1U) + +#define S_RX_ERR_DISC 14 +#define V_RX_ERR_DISC(x) ((x) << S_RX_ERR_DISC) +#define F_RX_ERR_DISC V_RX_ERR_DISC(1U) + +#define S_CMD_FRAME_ENA 13 +#define V_CMD_FRAME_ENA(x) ((x) << S_CMD_FRAME_ENA) +#define F_CMD_FRAME_ENA V_CMD_FRAME_ENA(1U) + +#define S_SW_RESET 12 +#define V_SW_RESET(x) ((x) << S_SW_RESET) +#define F_SW_RESET V_SW_RESET(1U) + +#define S_TX_PAD_EN 11 +#define V_TX_PAD_EN(x) ((x) << S_TX_PAD_EN) +#define F_TX_PAD_EN V_TX_PAD_EN(1U) + +#define S_PHY_LOOPBACK_EN 10 +#define V_PHY_LOOPBACK_EN(x) ((x) << S_PHY_LOOPBACK_EN) +#define F_PHY_LOOPBACK_EN V_PHY_LOOPBACK_EN(1U) + +#define S_TX_ADDR_INS 9 +#define V_TX_ADDR_INS(x) ((x) << S_TX_ADDR_INS) +#define F_TX_ADDR_INS V_TX_ADDR_INS(1U) + +#define S_PAUSE_IGNORE 8 +#define V_PAUSE_IGNORE(x) ((x) << S_PAUSE_IGNORE) +#define F_PAUSE_IGNORE V_PAUSE_IGNORE(1U) + +#define S_PAUSE_FWD 7 +#define V_PAUSE_FWD(x) ((x) << S_PAUSE_FWD) +#define F_PAUSE_FWD V_PAUSE_FWD(1U) + +#define S_CRC_FWD 6 +#define V_CRC_FWD(x) ((x) << S_CRC_FWD) +#define F_CRC_FWD V_CRC_FWD(1U) + +#define S_PAD_EN 5 +#define V_PAD_EN(x) ((x) << S_PAD_EN) +#define F_PAD_EN V_PAD_EN(1U) + +#define S_PROMIS_EN 4 +#define V_PROMIS_EN(x) ((x) << S_PROMIS_EN) +#define F_PROMIS_EN V_PROMIS_EN(1U) + +#define S_WAN_MODE 3 +#define V_WAN_MODE(x) ((x) << S_WAN_MODE) +#define F_WAN_MODE V_WAN_MODE(1U) + +#define S_RX_ENA 1 +#define V_RX_ENA(x) ((x) << S_RX_ENA) +#define F_RX_ENA V_RX_ENA(1U) + +#define S_TX_ENA 0 +#define V_TX_ENA(x) ((x) << S_TX_ENA) +#define F_TX_ENA V_TX_ENA(1U) + +#define A_MAC_PORT_MTIP_MAC_ADDR_0 0xa0c +#define A_MAC_PORT_MTIP_MAC_ADDR_1 0xa10 + +#define S_MACADDRHI 0 +#define M_MACADDRHI 0xffffU +#define V_MACADDRHI(x) ((x) << S_MACADDRHI) +#define G_MACADDRHI(x) (((x) >> S_MACADDRHI) & M_MACADDRHI) + +#define A_MAC_PORT_MTIP_FRM_LENGTH 0xa14 + +#define S_LEN 0 +#define M_LEN 0xffffU +#define V_LEN(x) ((x) << S_LEN) +#define G_LEN(x) (((x) >> S_LEN) & M_LEN) + +#define A_MAC_PORT_MTIP_RX_FIFO_SECTIONS 0xa1c + +#define S_AVAIL 16 +#define M_AVAIL 0xffffU +#define V_AVAIL(x) ((x) << S_AVAIL) +#define G_AVAIL(x) (((x) >> S_AVAIL) & M_AVAIL) + +#define S_EMPTY 0 +#define M_EMPTY 0xffffU +#define V_EMPTY(x) ((x) << S_EMPTY) +#define G_EMPTY(x) (((x) >> S_EMPTY) & M_EMPTY) + +#define A_MAC_PORT_MTIP_TX_FIFO_SECTIONS 0xa20 +#define A_MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E 0xa24 + +#define S_ALMSTFULL 16 +#define M_ALMSTFULL 0xffffU +#define V_ALMSTFULL(x) ((x) << S_ALMSTFULL) +#define G_ALMSTFULL(x) (((x) >> S_ALMSTFULL) & M_ALMSTFULL) + +#define S_ALMSTEMPTY 0 +#define M_ALMSTEMPTY 0xffffU +#define V_ALMSTEMPTY(x) ((x) << S_ALMSTEMPTY) +#define G_ALMSTEMPTY(x) (((x) >> S_ALMSTEMPTY) & M_ALMSTEMPTY) + +#define A_MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E 0xa28 +#define A_MAC_PORT_MTIP_HASHTABLE_LOAD 0xa2c + +#define S_ENABLE_MCAST_RX 8 +#define V_ENABLE_MCAST_RX(x) ((x) << S_ENABLE_MCAST_RX) +#define F_ENABLE_MCAST_RX V_ENABLE_MCAST_RX(1U) + +#define S_HASHTABLE_ADDR 0 +#define M_HASHTABLE_ADDR 0x3fU +#define V_HASHTABLE_ADDR(x) ((x) << S_HASHTABLE_ADDR) +#define G_HASHTABLE_ADDR(x) (((x) >> S_HASHTABLE_ADDR) & M_HASHTABLE_ADDR) + +#define A_MAC_PORT_MTIP_MAC_STATUS 0xa40 + +#define S_TS_AVAIL 3 +#define V_TS_AVAIL(x) ((x) << S_TS_AVAIL) +#define F_TS_AVAIL V_TS_AVAIL(1U) + +#define S_PHY_LOS 2 +#define V_PHY_LOS(x) ((x) << S_PHY_LOS) +#define F_PHY_LOS V_PHY_LOS(1U) + +#define S_RX_REM_FAULT 1 +#define V_RX_REM_FAULT(x) ((x) << S_RX_REM_FAULT) +#define F_RX_REM_FAULT V_RX_REM_FAULT(1U) + +#define S_RX_LOC_FAULT 0 +#define V_RX_LOC_FAULT(x) ((x) << S_RX_LOC_FAULT) +#define F_RX_LOC_FAULT V_RX_LOC_FAULT(1U) + +#define A_MAC_PORT_MTIP_TX_IPG_LENGTH 0xa44 + +#define S_IPG 0 +#define M_IPG 0x7fU +#define V_IPG(x) ((x) << S_IPG) +#define G_IPG(x) (((x) >> S_IPG) & M_IPG) + +#define A_MAC_PORT_MTIP_MAC_CREDIT_TRIGGER 0xa48 + +#define S_RXFIFORST 0 +#define V_RXFIFORST(x) ((x) << S_RXFIFORST) +#define F_RXFIFORST V_RXFIFORST(1U) + +#define A_MAC_PORT_MTIP_INIT_CREDIT 0xa4c + +#define S_MACCRDRST 0 +#define M_MACCRDRST 0xffU +#define V_MACCRDRST(x) ((x) << S_MACCRDRST) +#define G_MACCRDRST(x) (((x) >> S_MACCRDRST) & M_MACCRDRST) + +#define A_MAC_PORT_MTIP_CURRENT_CREDIT 0xa50 + +#define S_INITCREDIT 0 +#define M_INITCREDIT 0xffU +#define V_INITCREDIT(x) ((x) << S_INITCREDIT) +#define G_INITCREDIT(x) (((x) >> S_INITCREDIT) & M_INITCREDIT) + +#define A_MAC_PORT_RX_PAUSE_STATUS 0xa74 + +#define S_STATUS 0 +#define M_STATUS 0xffU +#define V_STATUS(x) ((x) << S_STATUS) +#define G_STATUS(x) (((x) >> S_STATUS) & M_STATUS) + +#define A_MAC_PORT_MTIP_TS_TIMESTAMP 0xa7c +#define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80 +#define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84 +#define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88 +#define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c +#define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS 0xa90 +#define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI 0xa94 +#define A_MAC_PORT_AALIGNMENTERRORS 0xa98 +#define A_MAC_PORT_AALIGNMENTERRORSHI 0xa9c +#define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED 0xaa0 +#define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI 0xaa4 +#define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED 0xaa8 +#define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI 0xaac +#define A_MAC_PORT_AFRAMETOOLONGERRORS 0xab0 +#define A_MAC_PORT_AFRAMETOOLONGERRORSHI 0xab4 +#define A_MAC_PORT_AINRANGELENGTHERRORS 0xab8 +#define A_MAC_PORT_AINRANGELENGTHERRORSHI 0xabc +#define A_MAC_PORT_VLANTRANSMITTEDOK 0xac0 +#define A_MAC_PORT_VLANTRANSMITTEDOKHI 0xac4 +#define A_MAC_PORT_VLANRECEIVEDOK 0xac8 +#define A_MAC_PORT_VLANRECEIVEDOKHI 0xacc +#define A_MAC_PORT_AOCTETSTRANSMITTEDOK 0xad0 +#define A_MAC_PORT_AOCTETSTRANSMITTEDOKHI 0xad4 +#define A_MAC_PORT_AOCTETSRECEIVEDOK 0xad8 +#define A_MAC_PORT_AOCTETSRECEIVEDOKHI 0xadc +#define A_MAC_PORT_IFINUCASTPKTS 0xae0 +#define A_MAC_PORT_IFINUCASTPKTSHI 0xae4 +#define A_MAC_PORT_IFINMULTICASTPKTS 0xae8 +#define A_MAC_PORT_IFINMULTICASTPKTSHI 0xaec +#define A_MAC_PORT_IFINBROADCASTPKTS 0xaf0 +#define A_MAC_PORT_IFINBROADCASTPKTSHI 0xaf4 +#define A_MAC_PORT_IFOUTERRORS 0xaf8 +#define A_MAC_PORT_IFOUTERRORSHI 0xafc +#define A_MAC_PORT_IFOUTUCASTPKTS 0xb08 +#define A_MAC_PORT_IFOUTUCASTPKTSHI 0xb0c +#define A_MAC_PORT_IFOUTMULTICASTPKTS 0xb10 +#define A_MAC_PORT_IFOUTMULTICASTPKTSHI 0xb14 +#define A_MAC_PORT_IFOUTBROADCASTPKTS 0xb18 +#define A_MAC_PORT_IFOUTBROADCASTPKTSHI 0xb1c +#define A_MAC_PORT_ETHERSTATSDROPEVENTS 0xb20 +#define A_MAC_PORT_ETHERSTATSDROPEVENTSHI 0xb24 +#define A_MAC_PORT_ETHERSTATSOCTETS 0xb28 +#define A_MAC_PORT_ETHERSTATSOCTETSHI 0xb2c +#define A_MAC_PORT_ETHERSTATSPKTS 0xb30 +#define A_MAC_PORT_ETHERSTATSPKTSHI 0xb34 +#define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTS 0xb38 +#define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI 0xb3c +#define A_MAC_PORT_ETHERSTATSPKTS64OCTETS 0xb40 +#define A_MAC_PORT_ETHERSTATSPKTS64OCTETSHI 0xb44 +#define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETS 0xb48 +#define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI 0xb4c +#define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETS 0xb50 +#define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI 0xb54 +#define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETS 0xb58 +#define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI 0xb5c +#define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS 0xb60 +#define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI 0xb64 +#define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS 0xb68 +#define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI 0xb6c +#define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS 0xb70 +#define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI 0xb74 +#define A_MAC_PORT_ETHERSTATSOVERSIZEPKTS 0xb78 +#define A_MAC_PORT_ETHERSTATSOVERSIZEPKTSHI 0xb7c +#define A_MAC_PORT_ETHERSTATSJABBERS 0xb80 +#define A_MAC_PORT_ETHERSTATSJABBERSHI 0xb84 +#define A_MAC_PORT_ETHERSTATSFRAGMENTS 0xb88 +#define A_MAC_PORT_ETHERSTATSFRAGMENTSHI 0xb8c +#define A_MAC_PORT_IFINERRORS 0xb90 +#define A_MAC_PORT_IFINERRORSHI 0xb94 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 0xb98 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI 0xb9c +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 0xba0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI 0xba4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 0xba8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI 0xbac +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 0xbb0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI 0xbb4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 0xbb8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI 0xbbc +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 0xbc0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI 0xbc4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 0xbc8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI 0xbcc +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 0xbd0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI 0xbd4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 0xbd8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI 0xbdc +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 0xbe0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI 0xbe4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 0xbe8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 0xbec +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 0xbf0 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI 0xbf4 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 0xbf8 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI 0xbfc +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 0xc00 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI 0xc04 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 0xc08 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI 0xc0c +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 0xc10 +#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI 0xc14 +#define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTED 0xc18 +#define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI 0xc1c +#define A_MAC_PORT_AMACCONTROLFRAMESRECEIVED 0xc20 +#define A_MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI 0xc24 +#define A_MAC_PORT_MTIP_SGMII_CONTROL 0xd00 + +#define S_RESET 15 +#define V_RESET(x) ((x) << S_RESET) +#define F_RESET V_RESET(1U) + +#define S_LOOPBACK 14 +#define V_LOOPBACK(x) ((x) << S_LOOPBACK) +#define F_LOOPBACK V_LOOPBACK(1U) + +#define S_SPPEDSEL1 13 +#define V_SPPEDSEL1(x) ((x) << S_SPPEDSEL1) +#define F_SPPEDSEL1 V_SPPEDSEL1(1U) + +#define S_AN_EN 12 +#define V_AN_EN(x) ((x) << S_AN_EN) +#define F_AN_EN V_AN_EN(1U) + +#define S_PWRDWN 11 +#define V_PWRDWN(x) ((x) << S_PWRDWN) +#define F_PWRDWN V_PWRDWN(1U) + +#define S_ISOLATE 10 +#define V_ISOLATE(x) ((x) << S_ISOLATE) +#define F_ISOLATE V_ISOLATE(1U) + +#define S_AN_RESTART 9 +#define V_AN_RESTART(x) ((x) << S_AN_RESTART) +#define F_AN_RESTART V_AN_RESTART(1U) + +#define S_DPLX 8 +#define V_DPLX(x) ((x) << S_DPLX) +#define F_DPLX V_DPLX(1U) + +#define S_COLLISIONTEST 7 +#define V_COLLISIONTEST(x) ((x) << S_COLLISIONTEST) +#define F_COLLISIONTEST V_COLLISIONTEST(1U) + +#define S_SPEEDSEL0 6 +#define V_SPEEDSEL0(x) ((x) << S_SPEEDSEL0) +#define F_SPEEDSEL0 V_SPEEDSEL0(1U) + +#define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04 + +#define S_100BASET4 15 +#define V_100BASET4(x) ((x) << S_100BASET4) +#define F_100BASET4 V_100BASET4(1U) + +#define S_100BASEXFULLDPLX 14 +#define V_100BASEXFULLDPLX(x) ((x) << S_100BASEXFULLDPLX) +#define F_100BASEXFULLDPLX V_100BASEXFULLDPLX(1U) + +#define S_100BASEXHALFDPLX 13 +#define V_100BASEXHALFDPLX(x) ((x) << S_100BASEXHALFDPLX) +#define F_100BASEXHALFDPLX V_100BASEXHALFDPLX(1U) + +#define S_10MBPSFULLDPLX 12 +#define V_10MBPSFULLDPLX(x) ((x) << S_10MBPSFULLDPLX) +#define F_10MBPSFULLDPLX V_10MBPSFULLDPLX(1U) + +#define S_10MBPSHALFDPLX 11 +#define V_10MBPSHALFDPLX(x) ((x) << S_10MBPSHALFDPLX) +#define F_10MBPSHALFDPLX V_10MBPSHALFDPLX(1U) + +#define S_100BASET2FULLDPLX 10 +#define V_100BASET2FULLDPLX(x) ((x) << S_100BASET2FULLDPLX) +#define F_100BASET2FULLDPLX V_100BASET2FULLDPLX(1U) + +#define S_100BASET2HALFDPLX 9 +#define V_100BASET2HALFDPLX(x) ((x) << S_100BASET2HALFDPLX) +#define F_100BASET2HALFDPLX V_100BASET2HALFDPLX(1U) + +#define S_EXTDSTATUS 8 +#define V_EXTDSTATUS(x) ((x) << S_EXTDSTATUS) +#define F_EXTDSTATUS V_EXTDSTATUS(1U) + +#define S_SGMII_REM_FAULT 4 +#define V_SGMII_REM_FAULT(x) ((x) << S_SGMII_REM_FAULT) +#define F_SGMII_REM_FAULT V_SGMII_REM_FAULT(1U) + +#define S_JABBERDETECT 1 +#define V_JABBERDETECT(x) ((x) << S_JABBERDETECT) +#define F_JABBERDETECT V_JABBERDETECT(1U) + +#define S_EXTDCAPABILITY 0 +#define V_EXTDCAPABILITY(x) ((x) << S_EXTDCAPABILITY) +#define F_EXTDCAPABILITY V_EXTDCAPABILITY(1U) + +#define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08 +#define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c +#define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10 + +#define S_RF2 13 +#define V_RF2(x) ((x) << S_RF2) +#define F_RF2 V_RF2(1U) + +#define S_RF1 12 +#define V_RF1(x) ((x) << S_RF1) +#define F_RF1 V_RF1(1U) + +#define S_PS2 8 +#define V_PS2(x) ((x) << S_PS2) +#define F_PS2 V_PS2(1U) + +#define S_PS1 7 +#define V_PS1(x) ((x) << S_PS1) +#define F_PS1 V_PS1(1U) + +#define S_HD 6 +#define V_HD(x) ((x) << S_HD) +#define F_HD V_HD(1U) + +#define S_FD 5 +#define V_FD(x) ((x) << S_FD) +#define F_FD V_FD(1U) + +#define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14 + +#define S_CULINKSTATUS 15 +#define V_CULINKSTATUS(x) ((x) << S_CULINKSTATUS) +#define F_CULINKSTATUS V_CULINKSTATUS(1U) + +#define S_CUDPLXSTATUS 12 +#define V_CUDPLXSTATUS(x) ((x) << S_CUDPLXSTATUS) +#define F_CUDPLXSTATUS V_CUDPLXSTATUS(1U) + +#define S_CUSPEED 10 +#define M_CUSPEED 0x3U +#define V_CUSPEED(x) ((x) << S_CUSPEED) +#define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED) + +#define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18 + +#define S_PGRCVD 1 +#define V_PGRCVD(x) ((x) << S_PGRCVD) +#define F_PGRCVD V_PGRCVD(1U) + +#define S_REALTIMEPGRCVD 0 +#define V_REALTIMEPGRCVD(x) ((x) << S_REALTIMEPGRCVD) +#define F_REALTIMEPGRCVD V_REALTIMEPGRCVD(1U) + +#define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c +#define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20 +#define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c +#define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48 + +#define S_COUNT_LO 0 +#define M_COUNT_LO 0xffffU +#define V_COUNT_LO(x) ((x) << S_COUNT_LO) +#define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO) + +#define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c + +#define S_COUNT_HI 0 +#define M_COUNT_HI 0x1fU +#define V_COUNT_HI(x) ((x) << S_COUNT_HI) +#define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI) + +#define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50 + +#define S_SGMII_PCS_ENABLE 5 +#define V_SGMII_PCS_ENABLE(x) ((x) << S_SGMII_PCS_ENABLE) +#define F_SGMII_PCS_ENABLE V_SGMII_PCS_ENABLE(1U) + +#define S_SGMII_HDUPLEX 4 +#define V_SGMII_HDUPLEX(x) ((x) << S_SGMII_HDUPLEX) +#define F_SGMII_HDUPLEX V_SGMII_HDUPLEX(1U) + +#define S_SGMII_SPEED 2 +#define M_SGMII_SPEED 0x3U +#define V_SGMII_SPEED(x) ((x) << S_SGMII_SPEED) +#define G_SGMII_SPEED(x) (((x) >> S_SGMII_SPEED) & M_SGMII_SPEED) + +#define S_USE_SGMII_AN 1 +#define V_USE_SGMII_AN(x) ((x) << S_USE_SGMII_AN) +#define F_USE_SGMII_AN V_USE_SGMII_AN(1U) + +#define S_SGMII_ENA 0 +#define V_SGMII_ENA(x) ((x) << S_SGMII_ENA) +#define F_SGMII_ENA V_SGMII_ENA(1U) + +#define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200 + +#define S_ACTIVE 0 +#define M_ACTIVE 0x3fU +#define V_ACTIVE(x) ((x) << S_ACTIVE) +#define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE) + +#define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204 + +#define S_MODE_CTL 0 +#define M_MODE_CTL 0x3U +#define V_MODE_CTL(x) ((x) << S_MODE_CTL) +#define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL) + +#define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208 + +#define S_TXCLK_CTL 0 +#define M_TXCLK_CTL 0xffffU +#define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL) +#define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL) + +#define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c +#define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220 + +#define S_COL_CNT 0 +#define M_COL_CNT 0xffffU +#define V_COL_CNT(x) ((x) << S_COL_CNT) +#define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT) + +#define A_MAC_PORT_MTIP_VL_INTVL 0x1240 + +#define S_VL_INTVL 1 +#define V_VL_INTVL(x) ((x) << S_VL_INTVL) +#define F_VL_INTVL V_VL_INTVL(1U) + +#define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600 + +#define S_CLK_DIV 7 +#define M_CLK_DIV 0x1ffU +#define V_CLK_DIV(x) ((x) << S_CLK_DIV) +#define G_CLK_DIV(x) (((x) >> S_CLK_DIV) & M_CLK_DIV) + +#define S_CL45_EN 6 +#define V_CL45_EN(x) ((x) << S_CL45_EN) +#define F_CL45_EN V_CL45_EN(1U) + +#define S_DISABLE_PREAMBLE 5 +#define V_DISABLE_PREAMBLE(x) ((x) << S_DISABLE_PREAMBLE) +#define F_DISABLE_PREAMBLE V_DISABLE_PREAMBLE(1U) + +#define S_MDIO_HOLD_TIME 2 +#define M_MDIO_HOLD_TIME 0x7U +#define V_MDIO_HOLD_TIME(x) ((x) << S_MDIO_HOLD_TIME) +#define G_MDIO_HOLD_TIME(x) (((x) >> S_MDIO_HOLD_TIME) & M_MDIO_HOLD_TIME) + +#define S_MDIO_READ_ERR 1 +#define V_MDIO_READ_ERR(x) ((x) << S_MDIO_READ_ERR) +#define F_MDIO_READ_ERR V_MDIO_READ_ERR(1U) + +#define S_MDIO_BUSY 0 +#define V_MDIO_BUSY(x) ((x) << S_MDIO_BUSY) +#define F_MDIO_BUSY V_MDIO_BUSY(1U) + +#define A_MAC_PORT_MTIP_MDIO_COMMAND 0x1604 + +#define S_MDIO_CMD_READ 15 +#define V_MDIO_CMD_READ(x) ((x) << S_MDIO_CMD_READ) +#define F_MDIO_CMD_READ V_MDIO_CMD_READ(1U) + +#define S_READ_INCR 14 +#define V_READ_INCR(x) ((x) << S_READ_INCR) +#define F_READ_INCR V_READ_INCR(1U) + +#define S_PORT_ADDR 5 +#define M_PORT_ADDR 0x1fU +#define V_PORT_ADDR(x) ((x) << S_PORT_ADDR) +#define G_PORT_ADDR(x) (((x) >> S_PORT_ADDR) & M_PORT_ADDR) + +#define S_DEV_ADDR 0 +#define M_DEV_ADDR 0x1fU +#define V_DEV_ADDR(x) ((x) << S_DEV_ADDR) +#define G_DEV_ADDR(x) (((x) >> S_DEV_ADDR) & M_DEV_ADDR) + +#define A_MAC_PORT_MTIP_MDIO_DATA 0x1608 + +#define S_READBUSY 31 +#define V_READBUSY(x) ((x) << S_READBUSY) +#define F_READBUSY V_READBUSY(1U) + +#define S_DATA_WORD 0 +#define M_DATA_WORD 0xffffU +#define V_DATA_WORD(x) ((x) << S_DATA_WORD) +#define G_DATA_WORD(x) (((x) >> S_DATA_WORD) & M_DATA_WORD) + +#define A_MAC_PORT_MTIP_MDIO_REGADDR 0x160c + +#define S_MDIO_ADDR 0 +#define M_MDIO_ADDR 0xffffU +#define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR) +#define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR) + +#define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00 + +#define S_VLANTAG 0 +#define M_VLANTAG 0xffffU +#define V_VLANTAG(x) ((x) << S_VLANTAG) +#define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG) + +#define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04 +#define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08 +#define A_MAC_PORT_MTIP_VLAN_TPID_3 0x1a0c +#define A_MAC_PORT_MTIP_VLAN_TPID_4 0x1a10 +#define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14 +#define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18 +#define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c +#define A_MAC_PORT_MTIP_PCS_CTL 0x1e00 + +#define S_PCS_LPBK 14 +#define V_PCS_LPBK(x) ((x) << S_PCS_LPBK) +#define F_PCS_LPBK V_PCS_LPBK(1U) + +#define S_SPEED_SEL1 13 +#define V_SPEED_SEL1(x) ((x) << S_SPEED_SEL1) +#define F_SPEED_SEL1 V_SPEED_SEL1(1U) + +#define S_LP_MODE 11 +#define V_LP_MODE(x) ((x) << S_LP_MODE) +#define F_LP_MODE V_LP_MODE(1U) + +#define S_SPEED_SEL0 6 +#define V_SPEED_SEL0(x) ((x) << S_SPEED_SEL0) +#define F_SPEED_SEL0 V_SPEED_SEL0(1U) + +#define S_PCS_SPEED 2 +#define M_PCS_SPEED 0xfU +#define V_PCS_SPEED(x) ((x) << S_PCS_SPEED) +#define G_PCS_SPEED(x) (((x) >> S_PCS_SPEED) & M_PCS_SPEED) + +#define A_MAC_PORT_MTIP_PCS_STATUS1 0x1e04 + +#define S_FAULTDET 7 +#define V_FAULTDET(x) ((x) << S_FAULTDET) +#define F_FAULTDET V_FAULTDET(1U) + +#define S_RX_LINK_STATUS 2 +#define V_RX_LINK_STATUS(x) ((x) << S_RX_LINK_STATUS) +#define F_RX_LINK_STATUS V_RX_LINK_STATUS(1U) + +#define S_LOPWRABL 1 +#define V_LOPWRABL(x) ((x) << S_LOPWRABL) +#define F_LOPWRABL V_LOPWRABL(1U) + +#define A_MAC_PORT_MTIP_PCS_DEVICE_ID0 0x1e08 + +#define S_DEVICE_ID0 0 +#define M_DEVICE_ID0 0xffffU +#define V_DEVICE_ID0(x) ((x) << S_DEVICE_ID0) +#define G_DEVICE_ID0(x) (((x) >> S_DEVICE_ID0) & M_DEVICE_ID0) + +#define A_MAC_PORT_MTIP_PCS_DEVICE_ID1 0x1e0c + +#define S_DEVICE_ID1 0 +#define M_DEVICE_ID1 0xffffU +#define V_DEVICE_ID1(x) ((x) << S_DEVICE_ID1) +#define G_DEVICE_ID1(x) (((x) >> S_DEVICE_ID1) & M_DEVICE_ID1) + +#define A_MAC_PORT_MTIP_PCS_SPEED_ABILITY 0x1e10 + +#define S_100G 8 +#define V_100G(x) ((x) << S_100G) +#define F_100G V_100G(1U) + +#define S_40G 7 +#define V_40G(x) ((x) << S_40G) +#define F_40G V_40G(1U) + +#define S_10BASE_TL 1 +#define V_10BASE_TL(x) ((x) << S_10BASE_TL) +#define F_10BASE_TL V_10BASE_TL(1U) + +#define S_10G 0 +#define V_10G(x) ((x) << S_10G) +#define F_10G V_10G(1U) + +#define A_MAC_PORT_MTIP_PCS_DEVICE_PKG1 0x1e14 + +#define S_TC_PRESENT 6 +#define V_TC_PRESENT(x) ((x) << S_TC_PRESENT) +#define F_TC_PRESENT V_TC_PRESENT(1U) + +#define S_DTEXS 5 +#define V_DTEXS(x) ((x) << S_DTEXS) +#define F_DTEXS V_DTEXS(1U) + +#define S_PHYXS 4 +#define V_PHYXS(x) ((x) << S_PHYXS) +#define F_PHYXS V_PHYXS(1U) + +#define S_PCS 3 +#define V_PCS(x) ((x) << S_PCS) +#define F_PCS V_PCS(1U) + +#define S_WIS 2 +#define V_WIS(x) ((x) << S_WIS) +#define F_WIS V_WIS(1U) + +#define S_PMD_PMA 1 +#define V_PMD_PMA(x) ((x) << S_PMD_PMA) +#define F_PMD_PMA V_PMD_PMA(1U) + +#define S_CL22 0 +#define V_CL22(x) ((x) << S_CL22) +#define F_CL22 V_CL22(1U) + +#define A_MAC_PORT_MTIP_PCS_DEVICE_PKG2 0x1e18 + +#define S_VENDDEV2 15 +#define V_VENDDEV2(x) ((x) << S_VENDDEV2) +#define F_VENDDEV2 V_VENDDEV2(1U) + +#define S_VENDDEV1 14 +#define V_VENDDEV1(x) ((x) << S_VENDDEV1) +#define F_VENDDEV1 V_VENDDEV1(1U) + +#define S_CL22EXT 13 +#define V_CL22EXT(x) ((x) << S_CL22EXT) +#define F_CL22EXT V_CL22EXT(1U) + +#define A_MAC_PORT_MTIP_PCS_CTL2 0x1e1c + +#define S_PCSTYPE 0 +#define M_PCSTYPE 0x7U +#define V_PCSTYPE(x) ((x) << S_PCSTYPE) +#define G_PCSTYPE(x) (((x) >> S_PCSTYPE) & M_PCSTYPE) + +#define A_MAC_PORT_MTIP_PCS_STATUS2 0x1e20 + +#define S_PCS_STAT2_DEVICE 15 +#define V_PCS_STAT2_DEVICE(x) ((x) << S_PCS_STAT2_DEVICE) +#define F_PCS_STAT2_DEVICE V_PCS_STAT2_DEVICE(1U) + +#define S_TXFAULT 7 +#define V_TXFAULT(x) ((x) << S_TXFAULT) +#define F_TXFAULT V_TXFAULT(1U) + +#define S_RXFAULT 6 +#define V_RXFAULT(x) ((x) << S_RXFAULT) +#define F_RXFAULT V_RXFAULT(1U) + +#define S_100BASE_R 5 +#define V_100BASE_R(x) ((x) << S_100BASE_R) +#define F_100BASE_R V_100BASE_R(1U) + +#define S_40GBASE_R 4 +#define V_40GBASE_R(x) ((x) << S_40GBASE_R) +#define F_40GBASE_R V_40GBASE_R(1U) + +#define S_10GBASE_T 3 +#define V_10GBASE_T(x) ((x) << S_10GBASE_T) +#define F_10GBASE_T V_10GBASE_T(1U) + +#define S_10GBASE_W 2 +#define V_10GBASE_W(x) ((x) << S_10GBASE_W) +#define F_10GBASE_W V_10GBASE_W(1U) + +#define S_10GBASE_X 1 +#define V_10GBASE_X(x) ((x) << S_10GBASE_X) +#define F_10GBASE_X V_10GBASE_X(1U) + +#define S_10GBASE_R 0 +#define V_10GBASE_R(x) ((x) << S_10GBASE_R) +#define F_10GBASE_R V_10GBASE_R(1U) + +#define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38 + +#define S_PKG_ID0 0 +#define M_PKG_ID0 0xffffU +#define V_PKG_ID0(x) ((x) << S_PKG_ID0) +#define G_PKG_ID0(x) (((x) >> S_PKG_ID0) & M_PKG_ID0) + +#define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c + +#define S_PKG_ID1 0 +#define M_PKG_ID1 0xffffU +#define V_PKG_ID1(x) ((x) << S_PKG_ID1) +#define G_PKG_ID1(x) (((x) >> S_PKG_ID1) & M_PKG_ID1) + +#define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80 + +#define S_RXLINKSTATUS 12 +#define V_RXLINKSTATUS(x) ((x) << S_RXLINKSTATUS) +#define F_RXLINKSTATUS V_RXLINKSTATUS(1U) + +#define S_RESEREVED 4 +#define M_RESEREVED 0xffU +#define V_RESEREVED(x) ((x) << S_RESEREVED) +#define G_RESEREVED(x) (((x) >> S_RESEREVED) & M_RESEREVED) + +#define S_10GPRBS9 3 +#define V_10GPRBS9(x) ((x) << S_10GPRBS9) +#define F_10GPRBS9 V_10GPRBS9(1U) + +#define S_10GPRBS31 2 +#define V_10GPRBS31(x) ((x) << S_10GPRBS31) +#define F_10GPRBS31 V_10GPRBS31(1U) + +#define S_HIBER 1 +#define V_HIBER(x) ((x) << S_HIBER) +#define F_HIBER V_HIBER(1U) + +#define S_BLOCKLOCK 0 +#define V_BLOCKLOCK(x) ((x) << S_BLOCKLOCK) +#define F_BLOCKLOCK V_BLOCKLOCK(1U) + +#define A_MAC_PORT_MTIP_PCS_BASER_STATUS2 0x1e84 + +#define S_BLOCKLOCKLL 15 +#define V_BLOCKLOCKLL(x) ((x) << S_BLOCKLOCKLL) +#define F_BLOCKLOCKLL V_BLOCKLOCKLL(1U) + +#define S_HIBERLH 14 +#define V_HIBERLH(x) ((x) << S_HIBERLH) +#define F_HIBERLH V_HIBERLH(1U) + +#define S_HIBERCOUNT 8 +#define M_HIBERCOUNT 0x3fU +#define V_HIBERCOUNT(x) ((x) << S_HIBERCOUNT) +#define G_HIBERCOUNT(x) (((x) >> S_HIBERCOUNT) & M_HIBERCOUNT) + +#define S_ERRBLKCNT 0 +#define M_ERRBLKCNT 0xffU +#define V_ERRBLKCNT(x) ((x) << S_ERRBLKCNT) +#define G_ERRBLKCNT(x) (((x) >> S_ERRBLKCNT) & M_ERRBLKCNT) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_A 0x1e88 + +#define S_SEEDA 0 +#define M_SEEDA 0xffffU +#define V_SEEDA(x) ((x) << S_SEEDA) +#define G_SEEDA(x) (((x) >> S_SEEDA) & M_SEEDA) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_A1 0x1e8c + +#define S_SEEDA1 0 +#define M_SEEDA1 0xffffU +#define V_SEEDA1(x) ((x) << S_SEEDA1) +#define G_SEEDA1(x) (((x) >> S_SEEDA1) & M_SEEDA1) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_A2 0x1e90 + +#define S_SEEDA2 0 +#define M_SEEDA2 0xffffU +#define V_SEEDA2(x) ((x) << S_SEEDA2) +#define G_SEEDA2(x) (((x) >> S_SEEDA2) & M_SEEDA2) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_A3 0x1e94 + +#define S_SEEDA3 0 +#define M_SEEDA3 0x3ffU +#define V_SEEDA3(x) ((x) << S_SEEDA3) +#define G_SEEDA3(x) (((x) >> S_SEEDA3) & M_SEEDA3) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_B 0x1e98 + +#define S_SEEDB 0 +#define M_SEEDB 0xffffU +#define V_SEEDB(x) ((x) << S_SEEDB) +#define G_SEEDB(x) (((x) >> S_SEEDB) & M_SEEDB) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_B1 0x1e9c + +#define S_SEEDB1 0 +#define M_SEEDB1 0xffffU +#define V_SEEDB1(x) ((x) << S_SEEDB1) +#define G_SEEDB1(x) (((x) >> S_SEEDB1) & M_SEEDB1) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_B2 0x1ea0 + +#define S_SEEDB2 0 +#define M_SEEDB2 0xffffU +#define V_SEEDB2(x) ((x) << S_SEEDB2) +#define G_SEEDB2(x) (((x) >> S_SEEDB2) & M_SEEDB2) + +#define A_MAC_PORT_MTIP_10GBASER_SEED_B3 0x1ea4 + +#define S_SEEDB3 0 +#define M_SEEDB3 0x3ffU +#define V_SEEDB3(x) ((x) << S_SEEDB3) +#define G_SEEDB3(x) (((x) >> S_SEEDB3) & M_SEEDB3) + +#define A_MAC_PORT_MTIP_BASER_TEST_CTRL 0x1ea8 + +#define S_TXPRBS9 6 +#define V_TXPRBS9(x) ((x) << S_TXPRBS9) +#define F_TXPRBS9 V_TXPRBS9(1U) + +#define S_RXPRBS31 5 +#define V_RXPRBS31(x) ((x) << S_RXPRBS31) +#define F_RXPRBS31 V_RXPRBS31(1U) + +#define S_TXPRBS31 4 +#define V_TXPRBS31(x) ((x) << S_TXPRBS31) +#define F_TXPRBS31 V_TXPRBS31(1U) + +#define S_TXTESTPATEN 3 +#define V_TXTESTPATEN(x) ((x) << S_TXTESTPATEN) +#define F_TXTESTPATEN V_TXTESTPATEN(1U) + +#define S_RXTESTPATEN 2 +#define V_RXTESTPATEN(x) ((x) << S_RXTESTPATEN) +#define F_RXTESTPATEN V_RXTESTPATEN(1U) + +#define S_TESTPATSEL 1 +#define V_TESTPATSEL(x) ((x) << S_TESTPATSEL) +#define F_TESTPATSEL V_TESTPATSEL(1U) + +#define S_DATAPATSEL 0 +#define V_DATAPATSEL(x) ((x) << S_DATAPATSEL) +#define F_DATAPATSEL V_DATAPATSEL(1U) + +#define A_MAC_PORT_MTIP_BASER_TEST_ERR_CNT 0x1eac + +#define S_TEST_ERR_CNT 0 +#define M_TEST_ERR_CNT 0xffffU +#define V_TEST_ERR_CNT(x) ((x) << S_TEST_ERR_CNT) +#define G_TEST_ERR_CNT(x) (((x) >> S_TEST_ERR_CNT) & M_TEST_ERR_CNT) + +#define A_MAC_PORT_MTIP_BER_HIGH_ORDER_CNT 0x1eb0 + +#define S_BER_CNT_HI 0 +#define M_BER_CNT_HI 0xffffU +#define V_BER_CNT_HI(x) ((x) << S_BER_CNT_HI) +#define G_BER_CNT_HI(x) (((x) >> S_BER_CNT_HI) & M_BER_CNT_HI) + +#define A_MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT 0x1eb4 + +#define S_HICOUNTPRSNT 15 +#define V_HICOUNTPRSNT(x) ((x) << S_HICOUNTPRSNT) +#define F_HICOUNTPRSNT V_HICOUNTPRSNT(1U) + +#define S_BLOCK_CNT_HI 0 +#define M_BLOCK_CNT_HI 0x3fffU +#define V_BLOCK_CNT_HI(x) ((x) << S_BLOCK_CNT_HI) +#define G_BLOCK_CNT_HI(x) (((x) >> S_BLOCK_CNT_HI) & M_BLOCK_CNT_HI) + +#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 0x1ec8 + +#define S_ALIGNSTATUS 12 +#define V_ALIGNSTATUS(x) ((x) << S_ALIGNSTATUS) +#define F_ALIGNSTATUS V_ALIGNSTATUS(1U) + +#define S_LANE7 7 +#define V_LANE7(x) ((x) << S_LANE7) +#define F_LANE7 V_LANE7(1U) + +#define S_LANE6 6 +#define V_LANE6(x) ((x) << S_LANE6) +#define F_LANE6 V_LANE6(1U) + +#define S_LANE5 5 +#define V_LANE5(x) ((x) << S_LANE5) +#define F_LANE5 V_LANE5(1U) + +#define S_LANE4 4 +#define V_LANE4(x) ((x) << S_LANE4) +#define F_LANE4 V_LANE4(1U) + +#define S_LANE3 3 +#define V_LANE3(x) ((x) << S_LANE3) +#define F_LANE3 V_LANE3(1U) + +#define S_LANE2 2 +#define V_LANE2(x) ((x) << S_LANE2) +#define F_LANE2 V_LANE2(1U) + +#define S_LANE1 1 +#define V_LANE1(x) ((x) << S_LANE1) +#define F_LANE1 V_LANE1(1U) + +#define S_LANE0 0 +#define V_LANE0(x) ((x) << S_LANE0) +#define F_LANE0 V_LANE0(1U) + +#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 0x1ecc + +#define S_LANE19 11 +#define V_LANE19(x) ((x) << S_LANE19) +#define F_LANE19 V_LANE19(1U) + +#define S_LANE18 10 +#define V_LANE18(x) ((x) << S_LANE18) +#define F_LANE18 V_LANE18(1U) + +#define S_LANE17 9 +#define V_LANE17(x) ((x) << S_LANE17) +#define F_LANE17 V_LANE17(1U) + +#define S_LANE16 8 +#define V_LANE16(x) ((x) << S_LANE16) +#define F_LANE16 V_LANE16(1U) + +#define S_LANE15 7 +#define V_LANE15(x) ((x) << S_LANE15) +#define F_LANE15 V_LANE15(1U) + +#define S_LANE14 6 +#define V_LANE14(x) ((x) << S_LANE14) +#define F_LANE14 V_LANE14(1U) + +#define S_LANE13 5 +#define V_LANE13(x) ((x) << S_LANE13) +#define F_LANE13 V_LANE13(1U) + +#define S_LANE12 4 +#define V_LANE12(x) ((x) << S_LANE12) +#define F_LANE12 V_LANE12(1U) + +#define S_LANE11 3 +#define V_LANE11(x) ((x) << S_LANE11) +#define F_LANE11 V_LANE11(1U) + +#define S_LANE10 2 +#define V_LANE10(x) ((x) << S_LANE10) +#define F_LANE10 V_LANE10(1U) + +#define S_LANE9 1 +#define V_LANE9(x) ((x) << S_LANE9) +#define F_LANE9 V_LANE9(1U) + +#define S_LANE8 0 +#define V_LANE8(x) ((x) << S_LANE8) +#define F_LANE8 V_LANE8(1U) + +#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 0x1ed0 + +#define S_AMLOCK7 7 +#define V_AMLOCK7(x) ((x) << S_AMLOCK7) +#define F_AMLOCK7 V_AMLOCK7(1U) + +#define S_AMLOCK6 6 +#define V_AMLOCK6(x) ((x) << S_AMLOCK6) +#define F_AMLOCK6 V_AMLOCK6(1U) + +#define S_AMLOCK5 5 +#define V_AMLOCK5(x) ((x) << S_AMLOCK5) +#define F_AMLOCK5 V_AMLOCK5(1U) + +#define S_AMLOCK4 4 +#define V_AMLOCK4(x) ((x) << S_AMLOCK4) +#define F_AMLOCK4 V_AMLOCK4(1U) + +#define S_AMLOCK3 3 +#define V_AMLOCK3(x) ((x) << S_AMLOCK3) +#define F_AMLOCK3 V_AMLOCK3(1U) + +#define S_AMLOCK2 2 +#define V_AMLOCK2(x) ((x) << S_AMLOCK2) +#define F_AMLOCK2 V_AMLOCK2(1U) + +#define S_AMLOCK1 1 +#define V_AMLOCK1(x) ((x) << S_AMLOCK1) +#define F_AMLOCK1 V_AMLOCK1(1U) + +#define S_AMLOCK0 0 +#define V_AMLOCK0(x) ((x) << S_AMLOCK0) +#define F_AMLOCK0 V_AMLOCK0(1U) + +#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 0x1ed4 + +#define S_AMLOCK19 11 +#define V_AMLOCK19(x) ((x) << S_AMLOCK19) +#define F_AMLOCK19 V_AMLOCK19(1U) + +#define S_AMLOCK18 10 +#define V_AMLOCK18(x) ((x) << S_AMLOCK18) +#define F_AMLOCK18 V_AMLOCK18(1U) + +#define S_AMLOCK17 9 +#define V_AMLOCK17(x) ((x) << S_AMLOCK17) +#define F_AMLOCK17 V_AMLOCK17(1U) + +#define S_AMLOCK16 8 +#define V_AMLOCK16(x) ((x) << S_AMLOCK16) +#define F_AMLOCK16 V_AMLOCK16(1U) + +#define S_AMLOCK15 7 +#define V_AMLOCK15(x) ((x) << S_AMLOCK15) +#define F_AMLOCK15 V_AMLOCK15(1U) + +#define S_AMLOCK14 6 +#define V_AMLOCK14(x) ((x) << S_AMLOCK14) +#define F_AMLOCK14 V_AMLOCK14(1U) + +#define S_AMLOCK13 5 +#define V_AMLOCK13(x) ((x) << S_AMLOCK13) +#define F_AMLOCK13 V_AMLOCK13(1U) + +#define S_AMLOCK12 4 +#define V_AMLOCK12(x) ((x) << S_AMLOCK12) +#define F_AMLOCK12 V_AMLOCK12(1U) + +#define S_AMLOCK11 3 +#define V_AMLOCK11(x) ((x) << S_AMLOCK11) +#define F_AMLOCK11 V_AMLOCK11(1U) + +#define S_AMLOCK10 2 +#define V_AMLOCK10(x) ((x) << S_AMLOCK10) +#define F_AMLOCK10 V_AMLOCK10(1U) + +#define S_AMLOCK9 1 +#define V_AMLOCK9(x) ((x) << S_AMLOCK9) +#define F_AMLOCK9 V_AMLOCK9(1U) + +#define S_AMLOCK8 0 +#define V_AMLOCK8(x) ((x) << S_AMLOCK8) +#define F_AMLOCK8 V_AMLOCK8(1U) + +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 0x1f68 + +#define S_BIPERR_CNT 0 +#define M_BIPERR_CNT 0xffffU +#define V_BIPERR_CNT(x) ((x) << S_BIPERR_CNT) +#define G_BIPERR_CNT(x) (((x) >> S_BIPERR_CNT) & M_BIPERR_CNT) + +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 0x1f6c +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 0x1f70 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 0x1f74 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 0x1f78 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 0x1f7c +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 0x1f80 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 0x1f84 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 0x1f88 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 0x1f8c +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 0x1f90 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 0x1f94 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 0x1f98 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 0x1f9c +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 0x1fa0 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 0x1fa4 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 0x1fa8 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 0x1fac +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 0x1fb0 +#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 0x1fb4 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_0 0x1fb8 + +#define S_MAP 0 +#define M_MAP 0x1fU +#define V_MAP(x) ((x) << S_MAP) +#define G_MAP(x) (((x) >> S_MAP) & M_MAP) + +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_1 0x1fbc +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_2 0x1fc0 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_3 0x1fc4 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_4 0x1fc8 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_5 0x1fcc +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_6 0x1fd0 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_7 0x1fd4 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_8 0x1fd8 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_9 0x1fdc +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_10 0x1fe0 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_11 0x1fe4 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_12 0x1fe8 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_13 0x1fec +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_14 0x1ff0 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_15 0x1ff4 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_16 0x1ff8 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000 +#define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004 +#define A_MAC_PORT_BEAN_CTL 0x2200 + +#define S_AN_RESET 15 +#define V_AN_RESET(x) ((x) << S_AN_RESET) +#define F_AN_RESET V_AN_RESET(1U) + +#define S_EXT_NXP_CTRL 13 +#define V_EXT_NXP_CTRL(x) ((x) << S_EXT_NXP_CTRL) +#define F_EXT_NXP_CTRL V_EXT_NXP_CTRL(1U) + +#define S_BEAN_EN 12 +#define V_BEAN_EN(x) ((x) << S_BEAN_EN) +#define F_BEAN_EN V_BEAN_EN(1U) + +#define S_RESTART_BEAN 9 +#define V_RESTART_BEAN(x) ((x) << S_RESTART_BEAN) +#define F_RESTART_BEAN V_RESTART_BEAN(1U) + +#define A_MAC_PORT_BEAN_STATUS 0x2204 + +#define S_PDF 9 +#define V_PDF(x) ((x) << S_PDF) +#define F_PDF V_PDF(1U) + +#define S_EXT_NXP_STATUS 7 +#define V_EXT_NXP_STATUS(x) ((x) << S_EXT_NXP_STATUS) +#define F_EXT_NXP_STATUS V_EXT_NXP_STATUS(1U) + +#define S_PAGE_RCVD 6 +#define V_PAGE_RCVD(x) ((x) << S_PAGE_RCVD) +#define F_PAGE_RCVD V_PAGE_RCVD(1U) + +#define S_BEAN_COMPLETE 5 +#define V_BEAN_COMPLETE(x) ((x) << S_BEAN_COMPLETE) +#define F_BEAN_COMPLETE V_BEAN_COMPLETE(1U) + +#define S_REM_FAULT_STATUS 4 +#define V_REM_FAULT_STATUS(x) ((x) << S_REM_FAULT_STATUS) +#define F_REM_FAULT_STATUS V_REM_FAULT_STATUS(1U) + +#define S_BEAN_ABILITY 3 +#define V_BEAN_ABILITY(x) ((x) << S_BEAN_ABILITY) +#define F_BEAN_ABILITY V_BEAN_ABILITY(1U) + +#define S_LP_BEAN_ABILITY 0 +#define V_LP_BEAN_ABILITY(x) ((x) << S_LP_BEAN_ABILITY) +#define F_LP_BEAN_ABILITY V_LP_BEAN_ABILITY(1U) + +#define A_MAC_PORT_BEAN_ABILITY_0 0x2208 + +#define S_NXP 15 +#define V_NXP(x) ((x) << S_NXP) +#define F_NXP V_NXP(1U) + +#define S_REM_FAULT 13 +#define V_REM_FAULT(x) ((x) << S_REM_FAULT) +#define F_REM_FAULT V_REM_FAULT(1U) + +#define S_PAUSE_ABILITY 10 +#define M_PAUSE_ABILITY 0x7U +#define V_PAUSE_ABILITY(x) ((x) << S_PAUSE_ABILITY) +#define G_PAUSE_ABILITY(x) (((x) >> S_PAUSE_ABILITY) & M_PAUSE_ABILITY) + +#define S_ECHO_NONCE 5 +#define M_ECHO_NONCE 0x1fU +#define V_ECHO_NONCE(x) ((x) << S_ECHO_NONCE) +#define G_ECHO_NONCE(x) (((x) >> S_ECHO_NONCE) & M_ECHO_NONCE) + +#define S_SELECTOR 0 +#define M_SELECTOR 0x1fU +#define V_SELECTOR(x) ((x) << S_SELECTOR) +#define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR) + +#define A_MAC_PORT_BEAN_ABILITY_1 0x220c + +#define S_TECH_ABILITY_1 5 +#define M_TECH_ABILITY_1 0x7ffU +#define V_TECH_ABILITY_1(x) ((x) << S_TECH_ABILITY_1) +#define G_TECH_ABILITY_1(x) (((x) >> S_TECH_ABILITY_1) & M_TECH_ABILITY_1) + +#define S_TX_NONCE 0 +#define M_TX_NONCE 0x1fU +#define V_TX_NONCE(x) ((x) << S_TX_NONCE) +#define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE) + +#define A_MAC_PORT_BEAN_ABILITY_2 0x2210 + +#define S_T5_FEC_ABILITY 14 +#define M_T5_FEC_ABILITY 0x3U +#define V_T5_FEC_ABILITY(x) ((x) << S_T5_FEC_ABILITY) +#define G_T5_FEC_ABILITY(x) (((x) >> S_T5_FEC_ABILITY) & M_T5_FEC_ABILITY) + +#define S_TECH_ABILITY_2 0 +#define M_TECH_ABILITY_2 0x3fffU +#define V_TECH_ABILITY_2(x) ((x) << S_TECH_ABILITY_2) +#define G_TECH_ABILITY_2(x) (((x) >> S_TECH_ABILITY_2) & M_TECH_ABILITY_2) + +#define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214 +#define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218 +#define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c +#define A_MAC_PORT_BEAN_MS_COUNT 0x2220 + +#define S_MS_COUNT 0 +#define M_MS_COUNT 0xffffU +#define V_MS_COUNT(x) ((x) << S_MS_COUNT) +#define G_MS_COUNT(x) (((x) >> S_MS_COUNT) & M_MS_COUNT) + +#define A_MAC_PORT_BEAN_XNP_0 0x2224 + +#define S_XNP 15 +#define V_XNP(x) ((x) << S_XNP) +#define F_XNP V_XNP(1U) + +#define S_ACKNOWLEDGE 14 +#define V_ACKNOWLEDGE(x) ((x) << S_ACKNOWLEDGE) +#define F_ACKNOWLEDGE V_ACKNOWLEDGE(1U) + +#define S_MP 13 +#define V_MP(x) ((x) << S_MP) +#define F_MP V_MP(1U) + +#define S_ACK2 12 +#define V_ACK2(x) ((x) << S_ACK2) +#define F_ACK2 V_ACK2(1U) + +#define S_MU 0 +#define M_MU 0x7ffU +#define V_MU(x) ((x) << S_MU) +#define G_MU(x) (((x) >> S_MU) & M_MU) + +#define A_MAC_PORT_BEAN_XNP_1 0x2228 + +#define S_UNFORMATED 0 +#define M_UNFORMATED 0xffffU +#define V_UNFORMATED(x) ((x) << S_UNFORMATED) +#define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED) + +#define A_MAC_PORT_BEAN_XNP_2 0x222c +#define A_MAC_PORT_LP_BEAN_XNP_0 0x2230 +#define A_MAC_PORT_LP_BEAN_XNP_1 0x2234 +#define A_MAC_PORT_LP_BEAN_XNP_2 0x2238 +#define A_MAC_PORT_BEAN_ETH_STATUS 0x223c + +#define S_100GCR10 8 +#define V_100GCR10(x) ((x) << S_100GCR10) +#define F_100GCR10 V_100GCR10(1U) + +#define S_40GCR4 6 +#define V_40GCR4(x) ((x) << S_40GCR4) +#define F_40GCR4 V_40GCR4(1U) + +#define S_40GKR4 5 +#define V_40GKR4(x) ((x) << S_40GKR4) +#define F_40GKR4 V_40GKR4(1U) + +#define S_FEC 4 +#define V_FEC(x) ((x) << S_FEC) +#define F_FEC V_FEC(1U) + +#define S_10GKR 3 +#define V_10GKR(x) ((x) << S_10GKR) +#define F_10GKR V_10GKR(1U) + +#define S_10GKX4 2 +#define V_10GKX4(x) ((x) << S_10GKX4) +#define F_10GKX4 V_10GKX4(1U) + +#define S_1GKX 1 +#define V_1GKX(x) ((x) << S_1GKX) +#define F_1GKX V_1GKX(1U) + +#define A_MAC_PORT_BEAN_CTL_LANE1 0x2240 +#define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244 +#define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248 +#define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c +#define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250 +#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE1 0x2254 +#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE1 0x2258 +#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE1 0x225c +#define A_MAC_PORT_BEAN_MS_COUNT_LANE1 0x2260 +#define A_MAC_PORT_BEAN_XNP_0_LANE1 0x2264 +#define A_MAC_PORT_BEAN_XNP_1_LANE1 0x2268 +#define A_MAC_PORT_BEAN_XNP_2_LANE1 0x226c +#define A_MAC_PORT_LP_BEAN_XNP_0_LANE1 0x2270 +#define A_MAC_PORT_LP_BEAN_XNP_1_LANE1 0x2274 +#define A_MAC_PORT_LP_BEAN_XNP_2_LANE1 0x2278 +#define A_MAC_PORT_BEAN_ETH_STATUS_LANE1 0x227c +#define A_MAC_PORT_BEAN_CTL_LANE2 0x2280 +#define A_MAC_PORT_BEAN_STATUS_LANE2 0x2284 +#define A_MAC_PORT_BEAN_ABILITY_0_LANE2 0x2288 +#define A_MAC_PORT_BEAN_ABILITY_1_LANE2 0x228c +#define A_MAC_PORT_BEAN_ABILITY_2_LANE2 0x2290 +#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE2 0x2294 +#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE2 0x2298 +#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE2 0x229c +#define A_MAC_PORT_BEAN_MS_COUNT_LANE2 0x22a0 +#define A_MAC_PORT_BEAN_XNP_0_LANE2 0x22a4 +#define A_MAC_PORT_BEAN_XNP_1_LANE2 0x22a8 +#define A_MAC_PORT_BEAN_XNP_2_LANE2 0x22ac +#define A_MAC_PORT_LP_BEAN_XNP_0_LANE2 0x22b0 +#define A_MAC_PORT_LP_BEAN_XNP_1_LANE2 0x22b4 +#define A_MAC_PORT_LP_BEAN_XNP_2_LANE2 0x22b8 +#define A_MAC_PORT_BEAN_ETH_STATUS_LANE2 0x22bc +#define A_MAC_PORT_BEAN_CTL_LANE3 0x22c0 +#define A_MAC_PORT_BEAN_STATUS_LANE3 0x22c4 +#define A_MAC_PORT_BEAN_ABILITY_0_LANE3 0x22c8 +#define A_MAC_PORT_BEAN_ABILITY_1_LANE3 0x22cc +#define A_MAC_PORT_BEAN_ABILITY_2_LANE3 0x22d0 +#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE3 0x22d4 +#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE3 0x22d8 +#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE3 0x22dc +#define A_MAC_PORT_BEAN_MS_COUNT_LANE3 0x22e0 +#define A_MAC_PORT_BEAN_XNP_0_LANE3 0x22e4 +#define A_MAC_PORT_BEAN_XNP_1_LANE3 0x22e8 +#define A_MAC_PORT_BEAN_XNP_2_LANE3 0x22ec +#define A_MAC_PORT_LP_BEAN_XNP_0_LANE3 0x22f0 +#define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4 +#define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8 +#define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc +#define A_MAC_PORT_FEC_KR_CONTROL 0x2600 + +#define S_ENABLE_TR 1 +#define V_ENABLE_TR(x) ((x) << S_ENABLE_TR) +#define F_ENABLE_TR V_ENABLE_TR(1U) + +#define S_RESTART_TR 0 +#define V_RESTART_TR(x) ((x) << S_RESTART_TR) +#define F_RESTART_TR V_RESTART_TR(1U) + +#define A_MAC_PORT_FEC_KR_STATUS 0x2604 + +#define S_FECKRSIGDET 15 +#define V_FECKRSIGDET(x) ((x) << S_FECKRSIGDET) +#define F_FECKRSIGDET V_FECKRSIGDET(1U) + +#define S_TRAIN_FAIL 3 +#define V_TRAIN_FAIL(x) ((x) << S_TRAIN_FAIL) +#define F_TRAIN_FAIL V_TRAIN_FAIL(1U) + +#define S_STARTUP_STATUS 2 +#define V_STARTUP_STATUS(x) ((x) << S_STARTUP_STATUS) +#define F_STARTUP_STATUS V_STARTUP_STATUS(1U) + +#define S_RX_STATUS 0 +#define V_RX_STATUS(x) ((x) << S_RX_STATUS) +#define F_RX_STATUS V_RX_STATUS(1U) + +#define A_MAC_PORT_FEC_KR_LP_COEFF 0x2608 + +#define S_PRESET 13 +#define V_PRESET(x) ((x) << S_PRESET) +#define F_PRESET V_PRESET(1U) + +#define S_INITIALIZE 12 +#define V_INITIALIZE(x) ((x) << S_INITIALIZE) +#define F_INITIALIZE V_INITIALIZE(1U) + +#define S_CP1_UPD 4 +#define M_CP1_UPD 0x3U +#define V_CP1_UPD(x) ((x) << S_CP1_UPD) +#define G_CP1_UPD(x) (((x) >> S_CP1_UPD) & M_CP1_UPD) + +#define S_C0_UPD 2 +#define M_C0_UPD 0x3U +#define V_C0_UPD(x) ((x) << S_C0_UPD) +#define G_C0_UPD(x) (((x) >> S_C0_UPD) & M_C0_UPD) + +#define S_CN1_UPD 0 +#define M_CN1_UPD 0x3U +#define V_CN1_UPD(x) ((x) << S_CN1_UPD) +#define G_CN1_UPD(x) (((x) >> S_CN1_UPD) & M_CN1_UPD) + +#define A_MAC_PORT_FEC_KR_LP_STAT 0x260c + +#define S_RX_READY 15 +#define V_RX_READY(x) ((x) << S_RX_READY) +#define F_RX_READY V_RX_READY(1U) + +#define S_CP1_STAT 4 +#define M_CP1_STAT 0x3U +#define V_CP1_STAT(x) ((x) << S_CP1_STAT) +#define G_CP1_STAT(x) (((x) >> S_CP1_STAT) & M_CP1_STAT) + +#define S_C0_STAT 2 +#define M_C0_STAT 0x3U +#define V_C0_STAT(x) ((x) << S_C0_STAT) +#define G_C0_STAT(x) (((x) >> S_C0_STAT) & M_C0_STAT) + +#define S_CN1_STAT 0 +#define M_CN1_STAT 0x3U +#define V_CN1_STAT(x) ((x) << S_CN1_STAT) +#define G_CN1_STAT(x) (((x) >> S_CN1_STAT) & M_CN1_STAT) + +#define A_MAC_PORT_FEC_KR_LD_COEFF 0x2610 +#define A_MAC_PORT_FEC_KR_LD_STAT 0x2614 +#define A_MAC_PORT_FEC_ABILITY 0x2618 + +#define S_FEC_IND_ABILITY 1 +#define V_FEC_IND_ABILITY(x) ((x) << S_FEC_IND_ABILITY) +#define F_FEC_IND_ABILITY V_FEC_IND_ABILITY(1U) + +#define S_ABILITY 0 +#define V_ABILITY(x) ((x) << S_ABILITY) +#define F_ABILITY V_ABILITY(1U) + +#define A_MAC_PORT_FEC_CONTROL 0x261c + +#define S_FEC_EN_ERR_IND 1 +#define V_FEC_EN_ERR_IND(x) ((x) << S_FEC_EN_ERR_IND) +#define F_FEC_EN_ERR_IND V_FEC_EN_ERR_IND(1U) + +#define S_FEC_EN 0 +#define V_FEC_EN(x) ((x) << S_FEC_EN) +#define F_FEC_EN V_FEC_EN(1U) + +#define A_MAC_PORT_FEC_STATUS 0x2620 + +#define S_FEC_LOCKED_100 1 +#define V_FEC_LOCKED_100(x) ((x) << S_FEC_LOCKED_100) +#define F_FEC_LOCKED_100 V_FEC_LOCKED_100(1U) + +#define S_FEC_LOCKED 0 +#define V_FEC_LOCKED(x) ((x) << S_FEC_LOCKED) +#define F_FEC_LOCKED V_FEC_LOCKED(1U) + +#define A_MAC_PORT_FEC_CERR_CNT_0 0x2624 + +#define S_FEC_CERR_CNT_0 0 +#define M_FEC_CERR_CNT_0 0xffffU +#define V_FEC_CERR_CNT_0(x) ((x) << S_FEC_CERR_CNT_0) +#define G_FEC_CERR_CNT_0(x) (((x) >> S_FEC_CERR_CNT_0) & M_FEC_CERR_CNT_0) + +#define A_MAC_PORT_FEC_CERR_CNT_1 0x2628 + +#define S_FEC_CERR_CNT_1 0 +#define M_FEC_CERR_CNT_1 0xffffU +#define V_FEC_CERR_CNT_1(x) ((x) << S_FEC_CERR_CNT_1) +#define G_FEC_CERR_CNT_1(x) (((x) >> S_FEC_CERR_CNT_1) & M_FEC_CERR_CNT_1) + +#define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c + +#define S_FEC_NCERR_CNT_0 0 +#define M_FEC_NCERR_CNT_0 0xffffU +#define V_FEC_NCERR_CNT_0(x) ((x) << S_FEC_NCERR_CNT_0) +#define G_FEC_NCERR_CNT_0(x) (((x) >> S_FEC_NCERR_CNT_0) & M_FEC_NCERR_CNT_0) + +#define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630 + +#define S_FEC_NCERR_CNT_1 0 +#define M_FEC_NCERR_CNT_1 0xffffU +#define V_FEC_NCERR_CNT_1(x) ((x) << S_FEC_NCERR_CNT_1) +#define G_FEC_NCERR_CNT_1(x) (((x) >> S_FEC_NCERR_CNT_1) & M_FEC_NCERR_CNT_1) + +#define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00 + +#define S_T5_RXREQ_C2 4 +#define M_T5_RXREQ_C2 0x3U +#define V_T5_RXREQ_C2(x) ((x) << S_T5_RXREQ_C2) +#define G_T5_RXREQ_C2(x) (((x) >> S_T5_RXREQ_C2) & M_T5_RXREQ_C2) + +#define S_T5_RXREQ_C1 2 +#define M_T5_RXREQ_C1 0x3U +#define V_T5_RXREQ_C1(x) ((x) << S_T5_RXREQ_C1) +#define G_T5_RXREQ_C1(x) (((x) >> S_T5_RXREQ_C1) & M_T5_RXREQ_C1) + +#define S_T5_RXREQ_C0 0 +#define M_T5_RXREQ_C0 0x3U +#define V_T5_RXREQ_C0(x) ((x) << S_T5_RXREQ_C0) +#define G_T5_RXREQ_C0(x) (((x) >> S_T5_RXREQ_C0) & M_T5_RXREQ_C0) + +#define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04 + +#define S_T5_AE0_RXSTAT_RDY 15 +#define V_T5_AE0_RXSTAT_RDY(x) ((x) << S_T5_AE0_RXSTAT_RDY) +#define F_T5_AE0_RXSTAT_RDY V_T5_AE0_RXSTAT_RDY(1U) + +#define S_T5_AE0_RXSTAT_C2 4 +#define M_T5_AE0_RXSTAT_C2 0x3U +#define V_T5_AE0_RXSTAT_C2(x) ((x) << S_T5_AE0_RXSTAT_C2) +#define G_T5_AE0_RXSTAT_C2(x) (((x) >> S_T5_AE0_RXSTAT_C2) & M_T5_AE0_RXSTAT_C2) + +#define S_T5_AE0_RXSTAT_C1 2 +#define M_T5_AE0_RXSTAT_C1 0x3U +#define V_T5_AE0_RXSTAT_C1(x) ((x) << S_T5_AE0_RXSTAT_C1) +#define G_T5_AE0_RXSTAT_C1(x) (((x) >> S_T5_AE0_RXSTAT_C1) & M_T5_AE0_RXSTAT_C1) + +#define S_T5_AE0_RXSTAT_C0 0 +#define M_T5_AE0_RXSTAT_C0 0x3U +#define V_T5_AE0_RXSTAT_C0(x) ((x) << S_T5_AE0_RXSTAT_C0) +#define G_T5_AE0_RXSTAT_C0(x) (((x) >> S_T5_AE0_RXSTAT_C0) & M_T5_AE0_RXSTAT_C0) + +#define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08 + +#define S_T5_TXREQ_C2 4 +#define M_T5_TXREQ_C2 0x3U +#define V_T5_TXREQ_C2(x) ((x) << S_T5_TXREQ_C2) +#define G_T5_TXREQ_C2(x) (((x) >> S_T5_TXREQ_C2) & M_T5_TXREQ_C2) + +#define S_T5_TXREQ_C1 2 +#define M_T5_TXREQ_C1 0x3U +#define V_T5_TXREQ_C1(x) ((x) << S_T5_TXREQ_C1) +#define G_T5_TXREQ_C1(x) (((x) >> S_T5_TXREQ_C1) & M_T5_TXREQ_C1) + +#define S_T5_TXREQ_C0 0 +#define M_T5_TXREQ_C0 0x3U +#define V_T5_TXREQ_C0(x) ((x) << S_T5_TXREQ_C0) +#define G_T5_TXREQ_C0(x) (((x) >> S_T5_TXREQ_C0) & M_T5_TXREQ_C0) + +#define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c + +#define S_T5_TXSTAT_C2 4 +#define M_T5_TXSTAT_C2 0x3U +#define V_T5_TXSTAT_C2(x) ((x) << S_T5_TXSTAT_C2) +#define G_T5_TXSTAT_C2(x) (((x) >> S_T5_TXSTAT_C2) & M_T5_TXSTAT_C2) + +#define S_T5_TXSTAT_C1 2 +#define M_T5_TXSTAT_C1 0x3U +#define V_T5_TXSTAT_C1(x) ((x) << S_T5_TXSTAT_C1) +#define G_T5_TXSTAT_C1(x) (((x) >> S_T5_TXSTAT_C1) & M_T5_TXSTAT_C1) + +#define S_T5_TXSTAT_C0 0 +#define M_T5_TXSTAT_C0 0x3U +#define V_T5_TXSTAT_C0(x) ((x) << S_T5_TXSTAT_C0) +#define G_T5_TXSTAT_C0(x) (((x) >> S_T5_TXSTAT_C0) & M_T5_TXSTAT_C0) + +#define A_MAC_PORT_AE_REG_MODE 0x2a10 + +#define S_AET_RSVD 7 +#define V_AET_RSVD(x) ((x) << S_AET_RSVD) +#define F_AET_RSVD V_AET_RSVD(1U) + +#define S_AET_ENABLE 6 +#define V_AET_ENABLE(x) ((x) << S_AET_ENABLE) +#define F_AET_ENABLE V_AET_ENABLE(1U) + +#define A_MAC_PORT_AE_PRBS_CTL 0x2a14 +#define A_MAC_PORT_AE_FSM_CTL 0x2a18 + +#define S_CIN_ENABLE 15 +#define V_CIN_ENABLE(x) ((x) << S_CIN_ENABLE) +#define F_CIN_ENABLE V_CIN_ENABLE(1U) + +#define A_MAC_PORT_AE_FSM_STATE 0x2a1c +#define A_MAC_PORT_AE_RX_COEF_REQ_1 0x2a20 +#define A_MAC_PORT_AE_RX_COEF_STAT_1 0x2a24 + +#define S_T5_AE1_RXSTAT_RDY 15 +#define V_T5_AE1_RXSTAT_RDY(x) ((x) << S_T5_AE1_RXSTAT_RDY) +#define F_T5_AE1_RXSTAT_RDY V_T5_AE1_RXSTAT_RDY(1U) + +#define S_T5_AE1_RXSTAT_C2 4 +#define M_T5_AE1_RXSTAT_C2 0x3U +#define V_T5_AE1_RXSTAT_C2(x) ((x) << S_T5_AE1_RXSTAT_C2) +#define G_T5_AE1_RXSTAT_C2(x) (((x) >> S_T5_AE1_RXSTAT_C2) & M_T5_AE1_RXSTAT_C2) + +#define S_T5_AE1_RXSTAT_C1 2 +#define M_T5_AE1_RXSTAT_C1 0x3U +#define V_T5_AE1_RXSTAT_C1(x) ((x) << S_T5_AE1_RXSTAT_C1) +#define G_T5_AE1_RXSTAT_C1(x) (((x) >> S_T5_AE1_RXSTAT_C1) & M_T5_AE1_RXSTAT_C1) + +#define S_T5_AE1_RXSTAT_C0 0 +#define M_T5_AE1_RXSTAT_C0 0x3U +#define V_T5_AE1_RXSTAT_C0(x) ((x) << S_T5_AE1_RXSTAT_C0) +#define G_T5_AE1_RXSTAT_C0(x) (((x) >> S_T5_AE1_RXSTAT_C0) & M_T5_AE1_RXSTAT_C0) + +#define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28 +#define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c +#define A_MAC_PORT_AE_REG_MODE_1 0x2a30 +#define A_MAC_PORT_AE_PRBS_CTL_1 0x2a34 +#define A_MAC_PORT_AE_FSM_CTL_1 0x2a38 +#define A_MAC_PORT_AE_FSM_STATE_1 0x2a3c +#define A_MAC_PORT_AE_RX_COEF_REQ_2 0x2a40 +#define A_MAC_PORT_AE_RX_COEF_STAT_2 0x2a44 + +#define S_T5_AE2_RXSTAT_RDY 15 +#define V_T5_AE2_RXSTAT_RDY(x) ((x) << S_T5_AE2_RXSTAT_RDY) +#define F_T5_AE2_RXSTAT_RDY V_T5_AE2_RXSTAT_RDY(1U) + +#define S_T5_AE2_RXSTAT_C2 4 +#define M_T5_AE2_RXSTAT_C2 0x3U +#define V_T5_AE2_RXSTAT_C2(x) ((x) << S_T5_AE2_RXSTAT_C2) +#define G_T5_AE2_RXSTAT_C2(x) (((x) >> S_T5_AE2_RXSTAT_C2) & M_T5_AE2_RXSTAT_C2) + +#define S_T5_AE2_RXSTAT_C1 2 +#define M_T5_AE2_RXSTAT_C1 0x3U +#define V_T5_AE2_RXSTAT_C1(x) ((x) << S_T5_AE2_RXSTAT_C1) +#define G_T5_AE2_RXSTAT_C1(x) (((x) >> S_T5_AE2_RXSTAT_C1) & M_T5_AE2_RXSTAT_C1) + +#define S_T5_AE2_RXSTAT_C0 0 +#define M_T5_AE2_RXSTAT_C0 0x3U +#define V_T5_AE2_RXSTAT_C0(x) ((x) << S_T5_AE2_RXSTAT_C0) +#define G_T5_AE2_RXSTAT_C0(x) (((x) >> S_T5_AE2_RXSTAT_C0) & M_T5_AE2_RXSTAT_C0) + +#define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48 +#define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c +#define A_MAC_PORT_AE_REG_MODE_2 0x2a50 +#define A_MAC_PORT_AE_PRBS_CTL_2 0x2a54 +#define A_MAC_PORT_AE_FSM_CTL_2 0x2a58 +#define A_MAC_PORT_AE_FSM_STATE_2 0x2a5c +#define A_MAC_PORT_AE_RX_COEF_REQ_3 0x2a60 +#define A_MAC_PORT_AE_RX_COEF_STAT_3 0x2a64 + +#define S_T5_AE3_RXSTAT_RDY 15 +#define V_T5_AE3_RXSTAT_RDY(x) ((x) << S_T5_AE3_RXSTAT_RDY) +#define F_T5_AE3_RXSTAT_RDY V_T5_AE3_RXSTAT_RDY(1U) + +#define S_T5_AE3_RXSTAT_C2 4 +#define M_T5_AE3_RXSTAT_C2 0x3U +#define V_T5_AE3_RXSTAT_C2(x) ((x) << S_T5_AE3_RXSTAT_C2) +#define G_T5_AE3_RXSTAT_C2(x) (((x) >> S_T5_AE3_RXSTAT_C2) & M_T5_AE3_RXSTAT_C2) + +#define S_T5_AE3_RXSTAT_C1 2 +#define M_T5_AE3_RXSTAT_C1 0x3U +#define V_T5_AE3_RXSTAT_C1(x) ((x) << S_T5_AE3_RXSTAT_C1) +#define G_T5_AE3_RXSTAT_C1(x) (((x) >> S_T5_AE3_RXSTAT_C1) & M_T5_AE3_RXSTAT_C1) + +#define S_T5_AE3_RXSTAT_C0 0 +#define M_T5_AE3_RXSTAT_C0 0x3U +#define V_T5_AE3_RXSTAT_C0(x) ((x) << S_T5_AE3_RXSTAT_C0) +#define G_T5_AE3_RXSTAT_C0(x) (((x) >> S_T5_AE3_RXSTAT_C0) & M_T5_AE3_RXSTAT_C0) + +#define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68 +#define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c +#define A_MAC_PORT_AE_REG_MODE_3 0x2a70 +#define A_MAC_PORT_AE_PRBS_CTL_3 0x2a74 +#define A_MAC_PORT_AE_FSM_CTL_3 0x2a78 +#define A_MAC_PORT_AE_FSM_STATE_3 0x2a7c +#define A_MAC_PORT_AE_TX_DIS 0x2a80 +#define A_MAC_PORT_AE_KR_CTRL 0x2a84 +#define A_MAC_PORT_AE_RX_SIGDET 0x2a88 +#define A_MAC_PORT_AE_KR_STATUS 0x2a8c +#define A_MAC_PORT_AE_TX_DIS_1 0x2a90 +#define A_MAC_PORT_AE_KR_CTRL_1 0x2a94 +#define A_MAC_PORT_AE_RX_SIGDET_1 0x2a98 +#define A_MAC_PORT_AE_KR_STATUS_1 0x2a9c +#define A_MAC_PORT_AE_TX_DIS_2 0x2aa0 +#define A_MAC_PORT_AE_KR_CTRL_2 0x2aa4 +#define A_MAC_PORT_AE_RX_SIGDET_2 0x2aa8 +#define A_MAC_PORT_AE_KR_STATUS_2 0x2aac +#define A_MAC_PORT_AE_TX_DIS_3 0x2ab0 +#define A_MAC_PORT_AE_KR_CTRL_3 0x2ab4 +#define A_MAC_PORT_AE_RX_SIGDET_3 0x2ab8 +#define A_MAC_PORT_AE_KR_STATUS_3 0x2abc +#define A_MAC_PORT_AET_STAGE_CONFIGURATION_0 0x2b00 + +#define S_EN_HOLD_FAIL 14 +#define V_EN_HOLD_FAIL(x) ((x) << S_EN_HOLD_FAIL) +#define F_EN_HOLD_FAIL V_EN_HOLD_FAIL(1U) + +#define S_INIT_METH 12 +#define M_INIT_METH 0x3U +#define V_INIT_METH(x) ((x) << S_INIT_METH) +#define G_INIT_METH(x) (((x) >> S_INIT_METH) & M_INIT_METH) + +#define S_CE_DECS 8 +#define M_CE_DECS 0xfU +#define V_CE_DECS(x) ((x) << S_CE_DECS) +#define G_CE_DECS(x) (((x) >> S_CE_DECS) & M_CE_DECS) + +#define S_EN_ZFE 7 +#define V_EN_ZFE(x) ((x) << S_EN_ZFE) +#define F_EN_ZFE V_EN_ZFE(1U) + +#define S_EN_GAIN_TOG 6 +#define V_EN_GAIN_TOG(x) ((x) << S_EN_GAIN_TOG) +#define F_EN_GAIN_TOG V_EN_GAIN_TOG(1U) + +#define S_EN_AI_C1 5 +#define V_EN_AI_C1(x) ((x) << S_EN_AI_C1) +#define F_EN_AI_C1 V_EN_AI_C1(1U) + +#define S_EN_MAX_ST 4 +#define V_EN_MAX_ST(x) ((x) << S_EN_MAX_ST) +#define F_EN_MAX_ST V_EN_MAX_ST(1U) + +#define S_EN_H1T_EQ 3 +#define V_EN_H1T_EQ(x) ((x) << S_EN_H1T_EQ) +#define F_EN_H1T_EQ V_EN_H1T_EQ(1U) + +#define S_H1TEQ_GOAL 0 +#define M_H1TEQ_GOAL 0x7U +#define V_H1TEQ_GOAL(x) ((x) << S_H1TEQ_GOAL) +#define G_H1TEQ_GOAL(x) (((x) >> S_H1TEQ_GOAL) & M_H1TEQ_GOAL) + +#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04 + +#define S_GAIN_TH 6 +#define M_GAIN_TH 0x1fU +#define V_GAIN_TH(x) ((x) << S_GAIN_TH) +#define G_GAIN_TH(x) (((x) >> S_GAIN_TH) & M_GAIN_TH) + +#define S_EN_SD_TH 5 +#define V_EN_SD_TH(x) ((x) << S_EN_SD_TH) +#define F_EN_SD_TH V_EN_SD_TH(1U) + +#define S_EN_AMIN_TH 4 +#define V_EN_AMIN_TH(x) ((x) << S_EN_AMIN_TH) +#define F_EN_AMIN_TH V_EN_AMIN_TH(1U) + +#define S_AMIN_TH 0 +#define M_AMIN_TH 0xfU +#define V_AMIN_TH(x) ((x) << S_AMIN_TH) +#define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH) + +#define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08 + +#define S_ACC_LIM 8 +#define M_ACC_LIM 0xfU +#define V_ACC_LIM(x) ((x) << S_ACC_LIM) +#define G_ACC_LIM(x) (((x) >> S_ACC_LIM) & M_ACC_LIM) + +#define S_CNV_LIM 4 +#define M_CNV_LIM 0xfU +#define V_CNV_LIM(x) ((x) << S_CNV_LIM) +#define G_CNV_LIM(x) (((x) >> S_CNV_LIM) & M_CNV_LIM) + +#define S_TOG_LIM 0 +#define M_TOG_LIM 0xfU +#define V_TOG_LIM(x) ((x) << S_TOG_LIM) +#define G_TOG_LIM(x) (((x) >> S_TOG_LIM) & M_TOG_LIM) + +#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 0x2b0c + +#define S_BOOT_LUT7 12 +#define M_BOOT_LUT7 0xfU +#define V_BOOT_LUT7(x) ((x) << S_BOOT_LUT7) +#define G_BOOT_LUT7(x) (((x) >> S_BOOT_LUT7) & M_BOOT_LUT7) + +#define S_BOOT_LUT6 8 +#define M_BOOT_LUT6 0xfU +#define V_BOOT_LUT6(x) ((x) << S_BOOT_LUT6) +#define G_BOOT_LUT6(x) (((x) >> S_BOOT_LUT6) & M_BOOT_LUT6) + +#define S_BOOT_LUT45 4 +#define M_BOOT_LUT45 0xfU +#define V_BOOT_LUT45(x) ((x) << S_BOOT_LUT45) +#define G_BOOT_LUT45(x) (((x) >> S_BOOT_LUT45) & M_BOOT_LUT45) + +#define S_BOOT_LUT0123 2 +#define M_BOOT_LUT0123 0x3U +#define V_BOOT_LUT0123(x) ((x) << S_BOOT_LUT0123) +#define G_BOOT_LUT0123(x) (((x) >> S_BOOT_LUT0123) & M_BOOT_LUT0123) + +#define S_BOOT_DEC_C0 1 +#define V_BOOT_DEC_C0(x) ((x) << S_BOOT_DEC_C0) +#define F_BOOT_DEC_C0 V_BOOT_DEC_C0(1U) + +#define A_MAC_PORT_AET_STATUS_0 0x2b10 + +#define S_AET_STAT 9 +#define M_AET_STAT 0xfU +#define V_AET_STAT(x) ((x) << S_AET_STAT) +#define G_AET_STAT(x) (((x) >> S_AET_STAT) & M_AET_STAT) + +#define S_NEU_STATE 5 +#define M_NEU_STATE 0xfU +#define V_NEU_STATE(x) ((x) << S_NEU_STATE) +#define G_NEU_STATE(x) (((x) >> S_NEU_STATE) & M_NEU_STATE) + +#define S_CTRL_STATE 0 +#define M_CTRL_STATE 0x1fU +#define V_CTRL_STATE(x) ((x) << S_CTRL_STATE) +#define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE) + +#define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20 +#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24 +#define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28 +#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c +#define A_MAC_PORT_AET_STATUS_1 0x2b30 +#define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40 +#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44 +#define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48 +#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c +#define A_MAC_PORT_AET_STATUS_2 0x2b50 +#define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60 +#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64 +#define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68 +#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c +#define A_MAC_PORT_AET_STATUS_3 0x2b70 +#define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000 + +#define S_T5_TX_LINKEN 15 +#define V_T5_TX_LINKEN(x) ((x) << S_T5_TX_LINKEN) +#define F_T5_TX_LINKEN V_T5_TX_LINKEN(1U) + +#define S_T5_TX_LINKRST 14 +#define V_T5_TX_LINKRST(x) ((x) << S_T5_TX_LINKRST) +#define F_T5_TX_LINKRST V_T5_TX_LINKRST(1U) + +#define S_T5_TX_CFGWRT 13 +#define V_T5_TX_CFGWRT(x) ((x) << S_T5_TX_CFGWRT) +#define F_T5_TX_CFGWRT V_T5_TX_CFGWRT(1U) + +#define S_T5_TX_CFGPTR 11 +#define M_T5_TX_CFGPTR 0x3U +#define V_T5_TX_CFGPTR(x) ((x) << S_T5_TX_CFGPTR) +#define G_T5_TX_CFGPTR(x) (((x) >> S_T5_TX_CFGPTR) & M_T5_TX_CFGPTR) + +#define S_T5_TX_CFGEXT 10 +#define V_T5_TX_CFGEXT(x) ((x) << S_T5_TX_CFGEXT) +#define F_T5_TX_CFGEXT V_T5_TX_CFGEXT(1U) + +#define S_T5_TX_CFGACT 9 +#define V_T5_TX_CFGACT(x) ((x) << S_T5_TX_CFGACT) +#define F_T5_TX_CFGACT V_T5_TX_CFGACT(1U) + +#define S_T5_TX_RSYNCC 8 +#define V_T5_TX_RSYNCC(x) ((x) << S_T5_TX_RSYNCC) +#define F_T5_TX_RSYNCC V_T5_TX_RSYNCC(1U) + +#define S_T5_TX_PLLSEL 6 +#define M_T5_TX_PLLSEL 0x3U +#define V_T5_TX_PLLSEL(x) ((x) << S_T5_TX_PLLSEL) +#define G_T5_TX_PLLSEL(x) (((x) >> S_T5_TX_PLLSEL) & M_T5_TX_PLLSEL) + +#define S_T5_TX_EXTC16 5 +#define V_T5_TX_EXTC16(x) ((x) << S_T5_TX_EXTC16) +#define F_T5_TX_EXTC16 V_T5_TX_EXTC16(1U) + +#define S_T5_TX_DCKSEL 4 +#define V_T5_TX_DCKSEL(x) ((x) << S_T5_TX_DCKSEL) +#define F_T5_TX_DCKSEL V_T5_TX_DCKSEL(1U) + +#define S_T5_TX_RXLOOP 3 +#define V_T5_TX_RXLOOP(x) ((x) << S_T5_TX_RXLOOP) +#define F_T5_TX_RXLOOP V_T5_TX_RXLOOP(1U) + +#define S_T5_TX_BWSEL 2 +#define V_T5_TX_BWSEL(x) ((x) << S_T5_TX_BWSEL) +#define F_T5_TX_BWSEL V_T5_TX_BWSEL(1U) + +#define S_T5_TX_RTSEL 0 +#define M_T5_TX_RTSEL 0x3U +#define V_T5_TX_RTSEL(x) ((x) << S_T5_TX_RTSEL) +#define G_T5_TX_RTSEL(x) (((x) >> S_T5_TX_RTSEL) & M_T5_TX_RTSEL) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004 + +#define S_SPSEL 11 +#define M_SPSEL 0x7U +#define V_SPSEL(x) ((x) << S_SPSEL) +#define G_SPSEL(x) (((x) >> S_SPSEL) & M_SPSEL) + +#define S_AFDWEN 7 +#define V_AFDWEN(x) ((x) << S_AFDWEN) +#define F_AFDWEN V_AFDWEN(1U) + +#define S_TPGMD 3 +#define V_TPGMD(x) ((x) << S_TPGMD) +#define F_TPGMD V_TPGMD(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008 + +#define S_ZCALOVRD 8 +#define V_ZCALOVRD(x) ((x) << S_ZCALOVRD) +#define F_ZCALOVRD V_ZCALOVRD(1U) + +#define S_AMMODE 7 +#define V_AMMODE(x) ((x) << S_AMMODE) +#define F_AMMODE V_AMMODE(1U) + +#define S_AEPOL 6 +#define V_AEPOL(x) ((x) << S_AEPOL) +#define F_AEPOL V_AEPOL(1U) + +#define S_AESRC 5 +#define V_AESRC(x) ((x) << S_AESRC) +#define F_AESRC V_AESRC(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c + +#define S_T5DRVHIZ 5 +#define V_T5DRVHIZ(x) ((x) << S_T5DRVHIZ) +#define F_T5DRVHIZ V_T5DRVHIZ(1U) + +#define S_T5SASIMP 4 +#define V_T5SASIMP(x) ((x) << S_T5SASIMP) +#define F_T5SASIMP V_T5SASIMP(1U) + +#define S_T5SLEW 2 +#define M_T5SLEW 0x3U +#define V_T5SLEW(x) ((x) << S_T5SLEW) +#define G_T5SLEW(x) (((x) >> S_T5SLEW) & M_T5SLEW) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3010 + +#define S_T5C2BUFDCEN 5 +#define V_T5C2BUFDCEN(x) ((x) << S_T5C2BUFDCEN) +#define F_T5C2BUFDCEN V_T5C2BUFDCEN(1U) + +#define S_T5DCCEN 4 +#define V_T5DCCEN(x) ((x) << S_T5DCCEN) +#define F_T5DCCEN V_T5DCCEN(1U) + +#define S_T5REGBYP 3 +#define V_T5REGBYP(x) ((x) << S_T5REGBYP) +#define F_T5REGBYP V_T5REGBYP(1U) + +#define S_T5REGAEN 2 +#define V_T5REGAEN(x) ((x) << S_T5REGAEN) +#define F_T5REGAEN V_T5REGAEN(1U) + +#define S_T5REGAMP 0 +#define M_T5REGAMP 0x3U +#define V_T5REGAMP(x) ((x) << S_T5REGAMP) +#define G_T5REGAMP(x) (((x) >> S_T5REGAMP) & M_T5REGAMP) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3014 + +#define S_RSTEP 15 +#define V_RSTEP(x) ((x) << S_RSTEP) +#define F_RSTEP V_RSTEP(1U) + +#define S_RLOCK 14 +#define V_RLOCK(x) ((x) << S_RLOCK) +#define F_RLOCK V_RLOCK(1U) + +#define S_RPOS 8 +#define M_RPOS 0x3fU +#define V_RPOS(x) ((x) << S_RPOS) +#define G_RPOS(x) (((x) >> S_RPOS) & M_RPOS) + +#define S_DCLKSAM 7 +#define V_DCLKSAM(x) ((x) << S_DCLKSAM) +#define F_DCLKSAM V_DCLKSAM(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3018 + +#define S_CALSSTN 3 +#define M_CALSSTN 0x7U +#define V_CALSSTN(x) ((x) << S_CALSSTN) +#define G_CALSSTN(x) (((x) >> S_CALSSTN) & M_CALSSTN) + +#define S_CALSSTP 0 +#define M_CALSSTP 0x7U +#define V_CALSSTP(x) ((x) << S_CALSSTP) +#define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c + +#define S_DRTOL 0 +#define M_DRTOL 0x1fU +#define V_DRTOL(x) ((x) << S_DRTOL) +#define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020 + +#define S_T5NXTT0 0 +#define M_T5NXTT0 0x1fU +#define V_T5NXTT0(x) ((x) << S_T5NXTT0) +#define G_T5NXTT0(x) (((x) >> S_T5NXTT0) & M_T5NXTT0) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024 + +#define S_T5NXTT1 0 +#define M_T5NXTT1 0x3fU +#define V_T5NXTT1(x) ((x) << S_T5NXTT1) +#define G_T5NXTT1(x) (((x) >> S_T5NXTT1) & M_T5NXTT1) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT 0x3028 + +#define S_T5NXTT2 0 +#define M_T5NXTT2 0x3fU +#define V_T5NXTT2(x) ((x) << S_T5NXTT2) +#define G_T5NXTT2(x) (((x) >> S_T5NXTT2) & M_T5NXTT2) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030 + +#define S_T5TXPWR 0 +#define M_T5TXPWR 0x3fU +#define V_T5TXPWR(x) ((x) << S_T5TXPWR) +#define G_T5TXPWR(x) (((x) >> S_T5TXPWR) & M_T5TXPWR) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_POLARITY 0x3034 + +#define S_NXTPOL 0 +#define M_NXTPOL 0x7U +#define V_NXTPOL(x) ((x) << S_NXTPOL) +#define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038 + +#define S_CPREST 13 +#define V_CPREST(x) ((x) << S_CPREST) +#define F_CPREST V_CPREST(1U) + +#define S_CINIT 12 +#define V_CINIT(x) ((x) << S_CINIT) +#define F_CINIT V_CINIT(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040 +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044 + +#define S_T5NIDAC1 0 +#define M_T5NIDAC1 0x3fU +#define V_T5NIDAC1(x) ((x) << S_T5NIDAC1) +#define G_T5NIDAC1(x) (((x) >> S_T5NIDAC1) & M_T5NIDAC1) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048 + +#define S_T5NIDAC2 0 +#define M_T5NIDAC2 0x3fU +#define V_T5NIDAC2(x) ((x) << S_T5NIDAC2) +#define G_T5NIDAC2(x) (((x) >> S_T5NIDAC2) & M_T5NIDAC2) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060 +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064 + +#define S_T5AIDAC1 0 +#define M_T5AIDAC1 0x3fU +#define V_T5AIDAC1(x) ((x) << S_T5AIDAC1) +#define G_T5AIDAC1(x) (((x) >> S_T5AIDAC1) & M_T5AIDAC1) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068 +#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070 + +#define S_MAINSC 6 +#define M_MAINSC 0x3fU +#define V_MAINSC(x) ((x) << S_MAINSC) +#define G_MAINSC(x) (((x) >> S_MAINSC) & M_MAINSC) + +#define S_POSTSC 0 +#define M_POSTSC 0x3fU +#define V_POSTSC(x) ((x) << S_POSTSC) +#define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074 + +#define S_PRESC 0 +#define M_PRESC 0x1fU +#define V_PRESC(x) ((x) << S_PRESC) +#define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078 +#define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c + +#define S_T5XADDR 1 +#define M_T5XADDR 0x1fU +#define V_T5XADDR(x) ((x) << S_T5XADDR) +#define G_T5XADDR(x) (((x) >> S_T5XADDR) & M_T5XADDR) + +#define S_T5XWR 0 +#define V_T5XWR(x) ((x) << S_T5XWR) +#define F_T5XWR V_T5XWR(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080 + +#define S_XDAT10 0 +#define M_XDAT10 0xffffU +#define V_XDAT10(x) ((x) << S_XDAT10) +#define G_XDAT10(x) (((x) >> S_XDAT10) & M_XDAT10) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3084 + +#define S_XDAT32 0 +#define M_XDAT32 0xffffU +#define V_XDAT32(x) ((x) << S_XDAT32) +#define G_XDAT32(x) (((x) >> S_XDAT32) & M_XDAT32) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3088 + +#define S_XDAT4 0 +#define M_XDAT4 0xffU +#define V_XDAT4(x) ((x) << S_XDAT4) +#define G_XDAT4(x) (((x) >> S_XDAT4) & M_XDAT4) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c + +#define S_DCCTIMEDOUT 15 +#define V_DCCTIMEDOUT(x) ((x) << S_DCCTIMEDOUT) +#define F_DCCTIMEDOUT V_DCCTIMEDOUT(1U) + +#define S_DCCTIMEEN 14 +#define V_DCCTIMEEN(x) ((x) << S_DCCTIMEEN) +#define F_DCCTIMEEN V_DCCTIMEEN(1U) + +#define S_DCCLOCK 13 +#define V_DCCLOCK(x) ((x) << S_DCCLOCK) +#define F_DCCLOCK V_DCCLOCK(1U) + +#define S_DCCOFFSET 8 +#define M_DCCOFFSET 0x1fU +#define V_DCCOFFSET(x) ((x) << S_DCCOFFSET) +#define G_DCCOFFSET(x) (((x) >> S_DCCOFFSET) & M_DCCOFFSET) + +#define S_DCCSTEP 6 +#define M_DCCSTEP 0x3U +#define V_DCCSTEP(x) ((x) << S_DCCSTEP) +#define G_DCCSTEP(x) (((x) >> S_DCCSTEP) & M_DCCSTEP) + +#define S_DCCASTEP 1 +#define M_DCCASTEP 0x1fU +#define V_DCCASTEP(x) ((x) << S_DCCASTEP) +#define G_DCCASTEP(x) (((x) >> S_DCCASTEP) & M_DCCASTEP) + +#define S_DCCAEN 0 +#define V_DCCAEN(x) ((x) << S_DCCAEN) +#define F_DCCAEN V_DCCAEN(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090 + +#define S_DCCOUT 12 +#define V_DCCOUT(x) ((x) << S_DCCOUT) +#define F_DCCOUT V_DCCOUT(1U) + +#define S_DCCCLK 11 +#define V_DCCCLK(x) ((x) << S_DCCCLK) +#define F_DCCCLK V_DCCCLK(1U) + +#define S_DCCHOLD 10 +#define V_DCCHOLD(x) ((x) << S_DCCHOLD) +#define F_DCCHOLD V_DCCHOLD(1U) + +#define S_DCCSIGN 8 +#define M_DCCSIGN 0x3U +#define V_DCCSIGN(x) ((x) << S_DCCSIGN) +#define G_DCCSIGN(x) (((x) >> S_DCCSIGN) & M_DCCSIGN) + +#define S_DCCAMP 1 +#define M_DCCAMP 0x7fU +#define V_DCCAMP(x) ((x) << S_DCCAMP) +#define G_DCCAMP(x) (((x) >> S_DCCAMP) & M_DCCAMP) + +#define S_DCCOEN 0 +#define V_DCCOEN(x) ((x) << S_DCCOEN) +#define F_DCCOEN V_DCCOEN(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x3094 + +#define S_DCCASIGN 7 +#define M_DCCASIGN 0x3U +#define V_DCCASIGN(x) ((x) << S_DCCASIGN) +#define G_DCCASIGN(x) (((x) >> S_DCCASIGN) & M_DCCASIGN) + +#define S_DCCAAMP 0 +#define M_DCCAAMP 0x7fU +#define V_DCCAAMP(x) ((x) << S_DCCAAMP) +#define G_DCCAAMP(x) (((x) >> S_DCCAAMP) & M_DCCAAMP) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x3098 + +#define S_DCCTIMEOUTVAL 0 +#define M_DCCTIMEOUTVAL 0xffffU +#define V_DCCTIMEOUTVAL(x) ((x) << S_DCCTIMEOUTVAL) +#define G_DCCTIMEOUTVAL(x) (((x) >> S_DCCTIMEOUTVAL) & M_DCCTIMEOUTVAL) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL 0x309c + +#define S_LPIDCLK 4 +#define V_LPIDCLK(x) ((x) << S_LPIDCLK) +#define F_LPIDCLK V_LPIDCLK(1U) + +#define S_LPITERM 2 +#define M_LPITERM 0x3U +#define V_LPITERM(x) ((x) << S_LPITERM) +#define G_LPITERM(x) (((x) >> S_LPITERM) & M_LPITERM) + +#define S_LPIPRCD 0 +#define M_LPIPRCD 0x3U +#define V_LPIPRCD(x) ((x) << S_LPIPRCD) +#define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0 + +#define S_SDOVRDEN 8 +#define V_SDOVRDEN(x) ((x) << S_SDOVRDEN) +#define F_SDOVRDEN V_SDOVRDEN(1U) + +#define S_SDOVRD 0 +#define M_SDOVRD 0xffU +#define V_SDOVRD(x) ((x) << S_SDOVRD) +#define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4 + +#define S_SLEWCODE 1 +#define M_SLEWCODE 0x3U +#define V_SLEWCODE(x) ((x) << S_SLEWCODE) +#define G_SLEWCODE(x) (((x) >> S_SLEWCODE) & M_SLEWCODE) + +#define S_ASEGEN 0 +#define V_ASEGEN(x) ((x) << S_ASEGEN) +#define F_ASEGEN V_ASEGEN(1U) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8 + +#define S_AECMDVAL 14 +#define V_AECMDVAL(x) ((x) << S_AECMDVAL) +#define F_AECMDVAL V_AECMDVAL(1U) + +#define S_AECMD1312 12 +#define M_AECMD1312 0x3U +#define V_AECMD1312(x) ((x) << S_AECMD1312) +#define G_AECMD1312(x) (((x) >> S_AECMD1312) & M_AECMD1312) + +#define S_AECMD70 0 +#define M_AECMD70 0xffU +#define V_AECMD70(x) ((x) << S_AECMD70) +#define G_AECMD70(x) (((x) >> S_AECMD70) & M_AECMD70) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 0x30fc + +#define S_C48DIVCTL 12 +#define M_C48DIVCTL 0x7U +#define V_C48DIVCTL(x) ((x) << S_C48DIVCTL) +#define G_C48DIVCTL(x) (((x) >> S_C48DIVCTL) & M_C48DIVCTL) + +#define S_RATEDIVCTL 9 +#define M_RATEDIVCTL 0x7U +#define V_RATEDIVCTL(x) ((x) << S_RATEDIVCTL) +#define G_RATEDIVCTL(x) (((x) >> S_RATEDIVCTL) & M_RATEDIVCTL) + +#define S_ANLGFLSH 8 +#define V_ANLGFLSH(x) ((x) << S_ANLGFLSH) +#define F_ANLGFLSH V_ANLGFLSH(1U) + +#define S_DCCTSTOUT 7 +#define V_DCCTSTOUT(x) ((x) << S_DCCTSTOUT) +#define F_DCCTSTOUT V_DCCTSTOUT(1U) + +#define S_BSOUT 6 +#define V_BSOUT(x) ((x) << S_BSOUT) +#define F_BSOUT V_BSOUT(1U) + +#define S_BSIN 5 +#define V_BSIN(x) ((x) << S_BSIN) +#define F_BSIN V_BSIN(1U) + +#define S_JTAGAMPL 3 +#define M_JTAGAMPL 0x3U +#define V_JTAGAMPL(x) ((x) << S_JTAGAMPL) +#define G_JTAGAMPL(x) (((x) >> S_JTAGAMPL) & M_JTAGAMPL) + +#define S_JTAGTS 2 +#define V_JTAGTS(x) ((x) << S_JTAGTS) +#define F_JTAGTS V_JTAGTS(1U) + +#define S_TS 1 +#define V_TS(x) ((x) << S_TS) +#define F_TS V_TS(1U) + +#define S_OBS 0 +#define V_OBS(x) ((x) << S_OBS) +#define F_OBS V_OBS(1U) + +#define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c +#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc +#define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200 + +#define S_T5_RX_LINKEN 15 +#define V_T5_RX_LINKEN(x) ((x) << S_T5_RX_LINKEN) +#define F_T5_RX_LINKEN V_T5_RX_LINKEN(1U) + +#define S_T5_RX_LINKRST 14 +#define V_T5_RX_LINKRST(x) ((x) << S_T5_RX_LINKRST) +#define F_T5_RX_LINKRST V_T5_RX_LINKRST(1U) + +#define S_T5_RX_CFGWRT 13 +#define V_T5_RX_CFGWRT(x) ((x) << S_T5_RX_CFGWRT) +#define F_T5_RX_CFGWRT V_T5_RX_CFGWRT(1U) + +#define S_T5_RX_CFGPTR 11 +#define M_T5_RX_CFGPTR 0x3U +#define V_T5_RX_CFGPTR(x) ((x) << S_T5_RX_CFGPTR) +#define G_T5_RX_CFGPTR(x) (((x) >> S_T5_RX_CFGPTR) & M_T5_RX_CFGPTR) + +#define S_T5_RX_CFGEXT 10 +#define V_T5_RX_CFGEXT(x) ((x) << S_T5_RX_CFGEXT) +#define F_T5_RX_CFGEXT V_T5_RX_CFGEXT(1U) + +#define S_T5_RX_CFGACT 9 +#define V_T5_RX_CFGACT(x) ((x) << S_T5_RX_CFGACT) +#define F_T5_RX_CFGACT V_T5_RX_CFGACT(1U) + +#define S_T5_RX_AUXCLK 8 +#define V_T5_RX_AUXCLK(x) ((x) << S_T5_RX_AUXCLK) +#define F_T5_RX_AUXCLK V_T5_RX_AUXCLK(1U) + +#define S_T5_RX_PLLSEL 6 +#define M_T5_RX_PLLSEL 0x3U +#define V_T5_RX_PLLSEL(x) ((x) << S_T5_RX_PLLSEL) +#define G_T5_RX_PLLSEL(x) (((x) >> S_T5_RX_PLLSEL) & M_T5_RX_PLLSEL) + +#define S_T5_RX_DMSEL 4 +#define M_T5_RX_DMSEL 0x3U +#define V_T5_RX_DMSEL(x) ((x) << S_T5_RX_DMSEL) +#define G_T5_RX_DMSEL(x) (((x) >> S_T5_RX_DMSEL) & M_T5_RX_DMSEL) + +#define S_T5_RX_BWSEL 2 +#define M_T5_RX_BWSEL 0x3U +#define V_T5_RX_BWSEL(x) ((x) << S_T5_RX_BWSEL) +#define G_T5_RX_BWSEL(x) (((x) >> S_T5_RX_BWSEL) & M_T5_RX_BWSEL) + +#define S_T5_RX_RTSEL 0 +#define M_T5_RX_RTSEL 0x3U +#define V_T5_RX_RTSEL(x) ((x) << S_T5_RX_RTSEL) +#define G_T5_RX_RTSEL(x) (((x) >> S_T5_RX_RTSEL) & M_T5_RX_RTSEL) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204 + +#define S_FERRST 10 +#define V_FERRST(x) ((x) << S_FERRST) +#define F_FERRST V_FERRST(1U) + +#define S_ERRST 9 +#define V_ERRST(x) ((x) << S_ERRST) +#define F_ERRST V_ERRST(1U) + +#define S_SYNCST 8 +#define V_SYNCST(x) ((x) << S_SYNCST) +#define F_SYNCST V_SYNCST(1U) + +#define S_WRPSM 7 +#define V_WRPSM(x) ((x) << S_WRPSM) +#define F_WRPSM V_WRPSM(1U) + +#define S_WPLPEN 6 +#define V_WPLPEN(x) ((x) << S_WPLPEN) +#define F_WPLPEN V_WPLPEN(1U) + +#define S_WRPMD 5 +#define V_WRPMD(x) ((x) << S_WRPMD) +#define F_WRPMD V_WRPMD(1U) + +#define S_PATSEL 0 +#define M_PATSEL 0x7U +#define V_PATSEL(x) ((x) << S_PATSEL) +#define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL) + +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208 + +#define S_RSTUCK 3 +#define V_RSTUCK(x) ((x) << S_RSTUCK) +#define F_RSTUCK V_RSTUCK(1U) + +#define S_FRZFW 2 +#define V_FRZFW(x) ((x) << S_FRZFW) +#define F_FRZFW V_FRZFW(1U) + +#define S_RSTFW 1 +#define V_RSTFW(x) ((x) << S_RSTFW) +#define F_RSTFW V_RSTFW(1U) + +#define S_SSCEN 0 +#define V_SSCEN(x) ((x) << S_SSCEN) +#define F_SSCEN V_SSCEN(1U) + +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210 + +#define S_ROT00 0 +#define M_ROT00 0x3fU +#define V_ROT00(x) ((x) << S_ROT00) +#define G_ROT00(x) (((x) >> S_ROT00) & M_ROT00) + +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214 + +#define S_FREQFW 8 +#define M_FREQFW 0xffU +#define V_FREQFW(x) ((x) << S_FREQFW) +#define G_FREQFW(x) (((x) >> S_FREQFW) & M_FREQFW) + +#define S_FWSNAP 7 +#define V_FWSNAP(x) ((x) << S_FWSNAP) +#define F_FWSNAP V_FWSNAP(1U) + +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218 +#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c + +#define S_RBOOFF 10 +#define M_RBOOFF 0x1fU +#define V_RBOOFF(x) ((x) << S_RBOOFF) +#define G_RBOOFF(x) (((x) >> S_RBOOFF) & M_RBOOFF) + +#define S_RBEOFF 5 +#define M_RBEOFF 0x1fU +#define V_RBEOFF(x) ((x) << S_RBEOFF) +#define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF) + +#define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220 +#define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224 + +#define S_T5BYTE1 8 +#define M_T5BYTE1 0xffU +#define V_T5BYTE1(x) ((x) << S_T5BYTE1) +#define G_T5BYTE1(x) (((x) >> S_T5BYTE1) & M_T5BYTE1) + +#define S_T5BYTE0 0 +#define M_T5BYTE0 0xffU +#define V_T5BYTE0(x) ((x) << S_T5BYTE0) +#define G_T5BYTE0(x) (((x) >> S_T5BYTE0) & M_T5BYTE0) + +#define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 0x3228 + +#define S_T5_RX_SMODE 8 +#define M_T5_RX_SMODE 0x7U +#define V_T5_RX_SMODE(x) ((x) << S_T5_RX_SMODE) +#define G_T5_RX_SMODE(x) (((x) >> S_T5_RX_SMODE) & M_T5_RX_SMODE) + +#define S_T5_RX_ADCORR 7 +#define V_T5_RX_ADCORR(x) ((x) << S_T5_RX_ADCORR) +#define F_T5_RX_ADCORR V_T5_RX_ADCORR(1U) + +#define S_T5_RX_TRAINEN 6 +#define V_T5_RX_TRAINEN(x) ((x) << S_T5_RX_TRAINEN) +#define F_T5_RX_TRAINEN V_T5_RX_TRAINEN(1U) + +#define S_T5_RX_ASAMPQ 3 +#define M_T5_RX_ASAMPQ 0x7U +#define V_T5_RX_ASAMPQ(x) ((x) << S_T5_RX_ASAMPQ) +#define G_T5_RX_ASAMPQ(x) (((x) >> S_T5_RX_ASAMPQ) & M_T5_RX_ASAMPQ) + +#define S_T5_RX_ASAMP 0 +#define M_T5_RX_ASAMP 0x7U +#define V_T5_RX_ASAMP(x) ((x) << S_T5_RX_ASAMP) +#define G_T5_RX_ASAMP(x) (((x) >> S_T5_RX_ASAMP) & M_T5_RX_ASAMP) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c +#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230 + +#define S_T5SHORTV 10 +#define V_T5SHORTV(x) ((x) << S_T5SHORTV) +#define F_T5SHORTV V_T5SHORTV(1U) + +#define S_T5VGAIN 0 +#define M_T5VGAIN 0x1fU +#define V_T5VGAIN(x) ((x) << S_T5VGAIN) +#define G_T5VGAIN(x) (((x) >> S_T5VGAIN) & M_T5VGAIN) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234 +#define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238 + +#define S_IQSEP 10 +#define M_IQSEP 0x1fU +#define V_IQSEP(x) ((x) << S_IQSEP) +#define G_IQSEP(x) (((x) >> S_IQSEP) & M_IQSEP) + +#define S_DUTYQ 5 +#define M_DUTYQ 0x1fU +#define V_DUTYQ(x) ((x) << S_DUTYQ) +#define G_DUTYQ(x) (((x) >> S_DUTYQ) & M_DUTYQ) + +#define S_DUTYI 0 +#define M_DUTYI 0x1fU +#define V_DUTYI(x) ((x) << S_DUTYI) +#define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240 + +#define S_DTHR 8 +#define M_DTHR 0x3fU +#define V_DTHR(x) ((x) << S_DTHR) +#define G_DTHR(x) (((x) >> S_DTHR) & M_DTHR) + +#define S_SNUL 0 +#define M_SNUL 0x1fU +#define V_SNUL(x) ((x) << S_SNUL) +#define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248 +#define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c +#define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250 + +#define S_ADSN_READWRITE 8 +#define V_ADSN_READWRITE(x) ((x) << S_ADSN_READWRITE) +#define F_ADSN_READWRITE V_ADSN_READWRITE(1U) + +#define S_ADSN_READONLY 7 +#define V_ADSN_READONLY(x) ((x) << S_ADSN_READONLY) +#define F_ADSN_READONLY V_ADSN_READONLY(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c + +#define S_H1O2 8 +#define M_H1O2 0x3fU +#define V_H1O2(x) ((x) << S_H1O2) +#define G_H1O2(x) (((x) >> S_H1O2) & M_H1O2) + +#define S_H1E2 0 +#define M_H1E2 0x3fU +#define V_H1E2(x) ((x) << S_H1E2) +#define G_H1E2(x) (((x) >> S_H1E2) & M_H1E2) + +#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260 + +#define S_H1O3 8 +#define M_H1O3 0x3fU +#define V_H1O3(x) ((x) << S_H1O3) +#define G_H1O3(x) (((x) >> S_H1O3) & M_H1O3) + +#define S_H1E3 0 +#define M_H1E3 0x3fU +#define V_H1E3(x) ((x) << S_H1E3) +#define G_H1E3(x) (((x) >> S_H1E3) & M_H1E3) + +#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264 + +#define S_H1O4 8 +#define M_H1O4 0x3fU +#define V_H1O4(x) ((x) << S_H1O4) +#define G_H1O4(x) (((x) >> S_H1O4) & M_H1O4) + +#define S_H1E4 0 +#define M_H1E4 0x3fU +#define V_H1E4(x) ((x) << S_H1E4) +#define G_H1E4(x) (((x) >> S_H1E4) & M_H1E4) + +#define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270 + +#define S_DPCMD 14 +#define V_DPCMD(x) ((x) << S_DPCMD) +#define F_DPCMD V_DPCMD(1U) + +#define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274 +#define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278 + +#define S_T5BER6VAL 15 +#define V_T5BER6VAL(x) ((x) << S_T5BER6VAL) +#define F_T5BER6VAL V_T5BER6VAL(1U) + +#define S_T5BER6 14 +#define V_T5BER6(x) ((x) << S_T5BER6) +#define F_T5BER6 V_T5BER6(1U) + +#define S_T5BER3VAL 13 +#define V_T5BER3VAL(x) ((x) << S_T5BER3VAL) +#define F_T5BER3VAL V_T5BER3VAL(1U) + +#define S_T5TOOFAST 12 +#define V_T5TOOFAST(x) ((x) << S_T5TOOFAST) +#define F_T5TOOFAST V_T5TOOFAST(1U) + +#define S_T5DPCCMP 9 +#define V_T5DPCCMP(x) ((x) << S_T5DPCCMP) +#define F_T5DPCCMP V_T5DPCCMP(1U) + +#define S_T5DACCMP 8 +#define V_T5DACCMP(x) ((x) << S_T5DACCMP) +#define F_T5DACCMP V_T5DACCMP(1U) + +#define S_T5DDCCMP 7 +#define V_T5DDCCMP(x) ((x) << S_T5DDCCMP) +#define F_T5DDCCMP V_T5DDCCMP(1U) + +#define S_T5AERRFLG 6 +#define V_T5AERRFLG(x) ((x) << S_T5AERRFLG) +#define F_T5AERRFLG V_T5AERRFLG(1U) + +#define S_T5WERRFLG 5 +#define V_T5WERRFLG(x) ((x) << S_T5WERRFLG) +#define F_T5WERRFLG V_T5WERRFLG(1U) + +#define S_T5TRCMP 4 +#define V_T5TRCMP(x) ((x) << S_T5TRCMP) +#define F_T5TRCMP V_T5TRCMP(1U) + +#define S_T5VLCKF 3 +#define V_T5VLCKF(x) ((x) << S_T5VLCKF) +#define F_T5VLCKF V_T5VLCKF(1U) + +#define S_T5ROCCMP 2 +#define V_T5ROCCMP(x) ((x) << S_T5ROCCMP) +#define F_T5ROCCMP V_T5ROCCMP(1U) + +#define S_T5DQCCCMP 1 +#define V_T5DQCCCMP(x) ((x) << S_T5DQCCCMP) +#define F_T5DQCCCMP V_T5DQCCCMP(1U) + +#define S_T5OCCMP 0 +#define V_T5OCCMP(x) ((x) << S_T5OCCMP) +#define F_T5OCCMP V_T5OCCMP(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c + +#define S_FLOFF 1 +#define V_FLOFF(x) ((x) << S_FLOFF) +#define F_FLOFF V_FLOFF(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 0x3280 + +#define S_H25SPC 15 +#define V_H25SPC(x) ((x) << S_H25SPC) +#define F_H25SPC V_H25SPC(1U) + +#define S_FTOOFAST 8 +#define V_FTOOFAST(x) ((x) << S_FTOOFAST) +#define F_FTOOFAST V_FTOOFAST(1U) + +#define S_FINTTRIM 7 +#define V_FINTTRIM(x) ((x) << S_FINTTRIM) +#define F_FINTTRIM V_FINTTRIM(1U) + +#define S_FDINV 6 +#define V_FDINV(x) ((x) << S_FDINV) +#define F_FDINV V_FDINV(1U) + +#define S_FHGS 5 +#define V_FHGS(x) ((x) << S_FHGS) +#define F_FHGS V_FHGS(1U) + +#define S_FH6H12 4 +#define V_FH6H12(x) ((x) << S_FH6H12) +#define F_FH6H12 V_FH6H12(1U) + +#define S_FH1CAL 3 +#define V_FH1CAL(x) ((x) << S_FH1CAL) +#define F_FH1CAL V_FH1CAL(1U) + +#define S_FINTCAL 2 +#define V_FINTCAL(x) ((x) << S_FINTCAL) +#define F_FINTCAL V_FINTCAL(1U) + +#define S_FDCA 1 +#define V_FDCA(x) ((x) << S_FDCA) +#define F_FDCA V_FDCA(1U) + +#define S_FDQCC 0 +#define V_FDQCC(x) ((x) << S_FDQCC) +#define F_FDQCC V_FDQCC(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284 + +#define S_LOFE2S_READWRITE 16 +#define V_LOFE2S_READWRITE(x) ((x) << S_LOFE2S_READWRITE) +#define F_LOFE2S_READWRITE V_LOFE2S_READWRITE(1U) + +#define S_LOFE2S_READONLY 14 +#define M_LOFE2S_READONLY 0x3U +#define V_LOFE2S_READONLY(x) ((x) << S_LOFE2S_READONLY) +#define G_LOFE2S_READONLY(x) (((x) >> S_LOFE2S_READONLY) & M_LOFE2S_READONLY) + +#define S_LOFE2 8 +#define M_LOFE2 0x3fU +#define V_LOFE2(x) ((x) << S_LOFE2) +#define G_LOFE2(x) (((x) >> S_LOFE2) & M_LOFE2) + +#define S_LOFE1S_READWRITE 7 +#define V_LOFE1S_READWRITE(x) ((x) << S_LOFE1S_READWRITE) +#define F_LOFE1S_READWRITE V_LOFE1S_READWRITE(1U) + +#define S_LOFE1S_READONLY 6 +#define V_LOFE1S_READONLY(x) ((x) << S_LOFE1S_READONLY) +#define F_LOFE1S_READONLY V_LOFE1S_READONLY(1U) + +#define S_LOFE1 0 +#define M_LOFE1 0x3fU +#define V_LOFE1(x) ((x) << S_LOFE1) +#define G_LOFE1(x) (((x) >> S_LOFE1) & M_LOFE1) + +#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288 + +#define S_LOFO2S_READWRITE 15 +#define V_LOFO2S_READWRITE(x) ((x) << S_LOFO2S_READWRITE) +#define F_LOFO2S_READWRITE V_LOFO2S_READWRITE(1U) + +#define S_LOFO2S_READONLY 14 +#define V_LOFO2S_READONLY(x) ((x) << S_LOFO2S_READONLY) +#define F_LOFO2S_READONLY V_LOFO2S_READONLY(1U) + +#define S_LOFO2 8 +#define M_LOFO2 0x3fU +#define V_LOFO2(x) ((x) << S_LOFO2) +#define G_LOFO2(x) (((x) >> S_LOFO2) & M_LOFO2) + +#define S_LOFO1S_READWRITE 7 +#define V_LOFO1S_READWRITE(x) ((x) << S_LOFO1S_READWRITE) +#define F_LOFO1S_READWRITE V_LOFO1S_READWRITE(1U) + +#define S_LOFO1S_READONLY 6 +#define V_LOFO1S_READONLY(x) ((x) << S_LOFO1S_READONLY) +#define F_LOFO1S_READONLY V_LOFO1S_READONLY(1U) + +#define S_LOFO1 0 +#define M_LOFO1 0x3fU +#define V_LOFO1(x) ((x) << S_LOFO1) +#define G_LOFO1(x) (((x) >> S_LOFO1) & M_LOFO1) + +#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c + +#define S_LOFE4S_READWRITE 15 +#define V_LOFE4S_READWRITE(x) ((x) << S_LOFE4S_READWRITE) +#define F_LOFE4S_READWRITE V_LOFE4S_READWRITE(1U) + +#define S_LOFE4S_READONLY 14 +#define V_LOFE4S_READONLY(x) ((x) << S_LOFE4S_READONLY) +#define F_LOFE4S_READONLY V_LOFE4S_READONLY(1U) + +#define S_LOFE 8 +#define M_LOFE 0x3fU +#define V_LOFE(x) ((x) << S_LOFE) +#define G_LOFE(x) (((x) >> S_LOFE) & M_LOFE) + +#define S_LOFE3S_READWRITE 7 +#define V_LOFE3S_READWRITE(x) ((x) << S_LOFE3S_READWRITE) +#define F_LOFE3S_READWRITE V_LOFE3S_READWRITE(1U) + +#define S_LOFE3S_READONLY 6 +#define V_LOFE3S_READONLY(x) ((x) << S_LOFE3S_READONLY) +#define F_LOFE3S_READONLY V_LOFE3S_READONLY(1U) + +#define S_LOFE3 0 +#define M_LOFE3 0x3fU +#define V_LOFE3(x) ((x) << S_LOFE3) +#define G_LOFE3(x) (((x) >> S_LOFE3) & M_LOFE3) + +#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290 + +#define S_LOFO4S_READWRITE 15 +#define V_LOFO4S_READWRITE(x) ((x) << S_LOFO4S_READWRITE) +#define F_LOFO4S_READWRITE V_LOFO4S_READWRITE(1U) + +#define S_LOFO4S_READONLY 14 +#define V_LOFO4S_READONLY(x) ((x) << S_LOFO4S_READONLY) +#define F_LOFO4S_READONLY V_LOFO4S_READONLY(1U) + +#define S_LOFO4 8 +#define M_LOFO4 0x3fU +#define V_LOFO4(x) ((x) << S_LOFO4) +#define G_LOFO4(x) (((x) >> S_LOFO4) & M_LOFO4) + +#define S_LOFO3S_READWRITE 7 +#define V_LOFO3S_READWRITE(x) ((x) << S_LOFO3S_READWRITE) +#define F_LOFO3S_READWRITE V_LOFO3S_READWRITE(1U) + +#define S_LOFO3S_READONLY 6 +#define V_LOFO3S_READONLY(x) ((x) << S_LOFO3S_READONLY) +#define F_LOFO3S_READONLY V_LOFO3S_READONLY(1U) + +#define S_LOFO3 0 +#define M_LOFO3 0x3fU +#define V_LOFO3(x) ((x) << S_LOFO3) +#define G_LOFO3(x) (((x) >> S_LOFO3) & M_LOFO3) + +#define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294 + +#define S_T5E1SN_READWRITE 15 +#define V_T5E1SN_READWRITE(x) ((x) << S_T5E1SN_READWRITE) +#define F_T5E1SN_READWRITE V_T5E1SN_READWRITE(1U) + +#define S_T5E1SN_READONLY 14 +#define V_T5E1SN_READONLY(x) ((x) << S_T5E1SN_READONLY) +#define F_T5E1SN_READONLY V_T5E1SN_READONLY(1U) + +#define S_T5E1AMP 8 +#define M_T5E1AMP 0x3fU +#define V_T5E1AMP(x) ((x) << S_T5E1AMP) +#define G_T5E1AMP(x) (((x) >> S_T5E1AMP) & M_T5E1AMP) + +#define S_T5E0SN_READWRITE 7 +#define V_T5E0SN_READWRITE(x) ((x) << S_T5E0SN_READWRITE) +#define F_T5E0SN_READWRITE V_T5E0SN_READWRITE(1U) + +#define S_T5E0SN_READONLY 6 +#define V_T5E0SN_READONLY(x) ((x) << S_T5E0SN_READONLY) +#define F_T5E0SN_READONLY V_T5E0SN_READONLY(1U) + +#define S_T5E0AMP 0 +#define M_T5E0AMP 0x3fU +#define V_T5E0AMP(x) ((x) << S_T5E0AMP) +#define G_T5E0AMP(x) (((x) >> S_T5E0AMP) & M_T5E0AMP) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL 0x3298 + +#define S_T5LFREG 12 +#define V_T5LFREG(x) ((x) << S_T5LFREG) +#define F_T5LFREG V_T5LFREG(1U) + +#define S_T5LFRC 11 +#define V_T5LFRC(x) ((x) << S_T5LFRC) +#define F_T5LFRC V_T5LFRC(1U) + +#define S_T5LFSEL 8 +#define M_T5LFSEL 0x7U +#define V_T5LFSEL(x) ((x) << S_T5LFSEL) +#define G_T5LFSEL(x) (((x) >> S_T5LFSEL) & M_T5LFSEL) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c + +#define S_OFFSN_READWRITE 14 +#define V_OFFSN_READWRITE(x) ((x) << S_OFFSN_READWRITE) +#define F_OFFSN_READWRITE V_OFFSN_READWRITE(1U) + +#define S_OFFSN_READONLY 13 +#define V_OFFSN_READONLY(x) ((x) << S_OFFSN_READONLY) +#define F_OFFSN_READONLY V_OFFSN_READONLY(1U) + +#define S_OFFAMP 8 +#define M_OFFAMP 0x1fU +#define V_OFFAMP(x) ((x) << S_OFFAMP) +#define G_OFFAMP(x) (((x) >> S_OFFAMP) & M_OFFAMP) + +#define S_SDACDC 7 +#define V_SDACDC(x) ((x) << S_SDACDC) +#define F_SDACDC V_SDACDC(1U) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0 + +#define S_T5_RX_SETHDIS 7 +#define V_T5_RX_SETHDIS(x) ((x) << S_T5_RX_SETHDIS) +#define F_T5_RX_SETHDIS V_T5_RX_SETHDIS(1U) + +#define S_T5_RX_PDTERM 6 +#define V_T5_RX_PDTERM(x) ((x) << S_T5_RX_PDTERM) +#define F_T5_RX_PDTERM V_T5_RX_PDTERM(1U) + +#define S_T5_RX_BYPASS 5 +#define V_T5_RX_BYPASS(x) ((x) << S_T5_RX_BYPASS) +#define F_T5_RX_BYPASS V_T5_RX_BYPASS(1U) + +#define S_T5_RX_LPFEN 4 +#define V_T5_RX_LPFEN(x) ((x) << S_T5_RX_LPFEN) +#define F_T5_RX_LPFEN V_T5_RX_LPFEN(1U) + +#define S_T5_RX_VGABOD 3 +#define V_T5_RX_VGABOD(x) ((x) << S_T5_RX_VGABOD) +#define F_T5_RX_VGABOD V_T5_RX_VGABOD(1U) + +#define S_T5_RX_VTBYP 2 +#define V_T5_RX_VTBYP(x) ((x) << S_T5_RX_VTBYP) +#define F_T5_RX_VTBYP V_T5_RX_VTBYP(1U) + +#define S_T5_RX_VTERM 0 +#define M_T5_RX_VTERM 0x3U +#define V_T5_RX_VTERM(x) ((x) << S_T5_RX_VTERM) +#define G_T5_RX_VTERM(x) (((x) >> S_T5_RX_VTERM) & M_T5_RX_VTERM) + +#define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4 + +#define S_ISTRIMS 14 +#define M_ISTRIMS 0x3U +#define V_ISTRIMS(x) ((x) << S_ISTRIMS) +#define G_ISTRIMS(x) (((x) >> S_ISTRIMS) & M_ISTRIMS) + +#define S_ISTRIM 8 +#define M_ISTRIM 0x3fU +#define V_ISTRIM(x) ((x) << S_ISTRIM) +#define G_ISTRIM(x) (((x) >> S_ISTRIM) & M_ISTRIM) + +#define S_HALF1 7 +#define V_HALF1(x) ((x) << S_HALF1) +#define F_HALF1 V_HALF1(1U) + +#define S_HALF2 6 +#define V_HALF2(x) ((x) << S_HALF2) +#define F_HALF2 V_HALF2(1U) + +#define S_INTDAC 0 +#define M_INTDAC 0x3fU +#define V_INTDAC(x) ((x) << S_INTDAC) +#define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC) + +#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8 + +#define S_MINWDTH 5 +#define M_MINWDTH 0x1fU +#define V_MINWDTH(x) ((x) << S_MINWDTH) +#define G_MINWDTH(x) (((x) >> S_MINWDTH) & M_MINWDTH) + +#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS 0x32ac + +#define S_T5SMQM 13 +#define M_T5SMQM 0x7U +#define V_T5SMQM(x) ((x) << S_T5SMQM) +#define G_T5SMQM(x) (((x) >> S_T5SMQM) & M_T5SMQM) + +#define S_T5SMQ 5 +#define M_T5SMQ 0xffU +#define V_T5SMQ(x) ((x) << S_T5SMQ) +#define G_T5SMQ(x) (((x) >> S_T5SMQ) & M_T5SMQ) + +#define S_T5EMMD 3 +#define M_T5EMMD 0x3U +#define V_T5EMMD(x) ((x) << S_T5EMMD) +#define G_T5EMMD(x) (((x) >> S_T5EMMD) & M_T5EMMD) + +#define S_T5EMBRDY 2 +#define V_T5EMBRDY(x) ((x) << S_T5EMBRDY) +#define F_T5EMBRDY V_T5EMBRDY(1U) + +#define S_T5EMBUMP 1 +#define V_T5EMBUMP(x) ((x) << S_T5EMBUMP) +#define F_T5EMBUMP V_T5EMBUMP(1U) + +#define S_T5EMEN 0 +#define V_T5EMEN(x) ((x) << S_T5EMEN) +#define F_T5EMEN V_T5EMEN(1U) + +#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0 + +#define S_EMF8 15 +#define V_EMF8(x) ((x) << S_EMF8) +#define F_EMF8 V_EMF8(1U) + +#define S_EMCNT 4 +#define M_EMCNT 0xffU +#define V_EMCNT(x) ((x) << S_EMCNT) +#define G_EMCNT(x) (((x) >> S_EMCNT) & M_EMCNT) + +#define S_EMOFLO 2 +#define V_EMOFLO(x) ((x) << S_EMOFLO) +#define F_EMOFLO V_EMOFLO(1U) + +#define S_EMCRST 1 +#define V_EMCRST(x) ((x) << S_EMCRST) +#define F_EMCRST V_EMCRST(1U) + +#define S_EMCEN 0 +#define V_EMCEN(x) ((x) << S_EMCEN) +#define F_EMCEN V_EMCEN(1U) + +#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4 + +#define S_SM2RDY 15 +#define V_SM2RDY(x) ((x) << S_SM2RDY) +#define F_SM2RDY V_SM2RDY(1U) + +#define S_SM2RST 14 +#define V_SM2RST(x) ((x) << S_SM2RST) +#define F_SM2RST V_SM2RST(1U) + +#define S_APDF 0 +#define M_APDF 0xfffU +#define V_APDF(x) ((x) << S_APDF) +#define G_APDF(x) (((x) >> S_APDF) & M_APDF) + +#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x32b8 + +#define S_SM0LEN 0 +#define M_SM0LEN 0x7fffU +#define V_SM0LEN(x) ((x) << S_SM0LEN) +#define G_SM0LEN(x) (((x) >> S_SM0LEN) & M_SM0LEN) + +#define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0 + +#define S_H_EN 1 +#define M_H_EN 0xfffU +#define V_H_EN(x) ((x) << S_H_EN) +#define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN) + +#define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4 +#define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8 + +#define S_H2OSN_READWRITE 14 +#define V_H2OSN_READWRITE(x) ((x) << S_H2OSN_READWRITE) +#define F_H2OSN_READWRITE V_H2OSN_READWRITE(1U) + +#define S_H2OSN_READONLY 13 +#define V_H2OSN_READONLY(x) ((x) << S_H2OSN_READONLY) +#define F_H2OSN_READONLY V_H2OSN_READONLY(1U) + +#define S_H2ESN_READWRITE 6 +#define V_H2ESN_READWRITE(x) ((x) << S_H2ESN_READWRITE) +#define F_H2ESN_READWRITE V_H2ESN_READWRITE(1U) + +#define S_H2ESN_READONLY 5 +#define V_H2ESN_READONLY(x) ((x) << S_H2ESN_READONLY) +#define F_H2ESN_READONLY V_H2ESN_READONLY(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_H3 0x32cc + +#define S_H3OSN_READWRITE 13 +#define V_H3OSN_READWRITE(x) ((x) << S_H3OSN_READWRITE) +#define F_H3OSN_READWRITE V_H3OSN_READWRITE(1U) + +#define S_H3OSN_READONLY 12 +#define V_H3OSN_READONLY(x) ((x) << S_H3OSN_READONLY) +#define F_H3OSN_READONLY V_H3OSN_READONLY(1U) + +#define S_H3ESN_READWRITE 5 +#define V_H3ESN_READWRITE(x) ((x) << S_H3ESN_READWRITE) +#define F_H3ESN_READWRITE V_H3ESN_READWRITE(1U) + +#define S_H3ESN_READONLY 4 +#define V_H3ESN_READONLY(x) ((x) << S_H3ESN_READONLY) +#define F_H3ESN_READONLY V_H3ESN_READONLY(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_H4 0x32d0 + +#define S_H4OGS 14 +#define M_H4OGS 0x3U +#define V_H4OGS(x) ((x) << S_H4OGS) +#define G_H4OGS(x) (((x) >> S_H4OGS) & M_H4OGS) + +#define S_H4OSN_READWRITE 13 +#define V_H4OSN_READWRITE(x) ((x) << S_H4OSN_READWRITE) +#define F_H4OSN_READWRITE V_H4OSN_READWRITE(1U) + +#define S_H4OSN_READONLY 12 +#define V_H4OSN_READONLY(x) ((x) << S_H4OSN_READONLY) +#define F_H4OSN_READONLY V_H4OSN_READONLY(1U) + +#define S_H4EGS 6 +#define M_H4EGS 0x3U +#define V_H4EGS(x) ((x) << S_H4EGS) +#define G_H4EGS(x) (((x) >> S_H4EGS) & M_H4EGS) + +#define S_H4ESN_READWRITE 5 +#define V_H4ESN_READWRITE(x) ((x) << S_H4ESN_READWRITE) +#define F_H4ESN_READWRITE V_H4ESN_READWRITE(1U) + +#define S_H4ESN_READONLY 4 +#define V_H4ESN_READONLY(x) ((x) << S_H4ESN_READONLY) +#define F_H4ESN_READONLY V_H4ESN_READONLY(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_H5 0x32d4 + +#define S_H5OGS 14 +#define M_H5OGS 0x3U +#define V_H5OGS(x) ((x) << S_H5OGS) +#define G_H5OGS(x) (((x) >> S_H5OGS) & M_H5OGS) + +#define S_H5OSN_READWRITE 13 +#define V_H5OSN_READWRITE(x) ((x) << S_H5OSN_READWRITE) +#define F_H5OSN_READWRITE V_H5OSN_READWRITE(1U) + +#define S_H5OSN_READONLY 12 +#define V_H5OSN_READONLY(x) ((x) << S_H5OSN_READONLY) +#define F_H5OSN_READONLY V_H5OSN_READONLY(1U) + +#define S_H5EGS 6 +#define M_H5EGS 0x3U +#define V_H5EGS(x) ((x) << S_H5EGS) +#define G_H5EGS(x) (((x) >> S_H5EGS) & M_H5EGS) + +#define S_H5ESN_READWRITE 5 +#define V_H5ESN_READWRITE(x) ((x) << S_H5ESN_READWRITE) +#define F_H5ESN_READWRITE V_H5ESN_READWRITE(1U) + +#define S_H5ESN_READONLY 4 +#define V_H5ESN_READONLY(x) ((x) << S_H5ESN_READONLY) +#define F_H5ESN_READONLY V_H5ESN_READONLY(1U) + +#define A_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x32d8 + +#define S_H7GS 14 +#define M_H7GS 0x3U +#define V_H7GS(x) ((x) << S_H7GS) +#define G_H7GS(x) (((x) >> S_H7GS) & M_H7GS) + +#define S_H7SN_READWRITE 13 +#define V_H7SN_READWRITE(x) ((x) << S_H7SN_READWRITE) +#define F_H7SN_READWRITE V_H7SN_READWRITE(1U) + +#define S_H7SN_READONLY 12 +#define V_H7SN_READONLY(x) ((x) << S_H7SN_READONLY) +#define F_H7SN_READONLY V_H7SN_READONLY(1U) + +#define S_H7MAG 8 +#define M_H7MAG 0xfU +#define V_H7MAG(x) ((x) << S_H7MAG) +#define G_H7MAG(x) (((x) >> S_H7MAG) & M_H7MAG) + +#define S_H6GS 6 +#define M_H6GS 0x3U +#define V_H6GS(x) ((x) << S_H6GS) +#define G_H6GS(x) (((x) >> S_H6GS) & M_H6GS) + +#define S_H6SN_READWRITE 5 +#define V_H6SN_READWRITE(x) ((x) << S_H6SN_READWRITE) +#define F_H6SN_READWRITE V_H6SN_READWRITE(1U) + +#define S_H6SN_READONLY 4 +#define V_H6SN_READONLY(x) ((x) << S_H6SN_READONLY) +#define F_H6SN_READONLY V_H6SN_READONLY(1U) + +#define S_H6MAG 0 +#define M_H6MAG 0xfU +#define V_H6MAG(x) ((x) << S_H6MAG) +#define G_H6MAG(x) (((x) >> S_H6MAG) & M_H6MAG) + +#define A_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x32dc + +#define S_H9GS 14 +#define M_H9GS 0x3U +#define V_H9GS(x) ((x) << S_H9GS) +#define G_H9GS(x) (((x) >> S_H9GS) & M_H9GS) + +#define S_H9SN_READWRITE 13 +#define V_H9SN_READWRITE(x) ((x) << S_H9SN_READWRITE) +#define F_H9SN_READWRITE V_H9SN_READWRITE(1U) + +#define S_H9SN_READONLY 12 +#define V_H9SN_READONLY(x) ((x) << S_H9SN_READONLY) +#define F_H9SN_READONLY V_H9SN_READONLY(1U) + +#define S_H9MAG 8 +#define M_H9MAG 0xfU +#define V_H9MAG(x) ((x) << S_H9MAG) +#define G_H9MAG(x) (((x) >> S_H9MAG) & M_H9MAG) + +#define S_H8GS 6 +#define M_H8GS 0x3U +#define V_H8GS(x) ((x) << S_H8GS) +#define G_H8GS(x) (((x) >> S_H8GS) & M_H8GS) + +#define S_H8SN_READWRITE 5 +#define V_H8SN_READWRITE(x) ((x) << S_H8SN_READWRITE) +#define F_H8SN_READWRITE V_H8SN_READWRITE(1U) + +#define S_H8SN_READONLY 4 +#define V_H8SN_READONLY(x) ((x) << S_H8SN_READONLY) +#define F_H8SN_READONLY V_H8SN_READONLY(1U) + +#define S_H8MAG 0 +#define M_H8MAG 0xfU +#define V_H8MAG(x) ((x) << S_H8MAG) +#define G_H8MAG(x) (((x) >> S_H8MAG) & M_H8MAG) + +#define A_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x32e0 + +#define S_H11GS 14 +#define M_H11GS 0x3U +#define V_H11GS(x) ((x) << S_H11GS) +#define G_H11GS(x) (((x) >> S_H11GS) & M_H11GS) + +#define S_H11SN_READWRITE 13 +#define V_H11SN_READWRITE(x) ((x) << S_H11SN_READWRITE) +#define F_H11SN_READWRITE V_H11SN_READWRITE(1U) + +#define S_H11SN_READONLY 12 +#define V_H11SN_READONLY(x) ((x) << S_H11SN_READONLY) +#define F_H11SN_READONLY V_H11SN_READONLY(1U) + +#define S_H11MAG 8 +#define M_H11MAG 0xfU +#define V_H11MAG(x) ((x) << S_H11MAG) +#define G_H11MAG(x) (((x) >> S_H11MAG) & M_H11MAG) + +#define S_H10GS 6 +#define M_H10GS 0x3U +#define V_H10GS(x) ((x) << S_H10GS) +#define G_H10GS(x) (((x) >> S_H10GS) & M_H10GS) + +#define S_H10SN_READWRITE 5 +#define V_H10SN_READWRITE(x) ((x) << S_H10SN_READWRITE) +#define F_H10SN_READWRITE V_H10SN_READWRITE(1U) + +#define S_H10SN_READONLY 4 +#define V_H10SN_READONLY(x) ((x) << S_H10SN_READONLY) +#define F_H10SN_READONLY V_H10SN_READONLY(1U) + +#define S_H10MAG 0 +#define M_H10MAG 0xfU +#define V_H10MAG(x) ((x) << S_H10MAG) +#define G_H10MAG(x) (((x) >> S_H10MAG) & M_H10MAG) + +#define A_MAC_PORT_RX_LINKA_DFE_H12 0x32e4 + +#define S_H12GS 6 +#define M_H12GS 0x3U +#define V_H12GS(x) ((x) << S_H12GS) +#define G_H12GS(x) (((x) >> S_H12GS) & M_H12GS) + +#define S_H12SN_READWRITE 5 +#define V_H12SN_READWRITE(x) ((x) << S_H12SN_READWRITE) +#define F_H12SN_READWRITE V_H12SN_READWRITE(1U) + +#define S_H12SN_READONLY 4 +#define V_H12SN_READONLY(x) ((x) << S_H12SN_READONLY) +#define F_H12SN_READONLY V_H12SN_READONLY(1U) + +#define S_H12MAG 0 +#define M_H12MAG 0xfU +#define V_H12MAG(x) ((x) << S_H12MAG) +#define G_H12MAG(x) (((x) >> S_H12MAG) & M_H12MAG) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8 + +#define S_DFEDACLSSD 6 +#define V_DFEDACLSSD(x) ((x) << S_DFEDACLSSD) +#define F_DFEDACLSSD V_DFEDACLSSD(1U) + +#define S_SDLSSD 5 +#define V_SDLSSD(x) ((x) << S_SDLSSD) +#define F_SDLSSD V_SDLSSD(1U) + +#define S_DFEOBSBIAS 4 +#define V_DFEOBSBIAS(x) ((x) << S_DFEOBSBIAS) +#define F_DFEOBSBIAS V_DFEOBSBIAS(1U) + +#define S_GBOFSTLSSD 3 +#define V_GBOFSTLSSD(x) ((x) << S_GBOFSTLSSD) +#define F_GBOFSTLSSD V_GBOFSTLSSD(1U) + +#define S_RXDOBS 2 +#define V_RXDOBS(x) ((x) << S_RXDOBS) +#define F_RXDOBS V_RXDOBS(1U) + +#define S_ACJZPT 1 +#define V_ACJZPT(x) ((x) << S_ACJZPT) +#define F_ACJZPT V_ACJZPT(1U) + +#define S_ACJZNT 0 +#define V_ACJZNT(x) ((x) << S_ACJZNT) +#define F_ACJZNT V_ACJZNT(1U) + +#define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc + +#define S_PHSLOCK 10 +#define V_PHSLOCK(x) ((x) << S_PHSLOCK) +#define F_PHSLOCK V_PHSLOCK(1U) + +#define S_TESTMODE 9 +#define V_TESTMODE(x) ((x) << S_TESTMODE) +#define F_TESTMODE V_TESTMODE(1U) + +#define S_CALMODE 8 +#define V_CALMODE(x) ((x) << S_CALMODE) +#define F_CALMODE V_CALMODE(1U) + +#define S_AMPSEL 7 +#define V_AMPSEL(x) ((x) << S_AMPSEL) +#define F_AMPSEL V_AMPSEL(1U) + +#define S_WHICHNRZ 6 +#define V_WHICHNRZ(x) ((x) << S_WHICHNRZ) +#define F_WHICHNRZ V_WHICHNRZ(1U) + +#define S_BANKA 5 +#define V_BANKA(x) ((x) << S_BANKA) +#define F_BANKA V_BANKA(1U) + +#define S_BANKB 4 +#define V_BANKB(x) ((x) << S_BANKB) +#define F_BANKB V_BANKB(1U) + +#define S_ACJPDP 3 +#define V_ACJPDP(x) ((x) << S_ACJPDP) +#define F_ACJPDP V_ACJPDP(1U) + +#define S_ACJPDN 2 +#define V_ACJPDN(x) ((x) << S_ACJPDN) +#define F_ACJPDN V_ACJPDN(1U) + +#define S_LSSDT 1 +#define V_LSSDT(x) ((x) << S_LSSDT) +#define F_LSSDT V_LSSDT(1U) + +#define S_MTHOLD 0 +#define V_MTHOLD(x) ((x) << S_MTHOLD) +#define F_MTHOLD V_MTHOLD(1U) + +#define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300 +#define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304 +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308 +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310 +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314 +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318 +#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c +#define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320 +#define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324 +#define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328 +#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c +#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330 +#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334 +#define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338 +#define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340 +#define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348 +#define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c +#define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350 +#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c +#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360 +#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364 +#define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370 +#define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374 +#define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378 +#define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c +#define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380 +#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384 +#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388 +#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c +#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390 +#define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394 +#define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398 +#define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c +#define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0 +#define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4 +#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8 +#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac +#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0 +#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4 +#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8 +#define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0 +#define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4 +#define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8 +#define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc +#define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0 +#define A_MAC_PORT_RX_LINKB_DFE_H5 0x33d4 +#define A_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x33d8 +#define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc +#define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0 +#define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4 +#define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8 +#define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc +#define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c +#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc +#define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c +#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc +#define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600 +#define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604 +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608 +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610 +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614 +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618 +#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c +#define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620 +#define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624 +#define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628 +#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c +#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630 +#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634 +#define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638 +#define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640 +#define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648 +#define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c +#define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650 +#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c +#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660 +#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664 +#define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670 +#define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674 +#define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678 +#define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c +#define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680 +#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684 +#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688 +#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c +#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690 +#define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694 +#define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698 +#define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c +#define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0 +#define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4 +#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8 +#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac +#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0 +#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4 +#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8 +#define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0 +#define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4 +#define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8 +#define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc +#define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0 +#define A_MAC_PORT_RX_LINKC_DFE_H5 0x36d4 +#define A_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x36d8 +#define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc +#define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0 +#define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4 +#define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8 +#define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc +#define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700 +#define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704 +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708 +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710 +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714 +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718 +#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c +#define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720 +#define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724 +#define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728 +#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c +#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730 +#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734 +#define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738 +#define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740 +#define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748 +#define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c +#define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750 +#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c +#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760 +#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764 +#define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770 +#define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774 +#define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778 +#define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c +#define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780 +#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784 +#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788 +#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c +#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790 +#define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794 +#define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798 +#define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c +#define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0 +#define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4 +#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8 +#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac +#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0 +#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4 +#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8 +#define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0 +#define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4 +#define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8 +#define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc +#define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0 +#define A_MAC_PORT_RX_LINKD_DFE_H5 0x37d4 +#define A_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x37d8 +#define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc +#define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0 +#define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4 +#define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8 +#define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc +#define A_MAC_PORT_ANALOG_TEST_MUX 0x3814 +#define A_MAC_PORT_BANDGAP_CONTROL 0x382c + +#define S_T5BGCTL 0 +#define M_T5BGCTL 0xfU +#define V_T5BGCTL(x) ((x) << S_T5BGCTL) +#define G_T5BGCTL(x) (((x) >> S_T5BGCTL) & M_T5BGCTL) + +#define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880 + +#define S_RCCTL1 5 +#define V_RCCTL1(x) ((x) << S_RCCTL1) +#define F_RCCTL1 V_RCCTL1(1U) + +#define S_RCCTL0 4 +#define V_RCCTL0(x) ((x) << S_RCCTL0) +#define F_RCCTL0 V_RCCTL0(1U) + +#define S_RCAMP1 3 +#define V_RCAMP1(x) ((x) << S_RCAMP1) +#define F_RCAMP1 V_RCAMP1(1U) + +#define S_RCAMP0 2 +#define V_RCAMP0(x) ((x) << S_RCAMP0) +#define F_RCAMP0 V_RCAMP0(1U) + +#define S_RCAMPEN 1 +#define V_RCAMPEN(x) ((x) << S_RCAMPEN) +#define F_RCAMPEN V_RCAMPEN(1U) + +#define S_RCRST 0 +#define V_RCRST(x) ((x) << S_RCRST) +#define F_RCRST V_RCRST(1U) + +#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884 + +#define S_RCERR 1 +#define V_RCERR(x) ((x) << S_RCERR) +#define F_RCERR V_RCERR(1U) + +#define S_RCCOMP 0 +#define V_RCCOMP(x) ((x) << S_RCCOMP) +#define F_RCCOMP V_RCCOMP(1U) + +#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888 + +#define S_RESREG2 0 +#define M_RESREG2 0xffU +#define V_RESREG2(x) ((x) << S_RESREG2) +#define G_RESREG2(x) (((x) >> S_RESREG2) & M_RESREG2) + +#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c + +#define S_RESREG3 0 +#define M_RESREG3 0xffU +#define V_RESREG3(x) ((x) << S_RESREG3) +#define G_RESREG3(x) (((x) >> S_RESREG3) & M_RESREG3) + +#define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8 + +#define S_LBIST 7 +#define V_LBIST(x) ((x) << S_LBIST) +#define F_LBIST V_LBIST(1U) + +#define S_LOGICTEST 6 +#define V_LOGICTEST(x) ((x) << S_LOGICTEST) +#define F_LOGICTEST V_LOGICTEST(1U) + +#define S_MAVDHI 5 +#define V_MAVDHI(x) ((x) << S_MAVDHI) +#define F_MAVDHI V_MAVDHI(1U) + +#define S_AUXEN 4 +#define V_AUXEN(x) ((x) << S_AUXEN) +#define F_AUXEN V_AUXEN(1U) + +#define S_JTAGMD 3 +#define V_JTAGMD(x) ((x) << S_JTAGMD) +#define F_JTAGMD V_JTAGMD(1U) + +#define S_RXACMODE 2 +#define V_RXACMODE(x) ((x) << S_RXACMODE) +#define F_RXACMODE V_RXACMODE(1U) + +#define S_HSSACJPC 1 +#define V_HSSACJPC(x) ((x) << S_HSSACJPC) +#define F_HSSACJPC V_HSSACJPC(1U) + +#define S_HSSACJAC 0 +#define V_HSSACJAC(x) ((x) << S_HSSACJAC) +#define F_HSSACJAC V_HSSACJAC(1U) + +#define A_MAC_PORT_MACRO_TEST_CONTROL_5 0x38ec + +#define S_REFVALIDD 6 +#define V_REFVALIDD(x) ((x) << S_REFVALIDD) +#define F_REFVALIDD V_REFVALIDD(1U) + +#define S_REFVALIDC 5 +#define V_REFVALIDC(x) ((x) << S_REFVALIDC) +#define F_REFVALIDC V_REFVALIDC(1U) + +#define S_REFVALIDB 4 +#define V_REFVALIDB(x) ((x) << S_REFVALIDB) +#define F_REFVALIDB V_REFVALIDB(1U) + +#define S_REFVALIDA 3 +#define V_REFVALIDA(x) ((x) << S_REFVALIDA) +#define F_REFVALIDA V_REFVALIDA(1U) + +#define S_REFSELRESET 2 +#define V_REFSELRESET(x) ((x) << S_REFSELRESET) +#define F_REFSELRESET V_REFSELRESET(1U) + +#define S_SOFTRESET 1 +#define V_SOFTRESET(x) ((x) << S_SOFTRESET) +#define F_SOFTRESET V_SOFTRESET(1U) + +#define S_MACROTEST 0 +#define V_MACROTEST(x) ((x) << S_MACROTEST) +#define F_MACROTEST V_MACROTEST(1U) + +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3948 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3960 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3964 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3968 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3970 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3974 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x398c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x3990 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x3994 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x3998 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04 +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08 +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10 +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14 +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18 +#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c +#define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20 +#define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24 +#define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 0x3a40 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN 0x3a48 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ 0x3a4c +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL 0x3a50 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x3a5c +#define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3a60 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3a64 +#define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3a70 +#define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78 +#define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 0x3a7c +#define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 0x3a80 +#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 0x3a84 +#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 0x3a88 +#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 0x3a8c +#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 0x3a90 +#define A_MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET 0x3a94 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL 0x3a98 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL 0x3a9c +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH 0x3aa0 +#define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4 +#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8 +#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac +#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0 +#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4 +#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8 +#define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3ac0 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3ac4 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3ac8 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H3 0x3acc +#define A_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3ad0 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3ad4 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3ad8 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x3adc +#define A_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3ae0 +#define A_MAC_PORT_RX_LINK_BCST_DFE_H12 0x3ae4 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 0x3af8 +#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 0x3afc +#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 0x3b00 +#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 0x3b04 +#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 0x3b08 +#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 0x3b0c +#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 0x3b10 +#define A_MAC_PORT_PLLA_CHARGE_PUMP_CONTROL 0x3b28 + +#define S_T5CPISEL 0 +#define M_T5CPISEL 0x7U +#define V_T5CPISEL(x) ((x) << S_T5CPISEL) +#define G_T5CPISEL(x) (((x) >> S_T5CPISEL) & M_T5CPISEL) + +#define A_MAC_PORT_PLLA_PCLK_CONTROL 0x3b3c + +#define S_SPEDIV 3 +#define M_SPEDIV 0x1fU +#define V_SPEDIV(x) ((x) << S_SPEDIV) +#define G_SPEDIV(x) (((x) >> S_SPEDIV) & M_SPEDIV) + +#define S_PCKSEL 0 +#define M_PCKSEL 0x7U +#define V_PCKSEL(x) ((x) << S_PCKSEL) +#define G_PCKSEL(x) (((x) >> S_PCKSEL) & M_PCKSEL) + +#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL 0x3b40 + +#define S_EMIL 2 +#define V_EMIL(x) ((x) << S_EMIL) +#define F_EMIL V_EMIL(1U) + +#define S_EMID 1 +#define V_EMID(x) ((x) << S_EMID) +#define F_EMID V_EMID(1U) + +#define S_EMIS 0 +#define V_EMIS(x) ((x) << S_EMIS) +#define F_EMIS V_EMIS(1U) + +#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1 0x3b44 + +#define S_EMIL1 0 +#define M_EMIL1 0xffU +#define V_EMIL1(x) ((x) << S_EMIL1) +#define G_EMIL1(x) (((x) >> S_EMIL1) & M_EMIL1) + +#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2 0x3b48 + +#define S_EMIL2 0 +#define M_EMIL2 0xffU +#define V_EMIL2(x) ((x) << S_EMIL2) +#define G_EMIL2(x) (((x) >> S_EMIL2) & M_EMIL2) + +#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3 0x3b4c + +#define S_EMIL3 0 +#define M_EMIL3 0xffU +#define V_EMIL3(x) ((x) << S_EMIL3) +#define G_EMIL3(x) (((x) >> S_EMIL3) & M_EMIL3) + +#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4 0x3b50 + +#define S_EMIL4 0 +#define M_EMIL4 0xffU +#define V_EMIL4(x) ((x) << S_EMIL4) +#define G_EMIL4(x) (((x) >> S_EMIL4) & M_EMIL4) + +#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_4 0x3bf0 + +#define S_VBST 1 +#define M_VBST 0x7U +#define V_VBST(x) ((x) << S_VBST) +#define G_VBST(x) (((x) >> S_VBST) & M_VBST) + +#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 0x3bf4 + +#define S_RESYNC 6 +#define V_RESYNC(x) ((x) << S_RESYNC) +#define F_RESYNC V_RESYNC(1U) + +#define S_RXCLKSEL 5 +#define V_RXCLKSEL(x) ((x) << S_RXCLKSEL) +#define F_RXCLKSEL V_RXCLKSEL(1U) + +#define S_FRCBAND 4 +#define V_FRCBAND(x) ((x) << S_FRCBAND) +#define F_FRCBAND V_FRCBAND(1U) + +#define S_PLLBYP 3 +#define V_PLLBYP(x) ((x) << S_PLLBYP) +#define F_PLLBYP V_PLLBYP(1U) + +#define S_PDWNP 2 +#define V_PDWNP(x) ((x) << S_PDWNP) +#define F_PDWNP V_PDWNP(1U) + +#define S_VCOSEL 1 +#define V_VCOSEL(x) ((x) << S_VCOSEL) +#define F_VCOSEL V_VCOSEL(1U) + +#define S_DIVSEL8 0 +#define V_DIVSEL8(x) ((x) << S_DIVSEL8) +#define F_DIVSEL8 V_DIVSEL8(1U) + +#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_2 0x3bf8 + +#define S_DIVSEL 0 +#define M_DIVSEL 0xffU +#define V_DIVSEL(x) ((x) << S_DIVSEL) +#define G_DIVSEL(x) (((x) >> S_DIVSEL) & M_DIVSEL) + +#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_1 0x3bfc + +#define S_CONFIG 0 +#define M_CONFIG 0xffU +#define V_CONFIG(x) ((x) << S_CONFIG) +#define G_CONFIG(x) (((x) >> S_CONFIG) & M_CONFIG) + +#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0 0x3c00 +#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1 0x3c04 +#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 0x3c08 +#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 0x3c0c +#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 0x3c10 +#define A_MAC_PORT_PLLB_CHARGE_PUMP_CONTROL 0x3c28 +#define A_MAC_PORT_PLLB_PCLK_CONTROL 0x3c3c +#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL 0x3c40 +#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 0x3c44 +#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2 0x3c48 +#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3 0x3c4c +#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4 0x3c50 +#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_4 0x3cf0 +#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_3 0x3cf4 +#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_2 0x3cf8 +#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_1 0x3cfc +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0 + +#define S_STEP 0 +#define M_STEP 0x7U +#define V_STEP(x) ((x) << S_STEP) +#define G_STEP(x) (((x) >> S_STEP) & M_STEP) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 + +#define S_C0INIT 0 +#define M_C0INIT 0x1fU +#define V_C0INIT(x) ((x) << S_C0INIT) +#define G_C0INIT(x) (((x) >> S_C0INIT) & M_C0INIT) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 + +#define S_C0MAX 8 +#define M_C0MAX 0x1fU +#define V_C0MAX(x) ((x) << S_C0MAX) +#define G_C0MAX(x) (((x) >> S_C0MAX) & M_C0MAX) + +#define S_C0MIN 0 +#define M_C0MIN 0x1fU +#define V_C0MIN(x) ((x) << S_C0MIN) +#define G_C0MIN(x) (((x) >> S_C0MIN) & M_C0MIN) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 + +#define S_C1INIT 0 +#define M_C1INIT 0x7fU +#define V_C1INIT(x) ((x) << S_C1INIT) +#define G_C1INIT(x) (((x) >> S_C1INIT) & M_C1INIT) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 + +#define S_C1MAX 8 +#define M_C1MAX 0x7fU +#define V_C1MAX(x) ((x) << S_C1MAX) +#define G_C1MAX(x) (((x) >> S_C1MAX) & M_C1MAX) + +#define S_C1MIN 0 +#define M_C1MIN 0x7fU +#define V_C1MIN(x) ((x) << S_C1MIN) +#define G_C1MIN(x) (((x) >> S_C1MIN) & M_C1MIN) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28 + +#define S_C2INIT 0 +#define M_C2INIT 0x3fU +#define V_C2INIT(x) ((x) << S_C2INIT) +#define G_C2INIT(x) (((x) >> S_C2INIT) & M_C2INIT) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 + +#define S_C2MAX 8 +#define M_C2MAX 0x3fU +#define V_C2MAX(x) ((x) << S_C2MAX) +#define G_C2MAX(x) (((x) >> S_C2MAX) & M_C2MAX) + +#define S_C2MIN 0 +#define M_C2MIN 0x3fU +#define V_C2MIN(x) ((x) << S_C2MIN) +#define G_C2MIN(x) (((x) >> S_C2MIN) & M_C2MIN) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 + +#define S_VMMAX 0 +#define M_VMMAX 0x7fU +#define V_VMMAX(x) ((x) << S_VMMAX) +#define G_VMMAX(x) (((x) >> S_VMMAX) & M_VMMAX) + +#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 + +#define S_V2MIN 0 +#define M_V2MIN 0x7fU +#define V_V2MIN(x) ((x) << S_V2MIN) +#define G_V2MIN(x) (((x) >> S_V2MIN) & M_V2MIN) + +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 +#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 +#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 +#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38 +#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40 + +/* registers for module MC_0 */ +#define MC_0_BASE_ADDR 0x40000 + +#define A_MC_UPCTL_SCFG 0x40000 + +#define S_BBFLAGS_TIMING 8 +#define M_BBFLAGS_TIMING 0xfU +#define V_BBFLAGS_TIMING(x) ((x) << S_BBFLAGS_TIMING) +#define G_BBFLAGS_TIMING(x) (((x) >> S_BBFLAGS_TIMING) & M_BBFLAGS_TIMING) + +#define S_NFIFO_NIF1_DIS 6 +#define V_NFIFO_NIF1_DIS(x) ((x) << S_NFIFO_NIF1_DIS) +#define F_NFIFO_NIF1_DIS V_NFIFO_NIF1_DIS(1U) + +#define A_MC_UPCTL_SCTL 0x40004 +#define A_MC_UPCTL_STAT 0x40008 + +#define S_LP_TRIG 4 +#define M_LP_TRIG 0x7U +#define V_LP_TRIG(x) ((x) << S_LP_TRIG) +#define G_LP_TRIG(x) (((x) >> S_LP_TRIG) & M_LP_TRIG) + +#define A_MC_UPCTL_INTRSTAT 0x4000c + +#define S_PARITY_INTR 1 +#define V_PARITY_INTR(x) ((x) << S_PARITY_INTR) +#define F_PARITY_INTR V_PARITY_INTR(1U) + +#define S_ECC_INTR 0 +#define V_ECC_INTR(x) ((x) << S_ECC_INTR) +#define F_ECC_INTR V_ECC_INTR(1U) + +#define A_MC_UPCTL_MCMD 0x40040 + +#define S_CMD_OPCODE0 0 +#define M_CMD_OPCODE0 0xfU +#define V_CMD_OPCODE0(x) ((x) << S_CMD_OPCODE0) +#define G_CMD_OPCODE0(x) (((x) >> S_CMD_OPCODE0) & M_CMD_OPCODE0) + +#define A_MC_UPCTL_POWCTL 0x40044 +#define A_MC_UPCTL_POWSTAT 0x40048 +#define A_MC_UPCTL_CMDTSTAT 0x4004c + +#define S_CMD_TSTAT 0 +#define V_CMD_TSTAT(x) ((x) << S_CMD_TSTAT) +#define F_CMD_TSTAT V_CMD_TSTAT(1U) + +#define A_MC_UPCTL_CMDTSTATEN 0x40050 + +#define S_CMD_TSTAT_EN 0 +#define V_CMD_TSTAT_EN(x) ((x) << S_CMD_TSTAT_EN) +#define F_CMD_TSTAT_EN V_CMD_TSTAT_EN(1U) + +#define A_MC_UPCTL_MRRCFG0 0x40060 + +#define S_MRR_BYTE_SEL 0 +#define M_MRR_BYTE_SEL 0xfU +#define V_MRR_BYTE_SEL(x) ((x) << S_MRR_BYTE_SEL) +#define G_MRR_BYTE_SEL(x) (((x) >> S_MRR_BYTE_SEL) & M_MRR_BYTE_SEL) + +#define A_MC_UPCTL_MRRSTAT0 0x40064 + +#define S_MRRSTAT_BEAT3 24 +#define M_MRRSTAT_BEAT3 0xffU +#define V_MRRSTAT_BEAT3(x) ((x) << S_MRRSTAT_BEAT3) +#define G_MRRSTAT_BEAT3(x) (((x) >> S_MRRSTAT_BEAT3) & M_MRRSTAT_BEAT3) + +#define S_MRRSTAT_BEAT2 16 +#define M_MRRSTAT_BEAT2 0xffU +#define V_MRRSTAT_BEAT2(x) ((x) << S_MRRSTAT_BEAT2) +#define G_MRRSTAT_BEAT2(x) (((x) >> S_MRRSTAT_BEAT2) & M_MRRSTAT_BEAT2) + +#define S_MRRSTAT_BEAT1 8 +#define M_MRRSTAT_BEAT1 0xffU +#define V_MRRSTAT_BEAT1(x) ((x) << S_MRRSTAT_BEAT1) +#define G_MRRSTAT_BEAT1(x) (((x) >> S_MRRSTAT_BEAT1) & M_MRRSTAT_BEAT1) + +#define S_MRRSTAT_BEAT0 0 +#define M_MRRSTAT_BEAT0 0xffU +#define V_MRRSTAT_BEAT0(x) ((x) << S_MRRSTAT_BEAT0) +#define G_MRRSTAT_BEAT0(x) (((x) >> S_MRRSTAT_BEAT0) & M_MRRSTAT_BEAT0) + +#define A_MC_UPCTL_MRRSTAT1 0x40068 + +#define S_MRRSTAT_BEAT7 24 +#define M_MRRSTAT_BEAT7 0xffU +#define V_MRRSTAT_BEAT7(x) ((x) << S_MRRSTAT_BEAT7) +#define G_MRRSTAT_BEAT7(x) (((x) >> S_MRRSTAT_BEAT7) & M_MRRSTAT_BEAT7) + +#define S_MRRSTAT_BEAT6 16 +#define M_MRRSTAT_BEAT6 0xffU +#define V_MRRSTAT_BEAT6(x) ((x) << S_MRRSTAT_BEAT6) +#define G_MRRSTAT_BEAT6(x) (((x) >> S_MRRSTAT_BEAT6) & M_MRRSTAT_BEAT6) + +#define S_MRRSTAT_BEAT5 8 +#define M_MRRSTAT_BEAT5 0xffU +#define V_MRRSTAT_BEAT5(x) ((x) << S_MRRSTAT_BEAT5) +#define G_MRRSTAT_BEAT5(x) (((x) >> S_MRRSTAT_BEAT5) & M_MRRSTAT_BEAT5) + +#define S_MRRSTAT_BEAT4 0 +#define M_MRRSTAT_BEAT4 0xffU +#define V_MRRSTAT_BEAT4(x) ((x) << S_MRRSTAT_BEAT4) +#define G_MRRSTAT_BEAT4(x) (((x) >> S_MRRSTAT_BEAT4) & M_MRRSTAT_BEAT4) + +#define A_MC_UPCTL_MCFG1 0x4007c + +#define S_HW_EXIT_IDLE_EN 31 +#define V_HW_EXIT_IDLE_EN(x) ((x) << S_HW_EXIT_IDLE_EN) +#define F_HW_EXIT_IDLE_EN V_HW_EXIT_IDLE_EN(1U) + +#define S_HW_IDLE 16 +#define M_HW_IDLE 0xffU +#define V_HW_IDLE(x) ((x) << S_HW_IDLE) +#define G_HW_IDLE(x) (((x) >> S_HW_IDLE) & M_HW_IDLE) + +#define S_SR_IDLE 0 +#define M_SR_IDLE 0xffU +#define V_SR_IDLE(x) ((x) << S_SR_IDLE) +#define G_SR_IDLE(x) (((x) >> S_SR_IDLE) & M_SR_IDLE) + +#define A_MC_UPCTL_MCFG 0x40080 + +#define S_MDDR_LPDDR2_CLK_STOP_IDLE 24 +#define M_MDDR_LPDDR2_CLK_STOP_IDLE 0xffU +#define V_MDDR_LPDDR2_CLK_STOP_IDLE(x) ((x) << S_MDDR_LPDDR2_CLK_STOP_IDLE) +#define G_MDDR_LPDDR2_CLK_STOP_IDLE(x) \ + (((x) >> S_MDDR_LPDDR2_CLK_STOP_IDLE) & M_MDDR_LPDDR2_CLK_STOP_IDLE) + +#define S_MDDR_LPDDR2_EN 22 +#define M_MDDR_LPDDR2_EN 0x3U +#define V_MDDR_LPDDR2_EN(x) ((x) << S_MDDR_LPDDR2_EN) +#define G_MDDR_LPDDR2_EN(x) (((x) >> S_MDDR_LPDDR2_EN) & M_MDDR_LPDDR2_EN) + +#define S_MDDR_LPDDR2_BL 20 +#define M_MDDR_LPDDR2_BL 0x3U +#define V_MDDR_LPDDR2_BL(x) ((x) << S_MDDR_LPDDR2_BL) +#define G_MDDR_LPDDR2_BL(x) (((x) >> S_MDDR_LPDDR2_BL) & M_MDDR_LPDDR2_BL) + +#define S_LPDDR2_S4 6 +#define V_LPDDR2_S4(x) ((x) << S_LPDDR2_S4) +#define F_LPDDR2_S4 V_LPDDR2_S4(1U) + +#define S_STAGGER_CS 4 +#define V_STAGGER_CS(x) ((x) << S_STAGGER_CS) +#define F_STAGGER_CS V_STAGGER_CS(1U) + +#define S_CKE_OR_EN 1 +#define V_CKE_OR_EN(x) ((x) << S_CKE_OR_EN) +#define F_CKE_OR_EN V_CKE_OR_EN(1U) + +#define A_MC_UPCTL_PPCFG 0x40084 +#define A_MC_UPCTL_MSTAT 0x40088 + +#define S_SELF_REFRESH 2 +#define V_SELF_REFRESH(x) ((x) << S_SELF_REFRESH) +#define F_SELF_REFRESH V_SELF_REFRESH(1U) + +#define S_CLOCK_STOP 1 +#define V_CLOCK_STOP(x) ((x) << S_CLOCK_STOP) +#define F_CLOCK_STOP V_CLOCK_STOP(1U) + +#define A_MC_UPCTL_LPDDR2ZQCFG 0x4008c + +#define S_ZQCL_OP 24 +#define M_ZQCL_OP 0xffU +#define V_ZQCL_OP(x) ((x) << S_ZQCL_OP) +#define G_ZQCL_OP(x) (((x) >> S_ZQCL_OP) & M_ZQCL_OP) + +#define S_ZQCL_MA 16 +#define M_ZQCL_MA 0xffU +#define V_ZQCL_MA(x) ((x) << S_ZQCL_MA) +#define G_ZQCL_MA(x) (((x) >> S_ZQCL_MA) & M_ZQCL_MA) + +#define S_ZQCS_OP 8 +#define M_ZQCS_OP 0xffU +#define V_ZQCS_OP(x) ((x) << S_ZQCS_OP) +#define G_ZQCS_OP(x) (((x) >> S_ZQCS_OP) & M_ZQCS_OP) + +#define S_ZQCS_MA 0 +#define M_ZQCS_MA 0xffU +#define V_ZQCS_MA(x) ((x) << S_ZQCS_MA) +#define G_ZQCS_MA(x) (((x) >> S_ZQCS_MA) & M_ZQCS_MA) + +#define A_MC_UPCTL_DTUPDES 0x40094 + +#define S_DTU_ERR_B7 7 +#define V_DTU_ERR_B7(x) ((x) << S_DTU_ERR_B7) +#define F_DTU_ERR_B7 V_DTU_ERR_B7(1U) + +#define A_MC_UPCTL_DTUNA 0x40098 +#define A_MC_UPCTL_DTUNE 0x4009c +#define A_MC_UPCTL_DTUPRD0 0x400a0 +#define A_MC_UPCTL_DTUPRD1 0x400a4 +#define A_MC_UPCTL_DTUPRD2 0x400a8 +#define A_MC_UPCTL_DTUPRD3 0x400ac +#define A_MC_UPCTL_DTUAWDT 0x400b0 +#define A_MC_UPCTL_TOGCNT1U 0x400c0 +#define A_MC_UPCTL_TINIT 0x400c4 +#define A_MC_UPCTL_TRSTH 0x400c8 +#define A_MC_UPCTL_TOGCNT100N 0x400cc +#define A_MC_UPCTL_TREFI 0x400d0 +#define A_MC_UPCTL_TMRD 0x400d4 +#define A_MC_UPCTL_TRFC 0x400d8 + +#define S_T_RFC0 0 +#define M_T_RFC0 0x1ffU +#define V_T_RFC0(x) ((x) << S_T_RFC0) +#define G_T_RFC0(x) (((x) >> S_T_RFC0) & M_T_RFC0) + +#define A_MC_UPCTL_TRP 0x400dc + +#define S_PREA_EXTRA 16 +#define M_PREA_EXTRA 0x3U +#define V_PREA_EXTRA(x) ((x) << S_PREA_EXTRA) +#define G_PREA_EXTRA(x) (((x) >> S_PREA_EXTRA) & M_PREA_EXTRA) + +#define A_MC_UPCTL_TRTW 0x400e0 + +#define S_T_RTW0 0 +#define M_T_RTW0 0xfU +#define V_T_RTW0(x) ((x) << S_T_RTW0) +#define G_T_RTW0(x) (((x) >> S_T_RTW0) & M_T_RTW0) + +#define A_MC_UPCTL_TAL 0x400e4 +#define A_MC_UPCTL_TCL 0x400e8 +#define A_MC_UPCTL_TCWL 0x400ec +#define A_MC_UPCTL_TRAS 0x400f0 +#define A_MC_UPCTL_TRC 0x400f4 +#define A_MC_UPCTL_TRCD 0x400f8 +#define A_MC_UPCTL_TRRD 0x400fc +#define A_MC_UPCTL_TRTP 0x40100 + +#define S_T_RTP0 0 +#define M_T_RTP0 0xfU +#define V_T_RTP0(x) ((x) << S_T_RTP0) +#define G_T_RTP0(x) (((x) >> S_T_RTP0) & M_T_RTP0) + +#define A_MC_UPCTL_TWR 0x40104 + +#define S_U_T_WR 0 +#define M_U_T_WR 0x1fU +#define V_U_T_WR(x) ((x) << S_U_T_WR) +#define G_U_T_WR(x) (((x) >> S_U_T_WR) & M_U_T_WR) + +#define A_MC_UPCTL_TWTR 0x40108 + +#define S_T_WTR0 0 +#define M_T_WTR0 0xfU +#define V_T_WTR0(x) ((x) << S_T_WTR0) +#define G_T_WTR0(x) (((x) >> S_T_WTR0) & M_T_WTR0) + +#define A_MC_UPCTL_TEXSR 0x4010c +#define A_MC_UPCTL_TXP 0x40110 +#define A_MC_UPCTL_TXPDLL 0x40114 +#define A_MC_UPCTL_TZQCS 0x40118 +#define A_MC_UPCTL_TZQCSI 0x4011c +#define A_MC_UPCTL_TDQS 0x40120 +#define A_MC_UPCTL_TCKSRE 0x40124 + +#define S_T_CKSRE0 0 +#define M_T_CKSRE0 0x1fU +#define V_T_CKSRE0(x) ((x) << S_T_CKSRE0) +#define G_T_CKSRE0(x) (((x) >> S_T_CKSRE0) & M_T_CKSRE0) + +#define A_MC_UPCTL_TCKSRX 0x40128 + +#define S_T_CKSRX0 0 +#define M_T_CKSRX0 0x1fU +#define V_T_CKSRX0(x) ((x) << S_T_CKSRX0) +#define G_T_CKSRX0(x) (((x) >> S_T_CKSRX0) & M_T_CKSRX0) + +#define A_MC_UPCTL_TCKE 0x4012c +#define A_MC_UPCTL_TMOD 0x40130 + +#define S_T_MOD0 0 +#define M_T_MOD0 0x1fU +#define V_T_MOD0(x) ((x) << S_T_MOD0) +#define G_T_MOD0(x) (((x) >> S_T_MOD0) & M_T_MOD0) + +#define A_MC_UPCTL_TRSTL 0x40134 + +#define S_T_RSTL 0 +#define M_T_RSTL 0x7fU +#define V_T_RSTL(x) ((x) << S_T_RSTL) +#define G_T_RSTL(x) (((x) >> S_T_RSTL) & M_T_RSTL) + +#define A_MC_UPCTL_TZQCL 0x40138 +#define A_MC_UPCTL_TMRR 0x4013c + +#define S_T_MRR 0 +#define M_T_MRR 0xffU +#define V_T_MRR(x) ((x) << S_T_MRR) +#define G_T_MRR(x) (((x) >> S_T_MRR) & M_T_MRR) + +#define A_MC_UPCTL_TCKESR 0x40140 + +#define S_T_CKESR 0 +#define M_T_CKESR 0xfU +#define V_T_CKESR(x) ((x) << S_T_CKESR) +#define G_T_CKESR(x) (((x) >> S_T_CKESR) & M_T_CKESR) + +#define A_MC_UPCTL_TDPD 0x40144 + +#define S_T_DPD 0 +#define M_T_DPD 0x3ffU +#define V_T_DPD(x) ((x) << S_T_DPD) +#define G_T_DPD(x) (((x) >> S_T_DPD) & M_T_DPD) + +#define A_MC_UPCTL_ECCCFG 0x40180 +#define A_MC_UPCTL_ECCTST 0x40184 + +#define S_ECC_TEST_MASK0 0 +#define M_ECC_TEST_MASK0 0x7fU +#define V_ECC_TEST_MASK0(x) ((x) << S_ECC_TEST_MASK0) +#define G_ECC_TEST_MASK0(x) (((x) >> S_ECC_TEST_MASK0) & M_ECC_TEST_MASK0) + +#define A_MC_UPCTL_ECCCLR 0x40188 +#define A_MC_UPCTL_ECCLOG 0x4018c +#define A_MC_UPCTL_DTUWACTL 0x40200 + +#define S_DTU_WR_ROW0 13 +#define M_DTU_WR_ROW0 0xffffU +#define V_DTU_WR_ROW0(x) ((x) << S_DTU_WR_ROW0) +#define G_DTU_WR_ROW0(x) (((x) >> S_DTU_WR_ROW0) & M_DTU_WR_ROW0) + +#define A_MC_UPCTL_DTURACTL 0x40204 + +#define S_DTU_RD_ROW0 13 +#define M_DTU_RD_ROW0 0xffffU +#define V_DTU_RD_ROW0(x) ((x) << S_DTU_RD_ROW0) +#define G_DTU_RD_ROW0(x) (((x) >> S_DTU_RD_ROW0) & M_DTU_RD_ROW0) + +#define A_MC_UPCTL_DTUCFG 0x40208 +#define A_MC_UPCTL_DTUECTL 0x4020c +#define A_MC_UPCTL_DTUWD0 0x40210 +#define A_MC_UPCTL_DTUWD1 0x40214 +#define A_MC_UPCTL_DTUWD2 0x40218 +#define A_MC_UPCTL_DTUWD3 0x4021c +#define A_MC_UPCTL_DTUWDM 0x40220 +#define A_MC_UPCTL_DTURD0 0x40224 +#define A_MC_UPCTL_DTURD1 0x40228 +#define A_MC_UPCTL_DTURD2 0x4022c +#define A_MC_UPCTL_DTURD3 0x40230 +#define A_MC_UPCTL_DTULFSRWD 0x40234 +#define A_MC_UPCTL_DTULFSRRD 0x40238 +#define A_MC_UPCTL_DTUEAF 0x4023c + +#define S_EA_ROW0 13 +#define M_EA_ROW0 0xffffU +#define V_EA_ROW0(x) ((x) << S_EA_ROW0) +#define G_EA_ROW0(x) (((x) >> S_EA_ROW0) & M_EA_ROW0) + +#define A_MC_UPCTL_DFITCTRLDELAY 0x40240 + +#define S_TCTRL_DELAY 0 +#define M_TCTRL_DELAY 0xfU +#define V_TCTRL_DELAY(x) ((x) << S_TCTRL_DELAY) +#define G_TCTRL_DELAY(x) (((x) >> S_TCTRL_DELAY) & M_TCTRL_DELAY) + +#define A_MC_UPCTL_DFIODTCFG 0x40244 + +#define S_RANK3_ODT_WRITE_NSEL 26 +#define V_RANK3_ODT_WRITE_NSEL(x) ((x) << S_RANK3_ODT_WRITE_NSEL) +#define F_RANK3_ODT_WRITE_NSEL V_RANK3_ODT_WRITE_NSEL(1U) + +#define A_MC_UPCTL_DFIODTCFG1 0x40248 + +#define S_ODT_LEN_B8_R 24 +#define M_ODT_LEN_B8_R 0x7U +#define V_ODT_LEN_B8_R(x) ((x) << S_ODT_LEN_B8_R) +#define G_ODT_LEN_B8_R(x) (((x) >> S_ODT_LEN_B8_R) & M_ODT_LEN_B8_R) + +#define S_ODT_LEN_BL8_W 16 +#define M_ODT_LEN_BL8_W 0x7U +#define V_ODT_LEN_BL8_W(x) ((x) << S_ODT_LEN_BL8_W) +#define G_ODT_LEN_BL8_W(x) (((x) >> S_ODT_LEN_BL8_W) & M_ODT_LEN_BL8_W) + +#define S_ODT_LAT_R 8 +#define M_ODT_LAT_R 0x1fU +#define V_ODT_LAT_R(x) ((x) << S_ODT_LAT_R) +#define G_ODT_LAT_R(x) (((x) >> S_ODT_LAT_R) & M_ODT_LAT_R) + +#define S_ODT_LAT_W 0 +#define M_ODT_LAT_W 0x1fU +#define V_ODT_LAT_W(x) ((x) << S_ODT_LAT_W) +#define G_ODT_LAT_W(x) (((x) >> S_ODT_LAT_W) & M_ODT_LAT_W) + +#define A_MC_UPCTL_DFIODTRANKMAP 0x4024c + +#define S_ODT_RANK_MAP3 12 +#define M_ODT_RANK_MAP3 0xfU +#define V_ODT_RANK_MAP3(x) ((x) << S_ODT_RANK_MAP3) +#define G_ODT_RANK_MAP3(x) (((x) >> S_ODT_RANK_MAP3) & M_ODT_RANK_MAP3) + +#define S_ODT_RANK_MAP2 8 +#define M_ODT_RANK_MAP2 0xfU +#define V_ODT_RANK_MAP2(x) ((x) << S_ODT_RANK_MAP2) +#define G_ODT_RANK_MAP2(x) (((x) >> S_ODT_RANK_MAP2) & M_ODT_RANK_MAP2) + +#define S_ODT_RANK_MAP1 4 +#define M_ODT_RANK_MAP1 0xfU +#define V_ODT_RANK_MAP1(x) ((x) << S_ODT_RANK_MAP1) +#define G_ODT_RANK_MAP1(x) (((x) >> S_ODT_RANK_MAP1) & M_ODT_RANK_MAP1) + +#define S_ODT_RANK_MAP0 0 +#define M_ODT_RANK_MAP0 0xfU +#define V_ODT_RANK_MAP0(x) ((x) << S_ODT_RANK_MAP0) +#define G_ODT_RANK_MAP0(x) (((x) >> S_ODT_RANK_MAP0) & M_ODT_RANK_MAP0) + +#define A_MC_UPCTL_DFITPHYWRDATA 0x40250 + +#define S_TPHY_WRDATA 0 +#define M_TPHY_WRDATA 0x1fU +#define V_TPHY_WRDATA(x) ((x) << S_TPHY_WRDATA) +#define G_TPHY_WRDATA(x) (((x) >> S_TPHY_WRDATA) & M_TPHY_WRDATA) + +#define A_MC_UPCTL_DFITPHYWRLAT 0x40254 + +#define S_TPHY_WRLAT 0 +#define M_TPHY_WRLAT 0x1fU +#define V_TPHY_WRLAT(x) ((x) << S_TPHY_WRLAT) +#define G_TPHY_WRLAT(x) (((x) >> S_TPHY_WRLAT) & M_TPHY_WRLAT) + +#define A_MC_UPCTL_DFITRDDATAEN 0x40260 + +#define S_TRDDATA_EN 0 +#define M_TRDDATA_EN 0x1fU +#define V_TRDDATA_EN(x) ((x) << S_TRDDATA_EN) +#define G_TRDDATA_EN(x) (((x) >> S_TRDDATA_EN) & M_TRDDATA_EN) + +#define A_MC_UPCTL_DFITPHYRDLAT 0x40264 + +#define S_TPHY_RDLAT 0 +#define M_TPHY_RDLAT 0x3fU +#define V_TPHY_RDLAT(x) ((x) << S_TPHY_RDLAT) +#define G_TPHY_RDLAT(x) (((x) >> S_TPHY_RDLAT) & M_TPHY_RDLAT) + +#define A_MC_UPCTL_DFITPHYUPDTYPE0 0x40270 + +#define S_TPHYUPD_TYPE0 0 +#define M_TPHYUPD_TYPE0 0xfffU +#define V_TPHYUPD_TYPE0(x) ((x) << S_TPHYUPD_TYPE0) +#define G_TPHYUPD_TYPE0(x) (((x) >> S_TPHYUPD_TYPE0) & M_TPHYUPD_TYPE0) + +#define A_MC_UPCTL_DFITPHYUPDTYPE1 0x40274 + +#define S_TPHYUPD_TYPE1 0 +#define M_TPHYUPD_TYPE1 0xfffU +#define V_TPHYUPD_TYPE1(x) ((x) << S_TPHYUPD_TYPE1) +#define G_TPHYUPD_TYPE1(x) (((x) >> S_TPHYUPD_TYPE1) & M_TPHYUPD_TYPE1) + +#define A_MC_UPCTL_DFITPHYUPDTYPE2 0x40278 + +#define S_TPHYUPD_TYPE2 0 +#define M_TPHYUPD_TYPE2 0xfffU +#define V_TPHYUPD_TYPE2(x) ((x) << S_TPHYUPD_TYPE2) +#define G_TPHYUPD_TYPE2(x) (((x) >> S_TPHYUPD_TYPE2) & M_TPHYUPD_TYPE2) + +#define A_MC_UPCTL_DFITPHYUPDTYPE3 0x4027c + +#define S_TPHYUPD_TYPE3 0 +#define M_TPHYUPD_TYPE3 0xfffU +#define V_TPHYUPD_TYPE3(x) ((x) << S_TPHYUPD_TYPE3) +#define G_TPHYUPD_TYPE3(x) (((x) >> S_TPHYUPD_TYPE3) & M_TPHYUPD_TYPE3) + +#define A_MC_UPCTL_DFITCTRLUPDMIN 0x40280 + +#define S_TCTRLUPD_MIN 0 +#define M_TCTRLUPD_MIN 0xffffU +#define V_TCTRLUPD_MIN(x) ((x) << S_TCTRLUPD_MIN) +#define G_TCTRLUPD_MIN(x) (((x) >> S_TCTRLUPD_MIN) & M_TCTRLUPD_MIN) + +#define A_MC_UPCTL_DFITCTRLUPDMAX 0x40284 + +#define S_TCTRLUPD_MAX 0 +#define M_TCTRLUPD_MAX 0xffffU +#define V_TCTRLUPD_MAX(x) ((x) << S_TCTRLUPD_MAX) +#define G_TCTRLUPD_MAX(x) (((x) >> S_TCTRLUPD_MAX) & M_TCTRLUPD_MAX) + +#define A_MC_UPCTL_DFITCTRLUPDDLY 0x40288 + +#define S_TCTRLUPD_DLY 0 +#define M_TCTRLUPD_DLY 0xfU +#define V_TCTRLUPD_DLY(x) ((x) << S_TCTRLUPD_DLY) +#define G_TCTRLUPD_DLY(x) (((x) >> S_TCTRLUPD_DLY) & M_TCTRLUPD_DLY) + +#define A_MC_UPCTL_DFIUPDCFG 0x40290 + +#define S_DFI_PHYUPD_EN 1 +#define V_DFI_PHYUPD_EN(x) ((x) << S_DFI_PHYUPD_EN) +#define F_DFI_PHYUPD_EN V_DFI_PHYUPD_EN(1U) + +#define S_DFI_CTRLUPD_EN 0 +#define V_DFI_CTRLUPD_EN(x) ((x) << S_DFI_CTRLUPD_EN) +#define F_DFI_CTRLUPD_EN V_DFI_CTRLUPD_EN(1U) + +#define A_MC_UPCTL_DFITREFMSKI 0x40294 + +#define S_TREFMSKI 0 +#define M_TREFMSKI 0xffU +#define V_TREFMSKI(x) ((x) << S_TREFMSKI) +#define G_TREFMSKI(x) (((x) >> S_TREFMSKI) & M_TREFMSKI) + +#define A_MC_UPCTL_DFITCTRLUPDI 0x40298 +#define A_MC_UPCTL_DFITRCFG0 0x402ac + +#define S_DFI_WRLVL_RANK_SEL 16 +#define M_DFI_WRLVL_RANK_SEL 0xfU +#define V_DFI_WRLVL_RANK_SEL(x) ((x) << S_DFI_WRLVL_RANK_SEL) +#define G_DFI_WRLVL_RANK_SEL(x) \ + (((x) >> S_DFI_WRLVL_RANK_SEL) & M_DFI_WRLVL_RANK_SEL) + +#define S_DFI_RDLVL_EDGE 4 +#define M_DFI_RDLVL_EDGE 0x1ffU +#define V_DFI_RDLVL_EDGE(x) ((x) << S_DFI_RDLVL_EDGE) +#define G_DFI_RDLVL_EDGE(x) (((x) >> S_DFI_RDLVL_EDGE) & M_DFI_RDLVL_EDGE) + +#define S_DFI_RDLVL_RANK_SEL 0 +#define M_DFI_RDLVL_RANK_SEL 0xfU +#define V_DFI_RDLVL_RANK_SEL(x) ((x) << S_DFI_RDLVL_RANK_SEL) +#define G_DFI_RDLVL_RANK_SEL(x) \ + (((x) >> S_DFI_RDLVL_RANK_SEL) & M_DFI_RDLVL_RANK_SEL) + +#define A_MC_UPCTL_DFITRSTAT0 0x402b0 + +#define S_DFI_WRLVL_MODE 16 +#define M_DFI_WRLVL_MODE 0x3U +#define V_DFI_WRLVL_MODE(x) ((x) << S_DFI_WRLVL_MODE) +#define G_DFI_WRLVL_MODE(x) (((x) >> S_DFI_WRLVL_MODE) & M_DFI_WRLVL_MODE) + +#define S_DFI_RDLVL_GATE_MODE 8 +#define M_DFI_RDLVL_GATE_MODE 0x3U +#define V_DFI_RDLVL_GATE_MODE(x) ((x) << S_DFI_RDLVL_GATE_MODE) +#define G_DFI_RDLVL_GATE_MODE(x) \ + (((x) >> S_DFI_RDLVL_GATE_MODE) & M_DFI_RDLVL_GATE_MODE) + +#define S_DFI_RDLVL_MODE 0 +#define M_DFI_RDLVL_MODE 0x3U +#define V_DFI_RDLVL_MODE(x) ((x) << S_DFI_RDLVL_MODE) +#define G_DFI_RDLVL_MODE(x) (((x) >> S_DFI_RDLVL_MODE) & M_DFI_RDLVL_MODE) + +#define A_MC_UPCTL_DFITRWRLVLEN 0x402b4 + +#define S_DFI_WRLVL_EN 0 +#define M_DFI_WRLVL_EN 0x1ffU +#define V_DFI_WRLVL_EN(x) ((x) << S_DFI_WRLVL_EN) +#define G_DFI_WRLVL_EN(x) (((x) >> S_DFI_WRLVL_EN) & M_DFI_WRLVL_EN) + +#define A_MC_UPCTL_DFITRRDLVLEN 0x402b8 + +#define S_DFI_RDLVL_EN 0 +#define M_DFI_RDLVL_EN 0x1ffU +#define V_DFI_RDLVL_EN(x) ((x) << S_DFI_RDLVL_EN) +#define G_DFI_RDLVL_EN(x) (((x) >> S_DFI_RDLVL_EN) & M_DFI_RDLVL_EN) + +#define A_MC_UPCTL_DFITRRDLVLGATEEN 0x402bc + +#define S_DFI_RDLVL_GATE_EN 0 +#define M_DFI_RDLVL_GATE_EN 0x1ffU +#define V_DFI_RDLVL_GATE_EN(x) ((x) << S_DFI_RDLVL_GATE_EN) +#define G_DFI_RDLVL_GATE_EN(x) \ + (((x) >> S_DFI_RDLVL_GATE_EN) & M_DFI_RDLVL_GATE_EN) + +#define A_MC_UPCTL_DFISTSTAT0 0x402c0 + +#define S_DFI_DATA_BYTE_DISABLE 16 +#define M_DFI_DATA_BYTE_DISABLE 0x1ffU +#define V_DFI_DATA_BYTE_DISABLE(x) ((x) << S_DFI_DATA_BYTE_DISABLE) +#define G_DFI_DATA_BYTE_DISABLE(x) \ + (((x) >> S_DFI_DATA_BYTE_DISABLE) & M_DFI_DATA_BYTE_DISABLE) + +#define S_DFI_FREQ_RATIO 4 +#define M_DFI_FREQ_RATIO 0x3U +#define V_DFI_FREQ_RATIO(x) ((x) << S_DFI_FREQ_RATIO) +#define G_DFI_FREQ_RATIO(x) (((x) >> S_DFI_FREQ_RATIO) & M_DFI_FREQ_RATIO) + +#define S_DFI_INIT_START0 1 +#define V_DFI_INIT_START0(x) ((x) << S_DFI_INIT_START0) +#define F_DFI_INIT_START0 V_DFI_INIT_START0(1U) + +#define S_DFI_INIT_COMPLETE 0 +#define V_DFI_INIT_COMPLETE(x) ((x) << S_DFI_INIT_COMPLETE) +#define F_DFI_INIT_COMPLETE V_DFI_INIT_COMPLETE(1U) + +#define A_MC_UPCTL_DFISTCFG0 0x402c4 + +#define S_DFI_DATA_BYTE_DISABLE_EN 2 +#define V_DFI_DATA_BYTE_DISABLE_EN(x) ((x) << S_DFI_DATA_BYTE_DISABLE_EN) +#define F_DFI_DATA_BYTE_DISABLE_EN V_DFI_DATA_BYTE_DISABLE_EN(1U) + +#define S_DFI_FREQ_RATIO_EN 1 +#define V_DFI_FREQ_RATIO_EN(x) ((x) << S_DFI_FREQ_RATIO_EN) +#define F_DFI_FREQ_RATIO_EN V_DFI_FREQ_RATIO_EN(1U) + +#define S_DFI_INIT_START 0 +#define V_DFI_INIT_START(x) ((x) << S_DFI_INIT_START) +#define F_DFI_INIT_START V_DFI_INIT_START(1U) + +#define A_MC_UPCTL_DFISTCFG1 0x402c8 + +#define S_DFI_DRAM_CLK_DISABLE_EN_DPD 1 +#define V_DFI_DRAM_CLK_DISABLE_EN_DPD(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN_DPD) +#define F_DFI_DRAM_CLK_DISABLE_EN_DPD V_DFI_DRAM_CLK_DISABLE_EN_DPD(1U) + +#define S_DFI_DRAM_CLK_DISABLE_EN 0 +#define V_DFI_DRAM_CLK_DISABLE_EN(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN) +#define F_DFI_DRAM_CLK_DISABLE_EN V_DFI_DRAM_CLK_DISABLE_EN(1U) + +#define A_MC_UPCTL_DFITDRAMCLKEN 0x402d0 + +#define S_TDRAM_CLK_ENABLE 0 +#define M_TDRAM_CLK_ENABLE 0xfU +#define V_TDRAM_CLK_ENABLE(x) ((x) << S_TDRAM_CLK_ENABLE) +#define G_TDRAM_CLK_ENABLE(x) (((x) >> S_TDRAM_CLK_ENABLE) & M_TDRAM_CLK_ENABLE) + +#define A_MC_UPCTL_DFITDRAMCLKDIS 0x402d4 + +#define S_TDRAM_CLK_DISABLE 0 +#define M_TDRAM_CLK_DISABLE 0xfU +#define V_TDRAM_CLK_DISABLE(x) ((x) << S_TDRAM_CLK_DISABLE) +#define G_TDRAM_CLK_DISABLE(x) \ + (((x) >> S_TDRAM_CLK_DISABLE) & M_TDRAM_CLK_DISABLE) + +#define A_MC_UPCTL_DFISTCFG2 0x402d8 + +#define S_PARITY_EN 1 +#define V_PARITY_EN(x) ((x) << S_PARITY_EN) +#define F_PARITY_EN V_PARITY_EN(1U) + +#define S_PARITY_INTR_EN 0 +#define V_PARITY_INTR_EN(x) ((x) << S_PARITY_INTR_EN) +#define F_PARITY_INTR_EN V_PARITY_INTR_EN(1U) + +#define A_MC_UPCTL_DFISTPARCLR 0x402dc + +#define S_PARITY_LOG_CLR 1 +#define V_PARITY_LOG_CLR(x) ((x) << S_PARITY_LOG_CLR) +#define F_PARITY_LOG_CLR V_PARITY_LOG_CLR(1U) + +#define S_PARITY_INTR_CLR 0 +#define V_PARITY_INTR_CLR(x) ((x) << S_PARITY_INTR_CLR) +#define F_PARITY_INTR_CLR V_PARITY_INTR_CLR(1U) + +#define A_MC_UPCTL_DFISTPARLOG 0x402e0 +#define A_MC_UPCTL_DFILPCFG0 0x402f0 + +#define S_DFI_LP_WAKEUP_DPD 28 +#define M_DFI_LP_WAKEUP_DPD 0xfU +#define V_DFI_LP_WAKEUP_DPD(x) ((x) << S_DFI_LP_WAKEUP_DPD) +#define G_DFI_LP_WAKEUP_DPD(x) \ + (((x) >> S_DFI_LP_WAKEUP_DPD) & M_DFI_LP_WAKEUP_DPD) + +#define S_DFI_LP_EN_DPD 24 +#define V_DFI_LP_EN_DPD(x) ((x) << S_DFI_LP_EN_DPD) +#define F_DFI_LP_EN_DPD V_DFI_LP_EN_DPD(1U) + +#define S_DFI_TLP_RESP 16 +#define M_DFI_TLP_RESP 0xfU +#define V_DFI_TLP_RESP(x) ((x) << S_DFI_TLP_RESP) +#define G_DFI_TLP_RESP(x) (((x) >> S_DFI_TLP_RESP) & M_DFI_TLP_RESP) + +#define S_DFI_LP_EN_SR 8 +#define V_DFI_LP_EN_SR(x) ((x) << S_DFI_LP_EN_SR) +#define F_DFI_LP_EN_SR V_DFI_LP_EN_SR(1U) + +#define S_DFI_LP_WAKEUP_PD 4 +#define M_DFI_LP_WAKEUP_PD 0xfU +#define V_DFI_LP_WAKEUP_PD(x) ((x) << S_DFI_LP_WAKEUP_PD) +#define G_DFI_LP_WAKEUP_PD(x) (((x) >> S_DFI_LP_WAKEUP_PD) & M_DFI_LP_WAKEUP_PD) + +#define S_DFI_LP_EN_PD 0 +#define V_DFI_LP_EN_PD(x) ((x) << S_DFI_LP_EN_PD) +#define F_DFI_LP_EN_PD V_DFI_LP_EN_PD(1U) + +#define A_MC_UPCTL_DFITRWRLVLRESP0 0x40300 +#define A_MC_UPCTL_DFITRWRLVLRESP1 0x40304 +#define A_MC_UPCTL_DFITRWRLVLRESP2 0x40308 + +#define S_DFI_WRLVL_RESP2 0 +#define M_DFI_WRLVL_RESP2 0xffU +#define V_DFI_WRLVL_RESP2(x) ((x) << S_DFI_WRLVL_RESP2) +#define G_DFI_WRLVL_RESP2(x) (((x) >> S_DFI_WRLVL_RESP2) & M_DFI_WRLVL_RESP2) + +#define A_MC_UPCTL_DFITRRDLVLRESP0 0x4030c +#define A_MC_UPCTL_DFITRRDLVLRESP1 0x40310 +#define A_MC_UPCTL_DFITRRDLVLRESP2 0x40314 + +#define S_DFI_RDLVL_RESP2 0 +#define M_DFI_RDLVL_RESP2 0xffU +#define V_DFI_RDLVL_RESP2(x) ((x) << S_DFI_RDLVL_RESP2) +#define G_DFI_RDLVL_RESP2(x) (((x) >> S_DFI_RDLVL_RESP2) & M_DFI_RDLVL_RESP2) + +#define A_MC_UPCTL_DFITRWRLVLDELAY0 0x40318 +#define A_MC_UPCTL_DFITRWRLVLDELAY1 0x4031c +#define A_MC_UPCTL_DFITRWRLVLDELAY2 0x40320 + +#define S_DFI_WRLVL_DELAY2 0 +#define M_DFI_WRLVL_DELAY2 0xffU +#define V_DFI_WRLVL_DELAY2(x) ((x) << S_DFI_WRLVL_DELAY2) +#define G_DFI_WRLVL_DELAY2(x) (((x) >> S_DFI_WRLVL_DELAY2) & M_DFI_WRLVL_DELAY2) + +#define A_MC_UPCTL_DFITRRDLVLDELAY0 0x40324 +#define A_MC_UPCTL_DFITRRDLVLDELAY1 0x40328 +#define A_MC_UPCTL_DFITRRDLVLDELAY2 0x4032c + +#define S_DFI_RDLVL_DELAY2 0 +#define M_DFI_RDLVL_DELAY2 0xffU +#define V_DFI_RDLVL_DELAY2(x) ((x) << S_DFI_RDLVL_DELAY2) +#define G_DFI_RDLVL_DELAY2(x) (((x) >> S_DFI_RDLVL_DELAY2) & M_DFI_RDLVL_DELAY2) + +#define A_MC_UPCTL_DFITRRDLVLGATEDELAY0 0x40330 +#define A_MC_UPCTL_DFITRRDLVLGATEDELAY1 0x40334 +#define A_MC_UPCTL_DFITRRDLVLGATEDELAY2 0x40338 + +#define S_DFI_RDLVL_GATE_DELAY2 0 +#define M_DFI_RDLVL_GATE_DELAY2 0xffU +#define V_DFI_RDLVL_GATE_DELAY2(x) ((x) << S_DFI_RDLVL_GATE_DELAY2) +#define G_DFI_RDLVL_GATE_DELAY2(x) \ + (((x) >> S_DFI_RDLVL_GATE_DELAY2) & M_DFI_RDLVL_GATE_DELAY2) + +#define A_MC_UPCTL_DFITRCMD 0x4033c + +#define S_DFITRCMD_START 31 +#define V_DFITRCMD_START(x) ((x) << S_DFITRCMD_START) +#define F_DFITRCMD_START V_DFITRCMD_START(1U) + +#define S_DFITRCMD_EN 4 +#define M_DFITRCMD_EN 0x1ffU +#define V_DFITRCMD_EN(x) ((x) << S_DFITRCMD_EN) +#define G_DFITRCMD_EN(x) (((x) >> S_DFITRCMD_EN) & M_DFITRCMD_EN) + +#define S_DFITRCMD_OPCODE 0 +#define M_DFITRCMD_OPCODE 0x3U +#define V_DFITRCMD_OPCODE(x) ((x) << S_DFITRCMD_OPCODE) +#define G_DFITRCMD_OPCODE(x) (((x) >> S_DFITRCMD_OPCODE) & M_DFITRCMD_OPCODE) + +#define A_MC_UPCTL_IPVR 0x403f8 +#define A_MC_UPCTL_IPTR 0x403fc +#define A_MC_P_DDRPHY_RST_CTRL 0x41300 + +#define S_PHY_DRAM_WL 17 +#define M_PHY_DRAM_WL 0x1fU +#define V_PHY_DRAM_WL(x) ((x) << S_PHY_DRAM_WL) +#define G_PHY_DRAM_WL(x) (((x) >> S_PHY_DRAM_WL) & M_PHY_DRAM_WL) + +#define S_PHY_CALIB_DONE 5 +#define V_PHY_CALIB_DONE(x) ((x) << S_PHY_CALIB_DONE) +#define F_PHY_CALIB_DONE V_PHY_CALIB_DONE(1U) + +#define S_CTL_CAL_REQ 4 +#define V_CTL_CAL_REQ(x) ((x) << S_CTL_CAL_REQ) +#define F_CTL_CAL_REQ V_CTL_CAL_REQ(1U) + +#define S_CTL_CKE 3 +#define V_CTL_CKE(x) ((x) << S_CTL_CKE) +#define F_CTL_CKE V_CTL_CKE(1U) + +#define S_CTL_RST_N 2 +#define V_CTL_RST_N(x) ((x) << S_CTL_RST_N) +#define F_CTL_RST_N V_CTL_RST_N(1U) + +#define A_MC_P_PERFORMANCE_CTRL 0x41304 +#define A_MC_P_ECC_CTRL 0x41308 +#define A_MC_P_PAR_ENABLE 0x4130c +#define A_MC_P_PAR_CAUSE 0x41310 +#define A_MC_P_INT_ENABLE 0x41314 +#define A_MC_P_INT_CAUSE 0x41318 +#define A_MC_P_ECC_STATUS 0x4131c +#define A_MC_P_PHY_CTRL 0x41320 +#define A_MC_P_STATIC_CFG_STATUS 0x41324 + +#define S_STATIC_AWEN 23 +#define V_STATIC_AWEN(x) ((x) << S_STATIC_AWEN) +#define F_STATIC_AWEN V_STATIC_AWEN(1U) + +#define S_STATIC_SWLAT 18 +#define M_STATIC_SWLAT 0x1fU +#define V_STATIC_SWLAT(x) ((x) << S_STATIC_SWLAT) +#define G_STATIC_SWLAT(x) (((x) >> S_STATIC_SWLAT) & M_STATIC_SWLAT) + +#define S_STATIC_WLAT 17 +#define V_STATIC_WLAT(x) ((x) << S_STATIC_WLAT) +#define F_STATIC_WLAT V_STATIC_WLAT(1U) + +#define S_STATIC_ALIGN 16 +#define V_STATIC_ALIGN(x) ((x) << S_STATIC_ALIGN) +#define F_STATIC_ALIGN V_STATIC_ALIGN(1U) + +#define S_STATIC_SLAT 11 +#define M_STATIC_SLAT 0x1fU +#define V_STATIC_SLAT(x) ((x) << S_STATIC_SLAT) +#define G_STATIC_SLAT(x) (((x) >> S_STATIC_SLAT) & M_STATIC_SLAT) + +#define S_STATIC_LAT 10 +#define V_STATIC_LAT(x) ((x) << S_STATIC_LAT) +#define F_STATIC_LAT V_STATIC_LAT(1U) + +#define A_MC_P_CORE_PCTL_STAT 0x41328 +#define A_MC_P_DEBUG_CNT 0x4132c +#define A_MC_CE_ERR_DATA_RDATA 0x41330 +#define A_MC_CE_COR_DATA_RDATA 0x41350 +#define A_MC_UE_ERR_DATA_RDATA 0x41370 +#define A_MC_UE_COR_DATA_RDATA 0x41390 +#define A_MC_CE_ADDR 0x413b0 +#define A_MC_UE_ADDR 0x413b4 +#define A_MC_P_DEEP_SLEEP 0x413b8 + +#define S_SLEEPSTATUS 1 +#define V_SLEEPSTATUS(x) ((x) << S_SLEEPSTATUS) +#define F_SLEEPSTATUS V_SLEEPSTATUS(1U) + +#define S_SLEEPREQ 0 +#define V_SLEEPREQ(x) ((x) << S_SLEEPREQ) +#define F_SLEEPREQ V_SLEEPREQ(1U) + +#define A_MC_P_FPGA_BONUS 0x413bc +#define A_MC_P_DEBUG_CFG 0x413c0 +#define A_MC_P_DEBUG_RPT 0x413c4 +#define A_MC_P_BIST_CMD 0x41400 + +#define S_BURST_LEN 16 +#define M_BURST_LEN 0x3U +#define V_BURST_LEN(x) ((x) << S_BURST_LEN) +#define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN) + +#define A_MC_P_BIST_CMD_ADDR 0x41404 +#define A_MC_P_BIST_CMD_LEN 0x41408 +#define A_MC_P_BIST_DATA_PATTERN 0x4140c +#define A_MC_P_BIST_USER_WDATA0 0x41414 +#define A_MC_P_BIST_USER_WDATA1 0x41418 +#define A_MC_P_BIST_USER_WDATA2 0x4141c + +#define S_USER_DATA_MASK 8 +#define M_USER_DATA_MASK 0x1ffU +#define V_USER_DATA_MASK(x) ((x) << S_USER_DATA_MASK) +#define G_USER_DATA_MASK(x) (((x) >> S_USER_DATA_MASK) & M_USER_DATA_MASK) + +#define A_MC_P_BIST_NUM_ERR 0x41480 +#define A_MC_P_BIST_ERR_FIRST_ADDR 0x41484 +#define A_MC_P_BIST_STATUS_RDATA 0x41488 +#define A_MC_P_BIST_CRC_SEED 0x414d0 +#define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE0 0x44000 + +#define S_DATA_BIT_ENABLE_0_15 0 +#define M_DATA_BIT_ENABLE_0_15 0xffffU +#define V_DATA_BIT_ENABLE_0_15(x) ((x) << S_DATA_BIT_ENABLE_0_15) +#define G_DATA_BIT_ENABLE_0_15(x) \ + (((x) >> S_DATA_BIT_ENABLE_0_15) & M_DATA_BIT_ENABLE_0_15) + +#define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE1 0x44004 + +#define S_DATA_BIT_ENABLE_16_23 8 +#define M_DATA_BIT_ENABLE_16_23 0xffU +#define V_DATA_BIT_ENABLE_16_23(x) ((x) << S_DATA_BIT_ENABLE_16_23) +#define G_DATA_BIT_ENABLE_16_23(x) \ + (((x) >> S_DATA_BIT_ENABLE_16_23) & M_DATA_BIT_ENABLE_16_23) + +#define S_DFT_FORCE_OUTPUTS 7 +#define V_DFT_FORCE_OUTPUTS(x) ((x) << S_DFT_FORCE_OUTPUTS) +#define F_DFT_FORCE_OUTPUTS V_DFT_FORCE_OUTPUTS(1U) + +#define S_DFT_PRBS7_GEN_EN 6 +#define V_DFT_PRBS7_GEN_EN(x) ((x) << S_DFT_PRBS7_GEN_EN) +#define F_DFT_PRBS7_GEN_EN V_DFT_PRBS7_GEN_EN(1U) + +#define S_WRAPSEL 5 +#define V_WRAPSEL(x) ((x) << S_WRAPSEL) +#define F_WRAPSEL V_WRAPSEL(1U) + +#define S_MRS_CMD_DATA_N0 3 +#define V_MRS_CMD_DATA_N0(x) ((x) << S_MRS_CMD_DATA_N0) +#define F_MRS_CMD_DATA_N0 V_MRS_CMD_DATA_N0(1U) + +#define S_MRS_CMD_DATA_N1 2 +#define V_MRS_CMD_DATA_N1(x) ((x) << S_MRS_CMD_DATA_N1) +#define F_MRS_CMD_DATA_N1 V_MRS_CMD_DATA_N1(1U) + +#define S_MRS_CMD_DATA_N2 1 +#define V_MRS_CMD_DATA_N2(x) ((x) << S_MRS_CMD_DATA_N2) +#define F_MRS_CMD_DATA_N2 V_MRS_CMD_DATA_N2(1U) + +#define S_MRS_CMD_DATA_N3 0 +#define V_MRS_CMD_DATA_N3(x) ((x) << S_MRS_CMD_DATA_N3) +#define F_MRS_CMD_DATA_N3 V_MRS_CMD_DATA_N3(1U) + +#define A_MC_DDRPHY_DP18_DATA_BIT_DIR0 0x44008 + +#define S_DATA_BIT_DIR_0_15 0 +#define M_DATA_BIT_DIR_0_15 0xffffU +#define V_DATA_BIT_DIR_0_15(x) ((x) << S_DATA_BIT_DIR_0_15) +#define G_DATA_BIT_DIR_0_15(x) \ + (((x) >> S_DATA_BIT_DIR_0_15) & M_DATA_BIT_DIR_0_15) + +#define A_MC_DDRPHY_DP18_DATA_BIT_DIR1 0x4400c + +#define S_DATA_BIT_DIR_16_23 8 +#define M_DATA_BIT_DIR_16_23 0xffU +#define V_DATA_BIT_DIR_16_23(x) ((x) << S_DATA_BIT_DIR_16_23) +#define G_DATA_BIT_DIR_16_23(x) \ + (((x) >> S_DATA_BIT_DIR_16_23) & M_DATA_BIT_DIR_16_23) + +#define S_WL_ADVANCE_DISABLE 7 +#define V_WL_ADVANCE_DISABLE(x) ((x) << S_WL_ADVANCE_DISABLE) +#define F_WL_ADVANCE_DISABLE V_WL_ADVANCE_DISABLE(1U) + +#define S_DISABLE_PING_PONG 6 +#define V_DISABLE_PING_PONG(x) ((x) << S_DISABLE_PING_PONG) +#define F_DISABLE_PING_PONG V_DISABLE_PING_PONG(1U) + +#define S_DELAY_PING_PONG_HALF 5 +#define V_DELAY_PING_PONG_HALF(x) ((x) << S_DELAY_PING_PONG_HALF) +#define F_DELAY_PING_PONG_HALF V_DELAY_PING_PONG_HALF(1U) + +#define S_ADVANCE_PING_PONG 4 +#define V_ADVANCE_PING_PONG(x) ((x) << S_ADVANCE_PING_PONG) +#define F_ADVANCE_PING_PONG V_ADVANCE_PING_PONG(1U) + +#define S_ATEST_MUX_CTL0 3 +#define V_ATEST_MUX_CTL0(x) ((x) << S_ATEST_MUX_CTL0) +#define F_ATEST_MUX_CTL0 V_ATEST_MUX_CTL0(1U) + +#define S_ATEST_MUX_CTL1 2 +#define V_ATEST_MUX_CTL1(x) ((x) << S_ATEST_MUX_CTL1) +#define F_ATEST_MUX_CTL1 V_ATEST_MUX_CTL1(1U) + +#define S_ATEST_MUX_CTL2 1 +#define V_ATEST_MUX_CTL2(x) ((x) << S_ATEST_MUX_CTL2) +#define F_ATEST_MUX_CTL2 V_ATEST_MUX_CTL2(1U) + +#define S_ATEST_MUX_CTL3 0 +#define V_ATEST_MUX_CTL3(x) ((x) << S_ATEST_MUX_CTL3) +#define F_ATEST_MUX_CTL3 V_ATEST_MUX_CTL3(1U) + +#define A_MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR 0x44010 + +#define S_QUAD0_CLK16_BIT0 15 +#define V_QUAD0_CLK16_BIT0(x) ((x) << S_QUAD0_CLK16_BIT0) +#define F_QUAD0_CLK16_BIT0 V_QUAD0_CLK16_BIT0(1U) + +#define S_QUAD1_CLK16_BIT1 14 +#define V_QUAD1_CLK16_BIT1(x) ((x) << S_QUAD1_CLK16_BIT1) +#define F_QUAD1_CLK16_BIT1 V_QUAD1_CLK16_BIT1(1U) + +#define S_QUAD2_CLK16_BIT2 13 +#define V_QUAD2_CLK16_BIT2(x) ((x) << S_QUAD2_CLK16_BIT2) +#define F_QUAD2_CLK16_BIT2 V_QUAD2_CLK16_BIT2(1U) + +#define S_QUAD3_CLK16_BIT3 12 +#define V_QUAD3_CLK16_BIT3(x) ((x) << S_QUAD3_CLK16_BIT3) +#define F_QUAD3_CLK16_BIT3 V_QUAD3_CLK16_BIT3(1U) + +#define S_QUAD0_CLK18_BIT4 11 +#define V_QUAD0_CLK18_BIT4(x) ((x) << S_QUAD0_CLK18_BIT4) +#define F_QUAD0_CLK18_BIT4 V_QUAD0_CLK18_BIT4(1U) + +#define S_QUAD1_CLK18_BIT5 10 +#define V_QUAD1_CLK18_BIT5(x) ((x) << S_QUAD1_CLK18_BIT5) +#define F_QUAD1_CLK18_BIT5 V_QUAD1_CLK18_BIT5(1U) + +#define S_QUAD2_CLK20_BIT6 9 +#define V_QUAD2_CLK20_BIT6(x) ((x) << S_QUAD2_CLK20_BIT6) +#define F_QUAD2_CLK20_BIT6 V_QUAD2_CLK20_BIT6(1U) + +#define S_QUAD3_CLK20_BIT7 8 +#define V_QUAD3_CLK20_BIT7(x) ((x) << S_QUAD3_CLK20_BIT7) +#define F_QUAD3_CLK20_BIT7 V_QUAD3_CLK20_BIT7(1U) + +#define S_QUAD2_CLK22_BIT8 7 +#define V_QUAD2_CLK22_BIT8(x) ((x) << S_QUAD2_CLK22_BIT8) +#define F_QUAD2_CLK22_BIT8 V_QUAD2_CLK22_BIT8(1U) + +#define S_QUAD3_CLK22_BIT9 6 +#define V_QUAD3_CLK22_BIT9(x) ((x) << S_QUAD3_CLK22_BIT9) +#define F_QUAD3_CLK22_BIT9 V_QUAD3_CLK22_BIT9(1U) + +#define S_CLK16_SINGLE_ENDED_BIT10 5 +#define V_CLK16_SINGLE_ENDED_BIT10(x) ((x) << S_CLK16_SINGLE_ENDED_BIT10) +#define F_CLK16_SINGLE_ENDED_BIT10 V_CLK16_SINGLE_ENDED_BIT10(1U) + +#define S_CLK18_SINGLE_ENDED_BIT11 4 +#define V_CLK18_SINGLE_ENDED_BIT11(x) ((x) << S_CLK18_SINGLE_ENDED_BIT11) +#define F_CLK18_SINGLE_ENDED_BIT11 V_CLK18_SINGLE_ENDED_BIT11(1U) + +#define S_CLK20_SINGLE_ENDED_BIT12 3 +#define V_CLK20_SINGLE_ENDED_BIT12(x) ((x) << S_CLK20_SINGLE_ENDED_BIT12) +#define F_CLK20_SINGLE_ENDED_BIT12 V_CLK20_SINGLE_ENDED_BIT12(1U) + +#define S_CLK22_SINGLE_ENDED_BIT13 2 +#define V_CLK22_SINGLE_ENDED_BIT13(x) ((x) << S_CLK22_SINGLE_ENDED_BIT13) +#define F_CLK22_SINGLE_ENDED_BIT13 V_CLK22_SINGLE_ENDED_BIT13(1U) + +#define A_MC_DDRPHY_DP18_WRCLK_EN_RP 0x44014 + +#define S_QUAD2_CLK18_BIT14 1 +#define V_QUAD2_CLK18_BIT14(x) ((x) << S_QUAD2_CLK18_BIT14) +#define F_QUAD2_CLK18_BIT14 V_QUAD2_CLK18_BIT14(1U) + +#define S_QUAD3_CLK18_BIT15 0 +#define V_QUAD3_CLK18_BIT15(x) ((x) << S_QUAD3_CLK18_BIT15) +#define F_QUAD3_CLK18_BIT15 V_QUAD3_CLK18_BIT15(1U) + +#define A_MC_DDRPHY_DP18_RX_PEAK_AMP 0x44018 + +#define S_PEAK_AMP_CTL_SIDE0 13 +#define M_PEAK_AMP_CTL_SIDE0 0x7U +#define V_PEAK_AMP_CTL_SIDE0(x) ((x) << S_PEAK_AMP_CTL_SIDE0) +#define G_PEAK_AMP_CTL_SIDE0(x) \ + (((x) >> S_PEAK_AMP_CTL_SIDE0) & M_PEAK_AMP_CTL_SIDE0) + +#define S_PEAK_AMP_CTL_SIDE1 9 +#define M_PEAK_AMP_CTL_SIDE1 0x7U +#define V_PEAK_AMP_CTL_SIDE1(x) ((x) << S_PEAK_AMP_CTL_SIDE1) +#define G_PEAK_AMP_CTL_SIDE1(x) \ + (((x) >> S_PEAK_AMP_CTL_SIDE1) & M_PEAK_AMP_CTL_SIDE1) + +#define S_SXMCVREF_0_3 4 +#define M_SXMCVREF_0_3 0xfU +#define V_SXMCVREF_0_3(x) ((x) << S_SXMCVREF_0_3) +#define G_SXMCVREF_0_3(x) (((x) >> S_SXMCVREF_0_3) & M_SXMCVREF_0_3) + +#define S_SXPODVREF 3 +#define V_SXPODVREF(x) ((x) << S_SXPODVREF) +#define F_SXPODVREF V_SXPODVREF(1U) + +#define S_DISABLE_TERMINATION 2 +#define V_DISABLE_TERMINATION(x) ((x) << S_DISABLE_TERMINATION) +#define F_DISABLE_TERMINATION V_DISABLE_TERMINATION(1U) + +#define S_READ_CENTERING_MODE 0 +#define M_READ_CENTERING_MODE 0x3U +#define V_READ_CENTERING_MODE(x) ((x) << S_READ_CENTERING_MODE) +#define G_READ_CENTERING_MODE(x) \ + (((x) >> S_READ_CENTERING_MODE) & M_READ_CENTERING_MODE) + +#define A_MC_DDRPHY_DP18_SYSCLK_PR 0x4401c + +#define S_SYSCLK_PHASE_ALIGN_RESET 6 +#define V_SYSCLK_PHASE_ALIGN_RESET(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESET) +#define F_SYSCLK_PHASE_ALIGN_RESET V_SYSCLK_PHASE_ALIGN_RESET(1U) + +#define A_MC_DDRPHY_DP18_DFT_DIG_EYE 0x44020 + +#define S_DIGITAL_EYE_EN 15 +#define V_DIGITAL_EYE_EN(x) ((x) << S_DIGITAL_EYE_EN) +#define F_DIGITAL_EYE_EN V_DIGITAL_EYE_EN(1U) + +#define S_BUMP 14 +#define V_BUMP(x) ((x) << S_BUMP) +#define F_BUMP V_BUMP(1U) + +#define S_TRIG_PERIOD 13 +#define V_TRIG_PERIOD(x) ((x) << S_TRIG_PERIOD) +#define F_TRIG_PERIOD V_TRIG_PERIOD(1U) + +#define S_CNTL_POL 12 +#define V_CNTL_POL(x) ((x) << S_CNTL_POL) +#define F_CNTL_POL V_CNTL_POL(1U) + +#define S_CNTL_SRC 8 +#define V_CNTL_SRC(x) ((x) << S_CNTL_SRC) +#define F_CNTL_SRC V_CNTL_SRC(1U) + +#define S_DIGITAL_EYE_VALUE 0 +#define M_DIGITAL_EYE_VALUE 0xffU +#define V_DIGITAL_EYE_VALUE(x) ((x) << S_DIGITAL_EYE_VALUE) +#define G_DIGITAL_EYE_VALUE(x) \ + (((x) >> S_DIGITAL_EYE_VALUE) & M_DIGITAL_EYE_VALUE) + +#define A_MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR 0x44024 + +#define S_DQSCLK_SELECT0 14 +#define M_DQSCLK_SELECT0 0x3U +#define V_DQSCLK_SELECT0(x) ((x) << S_DQSCLK_SELECT0) +#define G_DQSCLK_SELECT0(x) (((x) >> S_DQSCLK_SELECT0) & M_DQSCLK_SELECT0) + +#define S_RDCLK_SELECT0 12 +#define M_RDCLK_SELECT0 0x3U +#define V_RDCLK_SELECT0(x) ((x) << S_RDCLK_SELECT0) +#define G_RDCLK_SELECT0(x) (((x) >> S_RDCLK_SELECT0) & M_RDCLK_SELECT0) + +#define S_DQSCLK_SELECT1 10 +#define M_DQSCLK_SELECT1 0x3U +#define V_DQSCLK_SELECT1(x) ((x) << S_DQSCLK_SELECT1) +#define G_DQSCLK_SELECT1(x) (((x) >> S_DQSCLK_SELECT1) & M_DQSCLK_SELECT1) + +#define S_RDCLK_SELECT1 8 +#define M_RDCLK_SELECT1 0x3U +#define V_RDCLK_SELECT1(x) ((x) << S_RDCLK_SELECT1) +#define G_RDCLK_SELECT1(x) (((x) >> S_RDCLK_SELECT1) & M_RDCLK_SELECT1) + +#define S_DQSCLK_SELECT2 6 +#define M_DQSCLK_SELECT2 0x3U +#define V_DQSCLK_SELECT2(x) ((x) << S_DQSCLK_SELECT2) +#define G_DQSCLK_SELECT2(x) (((x) >> S_DQSCLK_SELECT2) & M_DQSCLK_SELECT2) + +#define S_RDCLK_SELECT2 4 +#define M_RDCLK_SELECT2 0x3U +#define V_RDCLK_SELECT2(x) ((x) << S_RDCLK_SELECT2) +#define G_RDCLK_SELECT2(x) (((x) >> S_RDCLK_SELECT2) & M_RDCLK_SELECT2) + +#define S_DQSCLK_SELECT3 2 +#define M_DQSCLK_SELECT3 0x3U +#define V_DQSCLK_SELECT3(x) ((x) << S_DQSCLK_SELECT3) +#define G_DQSCLK_SELECT3(x) (((x) >> S_DQSCLK_SELECT3) & M_DQSCLK_SELECT3) + +#define S_RDCLK_SELECT3 0 +#define M_RDCLK_SELECT3 0x3U +#define V_RDCLK_SELECT3(x) ((x) << S_RDCLK_SELECT3) +#define G_RDCLK_SELECT3(x) (((x) >> S_RDCLK_SELECT3) & M_RDCLK_SELECT3) + +#define A_MC_DDRPHY_DP18_DRIFT_LIMITS 0x44028 + +#define S_MIN_RD_EYE_SIZE 8 +#define M_MIN_RD_EYE_SIZE 0x3fU +#define V_MIN_RD_EYE_SIZE(x) ((x) << S_MIN_RD_EYE_SIZE) +#define G_MIN_RD_EYE_SIZE(x) (((x) >> S_MIN_RD_EYE_SIZE) & M_MIN_RD_EYE_SIZE) + +#define S_MAX_DQS_DRIFT 0 +#define M_MAX_DQS_DRIFT 0x3fU +#define V_MAX_DQS_DRIFT(x) ((x) << S_MAX_DQS_DRIFT) +#define G_MAX_DQS_DRIFT(x) (((x) >> S_MAX_DQS_DRIFT) & M_MAX_DQS_DRIFT) + +#define A_MC_DDRPHY_DP18_DEBUG_SEL 0x4402c + +#define S_HS_PROBE_A_SEL 11 +#define M_HS_PROBE_A_SEL 0x1fU +#define V_HS_PROBE_A_SEL(x) ((x) << S_HS_PROBE_A_SEL) +#define G_HS_PROBE_A_SEL(x) (((x) >> S_HS_PROBE_A_SEL) & M_HS_PROBE_A_SEL) + +#define S_HS_PROBE_B_SEL 6 +#define M_HS_PROBE_B_SEL 0x1fU +#define V_HS_PROBE_B_SEL(x) ((x) << S_HS_PROBE_B_SEL) +#define G_HS_PROBE_B_SEL(x) (((x) >> S_HS_PROBE_B_SEL) & M_HS_PROBE_B_SEL) + +#define S_RD_DEBUG_SEL 3 +#define M_RD_DEBUG_SEL 0x7U +#define V_RD_DEBUG_SEL(x) ((x) << S_RD_DEBUG_SEL) +#define G_RD_DEBUG_SEL(x) (((x) >> S_RD_DEBUG_SEL) & M_RD_DEBUG_SEL) + +#define S_WR_DEBUG_SEL 0 +#define M_WR_DEBUG_SEL 0x7U +#define V_WR_DEBUG_SEL(x) ((x) << S_WR_DEBUG_SEL) +#define G_WR_DEBUG_SEL(x) (((x) >> S_WR_DEBUG_SEL) & M_WR_DEBUG_SEL) + +#define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR 0x44030 + +#define S_OFFSET_BITS1_7 8 +#define M_OFFSET_BITS1_7 0x7fU +#define V_OFFSET_BITS1_7(x) ((x) << S_OFFSET_BITS1_7) +#define G_OFFSET_BITS1_7(x) (((x) >> S_OFFSET_BITS1_7) & M_OFFSET_BITS1_7) + +#define S_OFFSET_BITS9_15 0 +#define M_OFFSET_BITS9_15 0x7fU +#define V_OFFSET_BITS9_15(x) ((x) << S_OFFSET_BITS9_15) +#define G_OFFSET_BITS9_15(x) (((x) >> S_OFFSET_BITS9_15) & M_OFFSET_BITS9_15) + +#define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR 0x44034 +#define A_MC_DDRPHY_DP18_RD_LVL_STATUS0 0x44038 + +#define S_LEADING_EDGE_NOT_FOUND_0 0 +#define M_LEADING_EDGE_NOT_FOUND_0 0xffffU +#define V_LEADING_EDGE_NOT_FOUND_0(x) ((x) << S_LEADING_EDGE_NOT_FOUND_0) +#define G_LEADING_EDGE_NOT_FOUND_0(x) \ + (((x) >> S_LEADING_EDGE_NOT_FOUND_0) & M_LEADING_EDGE_NOT_FOUND_0) + +#define A_MC_DDRPHY_DP18_RD_LVL_STATUS1 0x4403c + +#define S_LEADING_EDGE_NOT_FOUND_1 8 +#define M_LEADING_EDGE_NOT_FOUND_1 0xffU +#define V_LEADING_EDGE_NOT_FOUND_1(x) ((x) << S_LEADING_EDGE_NOT_FOUND_1) +#define G_LEADING_EDGE_NOT_FOUND_1(x) \ + (((x) >> S_LEADING_EDGE_NOT_FOUND_1) & M_LEADING_EDGE_NOT_FOUND_1) + +#define A_MC_DDRPHY_DP18_RD_LVL_STATUS2 0x44040 + +#define S_TRAILING_EDGE_NOT_FOUND 0 +#define M_TRAILING_EDGE_NOT_FOUND 0xffffU +#define V_TRAILING_EDGE_NOT_FOUND(x) ((x) << S_TRAILING_EDGE_NOT_FOUND) +#define G_TRAILING_EDGE_NOT_FOUND(x) \ + (((x) >> S_TRAILING_EDGE_NOT_FOUND) & M_TRAILING_EDGE_NOT_FOUND) + +#define A_MC_DDRPHY_DP18_RD_LVL_STATUS3 0x44044 + +#define S_TRAILING_EDGE_NOT_FOUND_16_23 8 +#define M_TRAILING_EDGE_NOT_FOUND_16_23 0xffU +#define V_TRAILING_EDGE_NOT_FOUND_16_23(x) \ + ((x) << S_TRAILING_EDGE_NOT_FOUND_16_23) +#define G_TRAILING_EDGE_NOT_FOUND_16_23(x) \ + (((x) >> S_TRAILING_EDGE_NOT_FOUND_16_23) & \ + M_TRAILING_EDGE_NOT_FOUND_16_23) + +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG5 0x44048 + +#define S_DYN_POWER_CNTL_EN 15 +#define V_DYN_POWER_CNTL_EN(x) ((x) << S_DYN_POWER_CNTL_EN) +#define F_DYN_POWER_CNTL_EN V_DYN_POWER_CNTL_EN(1U) + +#define S_DYN_MCTERM_CNTL_EN 14 +#define V_DYN_MCTERM_CNTL_EN(x) ((x) << S_DYN_MCTERM_CNTL_EN) +#define F_DYN_MCTERM_CNTL_EN V_DYN_MCTERM_CNTL_EN(1U) + +#define S_DYN_RX_GATE_CNTL_EN 13 +#define V_DYN_RX_GATE_CNTL_EN(x) ((x) << S_DYN_RX_GATE_CNTL_EN) +#define F_DYN_RX_GATE_CNTL_EN V_DYN_RX_GATE_CNTL_EN(1U) + +#define S_CALGATE_ON 12 +#define V_CALGATE_ON(x) ((x) << S_CALGATE_ON) +#define F_CALGATE_ON V_CALGATE_ON(1U) + +#define S_PER_RDCLK_UPDATE_DIS 11 +#define V_PER_RDCLK_UPDATE_DIS(x) ((x) << S_PER_RDCLK_UPDATE_DIS) +#define F_PER_RDCLK_UPDATE_DIS V_PER_RDCLK_UPDATE_DIS(1U) + +#define A_MC_DDRPHY_DP18_DQS_GATE_DELAY_RP 0x4404c + +#define S_DQS_GATE_DELAY_N0 12 +#define M_DQS_GATE_DELAY_N0 0x7U +#define V_DQS_GATE_DELAY_N0(x) ((x) << S_DQS_GATE_DELAY_N0) +#define G_DQS_GATE_DELAY_N0(x) \ + (((x) >> S_DQS_GATE_DELAY_N0) & M_DQS_GATE_DELAY_N0) + +#define S_DQS_GATE_DELAY_N1 8 +#define M_DQS_GATE_DELAY_N1 0x7U +#define V_DQS_GATE_DELAY_N1(x) ((x) << S_DQS_GATE_DELAY_N1) +#define G_DQS_GATE_DELAY_N1(x) \ + (((x) >> S_DQS_GATE_DELAY_N1) & M_DQS_GATE_DELAY_N1) + +#define S_DQS_GATE_DELAY_N2 4 +#define M_DQS_GATE_DELAY_N2 0x7U +#define V_DQS_GATE_DELAY_N2(x) ((x) << S_DQS_GATE_DELAY_N2) +#define G_DQS_GATE_DELAY_N2(x) \ + (((x) >> S_DQS_GATE_DELAY_N2) & M_DQS_GATE_DELAY_N2) + +#define S_DQS_GATE_DELAY_N3 0 +#define M_DQS_GATE_DELAY_N3 0x7U +#define V_DQS_GATE_DELAY_N3(x) ((x) << S_DQS_GATE_DELAY_N3) +#define G_DQS_GATE_DELAY_N3(x) \ + (((x) >> S_DQS_GATE_DELAY_N3) & M_DQS_GATE_DELAY_N3) + +#define A_MC_DDRPHY_DP18_RD_STATUS0 0x44050 + +#define S_NO_EYE_DETECTED 15 +#define V_NO_EYE_DETECTED(x) ((x) << S_NO_EYE_DETECTED) +#define F_NO_EYE_DETECTED V_NO_EYE_DETECTED(1U) + +#define S_LEADING_EDGE_FOUND 14 +#define V_LEADING_EDGE_FOUND(x) ((x) << S_LEADING_EDGE_FOUND) +#define F_LEADING_EDGE_FOUND V_LEADING_EDGE_FOUND(1U) + +#define S_TRAILING_EDGE_FOUND 13 +#define V_TRAILING_EDGE_FOUND(x) ((x) << S_TRAILING_EDGE_FOUND) +#define F_TRAILING_EDGE_FOUND V_TRAILING_EDGE_FOUND(1U) + +#define S_INCOMPLETE_RD_CAL_N0 12 +#define V_INCOMPLETE_RD_CAL_N0(x) ((x) << S_INCOMPLETE_RD_CAL_N0) +#define F_INCOMPLETE_RD_CAL_N0 V_INCOMPLETE_RD_CAL_N0(1U) + +#define S_INCOMPLETE_RD_CAL_N1 11 +#define V_INCOMPLETE_RD_CAL_N1(x) ((x) << S_INCOMPLETE_RD_CAL_N1) +#define F_INCOMPLETE_RD_CAL_N1 V_INCOMPLETE_RD_CAL_N1(1U) + +#define S_INCOMPLETE_RD_CAL_N2 10 +#define V_INCOMPLETE_RD_CAL_N2(x) ((x) << S_INCOMPLETE_RD_CAL_N2) +#define F_INCOMPLETE_RD_CAL_N2 V_INCOMPLETE_RD_CAL_N2(1U) + +#define S_INCOMPLETE_RD_CAL_N3 9 +#define V_INCOMPLETE_RD_CAL_N3(x) ((x) << S_INCOMPLETE_RD_CAL_N3) +#define F_INCOMPLETE_RD_CAL_N3 V_INCOMPLETE_RD_CAL_N3(1U) + +#define S_COARSE_PATTERN_ERR_N0 8 +#define V_COARSE_PATTERN_ERR_N0(x) ((x) << S_COARSE_PATTERN_ERR_N0) +#define F_COARSE_PATTERN_ERR_N0 V_COARSE_PATTERN_ERR_N0(1U) + +#define S_COARSE_PATTERN_ERR_N1 7 +#define V_COARSE_PATTERN_ERR_N1(x) ((x) << S_COARSE_PATTERN_ERR_N1) +#define F_COARSE_PATTERN_ERR_N1 V_COARSE_PATTERN_ERR_N1(1U) + +#define S_COARSE_PATTERN_ERR_N2 6 +#define V_COARSE_PATTERN_ERR_N2(x) ((x) << S_COARSE_PATTERN_ERR_N2) +#define F_COARSE_PATTERN_ERR_N2 V_COARSE_PATTERN_ERR_N2(1U) + +#define S_COARSE_PATTERN_ERR_N3 5 +#define V_COARSE_PATTERN_ERR_N3(x) ((x) << S_COARSE_PATTERN_ERR_N3) +#define F_COARSE_PATTERN_ERR_N3 V_COARSE_PATTERN_ERR_N3(1U) + +#define S_EYE_CLIPPING 4 +#define V_EYE_CLIPPING(x) ((x) << S_EYE_CLIPPING) +#define F_EYE_CLIPPING V_EYE_CLIPPING(1U) + +#define S_NO_DQS 3 +#define V_NO_DQS(x) ((x) << S_NO_DQS) +#define F_NO_DQS V_NO_DQS(1U) + +#define S_NO_LOCK 2 +#define V_NO_LOCK(x) ((x) << S_NO_LOCK) +#define F_NO_LOCK V_NO_LOCK(1U) + +#define S_DRIFT_ERROR 1 +#define V_DRIFT_ERROR(x) ((x) << S_DRIFT_ERROR) +#define F_DRIFT_ERROR V_DRIFT_ERROR(1U) + +#define S_MIN_EYE 0 +#define V_MIN_EYE(x) ((x) << S_MIN_EYE) +#define F_MIN_EYE V_MIN_EYE(1U) + +#define A_MC_DDRPHY_DP18_RD_ERROR_MASK0 0x44054 + +#define S_NO_EYE_DETECTED_MASK 15 +#define V_NO_EYE_DETECTED_MASK(x) ((x) << S_NO_EYE_DETECTED_MASK) +#define F_NO_EYE_DETECTED_MASK V_NO_EYE_DETECTED_MASK(1U) + +#define S_LEADING_EDGE_FOUND_MASK 14 +#define V_LEADING_EDGE_FOUND_MASK(x) ((x) << S_LEADING_EDGE_FOUND_MASK) +#define F_LEADING_EDGE_FOUND_MASK V_LEADING_EDGE_FOUND_MASK(1U) + +#define S_TRAILING_EDGE_FOUND_MASK 13 +#define V_TRAILING_EDGE_FOUND_MASK(x) ((x) << S_TRAILING_EDGE_FOUND_MASK) +#define F_TRAILING_EDGE_FOUND_MASK V_TRAILING_EDGE_FOUND_MASK(1U) + +#define S_INCOMPLETE_RD_CAL_N0_MASK 12 +#define V_INCOMPLETE_RD_CAL_N0_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N0_MASK) +#define F_INCOMPLETE_RD_CAL_N0_MASK V_INCOMPLETE_RD_CAL_N0_MASK(1U) + +#define S_INCOMPLETE_RD_CAL_N1_MASK 11 +#define V_INCOMPLETE_RD_CAL_N1_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N1_MASK) +#define F_INCOMPLETE_RD_CAL_N1_MASK V_INCOMPLETE_RD_CAL_N1_MASK(1U) + +#define S_INCOMPLETE_RD_CAL_N2_MASK 10 +#define V_INCOMPLETE_RD_CAL_N2_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N2_MASK) +#define F_INCOMPLETE_RD_CAL_N2_MASK V_INCOMPLETE_RD_CAL_N2_MASK(1U) + +#define S_INCOMPLETE_RD_CAL_N3_MASK 9 +#define V_INCOMPLETE_RD_CAL_N3_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N3_MASK) +#define F_INCOMPLETE_RD_CAL_N3_MASK V_INCOMPLETE_RD_CAL_N3_MASK(1U) + +#define S_COARSE_PATTERN_ERR_N0_MASK 8 +#define V_COARSE_PATTERN_ERR_N0_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N0_MASK) +#define F_COARSE_PATTERN_ERR_N0_MASK V_COARSE_PATTERN_ERR_N0_MASK(1U) + +#define S_COARSE_PATTERN_ERR_N1_MASK 7 +#define V_COARSE_PATTERN_ERR_N1_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N1_MASK) +#define F_COARSE_PATTERN_ERR_N1_MASK V_COARSE_PATTERN_ERR_N1_MASK(1U) + +#define S_COARSE_PATTERN_ERR_N2_MASK 6 +#define V_COARSE_PATTERN_ERR_N2_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N2_MASK) +#define F_COARSE_PATTERN_ERR_N2_MASK V_COARSE_PATTERN_ERR_N2_MASK(1U) + +#define S_COARSE_PATTERN_ERR_N3_MASK 5 +#define V_COARSE_PATTERN_ERR_N3_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N3_MASK) +#define F_COARSE_PATTERN_ERR_N3_MASK V_COARSE_PATTERN_ERR_N3_MASK(1U) + +#define S_EYE_CLIPPING_MASK 4 +#define V_EYE_CLIPPING_MASK(x) ((x) << S_EYE_CLIPPING_MASK) +#define F_EYE_CLIPPING_MASK V_EYE_CLIPPING_MASK(1U) + +#define S_NO_DQS_MASK 3 +#define V_NO_DQS_MASK(x) ((x) << S_NO_DQS_MASK) +#define F_NO_DQS_MASK V_NO_DQS_MASK(1U) + +#define S_NO_LOCK_MASK 2 +#define V_NO_LOCK_MASK(x) ((x) << S_NO_LOCK_MASK) +#define F_NO_LOCK_MASK V_NO_LOCK_MASK(1U) + +#define S_DRIFT_ERROR_MASK 1 +#define V_DRIFT_ERROR_MASK(x) ((x) << S_DRIFT_ERROR_MASK) +#define F_DRIFT_ERROR_MASK V_DRIFT_ERROR_MASK(1U) + +#define S_MIN_EYE_MASK 0 +#define V_MIN_EYE_MASK(x) ((x) << S_MIN_EYE_MASK) +#define F_MIN_EYE_MASK V_MIN_EYE_MASK(1U) + +#define A_MC_DDRPHY_DP18_WR_LVL_STATUS0 0x4405c + +#define S_CLK_LEVEL 14 +#define M_CLK_LEVEL 0x3U +#define V_CLK_LEVEL(x) ((x) << S_CLK_LEVEL) +#define G_CLK_LEVEL(x) (((x) >> S_CLK_LEVEL) & M_CLK_LEVEL) + +#define S_FINE_STEPPING 13 +#define V_FINE_STEPPING(x) ((x) << S_FINE_STEPPING) +#define F_FINE_STEPPING V_FINE_STEPPING(1U) + +#define S_DONE 12 +#define V_DONE(x) ((x) << S_DONE) +#define F_DONE V_DONE(1U) + +#define S_WL_ERR_CLK16_ST 11 +#define V_WL_ERR_CLK16_ST(x) ((x) << S_WL_ERR_CLK16_ST) +#define F_WL_ERR_CLK16_ST V_WL_ERR_CLK16_ST(1U) + +#define S_WL_ERR_CLK18_ST 10 +#define V_WL_ERR_CLK18_ST(x) ((x) << S_WL_ERR_CLK18_ST) +#define F_WL_ERR_CLK18_ST V_WL_ERR_CLK18_ST(1U) + +#define S_WL_ERR_CLK20_ST 9 +#define V_WL_ERR_CLK20_ST(x) ((x) << S_WL_ERR_CLK20_ST) +#define F_WL_ERR_CLK20_ST V_WL_ERR_CLK20_ST(1U) + +#define S_WL_ERR_CLK22_ST 8 +#define V_WL_ERR_CLK22_ST(x) ((x) << S_WL_ERR_CLK22_ST) +#define F_WL_ERR_CLK22_ST V_WL_ERR_CLK22_ST(1U) + +#define S_ZERO_DETECTED 7 +#define V_ZERO_DETECTED(x) ((x) << S_ZERO_DETECTED) +#define F_ZERO_DETECTED V_ZERO_DETECTED(1U) + +#define A_MC_DDRPHY_DP18_WR_CNTR_STATUS0 0x44060 + +#define S_BIT_CENTERED 11 +#define M_BIT_CENTERED 0x1fU +#define V_BIT_CENTERED(x) ((x) << S_BIT_CENTERED) +#define G_BIT_CENTERED(x) (((x) >> S_BIT_CENTERED) & M_BIT_CENTERED) + +#define S_SMALL_STEP_LEFT 10 +#define V_SMALL_STEP_LEFT(x) ((x) << S_SMALL_STEP_LEFT) +#define F_SMALL_STEP_LEFT V_SMALL_STEP_LEFT(1U) + +#define S_BIG_STEP_RIGHT 9 +#define V_BIG_STEP_RIGHT(x) ((x) << S_BIG_STEP_RIGHT) +#define F_BIG_STEP_RIGHT V_BIG_STEP_RIGHT(1U) + +#define S_MATCH_STEP_RIGHT 8 +#define V_MATCH_STEP_RIGHT(x) ((x) << S_MATCH_STEP_RIGHT) +#define F_MATCH_STEP_RIGHT V_MATCH_STEP_RIGHT(1U) + +#define S_JUMP_BACK_RIGHT 7 +#define V_JUMP_BACK_RIGHT(x) ((x) << S_JUMP_BACK_RIGHT) +#define F_JUMP_BACK_RIGHT V_JUMP_BACK_RIGHT(1U) + +#define S_SMALL_STEP_RIGHT 6 +#define V_SMALL_STEP_RIGHT(x) ((x) << S_SMALL_STEP_RIGHT) +#define F_SMALL_STEP_RIGHT V_SMALL_STEP_RIGHT(1U) + +#define S_DDONE 5 +#define V_DDONE(x) ((x) << S_DDONE) +#define F_DDONE V_DDONE(1U) + +#define A_MC_DDRPHY_DP18_WR_CNTR_STATUS1 0x44064 + +#define S_FW_LEFT_SIDE 5 +#define M_FW_LEFT_SIDE 0x7ffU +#define V_FW_LEFT_SIDE(x) ((x) << S_FW_LEFT_SIDE) +#define G_FW_LEFT_SIDE(x) (((x) >> S_FW_LEFT_SIDE) & M_FW_LEFT_SIDE) + +#define A_MC_DDRPHY_DP18_WR_CNTR_STATUS2 0x44068 + +#define S_FW_RIGHT_SIDE 5 +#define M_FW_RIGHT_SIDE 0x7ffU +#define V_FW_RIGHT_SIDE(x) ((x) << S_FW_RIGHT_SIDE) +#define G_FW_RIGHT_SIDE(x) (((x) >> S_FW_RIGHT_SIDE) & M_FW_RIGHT_SIDE) + +#define A_MC_DDRPHY_DP18_WR_ERROR0 0x4406c + +#define S_WL_ERR_CLK16 15 +#define V_WL_ERR_CLK16(x) ((x) << S_WL_ERR_CLK16) +#define F_WL_ERR_CLK16 V_WL_ERR_CLK16(1U) + +#define S_WL_ERR_CLK18 14 +#define V_WL_ERR_CLK18(x) ((x) << S_WL_ERR_CLK18) +#define F_WL_ERR_CLK18 V_WL_ERR_CLK18(1U) + +#define S_WL_ERR_CLK20 13 +#define V_WL_ERR_CLK20(x) ((x) << S_WL_ERR_CLK20) +#define F_WL_ERR_CLK20 V_WL_ERR_CLK20(1U) + +#define S_WL_ERR_CLK22 12 +#define V_WL_ERR_CLK22(x) ((x) << S_WL_ERR_CLK22) +#define F_WL_ERR_CLK22 V_WL_ERR_CLK22(1U) + +#define S_VALID_NS_BIG_L 7 +#define V_VALID_NS_BIG_L(x) ((x) << S_VALID_NS_BIG_L) +#define F_VALID_NS_BIG_L V_VALID_NS_BIG_L(1U) + +#define S_INVALID_NS_SMALL_L 6 +#define V_INVALID_NS_SMALL_L(x) ((x) << S_INVALID_NS_SMALL_L) +#define F_INVALID_NS_SMALL_L V_INVALID_NS_SMALL_L(1U) + +#define S_VALID_NS_BIG_R 5 +#define V_VALID_NS_BIG_R(x) ((x) << S_VALID_NS_BIG_R) +#define F_VALID_NS_BIG_R V_VALID_NS_BIG_R(1U) + +#define S_INVALID_NS_BIG_R 4 +#define V_INVALID_NS_BIG_R(x) ((x) << S_INVALID_NS_BIG_R) +#define F_INVALID_NS_BIG_R V_INVALID_NS_BIG_R(1U) + +#define S_VALID_NS_JUMP_BACK 3 +#define V_VALID_NS_JUMP_BACK(x) ((x) << S_VALID_NS_JUMP_BACK) +#define F_VALID_NS_JUMP_BACK V_VALID_NS_JUMP_BACK(1U) + +#define S_INVALID_NS_SMALL_R 2 +#define V_INVALID_NS_SMALL_R(x) ((x) << S_INVALID_NS_SMALL_R) +#define F_INVALID_NS_SMALL_R V_INVALID_NS_SMALL_R(1U) + +#define S_OFFSET_ERR 1 +#define V_OFFSET_ERR(x) ((x) << S_OFFSET_ERR) +#define F_OFFSET_ERR V_OFFSET_ERR(1U) + +#define A_MC_DDRPHY_DP18_WR_ERROR_MASK0 0x44070 + +#define S_WL_ERR_CLK16_MASK 15 +#define V_WL_ERR_CLK16_MASK(x) ((x) << S_WL_ERR_CLK16_MASK) +#define F_WL_ERR_CLK16_MASK V_WL_ERR_CLK16_MASK(1U) + +#define S_WL_ERR_CLK18_MASK 14 +#define V_WL_ERR_CLK18_MASK(x) ((x) << S_WL_ERR_CLK18_MASK) +#define F_WL_ERR_CLK18_MASK V_WL_ERR_CLK18_MASK(1U) + +#define S_WL_ERR_CLK20_MASK 13 +#define V_WL_ERR_CLK20_MASK(x) ((x) << S_WL_ERR_CLK20_MASK) +#define F_WL_ERR_CLK20_MASK V_WL_ERR_CLK20_MASK(1U) + +#define S_WR_ERR_CLK22_MASK 12 +#define V_WR_ERR_CLK22_MASK(x) ((x) << S_WR_ERR_CLK22_MASK) +#define F_WR_ERR_CLK22_MASK V_WR_ERR_CLK22_MASK(1U) + +#define S_VALID_NS_BIG_L_MASK 7 +#define V_VALID_NS_BIG_L_MASK(x) ((x) << S_VALID_NS_BIG_L_MASK) +#define F_VALID_NS_BIG_L_MASK V_VALID_NS_BIG_L_MASK(1U) + +#define S_INVALID_NS_SMALL_L_MASK 6 +#define V_INVALID_NS_SMALL_L_MASK(x) ((x) << S_INVALID_NS_SMALL_L_MASK) +#define F_INVALID_NS_SMALL_L_MASK V_INVALID_NS_SMALL_L_MASK(1U) + +#define S_VALID_NS_BIG_R_MASK 5 +#define V_VALID_NS_BIG_R_MASK(x) ((x) << S_VALID_NS_BIG_R_MASK) +#define F_VALID_NS_BIG_R_MASK V_VALID_NS_BIG_R_MASK(1U) + +#define S_INVALID_NS_BIG_R_MASK 4 +#define V_INVALID_NS_BIG_R_MASK(x) ((x) << S_INVALID_NS_BIG_R_MASK) +#define F_INVALID_NS_BIG_R_MASK V_INVALID_NS_BIG_R_MASK(1U) + +#define S_VALID_NS_JUMP_BACK_MASK 3 +#define V_VALID_NS_JUMP_BACK_MASK(x) ((x) << S_VALID_NS_JUMP_BACK_MASK) +#define F_VALID_NS_JUMP_BACK_MASK V_VALID_NS_JUMP_BACK_MASK(1U) + +#define S_INVALID_NS_SMALL_R_MASK 2 +#define V_INVALID_NS_SMALL_R_MASK(x) ((x) << S_INVALID_NS_SMALL_R_MASK) +#define F_INVALID_NS_SMALL_R_MASK V_INVALID_NS_SMALL_R_MASK(1U) + +#define S_OFFSET_ERR_MASK 1 +#define V_OFFSET_ERR_MASK(x) ((x) << S_OFFSET_ERR_MASK) +#define F_OFFSET_ERR_MASK V_OFFSET_ERR_MASK(1U) + +#define A_MC_DDRPHY_DP18_DFT_WRAP_STATUS 0x44074 + +#define S_CHECKER_RESET 14 +#define V_CHECKER_RESET(x) ((x) << S_CHECKER_RESET) +#define F_CHECKER_RESET V_CHECKER_RESET(1U) + +#define S_DP18_DFT_SYNC 6 +#define M_DP18_DFT_SYNC 0x3fU +#define V_DP18_DFT_SYNC(x) ((x) << S_DP18_DFT_SYNC) +#define G_DP18_DFT_SYNC(x) (((x) >> S_DP18_DFT_SYNC) & M_DP18_DFT_SYNC) + +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG0 0x44078 +#define A_MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR 0x440c0 + +#define S_DQSCLK_ROT_CLK_N0_N2 8 +#define M_DQSCLK_ROT_CLK_N0_N2 0x7fU +#define V_DQSCLK_ROT_CLK_N0_N2(x) ((x) << S_DQSCLK_ROT_CLK_N0_N2) +#define G_DQSCLK_ROT_CLK_N0_N2(x) \ + (((x) >> S_DQSCLK_ROT_CLK_N0_N2) & M_DQSCLK_ROT_CLK_N0_N2) + +#define S_DQSCLK_ROT_CLK_N1_N3 0 +#define M_DQSCLK_ROT_CLK_N1_N3 0x7fU +#define V_DQSCLK_ROT_CLK_N1_N3(x) ((x) << S_DQSCLK_ROT_CLK_N1_N3) +#define G_DQSCLK_ROT_CLK_N1_N3(x) \ + (((x) >> S_DQSCLK_ROT_CLK_N1_N3) & M_DQSCLK_ROT_CLK_N1_N3) + +#define A_MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR 0x440c4 +#define A_MC_DDRPHY_DP18_PATTERN_POS_0 0x440c8 + +#define S_MEMINTD00_POS 14 +#define M_MEMINTD00_POS 0x3U +#define V_MEMINTD00_POS(x) ((x) << S_MEMINTD00_POS) +#define G_MEMINTD00_POS(x) (((x) >> S_MEMINTD00_POS) & M_MEMINTD00_POS) + +#define S_MEMINTD01_PO 12 +#define M_MEMINTD01_PO 0x3U +#define V_MEMINTD01_PO(x) ((x) << S_MEMINTD01_PO) +#define G_MEMINTD01_PO(x) (((x) >> S_MEMINTD01_PO) & M_MEMINTD01_PO) + +#define S_MEMINTD02_POS 10 +#define M_MEMINTD02_POS 0x3U +#define V_MEMINTD02_POS(x) ((x) << S_MEMINTD02_POS) +#define G_MEMINTD02_POS(x) (((x) >> S_MEMINTD02_POS) & M_MEMINTD02_POS) + +#define S_MEMINTD03_POS 8 +#define M_MEMINTD03_POS 0x3U +#define V_MEMINTD03_POS(x) ((x) << S_MEMINTD03_POS) +#define G_MEMINTD03_POS(x) (((x) >> S_MEMINTD03_POS) & M_MEMINTD03_POS) + +#define S_MEMINTD04_POS 6 +#define M_MEMINTD04_POS 0x3U +#define V_MEMINTD04_POS(x) ((x) << S_MEMINTD04_POS) +#define G_MEMINTD04_POS(x) (((x) >> S_MEMINTD04_POS) & M_MEMINTD04_POS) + +#define S_MEMINTD05_POS 4 +#define M_MEMINTD05_POS 0x3U +#define V_MEMINTD05_POS(x) ((x) << S_MEMINTD05_POS) +#define G_MEMINTD05_POS(x) (((x) >> S_MEMINTD05_POS) & M_MEMINTD05_POS) + +#define S_MEMINTD06_POS 2 +#define M_MEMINTD06_POS 0x3U +#define V_MEMINTD06_POS(x) ((x) << S_MEMINTD06_POS) +#define G_MEMINTD06_POS(x) (((x) >> S_MEMINTD06_POS) & M_MEMINTD06_POS) + +#define S_MEMINTD07_POS 0 +#define M_MEMINTD07_POS 0x3U +#define V_MEMINTD07_POS(x) ((x) << S_MEMINTD07_POS) +#define G_MEMINTD07_POS(x) (((x) >> S_MEMINTD07_POS) & M_MEMINTD07_POS) + +#define A_MC_DDRPHY_DP18_PATTERN_POS_1 0x440cc + +#define S_MEMINTD08_POS 14 +#define M_MEMINTD08_POS 0x3U +#define V_MEMINTD08_POS(x) ((x) << S_MEMINTD08_POS) +#define G_MEMINTD08_POS(x) (((x) >> S_MEMINTD08_POS) & M_MEMINTD08_POS) + +#define S_MEMINTD09_POS 12 +#define M_MEMINTD09_POS 0x3U +#define V_MEMINTD09_POS(x) ((x) << S_MEMINTD09_POS) +#define G_MEMINTD09_POS(x) (((x) >> S_MEMINTD09_POS) & M_MEMINTD09_POS) + +#define S_MEMINTD10_POS 10 +#define M_MEMINTD10_POS 0x3U +#define V_MEMINTD10_POS(x) ((x) << S_MEMINTD10_POS) +#define G_MEMINTD10_POS(x) (((x) >> S_MEMINTD10_POS) & M_MEMINTD10_POS) + +#define S_MEMINTD11_POS 8 +#define M_MEMINTD11_POS 0x3U +#define V_MEMINTD11_POS(x) ((x) << S_MEMINTD11_POS) +#define G_MEMINTD11_POS(x) (((x) >> S_MEMINTD11_POS) & M_MEMINTD11_POS) + +#define S_MEMINTD12_POS 6 +#define M_MEMINTD12_POS 0x3U +#define V_MEMINTD12_POS(x) ((x) << S_MEMINTD12_POS) +#define G_MEMINTD12_POS(x) (((x) >> S_MEMINTD12_POS) & M_MEMINTD12_POS) + +#define S_MEMINTD13_POS 4 +#define M_MEMINTD13_POS 0x3U +#define V_MEMINTD13_POS(x) ((x) << S_MEMINTD13_POS) +#define G_MEMINTD13_POS(x) (((x) >> S_MEMINTD13_POS) & M_MEMINTD13_POS) + +#define S_MEMINTD14_POS 2 +#define M_MEMINTD14_POS 0x3U +#define V_MEMINTD14_POS(x) ((x) << S_MEMINTD14_POS) +#define G_MEMINTD14_POS(x) (((x) >> S_MEMINTD14_POS) & M_MEMINTD14_POS) + +#define S_MEMINTD15_POS 0 +#define M_MEMINTD15_POS 0x3U +#define V_MEMINTD15_POS(x) ((x) << S_MEMINTD15_POS) +#define G_MEMINTD15_POS(x) (((x) >> S_MEMINTD15_POS) & M_MEMINTD15_POS) + +#define A_MC_DDRPHY_DP18_PATTERN_POS_2 0x440d0 + +#define S_MEMINTD16_POS 14 +#define M_MEMINTD16_POS 0x3U +#define V_MEMINTD16_POS(x) ((x) << S_MEMINTD16_POS) +#define G_MEMINTD16_POS(x) (((x) >> S_MEMINTD16_POS) & M_MEMINTD16_POS) + +#define S_MEMINTD17_POS 12 +#define M_MEMINTD17_POS 0x3U +#define V_MEMINTD17_POS(x) ((x) << S_MEMINTD17_POS) +#define G_MEMINTD17_POS(x) (((x) >> S_MEMINTD17_POS) & M_MEMINTD17_POS) + +#define S_MEMINTD18_POS 10 +#define M_MEMINTD18_POS 0x3U +#define V_MEMINTD18_POS(x) ((x) << S_MEMINTD18_POS) +#define G_MEMINTD18_POS(x) (((x) >> S_MEMINTD18_POS) & M_MEMINTD18_POS) + +#define S_MEMINTD19_POS 8 +#define M_MEMINTD19_POS 0x3U +#define V_MEMINTD19_POS(x) ((x) << S_MEMINTD19_POS) +#define G_MEMINTD19_POS(x) (((x) >> S_MEMINTD19_POS) & M_MEMINTD19_POS) + +#define S_MEMINTD20_POS 6 +#define M_MEMINTD20_POS 0x3U +#define V_MEMINTD20_POS(x) ((x) << S_MEMINTD20_POS) +#define G_MEMINTD20_POS(x) (((x) >> S_MEMINTD20_POS) & M_MEMINTD20_POS) + +#define S_MEMINTD21_POS 4 +#define M_MEMINTD21_POS 0x3U +#define V_MEMINTD21_POS(x) ((x) << S_MEMINTD21_POS) +#define G_MEMINTD21_POS(x) (((x) >> S_MEMINTD21_POS) & M_MEMINTD21_POS) + +#define S_MEMINTD22_POS 2 +#define M_MEMINTD22_POS 0x3U +#define V_MEMINTD22_POS(x) ((x) << S_MEMINTD22_POS) +#define G_MEMINTD22_POS(x) (((x) >> S_MEMINTD22_POS) & M_MEMINTD22_POS) + +#define S_MEMINTD23_POS 0 +#define M_MEMINTD23_POS 0x3U +#define V_MEMINTD23_POS(x) ((x) << S_MEMINTD23_POS) +#define G_MEMINTD23_POS(x) (((x) >> S_MEMINTD23_POS) & M_MEMINTD23_POS) + +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG1 0x440d4 +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG2 0x440d8 +#define A_MC_DDRPHY_DP18_DQSCLK_OFFSET 0x440dc + +#define S_DQS_OFFSET 8 +#define M_DQS_OFFSET 0x7fU +#define V_DQS_OFFSET(x) ((x) << S_DQS_OFFSET) +#define G_DQS_OFFSET(x) (((x) >> S_DQS_OFFSET) & M_DQS_OFFSET) + +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP 0x440e0 + +#define S_WR_DELAY 6 +#define M_WR_DELAY 0x3ffU +#define V_WR_DELAY(x) ((x) << S_WR_DELAY) +#define G_WR_DELAY(x) (((x) >> S_WR_DELAY) & M_WR_DELAY) + +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP 0x440e4 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP 0x440e8 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP 0x440ec +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP 0x440f0 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP 0x440f4 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP 0x440f8 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP 0x440fc +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP 0x44100 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP 0x44104 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP 0x44108 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP 0x4410c +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP 0x44110 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP 0x44114 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP 0x44118 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP 0x4411c +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP 0x44120 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP 0x44124 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP 0x44128 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP 0x4412c +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP 0x44130 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP 0x44134 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP 0x44138 +#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP 0x4413c +#define A_MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR 0x44140 + +#define S_RD_DELAY_BITS0_6 9 +#define M_RD_DELAY_BITS0_6 0x7fU +#define V_RD_DELAY_BITS0_6(x) ((x) << S_RD_DELAY_BITS0_6) +#define G_RD_DELAY_BITS0_6(x) (((x) >> S_RD_DELAY_BITS0_6) & M_RD_DELAY_BITS0_6) + +#define S_RD_DELAY_BITS8_14 1 +#define M_RD_DELAY_BITS8_14 0x7fU +#define V_RD_DELAY_BITS8_14(x) ((x) << S_RD_DELAY_BITS8_14) +#define G_RD_DELAY_BITS8_14(x) \ + (((x) >> S_RD_DELAY_BITS8_14) & M_RD_DELAY_BITS8_14) + +#define A_MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR 0x44144 +#define A_MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR 0x44148 +#define A_MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR 0x4414c +#define A_MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR 0x44150 +#define A_MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR 0x44154 +#define A_MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR 0x44158 +#define A_MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR 0x4415c +#define A_MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR 0x44160 +#define A_MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR 0x44164 +#define A_MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR 0x44168 +#define A_MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR 0x4416c +#define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR 0x44170 + +#define S_INITIAL_DQS_ROT_N0_N2 8 +#define M_INITIAL_DQS_ROT_N0_N2 0x7fU +#define V_INITIAL_DQS_ROT_N0_N2(x) ((x) << S_INITIAL_DQS_ROT_N0_N2) +#define G_INITIAL_DQS_ROT_N0_N2(x) \ + (((x) >> S_INITIAL_DQS_ROT_N0_N2) & M_INITIAL_DQS_ROT_N0_N2) + +#define S_INITIAL_DQS_ROT_N1_N3 0 +#define M_INITIAL_DQS_ROT_N1_N3 0x7fU +#define V_INITIAL_DQS_ROT_N1_N3(x) ((x) << S_INITIAL_DQS_ROT_N1_N3) +#define G_INITIAL_DQS_ROT_N1_N3(x) \ + (((x) >> S_INITIAL_DQS_ROT_N1_N3) & M_INITIAL_DQS_ROT_N1_N3) + +#define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR 0x44174 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR 0x44180 + +#define S_RD_EYE_SIZE_BITS2_7 8 +#define M_RD_EYE_SIZE_BITS2_7 0x3fU +#define V_RD_EYE_SIZE_BITS2_7(x) ((x) << S_RD_EYE_SIZE_BITS2_7) +#define G_RD_EYE_SIZE_BITS2_7(x) \ + (((x) >> S_RD_EYE_SIZE_BITS2_7) & M_RD_EYE_SIZE_BITS2_7) + +#define S_RD_EYE_SIZE_BITS10_15 0 +#define M_RD_EYE_SIZE_BITS10_15 0x3fU +#define V_RD_EYE_SIZE_BITS10_15(x) ((x) << S_RD_EYE_SIZE_BITS10_15) +#define G_RD_EYE_SIZE_BITS10_15(x) \ + (((x) >> S_RD_EYE_SIZE_BITS10_15) & M_RD_EYE_SIZE_BITS10_15) + +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR 0x44184 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR 0x44188 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR 0x4418c +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR 0x44190 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR 0x44194 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR 0x44198 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR 0x4419c +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR 0x441a0 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR 0x441a4 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR 0x441a8 +#define A_MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR 0x441ac +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG3 0x441b4 +#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG4 0x441b8 +#define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 0x441c0 + +#define S_REFERENCE_BITS1_7 8 +#define M_REFERENCE_BITS1_7 0x7fU +#define V_REFERENCE_BITS1_7(x) ((x) << S_REFERENCE_BITS1_7) +#define G_REFERENCE_BITS1_7(x) \ + (((x) >> S_REFERENCE_BITS1_7) & M_REFERENCE_BITS1_7) + +#define S_REFERENCE_BITS9_15 0 +#define M_REFERENCE_BITS9_15 0x7fU +#define V_REFERENCE_BITS9_15(x) ((x) << S_REFERENCE_BITS9_15) +#define G_REFERENCE_BITS9_15(x) \ + (((x) >> S_REFERENCE_BITS9_15) & M_REFERENCE_BITS9_15) + +#define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE1 0x441c4 +#define A_MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE 0x441c8 + +#define S_REFERENCE 8 +#define M_REFERENCE 0x7fU +#define V_REFERENCE(x) ((x) << S_REFERENCE) +#define G_REFERENCE(x) (((x) >> S_REFERENCE) & M_REFERENCE) + +#define A_MC_DDRPHY_DP18_SYSCLK_PR_VALUE 0x441cc +#define A_MC_DDRPHY_DP18_WRCLK_PR 0x441d0 +#define A_MC_DDRPHY_DP18_IO_TX_CONFIG0 0x441d4 + +#define S_INTERP_SIG_SLEW 12 +#define M_INTERP_SIG_SLEW 0xfU +#define V_INTERP_SIG_SLEW(x) ((x) << S_INTERP_SIG_SLEW) +#define G_INTERP_SIG_SLEW(x) (((x) >> S_INTERP_SIG_SLEW) & M_INTERP_SIG_SLEW) + +#define S_POST_CURSOR 8 +#define M_POST_CURSOR 0xfU +#define V_POST_CURSOR(x) ((x) << S_POST_CURSOR) +#define G_POST_CURSOR(x) (((x) >> S_POST_CURSOR) & M_POST_CURSOR) + +#define S_SLEW_CTL 4 +#define M_SLEW_CTL 0xfU +#define V_SLEW_CTL(x) ((x) << S_SLEW_CTL) +#define G_SLEW_CTL(x) (((x) >> S_SLEW_CTL) & M_SLEW_CTL) + +#define A_MC_DDRPHY_DP18_PLL_CONFIG0 0x441d8 +#define A_MC_DDRPHY_DP18_PLL_CONFIG1 0x441dc + +#define S_CE0DLTVCCA 7 +#define V_CE0DLTVCCA(x) ((x) << S_CE0DLTVCCA) +#define F_CE0DLTVCCA V_CE0DLTVCCA(1U) + +#define S_CE0DLTVCCD1 4 +#define V_CE0DLTVCCD1(x) ((x) << S_CE0DLTVCCD1) +#define F_CE0DLTVCCD1 V_CE0DLTVCCD1(1U) + +#define S_CE0DLTVCCD2 3 +#define V_CE0DLTVCCD2(x) ((x) << S_CE0DLTVCCD2) +#define F_CE0DLTVCCD2 V_CE0DLTVCCD2(1U) + +#define S_S0INSDLYTAP 2 +#define V_S0INSDLYTAP(x) ((x) << S_S0INSDLYTAP) +#define F_S0INSDLYTAP V_S0INSDLYTAP(1U) + +#define S_S1INSDLYTAP 1 +#define V_S1INSDLYTAP(x) ((x) << S_S1INSDLYTAP) +#define F_S1INSDLYTAP V_S1INSDLYTAP(1U) + +#define A_MC_DDRPHY_DP18_IO_TX_NFET_SLICE 0x441e0 + +#define S_EN_SLICE_N_WR 8 +#define M_EN_SLICE_N_WR 0xffU +#define V_EN_SLICE_N_WR(x) ((x) << S_EN_SLICE_N_WR) +#define G_EN_SLICE_N_WR(x) (((x) >> S_EN_SLICE_N_WR) & M_EN_SLICE_N_WR) + +#define A_MC_DDRPHY_DP18_IO_TX_PFET_SLICE 0x441e4 +#define A_MC_DDRPHY_DP18_IO_TX_NFET_TERM 0x441e8 + +#define S_EN_TERM_N_WR 8 +#define M_EN_TERM_N_WR 0xffU +#define V_EN_TERM_N_WR(x) ((x) << S_EN_TERM_N_WR) +#define G_EN_TERM_N_WR(x) (((x) >> S_EN_TERM_N_WR) & M_EN_TERM_N_WR) + +#define S_EN_TERM_N_WR_FFE 4 +#define M_EN_TERM_N_WR_FFE 0xfU +#define V_EN_TERM_N_WR_FFE(x) ((x) << S_EN_TERM_N_WR_FFE) +#define G_EN_TERM_N_WR_FFE(x) (((x) >> S_EN_TERM_N_WR_FFE) & M_EN_TERM_N_WR_FFE) + +#define A_MC_DDRPHY_DP18_IO_TX_PFET_TERM 0x441ec + +#define S_EN_TERM_P_WR 8 +#define M_EN_TERM_P_WR 0xffU +#define V_EN_TERM_P_WR(x) ((x) << S_EN_TERM_P_WR) +#define G_EN_TERM_P_WR(x) (((x) >> S_EN_TERM_P_WR) & M_EN_TERM_P_WR) + +#define S_EN_TERM_P_WR_FFE 4 +#define M_EN_TERM_P_WR_FFE 0xfU +#define V_EN_TERM_P_WR_FFE(x) ((x) << S_EN_TERM_P_WR_FFE) +#define G_EN_TERM_P_WR_FFE(x) (((x) >> S_EN_TERM_P_WR_FFE) & M_EN_TERM_P_WR_FFE) + +#define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP 0x441f0 + +#define S_DATA_BIT_DISABLE_0_15 0 +#define M_DATA_BIT_DISABLE_0_15 0xffffU +#define V_DATA_BIT_DISABLE_0_15(x) ((x) << S_DATA_BIT_DISABLE_0_15) +#define G_DATA_BIT_DISABLE_0_15(x) \ + (((x) >> S_DATA_BIT_DISABLE_0_15) & M_DATA_BIT_DISABLE_0_15) + +#define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP 0x441f4 + +#define S_DATA_BIT_DISABLE_16_23 8 +#define M_DATA_BIT_DISABLE_16_23 0xffU +#define V_DATA_BIT_DISABLE_16_23(x) ((x) << S_DATA_BIT_DISABLE_16_23) +#define G_DATA_BIT_DISABLE_16_23(x) \ + (((x) >> S_DATA_BIT_DISABLE_16_23) & M_DATA_BIT_DISABLE_16_23) + +#define A_MC_DDRPHY_DP18_DQ_WR_OFFSET_RP 0x441f8 + +#define S_DQ_WR_OFFSET_N0 12 +#define M_DQ_WR_OFFSET_N0 0xfU +#define V_DQ_WR_OFFSET_N0(x) ((x) << S_DQ_WR_OFFSET_N0) +#define G_DQ_WR_OFFSET_N0(x) (((x) >> S_DQ_WR_OFFSET_N0) & M_DQ_WR_OFFSET_N0) + +#define S_DQ_WR_OFFSET_N1 8 +#define M_DQ_WR_OFFSET_N1 0xfU +#define V_DQ_WR_OFFSET_N1(x) ((x) << S_DQ_WR_OFFSET_N1) +#define G_DQ_WR_OFFSET_N1(x) (((x) >> S_DQ_WR_OFFSET_N1) & M_DQ_WR_OFFSET_N1) + +#define S_DQ_WR_OFFSET_N2 4 +#define M_DQ_WR_OFFSET_N2 0xfU +#define V_DQ_WR_OFFSET_N2(x) ((x) << S_DQ_WR_OFFSET_N2) +#define G_DQ_WR_OFFSET_N2(x) (((x) >> S_DQ_WR_OFFSET_N2) & M_DQ_WR_OFFSET_N2) + +#define S_DQ_WR_OFFSET_N3 0 +#define M_DQ_WR_OFFSET_N3 0xfU +#define V_DQ_WR_OFFSET_N3(x) ((x) << S_DQ_WR_OFFSET_N3) +#define G_DQ_WR_OFFSET_N3(x) (((x) >> S_DQ_WR_OFFSET_N3) & M_DQ_WR_OFFSET_N3) + +#define A_MC_DDRPHY_DP18_POWERDOWN_1 0x441fc +#define A_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45000 + +#define S_BIT_ENABLE_0_11 4 +#define M_BIT_ENABLE_0_11 0xfffU +#define V_BIT_ENABLE_0_11(x) ((x) << S_BIT_ENABLE_0_11) +#define G_BIT_ENABLE_0_11(x) (((x) >> S_BIT_ENABLE_0_11) & M_BIT_ENABLE_0_11) + +#define S_BIT_ENABLE_12_15 0 +#define M_BIT_ENABLE_12_15 0xfU +#define V_BIT_ENABLE_12_15(x) ((x) << S_BIT_ENABLE_12_15) +#define G_BIT_ENABLE_12_15(x) (((x) >> S_BIT_ENABLE_12_15) & M_BIT_ENABLE_12_15) + +#define A_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45004 + +#define S_DI_ADR0_ADR1 15 +#define V_DI_ADR0_ADR1(x) ((x) << S_DI_ADR0_ADR1) +#define F_DI_ADR0_ADR1 V_DI_ADR0_ADR1(1U) + +#define S_DI_ADR2_ADR3 14 +#define V_DI_ADR2_ADR3(x) ((x) << S_DI_ADR2_ADR3) +#define F_DI_ADR2_ADR3 V_DI_ADR2_ADR3(1U) + +#define S_DI_ADR4_ADR5 13 +#define V_DI_ADR4_ADR5(x) ((x) << S_DI_ADR4_ADR5) +#define F_DI_ADR4_ADR5 V_DI_ADR4_ADR5(1U) + +#define S_DI_ADR6_ADR7 12 +#define V_DI_ADR6_ADR7(x) ((x) << S_DI_ADR6_ADR7) +#define F_DI_ADR6_ADR7 V_DI_ADR6_ADR7(1U) + +#define S_DI_ADR8_ADR9 11 +#define V_DI_ADR8_ADR9(x) ((x) << S_DI_ADR8_ADR9) +#define F_DI_ADR8_ADR9 V_DI_ADR8_ADR9(1U) + +#define S_DI_ADR10_ADR11 10 +#define V_DI_ADR10_ADR11(x) ((x) << S_DI_ADR10_ADR11) +#define F_DI_ADR10_ADR11 V_DI_ADR10_ADR11(1U) + +#define S_DI_ADR12_ADR13 9 +#define V_DI_ADR12_ADR13(x) ((x) << S_DI_ADR12_ADR13) +#define F_DI_ADR12_ADR13 V_DI_ADR12_ADR13(1U) + +#define S_DI_ADR14_ADR15 8 +#define V_DI_ADR14_ADR15(x) ((x) << S_DI_ADR14_ADR15) +#define F_DI_ADR14_ADR15 V_DI_ADR14_ADR15(1U) + +#define A_MC_ADR_DDRPHY_ADR_DELAY0 0x45010 + +#define S_ADR_DELAY_BITS1_7 8 +#define M_ADR_DELAY_BITS1_7 0x7fU +#define V_ADR_DELAY_BITS1_7(x) ((x) << S_ADR_DELAY_BITS1_7) +#define G_ADR_DELAY_BITS1_7(x) \ + (((x) >> S_ADR_DELAY_BITS1_7) & M_ADR_DELAY_BITS1_7) + +#define S_ADR_DELAY_BITS9_15 0 +#define M_ADR_DELAY_BITS9_15 0x7fU +#define V_ADR_DELAY_BITS9_15(x) ((x) << S_ADR_DELAY_BITS9_15) +#define G_ADR_DELAY_BITS9_15(x) \ + (((x) >> S_ADR_DELAY_BITS9_15) & M_ADR_DELAY_BITS9_15) + +#define A_MC_ADR_DDRPHY_ADR_DELAY1 0x45014 +#define A_MC_ADR_DDRPHY_ADR_DELAY2 0x45018 +#define A_MC_ADR_DDRPHY_ADR_DELAY3 0x4501c +#define A_MC_ADR_DDRPHY_ADR_DELAY4 0x45020 +#define A_MC_ADR_DDRPHY_ADR_DELAY5 0x45024 +#define A_MC_ADR_DDRPHY_ADR_DELAY6 0x45028 +#define A_MC_ADR_DDRPHY_ADR_DELAY7 0x4502c +#define A_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45030 + +#define S_ADR_TEST_LANE_PAIR_FAIL 8 +#define M_ADR_TEST_LANE_PAIR_FAIL 0xffU +#define V_ADR_TEST_LANE_PAIR_FAIL(x) ((x) << S_ADR_TEST_LANE_PAIR_FAIL) +#define G_ADR_TEST_LANE_PAIR_FAIL(x) \ + (((x) >> S_ADR_TEST_LANE_PAIR_FAIL) & M_ADR_TEST_LANE_PAIR_FAIL) + +#define S_ADR_TEST_DATA_EN 7 +#define V_ADR_TEST_DATA_EN(x) ((x) << S_ADR_TEST_DATA_EN) +#define F_ADR_TEST_DATA_EN V_ADR_TEST_DATA_EN(1U) + +#define S_DADR_TEST_MODE 5 +#define M_DADR_TEST_MODE 0x3U +#define V_DADR_TEST_MODE(x) ((x) << S_DADR_TEST_MODE) +#define G_DADR_TEST_MODE(x) (((x) >> S_DADR_TEST_MODE) & M_DADR_TEST_MODE) + +#define S_ADR_TEST_4TO1_MODE 4 +#define V_ADR_TEST_4TO1_MODE(x) ((x) << S_ADR_TEST_4TO1_MODE) +#define F_ADR_TEST_4TO1_MODE V_ADR_TEST_4TO1_MODE(1U) + +#define S_ADR_TEST_RESET 3 +#define V_ADR_TEST_RESET(x) ((x) << S_ADR_TEST_RESET) +#define F_ADR_TEST_RESET V_ADR_TEST_RESET(1U) + +#define S_ADR_TEST_GEN_EN 2 +#define V_ADR_TEST_GEN_EN(x) ((x) << S_ADR_TEST_GEN_EN) +#define F_ADR_TEST_GEN_EN V_ADR_TEST_GEN_EN(1U) + +#define S_ADR_TEST_CLEAR_ERROR 1 +#define V_ADR_TEST_CLEAR_ERROR(x) ((x) << S_ADR_TEST_CLEAR_ERROR) +#define F_ADR_TEST_CLEAR_ERROR V_ADR_TEST_CLEAR_ERROR(1U) + +#define S_ADR_TEST_CHECK_EN 0 +#define V_ADR_TEST_CHECK_EN(x) ((x) << S_ADR_TEST_CHECK_EN) +#define F_ADR_TEST_CHECK_EN V_ADR_TEST_CHECK_EN(1U) + +#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45040 + +#define S_EN_SLICE_N_WR_0 8 +#define M_EN_SLICE_N_WR_0 0xffU +#define V_EN_SLICE_N_WR_0(x) ((x) << S_EN_SLICE_N_WR_0) +#define G_EN_SLICE_N_WR_0(x) (((x) >> S_EN_SLICE_N_WR_0) & M_EN_SLICE_N_WR_0) + +#define S_EN_SLICE_N_WR_FFE 4 +#define M_EN_SLICE_N_WR_FFE 0xfU +#define V_EN_SLICE_N_WR_FFE(x) ((x) << S_EN_SLICE_N_WR_FFE) +#define G_EN_SLICE_N_WR_FFE(x) \ + (((x) >> S_EN_SLICE_N_WR_FFE) & M_EN_SLICE_N_WR_FFE) + +#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45044 + +#define S_EN_SLICE_N_WR_1 8 +#define M_EN_SLICE_N_WR_1 0xffU +#define V_EN_SLICE_N_WR_1(x) ((x) << S_EN_SLICE_N_WR_1) +#define G_EN_SLICE_N_WR_1(x) (((x) >> S_EN_SLICE_N_WR_1) & M_EN_SLICE_N_WR_1) + +#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45048 + +#define S_EN_SLICE_N_WR_2 8 +#define M_EN_SLICE_N_WR_2 0xffU +#define V_EN_SLICE_N_WR_2(x) ((x) << S_EN_SLICE_N_WR_2) +#define G_EN_SLICE_N_WR_2(x) (((x) >> S_EN_SLICE_N_WR_2) & M_EN_SLICE_N_WR_2) + +#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4504c + +#define S_EN_SLICE_N_WR_3 8 +#define M_EN_SLICE_N_WR_3 0xffU +#define V_EN_SLICE_N_WR_3(x) ((x) << S_EN_SLICE_N_WR_3) +#define G_EN_SLICE_N_WR_3(x) (((x) >> S_EN_SLICE_N_WR_3) & M_EN_SLICE_N_WR_3) + +#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45050 + +#define S_EN_SLICE_P_WR 8 +#define M_EN_SLICE_P_WR 0xffU +#define V_EN_SLICE_P_WR(x) ((x) << S_EN_SLICE_P_WR) +#define G_EN_SLICE_P_WR(x) (((x) >> S_EN_SLICE_P_WR) & M_EN_SLICE_P_WR) + +#define S_EN_SLICE_P_WR_FFE 4 +#define M_EN_SLICE_P_WR_FFE 0xfU +#define V_EN_SLICE_P_WR_FFE(x) ((x) << S_EN_SLICE_P_WR_FFE) +#define G_EN_SLICE_P_WR_FFE(x) \ + (((x) >> S_EN_SLICE_P_WR_FFE) & M_EN_SLICE_P_WR_FFE) + +#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45054 +#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45058 +#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4505c +#define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45060 + +#define S_POST_CURSOR0 12 +#define M_POST_CURSOR0 0xfU +#define V_POST_CURSOR0(x) ((x) << S_POST_CURSOR0) +#define G_POST_CURSOR0(x) (((x) >> S_POST_CURSOR0) & M_POST_CURSOR0) + +#define S_POST_CURSOR1 8 +#define M_POST_CURSOR1 0xfU +#define V_POST_CURSOR1(x) ((x) << S_POST_CURSOR1) +#define G_POST_CURSOR1(x) (((x) >> S_POST_CURSOR1) & M_POST_CURSOR1) + +#define S_POST_CURSOR2 4 +#define M_POST_CURSOR2 0xfU +#define V_POST_CURSOR2(x) ((x) << S_POST_CURSOR2) +#define G_POST_CURSOR2(x) (((x) >> S_POST_CURSOR2) & M_POST_CURSOR2) + +#define S_POST_CURSOR3 0 +#define M_POST_CURSOR3 0xfU +#define V_POST_CURSOR3(x) ((x) << S_POST_CURSOR3) +#define G_POST_CURSOR3(x) (((x) >> S_POST_CURSOR3) & M_POST_CURSOR3) + +#define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45068 + +#define S_SLEW_CTL0 12 +#define M_SLEW_CTL0 0xfU +#define V_SLEW_CTL0(x) ((x) << S_SLEW_CTL0) +#define G_SLEW_CTL0(x) (((x) >> S_SLEW_CTL0) & M_SLEW_CTL0) + +#define S_SLEW_CTL1 8 +#define M_SLEW_CTL1 0xfU +#define V_SLEW_CTL1(x) ((x) << S_SLEW_CTL1) +#define G_SLEW_CTL1(x) (((x) >> S_SLEW_CTL1) & M_SLEW_CTL1) + +#define S_SLEW_CTL2 4 +#define M_SLEW_CTL2 0xfU +#define V_SLEW_CTL2(x) ((x) << S_SLEW_CTL2) +#define G_SLEW_CTL2(x) (((x) >> S_SLEW_CTL2) & M_SLEW_CTL2) + +#define S_SLEW_CTL3 0 +#define M_SLEW_CTL3 0xfU +#define V_SLEW_CTL3(x) ((x) << S_SLEW_CTL3) +#define G_SLEW_CTL3(x) (((x) >> S_SLEW_CTL3) & M_SLEW_CTL3) + +#define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45080 + +#define S_SLICE_SEL_REG_BITS0_1 14 +#define M_SLICE_SEL_REG_BITS0_1 0x3U +#define V_SLICE_SEL_REG_BITS0_1(x) ((x) << S_SLICE_SEL_REG_BITS0_1) +#define G_SLICE_SEL_REG_BITS0_1(x) \ + (((x) >> S_SLICE_SEL_REG_BITS0_1) & M_SLICE_SEL_REG_BITS0_1) + +#define S_SLICE_SEL_REG_BITS2_3 12 +#define M_SLICE_SEL_REG_BITS2_3 0x3U +#define V_SLICE_SEL_REG_BITS2_3(x) ((x) << S_SLICE_SEL_REG_BITS2_3) +#define G_SLICE_SEL_REG_BITS2_3(x) \ + (((x) >> S_SLICE_SEL_REG_BITS2_3) & M_SLICE_SEL_REG_BITS2_3) + +#define S_SLICE_SEL_REG_BITS4_5 10 +#define M_SLICE_SEL_REG_BITS4_5 0x3U +#define V_SLICE_SEL_REG_BITS4_5(x) ((x) << S_SLICE_SEL_REG_BITS4_5) +#define G_SLICE_SEL_REG_BITS4_5(x) \ + (((x) >> S_SLICE_SEL_REG_BITS4_5) & M_SLICE_SEL_REG_BITS4_5) + +#define S_SLICE_SEL_REG_BITS6_7 8 +#define M_SLICE_SEL_REG_BITS6_7 0x3U +#define V_SLICE_SEL_REG_BITS6_7(x) ((x) << S_SLICE_SEL_REG_BITS6_7) +#define G_SLICE_SEL_REG_BITS6_7(x) \ + (((x) >> S_SLICE_SEL_REG_BITS6_7) & M_SLICE_SEL_REG_BITS6_7) + +#define S_SLICE_SEL_REG_BITS8_9 6 +#define M_SLICE_SEL_REG_BITS8_9 0x3U +#define V_SLICE_SEL_REG_BITS8_9(x) ((x) << S_SLICE_SEL_REG_BITS8_9) +#define G_SLICE_SEL_REG_BITS8_9(x) \ + (((x) >> S_SLICE_SEL_REG_BITS8_9) & M_SLICE_SEL_REG_BITS8_9) + +#define S_SLICE_SEL_REG_BITS10_11 4 +#define M_SLICE_SEL_REG_BITS10_11 0x3U +#define V_SLICE_SEL_REG_BITS10_11(x) ((x) << S_SLICE_SEL_REG_BITS10_11) +#define G_SLICE_SEL_REG_BITS10_11(x) \ + (((x) >> S_SLICE_SEL_REG_BITS10_11) & M_SLICE_SEL_REG_BITS10_11) + +#define S_SLICE_SEL_REG_BITS12_13 2 +#define M_SLICE_SEL_REG_BITS12_13 0x3U +#define V_SLICE_SEL_REG_BITS12_13(x) ((x) << S_SLICE_SEL_REG_BITS12_13) +#define G_SLICE_SEL_REG_BITS12_13(x) \ + (((x) >> S_SLICE_SEL_REG_BITS12_13) & M_SLICE_SEL_REG_BITS12_13) + +#define S_SLICE_SEL_REG_BITS14_15 0 +#define M_SLICE_SEL_REG_BITS14_15 0x3U +#define V_SLICE_SEL_REG_BITS14_15(x) ((x) << S_SLICE_SEL_REG_BITS14_15) +#define G_SLICE_SEL_REG_BITS14_15(x) \ + (((x) >> S_SLICE_SEL_REG_BITS14_15) & M_SLICE_SEL_REG_BITS14_15) + +#define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45084 +#define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x450a0 + +#define S_POST_CUR_SEL_BITS0_1 14 +#define M_POST_CUR_SEL_BITS0_1 0x3U +#define V_POST_CUR_SEL_BITS0_1(x) ((x) << S_POST_CUR_SEL_BITS0_1) +#define G_POST_CUR_SEL_BITS0_1(x) \ + (((x) >> S_POST_CUR_SEL_BITS0_1) & M_POST_CUR_SEL_BITS0_1) + +#define S_POST_CUR_SEL_BITS2_3 12 +#define M_POST_CUR_SEL_BITS2_3 0x3U +#define V_POST_CUR_SEL_BITS2_3(x) ((x) << S_POST_CUR_SEL_BITS2_3) +#define G_POST_CUR_SEL_BITS2_3(x) \ + (((x) >> S_POST_CUR_SEL_BITS2_3) & M_POST_CUR_SEL_BITS2_3) + +#define S_POST_CUR_SEL_BITS4_5 10 +#define M_POST_CUR_SEL_BITS4_5 0x3U +#define V_POST_CUR_SEL_BITS4_5(x) ((x) << S_POST_CUR_SEL_BITS4_5) +#define G_POST_CUR_SEL_BITS4_5(x) \ + (((x) >> S_POST_CUR_SEL_BITS4_5) & M_POST_CUR_SEL_BITS4_5) + +#define S_POST_CUR_SEL_BITS6_7 8 +#define M_POST_CUR_SEL_BITS6_7 0x3U +#define V_POST_CUR_SEL_BITS6_7(x) ((x) << S_POST_CUR_SEL_BITS6_7) +#define G_POST_CUR_SEL_BITS6_7(x) \ + (((x) >> S_POST_CUR_SEL_BITS6_7) & M_POST_CUR_SEL_BITS6_7) + +#define S_POST_CUR_SEL_BITS8_9 6 +#define M_POST_CUR_SEL_BITS8_9 0x3U +#define V_POST_CUR_SEL_BITS8_9(x) ((x) << S_POST_CUR_SEL_BITS8_9) +#define G_POST_CUR_SEL_BITS8_9(x) \ + (((x) >> S_POST_CUR_SEL_BITS8_9) & M_POST_CUR_SEL_BITS8_9) + +#define S_POST_CUR_SEL_BITS10_11 4 +#define M_POST_CUR_SEL_BITS10_11 0x3U +#define V_POST_CUR_SEL_BITS10_11(x) ((x) << S_POST_CUR_SEL_BITS10_11) +#define G_POST_CUR_SEL_BITS10_11(x) \ + (((x) >> S_POST_CUR_SEL_BITS10_11) & M_POST_CUR_SEL_BITS10_11) + +#define S_POST_CUR_SEL_BITS12_13 2 +#define M_POST_CUR_SEL_BITS12_13 0x3U +#define V_POST_CUR_SEL_BITS12_13(x) ((x) << S_POST_CUR_SEL_BITS12_13) +#define G_POST_CUR_SEL_BITS12_13(x) \ + (((x) >> S_POST_CUR_SEL_BITS12_13) & M_POST_CUR_SEL_BITS12_13) + +#define S_POST_CUR_SEL_BITS14_15 0 +#define M_POST_CUR_SEL_BITS14_15 0x3U +#define V_POST_CUR_SEL_BITS14_15(x) ((x) << S_POST_CUR_SEL_BITS14_15) +#define G_POST_CUR_SEL_BITS14_15(x) \ + (((x) >> S_POST_CUR_SEL_BITS14_15) & M_POST_CUR_SEL_BITS14_15) + +#define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x450a4 +#define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x450a8 + +#define S_SLEW_CTL_SEL_BITS0_1 14 +#define M_SLEW_CTL_SEL_BITS0_1 0x3U +#define V_SLEW_CTL_SEL_BITS0_1(x) ((x) << S_SLEW_CTL_SEL_BITS0_1) +#define G_SLEW_CTL_SEL_BITS0_1(x) \ + (((x) >> S_SLEW_CTL_SEL_BITS0_1) & M_SLEW_CTL_SEL_BITS0_1) + +#define S_SLEW_CTL_SEL_BITS2_3 12 +#define M_SLEW_CTL_SEL_BITS2_3 0x3U +#define V_SLEW_CTL_SEL_BITS2_3(x) ((x) << S_SLEW_CTL_SEL_BITS2_3) +#define G_SLEW_CTL_SEL_BITS2_3(x) \ + (((x) >> S_SLEW_CTL_SEL_BITS2_3) & M_SLEW_CTL_SEL_BITS2_3) + +#define S_SLEW_CTL_SEL_BITS4_5 10 +#define M_SLEW_CTL_SEL_BITS4_5 0x3U +#define V_SLEW_CTL_SEL_BITS4_5(x) ((x) << S_SLEW_CTL_SEL_BITS4_5) +#define G_SLEW_CTL_SEL_BITS4_5(x) \ + (((x) >> S_SLEW_CTL_SEL_BITS4_5) & M_SLEW_CTL_SEL_BITS4_5) + +#define S_SLEW_CTL_SEL_BITS6_7 8 +#define M_SLEW_CTL_SEL_BITS6_7 0x3U +#define V_SLEW_CTL_SEL_BITS6_7(x) ((x) << S_SLEW_CTL_SEL_BITS6_7) +#define G_SLEW_CTL_SEL_BITS6_7(x) \ + (((x) >> S_SLEW_CTL_SEL_BITS6_7) & M_SLEW_CTL_SEL_BITS6_7) + +#define S_SLEW_CTL_SEL_BITS8_9 6 +#define M_SLEW_CTL_SEL_BITS8_9 0x3U +#define V_SLEW_CTL_SEL_BITS8_9(x) ((x) << S_SLEW_CTL_SEL_BITS8_9) +#define G_SLEW_CTL_SEL_BITS8_9(x) \ + (((x) >> S_SLEW_CTL_SEL_BITS8_9) & M_SLEW_CTL_SEL_BITS8_9) + +#define S_SLEW_CTL_SEL_BITS10_11 4 +#define M_SLEW_CTL_SEL_BITS10_11 0x3U +#define V_SLEW_CTL_SEL_BITS10_11(x) ((x) << S_SLEW_CTL_SEL_BITS10_11) +#define G_SLEW_CTL_SEL_BITS10_11(x) \ + (((x) >> S_SLEW_CTL_SEL_BITS10_11) & M_SLEW_CTL_SEL_BITS10_11) + +#define S_SLEW_CTL_SEL_BITS12_13 2 +#define M_SLEW_CTL_SEL_BITS12_13 0x3U +#define V_SLEW_CTL_SEL_BITS12_13(x) ((x) << S_SLEW_CTL_SEL_BITS12_13) +#define G_SLEW_CTL_SEL_BITS12_13(x) \ + (((x) >> S_SLEW_CTL_SEL_BITS12_13) & M_SLEW_CTL_SEL_BITS12_13) + +#define S_SLEW_CTL_SEL_BITS14_15 0 +#define M_SLEW_CTL_SEL_BITS14_15 0x3U +#define V_SLEW_CTL_SEL_BITS14_15(x) ((x) << S_SLEW_CTL_SEL_BITS14_15) +#define G_SLEW_CTL_SEL_BITS14_15(x) \ + (((x) >> S_SLEW_CTL_SEL_BITS14_15) & M_SLEW_CTL_SEL_BITS14_15) + +#define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x450ac +#define A_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x450b0 + +#define S_ADR_LANE_0_11_PD 4 +#define M_ADR_LANE_0_11_PD 0xfffU +#define V_ADR_LANE_0_11_PD(x) ((x) << S_ADR_LANE_0_11_PD) +#define G_ADR_LANE_0_11_PD(x) (((x) >> S_ADR_LANE_0_11_PD) & M_ADR_LANE_0_11_PD) + +#define S_ADR_LANE_12_15_PD 0 +#define M_ADR_LANE_12_15_PD 0xfU +#define V_ADR_LANE_12_15_PD(x) ((x) << S_ADR_LANE_12_15_PD) +#define G_ADR_LANE_12_15_PD(x) \ + (((x) >> S_ADR_LANE_12_15_PD) & M_ADR_LANE_12_15_PD) + +#define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 0x460c0 + +#define S_PLL_TUNE_0_2 13 +#define M_PLL_TUNE_0_2 0x7U +#define V_PLL_TUNE_0_2(x) ((x) << S_PLL_TUNE_0_2) +#define G_PLL_TUNE_0_2(x) (((x) >> S_PLL_TUNE_0_2) & M_PLL_TUNE_0_2) + +#define S_PLL_TUNECP_0_2 10 +#define M_PLL_TUNECP_0_2 0x7U +#define V_PLL_TUNECP_0_2(x) ((x) << S_PLL_TUNECP_0_2) +#define G_PLL_TUNECP_0_2(x) (((x) >> S_PLL_TUNECP_0_2) & M_PLL_TUNECP_0_2) + +#define S_PLL_TUNEF_0_5 4 +#define M_PLL_TUNEF_0_5 0x3fU +#define V_PLL_TUNEF_0_5(x) ((x) << S_PLL_TUNEF_0_5) +#define G_PLL_TUNEF_0_5(x) (((x) >> S_PLL_TUNEF_0_5) & M_PLL_TUNEF_0_5) + +#define S_PLL_TUNEVCO_0_1 2 +#define M_PLL_TUNEVCO_0_1 0x3U +#define V_PLL_TUNEVCO_0_1(x) ((x) << S_PLL_TUNEVCO_0_1) +#define G_PLL_TUNEVCO_0_1(x) (((x) >> S_PLL_TUNEVCO_0_1) & M_PLL_TUNEVCO_0_1) + +#define S_PLL_PLLXTR_0_1 0 +#define M_PLL_PLLXTR_0_1 0x3U +#define V_PLL_PLLXTR_0_1(x) ((x) << S_PLL_PLLXTR_0_1) +#define G_PLL_PLLXTR_0_1(x) (((x) >> S_PLL_PLLXTR_0_1) & M_PLL_PLLXTR_0_1) + +#define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 0x460c4 + +#define S_PLL_TUNETDIV_0_2 13 +#define M_PLL_TUNETDIV_0_2 0x7U +#define V_PLL_TUNETDIV_0_2(x) ((x) << S_PLL_TUNETDIV_0_2) +#define G_PLL_TUNETDIV_0_2(x) (((x) >> S_PLL_TUNETDIV_0_2) & M_PLL_TUNETDIV_0_2) + +#define S_PLL_TUNEMDIV_0_1 11 +#define M_PLL_TUNEMDIV_0_1 0x3U +#define V_PLL_TUNEMDIV_0_1(x) ((x) << S_PLL_TUNEMDIV_0_1) +#define G_PLL_TUNEMDIV_0_1(x) (((x) >> S_PLL_TUNEMDIV_0_1) & M_PLL_TUNEMDIV_0_1) + +#define S_PLL_TUNEATST 10 +#define V_PLL_TUNEATST(x) ((x) << S_PLL_TUNEATST) +#define F_PLL_TUNEATST V_PLL_TUNEATST(1U) + +#define S_VREG_RANGE_0_1 8 +#define M_VREG_RANGE_0_1 0x3U +#define V_VREG_RANGE_0_1(x) ((x) << S_VREG_RANGE_0_1) +#define G_VREG_RANGE_0_1(x) (((x) >> S_VREG_RANGE_0_1) & M_VREG_RANGE_0_1) + +#define S_VREG_VREGSPARE 7 +#define V_VREG_VREGSPARE(x) ((x) << S_VREG_VREGSPARE) +#define F_VREG_VREGSPARE V_VREG_VREGSPARE(1U) + +#define S_VREG_VCCTUNE_0_1 5 +#define M_VREG_VCCTUNE_0_1 0x3U +#define V_VREG_VCCTUNE_0_1(x) ((x) << S_VREG_VCCTUNE_0_1) +#define G_VREG_VCCTUNE_0_1(x) (((x) >> S_VREG_VCCTUNE_0_1) & M_VREG_VCCTUNE_0_1) + +#define S_INTERP_SIG_SLEW_0_3 1 +#define M_INTERP_SIG_SLEW_0_3 0xfU +#define V_INTERP_SIG_SLEW_0_3(x) ((x) << S_INTERP_SIG_SLEW_0_3) +#define G_INTERP_SIG_SLEW_0_3(x) \ + (((x) >> S_INTERP_SIG_SLEW_0_3) & M_INTERP_SIG_SLEW_0_3) + +#define S_ANALOG_WRAPON 0 +#define V_ANALOG_WRAPON(x) ((x) << S_ANALOG_WRAPON) +#define F_ANALOG_WRAPON V_ANALOG_WRAPON(1U) + +#define A_MC_DDRPHY_ADR_SYSCLK_CNTL_PR 0x460c8 + +#define S_SYSCLK_ENABLE 15 +#define V_SYSCLK_ENABLE(x) ((x) << S_SYSCLK_ENABLE) +#define F_SYSCLK_ENABLE V_SYSCLK_ENABLE(1U) + +#define S_SYSCLK_ROT_OVERRIDE 8 +#define M_SYSCLK_ROT_OVERRIDE 0x7fU +#define V_SYSCLK_ROT_OVERRIDE(x) ((x) << S_SYSCLK_ROT_OVERRIDE) +#define G_SYSCLK_ROT_OVERRIDE(x) \ + (((x) >> S_SYSCLK_ROT_OVERRIDE) & M_SYSCLK_ROT_OVERRIDE) + +#define S_SYSCLK_ROT_OVERRIDE_EN 7 +#define V_SYSCLK_ROT_OVERRIDE_EN(x) ((x) << S_SYSCLK_ROT_OVERRIDE_EN) +#define F_SYSCLK_ROT_OVERRIDE_EN V_SYSCLK_ROT_OVERRIDE_EN(1U) + +#define S_SYSCLK_PHASE_ALIGN_RESE 6 +#define V_SYSCLK_PHASE_ALIGN_RESE(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESE) +#define F_SYSCLK_PHASE_ALIGN_RESE V_SYSCLK_PHASE_ALIGN_RESE(1U) + +#define S_SYSCLK_PHASE_CNTL_EN 5 +#define V_SYSCLK_PHASE_CNTL_EN(x) ((x) << S_SYSCLK_PHASE_CNTL_EN) +#define F_SYSCLK_PHASE_CNTL_EN V_SYSCLK_PHASE_CNTL_EN(1U) + +#define S_SYSCLK_PHASE_DEFAULT_EN 4 +#define V_SYSCLK_PHASE_DEFAULT_EN(x) ((x) << S_SYSCLK_PHASE_DEFAULT_EN) +#define F_SYSCLK_PHASE_DEFAULT_EN V_SYSCLK_PHASE_DEFAULT_EN(1U) + +#define S_SYSCLK_POS_EDGE_ALIGN 3 +#define V_SYSCLK_POS_EDGE_ALIGN(x) ((x) << S_SYSCLK_POS_EDGE_ALIGN) +#define F_SYSCLK_POS_EDGE_ALIGN V_SYSCLK_POS_EDGE_ALIGN(1U) + +#define S_CONTINUOUS_UPDATE 2 +#define V_CONTINUOUS_UPDATE(x) ((x) << S_CONTINUOUS_UPDATE) +#define F_CONTINUOUS_UPDATE V_CONTINUOUS_UPDATE(1U) + +#define S_CE0DLTVCC 0 +#define M_CE0DLTVCC 0x3U +#define V_CE0DLTVCC(x) ((x) << S_CE0DLTVCC) +#define G_CE0DLTVCC(x) (((x) >> S_CE0DLTVCC) & M_CE0DLTVCC) + +#define A_MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc + +#define S_TSYS_WRCLK 8 +#define M_TSYS_WRCLK 0x7fU +#define V_TSYS_WRCLK(x) ((x) << S_TSYS_WRCLK) +#define G_TSYS_WRCLK(x) (((x) >> S_TSYS_WRCLK) & M_TSYS_WRCLK) + +#define A_MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO 0x460d0 + +#define S_SLEW_LATE_SAMPLE 15 +#define V_SLEW_LATE_SAMPLE(x) ((x) << S_SLEW_LATE_SAMPLE) +#define F_SLEW_LATE_SAMPLE V_SLEW_LATE_SAMPLE(1U) + +#define S_SYSCLK_ROT 8 +#define M_SYSCLK_ROT 0x7fU +#define V_SYSCLK_ROT(x) ((x) << S_SYSCLK_ROT) +#define G_SYSCLK_ROT(x) (((x) >> S_SYSCLK_ROT) & M_SYSCLK_ROT) + +#define S_BB_LOCK 7 +#define V_BB_LOCK(x) ((x) << S_BB_LOCK) +#define F_BB_LOCK V_BB_LOCK(1U) + +#define S_SLEW_EARLY_SAMPLE 6 +#define V_SLEW_EARLY_SAMPLE(x) ((x) << S_SLEW_EARLY_SAMPLE) +#define F_SLEW_EARLY_SAMPLE V_SLEW_EARLY_SAMPLE(1U) + +#define S_SLEW_DONE_STATUS 4 +#define M_SLEW_DONE_STATUS 0x3U +#define V_SLEW_DONE_STATUS(x) ((x) << S_SLEW_DONE_STATUS) +#define G_SLEW_DONE_STATUS(x) (((x) >> S_SLEW_DONE_STATUS) & M_SLEW_DONE_STATUS) + +#define S_SLEW_CNTL 0 +#define M_SLEW_CNTL 0xfU +#define V_SLEW_CNTL(x) ((x) << S_SLEW_CNTL) +#define G_SLEW_CNTL(x) (((x) >> S_SLEW_CNTL) & M_SLEW_CNTL) + +#define A_MC_DDRPHY_ADR_GMTEST_ATEST_CNTL 0x460d4 + +#define S_FLUSH 15 +#define V_FLUSH(x) ((x) << S_FLUSH) +#define F_FLUSH V_FLUSH(1U) + +#define S_GIANT_MUX_TEST_EN 14 +#define V_GIANT_MUX_TEST_EN(x) ((x) << S_GIANT_MUX_TEST_EN) +#define F_GIANT_MUX_TEST_EN V_GIANT_MUX_TEST_EN(1U) + +#define S_GIANT_MUX_TEST_VAL 13 +#define V_GIANT_MUX_TEST_VAL(x) ((x) << S_GIANT_MUX_TEST_VAL) +#define F_GIANT_MUX_TEST_VAL V_GIANT_MUX_TEST_VAL(1U) + +#define S_HS_PROBE_A_SEL_ 8 +#define M_HS_PROBE_A_SEL_ 0xfU +#define V_HS_PROBE_A_SEL_(x) ((x) << S_HS_PROBE_A_SEL_) +#define G_HS_PROBE_A_SEL_(x) (((x) >> S_HS_PROBE_A_SEL_) & M_HS_PROBE_A_SEL_) + +#define S_HS_PROBE_B_SEL_ 4 +#define M_HS_PROBE_B_SEL_ 0xfU +#define V_HS_PROBE_B_SEL_(x) ((x) << S_HS_PROBE_B_SEL_) +#define G_HS_PROBE_B_SEL_(x) (((x) >> S_HS_PROBE_B_SEL_) & M_HS_PROBE_B_SEL_) + +#define S_ATEST1CTL0 3 +#define V_ATEST1CTL0(x) ((x) << S_ATEST1CTL0) +#define F_ATEST1CTL0 V_ATEST1CTL0(1U) + +#define S_ATEST1CTL1 2 +#define V_ATEST1CTL1(x) ((x) << S_ATEST1CTL1) +#define F_ATEST1CTL1 V_ATEST1CTL1(1U) + +#define S_ATEST1CTL2 1 +#define V_ATEST1CTL2(x) ((x) << S_ATEST1CTL2) +#define F_ATEST1CTL2 V_ATEST1CTL2(1U) + +#define S_ATEST1CTL3 0 +#define V_ATEST1CTL3(x) ((x) << S_ATEST1CTL3) +#define F_ATEST1CTL3 V_ATEST1CTL3(1U) + +#define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 0x460d8 + +#define S_GIANT_MUX_TEST_RESULTS 0 +#define M_GIANT_MUX_TEST_RESULTS 0xffffU +#define V_GIANT_MUX_TEST_RESULTS(x) ((x) << S_GIANT_MUX_TEST_RESULTS) +#define G_GIANT_MUX_TEST_RESULTS(x) \ + (((x) >> S_GIANT_MUX_TEST_RESULTS) & M_GIANT_MUX_TEST_RESULTS) + +#define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 0x460dc +#define A_MC_DDRPHY_ADR_POWERDOWN_1 0x460e0 + +#define S_MASTER_PD_CNTL 15 +#define V_MASTER_PD_CNTL(x) ((x) << S_MASTER_PD_CNTL) +#define F_MASTER_PD_CNTL V_MASTER_PD_CNTL(1U) + +#define S_ANALOG_INPUT_STAB2 14 +#define V_ANALOG_INPUT_STAB2(x) ((x) << S_ANALOG_INPUT_STAB2) +#define F_ANALOG_INPUT_STAB2 V_ANALOG_INPUT_STAB2(1U) + +#define S_ANALOG_INPUT_STAB1 8 +#define V_ANALOG_INPUT_STAB1(x) ((x) << S_ANALOG_INPUT_STAB1) +#define F_ANALOG_INPUT_STAB1 V_ANALOG_INPUT_STAB1(1U) + +#define S_SYSCLK_CLK_GATE 6 +#define M_SYSCLK_CLK_GATE 0x3U +#define V_SYSCLK_CLK_GATE(x) ((x) << S_SYSCLK_CLK_GATE) +#define G_SYSCLK_CLK_GATE(x) (((x) >> S_SYSCLK_CLK_GATE) & M_SYSCLK_CLK_GATE) + +#define S_WR_FIFO_STAB 5 +#define V_WR_FIFO_STAB(x) ((x) << S_WR_FIFO_STAB) +#define F_WR_FIFO_STAB V_WR_FIFO_STAB(1U) + +#define S_ADR_RX_PD 4 +#define V_ADR_RX_PD(x) ((x) << S_ADR_RX_PD) +#define F_ADR_RX_PD V_ADR_RX_PD(1U) + +#define S_TX_TRISTATE_CNTL 1 +#define V_TX_TRISTATE_CNTL(x) ((x) << S_TX_TRISTATE_CNTL) +#define F_TX_TRISTATE_CNTL V_TX_TRISTATE_CNTL(1U) + +#define S_DVCC_REG_PD 0 +#define V_DVCC_REG_PD(x) ((x) << S_DVCC_REG_PD) +#define F_DVCC_REG_PD V_DVCC_REG_PD(1U) + +#define A_MC_DDRPHY_ADR_SLEW_CAL_CNTL 0x460e4 + +#define S_SLEW_CAL_ENABLE 15 +#define V_SLEW_CAL_ENABLE(x) ((x) << S_SLEW_CAL_ENABLE) +#define F_SLEW_CAL_ENABLE V_SLEW_CAL_ENABLE(1U) + +#define S_SLEW_CAL_START 14 +#define V_SLEW_CAL_START(x) ((x) << S_SLEW_CAL_START) +#define F_SLEW_CAL_START V_SLEW_CAL_START(1U) + +#define S_SLEW_CAL_OVERRIDE_EN 12 +#define V_SLEW_CAL_OVERRIDE_EN(x) ((x) << S_SLEW_CAL_OVERRIDE_EN) +#define F_SLEW_CAL_OVERRIDE_EN V_SLEW_CAL_OVERRIDE_EN(1U) + +#define S_SLEW_CAL_OVERRIDE 8 +#define M_SLEW_CAL_OVERRIDE 0xfU +#define V_SLEW_CAL_OVERRIDE(x) ((x) << S_SLEW_CAL_OVERRIDE) +#define G_SLEW_CAL_OVERRIDE(x) \ + (((x) >> S_SLEW_CAL_OVERRIDE) & M_SLEW_CAL_OVERRIDE) + +#define S_SLEW_TARGET_PR_OFFSET 0 +#define M_SLEW_TARGET_PR_OFFSET 0x1fU +#define V_SLEW_TARGET_PR_OFFSET(x) ((x) << S_SLEW_TARGET_PR_OFFSET) +#define G_SLEW_TARGET_PR_OFFSET(x) \ + (((x) >> S_SLEW_TARGET_PR_OFFSET) & M_SLEW_TARGET_PR_OFFSET) + +#define A_MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS 0x47000 + +#define S_DP18_PLL_LOCK 1 +#define M_DP18_PLL_LOCK 0x7fffU +#define V_DP18_PLL_LOCK(x) ((x) << S_DP18_PLL_LOCK) +#define G_DP18_PLL_LOCK(x) (((x) >> S_DP18_PLL_LOCK) & M_DP18_PLL_LOCK) + +#define A_MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS 0x47004 + +#define S_AD32S_PLL_LOCK 14 +#define M_AD32S_PLL_LOCK 0x3U +#define V_AD32S_PLL_LOCK(x) ((x) << S_AD32S_PLL_LOCK) +#define G_AD32S_PLL_LOCK(x) (((x) >> S_AD32S_PLL_LOCK) & M_AD32S_PLL_LOCK) + +#define A_MC_DDRPHY_PC_RANK_PAIR0 0x47008 + +#define S_RANK_PAIR0_PRI 13 +#define M_RANK_PAIR0_PRI 0x7U +#define V_RANK_PAIR0_PRI(x) ((x) << S_RANK_PAIR0_PRI) +#define G_RANK_PAIR0_PRI(x) (((x) >> S_RANK_PAIR0_PRI) & M_RANK_PAIR0_PRI) + +#define S_RANK_PAIR0_PRI_V 12 +#define V_RANK_PAIR0_PRI_V(x) ((x) << S_RANK_PAIR0_PRI_V) +#define F_RANK_PAIR0_PRI_V V_RANK_PAIR0_PRI_V(1U) + +#define S_RANK_PAIR0_SEC 9 +#define M_RANK_PAIR0_SEC 0x7U +#define V_RANK_PAIR0_SEC(x) ((x) << S_RANK_PAIR0_SEC) +#define G_RANK_PAIR0_SEC(x) (((x) >> S_RANK_PAIR0_SEC) & M_RANK_PAIR0_SEC) + +#define S_RANK_PAIR0_SEC_V 8 +#define V_RANK_PAIR0_SEC_V(x) ((x) << S_RANK_PAIR0_SEC_V) +#define F_RANK_PAIR0_SEC_V V_RANK_PAIR0_SEC_V(1U) + +#define S_RANK_PAIR1_PRI 5 +#define M_RANK_PAIR1_PRI 0x7U +#define V_RANK_PAIR1_PRI(x) ((x) << S_RANK_PAIR1_PRI) +#define G_RANK_PAIR1_PRI(x) (((x) >> S_RANK_PAIR1_PRI) & M_RANK_PAIR1_PRI) + +#define S_RANK_PAIR1_PRI_V 4 +#define V_RANK_PAIR1_PRI_V(x) ((x) << S_RANK_PAIR1_PRI_V) +#define F_RANK_PAIR1_PRI_V V_RANK_PAIR1_PRI_V(1U) + +#define S_RANK_PAIR1_SEC 1 +#define M_RANK_PAIR1_SEC 0x7U +#define V_RANK_PAIR1_SEC(x) ((x) << S_RANK_PAIR1_SEC) +#define G_RANK_PAIR1_SEC(x) (((x) >> S_RANK_PAIR1_SEC) & M_RANK_PAIR1_SEC) + +#define S_RANK_PAIR1_SEC_V 0 +#define V_RANK_PAIR1_SEC_V(x) ((x) << S_RANK_PAIR1_SEC_V) +#define F_RANK_PAIR1_SEC_V V_RANK_PAIR1_SEC_V(1U) + +#define A_MC_DDRPHY_PC_RANK_PAIR1 0x4700c + +#define S_RANK_PAIR2_PRI 13 +#define M_RANK_PAIR2_PRI 0x7U +#define V_RANK_PAIR2_PRI(x) ((x) << S_RANK_PAIR2_PRI) +#define G_RANK_PAIR2_PRI(x) (((x) >> S_RANK_PAIR2_PRI) & M_RANK_PAIR2_PRI) + +#define S_RANK_PAIR2_PRI_V 12 +#define V_RANK_PAIR2_PRI_V(x) ((x) << S_RANK_PAIR2_PRI_V) +#define F_RANK_PAIR2_PRI_V V_RANK_PAIR2_PRI_V(1U) + +#define S_RANK_PAIR2_SEC 9 +#define M_RANK_PAIR2_SEC 0x7U +#define V_RANK_PAIR2_SEC(x) ((x) << S_RANK_PAIR2_SEC) +#define G_RANK_PAIR2_SEC(x) (((x) >> S_RANK_PAIR2_SEC) & M_RANK_PAIR2_SEC) + +#define S_RANK_PAIR2_SEC_V 8 +#define V_RANK_PAIR2_SEC_V(x) ((x) << S_RANK_PAIR2_SEC_V) +#define F_RANK_PAIR2_SEC_V V_RANK_PAIR2_SEC_V(1U) + +#define S_RANK_PAIR3_PRI 5 +#define M_RANK_PAIR3_PRI 0x7U +#define V_RANK_PAIR3_PRI(x) ((x) << S_RANK_PAIR3_PRI) +#define G_RANK_PAIR3_PRI(x) (((x) >> S_RANK_PAIR3_PRI) & M_RANK_PAIR3_PRI) + +#define S_RANK_PAIR3_PRI_V 4 +#define V_RANK_PAIR3_PRI_V(x) ((x) << S_RANK_PAIR3_PRI_V) +#define F_RANK_PAIR3_PRI_V V_RANK_PAIR3_PRI_V(1U) + +#define S_RANK_PAIR3_SEC 1 +#define M_RANK_PAIR3_SEC 0x7U +#define V_RANK_PAIR3_SEC(x) ((x) << S_RANK_PAIR3_SEC) +#define G_RANK_PAIR3_SEC(x) (((x) >> S_RANK_PAIR3_SEC) & M_RANK_PAIR3_SEC) + +#define S_RANK_PAIR3_SEC_V 0 +#define V_RANK_PAIR3_SEC_V(x) ((x) << S_RANK_PAIR3_SEC_V) +#define F_RANK_PAIR3_SEC_V V_RANK_PAIR3_SEC_V(1U) + +#define A_MC_DDRPHY_PC_BASE_CNTR0 0x47010 + +#define S_PERIODIC_BASE_CNTR0 0 +#define M_PERIODIC_BASE_CNTR0 0xffffU +#define V_PERIODIC_BASE_CNTR0(x) ((x) << S_PERIODIC_BASE_CNTR0) +#define G_PERIODIC_BASE_CNTR0(x) \ + (((x) >> S_PERIODIC_BASE_CNTR0) & M_PERIODIC_BASE_CNTR0) + +#define A_MC_DDRPHY_PC_RELOAD_VALUE0 0x47014 + +#define S_PERIODIC_CAL_REQ_EN 15 +#define V_PERIODIC_CAL_REQ_EN(x) ((x) << S_PERIODIC_CAL_REQ_EN) +#define F_PERIODIC_CAL_REQ_EN V_PERIODIC_CAL_REQ_EN(1U) + +#define S_PERIODIC_RELOAD_VALUE0 0 +#define M_PERIODIC_RELOAD_VALUE0 0x7fffU +#define V_PERIODIC_RELOAD_VALUE0(x) ((x) << S_PERIODIC_RELOAD_VALUE0) +#define G_PERIODIC_RELOAD_VALUE0(x) \ + (((x) >> S_PERIODIC_RELOAD_VALUE0) & M_PERIODIC_RELOAD_VALUE0) + +#define A_MC_DDRPHY_PC_BASE_CNTR1 0x47018 + +#define S_PERIODIC_BASE_CNTR1 0 +#define M_PERIODIC_BASE_CNTR1 0xffffU +#define V_PERIODIC_BASE_CNTR1(x) ((x) << S_PERIODIC_BASE_CNTR1) +#define G_PERIODIC_BASE_CNTR1(x) \ + (((x) >> S_PERIODIC_BASE_CNTR1) & M_PERIODIC_BASE_CNTR1) + +#define A_MC_DDRPHY_PC_CAL_TIMER 0x4701c + +#define S_PERIODIC_CAL_TIMER 0 +#define M_PERIODIC_CAL_TIMER 0xffffU +#define V_PERIODIC_CAL_TIMER(x) ((x) << S_PERIODIC_CAL_TIMER) +#define G_PERIODIC_CAL_TIMER(x) \ + (((x) >> S_PERIODIC_CAL_TIMER) & M_PERIODIC_CAL_TIMER) + +#define A_MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE 0x47020 + +#define S_PERIODIC_TIMER_RELOAD_VALUE 0 +#define M_PERIODIC_TIMER_RELOAD_VALUE 0xffffU +#define V_PERIODIC_TIMER_RELOAD_VALUE(x) ((x) << S_PERIODIC_TIMER_RELOAD_VALUE) +#define G_PERIODIC_TIMER_RELOAD_VALUE(x) \ + (((x) >> S_PERIODIC_TIMER_RELOAD_VALUE) & M_PERIODIC_TIMER_RELOAD_VALUE) + +#define A_MC_DDRPHY_PC_ZCAL_TIMER 0x47024 + +#define S_PERIODIC_ZCAL_TIMER 0 +#define M_PERIODIC_ZCAL_TIMER 0xffffU +#define V_PERIODIC_ZCAL_TIMER(x) ((x) << S_PERIODIC_ZCAL_TIMER) +#define G_PERIODIC_ZCAL_TIMER(x) \ + (((x) >> S_PERIODIC_ZCAL_TIMER) & M_PERIODIC_ZCAL_TIMER) + +#define A_MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE 0x47028 +#define A_MC_DDRPHY_PC_PER_CAL_CONFIG 0x4702c + +#define S_PER_ENA_RANK_PAIR 12 +#define M_PER_ENA_RANK_PAIR 0xfU +#define V_PER_ENA_RANK_PAIR(x) ((x) << S_PER_ENA_RANK_PAIR) +#define G_PER_ENA_RANK_PAIR(x) \ + (((x) >> S_PER_ENA_RANK_PAIR) & M_PER_ENA_RANK_PAIR) + +#define S_PER_ENA_ZCAL 11 +#define V_PER_ENA_ZCAL(x) ((x) << S_PER_ENA_ZCAL) +#define F_PER_ENA_ZCAL V_PER_ENA_ZCAL(1U) + +#define S_PER_ENA_SYSCLK_ALIGN 10 +#define V_PER_ENA_SYSCLK_ALIGN(x) ((x) << S_PER_ENA_SYSCLK_ALIGN) +#define F_PER_ENA_SYSCLK_ALIGN V_PER_ENA_SYSCLK_ALIGN(1U) + +#define S_ENA_PER_RDCLK_ALIGN 9 +#define V_ENA_PER_RDCLK_ALIGN(x) ((x) << S_ENA_PER_RDCLK_ALIGN) +#define F_ENA_PER_RDCLK_ALIGN V_ENA_PER_RDCLK_ALIGN(1U) + +#define S_ENA_PER_DQS_ALIGN 8 +#define V_ENA_PER_DQS_ALIGN(x) ((x) << S_ENA_PER_DQS_ALIGN) +#define F_ENA_PER_DQS_ALIGN V_ENA_PER_DQS_ALIGN(1U) + +#define S_ENA_PER_READ_CTR 7 +#define V_ENA_PER_READ_CTR(x) ((x) << S_ENA_PER_READ_CTR) +#define F_ENA_PER_READ_CTR V_ENA_PER_READ_CTR(1U) + +#define S_PER_NEXT_RANK_PAIR 5 +#define M_PER_NEXT_RANK_PAIR 0x3U +#define V_PER_NEXT_RANK_PAIR(x) ((x) << S_PER_NEXT_RANK_PAIR) +#define G_PER_NEXT_RANK_PAIR(x) \ + (((x) >> S_PER_NEXT_RANK_PAIR) & M_PER_NEXT_RANK_PAIR) + +#define S_FAST_SIM_PER_CNTR 4 +#define V_FAST_SIM_PER_CNTR(x) ((x) << S_FAST_SIM_PER_CNTR) +#define F_FAST_SIM_PER_CNTR V_FAST_SIM_PER_CNTR(1U) + +#define S_START_INIT_CAL 3 +#define V_START_INIT_CAL(x) ((x) << S_START_INIT_CAL) +#define F_START_INIT_CAL V_START_INIT_CAL(1U) + +#define S_START_PER_CAL 2 +#define V_START_PER_CAL(x) ((x) << S_START_PER_CAL) +#define F_START_PER_CAL V_START_PER_CAL(1U) + +#define A_MC_DDRPHY_PC_CONFIG0 0x47030 + +#define S_PROTOCOL_DDR 12 +#define M_PROTOCOL_DDR 0xfU +#define V_PROTOCOL_DDR(x) ((x) << S_PROTOCOL_DDR) +#define G_PROTOCOL_DDR(x) (((x) >> S_PROTOCOL_DDR) & M_PROTOCOL_DDR) + +#define S_DATA_MUX4_1MODE 11 +#define V_DATA_MUX4_1MODE(x) ((x) << S_DATA_MUX4_1MODE) +#define F_DATA_MUX4_1MODE V_DATA_MUX4_1MODE(1U) + +#define S_DDR4_CMD_SIG_REDUCTION 9 +#define V_DDR4_CMD_SIG_REDUCTION(x) ((x) << S_DDR4_CMD_SIG_REDUCTION) +#define F_DDR4_CMD_SIG_REDUCTION V_DDR4_CMD_SIG_REDUCTION(1U) + +#define S_SYSCLK_2X_MEMINTCLKO 8 +#define V_SYSCLK_2X_MEMINTCLKO(x) ((x) << S_SYSCLK_2X_MEMINTCLKO) +#define F_SYSCLK_2X_MEMINTCLKO V_SYSCLK_2X_MEMINTCLKO(1U) + +#define S_RANK_OVERRIDE 7 +#define V_RANK_OVERRIDE(x) ((x) << S_RANK_OVERRIDE) +#define F_RANK_OVERRIDE V_RANK_OVERRIDE(1U) + +#define S_RANK_OVERRIDE_VALUE 4 +#define M_RANK_OVERRIDE_VALUE 0x7U +#define V_RANK_OVERRIDE_VALUE(x) ((x) << S_RANK_OVERRIDE_VALUE) +#define G_RANK_OVERRIDE_VALUE(x) \ + (((x) >> S_RANK_OVERRIDE_VALUE) & M_RANK_OVERRIDE_VALUE) + +#define S_LOW_LATENCY 3 +#define V_LOW_LATENCY(x) ((x) << S_LOW_LATENCY) +#define F_LOW_LATENCY V_LOW_LATENCY(1U) + +#define S_DDR4_BANK_REFRESH 2 +#define V_DDR4_BANK_REFRESH(x) ((x) << S_DDR4_BANK_REFRESH) +#define F_DDR4_BANK_REFRESH V_DDR4_BANK_REFRESH(1U) + +#define S_DDR4_VLEVEL_BANK_GROUP 1 +#define V_DDR4_VLEVEL_BANK_GROUP(x) ((x) << S_DDR4_VLEVEL_BANK_GROUP) +#define F_DDR4_VLEVEL_BANK_GROUP V_DDR4_VLEVEL_BANK_GROUP(1U) + +#define A_MC_DDRPHY_PC_CONFIG1 0x47034 + +#define S_WRITE_LATENCY_OFFSET 12 +#define M_WRITE_LATENCY_OFFSET 0xfU +#define V_WRITE_LATENCY_OFFSET(x) ((x) << S_WRITE_LATENCY_OFFSET) +#define G_WRITE_LATENCY_OFFSET(x) \ + (((x) >> S_WRITE_LATENCY_OFFSET) & M_WRITE_LATENCY_OFFSET) + +#define S_READ_LATENCY_OFFSET 8 +#define M_READ_LATENCY_OFFSET 0xfU +#define V_READ_LATENCY_OFFSET(x) ((x) << S_READ_LATENCY_OFFSET) +#define G_READ_LATENCY_OFFSET(x) \ + (((x) >> S_READ_LATENCY_OFFSET) & M_READ_LATENCY_OFFSET) + +#define S_MEMCTL_CIC_FAST 7 +#define V_MEMCTL_CIC_FAST(x) ((x) << S_MEMCTL_CIC_FAST) +#define F_MEMCTL_CIC_FAST V_MEMCTL_CIC_FAST(1U) + +#define S_MEMCTL_CTRN_IGNORE 6 +#define V_MEMCTL_CTRN_IGNORE(x) ((x) << S_MEMCTL_CTRN_IGNORE) +#define F_MEMCTL_CTRN_IGNORE V_MEMCTL_CTRN_IGNORE(1U) + +#define S_DISABLE_MEMCTL_CAL 5 +#define V_DISABLE_MEMCTL_CAL(x) ((x) << S_DISABLE_MEMCTL_CAL) +#define F_DISABLE_MEMCTL_CAL V_DISABLE_MEMCTL_CAL(1U) + +#define A_MC_DDRPHY_PC_RESETS 0x47038 + +#define S_PLL_RESET 15 +#define V_PLL_RESET(x) ((x) << S_PLL_RESET) +#define F_PLL_RESET V_PLL_RESET(1U) + +#define S_SYSCLK_RESET 14 +#define V_SYSCLK_RESET(x) ((x) << S_SYSCLK_RESET) +#define F_SYSCLK_RESET V_SYSCLK_RESET(1U) + +#define A_MC_DDRPHY_PC_PER_ZCAL_CONFIG 0x4703c + +#define S_PER_ZCAL_ENA_RANK 8 +#define M_PER_ZCAL_ENA_RANK 0xffU +#define V_PER_ZCAL_ENA_RANK(x) ((x) << S_PER_ZCAL_ENA_RANK) +#define G_PER_ZCAL_ENA_RANK(x) \ + (((x) >> S_PER_ZCAL_ENA_RANK) & M_PER_ZCAL_ENA_RANK) + +#define S_PER_ZCAL_NEXT_RANK 5 +#define M_PER_ZCAL_NEXT_RANK 0x7U +#define V_PER_ZCAL_NEXT_RANK(x) ((x) << S_PER_ZCAL_NEXT_RANK) +#define G_PER_ZCAL_NEXT_RANK(x) \ + (((x) >> S_PER_ZCAL_NEXT_RANK) & M_PER_ZCAL_NEXT_RANK) + +#define S_START_PER_ZCAL 4 +#define V_START_PER_ZCAL(x) ((x) << S_START_PER_ZCAL) +#define F_START_PER_ZCAL V_START_PER_ZCAL(1U) + +#define A_MC_DDRPHY_PC_RANK_GROUP 0x47044 + +#define S_ADDR_MIRROR_RP0_PRI 15 +#define V_ADDR_MIRROR_RP0_PRI(x) ((x) << S_ADDR_MIRROR_RP0_PRI) +#define F_ADDR_MIRROR_RP0_PRI V_ADDR_MIRROR_RP0_PRI(1U) + +#define S_ADDR_MIRROR_RP0_SEC 14 +#define V_ADDR_MIRROR_RP0_SEC(x) ((x) << S_ADDR_MIRROR_RP0_SEC) +#define F_ADDR_MIRROR_RP0_SEC V_ADDR_MIRROR_RP0_SEC(1U) + +#define S_ADDR_MIRROR_RP1_PRI 13 +#define V_ADDR_MIRROR_RP1_PRI(x) ((x) << S_ADDR_MIRROR_RP1_PRI) +#define F_ADDR_MIRROR_RP1_PRI V_ADDR_MIRROR_RP1_PRI(1U) + +#define S_ADDR_MIRROR_RP1_SEC 12 +#define V_ADDR_MIRROR_RP1_SEC(x) ((x) << S_ADDR_MIRROR_RP1_SEC) +#define F_ADDR_MIRROR_RP1_SEC V_ADDR_MIRROR_RP1_SEC(1U) + +#define S_ADDR_MIRROR_RP2_PRI 11 +#define V_ADDR_MIRROR_RP2_PRI(x) ((x) << S_ADDR_MIRROR_RP2_PRI) +#define F_ADDR_MIRROR_RP2_PRI V_ADDR_MIRROR_RP2_PRI(1U) + +#define S_ADDR_MIRROR_RP2_SEC 10 +#define V_ADDR_MIRROR_RP2_SEC(x) ((x) << S_ADDR_MIRROR_RP2_SEC) +#define F_ADDR_MIRROR_RP2_SEC V_ADDR_MIRROR_RP2_SEC(1U) + +#define S_ADDR_MIRROR_RP3_PRI 9 +#define V_ADDR_MIRROR_RP3_PRI(x) ((x) << S_ADDR_MIRROR_RP3_PRI) +#define F_ADDR_MIRROR_RP3_PRI V_ADDR_MIRROR_RP3_PRI(1U) + +#define S_ADDR_MIRROR_RP3_SEC 8 +#define V_ADDR_MIRROR_RP3_SEC(x) ((x) << S_ADDR_MIRROR_RP3_SEC) +#define F_ADDR_MIRROR_RP3_SEC V_ADDR_MIRROR_RP3_SEC(1U) + +#define S_RANK_GROUPING 6 +#define M_RANK_GROUPING 0x3U +#define V_RANK_GROUPING(x) ((x) << S_RANK_GROUPING) +#define G_RANK_GROUPING(x) (((x) >> S_RANK_GROUPING) & M_RANK_GROUPING) + +#define A_MC_DDRPHY_PC_ERROR_STATUS0 0x47048 + +#define S_RC_ERROR 15 +#define V_RC_ERROR(x) ((x) << S_RC_ERROR) +#define F_RC_ERROR V_RC_ERROR(1U) + +#define S_WC_ERROR 14 +#define V_WC_ERROR(x) ((x) << S_WC_ERROR) +#define F_WC_ERROR V_WC_ERROR(1U) + +#define S_SEQ_ERROR 13 +#define V_SEQ_ERROR(x) ((x) << S_SEQ_ERROR) +#define F_SEQ_ERROR V_SEQ_ERROR(1U) + +#define S_CC_ERROR 12 +#define V_CC_ERROR(x) ((x) << S_CC_ERROR) +#define F_CC_ERROR V_CC_ERROR(1U) + +#define S_APB_ERROR 11 +#define V_APB_ERROR(x) ((x) << S_APB_ERROR) +#define F_APB_ERROR V_APB_ERROR(1U) + +#define S_PC_ERROR 10 +#define V_PC_ERROR(x) ((x) << S_PC_ERROR) +#define F_PC_ERROR V_PC_ERROR(1U) + +#define A_MC_DDRPHY_PC_ERROR_MASK0 0x4704c + +#define S_RC_ERROR_MASK 15 +#define V_RC_ERROR_MASK(x) ((x) << S_RC_ERROR_MASK) +#define F_RC_ERROR_MASK V_RC_ERROR_MASK(1U) + +#define S_WC_ERROR_MASK 14 +#define V_WC_ERROR_MASK(x) ((x) << S_WC_ERROR_MASK) +#define F_WC_ERROR_MASK V_WC_ERROR_MASK(1U) + +#define S_SEQ_ERROR_MASK 13 +#define V_SEQ_ERROR_MASK(x) ((x) << S_SEQ_ERROR_MASK) +#define F_SEQ_ERROR_MASK V_SEQ_ERROR_MASK(1U) + +#define S_CC_ERROR_MASK 12 +#define V_CC_ERROR_MASK(x) ((x) << S_CC_ERROR_MASK) +#define F_CC_ERROR_MASK V_CC_ERROR_MASK(1U) + +#define S_APB_ERROR_MASK 11 +#define V_APB_ERROR_MASK(x) ((x) << S_APB_ERROR_MASK) +#define F_APB_ERROR_MASK V_APB_ERROR_MASK(1U) + +#define S_PC_ERROR_MASK 10 +#define V_PC_ERROR_MASK(x) ((x) << S_PC_ERROR_MASK) +#define F_PC_ERROR_MASK V_PC_ERROR_MASK(1U) + +#define A_MC_DDRPHY_PC_IO_PVT_FET_CONTROL 0x47050 + +#define S_PVTP 11 +#define M_PVTP 0x1fU +#define V_PVTP(x) ((x) << S_PVTP) +#define G_PVTP(x) (((x) >> S_PVTP) & M_PVTP) + +#define S_PVTN 6 +#define M_PVTN 0x1fU +#define V_PVTN(x) ((x) << S_PVTN) +#define G_PVTN(x) (((x) >> S_PVTN) & M_PVTN) + +#define S_PVT_OVERRIDE 5 +#define V_PVT_OVERRIDE(x) ((x) << S_PVT_OVERRIDE) +#define F_PVT_OVERRIDE V_PVT_OVERRIDE(1U) + +#define S_ENABLE_ZCAL 4 +#define V_ENABLE_ZCAL(x) ((x) << S_ENABLE_ZCAL) +#define F_ENABLE_ZCAL V_ENABLE_ZCAL(1U) + +#define A_MC_DDRPHY_PC_VREF_DRV_CONTROL 0x47054 + +#define S_VREFDQ0DSGN 15 +#define V_VREFDQ0DSGN(x) ((x) << S_VREFDQ0DSGN) +#define F_VREFDQ0DSGN V_VREFDQ0DSGN(1U) + +#define S_VREFDQ0D 11 +#define M_VREFDQ0D 0xfU +#define V_VREFDQ0D(x) ((x) << S_VREFDQ0D) +#define G_VREFDQ0D(x) (((x) >> S_VREFDQ0D) & M_VREFDQ0D) + +#define S_VREFDQ1DSGN 10 +#define V_VREFDQ1DSGN(x) ((x) << S_VREFDQ1DSGN) +#define F_VREFDQ1DSGN V_VREFDQ1DSGN(1U) + +#define S_VREFDQ1D 6 +#define M_VREFDQ1D 0xfU +#define V_VREFDQ1D(x) ((x) << S_VREFDQ1D) +#define G_VREFDQ1D(x) (((x) >> S_VREFDQ1D) & M_VREFDQ1D) + +#define A_MC_DDRPHY_PC_INIT_CAL_CONFIG0 0x47058 + +#define S_ENA_WR_LEVEL 15 +#define V_ENA_WR_LEVEL(x) ((x) << S_ENA_WR_LEVEL) +#define F_ENA_WR_LEVEL V_ENA_WR_LEVEL(1U) + +#define S_ENA_INITIAL_PAT_WR 14 +#define V_ENA_INITIAL_PAT_WR(x) ((x) << S_ENA_INITIAL_PAT_WR) +#define F_ENA_INITIAL_PAT_WR V_ENA_INITIAL_PAT_WR(1U) + +#define S_ENA_DQS_ALIGN 13 +#define V_ENA_DQS_ALIGN(x) ((x) << S_ENA_DQS_ALIGN) +#define F_ENA_DQS_ALIGN V_ENA_DQS_ALIGN(1U) + +#define S_ENA_RDCLK_ALIGN 12 +#define V_ENA_RDCLK_ALIGN(x) ((x) << S_ENA_RDCLK_ALIGN) +#define F_ENA_RDCLK_ALIGN V_ENA_RDCLK_ALIGN(1U) + +#define S_ENA_READ_CTR 11 +#define V_ENA_READ_CTR(x) ((x) << S_ENA_READ_CTR) +#define F_ENA_READ_CTR V_ENA_READ_CTR(1U) + +#define S_ENA_WRITE_CTR 10 +#define V_ENA_WRITE_CTR(x) ((x) << S_ENA_WRITE_CTR) +#define F_ENA_WRITE_CTR V_ENA_WRITE_CTR(1U) + +#define S_ENA_INITIAL_COARSE_WR 9 +#define V_ENA_INITIAL_COARSE_WR(x) ((x) << S_ENA_INITIAL_COARSE_WR) +#define F_ENA_INITIAL_COARSE_WR V_ENA_INITIAL_COARSE_WR(1U) + +#define S_ENA_COARSE_RD 8 +#define V_ENA_COARSE_RD(x) ((x) << S_ENA_COARSE_RD) +#define F_ENA_COARSE_RD V_ENA_COARSE_RD(1U) + +#define S_ENA_CUSTOM_RD 7 +#define V_ENA_CUSTOM_RD(x) ((x) << S_ENA_CUSTOM_RD) +#define F_ENA_CUSTOM_RD V_ENA_CUSTOM_RD(1U) + +#define S_ENA_CUSTOM_WR 6 +#define V_ENA_CUSTOM_WR(x) ((x) << S_ENA_CUSTOM_WR) +#define F_ENA_CUSTOM_WR V_ENA_CUSTOM_WR(1U) + +#define S_ABORT_ON_CAL_ERROR 5 +#define V_ABORT_ON_CAL_ERROR(x) ((x) << S_ABORT_ON_CAL_ERROR) +#define F_ABORT_ON_CAL_ERROR V_ABORT_ON_CAL_ERROR(1U) + +#define S_ENA_DIGITAL_EYE 4 +#define V_ENA_DIGITAL_EYE(x) ((x) << S_ENA_DIGITAL_EYE) +#define F_ENA_DIGITAL_EYE V_ENA_DIGITAL_EYE(1U) + +#define S_ENA_RANK_PAIR 0 +#define M_ENA_RANK_PAIR 0xfU +#define V_ENA_RANK_PAIR(x) ((x) << S_ENA_RANK_PAIR) +#define G_ENA_RANK_PAIR(x) (((x) >> S_ENA_RANK_PAIR) & M_ENA_RANK_PAIR) + +#define A_MC_DDRPHY_PC_INIT_CAL_CONFIG1 0x4705c + +#define S_REFRESH_COUNT 12 +#define M_REFRESH_COUNT 0xfU +#define V_REFRESH_COUNT(x) ((x) << S_REFRESH_COUNT) +#define G_REFRESH_COUNT(x) (((x) >> S_REFRESH_COUNT) & M_REFRESH_COUNT) + +#define S_REFRESH_CONTROL 10 +#define M_REFRESH_CONTROL 0x3U +#define V_REFRESH_CONTROL(x) ((x) << S_REFRESH_CONTROL) +#define G_REFRESH_CONTROL(x) (((x) >> S_REFRESH_CONTROL) & M_REFRESH_CONTROL) + +#define S_REFRESH_ALL_RANKS 9 +#define V_REFRESH_ALL_RANKS(x) ((x) << S_REFRESH_ALL_RANKS) +#define F_REFRESH_ALL_RANKS V_REFRESH_ALL_RANKS(1U) + +#define S_REFRESH_INTERVAL 0 +#define M_REFRESH_INTERVAL 0x7fU +#define V_REFRESH_INTERVAL(x) ((x) << S_REFRESH_INTERVAL) +#define G_REFRESH_INTERVAL(x) (((x) >> S_REFRESH_INTERVAL) & M_REFRESH_INTERVAL) + +#define A_MC_DDRPHY_PC_INIT_CAL_ERROR 0x47060 + +#define S_ERROR_WR_LEVEL 15 +#define V_ERROR_WR_LEVEL(x) ((x) << S_ERROR_WR_LEVEL) +#define F_ERROR_WR_LEVEL V_ERROR_WR_LEVEL(1U) + +#define S_ERROR_INITIAL_PAT_WRITE 14 +#define V_ERROR_INITIAL_PAT_WRITE(x) ((x) << S_ERROR_INITIAL_PAT_WRITE) +#define F_ERROR_INITIAL_PAT_WRITE V_ERROR_INITIAL_PAT_WRITE(1U) + +#define S_ERROR_DQS_ALIGN 13 +#define V_ERROR_DQS_ALIGN(x) ((x) << S_ERROR_DQS_ALIGN) +#define F_ERROR_DQS_ALIGN V_ERROR_DQS_ALIGN(1U) + +#define S_ERROR_RDCLK_ALIGN 12 +#define V_ERROR_RDCLK_ALIGN(x) ((x) << S_ERROR_RDCLK_ALIGN) +#define F_ERROR_RDCLK_ALIGN V_ERROR_RDCLK_ALIGN(1U) + +#define S_ERROR_READ_CTR 11 +#define V_ERROR_READ_CTR(x) ((x) << S_ERROR_READ_CTR) +#define F_ERROR_READ_CTR V_ERROR_READ_CTR(1U) + +#define S_ERROR_WRITE_CTR 10 +#define V_ERROR_WRITE_CTR(x) ((x) << S_ERROR_WRITE_CTR) +#define F_ERROR_WRITE_CTR V_ERROR_WRITE_CTR(1U) + +#define S_ERROR_INITIAL_COARSE_WR 9 +#define V_ERROR_INITIAL_COARSE_WR(x) ((x) << S_ERROR_INITIAL_COARSE_WR) +#define F_ERROR_INITIAL_COARSE_WR V_ERROR_INITIAL_COARSE_WR(1U) + +#define S_ERROR_COARSE_RD 8 +#define V_ERROR_COARSE_RD(x) ((x) << S_ERROR_COARSE_RD) +#define F_ERROR_COARSE_RD V_ERROR_COARSE_RD(1U) + +#define S_ERROR_CUSTOM_RD 7 +#define V_ERROR_CUSTOM_RD(x) ((x) << S_ERROR_CUSTOM_RD) +#define F_ERROR_CUSTOM_RD V_ERROR_CUSTOM_RD(1U) + +#define S_ERROR_CUSTOM_WR 6 +#define V_ERROR_CUSTOM_WR(x) ((x) << S_ERROR_CUSTOM_WR) +#define F_ERROR_CUSTOM_WR V_ERROR_CUSTOM_WR(1U) + +#define S_ERROR_DIGITAL_EYE 5 +#define V_ERROR_DIGITAL_EYE(x) ((x) << S_ERROR_DIGITAL_EYE) +#define F_ERROR_DIGITAL_EYE V_ERROR_DIGITAL_EYE(1U) + +#define S_ERROR_RANK_PAIR 0 +#define M_ERROR_RANK_PAIR 0xfU +#define V_ERROR_RANK_PAIR(x) ((x) << S_ERROR_RANK_PAIR) +#define G_ERROR_RANK_PAIR(x) (((x) >> S_ERROR_RANK_PAIR) & M_ERROR_RANK_PAIR) + +#define A_MC_DDRPHY_PC_INIT_CAL_STATUS 0x47064 + +#define S_INIT_CAL_COMPLETE 12 +#define M_INIT_CAL_COMPLETE 0xfU +#define V_INIT_CAL_COMPLETE(x) ((x) << S_INIT_CAL_COMPLETE) +#define G_INIT_CAL_COMPLETE(x) \ + (((x) >> S_INIT_CAL_COMPLETE) & M_INIT_CAL_COMPLETE) + +#define A_MC_DDRPHY_PC_INIT_CAL_MASK 0x47068 + +#define S_ERROR_WR_LEVEL_MASK 15 +#define V_ERROR_WR_LEVEL_MASK(x) ((x) << S_ERROR_WR_LEVEL_MASK) +#define F_ERROR_WR_LEVEL_MASK V_ERROR_WR_LEVEL_MASK(1U) + +#define S_ERROR_INITIAL_PAT_WRITE_MASK 14 +#define V_ERROR_INITIAL_PAT_WRITE_MASK(x) \ + ((x) << S_ERROR_INITIAL_PAT_WRITE_MASK) +#define F_ERROR_INITIAL_PAT_WRITE_MASK V_ERROR_INITIAL_PAT_WRITE_MASK(1U) + +#define S_ERROR_DQS_ALIGN_MASK 13 +#define V_ERROR_DQS_ALIGN_MASK(x) ((x) << S_ERROR_DQS_ALIGN_MASK) +#define F_ERROR_DQS_ALIGN_MASK V_ERROR_DQS_ALIGN_MASK(1U) + +#define S_ERROR_RDCLK_ALIGN_MASK 12 +#define V_ERROR_RDCLK_ALIGN_MASK(x) ((x) << S_ERROR_RDCLK_ALIGN_MASK) +#define F_ERROR_RDCLK_ALIGN_MASK V_ERROR_RDCLK_ALIGN_MASK(1U) + +#define S_ERROR_READ_CTR_MASK 11 +#define V_ERROR_READ_CTR_MASK(x) ((x) << S_ERROR_READ_CTR_MASK) +#define F_ERROR_READ_CTR_MASK V_ERROR_READ_CTR_MASK(1U) + +#define S_ERROR_WRITE_CTR_MASK 10 +#define V_ERROR_WRITE_CTR_MASK(x) ((x) << S_ERROR_WRITE_CTR_MASK) +#define F_ERROR_WRITE_CTR_MASK V_ERROR_WRITE_CTR_MASK(1U) + +#define S_ERROR_INITIAL_COARSE_WR_MASK 9 +#define V_ERROR_INITIAL_COARSE_WR_MASK(x) \ + ((x) << S_ERROR_INITIAL_COARSE_WR_MASK) +#define F_ERROR_INITIAL_COARSE_WR_MASK V_ERROR_INITIAL_COARSE_WR_MASK(1U) + +#define S_ERROR_COARSE_RD_MASK 8 +#define V_ERROR_COARSE_RD_MASK(x) ((x) << S_ERROR_COARSE_RD_MASK) +#define F_ERROR_COARSE_RD_MASK V_ERROR_COARSE_RD_MASK(1U) + +#define S_ERROR_CUSTOM_RD_MASK 7 +#define V_ERROR_CUSTOM_RD_MASK(x) ((x) << S_ERROR_CUSTOM_RD_MASK) +#define F_ERROR_CUSTOM_RD_MASK V_ERROR_CUSTOM_RD_MASK(1U) + +#define S_ERROR_CUSTOM_WR_MASK 6 +#define V_ERROR_CUSTOM_WR_MASK(x) ((x) << S_ERROR_CUSTOM_WR_MASK) +#define F_ERROR_CUSTOM_WR_MASK V_ERROR_CUSTOM_WR_MASK(1U) + +#define S_ERROR_DIGITAL_EYE_MASK 5 +#define V_ERROR_DIGITAL_EYE_MASK(x) ((x) << S_ERROR_DIGITAL_EYE_MASK) +#define F_ERROR_DIGITAL_EYE_MASK V_ERROR_DIGITAL_EYE_MASK(1U) + +#define A_MC_DDRPHY_PC_IO_PVT_FET_STATUS 0x4706c +#define A_MC_DDRPHY_PC_MR0_PRI_RP 0x47070 + +#define S_MODEREGISTER0VALUE 0 +#define M_MODEREGISTER0VALUE 0xffffU +#define V_MODEREGISTER0VALUE(x) ((x) << S_MODEREGISTER0VALUE) +#define G_MODEREGISTER0VALUE(x) \ + (((x) >> S_MODEREGISTER0VALUE) & M_MODEREGISTER0VALUE) + +#define A_MC_DDRPHY_PC_MR1_PRI_RP 0x47074 + +#define S_MODEREGISTER1VALUE 0 +#define M_MODEREGISTER1VALUE 0xffffU +#define V_MODEREGISTER1VALUE(x) ((x) << S_MODEREGISTER1VALUE) +#define G_MODEREGISTER1VALUE(x) \ + (((x) >> S_MODEREGISTER1VALUE) & M_MODEREGISTER1VALUE) + +#define A_MC_DDRPHY_PC_MR2_PRI_RP 0x47078 + +#define S_MODEREGISTER2VALUE 0 +#define M_MODEREGISTER2VALUE 0xffffU +#define V_MODEREGISTER2VALUE(x) ((x) << S_MODEREGISTER2VALUE) +#define G_MODEREGISTER2VALUE(x) \ + (((x) >> S_MODEREGISTER2VALUE) & M_MODEREGISTER2VALUE) + +#define A_MC_DDRPHY_PC_MR3_PRI_RP 0x4707c + +#define S_MODEREGISTER3VALUE 0 +#define M_MODEREGISTER3VALUE 0xffffU +#define V_MODEREGISTER3VALUE(x) ((x) << S_MODEREGISTER3VALUE) +#define G_MODEREGISTER3VALUE(x) \ + (((x) >> S_MODEREGISTER3VALUE) & M_MODEREGISTER3VALUE) + +#define A_MC_DDRPHY_PC_MR0_SEC_RP 0x47080 +#define A_MC_DDRPHY_PC_MR1_SEC_RP 0x47084 +#define A_MC_DDRPHY_PC_MR2_SEC_RP 0x47088 +#define A_MC_DDRPHY_PC_MR3_SEC_RP 0x4708c + +#define S_MODE_REGISTER_3_VALUE 0 +#define M_MODE_REGISTER_3_VALUE 0xffffU +#define V_MODE_REGISTER_3_VALUE(x) ((x) << S_MODE_REGISTER_3_VALUE) +#define G_MODE_REGISTER_3_VALUE(x) \ + (((x) >> S_MODE_REGISTER_3_VALUE) & M_MODE_REGISTER_3_VALUE) + +#define A_MC_DDRPHY_SEQ_RD_WR_DATA0 0x47200 + +#define S_DRD_WR_DATA_REG 0 +#define M_DRD_WR_DATA_REG 0xffffU +#define V_DRD_WR_DATA_REG(x) ((x) << S_DRD_WR_DATA_REG) +#define G_DRD_WR_DATA_REG(x) (((x) >> S_DRD_WR_DATA_REG) & M_DRD_WR_DATA_REG) + +#define A_MC_DDRPHY_SEQ_RD_WR_DATA1 0x47204 +#define A_MC_DDRPHY_SEQ_CONFIG0 0x47208 + +#define S_MPR_PATTERN_BIT 15 +#define V_MPR_PATTERN_BIT(x) ((x) << S_MPR_PATTERN_BIT) +#define F_MPR_PATTERN_BIT V_MPR_PATTERN_BIT(1U) + +#define S_TWO_CYCLE_ADDR_EN 14 +#define V_TWO_CYCLE_ADDR_EN(x) ((x) << S_TWO_CYCLE_ADDR_EN) +#define F_TWO_CYCLE_ADDR_EN V_TWO_CYCLE_ADDR_EN(1U) + +#define S_MR_MASK_EN 10 +#define M_MR_MASK_EN 0xfU +#define V_MR_MASK_EN(x) ((x) << S_MR_MASK_EN) +#define G_MR_MASK_EN(x) (((x) >> S_MR_MASK_EN) & M_MR_MASK_EN) + +#define A_MC_DDRPHY_SEQ_RESERVED_ADDR0 0x4720c +#define A_MC_DDRPHY_SEQ_RESERVED_ADDR1 0x47210 +#define A_MC_DDRPHY_SEQ_RESERVED_ADDR2 0x47214 +#define A_MC_DDRPHY_SEQ_RESERVED_ADDR3 0x47218 +#define A_MC_DDRPHY_SEQ_RESERVED_ADDR4 0x4721c +#define A_MC_DDRPHY_SEQ_ERROR_STATUS0 0x47220 + +#define S_MULTIPLE_REQ_ERROR 15 +#define V_MULTIPLE_REQ_ERROR(x) ((x) << S_MULTIPLE_REQ_ERROR) +#define F_MULTIPLE_REQ_ERROR V_MULTIPLE_REQ_ERROR(1U) + +#define S_INVALID_REQTYPE_ERRO 14 +#define V_INVALID_REQTYPE_ERRO(x) ((x) << S_INVALID_REQTYPE_ERRO) +#define F_INVALID_REQTYPE_ERRO V_INVALID_REQTYPE_ERRO(1U) + +#define S_EARLY_REQ_ERROR 13 +#define V_EARLY_REQ_ERROR(x) ((x) << S_EARLY_REQ_ERROR) +#define F_EARLY_REQ_ERROR V_EARLY_REQ_ERROR(1U) + +#define S_MULTIPLE_REQ_SOURCE 10 +#define M_MULTIPLE_REQ_SOURCE 0x7U +#define V_MULTIPLE_REQ_SOURCE(x) ((x) << S_MULTIPLE_REQ_SOURCE) +#define G_MULTIPLE_REQ_SOURCE(x) \ + (((x) >> S_MULTIPLE_REQ_SOURCE) & M_MULTIPLE_REQ_SOURCE) + +#define S_INVALID_REQTYPE 6 +#define M_INVALID_REQTYPE 0xfU +#define V_INVALID_REQTYPE(x) ((x) << S_INVALID_REQTYPE) +#define G_INVALID_REQTYPE(x) (((x) >> S_INVALID_REQTYPE) & M_INVALID_REQTYPE) + +#define S_INVALID_REQ_SOURCE 3 +#define M_INVALID_REQ_SOURCE 0x7U +#define V_INVALID_REQ_SOURCE(x) ((x) << S_INVALID_REQ_SOURCE) +#define G_INVALID_REQ_SOURCE(x) \ + (((x) >> S_INVALID_REQ_SOURCE) & M_INVALID_REQ_SOURCE) + +#define S_EARLY_REQ_SOURCE 0 +#define M_EARLY_REQ_SOURCE 0x7U +#define V_EARLY_REQ_SOURCE(x) ((x) << S_EARLY_REQ_SOURCE) +#define G_EARLY_REQ_SOURCE(x) (((x) >> S_EARLY_REQ_SOURCE) & M_EARLY_REQ_SOURCE) + +#define A_MC_DDRPHY_SEQ_ERROR_MASK0 0x47224 + +#define S_MULT_REQ_ERR_MASK 15 +#define V_MULT_REQ_ERR_MASK(x) ((x) << S_MULT_REQ_ERR_MASK) +#define F_MULT_REQ_ERR_MASK V_MULT_REQ_ERR_MASK(1U) + +#define S_INVALID_REQTYPE_ERR_MASK 14 +#define V_INVALID_REQTYPE_ERR_MASK(x) ((x) << S_INVALID_REQTYPE_ERR_MASK) +#define F_INVALID_REQTYPE_ERR_MASK V_INVALID_REQTYPE_ERR_MASK(1U) + +#define S_EARLY_REQ_ERR_MASK 13 +#define V_EARLY_REQ_ERR_MASK(x) ((x) << S_EARLY_REQ_ERR_MASK) +#define F_EARLY_REQ_ERR_MASK V_EARLY_REQ_ERR_MASK(1U) + +#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG0 0x47228 + +#define S_ODT_WR_VALUES_BITS0_7 8 +#define M_ODT_WR_VALUES_BITS0_7 0xffU +#define V_ODT_WR_VALUES_BITS0_7(x) ((x) << S_ODT_WR_VALUES_BITS0_7) +#define G_ODT_WR_VALUES_BITS0_7(x) \ + (((x) >> S_ODT_WR_VALUES_BITS0_7) & M_ODT_WR_VALUES_BITS0_7) + +#define S_ODT_WR_VALUES_BITS8_15 0 +#define M_ODT_WR_VALUES_BITS8_15 0xffU +#define V_ODT_WR_VALUES_BITS8_15(x) ((x) << S_ODT_WR_VALUES_BITS8_15) +#define G_ODT_WR_VALUES_BITS8_15(x) \ + (((x) >> S_ODT_WR_VALUES_BITS8_15) & M_ODT_WR_VALUES_BITS8_15) + +#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG1 0x4722c +#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG2 0x47230 +#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG3 0x47234 +#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG0 0x47238 + +#define S_ODT_RD_VALUES_X2 8 +#define M_ODT_RD_VALUES_X2 0xffU +#define V_ODT_RD_VALUES_X2(x) ((x) << S_ODT_RD_VALUES_X2) +#define G_ODT_RD_VALUES_X2(x) (((x) >> S_ODT_RD_VALUES_X2) & M_ODT_RD_VALUES_X2) + +#define S_ODT_RD_VALUES_X2PLUS1 0 +#define M_ODT_RD_VALUES_X2PLUS1 0xffU +#define V_ODT_RD_VALUES_X2PLUS1(x) ((x) << S_ODT_RD_VALUES_X2PLUS1) +#define G_ODT_RD_VALUES_X2PLUS1(x) \ + (((x) >> S_ODT_RD_VALUES_X2PLUS1) & M_ODT_RD_VALUES_X2PLUS1) + +#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG1 0x4723c +#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG2 0x47240 +#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG3 0x47244 +#define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM0 0x47248 + +#define S_TMOD_CYCLES 12 +#define M_TMOD_CYCLES 0xfU +#define V_TMOD_CYCLES(x) ((x) << S_TMOD_CYCLES) +#define G_TMOD_CYCLES(x) (((x) >> S_TMOD_CYCLES) & M_TMOD_CYCLES) + +#define S_TRCD_CYCLES 8 +#define M_TRCD_CYCLES 0xfU +#define V_TRCD_CYCLES(x) ((x) << S_TRCD_CYCLES) +#define G_TRCD_CYCLES(x) (((x) >> S_TRCD_CYCLES) & M_TRCD_CYCLES) + +#define S_TRP_CYCLES 4 +#define M_TRP_CYCLES 0xfU +#define V_TRP_CYCLES(x) ((x) << S_TRP_CYCLES) +#define G_TRP_CYCLES(x) (((x) >> S_TRP_CYCLES) & M_TRP_CYCLES) + +#define S_TRFC_CYCLES 0 +#define M_TRFC_CYCLES 0xfU +#define V_TRFC_CYCLES(x) ((x) << S_TRFC_CYCLES) +#define G_TRFC_CYCLES(x) (((x) >> S_TRFC_CYCLES) & M_TRFC_CYCLES) + +#define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM1 0x4724c + +#define S_TZQINIT_CYCLES 12 +#define M_TZQINIT_CYCLES 0xfU +#define V_TZQINIT_CYCLES(x) ((x) << S_TZQINIT_CYCLES) +#define G_TZQINIT_CYCLES(x) (((x) >> S_TZQINIT_CYCLES) & M_TZQINIT_CYCLES) + +#define S_TZQCS_CYCLES 8 +#define M_TZQCS_CYCLES 0xfU +#define V_TZQCS_CYCLES(x) ((x) << S_TZQCS_CYCLES) +#define G_TZQCS_CYCLES(x) (((x) >> S_TZQCS_CYCLES) & M_TZQCS_CYCLES) + +#define S_TWLDQSEN_CYCLES 4 +#define M_TWLDQSEN_CYCLES 0xfU +#define V_TWLDQSEN_CYCLES(x) ((x) << S_TWLDQSEN_CYCLES) +#define G_TWLDQSEN_CYCLES(x) (((x) >> S_TWLDQSEN_CYCLES) & M_TWLDQSEN_CYCLES) + +#define S_TWRMRD_CYCLES 0 +#define M_TWRMRD_CYCLES 0xfU +#define V_TWRMRD_CYCLES(x) ((x) << S_TWRMRD_CYCLES) +#define G_TWRMRD_CYCLES(x) (((x) >> S_TWRMRD_CYCLES) & M_TWRMRD_CYCLES) + +#define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM2 0x47250 + +#define S_TODTLON_OFF_CYCLES 12 +#define M_TODTLON_OFF_CYCLES 0xfU +#define V_TODTLON_OFF_CYCLES(x) ((x) << S_TODTLON_OFF_CYCLES) +#define G_TODTLON_OFF_CYCLES(x) \ + (((x) >> S_TODTLON_OFF_CYCLES) & M_TODTLON_OFF_CYCLES) + +#define S_TRC_CYCLES 8 +#define M_TRC_CYCLES 0xfU +#define V_TRC_CYCLES(x) ((x) << S_TRC_CYCLES) +#define G_TRC_CYCLES(x) (((x) >> S_TRC_CYCLES) & M_TRC_CYCLES) + +#define S_TMRSC_CYCLES 4 +#define M_TMRSC_CYCLES 0xfU +#define V_TMRSC_CYCLES(x) ((x) << S_TMRSC_CYCLES) +#define G_TMRSC_CYCLES(x) (((x) >> S_TMRSC_CYCLES) & M_TMRSC_CYCLES) + +#define A_MC_DDRPHY_RC_CONFIG0 0x47400 + +#define S_GLOBAL_PHY_OFFSET 12 +#define M_GLOBAL_PHY_OFFSET 0xfU +#define V_GLOBAL_PHY_OFFSET(x) ((x) << S_GLOBAL_PHY_OFFSET) +#define G_GLOBAL_PHY_OFFSET(x) \ + (((x) >> S_GLOBAL_PHY_OFFSET) & M_GLOBAL_PHY_OFFSET) + +#define S_ADVANCE_RD_VALID 11 +#define V_ADVANCE_RD_VALID(x) ((x) << S_ADVANCE_RD_VALID) +#define F_ADVANCE_RD_VALID V_ADVANCE_RD_VALID(1U) + +#define S_SINGLE_BIT_MPR_RP0 6 +#define V_SINGLE_BIT_MPR_RP0(x) ((x) << S_SINGLE_BIT_MPR_RP0) +#define F_SINGLE_BIT_MPR_RP0 V_SINGLE_BIT_MPR_RP0(1U) + +#define S_SINGLE_BIT_MPR_RP1 5 +#define V_SINGLE_BIT_MPR_RP1(x) ((x) << S_SINGLE_BIT_MPR_RP1) +#define F_SINGLE_BIT_MPR_RP1 V_SINGLE_BIT_MPR_RP1(1U) + +#define S_SINGLE_BIT_MPR_RP2 4 +#define V_SINGLE_BIT_MPR_RP2(x) ((x) << S_SINGLE_BIT_MPR_RP2) +#define F_SINGLE_BIT_MPR_RP2 V_SINGLE_BIT_MPR_RP2(1U) + +#define S_SINGLE_BIT_MPR_RP3 3 +#define V_SINGLE_BIT_MPR_RP3(x) ((x) << S_SINGLE_BIT_MPR_RP3) +#define F_SINGLE_BIT_MPR_RP3 V_SINGLE_BIT_MPR_RP3(1U) + +#define S_ALIGN_ON_EVEN_CYCLES 2 +#define V_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_ALIGN_ON_EVEN_CYCLES) +#define F_ALIGN_ON_EVEN_CYCLES V_ALIGN_ON_EVEN_CYCLES(1U) + +#define S_PERFORM_RDCLK_ALIGN 1 +#define V_PERFORM_RDCLK_ALIGN(x) ((x) << S_PERFORM_RDCLK_ALIGN) +#define F_PERFORM_RDCLK_ALIGN V_PERFORM_RDCLK_ALIGN(1U) + +#define S_STAGGERED_PATTERN 0 +#define V_STAGGERED_PATTERN(x) ((x) << S_STAGGERED_PATTERN) +#define F_STAGGERED_PATTERN V_STAGGERED_PATTERN(1U) + +#define A_MC_DDRPHY_RC_CONFIG1 0x47404 + +#define S_OUTER_LOOP_CNT 2 +#define M_OUTER_LOOP_CNT 0x3fffU +#define V_OUTER_LOOP_CNT(x) ((x) << S_OUTER_LOOP_CNT) +#define G_OUTER_LOOP_CNT(x) (((x) >> S_OUTER_LOOP_CNT) & M_OUTER_LOOP_CNT) + +#define A_MC_DDRPHY_RC_CONFIG2 0x47408 + +#define S_CONSEQ_PASS 11 +#define M_CONSEQ_PASS 0x1fU +#define V_CONSEQ_PASS(x) ((x) << S_CONSEQ_PASS) +#define G_CONSEQ_PASS(x) (((x) >> S_CONSEQ_PASS) & M_CONSEQ_PASS) + +#define S_BURST_WINDOW 5 +#define M_BURST_WINDOW 0x3U +#define V_BURST_WINDOW(x) ((x) << S_BURST_WINDOW) +#define G_BURST_WINDOW(x) (((x) >> S_BURST_WINDOW) & M_BURST_WINDOW) + +#define S_ALLOW_RD_FIFO_AUTO_R_ESET 4 +#define V_ALLOW_RD_FIFO_AUTO_R_ESET(x) ((x) << S_ALLOW_RD_FIFO_AUTO_R_ESET) +#define F_ALLOW_RD_FIFO_AUTO_R_ESET V_ALLOW_RD_FIFO_AUTO_R_ESET(1U) + +#define A_MC_DDRPHY_RC_ERROR_STATUS0 0x47414 + +#define S_RD_CNTL_ERROR 15 +#define V_RD_CNTL_ERROR(x) ((x) << S_RD_CNTL_ERROR) +#define F_RD_CNTL_ERROR V_RD_CNTL_ERROR(1U) + +#define A_MC_DDRPHY_RC_ERROR_MASK0 0x47418 + +#define S_RD_CNTL_ERROR_MASK 15 +#define V_RD_CNTL_ERROR_MASK(x) ((x) << S_RD_CNTL_ERROR_MASK) +#define F_RD_CNTL_ERROR_MASK V_RD_CNTL_ERROR_MASK(1U) + +#define A_MC_DDRPHY_RC_CONFIG3 0x4741c + +#define S_FINE_CAL_STEP_SIZE 13 +#define M_FINE_CAL_STEP_SIZE 0x7U +#define V_FINE_CAL_STEP_SIZE(x) ((x) << S_FINE_CAL_STEP_SIZE) +#define G_FINE_CAL_STEP_SIZE(x) \ + (((x) >> S_FINE_CAL_STEP_SIZE) & M_FINE_CAL_STEP_SIZE) + +#define S_COARSE_CAL_STEP_SIZE 9 +#define M_COARSE_CAL_STEP_SIZE 0xfU +#define V_COARSE_CAL_STEP_SIZE(x) ((x) << S_COARSE_CAL_STEP_SIZE) +#define G_COARSE_CAL_STEP_SIZE(x) \ + (((x) >> S_COARSE_CAL_STEP_SIZE) & M_COARSE_CAL_STEP_SIZE) + +#define S_DQ_SEL_QUAD 7 +#define M_DQ_SEL_QUAD 0x3U +#define V_DQ_SEL_QUAD(x) ((x) << S_DQ_SEL_QUAD) +#define G_DQ_SEL_QUAD(x) (((x) >> S_DQ_SEL_QUAD) & M_DQ_SEL_QUAD) + +#define S_DQ_SEL_LANE 4 +#define M_DQ_SEL_LANE 0x7U +#define V_DQ_SEL_LANE(x) ((x) << S_DQ_SEL_LANE) +#define G_DQ_SEL_LANE(x) (((x) >> S_DQ_SEL_LANE) & M_DQ_SEL_LANE) + +#define A_MC_DDRPHY_RC_PERIODIC 0x47420 +#define A_MC_DDRPHY_WC_CONFIG0 0x47600 + +#define S_TWLO_TWLOE 8 +#define M_TWLO_TWLOE 0xffU +#define V_TWLO_TWLOE(x) ((x) << S_TWLO_TWLOE) +#define G_TWLO_TWLOE(x) (((x) >> S_TWLO_TWLOE) & M_TWLO_TWLOE) + +#define S_WL_ONE_DQS_PULSE 7 +#define V_WL_ONE_DQS_PULSE(x) ((x) << S_WL_ONE_DQS_PULSE) +#define F_WL_ONE_DQS_PULSE V_WL_ONE_DQS_PULSE(1U) + +#define S_FW_WR_RD 1 +#define M_FW_WR_RD 0x3fU +#define V_FW_WR_RD(x) ((x) << S_FW_WR_RD) +#define G_FW_WR_RD(x) (((x) >> S_FW_WR_RD) & M_FW_WR_RD) + +#define S_CUSTOM_INIT_WRITE 0 +#define V_CUSTOM_INIT_WRITE(x) ((x) << S_CUSTOM_INIT_WRITE) +#define F_CUSTOM_INIT_WRITE V_CUSTOM_INIT_WRITE(1U) + +#define A_MC_DDRPHY_WC_CONFIG1 0x47604 + +#define S_BIG_STEP 12 +#define M_BIG_STEP 0xfU +#define V_BIG_STEP(x) ((x) << S_BIG_STEP) +#define G_BIG_STEP(x) (((x) >> S_BIG_STEP) & M_BIG_STEP) + +#define S_SMALL_STEP 9 +#define M_SMALL_STEP 0x7U +#define V_SMALL_STEP(x) ((x) << S_SMALL_STEP) +#define G_SMALL_STEP(x) (((x) >> S_SMALL_STEP) & M_SMALL_STEP) + +#define S_WR_PRE_DLY 3 +#define M_WR_PRE_DLY 0x3fU +#define V_WR_PRE_DLY(x) ((x) << S_WR_PRE_DLY) +#define G_WR_PRE_DLY(x) (((x) >> S_WR_PRE_DLY) & M_WR_PRE_DLY) + +#define A_MC_DDRPHY_WC_CONFIG2 0x47608 + +#define S_NUM_VALID_SAMPLES 12 +#define M_NUM_VALID_SAMPLES 0xfU +#define V_NUM_VALID_SAMPLES(x) ((x) << S_NUM_VALID_SAMPLES) +#define G_NUM_VALID_SAMPLES(x) \ + (((x) >> S_NUM_VALID_SAMPLES) & M_NUM_VALID_SAMPLES) + +#define S_FW_RD_WR 6 +#define M_FW_RD_WR 0x3fU +#define V_FW_RD_WR(x) ((x) << S_FW_RD_WR) +#define G_FW_RD_WR(x) (((x) >> S_FW_RD_WR) & M_FW_RD_WR) + +#define A_MC_DDRPHY_WC_ERROR_STATUS0 0x4760c + +#define S_WR_CNTL_ERROR 15 +#define V_WR_CNTL_ERROR(x) ((x) << S_WR_CNTL_ERROR) +#define F_WR_CNTL_ERROR V_WR_CNTL_ERROR(1U) + +#define A_MC_DDRPHY_WC_ERROR_MASK0 0x47610 + +#define S_WR_CNTL_ERROR_MASK 15 +#define V_WR_CNTL_ERROR_MASK(x) ((x) << S_WR_CNTL_ERROR_MASK) +#define F_WR_CNTL_ERROR_MASK V_WR_CNTL_ERROR_MASK(1U) + +#define A_MC_DDRPHY_WC_CONFIG3 0x47614 + +#define S_DDR4_MRS_CMD_DQ_EN 15 +#define V_DDR4_MRS_CMD_DQ_EN(x) ((x) << S_DDR4_MRS_CMD_DQ_EN) +#define F_DDR4_MRS_CMD_DQ_EN V_DDR4_MRS_CMD_DQ_EN(1U) + +#define S_MRS_CMD_DQ_ON 9 +#define M_MRS_CMD_DQ_ON 0x3fU +#define V_MRS_CMD_DQ_ON(x) ((x) << S_MRS_CMD_DQ_ON) +#define G_MRS_CMD_DQ_ON(x) (((x) >> S_MRS_CMD_DQ_ON) & M_MRS_CMD_DQ_ON) + +#define S_MRS_CMD_DQ_OFF 3 +#define M_MRS_CMD_DQ_OFF 0x3fU +#define V_MRS_CMD_DQ_OFF(x) ((x) << S_MRS_CMD_DQ_OFF) +#define G_MRS_CMD_DQ_OFF(x) (((x) >> S_MRS_CMD_DQ_OFF) & M_MRS_CMD_DQ_OFF) + +#define A_MC_DDRPHY_WC_WRCLK_CNTL 0x47618 + +#define S_WRCLK_CAL_START 15 +#define V_WRCLK_CAL_START(x) ((x) << S_WRCLK_CAL_START) +#define F_WRCLK_CAL_START V_WRCLK_CAL_START(1U) + +#define S_WRCLK_CAL_DONE 14 +#define V_WRCLK_CAL_DONE(x) ((x) << S_WRCLK_CAL_DONE) +#define F_WRCLK_CAL_DONE V_WRCLK_CAL_DONE(1U) + +#define A_MC_DDRPHY_APB_CONFIG0 0x47800 + +#define S_DISABLE_PARITY_CHECKER 15 +#define V_DISABLE_PARITY_CHECKER(x) ((x) << S_DISABLE_PARITY_CHECKER) +#define F_DISABLE_PARITY_CHECKER V_DISABLE_PARITY_CHECKER(1U) + +#define S_GENERATE_EVEN_PARITY 14 +#define V_GENERATE_EVEN_PARITY(x) ((x) << S_GENERATE_EVEN_PARITY) +#define F_GENERATE_EVEN_PARITY V_GENERATE_EVEN_PARITY(1U) + +#define S_FORCE_ON_CLK_GATE 13 +#define V_FORCE_ON_CLK_GATE(x) ((x) << S_FORCE_ON_CLK_GATE) +#define F_FORCE_ON_CLK_GATE V_FORCE_ON_CLK_GATE(1U) + +#define S_DEBUG_BUS_SEL_LO 12 +#define V_DEBUG_BUS_SEL_LO(x) ((x) << S_DEBUG_BUS_SEL_LO) +#define F_DEBUG_BUS_SEL_LO V_DEBUG_BUS_SEL_LO(1U) + +#define S_DEBUG_BUS_SEL_HI 8 +#define M_DEBUG_BUS_SEL_HI 0xfU +#define V_DEBUG_BUS_SEL_HI(x) ((x) << S_DEBUG_BUS_SEL_HI) +#define G_DEBUG_BUS_SEL_HI(x) (((x) >> S_DEBUG_BUS_SEL_HI) & M_DEBUG_BUS_SEL_HI) + +#define A_MC_DDRPHY_APB_ERROR_STATUS0 0x47804 + +#define S_INVALID_ADDRESS 15 +#define V_INVALID_ADDRESS(x) ((x) << S_INVALID_ADDRESS) +#define F_INVALID_ADDRESS V_INVALID_ADDRESS(1U) + +#define S_WR_PAR_ERR 14 +#define V_WR_PAR_ERR(x) ((x) << S_WR_PAR_ERR) +#define F_WR_PAR_ERR V_WR_PAR_ERR(1U) + +#define A_MC_DDRPHY_APB_ERROR_MASK0 0x47808 + +#define S_INVALID_ADDRESS_MASK 15 +#define V_INVALID_ADDRESS_MASK(x) ((x) << S_INVALID_ADDRESS_MASK) +#define F_INVALID_ADDRESS_MASK V_INVALID_ADDRESS_MASK(1U) + +#define S_WR_PAR_ERR_MASK 14 +#define V_WR_PAR_ERR_MASK(x) ((x) << S_WR_PAR_ERR_MASK) +#define F_WR_PAR_ERR_MASK V_WR_PAR_ERR_MASK(1U) + +#define A_MC_DDRPHY_APB_DP18_POPULATION 0x4780c + +#define S_DP18_0_POPULATED 15 +#define V_DP18_0_POPULATED(x) ((x) << S_DP18_0_POPULATED) +#define F_DP18_0_POPULATED V_DP18_0_POPULATED(1U) + +#define S_DP18_1_POPULATED 14 +#define V_DP18_1_POPULATED(x) ((x) << S_DP18_1_POPULATED) +#define F_DP18_1_POPULATED V_DP18_1_POPULATED(1U) + +#define S_DP18_2_POPULATED 13 +#define V_DP18_2_POPULATED(x) ((x) << S_DP18_2_POPULATED) +#define F_DP18_2_POPULATED V_DP18_2_POPULATED(1U) + +#define S_DP18_3_POPULATED 12 +#define V_DP18_3_POPULATED(x) ((x) << S_DP18_3_POPULATED) +#define F_DP18_3_POPULATED V_DP18_3_POPULATED(1U) + +#define S_DP18_4_POPULATED 11 +#define V_DP18_4_POPULATED(x) ((x) << S_DP18_4_POPULATED) +#define F_DP18_4_POPULATED V_DP18_4_POPULATED(1U) + +#define S_DP18_5_POPULATED 10 +#define V_DP18_5_POPULATED(x) ((x) << S_DP18_5_POPULATED) +#define F_DP18_5_POPULATED V_DP18_5_POPULATED(1U) + +#define S_DP18_6_POPULATED 9 +#define V_DP18_6_POPULATED(x) ((x) << S_DP18_6_POPULATED) +#define F_DP18_6_POPULATED V_DP18_6_POPULATED(1U) + +#define S_DP18_7_POPULATED 8 +#define V_DP18_7_POPULATED(x) ((x) << S_DP18_7_POPULATED) +#define F_DP18_7_POPULATED V_DP18_7_POPULATED(1U) + +#define S_DP18_8_POPULATED 7 +#define V_DP18_8_POPULATED(x) ((x) << S_DP18_8_POPULATED) +#define F_DP18_8_POPULATED V_DP18_8_POPULATED(1U) + +#define S_DP18_9_POPULATED 6 +#define V_DP18_9_POPULATED(x) ((x) << S_DP18_9_POPULATED) +#define F_DP18_9_POPULATED V_DP18_9_POPULATED(1U) + +#define S_DP18_10_POPULATED 5 +#define V_DP18_10_POPULATED(x) ((x) << S_DP18_10_POPULATED) +#define F_DP18_10_POPULATED V_DP18_10_POPULATED(1U) + +#define S_DP18_11_POPULATED 4 +#define V_DP18_11_POPULATED(x) ((x) << S_DP18_11_POPULATED) +#define F_DP18_11_POPULATED V_DP18_11_POPULATED(1U) + +#define S_DP18_12_POPULATED 3 +#define V_DP18_12_POPULATED(x) ((x) << S_DP18_12_POPULATED) +#define F_DP18_12_POPULATED V_DP18_12_POPULATED(1U) + +#define S_DP18_13_POPULATED 2 +#define V_DP18_13_POPULATED(x) ((x) << S_DP18_13_POPULATED) +#define F_DP18_13_POPULATED V_DP18_13_POPULATED(1U) + +#define S_DP18_14_POPULATED 1 +#define V_DP18_14_POPULATED(x) ((x) << S_DP18_14_POPULATED) +#define F_DP18_14_POPULATED V_DP18_14_POPULATED(1U) + +#define A_MC_DDRPHY_APB_ADR_POPULATION 0x47810 + +#define S_ADR16_0_POPULATED 15 +#define V_ADR16_0_POPULATED(x) ((x) << S_ADR16_0_POPULATED) +#define F_ADR16_0_POPULATED V_ADR16_0_POPULATED(1U) + +#define S_ADR16_1_POPULATED 14 +#define V_ADR16_1_POPULATED(x) ((x) << S_ADR16_1_POPULATED) +#define F_ADR16_1_POPULATED V_ADR16_1_POPULATED(1U) + +#define S_ADR16_2_POPULATED 13 +#define V_ADR16_2_POPULATED(x) ((x) << S_ADR16_2_POPULATED) +#define F_ADR16_2_POPULATED V_ADR16_2_POPULATED(1U) + +#define S_ADR16_3_POPULATED 12 +#define V_ADR16_3_POPULATED(x) ((x) << S_ADR16_3_POPULATED) +#define F_ADR16_3_POPULATED V_ADR16_3_POPULATED(1U) + +#define S_ADR12_0_POPULATED 7 +#define V_ADR12_0_POPULATED(x) ((x) << S_ADR12_0_POPULATED) +#define F_ADR12_0_POPULATED V_ADR12_0_POPULATED(1U) + +#define S_ADR12_1_POPULATED 6 +#define V_ADR12_1_POPULATED(x) ((x) << S_ADR12_1_POPULATED) +#define F_ADR12_1_POPULATED V_ADR12_1_POPULATED(1U) + +#define S_ADR12_2_POPULATED 5 +#define V_ADR12_2_POPULATED(x) ((x) << S_ADR12_2_POPULATED) +#define F_ADR12_2_POPULATED V_ADR12_2_POPULATED(1U) + +#define S_ADR12_3_POPULATED 4 +#define V_ADR12_3_POPULATED(x) ((x) << S_ADR12_3_POPULATED) +#define F_ADR12_3_POPULATED V_ADR12_3_POPULATED(1U) + +#define A_MC_DDRPHY_APB_ATEST_MUX_SEL 0x47814 + +#define S_ATEST_CNTL 10 +#define M_ATEST_CNTL 0x3fU +#define V_ATEST_CNTL(x) ((x) << S_ATEST_CNTL) +#define G_ATEST_CNTL(x) (((x) >> S_ATEST_CNTL) & M_ATEST_CNTL) + +/* registers for module MC_1 */ +#define MC_1_BASE_ADDR 0x48000 + +/* registers for module EDC_T50 */ +#define EDC_T50_BASE_ADDR 0x50000 + +#define A_EDC_H_REF 0x50000 + +#define S_EDC_SLEEPSTATUS 31 +#define V_EDC_SLEEPSTATUS(x) ((x) << S_EDC_SLEEPSTATUS) +#define F_EDC_SLEEPSTATUS V_EDC_SLEEPSTATUS(1U) + +#define S_EDC_SLEEPREQ 30 +#define V_EDC_SLEEPREQ(x) ((x) << S_EDC_SLEEPREQ) +#define F_EDC_SLEEPREQ V_EDC_SLEEPREQ(1U) + +#define S_PING_PONG 29 +#define V_PING_PONG(x) ((x) << S_PING_PONG) +#define F_PING_PONG V_PING_PONG(1U) + +#define A_EDC_H_BIST_CMD 0x50004 +#define A_EDC_H_BIST_CMD_ADDR 0x50008 +#define A_EDC_H_BIST_CMD_LEN 0x5000c +#define A_EDC_H_BIST_DATA_PATTERN 0x50010 +#define A_EDC_H_BIST_USER_WDATA0 0x50014 +#define A_EDC_H_BIST_USER_WDATA1 0x50018 +#define A_EDC_H_BIST_USER_WDATA2 0x5001c +#define A_EDC_H_BIST_NUM_ERR 0x50020 +#define A_EDC_H_BIST_ERR_FIRST_ADDR 0x50024 +#define A_EDC_H_BIST_STATUS_RDATA 0x50028 +#define A_EDC_H_PAR_ENABLE 0x50070 + +#define S_PERR_PAR_ENABLE 0 +#define V_PERR_PAR_ENABLE(x) ((x) << S_PERR_PAR_ENABLE) +#define F_PERR_PAR_ENABLE V_PERR_PAR_ENABLE(1U) + +#define A_EDC_H_INT_ENABLE 0x50074 +#define A_EDC_H_INT_CAUSE 0x50078 +#define A_EDC_H_ECC_STATUS 0x5007c +#define A_EDC_H_ECC_ERR_SEL 0x50080 + +#define S_CFG 0 +#define M_CFG 0x3U +#define V_CFG(x) ((x) << S_CFG) +#define G_CFG(x) (((x) >> S_CFG) & M_CFG) + +#define A_EDC_H_ECC_ERR_ADDR 0x50084 + +#define S_ECC_ADDR 0 +#define M_ECC_ADDR 0x7fffffU +#define V_ECC_ADDR(x) ((x) << S_ECC_ADDR) +#define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR) + +#define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090 +#define A_EDC_H_BIST_CRC_SEED 0x50400 + +/* registers for module EDC_T51 */ +#define EDC_T51_BASE_ADDR 0x50800 + +/* registers for module HMA_T5 */ +#define HMA_T5_BASE_ADDR 0x51000 + +#define A_HMA_TABLE_ACCESS 0x51000 + +#define S_TRIG 31 +#define V_TRIG(x) ((x) << S_TRIG) +#define F_TRIG V_TRIG(1U) + +#define S_RW 30 +#define V_RW(x) ((x) << S_RW) +#define F_RW V_RW(1U) + +#define S_L_SEL 0 +#define M_L_SEL 0xfU +#define V_L_SEL(x) ((x) << S_L_SEL) +#define G_L_SEL(x) (((x) >> S_L_SEL) & M_L_SEL) + +#define A_HMA_TABLE_LINE0 0x51004 + +#define S_CLIENT_EN 0 +#define M_CLIENT_EN 0x1fffU +#define V_CLIENT_EN(x) ((x) << S_CLIENT_EN) +#define G_CLIENT_EN(x) (((x) >> S_CLIENT_EN) & M_CLIENT_EN) + +#define A_HMA_TABLE_LINE1 0x51008 +#define A_HMA_TABLE_LINE2 0x5100c +#define A_HMA_TABLE_LINE3 0x51010 +#define A_HMA_TABLE_LINE4 0x51014 +#define A_HMA_TABLE_LINE5 0x51018 + +#define S_FID 16 +#define M_FID 0x7ffU +#define V_FID(x) ((x) << S_FID) +#define G_FID(x) (((x) >> S_FID) & M_FID) + +#define S_NOS 15 +#define V_NOS(x) ((x) << S_NOS) +#define F_NOS V_NOS(1U) + +#define S_RO 14 +#define V_RO(x) ((x) << S_RO) +#define F_RO V_RO(1U) + +#define A_HMA_COOKIE 0x5101c + +#define S_C_REQ 31 +#define V_C_REQ(x) ((x) << S_C_REQ) +#define F_C_REQ V_C_REQ(1U) + +#define S_C_FID 18 +#define M_C_FID 0x7ffU +#define V_C_FID(x) ((x) << S_C_FID) +#define G_C_FID(x) (((x) >> S_C_FID) & M_C_FID) + +#define S_C_VAL 8 +#define M_C_VAL 0x3ffU +#define V_C_VAL(x) ((x) << S_C_VAL) +#define G_C_VAL(x) (((x) >> S_C_VAL) & M_C_VAL) + +#define S_C_SEL 0 +#define M_C_SEL 0xfU +#define V_C_SEL(x) ((x) << S_C_SEL) +#define G_C_SEL(x) (((x) >> S_C_SEL) & M_C_SEL) + +#define A_HMA_PAR_ENABLE 0x51300 +#define A_HMA_INT_ENABLE 0x51304 +#define A_HMA_INT_CAUSE 0x51308 + #endif /* _CXGBE_T4_REGS_H */ diff --git a/usr/src/uts/common/io/cxgbe/common/t4_regs_values.h b/usr/src/uts/common/io/cxgbe/common/t4_regs_values.h index 7c8792a9de..d0dabaf108 100644 --- a/usr/src/uts/common/io/cxgbe/common/t4_regs_values.h +++ b/usr/src/uts/common/io/cxgbe/common/t4_regs_values.h @@ -182,4 +182,58 @@ #define X_MBOWNER_FW 1 #define X_MBOWNER_PL 2 +/* + * PCI-E definitions. + * ================== + */ + +#define X_WINDOW_SHIFT 10 +#define X_PCIEOFST_SHIFT 10 + +/* + * TP definitions. + * =============== + */ + +/* + * TP_VLAN_PRI_MAP controls which subset of fields will be present in the + * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP + * selects for a particular field being present. These fields, when present + * in the Compressed Filter Tuple, have the following widths in bits. + */ +#define W_FT_FCOE 1 +#define W_FT_PORT 3 +#define W_FT_VNIC_ID 17 +#define W_FT_VLAN 17 +#define W_FT_TOS 8 +#define W_FT_PROTOCOL 8 +#define W_FT_ETHERTYPE 16 +#define W_FT_MACMATCH 9 +#define W_FT_MPSHITTYPE 3 +#define W_FT_FRAGMENTATION 1 + +/* + * Some of the Compressed Filter Tuple fields have internal structure. These + * bit shifts/masks describe those structures. All shifts are relative to the + * base position of the fields within the Compressed Filter Tuple + */ +#define S_FT_VLAN_VLD 16 +#define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD) +#define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U) + +#define S_FT_VNID_ID_VF 0 +#define M_FT_VNID_ID_VF 0x7fU +#define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF) +#define G_FT_VNID_ID_VF(x) (((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF) + +#define S_FT_VNID_ID_PF 7 +#define M_FT_VNID_ID_PF 0x7U +#define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF) +#define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF) + +#define S_FT_VNID_ID_VLD 16 +#define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD) +#define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U) + + #endif /* __T4_REGS_VALUES_H__ */ diff --git a/usr/src/uts/common/io/cxgbe/common/t4_tcb.h b/usr/src/uts/common/io/cxgbe/common/t4_tcb.h deleted file mode 100644 index ab9eb5683d..0000000000 --- a/usr/src/uts/common/io/cxgbe/common/t4_tcb.h +++ /dev/null @@ -1,752 +0,0 @@ -/* - * This file and its contents are supplied under the terms of the - * Common Development and Distribution License ("CDDL"), version 1.0. - * You may only use this file in accordance with the terms of version - * 1.0 of the CDDL. - * - * A full copy of the text of the CDDL should have accompanied this - * source. A copy of the CDDL is also available via the Internet at - * http://www.illumos.org/license/CDDL. - */ - -/* - * This file is part of the Chelsio T4 support code. - * - * Copyright (C) 2003-2013 Chelsio Communications. All rights reserved. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this - * release for licensing terms and conditions. - */ - -/* This file is automatically generated --- changes will be lost */ - -#ifndef _T4_TCB_DEFS_H -#define _T4_TCB_DEFS_H - -/* 3:0 */ -#define W_TCB_ULP_TYPE 0 -#define S_TCB_ULP_TYPE 0 -#define M_TCB_ULP_TYPE 0xfULL -#define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE) - -/* 11:4 */ -#define W_TCB_ULP_RAW 0 -#define S_TCB_ULP_RAW 4 -#define M_TCB_ULP_RAW 0xffULL -#define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW) - -/* 23:12 */ -#define W_TCB_L2T_IX 0 -#define S_TCB_L2T_IX 12 -#define M_TCB_L2T_IX 0xfffULL -#define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) - -/* 31:24 */ -#define W_TCB_SMAC_SEL 0 -#define S_TCB_SMAC_SEL 24 -#define M_TCB_SMAC_SEL 0xffULL -#define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) - -/* 95:32 */ -#define W_TCB_T_FLAGS 1 -#define S_TCB_T_FLAGS 0 -#define M_TCB_T_FLAGS 0xffffffffffffffffULL -#define V_TCB_T_FLAGS(x) ((__u64)(x) << S_TCB_T_FLAGS) - -/* 105:96 */ -#define W_TCB_RSS_INFO 3 -#define S_TCB_RSS_INFO 0 -#define M_TCB_RSS_INFO 0x3ffULL -#define V_TCB_RSS_INFO(x) ((x) << S_TCB_RSS_INFO) - -/* 111:106 */ -#define W_TCB_TOS 3 -#define S_TCB_TOS 10 -#define M_TCB_TOS 0x3fULL -#define V_TCB_TOS(x) ((x) << S_TCB_TOS) - -/* 115:112 */ -#define W_TCB_T_STATE 3 -#define S_TCB_T_STATE 16 -#define M_TCB_T_STATE 0xfULL -#define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) - -/* 119:116 */ -#define W_TCB_MAX_RT 3 -#define S_TCB_MAX_RT 20 -#define M_TCB_MAX_RT 0xfULL -#define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) - -/* 123:120 */ -#define W_TCB_T_MAXSEG 3 -#define S_TCB_T_MAXSEG 24 -#define M_TCB_T_MAXSEG 0xfULL -#define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG) - -/* 127:124 */ -#define W_TCB_SND_SCALE 3 -#define S_TCB_SND_SCALE 28 -#define M_TCB_SND_SCALE 0xfULL -#define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE) - -/* 131:128 */ -#define W_TCB_RCV_SCALE 4 -#define S_TCB_RCV_SCALE 0 -#define M_TCB_RCV_SCALE 0xfULL -#define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE) - -/* 135:132 */ -#define W_TCB_T_RXTSHIFT 4 -#define S_TCB_T_RXTSHIFT 4 -#define M_TCB_T_RXTSHIFT 0xfULL -#define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) - -/* 139:136 */ -#define W_TCB_T_DUPACKS 4 -#define S_TCB_T_DUPACKS 8 -#define M_TCB_T_DUPACKS 0xfULL -#define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) - -/* 143:140 */ -#define W_TCB_TIMESTAMP_OFFSET 4 -#define S_TCB_TIMESTAMP_OFFSET 12 -#define M_TCB_TIMESTAMP_OFFSET 0xfULL -#define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET) - -/* 159:144 */ -#define W_TCB_RCV_ADV 4 -#define S_TCB_RCV_ADV 16 -#define M_TCB_RCV_ADV 0xffffULL -#define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV) - -/* 191:160 */ -#define W_TCB_TIMESTAMP 5 -#define S_TCB_TIMESTAMP 0 -#define M_TCB_TIMESTAMP 0xffffffffULL -#define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP) - -/* 223:192 */ -#define W_TCB_T_RTT_TS_RECENT_AGE 6 -#define S_TCB_T_RTT_TS_RECENT_AGE 0 -#define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL -#define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE) - -/* 255:224 */ -#define W_TCB_T_RTSEQ_RECENT 7 -#define S_TCB_T_RTSEQ_RECENT 0 -#define M_TCB_T_RTSEQ_RECENT 0xffffffffULL -#define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT) - -/* 271:256 */ -#define W_TCB_T_SRTT 8 -#define S_TCB_T_SRTT 0 -#define M_TCB_T_SRTT 0xffffULL -#define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT) - -/* 287:272 */ -#define W_TCB_T_RTTVAR 8 -#define S_TCB_T_RTTVAR 16 -#define M_TCB_T_RTTVAR 0xffffULL -#define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR) - -/* 319:288 */ -#define W_TCB_TX_MAX 9 -#define S_TCB_TX_MAX 0 -#define M_TCB_TX_MAX 0xffffffffULL -#define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX) - -/* 347:320 */ -#define W_TCB_SND_UNA_RAW 10 -#define S_TCB_SND_UNA_RAW 0 -#define M_TCB_SND_UNA_RAW 0xfffffffULL -#define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW) - -/* 375:348 */ -#define W_TCB_SND_NXT_RAW 10 -#define S_TCB_SND_NXT_RAW 28 -#define M_TCB_SND_NXT_RAW 0xfffffffULL -#define V_TCB_SND_NXT_RAW(x) ((__u64)(x) << S_TCB_SND_NXT_RAW) - -/* 403:376 */ -#define W_TCB_SND_MAX_RAW 11 -#define S_TCB_SND_MAX_RAW 24 -#define M_TCB_SND_MAX_RAW 0xfffffffULL -#define V_TCB_SND_MAX_RAW(x) ((__u64)(x) << S_TCB_SND_MAX_RAW) - -/* 431:404 */ -#define W_TCB_SND_REC_RAW 12 -#define S_TCB_SND_REC_RAW 20 -#define M_TCB_SND_REC_RAW 0xfffffffULL -#define V_TCB_SND_REC_RAW(x) ((__u64)(x) << S_TCB_SND_REC_RAW) - -/* 459:432 */ -#define W_TCB_SND_CWND 13 -#define S_TCB_SND_CWND 16 -#define M_TCB_SND_CWND 0xfffffffULL -#define V_TCB_SND_CWND(x) ((__u64)(x) << S_TCB_SND_CWND) - -/* 487:460 */ -#define W_TCB_SND_SSTHRESH 14 -#define S_TCB_SND_SSTHRESH 12 -#define M_TCB_SND_SSTHRESH 0xfffffffULL -#define V_TCB_SND_SSTHRESH(x) ((__u64)(x) << S_TCB_SND_SSTHRESH) - -/* 504:488 */ -#define W_TCB_TX_HDR_PTR_RAW 15 -#define S_TCB_TX_HDR_PTR_RAW 8 -#define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL -#define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW) - -/* 521:505 */ -#define W_TCB_TX_LAST_PTR_RAW 15 -#define S_TCB_TX_LAST_PTR_RAW 25 -#define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL -#define V_TCB_TX_LAST_PTR_RAW(x) ((__u64)(x) << S_TCB_TX_LAST_PTR_RAW) - -/* 553:522 */ -#define W_TCB_RCV_NXT 16 -#define S_TCB_RCV_NXT 10 -#define M_TCB_RCV_NXT 0xffffffffULL -#define V_TCB_RCV_NXT(x) ((__u64)(x) << S_TCB_RCV_NXT) - -/* 581:554 */ -#define W_TCB_RCV_WND 17 -#define S_TCB_RCV_WND 10 -#define M_TCB_RCV_WND 0xfffffffULL -#define V_TCB_RCV_WND(x) ((__u64)(x) << S_TCB_RCV_WND) - -/* 609:582 */ -#define W_TCB_RX_HDR_OFFSET 18 -#define S_TCB_RX_HDR_OFFSET 6 -#define M_TCB_RX_HDR_OFFSET 0xfffffffULL -#define V_TCB_RX_HDR_OFFSET(x) ((__u64)(x) << S_TCB_RX_HDR_OFFSET) - -/* 637:610 */ -#define W_TCB_TS_LAST_ACK_SENT_RAW 19 -#define S_TCB_TS_LAST_ACK_SENT_RAW 2 -#define M_TCB_TS_LAST_ACK_SENT_RAW 0xfffffffULL -#define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW) - -/* 665:638 */ -#define W_TCB_RX_FRAG0_START_IDX_RAW 19 -#define S_TCB_RX_FRAG0_START_IDX_RAW 30 -#define M_TCB_RX_FRAG0_START_IDX_RAW 0xfffffffULL -#define V_TCB_RX_FRAG0_START_IDX_RAW(x) \ - ((__u64)(x) << S_TCB_RX_FRAG0_START_IDX_RAW) - -/* 693:666 */ -#define W_TCB_RX_FRAG1_START_IDX_OFFSET 20 -#define S_TCB_RX_FRAG1_START_IDX_OFFSET 26 -#define M_TCB_RX_FRAG1_START_IDX_OFFSET 0xfffffffULL -#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) \ - ((__u64)(x) << S_TCB_RX_FRAG1_START_IDX_OFFSET) - -/* 721:694 */ -#define W_TCB_RX_FRAG0_LEN 21 -#define S_TCB_RX_FRAG0_LEN 22 -#define M_TCB_RX_FRAG0_LEN 0xfffffffULL -#define V_TCB_RX_FRAG0_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG0_LEN) - -/* 749:722 */ -#define W_TCB_RX_FRAG1_LEN 22 -#define S_TCB_RX_FRAG1_LEN 18 -#define M_TCB_RX_FRAG1_LEN 0xfffffffULL -#define V_TCB_RX_FRAG1_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG1_LEN) - -/* 765:750 */ -#define W_TCB_PDU_LEN 23 -#define S_TCB_PDU_LEN 14 -#define M_TCB_PDU_LEN 0xffffULL -#define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN) - -/* 782:766 */ -#define W_TCB_RX_PTR_RAW 23 -#define S_TCB_RX_PTR_RAW 30 -#define M_TCB_RX_PTR_RAW 0x1ffffULL -#define V_TCB_RX_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_PTR_RAW) - -/* 799:783 */ -#define W_TCB_RX_FRAG1_PTR_RAW 24 -#define S_TCB_RX_FRAG1_PTR_RAW 15 -#define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL -#define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW) - -/* 831:800 */ -#define W_TCB_MAIN_SLUSH 25 -#define S_TCB_MAIN_SLUSH 0 -#define M_TCB_MAIN_SLUSH 0xffffffffULL -#define V_TCB_MAIN_SLUSH(x) ((x) << S_TCB_MAIN_SLUSH) - -/* 846:832 */ -#define W_TCB_AUX1_SLUSH0 26 -#define S_TCB_AUX1_SLUSH0 0 -#define M_TCB_AUX1_SLUSH0 0x7fffULL -#define V_TCB_AUX1_SLUSH0(x) ((x) << S_TCB_AUX1_SLUSH0) - -/* 874:847 */ -#define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26 -#define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15 -#define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0xfffffffULL -#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) \ - ((__u64)(x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW) - -/* 891:875 */ -#define W_TCB_RX_FRAG2_PTR_RAW 27 -#define S_TCB_RX_FRAG2_PTR_RAW 11 -#define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL -#define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW) - -/* 919:892 */ -#define W_TCB_RX_FRAG2_LEN_RAW 27 -#define S_TCB_RX_FRAG2_LEN_RAW 28 -#define M_TCB_RX_FRAG2_LEN_RAW 0xfffffffULL -#define V_TCB_RX_FRAG2_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_LEN_RAW) - -/* 936:920 */ -#define W_TCB_RX_FRAG3_PTR_RAW 28 -#define S_TCB_RX_FRAG3_PTR_RAW 24 -#define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL -#define V_TCB_RX_FRAG3_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_PTR_RAW) - -/* 964:937 */ -#define W_TCB_RX_FRAG3_LEN_RAW 29 -#define S_TCB_RX_FRAG3_LEN_RAW 9 -#define M_TCB_RX_FRAG3_LEN_RAW 0xfffffffULL -#define V_TCB_RX_FRAG3_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_LEN_RAW) - -/* 992:965 */ -#define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30 -#define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 5 -#define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0xfffffffULL -#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) \ - ((__u64)(x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW) - -/* 1000:993 */ -#define W_TCB_PDU_HDR_LEN 31 -#define S_TCB_PDU_HDR_LEN 1 -#define M_TCB_PDU_HDR_LEN 0xffULL -#define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN) - -/* 1023:1001 */ -#define W_TCB_AUX1_SLUSH1 31 -#define S_TCB_AUX1_SLUSH1 9 -#define M_TCB_AUX1_SLUSH1 0x7fffffULL -#define V_TCB_AUX1_SLUSH1(x) ((x) << S_TCB_AUX1_SLUSH1) - -/* 840:832 */ -#define W_TCB_IRS_ULP 26 -#define S_TCB_IRS_ULP 0 -#define M_TCB_IRS_ULP 0x1ffULL -#define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP) - -/* 849:841 */ -#define W_TCB_ISS_ULP 26 -#define S_TCB_ISS_ULP 9 -#define M_TCB_ISS_ULP 0x1ffULL -#define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP) - -/* 863:850 */ -#define W_TCB_TX_PDU_LEN 26 -#define S_TCB_TX_PDU_LEN 18 -#define M_TCB_TX_PDU_LEN 0x3fffULL -#define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN) - -/* 879:864 */ -#define W_TCB_CQ_IDX_SQ 27 -#define S_TCB_CQ_IDX_SQ 0 -#define M_TCB_CQ_IDX_SQ 0xffffULL -#define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ) - -/* 895:880 */ -#define W_TCB_CQ_IDX_RQ 27 -#define S_TCB_CQ_IDX_RQ 16 -#define M_TCB_CQ_IDX_RQ 0xffffULL -#define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ) - -/* 911:896 */ -#define W_TCB_QP_ID 28 -#define S_TCB_QP_ID 0 -#define M_TCB_QP_ID 0xffffULL -#define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID) - -/* 927:912 */ -#define W_TCB_PD_ID 28 -#define S_TCB_PD_ID 16 -#define M_TCB_PD_ID 0xffffULL -#define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID) - -/* 959:928 */ -#define W_TCB_STAG 29 -#define S_TCB_STAG 0 -#define M_TCB_STAG 0xffffffffULL -#define V_TCB_STAG(x) ((x) << S_TCB_STAG) - -/* 985:960 */ -#define W_TCB_RQ_START 30 -#define S_TCB_RQ_START 0 -#define M_TCB_RQ_START 0x3ffffffULL -#define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START) - -/* 998:986 */ -#define W_TCB_RQ_MSN 30 -#define S_TCB_RQ_MSN 26 -#define M_TCB_RQ_MSN 0x1fffULL -#define V_TCB_RQ_MSN(x) ((__u64)(x) << S_TCB_RQ_MSN) - -/* 1002:999 */ -#define W_TCB_RQ_MAX_OFFSET 31 -#define S_TCB_RQ_MAX_OFFSET 7 -#define M_TCB_RQ_MAX_OFFSET 0xfULL -#define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET) - -/* 1015:1003 */ -#define W_TCB_RQ_WRITE_PTR 31 -#define S_TCB_RQ_WRITE_PTR 11 -#define M_TCB_RQ_WRITE_PTR 0x1fffULL -#define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR) - -/* 1019:1016 */ -#define W_TCB_RDMAP_OPCODE 31 -#define S_TCB_RDMAP_OPCODE 24 -#define M_TCB_RDMAP_OPCODE 0xfULL -#define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE) - -/* 1020:1020 */ -#define W_TCB_ORD_L_BIT_VLD 31 -#define S_TCB_ORD_L_BIT_VLD 28 -#define M_TCB_ORD_L_BIT_VLD 0x1ULL -#define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD) - -/* 1021:1021 */ -#define W_TCB_TX_FLUSH 31 -#define S_TCB_TX_FLUSH 29 -#define M_TCB_TX_FLUSH 0x1ULL -#define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH) - -/* 1022:1022 */ -#define W_TCB_TX_OOS_RXMT 31 -#define S_TCB_TX_OOS_RXMT 30 -#define M_TCB_TX_OOS_RXMT 0x1ULL -#define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT) - -/* 1023:1023 */ -#define W_TCB_TX_OOS_TXMT 31 -#define S_TCB_TX_OOS_TXMT 31 -#define M_TCB_TX_OOS_TXMT 0x1ULL -#define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT) - -/* 855:832 */ -#define W_TCB_RX_DDP_BUF0_OFFSET 26 -#define S_TCB_RX_DDP_BUF0_OFFSET 0 -#define M_TCB_RX_DDP_BUF0_OFFSET 0xffffffULL -#define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET) - -/* 879:856 */ -#define W_TCB_RX_DDP_BUF0_LEN 26 -#define S_TCB_RX_DDP_BUF0_LEN 24 -#define M_TCB_RX_DDP_BUF0_LEN 0xffffffULL -#define V_TCB_RX_DDP_BUF0_LEN(x) ((__u64)(x) << S_TCB_RX_DDP_BUF0_LEN) - -/* 903:880 */ -#define W_TCB_RX_DDP_FLAGS 27 -#define S_TCB_RX_DDP_FLAGS 16 -#define M_TCB_RX_DDP_FLAGS 0xffffffULL -#define V_TCB_RX_DDP_FLAGS(x) ((__u64)(x) << S_TCB_RX_DDP_FLAGS) - -/* 927:904 */ -#define W_TCB_RX_DDP_BUF1_OFFSET 28 -#define S_TCB_RX_DDP_BUF1_OFFSET 8 -#define M_TCB_RX_DDP_BUF1_OFFSET 0xffffffULL -#define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET) - -/* 951:928 */ -#define W_TCB_RX_DDP_BUF1_LEN 29 -#define S_TCB_RX_DDP_BUF1_LEN 0 -#define M_TCB_RX_DDP_BUF1_LEN 0xffffffULL -#define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN) - -/* 959:952 */ -#define W_TCB_AUX3_SLUSH 29 -#define S_TCB_AUX3_SLUSH 24 -#define M_TCB_AUX3_SLUSH 0xffULL -#define V_TCB_AUX3_SLUSH(x) ((x) << S_TCB_AUX3_SLUSH) - -/* 991:960 */ -#define W_TCB_RX_DDP_BUF0_TAG 30 -#define S_TCB_RX_DDP_BUF0_TAG 0 -#define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL -#define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG) - -/* 1023:992 */ -#define W_TCB_RX_DDP_BUF1_TAG 31 -#define S_TCB_RX_DDP_BUF1_TAG 0 -#define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL -#define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG) - -#define S_TF_MIGRATING 0 -#define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING) - -#define S_TF_NON_OFFLOAD 1 -#define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD) - -#define S_TF_LOCK_TID 2 -#define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID) - -#define S_TF_KEEPALIVE 3 -#define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE) - -#define S_TF_DACK 4 -#define V_TF_DACK(x) ((x) << S_TF_DACK) - -#define S_TF_DACK_MSS 5 -#define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS) - -#define S_TF_DACK_NOT_ACKED 6 -#define V_TF_DACK_NOT_ACKED(x) ((x) << S_TF_DACK_NOT_ACKED) - -#define S_TF_NAGLE 7 -#define V_TF_NAGLE(x) ((x) << S_TF_NAGLE) - -#define S_TF_SSWS_DISABLED 8 -#define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED) - -#define S_TF_RX_FLOW_CONTROL_DDP 9 -#define V_TF_RX_FLOW_CONTROL_DDP(x) ((x) << S_TF_RX_FLOW_CONTROL_DDP) - -#define S_TF_RX_FLOW_CONTROL_DISABLE 10 -#define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE) - -#define S_TF_RX_CHANNEL 11 -#define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL) - -#define S_TF_TX_CHANNEL0 12 -#define V_TF_TX_CHANNEL0(x) ((x) << S_TF_TX_CHANNEL0) - -#define S_TF_TX_CHANNEL1 13 -#define V_TF_TX_CHANNEL1(x) ((x) << S_TF_TX_CHANNEL1) - -#define S_TF_TX_QUIESCE 14 -#define V_TF_TX_QUIESCE(x) ((x) << S_TF_TX_QUIESCE) - -#define S_TF_RX_QUIESCE 15 -#define V_TF_RX_QUIESCE(x) ((x) << S_TF_RX_QUIESCE) - -#define S_TF_TX_PACE_AUTO 16 -#define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO) - -#define S_TF_MASK_HASH 16 -#define V_TF_MASK_HASH(x) ((x) << S_TF_MASK_HASH) - -#define S_TF_TX_PACE_FIXED 17 -#define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED) - -#define S_TF_DIRECT_STEER_HASH 17 -#define V_TF_DIRECT_STEER_HASH(x) ((x) << S_TF_DIRECT_STEER_HASH) - -#define S_TF_TX_QUEUE 18 -#define M_TF_TX_QUEUE 0x7ULL -#define V_TF_TX_QUEUE(x) ((x) << S_TF_TX_QUEUE) - -#define S_TF_TURBO 21 -#define V_TF_TURBO(x) ((x) << S_TF_TURBO) - -#define S_TF_REPORT_TID 21 -#define V_TF_REPORT_TID(x) ((x) << S_TF_REPORT_TID) - -#define S_TF_CCTRL_SEL0 22 -#define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0) - -#define S_TF_DROP 22 -#define V_TF_DROP(x) ((x) << S_TF_DROP) - -#define S_TF_CCTRL_SEL1 23 -#define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1) - -#define S_TF_DIRECT_STEER 23 -#define V_TF_DIRECT_STEER(x) ((x) << S_TF_DIRECT_STEER) - -#define S_TF_CORE_FIN 24 -#define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN) - -#define S_TF_CORE_URG 25 -#define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG) - -#define S_TF_CORE_MORE 26 -#define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE) - -#define S_TF_CORE_PUSH 27 -#define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH) - -#define S_TF_CORE_FLUSH 28 -#define V_TF_CORE_FLUSH(x) ((x) << S_TF_CORE_FLUSH) - -#define S_TF_RCV_COALESCE_ENABLE 29 -#define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE) - -#define S_TF_RCV_COALESCE_PUSH 30 -#define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH) - -#define S_TF_RCV_COALESCE_LAST_PSH 31 -#define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH) - -#define S_TF_RCV_COALESCE_HEARTBEAT 32 -#define V_TF_RCV_COALESCE_HEARTBEAT(x) \ - ((__u64)(x) << S_TF_RCV_COALESCE_HEARTBEAT) - -#define S_TF_INIT 33 -#define V_TF_INIT(x) ((__u64)(x) << S_TF_INIT) - -#define S_TF_ACTIVE_OPEN 34 -#define V_TF_ACTIVE_OPEN(x) ((__u64)(x) << S_TF_ACTIVE_OPEN) - -#define S_TF_ASK_MODE 35 -#define V_TF_ASK_MODE(x) ((__u64)(x) << S_TF_ASK_MODE) - -#define S_TF_MOD_SCHD_REASON0 36 -#define V_TF_MOD_SCHD_REASON0(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON0) - -#define S_TF_MOD_SCHD_REASON1 37 -#define V_TF_MOD_SCHD_REASON1(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON1) - -#define S_TF_MOD_SCHD_REASON2 38 -#define V_TF_MOD_SCHD_REASON2(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON2) - -#define S_TF_MOD_SCHD_TX 39 -#define V_TF_MOD_SCHD_TX(x) ((__u64)(x) << S_TF_MOD_SCHD_TX) - -#define S_TF_MOD_SCHD_RX 40 -#define V_TF_MOD_SCHD_RX(x) ((__u64)(x) << S_TF_MOD_SCHD_RX) - -#define S_TF_TIMER 41 -#define V_TF_TIMER(x) ((__u64)(x) << S_TF_TIMER) - -#define S_TF_DACK_TIMER 42 -#define V_TF_DACK_TIMER(x) ((__u64)(x) << S_TF_DACK_TIMER) - -#define S_TF_PEER_FIN 43 -#define V_TF_PEER_FIN(x) ((__u64)(x) << S_TF_PEER_FIN) - -#define S_TF_TX_COMPACT 44 -#define V_TF_TX_COMPACT(x) ((__u64)(x) << S_TF_TX_COMPACT) - -#define S_TF_RX_COMPACT 45 -#define V_TF_RX_COMPACT(x) ((__u64)(x) << S_TF_RX_COMPACT) - -#define S_TF_RDMA_ERROR 46 -#define V_TF_RDMA_ERROR(x) ((__u64)(x) << S_TF_RDMA_ERROR) - -#define S_TF_RDMA_FLM_ERROR 47 -#define V_TF_RDMA_FLM_ERROR(x) ((__u64)(x) << S_TF_RDMA_FLM_ERROR) - -#define S_TF_TX_PDU_OUT 48 -#define V_TF_TX_PDU_OUT(x) ((__u64)(x) << S_TF_TX_PDU_OUT) - -#define S_TF_RX_PDU_OUT 49 -#define V_TF_RX_PDU_OUT(x) ((__u64)(x) << S_TF_RX_PDU_OUT) - -#define S_TF_DUPACK_COUNT_ODD 50 -#define V_TF_DUPACK_COUNT_ODD(x) ((__u64)(x) << S_TF_DUPACK_COUNT_ODD) - -#define S_TF_FAST_RECOVERY 51 -#define V_TF_FAST_RECOVERY(x) ((__u64)(x) << S_TF_FAST_RECOVERY) - -#define S_TF_RECV_SCALE 52 -#define V_TF_RECV_SCALE(x) ((__u64)(x) << S_TF_RECV_SCALE) - -#define S_TF_RECV_TSTMP 53 -#define V_TF_RECV_TSTMP(x) ((__u64)(x) << S_TF_RECV_TSTMP) - -#define S_TF_RECV_SACK 54 -#define V_TF_RECV_SACK(x) ((__u64)(x) << S_TF_RECV_SACK) - -#define S_TF_PEND_CTL0 55 -#define V_TF_PEND_CTL0(x) ((__u64)(x) << S_TF_PEND_CTL0) - -#define S_TF_PEND_CTL1 56 -#define V_TF_PEND_CTL1(x) ((__u64)(x) << S_TF_PEND_CTL1) - -#define S_TF_PEND_CTL2 57 -#define V_TF_PEND_CTL2(x) ((__u64)(x) << S_TF_PEND_CTL2) - -#define S_TF_IP_VERSION 58 -#define V_TF_IP_VERSION(x) ((__u64)(x) << S_TF_IP_VERSION) - -#define S_TF_CCTRL_ECN 59 -#define V_TF_CCTRL_ECN(x) ((__u64)(x) << S_TF_CCTRL_ECN) - -#define S_TF_LPBK 59 -#define V_TF_LPBK(x) ((__u64)(x) << S_TF_LPBK) - -#define S_TF_CCTRL_ECE 60 -#define V_TF_CCTRL_ECE(x) ((__u64)(x) << S_TF_CCTRL_ECE) - -#define S_TF_REWRITE_DMAC 60 -#define V_TF_REWRITE_DMAC(x) ((__u64)(x) << S_TF_REWRITE_DMAC) - -#define S_TF_CCTRL_CWR 61 -#define V_TF_CCTRL_CWR(x) ((__u64)(x) << S_TF_CCTRL_CWR) - -#define S_TF_REWRITE_SMAC 61 -#define V_TF_REWRITE_SMAC(x) ((__u64)(x) << S_TF_REWRITE_SMAC) - -#define S_TF_CCTRL_RFR 62 -#define V_TF_CCTRL_RFR(x) ((__u64)(x) << S_TF_CCTRL_RFR) - -#define S_TF_DDP_INDICATE_OUT 16 -#define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT) - -#define S_TF_DDP_ACTIVE_BUF 17 -#define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF) - -#define S_TF_DDP_OFF 18 -#define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF) - -#define S_TF_DDP_WAIT_FRAG 19 -#define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG) - -#define S_TF_DDP_BUF_INF 20 -#define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF) - -#define S_TF_DDP_RX2TX 21 -#define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX) - -#define S_TF_DDP_BUF0_VALID 24 -#define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID) - -#define S_TF_DDP_BUF0_INDICATE 25 -#define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE) - -#define S_TF_DDP_BUF0_FLUSH 26 -#define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH) - -#define S_TF_DDP_PSHF_ENABLE_0 27 -#define V_TF_DDP_PSHF_ENABLE_0(x) ((x) << S_TF_DDP_PSHF_ENABLE_0) - -#define S_TF_DDP_PUSH_DISABLE_0 28 -#define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0) - -#define S_TF_DDP_PSH_NO_INVALIDATE0 29 -#define V_TF_DDP_PSH_NO_INVALIDATE0(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE0) - -#define S_TF_DDP_BUF1_VALID 32 -#define V_TF_DDP_BUF1_VALID(x) ((__u64)(x) << S_TF_DDP_BUF1_VALID) - -#define S_TF_DDP_BUF1_INDICATE 33 -#define V_TF_DDP_BUF1_INDICATE(x) ((__u64)(x) << S_TF_DDP_BUF1_INDICATE) - -#define S_TF_DDP_BUF1_FLUSH 34 -#define V_TF_DDP_BUF1_FLUSH(x) ((__u64)(x) << S_TF_DDP_BUF1_FLUSH) - -#define S_TF_DDP_PSHF_ENABLE_1 35 -#define V_TF_DDP_PSHF_ENABLE_1(x) ((__u64)(x) << S_TF_DDP_PSHF_ENABLE_1) - -#define S_TF_DDP_PUSH_DISABLE_1 36 -#define V_TF_DDP_PUSH_DISABLE_1(x) ((__u64)(x) << S_TF_DDP_PUSH_DISABLE_1) - -#define S_TF_DDP_PSH_NO_INVALIDATE1 37 -#define V_TF_DDP_PSH_NO_INVALIDATE1(x) \ - ((__u64)(x) << S_TF_DDP_PSH_NO_INVALIDATE1) - -#endif /* _T4_TCB_DEFS_H */ diff --git a/usr/src/uts/common/io/cxgbe/cxgbe/cxgbe.c b/usr/src/uts/common/io/cxgbe/cxgbe/cxgbe.c index e214cc2647..ac1b4414db 100644 --- a/usr/src/uts/common/io/cxgbe/cxgbe/cxgbe.c +++ b/usr/src/uts/common/io/cxgbe/cxgbe/cxgbe.c @@ -74,7 +74,7 @@ struct dev_ops cxgbe_dev_ops = { static struct modldrv modldrv = { .drv_modops = &mod_driverops, - .drv_linkinfo = "Chelsio T4 NIC " DRV_VERSION, + .drv_linkinfo = "Chelsio T4/T5 NIC " DRV_VERSION, .drv_dev_ops = &cxgbe_dev_ops }; diff --git a/usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h b/usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h index 77aa44407b..2fb707708f 100644 --- a/usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h +++ b/usr/src/uts/common/io/cxgbe/firmware/t4fw_interface.h @@ -41,9 +41,11 @@ enum fw_retval { FW_EFAULT = 14, /* bad address; fw bad */ FW_EBUSY = 16, /* resource busy */ FW_EEXIST = 17, /* file exists */ + FW_ENODEV = 19, /* no such device */ FW_EINVAL = 22, /* invalid argument */ FW_ENOSPC = 28, /* no space left on device */ FW_ENOSYS = 38, /* functionality not implemented */ + FW_ENODATA = 61, /* no data available */ FW_EPROTO = 71, /* protocol error */ FW_EADDRINUSE = 98, /* address already in use */ FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ @@ -76,10 +78,12 @@ enum fw_retval { */ enum fw_wr_opcodes { + FW_FRAG_WR = 0x1d, FW_FILTER_WR = 0x02, FW_ULPTX_WR = 0x04, FW_TP_WR = 0x05, FW_ETH_TX_PKT_WR = 0x08, + FW_ETH_TX_PKT2_WR = 0x44, FW_ETH_TX_PKTS_WR = 0x09, FW_ETH_TX_UO_WR = 0x1c, FW_EQ_FLUSH_WR = 0x1b, @@ -112,6 +116,8 @@ enum fw_wr_opcodes { FW_SCSI_TGT_ACC_WR = 0x35, FW_SCSI_TGT_XMIT_WR = 0x36, FW_SCSI_TGT_RSP_WR = 0x37, + FW_POFCOE_TCB_WR = 0x42, + FW_POFCOE_ULPTX_WR = 0x43, FW_LASTC2E_WR = 0x70 }; @@ -189,6 +195,24 @@ struct fw_wr_hdr { #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) +struct fw_frag_wr { + __be32 op_to_fragoff16; + __be32 flowid_len16; + __be64 r4; +}; + +#define S_FW_FRAG_WR_EOF 15 +#define M_FW_FRAG_WR_EOF 0x1 +#define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) +#define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) +#define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) + +#define S_FW_FRAG_WR_FRAGOFF16 8 +#define M_FW_FRAG_WR_FRAGOFF16 0x7f +#define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) +#define G_FW_FRAG_WR_FRAGOFF16(x) \ + (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) + /* * valid filter configurations for compressed tuple * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple @@ -534,6 +558,64 @@ struct fw_eth_tx_pkt_wr { #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) +struct fw_eth_tx_pkt2_wr { + __be32 op_immdlen; + __be32 equiq_to_len16; + __be32 r3; + __be32 L4ChkDisable_to_IpHdrLen; +}; + +#define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 +#define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff +#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) +#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ + (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) + +#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 +#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 +#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ + ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) +#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ + (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ + M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) +#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ + V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) + +#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 +#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 +#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ + ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) +#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ + (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ + M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) +#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ + V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) + +#define S_FW_ETH_TX_PKT2_WR_IVLAN 28 +#define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 +#define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) +#define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ + (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) +#define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) + +#define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 +#define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff +#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) +#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ + (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) + +#define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 +#define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf +#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) +#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ + (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) + +#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 +#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff +#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) +#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ + (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) + struct fw_eth_tx_pkts_wr { __be32 op_pkd; __be32 equiq_to_len16; @@ -547,12 +629,15 @@ struct fw_eth_tx_uo_wr { __be32 op_immdlen; __be32 equiq_to_len16; __be64 r3; - __be16 ethlen; + __u8 r4; + __u8 ethlen; __be16 iplen; - __be16 udplen; + __u8 udplen; + __u8 rtplen; + __be16 r5; __be16 mss; + __be16 schedpktsize; __be32 length; - __be32 r4; }; struct fw_eq_flush_wr { @@ -691,18 +776,19 @@ enum fw_flowc_mnem_uostate { }; enum fw_flowc_mnem { - FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ - FW_FLOWC_MNEM_CH, - FW_FLOWC_MNEM_PORT, - FW_FLOWC_MNEM_IQID, - FW_FLOWC_MNEM_SNDNXT, - FW_FLOWC_MNEM_RCVNXT, - FW_FLOWC_MNEM_SNDBUF, - FW_FLOWC_MNEM_MSS, - FW_FLOWC_MNEM_TXDATAPLEN_MAX, - FW_FLOWC_MNEM_TCPSTATE, - FW_FLOWC_MNEM_UOSTATE, - FW_FLOWC_MNEM_SCHEDCLASS, + FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ + FW_FLOWC_MNEM_CH = 1, + FW_FLOWC_MNEM_PORT = 2, + FW_FLOWC_MNEM_IQID = 3, + FW_FLOWC_MNEM_SNDNXT = 4, + FW_FLOWC_MNEM_RCVNXT = 5, + FW_FLOWC_MNEM_SNDBUF = 6, + FW_FLOWC_MNEM_MSS = 7, + FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, + FW_FLOWC_MNEM_TCPSTATE = 9, + FW_FLOWC_MNEM_UOSTATE = 10, + FW_FLOWC_MNEM_SCHEDCLASS = 11, + FW_FLOWC_MNEM_DCBPRIO = 12, }; struct fw_flowc_mnemval { @@ -1700,7 +1786,7 @@ struct fw_ri_wr { #define FW_FOISCSI_NAME_MAX_LEN 224 #define FW_FOISCSI_ALIAS_MAX_LEN 224 -#define FW_FOISCSI_MAX_CHAP_NAME_LEN 64 +#define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 #define FW_FOISCSI_INIT_NODE_MAX 8 enum fw_chnet_ifconf_wr_subop { @@ -1766,6 +1852,11 @@ struct fw_chnet_ifconf_wr { } param; }; +enum fw_foiscsi_node_type { + FW_FOISCSI_NODE_TYPE_INITIATOR = 0, + FW_FOISCSI_NODE_TYPE_TARGET, +}; + enum fw_foiscsi_session_type { FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, FW_FOISCSI_SESSION_TYPE_NORMAL, @@ -2128,7 +2219,7 @@ struct fw_foiscsi_ctrl_wr { __be32 r1; } sess_attr; struct fw_foiscsi_conn_attr { - __be32 hdigest_to_auth_policy; + __be32 hdigest_to_ddp_pgsz; __be32 max_rcv_dsl; __be32 ping_tmo; __be16 dst_port; @@ -2146,7 +2237,7 @@ struct fw_foiscsi_ctrl_wr { } conn_attr; __u8 tgt_name_len; __u8 r3[7]; - __u8 tgt_name[224]; + __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; }; #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 @@ -2231,6 +2322,13 @@ struct fw_foiscsi_ctrl_wr { (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) +#define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 +#define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 +#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ + ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) +#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ + (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) + struct fw_foiscsi_chap_wr { __be32 op_compl; __be32 flowid_len16; @@ -2238,14 +2336,11 @@ struct fw_foiscsi_chap_wr { __u8 status; __u8 id_len; __u8 sec_len; - __u8 tgt_id_len; - __u8 tgt_sec_len; + __u8 node_type; __be16 node_id; - __u8 r2; - __u8 chap_id[64]; - __u8 chap_sec[16]; - __u8 tgt_id[64]; - __u8 tgt_sec[16]; + __u8 r3[2]; + __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; + __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; }; /* @@ -2753,6 +2848,55 @@ struct fw_scsi_tgt_rsp_wr { #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) +struct fw_pofcoe_tcb_wr { + __be32 op_compl; + __be32 equiq_to_len16; + __be64 cookie; + __be32 tid_to_port; + __be16 x_id; + __be16 vlan_id; + __be32 s_id; + __be32 d_id; + __be32 tag; + __be32 xfer_len; + __be32 r4; + __be16 r5; + __be16 iqid; +}; + +#define S_FW_POFCOE_TCB_WR_TID 12 +#define M_FW_POFCOE_TCB_WR_TID 0xfffff +#define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) +#define G_FW_POFCOE_TCB_WR_TID(x) \ + (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) + +#define S_FW_POFCOE_TCB_WR_ALLO 4 +#define M_FW_POFCOE_TCB_WR_ALLOC 0x1 +#define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) +#define G_FW_POFCOE_TCB_WR_ALLOC(x) \ + (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) +#define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) + +#define S_FW_POFCOE_TCB_WR_FREE 3 +#define M_FW_POFCOE_TCB_WR_FREE 0x1 +#define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) +#define G_FW_POFCOE_TCB_WR_FREE(x) \ + (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) +#define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) + +#define S_FW_POFCOE_TCB_WR_PORT 0 +#define M_FW_POFCOE_TCB_WR_PORT 0x7 +#define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) +#define G_FW_POFCOE_TCB_WR_PORT(x) \ + (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) + +struct fw_pofcoe_ulptx_wr { + __be32 op_pkd; + __be32 equiq_to_len16; + __u64 cookie; +}; + + /* * ******************* * C O M M A N D s @@ -2903,8 +3047,12 @@ enum fw_ldst_addrspc { FW_LDST_ADDRSPC_MPS = 0x0020, FW_LDST_ADDRSPC_FUNC = 0x0028, FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, - FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, + FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ FW_LDST_ADDRSPC_LE = 0x0030, + FW_LDST_ADDRSPC_I2C = 0x0038, + FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, + FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, + FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, }; /* @@ -2984,17 +3132,26 @@ struct fw_ldst_cmd { __be16 nset_pkd; __be32 data[12]; } pcie; - struct fw_ldst_i2c { + struct fw_ldst_i2c_deprecated { __u8 pid_pkd; __u8 base; __u8 boffset; __u8 data; __be32 r9; - } i2c; + } i2c_deprecated; + struct fw_ldst_i2c { + __u8 pid; + __u8 did; + __u8 boffset; + __u8 blen; + __be32 r9; + __u8 data[48]; + } i2c; struct fw_ldst_le { - __be16 region; - __be16 nval; - __u32 val[12]; + __be32 index; + __be32 r9; + __u8 val[33]; + __u8 r11[7]; } le; } u; }; @@ -3299,6 +3456,8 @@ enum fw_caps_config_fcoe { FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, + FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, + FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, }; enum fw_memtype_cf { @@ -3307,6 +3466,7 @@ enum fw_memtype_cf { FW_MEMTYPE_CF_EXTMEM = 0x2, FW_MEMTYPE_CF_FLASH = 0x4, FW_MEMTYPE_CF_INTERNAL = 0x5, + FW_MEMTYPE_CF_EXTMEM1 = 0x6, }; struct fw_caps_config_cmd { @@ -3379,10 +3539,21 @@ enum fw_params_param_dev { FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, - FW_PARAMS_PARAM_DEV_FWREV = 0x0B, - FW_PARAMS_PARAM_DEV_TPREV = 0x0C, - FW_PARAMS_PARAM_DEV_CF = 0x0D, - FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, + FW_PARAMS_PARAM_DEV_FWREV = 0x0B, + FW_PARAMS_PARAM_DEV_TPREV = 0x0C, + FW_PARAMS_PARAM_DEV_CF = 0x0D, + FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, + FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, + FW_PARAMS_PARAM_DEV_LOAD = 0x10, + FW_PARAMS_PARAM_DEV_DIAG = 0x11, + FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ + FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD + */ + FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD + */ + FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, + FW_PARAMS_PARAM_DEV_MCINIT = 0x16, + FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, }; /* @@ -3427,7 +3598,8 @@ enum fw_params_param_pfvf { FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, - FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30 + FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, + FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 }; /* @@ -3436,10 +3608,12 @@ enum fw_params_param_pfvf { enum fw_params_param_dmaq { FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, + FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, - FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13 + FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, + FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, }; /* @@ -3457,6 +3631,16 @@ enum fw_params_param_dev_bypass { FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, }; +enum fw_params_phyfw_actions { + FW_PARAMS_PARAM_PHYFW_DOWNLOAD = 0x00, + FW_PARAMS_PARAM_PHYFW_VERSION = 0x01, +}; + +enum fw_params_param_dev_diag { + FW_PARAM_DEV_DIAG_TMP = 0x00, + FW_PARAM_DEV_DIAG_VDD = 0x01, +}; + #define S_FW_PARAMS_MNEM 24 #define M_FW_PARAMS_MNEM 0xff #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) @@ -4896,7 +5080,7 @@ struct fw_vi_cmd { __u8 portid_pkd; __u8 nmac; __u8 nmac0[6]; - __be16 rsssize_pkd; + __be16 norss_rsssize; __u8 nmac1[6]; __be16 idsiiq_pkd; __u8 nmac2[6]; @@ -4951,6 +5135,13 @@ struct fw_vi_cmd { #define G_FW_VI_CMD_PORTID(x) \ (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) +#define S_FW_VI_CMD_NORSS 11 +#define M_FW_VI_CMD_NORSS 0x1 +#define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) +#define G_FW_VI_CMD_NORSS(x) \ + (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) +#define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) + #define S_FW_VI_CMD_RSSSIZE 0 #define M_FW_VI_CMD_RSSSIZE 0x7ff #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) @@ -5139,6 +5330,13 @@ struct fw_vi_enable_cmd { (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) +#define S_FW_VI_ENABLE_CMD_DCB_INFO 28 +#define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 +#define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) +#define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ + (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) +#define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) + /* VI VF stats offset definitions */ #define VI_VF_NUM_STATS 16 enum fw_vi_stats_vf_index { @@ -5418,6 +5616,9 @@ enum fw_port_action { FW_PORT_ACTION_GET_PORT_INFO = 0x0003, FW_PORT_ACTION_L2_PPP_CFG = 0x0004, FW_PORT_ACTION_L2_DCB_CFG = 0x0005, + FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, + FW_PORT_ACTION_DCB_READ_RECV = 0x0007, + FW_PORT_ACTION_DCB_READ_DET = 0x0008, FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, @@ -5426,13 +5627,14 @@ enum fw_port_action { FW_PORT_ACTION_MAC_LPBK = 0x0022, FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023, FW_PORT_ACTION_L1_EXT_LPBK = 0x0026, + FW_PORT_ACTION_DIAGNOSTICS = 0x0027, FW_PORT_ACTION_PCS_LPBK = 0x0028, FW_PORT_ACTION_PHY_RESET = 0x0040, FW_PORT_ACTION_PMA_RESET = 0x0041, FW_PORT_ACTION_PCS_RESET = 0x0042, FW_PORT_ACTION_PHYXS_RESET = 0x0043, FW_PORT_ACTION_DTEXS_REEST = 0x0044, - FW_PORT_ACTION_AN_RESET = 0x0045 + FW_PORT_ACTION_AN_RESET = 0x0045, }; enum fw_port_l2cfg_ctlbf { @@ -5462,6 +5664,13 @@ enum fw_port_dcb_type { FW_PORT_DCB_TYPE_PRIORATE = 0x02, FW_PORT_DCB_TYPE_PFC = 0x03, FW_PORT_DCB_TYPE_APP_ID = 0x04, + FW_PORT_DCB_TYPE_CONTROL = 0x04, +}; + +enum fw_port_diag_ops { + FW_PORT_DIAGS_TEMP = 0x00, + FW_PORT_DIAGS_TX_POWER = 0x01, + FW_PORT_DIAGS_RX_POWER = 0x02, }; struct fw_port_cmd { @@ -5497,6 +5706,11 @@ struct fw_port_cmd { __be32 r8; __be64 r9; } info; + struct fw_port_diags { + __u8 diagop; + __u8 r[3]; + __be32 diagval; + } diags; union fw_port_dcb { struct fw_port_dcb_pgid { __u8 type; @@ -5533,6 +5747,12 @@ struct fw_port_cmd { __be16 protocolid; __be64 r12; } app_priority; + struct fw_port_dcb_control { + __u8 type; + __u8 all_syncd_pkd; + __be16 r10_lo[3]; + __be64 r11; + } control; } dcb; } u; }; @@ -5683,6 +5903,13 @@ struct fw_port_cmd { (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) +#define S_FW_PORT_CMD_ALL_SYNCD 7 +#define M_FW_PORT_CMD_ALL_SYNCD 0x1 +#define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) +#define G_FW_PORT_CMD_ALL_SYNCD(x) \ + (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) +#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) + /* * These are configured into the VPD and hence tools that generate * VPD may use this enumeration. @@ -5703,6 +5930,10 @@ enum fw_port_type { FW_PORT_TYPE_BP_AP = 10, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ FW_PORT_TYPE_BP4_AP = 11, + FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ + FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ + /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ + FW_PORT_TYPE_BP40_BA = 15, FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE }; @@ -5729,7 +5960,11 @@ enum fw_port_module_type { enum fw_port_mod_sub_type { FW_PORT_MOD_SUB_TYPE_NA, FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, - FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, + FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, + FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, + FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, + FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, + FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, /* * The following will never been in the VPD. They are TWINAX cable @@ -5745,10 +5980,13 @@ enum fw_port_mod_sub_type { /* link down reason codes (3b) */ enum fw_port_link_dn_rc { FW_PORT_LINK_DN_RC_NONE, - FW_PORT_LINK_DN_RC_REMFLT, - FW_PORT_LINK_DN_ANEG_F, - FW_PORT_LINK_DN_MS_RES_F, - FW_PORT_LINK_DN_UNKNOWN + FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ + FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ + FW_PORT_LINK_DN_RESERVED3, + FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ + FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ + FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ + FW_PORT_LINK_DN_RESERVED7 }; /* port stats */ @@ -6547,7 +6785,6 @@ enum fw_sched_params_level { FW_SCHED_PARAMS_LEVEL_CL_RL = 0, FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, FW_SCHED_PARAMS_LEVEL_CH_RL = 2, - FW_SCHED_PARAMS_LEVEL_CH_WRR = 3, }; enum fw_sched_params_mode { @@ -6574,6 +6811,8 @@ struct fw_sched_cmd { __u8 type; __u8 minmaxen; __u8 r3[5]; + __u8 nclasses[4]; + __be32 r4; } config; struct fw_sched_params { __u8 sc; @@ -6588,7 +6827,8 @@ struct fw_sched_cmd { __be32 max; __be16 weight; __be16 pktsize; - __be32 r4; + __be16 burstsize; + __be16 r4; } params; } u; }; @@ -6621,6 +6861,7 @@ enum fw_devlog_level { */ enum fw_devlog_facility { FW_DEVLOG_FACILITY_CORE = 0x00, + FW_DEVLOG_FACILITY_CF = 0x01, FW_DEVLOG_FACILITY_SCHED = 0x02, FW_DEVLOG_FACILITY_TIMER = 0x04, FW_DEVLOG_FACILITY_RES = 0x06, @@ -6687,19 +6928,35 @@ struct fw_devlog_cmd { M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) enum fw_watchdog_actions { - FW_WATCHDOG_ACTION_FLR = 0x1, - FW_WATCHDOG_ACTION_BYPASS = 0x2, + FW_WATCHDOG_ACTION_SHUTDOWN = 0, + FW_WATCHDOG_ACTION_FLR = 1, + FW_WATCHDOG_ACTION_BYPASS = 2, + FW_WATCHDOG_ACTION_TMPCHK = 3, + + FW_WATCHDOG_ACTION_MAX = 4, }; #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 struct fw_watchdog_cmd { - __be32 op_to_write; + __be32 op_to_vfn; __be32 retval_len16; __be32 timeout; - __be32 actions; + __be32 action; }; +#define S_FW_WATCHDOG_CMD_PFN 8 +#define M_FW_WATCHDOG_CMD_PFN 0x7 +#define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) +#define G_FW_WATCHDOG_CMD_PFN(x) \ + (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) + +#define S_FW_WATCHDOG_CMD_VFN 0 +#define M_FW_WATCHDOG_CMD_VFN 0xff +#define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) +#define G_FW_WATCHDOG_CMD_VFN(x) \ + (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) + struct fw_clip_cmd { __be32 op_to_write; __be32 alloc_to_len16; @@ -7145,10 +7402,10 @@ struct fw_fcoe_fcf_cmd { */ enum fw_error_type { - FW_ERROR_TYPE_EXCEPTION = 0x0, - FW_ERROR_TYPE_HWMODULE = 0x1, - FW_ERROR_TYPE_WR = 0x2, - FW_ERROR_TYPE_ACL = 0x3, + FW_ERROR_TYPE_EXCEPTION = 0x0, + FW_ERROR_TYPE_HWMODULE = 0x1, + FW_ERROR_TYPE_WR = 0x2, + FW_ERROR_TYPE_ACL = 0x3, }; struct fw_error_cmd { @@ -7259,9 +7516,19 @@ struct fw_debug_cmd { * ************************************ */ +enum pcie_fw_eval { + PCIE_FW_EVAL_CRASH = 0, + PCIE_FW_EVAL_PREP = 1, + PCIE_FW_EVAL_CONF = 2, + PCIE_FW_EVAL_INIT = 3, + PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, + PCIE_FW_EVAL_OVERHEAT = 5, + PCIE_FW_EVAL_DEVICESHUTDOWN = 6, +}; + /* * Register definitions for the PCIE_FW register which the firmware uses - * to restain status across RESETs. This register should be considered + * to retain status across RESETs. This register should be considered * as a READ-ONLY register for Host Software and only to be used to * track firmware initialization/error state, etc. */ @@ -7283,6 +7550,11 @@ struct fw_debug_cmd { #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) +#define S_PCIE_FW_EVAL 24 +#define M_PCIE_FW_EVAL 0x7 +#define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) +#define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) + #define S_PCIE_FW_STAGE 21 #define M_PCIE_FW_STAGE 0x7 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) @@ -7362,11 +7634,11 @@ struct fw_hdr { __u8 intfver_ri; __u8 intfver_iscsipdu; __u8 intfver_iscsi; + __u8 intfver_fcoepdu; __u8 intfver_fcoe; - __u8 reserved2; + __u32 reserved2; __u32 reserved3; - __u32 reserved4; - __u32 reserved5; + __u32 magic; /* runtime or bootstrap fw */ __be32 flags; __be32 reserved6[23]; }; @@ -7404,16 +7676,43 @@ enum fw_hdr_chip { #define G_FW_HDR_FW_VER_BUILD(x) \ (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) -enum fw_hdr_intfver { - FW_HDR_INTFVER_NIC = 0x00, - FW_HDR_INTFVER_VNIC = 0x00, - FW_HDR_INTFVER_OFLD = 0x00, - FW_HDR_INTFVER_RI = 0x00, - FW_HDR_INTFVER_ISCSIPDU = 0x00, - FW_HDR_INTFVER_ISCSI = 0x00, - FW_HDR_INTFVER_FCOE = 0x00, +enum { + T4FW_VERSION_MAJOR = 0x01, + T4FW_VERSION_MINOR = 0x08, + T4FW_VERSION_MICRO = 0x18, + T4FW_VERSION_BUILD = 0x00, + + T5FW_VERSION_MAJOR = 0x01, + T5FW_VERSION_MINOR = 0x08, + T5FW_VERSION_MICRO = 0x1b, + T5FW_VERSION_BUILD = 0x00, +}; + +enum { + T4FW_HDR_INTFVER_NIC = 0x00, + T4FW_HDR_INTFVER_VNIC = 0x00, + T4FW_HDR_INTFVER_OFLD = 0x00, + T4FW_HDR_INTFVER_RI = 0x00, + T4FW_HDR_INTFVER_ISCSIPDU = 0x00, + T4FW_HDR_INTFVER_ISCSI = 0x00, + T4FW_HDR_INTFVER_FCOEPDU = 0x00, + T4FW_HDR_INTFVER_FCOE = 0x00, + + T5FW_HDR_INTFVER_NIC = 0x00, + T5FW_HDR_INTFVER_VNIC = 0x00, + T5FW_HDR_INTFVER_OFLD = 0x00, + T5FW_HDR_INTFVER_RI = 0x00, + T5FW_HDR_INTFVER_ISCSIPDU = 0x00, + T5FW_HDR_INTFVER_ISCSI = 0x00, + T5FW_HDR_INTFVER_FCOEPDU = 0x00, + T5FW_HDR_INTFVER_FCOE = 0x00, }; +enum { + FW_HDR_MAGIC_RUNTIME = 0x00000000, + FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, +}; + enum fw_hdr_flags { FW_HDR_FLAGS_RESET_HALT = 0x00000001, }; diff --git a/usr/src/uts/common/io/cxgbe/firmware/t5_cfg.c b/usr/src/uts/common/io/cxgbe/firmware/t5_cfg.c new file mode 100644 index 0000000000..3fb2197614 --- /dev/null +++ b/usr/src/uts/common/io/cxgbe/firmware/t5_cfg.c @@ -0,0 +1,1390 @@ +/* + * Automatically generated file. + */ + +unsigned char t5cfg_data[] = { + 0x23, 0x20, 0x43, 0x68, 0x65, 0x6c, 0x73, 0x69, 0x6f, 0x20, 0x54, 0x35, 0x20, 0x46, 0x61, 0x63, + 0x74, 0x6f, 0x72, 0x79, 0x20, 0x44, 0x65, 0x66, 0x61, 0x75, 0x6c, 0x74, 0x20, 0x63, 0x6f, 0x6e, + 0x66, 0x69, 0x67, 0x75, 0x72, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x20, 0x66, 0x69, 0x6c, 0x65, 0x2e, + 0x0a, 0x23, 0x0a, 0x23, 0x20, 0x43, 0x6f, 0x70, 0x79, 0x72, 0x69, 0x67, 0x68, 0x74, 0x20, 0x28, + 0x43, 0x29, 0x20, 0x32, 0x30, 0x31, 0x30, 0x2d, 0x32, 0x30, 0x31, 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+ */ + +unsigned char t5fw_data[] = { + 0x00, 0x01, 0x04, 0x8e, 0x01, 0x0f, 0x25, 0x00, 0x00, 0x01, 0x04, 0x09, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x04, 0x6f, 0x04, 0x7e, 0x04, 0x87, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + +}; +int t5fw_size = sizeof(t5fw_data); diff --git a/usr/src/uts/common/io/cxgbe/firmware/t5_fw.h b/usr/src/uts/common/io/cxgbe/firmware/t5_fw.h new file mode 100644 index 0000000000..b58499a1b0 --- /dev/null +++ b/usr/src/uts/common/io/cxgbe/firmware/t5_fw.h @@ -0,0 +1,16 @@ +/* + * Automatically generated file. + */ + +#ifndef __T5FW_H +#define __T5FW_H + +#define T5FW_VERSION_MAJOR 1 +#define T5FW_VERSION_MINOR 15 +#define T5FW_VERSION_MICRO 37 +#define T5FW_VERSION_BUILD 0 + +extern unsigned char t5fw_data[]; +extern int t5fw_size; + +#endif diff --git a/usr/src/uts/common/io/cxgbe/t4nex/adapter.c b/usr/src/uts/common/io/cxgbe/t4nex/adapter.c index ce2497b5d8..b05ec3f15f 100644 --- a/usr/src/uts/common/io/cxgbe/t4nex/adapter.c +++ b/usr/src/uts/common/io/cxgbe/t4nex/adapter.c @@ -110,6 +110,13 @@ iq_to_rxq(struct sge_iq *iq) return (container_of(iq, struct sge_rxq, iq)); } +bool +is_40G_port(const struct port_info *pi) +{ + return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); +} + +#ifndef TCP_OFFLOAD_DISABLE int t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m) { @@ -120,3 +127,4 @@ t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m) TXQ_UNLOCK(wrq); return (rc); } +#endif diff --git a/usr/src/uts/common/io/cxgbe/t4nex/adapter.h b/usr/src/uts/common/io/cxgbe/t4nex/adapter.h index 64ab9892a4..c88fa58bd8 100644 --- a/usr/src/uts/common/io/cxgbe/t4nex/adapter.h +++ b/usr/src/uts/common/io/cxgbe/t4nex/adapter.h @@ -203,6 +203,9 @@ enum { EQ_STARTED = (1 << 8), /* started */ }; +/* Listed in order of preference. Update t4_sysctls too if you change these */ +enum {DOORBELL_UDB=0x1 , DOORBELL_WCWR=0x2, DOORBELL_UDBWC=0x4, DOORBELL_KDB=0x8}; + /* * Egress Queue: driver is producer, T4 is consumer. * @@ -218,6 +221,9 @@ struct sge_eq { struct tx_desc *desc; /* KVA of descriptor ring */ uint64_t ba; /* bus address of descriptor ring */ struct sge_qstat *spg; /* status page, for convenience */ + int doorbells; + volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ + u_int udb_qid; /* relative qid within the doorbell page */ uint16_t cap; /* max # of desc, for convenience */ uint16_t avail; /* available descriptors, for convenience */ uint16_t qsize; /* size (# of entries) of the queue */ @@ -363,6 +369,7 @@ struct sge_wrq { struct sge { int fl_starve_threshold; + int s_qpp; int nrxq; /* total rx queues (all ports and the rest) */ int ntxq; /* total tx queues (all ports and the rest) */ @@ -374,7 +381,9 @@ struct sge { int neq; /* total egress queues */ struct sge_iq fwq; /* Firmware event queue */ +#ifndef TCP_OFFLOAD_DISABLE struct sge_wrq mgmtq; /* Management queue (Control queue) */ +#endif struct sge_txq *txq; /* NIC tx queues */ struct sge_rxq *rxq; /* NIC rx queues */ #ifndef TCP_OFFLOAD_DISABLE @@ -423,11 +432,14 @@ struct driver_properties { int timer_val[SGE_NTIMERS]; int counter_val[SGE_NCOUNTERS]; + + int wc; }; struct rss_header; typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, mblk_t *); +typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); struct adapter { SLIST_ENTRY(adapter) link; @@ -445,6 +457,9 @@ struct adapter { /* MMIO register access handle */ ddi_acc_handle_t regh; caddr_t regp; + /* BAR1 register access handle */ + ddi_acc_handle_t reg1h; + caddr_t reg1p; /* Interrupt information */ int intr_type; @@ -455,6 +470,7 @@ struct adapter { struct driver_properties props; kstat_t *ksp; + kstat_t *ksp_stat; struct sge sge; @@ -465,6 +481,7 @@ struct adapter { struct l2t_data *l2t; /* L2 table */ struct tid_info tids; + int doorbells; int registered_device_map; int open_device_map; int flags; @@ -488,6 +505,7 @@ struct adapter { uint16_t iscsicaps; uint16_t fcoecaps; + fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ kmutex_t lock; @@ -578,6 +596,7 @@ void t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val); struct port_info *adap2pinfo(struct adapter *sc, int idx); void t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]); bool is_10G_port(const struct port_info *pi); +bool is_40G_port(const struct port_info *pi); struct sge_rxq *iq_to_rxq(struct sge_iq *iq); int t4_wrq_tx(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m); @@ -591,6 +610,7 @@ int port_full_uninit(struct port_info *pi); void enable_port_queues(struct port_info *pi); void disable_port_queues(struct port_info *pi); int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h); +int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); void t4_iterate(void (*func)(int, void *), void *arg); /* t4_sge.c */ @@ -603,7 +623,11 @@ uint_t t4_intr_all(caddr_t arg1, caddr_t arg2); uint_t t4_intr(caddr_t arg1, caddr_t arg2); uint_t t4_intr_err(caddr_t arg1, caddr_t arg2); int t4_mgmt_tx(struct adapter *sc, mblk_t *m); +#ifndef TCP_OFFLOAD_DISABLE int t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m0); +#endif +void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); +uint32_t position_memwin(struct adapter *, int, uint32_t); mblk_t *t4_eth_tx(struct port_info *pi, struct sge_txq *txq, mblk_t *frame); int t4_alloc_tx_maps(struct adapter *sc, struct tx_maps *txmaps, int count, diff --git a/usr/src/uts/common/io/cxgbe/t4nex/offload.h b/usr/src/uts/common/io/cxgbe/t4nex/offload.h index fa23cb9b63..6358e0cda0 100644 --- a/usr/src/uts/common/io/cxgbe/t4nex/offload.h +++ b/usr/src/uts/common/io/cxgbe/t4nex/offload.h @@ -91,8 +91,8 @@ struct tid_info { }; struct t4_range { - unsigned int start; - unsigned int size; + u_int start; + u_int size; }; struct t4_virt_res { /* virtualized HW resources */ @@ -101,6 +101,7 @@ struct t4_virt_res { /* virtualized HW resources */ struct t4_range stag; struct t4_range rq; struct t4_range pbl; + struct t4_range l2t; }; struct adapter; diff --git a/usr/src/uts/common/io/cxgbe/t4nex/osdep.h b/usr/src/uts/common/io/cxgbe/t4nex/osdep.h index 70946b06c8..3e8df2b094 100644 --- a/usr/src/uts/common/io/cxgbe/t4nex/osdep.h +++ b/usr/src/uts/common/io/cxgbe/t4nex/osdep.h @@ -118,6 +118,7 @@ #define PCI_EXP_LNKSTA PCIE_LINKSTS #define PCI_EXP_LNKSTA_CLS PCIE_LINKSTS_SPEED_MASK #define PCI_EXP_LNKSTA_NLW PCIE_LINKSTS_NEG_WIDTH_MASK +#define PCI_EXP_DEVCTL2 0x28 #define PCI_VPD_ADDR 2 #define PCI_VPD_ADDR_F 0x8000 @@ -215,6 +216,7 @@ typedef boolean_t bool; #define SPEED_100 100 #define SPEED_1000 1000 #define SPEED_10000 10000 +#define SPEED_40000 40000 #define DUPLEX_HALF 0 #define DUPLEX_FULL 1 diff --git a/usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c b/usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c index 94c2b33d3a..7e5e2d541d 100644 --- a/usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c +++ b/usr/src/uts/common/io/cxgbe/t4nex/t4_ioctl.c @@ -36,6 +36,7 @@ static void reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start, static int regdump(struct adapter *sc, void *data, int flags); static int get_sge_context(struct adapter *sc, void *data, int flags); static int get_devlog(struct adapter *sc, void *data, int flags); +static int validate_mem_range(struct adapter *, uint32_t, int); static int read_card_mem(struct adapter *sc, void *data, int flags); static int read_tid_tab(struct adapter *sc, void *data, int flags); static int read_mbox(struct adapter *sc, void *data, int flags); @@ -150,13 +151,27 @@ reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start, *p++ = t4_read_reg(sc, start); } +/* + * Return a version number to identify the type of adapter. The scheme is: + * - bits 0..9: chip version + * - bits 10..15: chip revision + * - bits 16..23: register dump version + */ +static inline +unsigned int mk_adap_vers(const struct adapter *sc) +{ + return CHELSIO_CHIP_VERSION(sc->params.chip) | + (CHELSIO_CHIP_RELEASE(sc->params.chip) << 10) | (1 << 16); +} + static int regdump(struct adapter *sc, void *data, int flags) { struct t4_regdump r; uint8_t *buf; - int rc = 0, i; - static const unsigned int reg_ranges[] = { + static const unsigned int *reg_ranges; + int rc = 0, arr_size = 0, buf_size = 0, i; + static const unsigned int t4_reg_ranges[] = { 0x1008, 0x1108, 0x1180, 0x11b4, 0x11fc, 0x123c, @@ -374,6 +389,781 @@ regdump(struct adapter *sc, void *data, int flags) 0x27e00, 0x27e04 }; + static const unsigned int t5_reg_ranges[] = { + 0x1008, 0x10c0, + 0x10cc, 0x10f8, + 0x1100, 0x1100, + 0x110c, 0x1148, + 0x1180, 0x1184, + 0x1190, 0x1194, + 0x11a0, 0x11a4, + 0x11b0, 0x11b4, + 0x11fc, 0x123c, + 0x1280, 0x173c, + 0x1800, 0x18fc, + 0x3000, 0x3028, + 0x3060, 0x30b0, + 0x30b8, 0x30d8, + 0x30e0, 0x30fc, + 0x3140, 0x357c, + 0x35a8, 0x35cc, + 0x35ec, 0x35ec, + 0x3600, 0x5624, + 0x56cc, 0x56ec, + 0x56f4, 0x5720, + 0x5728, 0x575c, + 0x580c, 0x5814, + 0x5890, 0x589c, + 0x58a4, 0x58ac, + 0x58b8, 0x58bc, + 0x5940, 0x59c8, + 0x59d0, 0x59dc, + 0x59fc, 0x5a18, + 0x5a60, 0x5a70, + 0x5a80, 0x5a9c, + 0x5b94, 0x5bfc, + 0x6000, 0x6020, + 0x6028, 0x6040, + 0x6058, 0x609c, + 0x60a8, 0x614c, + 0x7700, 0x7798, + 0x77c0, 0x78fc, + 0x7b00, 0x7b58, + 0x7b60, 0x7b84, + 0x7b8c, 0x7c54, + 0x7d00, 0x7d38, + 0x7d40, 0x7d80, + 0x7d8c, 0x7ddc, + 0x7de4, 0x7e04, + 0x7e10, 0x7e1c, + 0x7e24, 0x7e38, + 0x7e40, 0x7e44, + 0x7e4c, 0x7e78, + 0x7e80, 0x7edc, + 0x7ee8, 0x7efc, + 0x8dc0, 0x8de0, + 0x8df8, 0x8e04, + 0x8e10, 0x8e84, + 0x8ea0, 0x8f84, + 0x8fc0, 0x9058, + 0x9060, 0x9060, + 0x9068, 0x90f8, + 0x9400, 0x9408, + 0x9410, 0x9470, + 0x9600, 0x9600, + 0x9608, 0x9638, + 0x9640, 0x96f4, + 0x9800, 0x9808, + 0x9820, 0x983c, + 0x9850, 0x9864, + 0x9c00, 0x9c6c, + 0x9c80, 0x9cec, + 0x9d00, 0x9d6c, + 0x9d80, 0x9dec, + 0x9e00, 0x9e6c, + 0x9e80, 0x9eec, + 0x9f00, 0x9f6c, + 0x9f80, 0xa020, + 0xd004, 0xd004, + 0xd010, 0xd03c, + 0xdfc0, 0xdfe0, + 0xe000, 0x1106c, + 0x11074, 0x11088, + 0x1109c, 0x1117c, + 0x11190, 0x11204, + 0x19040, 0x1906c, + 0x19078, 0x19080, + 0x1908c, 0x190e8, + 0x190f0, 0x190f8, + 0x19100, 0x19110, + 0x19120, 0x19124, + 0x19150, 0x19194, + 0x1919c, 0x191b0, + 0x191d0, 0x191e8, + 0x19238, 0x19290, + 0x193f8, 0x19428, + 0x19430, 0x19444, + 0x1944c, 0x1946c, + 0x19474, 0x19474, + 0x19490, 0x194cc, + 0x194f0, 0x194f8, + 0x19c00, 0x19c08, + 0x19c10, 0x19c60, + 0x19c94, 0x19ce4, + 0x19cf0, 0x19d40, + 0x19d50, 0x19d94, + 0x19da0, 0x19de8, + 0x19df0, 0x19e10, + 0x19e50, 0x19e90, + 0x19ea0, 0x19f24, + 0x19f34, 0x19f34, + 0x19f40, 0x19f50, + 0x19f90, 0x19fb4, + 0x19fc4, 0x19fe4, + 0x1a000, 0x1a004, + 0x1a010, 0x1a06c, + 0x1a0b0, 0x1a0e4, + 0x1a0ec, 0x1a0f8, + 0x1a100, 0x1a108, + 0x1a114, 0x1a120, + 0x1a128, 0x1a130, + 0x1a138, 0x1a138, + 0x1a190, 0x1a1c4, + 0x1a1fc, 0x1a1fc, + 0x1e008, 0x1e00c, + 0x1e040, 0x1e044, + 0x1e04c, 0x1e04c, + 0x1e284, 0x1e290, + 0x1e2c0, 0x1e2c0, + 0x1e2e0, 0x1e2e0, + 0x1e300, 0x1e384, + 0x1e3c0, 0x1e3c8, + 0x1e408, 0x1e40c, + 0x1e440, 0x1e444, + 0x1e44c, 0x1e44c, + 0x1e684, 0x1e690, + 0x1e6c0, 0x1e6c0, + 0x1e6e0, 0x1e6e0, + 0x1e700, 0x1e784, + 0x1e7c0, 0x1e7c8, + 0x1e808, 0x1e80c, + 0x1e840, 0x1e844, + 0x1e84c, 0x1e84c, + 0x1ea84, 0x1ea90, + 0x1eac0, 0x1eac0, + 0x1eae0, 0x1eae0, + 0x1eb00, 0x1eb84, + 0x1ebc0, 0x1ebc8, + 0x1ec08, 0x1ec0c, + 0x1ec40, 0x1ec44, + 0x1ec4c, 0x1ec4c, + 0x1ee84, 0x1ee90, + 0x1eec0, 0x1eec0, + 0x1eee0, 0x1eee0, + 0x1ef00, 0x1ef84, + 0x1efc0, 0x1efc8, + 0x1f008, 0x1f00c, + 0x1f040, 0x1f044, + 0x1f04c, 0x1f04c, + 0x1f284, 0x1f290, + 0x1f2c0, 0x1f2c0, + 0x1f2e0, 0x1f2e0, + 0x1f300, 0x1f384, + 0x1f3c0, 0x1f3c8, + 0x1f408, 0x1f40c, + 0x1f440, 0x1f444, + 0x1f44c, 0x1f44c, + 0x1f684, 0x1f690, + 0x1f6c0, 0x1f6c0, + 0x1f6e0, 0x1f6e0, + 0x1f700, 0x1f784, + 0x1f7c0, 0x1f7c8, + 0x1f808, 0x1f80c, + 0x1f840, 0x1f844, + 0x1f84c, 0x1f84c, + 0x1fa84, 0x1fa90, + 0x1fac0, 0x1fac0, + 0x1fae0, 0x1fae0, + 0x1fb00, 0x1fb84, + 0x1fbc0, 0x1fbc8, + 0x1fc08, 0x1fc0c, + 0x1fc40, 0x1fc44, + 0x1fc4c, 0x1fc4c, + 0x1fe84, 0x1fe90, + 0x1fec0, 0x1fec0, + 0x1fee0, 0x1fee0, + 0x1ff00, 0x1ff84, + 0x1ffc0, 0x1ffc8, + 0x30000, 0x30030, + 0x30038, 0x30038, + 0x30040, 0x30040, + 0x30100, 0x30144, + 0x30190, 0x301a0, + 0x301a8, 0x301b8, + 0x301c4, 0x301c8, + 0x301d0, 0x301d0, + 0x30200, 0x30318, + 0x30400, 0x304b4, + 0x304c0, 0x3052c, + 0x30540, 0x3061c, + 0x30800, 0x30828, + 0x30834, 0x30834, + 0x308c0, 0x30908, + 0x30910, 0x309ac, + 0x30a00, 0x30a14, + 0x30a1c, 0x30a2c, + 0x30a44, 0x30a50, + 0x30a74, 0x30a74, + 0x30a7c, 0x30afc, + 0x30b08, 0x30c24, + 0x30d00, 0x30d00, + 0x30d08, 0x30d14, + 0x30d1c, 0x30d20, + 0x30d3c, 0x30d3c, + 0x30d48, 0x30d50, + 0x31200, 0x3120c, + 0x31220, 0x31220, + 0x31240, 0x31240, + 0x31600, 0x3160c, + 0x31a00, 0x31a1c, + 0x31e00, 0x31e20, + 0x31e38, 0x31e3c, + 0x31e80, 0x31e80, + 0x31e88, 0x31ea8, + 0x31eb0, 0x31eb4, + 0x31ec8, 0x31ed4, + 0x31fb8, 0x32004, + 0x32200, 0x32200, + 0x32208, 0x32240, + 0x32248, 0x32280, + 0x32288, 0x322c0, + 0x322c8, 0x322fc, + 0x32600, 0x32630, + 0x32a00, 0x32abc, + 0x32b00, 0x32b10, + 0x32b20, 0x32b30, + 0x32b40, 0x32b50, + 0x32b60, 0x32b70, + 0x33000, 0x33028, + 0x33030, 0x33048, + 0x33060, 0x33068, + 0x33070, 0x3309c, + 0x330f0, 0x33128, + 0x33130, 0x33148, + 0x33160, 0x33168, + 0x33170, 0x3319c, + 0x331f0, 0x33238, + 0x33240, 0x33240, + 0x33248, 0x33250, + 0x3325c, 0x33264, + 0x33270, 0x332b8, + 0x332c0, 0x332e4, + 0x332f8, 0x33338, + 0x33340, 0x33340, + 0x33348, 0x33350, + 0x3335c, 0x33364, + 0x33370, 0x333b8, + 0x333c0, 0x333e4, + 0x333f8, 0x33428, + 0x33430, 0x33448, + 0x33460, 0x33468, + 0x33470, 0x3349c, + 0x334f0, 0x33528, + 0x33530, 0x33548, + 0x33560, 0x33568, + 0x33570, 0x3359c, + 0x335f0, 0x33638, + 0x33640, 0x33640, + 0x33648, 0x33650, + 0x3365c, 0x33664, + 0x33670, 0x336b8, + 0x336c0, 0x336e4, + 0x336f8, 0x33738, + 0x33740, 0x33740, + 0x33748, 0x33750, + 0x3375c, 0x33764, + 0x33770, 0x337b8, + 0x337c0, 0x337e4, + 0x337f8, 0x337fc, + 0x33814, 0x33814, + 0x3382c, 0x3382c, + 0x33880, 0x3388c, + 0x338e8, 0x338ec, + 0x33900, 0x33928, + 0x33930, 0x33948, + 0x33960, 0x33968, + 0x33970, 0x3399c, + 0x339f0, 0x33a38, + 0x33a40, 0x33a40, + 0x33a48, 0x33a50, + 0x33a5c, 0x33a64, + 0x33a70, 0x33ab8, + 0x33ac0, 0x33ae4, + 0x33af8, 0x33b10, + 0x33b28, 0x33b28, + 0x33b3c, 0x33b50, + 0x33bf0, 0x33c10, + 0x33c28, 0x33c28, + 0x33c3c, 0x33c50, + 0x33cf0, 0x33cfc, + 0x34000, 0x34030, + 0x34038, 0x34038, + 0x34040, 0x34040, + 0x34100, 0x34144, + 0x34190, 0x341a0, + 0x341a8, 0x341b8, + 0x341c4, 0x341c8, + 0x341d0, 0x341d0, + 0x34200, 0x34318, + 0x34400, 0x344b4, + 0x344c0, 0x3452c, + 0x34540, 0x3461c, + 0x34800, 0x34828, + 0x34834, 0x34834, + 0x348c0, 0x34908, + 0x34910, 0x349ac, + 0x34a00, 0x34a14, + 0x34a1c, 0x34a2c, + 0x34a44, 0x34a50, + 0x34a74, 0x34a74, + 0x34a7c, 0x34afc, + 0x34b08, 0x34c24, + 0x34d00, 0x34d00, + 0x34d08, 0x34d14, + 0x34d1c, 0x34d20, + 0x34d3c, 0x34d3c, + 0x34d48, 0x34d50, + 0x35200, 0x3520c, + 0x35220, 0x35220, + 0x35240, 0x35240, + 0x35600, 0x3560c, + 0x35a00, 0x35a1c, + 0x35e00, 0x35e20, + 0x35e38, 0x35e3c, + 0x35e80, 0x35e80, + 0x35e88, 0x35ea8, + 0x35eb0, 0x35eb4, + 0x35ec8, 0x35ed4, + 0x35fb8, 0x36004, + 0x36200, 0x36200, + 0x36208, 0x36240, + 0x36248, 0x36280, + 0x36288, 0x362c0, + 0x362c8, 0x362fc, + 0x36600, 0x36630, + 0x36a00, 0x36abc, + 0x36b00, 0x36b10, + 0x36b20, 0x36b30, + 0x36b40, 0x36b50, + 0x36b60, 0x36b70, + 0x37000, 0x37028, + 0x37030, 0x37048, + 0x37060, 0x37068, + 0x37070, 0x3709c, + 0x370f0, 0x37128, + 0x37130, 0x37148, + 0x37160, 0x37168, + 0x37170, 0x3719c, + 0x371f0, 0x37238, + 0x37240, 0x37240, + 0x37248, 0x37250, + 0x3725c, 0x37264, + 0x37270, 0x372b8, + 0x372c0, 0x372e4, + 0x372f8, 0x37338, + 0x37340, 0x37340, + 0x37348, 0x37350, + 0x3735c, 0x37364, + 0x37370, 0x373b8, + 0x373c0, 0x373e4, + 0x373f8, 0x37428, + 0x37430, 0x37448, + 0x37460, 0x37468, + 0x37470, 0x3749c, + 0x374f0, 0x37528, + 0x37530, 0x37548, + 0x37560, 0x37568, + 0x37570, 0x3759c, + 0x375f0, 0x37638, + 0x37640, 0x37640, + 0x37648, 0x37650, + 0x3765c, 0x37664, + 0x37670, 0x376b8, + 0x376c0, 0x376e4, + 0x376f8, 0x37738, + 0x37740, 0x37740, + 0x37748, 0x37750, + 0x3775c, 0x37764, + 0x37770, 0x377b8, + 0x377c0, 0x377e4, + 0x377f8, 0x377fc, + 0x37814, 0x37814, + 0x3782c, 0x3782c, + 0x37880, 0x3788c, + 0x378e8, 0x378ec, + 0x37900, 0x37928, + 0x37930, 0x37948, + 0x37960, 0x37968, + 0x37970, 0x3799c, + 0x379f0, 0x37a38, + 0x37a40, 0x37a40, + 0x37a48, 0x37a50, + 0x37a5c, 0x37a64, + 0x37a70, 0x37ab8, + 0x37ac0, 0x37ae4, + 0x37af8, 0x37b10, + 0x37b28, 0x37b28, + 0x37b3c, 0x37b50, + 0x37bf0, 0x37c10, + 0x37c28, 0x37c28, + 0x37c3c, 0x37c50, + 0x37cf0, 0x37cfc, + 0x38000, 0x38030, + 0x38038, 0x38038, + 0x38040, 0x38040, + 0x38100, 0x38144, + 0x38190, 0x381a0, + 0x381a8, 0x381b8, + 0x381c4, 0x381c8, + 0x381d0, 0x381d0, + 0x38200, 0x38318, + 0x38400, 0x384b4, + 0x384c0, 0x3852c, + 0x38540, 0x3861c, + 0x38800, 0x38828, + 0x38834, 0x38834, + 0x388c0, 0x38908, + 0x38910, 0x389ac, + 0x38a00, 0x38a14, + 0x38a1c, 0x38a2c, + 0x38a44, 0x38a50, + 0x38a74, 0x38a74, + 0x38a7c, 0x38afc, + 0x38b08, 0x38c24, + 0x38d00, 0x38d00, + 0x38d08, 0x38d14, + 0x38d1c, 0x38d20, + 0x38d3c, 0x38d3c, + 0x38d48, 0x38d50, + 0x39200, 0x3920c, + 0x39220, 0x39220, + 0x39240, 0x39240, + 0x39600, 0x3960c, + 0x39a00, 0x39a1c, + 0x39e00, 0x39e20, + 0x39e38, 0x39e3c, + 0x39e80, 0x39e80, + 0x39e88, 0x39ea8, + 0x39eb0, 0x39eb4, + 0x39ec8, 0x39ed4, + 0x39fb8, 0x3a004, + 0x3a200, 0x3a200, + 0x3a208, 0x3a240, + 0x3a248, 0x3a280, + 0x3a288, 0x3a2c0, + 0x3a2c8, 0x3a2fc, + 0x3a600, 0x3a630, + 0x3aa00, 0x3aabc, + 0x3ab00, 0x3ab10, + 0x3ab20, 0x3ab30, + 0x3ab40, 0x3ab50, + 0x3ab60, 0x3ab70, + 0x3b000, 0x3b028, + 0x3b030, 0x3b048, + 0x3b060, 0x3b068, + 0x3b070, 0x3b09c, + 0x3b0f0, 0x3b128, + 0x3b130, 0x3b148, + 0x3b160, 0x3b168, + 0x3b170, 0x3b19c, + 0x3b1f0, 0x3b238, + 0x3b240, 0x3b240, + 0x3b248, 0x3b250, + 0x3b25c, 0x3b264, + 0x3b270, 0x3b2b8, + 0x3b2c0, 0x3b2e4, + 0x3b2f8, 0x3b338, + 0x3b340, 0x3b340, + 0x3b348, 0x3b350, + 0x3b35c, 0x3b364, + 0x3b370, 0x3b3b8, + 0x3b3c0, 0x3b3e4, + 0x3b3f8, 0x3b428, + 0x3b430, 0x3b448, + 0x3b460, 0x3b468, + 0x3b470, 0x3b49c, + 0x3b4f0, 0x3b528, + 0x3b530, 0x3b548, + 0x3b560, 0x3b568, + 0x3b570, 0x3b59c, + 0x3b5f0, 0x3b638, + 0x3b640, 0x3b640, + 0x3b648, 0x3b650, + 0x3b65c, 0x3b664, + 0x3b670, 0x3b6b8, + 0x3b6c0, 0x3b6e4, + 0x3b6f8, 0x3b738, + 0x3b740, 0x3b740, + 0x3b748, 0x3b750, + 0x3b75c, 0x3b764, + 0x3b770, 0x3b7b8, + 0x3b7c0, 0x3b7e4, + 0x3b7f8, 0x3b7fc, + 0x3b814, 0x3b814, + 0x3b82c, 0x3b82c, + 0x3b880, 0x3b88c, + 0x3b8e8, 0x3b8ec, + 0x3b900, 0x3b928, + 0x3b930, 0x3b948, + 0x3b960, 0x3b968, + 0x3b970, 0x3b99c, + 0x3b9f0, 0x3ba38, + 0x3ba40, 0x3ba40, + 0x3ba48, 0x3ba50, + 0x3ba5c, 0x3ba64, + 0x3ba70, 0x3bab8, + 0x3bac0, 0x3bae4, + 0x3baf8, 0x3bb10, + 0x3bb28, 0x3bb28, + 0x3bb3c, 0x3bb50, + 0x3bbf0, 0x3bc10, + 0x3bc28, 0x3bc28, + 0x3bc3c, 0x3bc50, + 0x3bcf0, 0x3bcfc, + 0x3c000, 0x3c030, + 0x3c038, 0x3c038, + 0x3c040, 0x3c040, + 0x3c100, 0x3c144, + 0x3c190, 0x3c1a0, + 0x3c1a8, 0x3c1b8, + 0x3c1c4, 0x3c1c8, + 0x3c1d0, 0x3c1d0, + 0x3c200, 0x3c318, + 0x3c400, 0x3c4b4, + 0x3c4c0, 0x3c52c, + 0x3c540, 0x3c61c, + 0x3c800, 0x3c828, + 0x3c834, 0x3c834, + 0x3c8c0, 0x3c908, + 0x3c910, 0x3c9ac, + 0x3ca00, 0x3ca14, + 0x3ca1c, 0x3ca2c, + 0x3ca44, 0x3ca50, + 0x3ca74, 0x3ca74, + 0x3ca7c, 0x3cafc, + 0x3cb08, 0x3cc24, + 0x3cd00, 0x3cd00, + 0x3cd08, 0x3cd14, + 0x3cd1c, 0x3cd20, + 0x3cd3c, 0x3cd3c, + 0x3cd48, 0x3cd50, + 0x3d200, 0x3d20c, + 0x3d220, 0x3d220, + 0x3d240, 0x3d240, + 0x3d600, 0x3d60c, + 0x3da00, 0x3da1c, + 0x3de00, 0x3de20, + 0x3de38, 0x3de3c, + 0x3de80, 0x3de80, + 0x3de88, 0x3dea8, + 0x3deb0, 0x3deb4, + 0x3dec8, 0x3ded4, + 0x3dfb8, 0x3e004, + 0x3e200, 0x3e200, + 0x3e208, 0x3e240, + 0x3e248, 0x3e280, + 0x3e288, 0x3e2c0, + 0x3e2c8, 0x3e2fc, + 0x3e600, 0x3e630, + 0x3ea00, 0x3eabc, + 0x3eb00, 0x3eb10, + 0x3eb20, 0x3eb30, + 0x3eb40, 0x3eb50, + 0x3eb60, 0x3eb70, + 0x3f000, 0x3f028, + 0x3f030, 0x3f048, + 0x3f060, 0x3f068, + 0x3f070, 0x3f09c, + 0x3f0f0, 0x3f128, + 0x3f130, 0x3f148, + 0x3f160, 0x3f168, + 0x3f170, 0x3f19c, + 0x3f1f0, 0x3f238, + 0x3f240, 0x3f240, + 0x3f248, 0x3f250, + 0x3f25c, 0x3f264, + 0x3f270, 0x3f2b8, + 0x3f2c0, 0x3f2e4, + 0x3f2f8, 0x3f338, + 0x3f340, 0x3f340, + 0x3f348, 0x3f350, + 0x3f35c, 0x3f364, + 0x3f370, 0x3f3b8, + 0x3f3c0, 0x3f3e4, + 0x3f3f8, 0x3f428, + 0x3f430, 0x3f448, + 0x3f460, 0x3f468, + 0x3f470, 0x3f49c, + 0x3f4f0, 0x3f528, + 0x3f530, 0x3f548, + 0x3f560, 0x3f568, + 0x3f570, 0x3f59c, + 0x3f5f0, 0x3f638, + 0x3f640, 0x3f640, + 0x3f648, 0x3f650, + 0x3f65c, 0x3f664, + 0x3f670, 0x3f6b8, + 0x3f6c0, 0x3f6e4, + 0x3f6f8, 0x3f738, + 0x3f740, 0x3f740, + 0x3f748, 0x3f750, + 0x3f75c, 0x3f764, + 0x3f770, 0x3f7b8, + 0x3f7c0, 0x3f7e4, + 0x3f7f8, 0x3f7fc, + 0x3f814, 0x3f814, + 0x3f82c, 0x3f82c, + 0x3f880, 0x3f88c, + 0x3f8e8, 0x3f8ec, + 0x3f900, 0x3f928, + 0x3f930, 0x3f948, + 0x3f960, 0x3f968, + 0x3f970, 0x3f99c, + 0x3f9f0, 0x3fa38, + 0x3fa40, 0x3fa40, + 0x3fa48, 0x3fa50, + 0x3fa5c, 0x3fa64, + 0x3fa70, 0x3fab8, + 0x3fac0, 0x3fae4, + 0x3faf8, 0x3fb10, + 0x3fb28, 0x3fb28, + 0x3fb3c, 0x3fb50, + 0x3fbf0, 0x3fc10, + 0x3fc28, 0x3fc28, + 0x3fc3c, 0x3fc50, + 0x3fcf0, 0x3fcfc, + 0x40000, 0x4000c, + 0x40040, 0x40050, + 0x40060, 0x40068, + 0x4007c, 0x4008c, + 0x40094, 0x400b0, + 0x400c0, 0x40144, + 0x40180, 0x4018c, + 0x40200, 0x40254, + 0x40260, 0x40264, + 0x40270, 0x40288, + 0x40290, 0x40298, + 0x402ac, 0x402c8, + 0x402d0, 0x402e0, + 0x402f0, 0x402f0, + 0x40300, 0x4033c, + 0x403f8, 0x403fc, + 0x41304, 0x413c4, + 0x41400, 0x4140c, + 0x41414, 0x4141c, + 0x41480, 0x414d0, + 0x44000, 0x44054, + 0x4405c, 0x44078, + 0x440c0, 0x44174, + 0x44180, 0x441ac, + 0x441b4, 0x441b8, + 0x441c0, 0x44254, + 0x4425c, 0x44278, + 0x442c0, 0x44374, + 0x44380, 0x443ac, + 0x443b4, 0x443b8, + 0x443c0, 0x44454, + 0x4445c, 0x44478, + 0x444c0, 0x44574, + 0x44580, 0x445ac, + 0x445b4, 0x445b8, + 0x445c0, 0x44654, + 0x4465c, 0x44678, + 0x446c0, 0x44774, + 0x44780, 0x447ac, + 0x447b4, 0x447b8, + 0x447c0, 0x44854, + 0x4485c, 0x44878, + 0x448c0, 0x44974, + 0x44980, 0x449ac, + 0x449b4, 0x449b8, + 0x449c0, 0x449fc, + 0x45000, 0x45004, + 0x45010, 0x45030, + 0x45040, 0x45060, + 0x45068, 0x45068, + 0x45080, 0x45084, + 0x450a0, 0x450b0, + 0x45200, 0x45204, + 0x45210, 0x45230, + 0x45240, 0x45260, + 0x45268, 0x45268, + 0x45280, 0x45284, + 0x452a0, 0x452b0, + 0x460c0, 0x460e4, + 0x47000, 0x4703c, + 0x47044, 0x4708c, + 0x47200, 0x47250, + 0x47400, 0x47408, + 0x47414, 0x47420, + 0x47600, 0x47618, + 0x47800, 0x47814, + 0x48000, 0x4800c, + 0x48040, 0x48050, + 0x48060, 0x48068, + 0x4807c, 0x4808c, + 0x48094, 0x480b0, + 0x480c0, 0x48144, + 0x48180, 0x4818c, + 0x48200, 0x48254, + 0x48260, 0x48264, + 0x48270, 0x48288, + 0x48290, 0x48298, + 0x482ac, 0x482c8, + 0x482d0, 0x482e0, + 0x482f0, 0x482f0, + 0x48300, 0x4833c, + 0x483f8, 0x483fc, + 0x49304, 0x493c4, + 0x49400, 0x4940c, + 0x49414, 0x4941c, + 0x49480, 0x494d0, + 0x4c000, 0x4c054, + 0x4c05c, 0x4c078, + 0x4c0c0, 0x4c174, + 0x4c180, 0x4c1ac, + 0x4c1b4, 0x4c1b8, + 0x4c1c0, 0x4c254, + 0x4c25c, 0x4c278, + 0x4c2c0, 0x4c374, + 0x4c380, 0x4c3ac, + 0x4c3b4, 0x4c3b8, + 0x4c3c0, 0x4c454, + 0x4c45c, 0x4c478, + 0x4c4c0, 0x4c574, + 0x4c580, 0x4c5ac, + 0x4c5b4, 0x4c5b8, + 0x4c5c0, 0x4c654, + 0x4c65c, 0x4c678, + 0x4c6c0, 0x4c774, + 0x4c780, 0x4c7ac, + 0x4c7b4, 0x4c7b8, + 0x4c7c0, 0x4c854, + 0x4c85c, 0x4c878, + 0x4c8c0, 0x4c974, + 0x4c980, 0x4c9ac, + 0x4c9b4, 0x4c9b8, + 0x4c9c0, 0x4c9fc, + 0x4d000, 0x4d004, + 0x4d010, 0x4d030, + 0x4d040, 0x4d060, + 0x4d068, 0x4d068, + 0x4d080, 0x4d084, + 0x4d0a0, 0x4d0b0, + 0x4d200, 0x4d204, + 0x4d210, 0x4d230, + 0x4d240, 0x4d260, + 0x4d268, 0x4d268, + 0x4d280, 0x4d284, + 0x4d2a0, 0x4d2b0, + 0x4e0c0, 0x4e0e4, + 0x4f000, 0x4f03c, + 0x4f044, 0x4f08c, + 0x4f200, 0x4f250, + 0x4f400, 0x4f408, + 0x4f414, 0x4f420, + 0x4f600, 0x4f618, + 0x4f800, 0x4f814, + 0x50000, 0x50084, + 0x50090, 0x500cc, + 0x50400, 0x50400, + 0x50800, 0x50884, + 0x50890, 0x508cc, + 0x50c00, 0x50c00, + 0x51000, 0x5101c, + 0x51300, 0x51308, + }; + if (ddi_copyin(data, &r, sizeof (r), flags) < 0) return (EFAULT); @@ -382,10 +1172,23 @@ regdump(struct adapter *sc, void *data, int flags) else if (r.len < T4_REGDUMP_SIZE) return (E2BIG); - buf = kmem_zalloc(T4_REGDUMP_SIZE, KM_SLEEP); + r.version = mk_adap_vers(sc); - r.version = 4 | (sc->params.rev << 10); - for (i = 0; i < ARRAY_SIZE(reg_ranges); i += 2) + if (is_t4(sc->params.chip)) { + reg_ranges = &t4_reg_ranges[0]; + arr_size = ARRAY_SIZE(t4_reg_ranges); + buf_size = T4_REGDUMP_SIZE; + } else { + reg_ranges = &t5_reg_ranges[0]; + arr_size = ARRAY_SIZE(t5_reg_ranges); + buf_size = T5_REGDUMP_SIZE; + } + + buf = kmem_zalloc(buf_size, KM_SLEEP); + if (buf == NULL) + return (ENOMEM); + + for (i = 0; i < arr_size; i += 2) reg_block_dump(sc, buf, reg_ranges[i], reg_ranges[i + 1]); if (ddi_copyout(buf, r.data, r.len, flags) < 0) @@ -394,8 +1197,7 @@ regdump(struct adapter *sc, void *data, int flags) if (rc == 0 && ddi_copyout(&r, data, sizeof (r), flags) < 0) rc = EFAULT; - kmem_free(buf, T4_REGDUMP_SIZE); - + kmem_free(buf, buf_size); return (rc); } @@ -474,95 +1276,108 @@ _exit: return (rc); } +/* + * Verify that the memory range specified by the addr/len pair is valid and lies + * entirely within a single region (EDCx or MCx). + */ +static int +validate_mem_range(struct adapter *sc, uint32_t addr, int len) +{ + uint32_t em, addr_len, maddr, mlen; + + /* Memory can only be accessed in naturally aligned 4 byte units */ + if (addr & 3 || len & 3 || len == 0) + return (EINVAL); + + /* Enabled memories */ + em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); + if (em & F_EDRAM0_ENABLE) { + addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); + maddr = G_EDRAM0_BASE(addr_len) << 20; + mlen = G_EDRAM0_SIZE(addr_len) << 20; + if (mlen > 0 && addr >= maddr && addr < maddr + mlen && + addr + len <= maddr + mlen) + return (0); + } + if (em & F_EDRAM1_ENABLE) { + addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); + maddr = G_EDRAM1_BASE(addr_len) << 20; + mlen = G_EDRAM1_SIZE(addr_len) << 20; + if (mlen > 0 && addr >= maddr && addr < maddr + mlen && + addr + len <= maddr + mlen) + return (0); + } + if (em & F_EXT_MEM_ENABLE) { + addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); + maddr = G_EXT_MEM_BASE(addr_len) << 20; + mlen = G_EXT_MEM_SIZE(addr_len) << 20; + if (mlen > 0 && addr >= maddr && addr < maddr + mlen && + addr + len <= maddr + mlen) + return (0); + } + if (!is_t4(sc->params.chip) && em & F_EXT_MEM1_ENABLE) { + addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); + maddr = G_EXT_MEM1_BASE(addr_len) << 20; + mlen = G_EXT_MEM1_SIZE(addr_len) << 20; + if (mlen > 0 && addr >= maddr && addr < maddr + mlen && + addr + len <= maddr + mlen) + return (0); + } + + return (EFAULT); +} + static int read_card_mem(struct adapter *sc, void *data, int flags) { struct t4_mem_range mr; - uint32_t base, size, lo, hi, win, off, remaining, i, n; + uint32_t addr, off, remaining, i, n; uint32_t *buf, *b; int rc = 0; + uint32_t mw_base, mw_aperture; + uint8_t *dst; if (ddi_copyin(data, &mr, sizeof (mr), flags) < 0) { rc = EFAULT; goto _exit; } - /* reads are in multiples of 32 bits */ - if (mr.addr & 3 || mr.len & 3 || mr.len == 0) { - rc = EINVAL; - goto _exit; - } - - /* - * We don't want to deal with potential holes so we mandate that the - * requested region must lie entirely within one of the 3 memories. - */ - lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); - if (lo & F_EDRAM0_ENABLE) { - hi = t4_read_reg(sc, A_MA_EDRAM0_BAR); - base = G_EDRAM0_BASE(hi) << 20; - size = G_EDRAM0_SIZE(hi) << 20; - if (size > 0 && - mr.addr >= base && mr.addr < base + size && - mr.addr + mr.len <= base + size) - goto proceed; - } - if (lo & F_EDRAM1_ENABLE) { - hi = t4_read_reg(sc, A_MA_EDRAM1_BAR); - base = G_EDRAM1_BASE(hi) << 20; - size = G_EDRAM1_SIZE(hi) << 20; - if (size > 0 && - mr.addr >= base && mr.addr < base + size && - mr.addr + mr.len <= base + size) - goto proceed; - } - if (lo & F_EXT_MEM_ENABLE) { - hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); - base = G_EXT_MEM_BASE(hi) << 20; - size = G_EXT_MEM_SIZE(hi) << 20; - if (size > 0 && - mr.addr >= base && mr.addr < base + size && - mr.addr + mr.len <= base + size) - goto proceed; - } - return (ENXIO); + rc = validate_mem_range(sc, mr.addr, mr.len); + if (rc != 0) + return (rc); -proceed: - buf = b = kmem_zalloc(mr.len, KM_NOSLEEP); + memwin_info(sc, 2, &mw_base, &mw_aperture); + buf = b = kmem_zalloc(min(mr.len, mw_aperture), KM_NOSLEEP); if (buf == NULL) { rc = ENOMEM; goto _exit; } - /* - * Position the PCIe window (we use memwin2) to the 16B aligned area - * just at/before the requested region. - */ - win = mr.addr & ~0xf; - off = mr.addr - win; /* offset of the requested region in the win */ + addr = mr.addr; remaining = mr.len; + dst = (void *)mr.data; while (remaining) { - t4_write_reg(sc, - PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2), win); - (void) t4_read_reg(sc, - PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2)); + off = position_memwin(sc, 2, addr); /* number of bytes that we'll copy in the inner loop */ - n = min(remaining, MEMWIN2_APERTURE - off); + n = min(remaining, mw_aperture - off); - for (i = 0; i < n; i += 4, remaining -= 4) - *b++ = t4_read_reg(sc, MEMWIN2_BASE + off + i); + for (i = 0; i < n; i += 4) + *b++ = t4_read_reg(sc, mw_base + off + i); + rc = ddi_copyout(buf, dst, n, flags); + if (rc != 0) { + rc = EFAULT; + break; + } - win += MEMWIN2_APERTURE; - off = 0; + b = buf; + dst += n; + remaining -= n; + addr += n; } - if (ddi_copyout(buf, mr.data, mr.len, flags) < 0) - rc = EFAULT; - - kmem_free(buf, mr.len); - + kmem_free(buf, min(mr.len, mw_aperture)); _exit: return (rc); } @@ -581,8 +1396,9 @@ get_devlog(struct adapter *sc, void *data, int flags) } if (dparams->start == 0) { - rc = ENXIO; - goto done; + dparams->memtype = 0; + dparams->start = 0x84000; + dparams->size = 32768; } if (dl.len < dparams->size) { @@ -626,15 +1442,28 @@ read_cim_qcfg(struct adapter *sc, void *data, int flags) { struct t4_cim_qcfg t4cimqcfg; int rc = 0; + unsigned int ibq_rdaddr, obq_rdaddr, nq; if (ddi_copyin(data, &t4cimqcfg, sizeof (t4cimqcfg), flags) < 0) { rc = EFAULT; goto _exit; } - rc = t4_cim_read(sc, A_UP_IBQ_0_RDADDR, ARRAY_SIZE(t4cimqcfg.stat), - t4cimqcfg.stat); - + if (is_t4(sc->params.chip)) { + t4cimqcfg.num_obq = CIM_NUM_OBQ; + ibq_rdaddr = A_UP_IBQ_0_RDADDR; + obq_rdaddr = A_UP_OBQ_0_REALADDR; + } else { + t4cimqcfg.num_obq = CIM_NUM_OBQ_T5; + ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR; + obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR; + } + nq = CIM_NUM_IBQ + t4cimqcfg.num_obq; + + rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, t4cimqcfg.stat); + if (rc == 0) + rc = -t4_cim_read(sc, obq_rdaddr, 2 * t4cimqcfg.num_obq, + t4cimqcfg.obq_wr); if (rc != 0) return (rc); diff --git a/usr/src/uts/common/io/cxgbe/t4nex/t4_l2t.c b/usr/src/uts/common/io/cxgbe/t4nex/t4_l2t.c index d779f4caf3..4f0b734507 100644 --- a/usr/src/uts/common/io/cxgbe/t4nex/t4_l2t.c +++ b/usr/src/uts/common/io/cxgbe/t4nex/t4_l2t.c @@ -128,9 +128,10 @@ enum { struct l2t_data { krwlock_t lock; + u_int l2t_size; volatile uint_t nfree; /* number of free entries */ struct l2t_entry *rover; /* starting point for next allocation */ - struct l2t_entry l2tab[L2T_SIZE]; + struct l2t_entry l2tab[]; }; #define VLAN_NONE 0xfff @@ -153,7 +154,7 @@ alloc_l2e(struct l2t_data *d) return (NULL); /* there's definitely a free entry */ - for (e = d->rover, end = &d->l2tab[L2T_SIZE]; e != end; ++e) + for (e = d->rover, end = &d->l2tab[d->l2t_size]; e != end; ++e) if (atomic_read(&e->refcnt) == 0) goto found; @@ -190,6 +191,7 @@ write_l2e(adapter_t *sc, struct l2t_entry *e, int sync) { mblk_t *m; struct cpl_l2t_write_req *req; + int idx = e->idx + sc->vres.l2t.start; ASSERT(MUTEX_HELD(&e->lock)); @@ -201,10 +203,10 @@ write_l2e(adapter_t *sc, struct l2t_entry *e, int sync) /* LINTED: E_CONSTANT_CONDITION */ INIT_TP_WR(req, 0); - OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, e->idx | + OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, idx | V_SYNC_WR(sync) | V_TID_QID(sc->sge.fwq.abs_id))); req->params = htons(V_L2T_W_PORT(e->lport) | V_L2T_W_NOREPLY(!sync)); - req->l2t_idx = htons(e->idx); + req->l2t_idx = htons(idx); req->vlan = htons(e->vlan); (void) memcpy(req->dst_mac, e->dmac, sizeof (req->dst_mac)); @@ -221,16 +223,24 @@ write_l2e(adapter_t *sc, struct l2t_entry *e, int sync) struct l2t_data * t4_init_l2t(struct adapter *sc) { - int i; + int i, l2t_size; struct l2t_data *d; - d = kmem_zalloc(sizeof (*d), KM_SLEEP); + l2t_size = sc->vres.l2t.size; + if(l2t_size < 1) + return (NULL); + d = kmem_zalloc(sizeof(*d) + l2t_size * sizeof (struct l2t_entry), KM_SLEEP); + if (!d) + return (NULL); + + d->l2t_size = l2t_size; + d->rover = d->l2tab; - (void) atomic_swap_uint(&d->nfree, L2T_SIZE); + (void) atomic_swap_uint(&d->nfree, l2t_size); rw_init(&d->lock, NULL, RW_DRIVER, NULL); - for (i = 0; i < L2T_SIZE; i++) { + for (i = 0; i < l2t_size; i++) { /* LINTED: E_ASSIGN_NARROW_CONV */ d->l2tab[i].idx = i; d->l2tab[i].state = L2T_STATE_UNUSED; @@ -328,21 +338,6 @@ arpq_enqueue(struct l2t_entry *e, mblk_t *m) e->arpq_tail = m; } -static inline void -send_pending(struct adapter *sc, struct l2t_entry *e) -{ - mblk_t *m, *next; - - ASSERT(MUTEX_HELD(&e->lock)); - - for (m = e->arpq_head; m; m = next) { - next = m->b_next; - m->b_next = NULL; - (void) t4_wrq_tx(sc, MBUF_EQ(m), m); - } - e->arpq_head = e->arpq_tail = NULL; -} - int t4_l2t_send(struct adapter *sc, mblk_t *m, struct l2t_entry *e) { @@ -440,7 +435,7 @@ do_l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, mblk_t *m) struct adapter *sc = iq->adapter; const struct cpl_l2t_write_rpl *rpl = (const void *)(rss + 1); unsigned int tid = GET_TID(rpl); - unsigned int idx = tid & (L2T_SIZE - 1); + unsigned int idx = tid % L2T_SIZE; if (likely(rpl->status != CPL_ERR_NONE)) { cxgb_printf(sc->dip, CE_WARN, @@ -449,17 +444,6 @@ do_l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, mblk_t *m) return (-EINVAL); } - if (tid & F_SYNC_WR) { - struct l2t_entry *e = &sc->l2t->l2tab[idx]; - - mutex_enter(&e->lock); - if (e->state != L2T_STATE_SWITCHING) { - send_pending(sc, e); - e->state = L2T_STATE_VALID; - } - mutex_exit(&e->lock); - } - return (0); } diff --git a/usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c b/usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c index 9e7e3eb6c4..642e8fd763 100644 --- a/usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c +++ b/usr/src/uts/common/io/cxgbe/t4nex/t4_nexus.c @@ -39,9 +39,12 @@ #include "version.h" #include "common/common.h" +#include "common/t4_msg.h" #include "common/t4_regs.h" #include "firmware/t4_fw.h" #include "firmware/t4_cfg.h" +#include "firmware/t5_fw.h" +#include "firmware/t5_cfg.h" #include "t4_l2t.h" static int t4_cb_open(dev_t *devp, int flag, int otyp, cred_t *credp); @@ -132,6 +135,7 @@ struct intrs_and_queues { static int cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, mblk_t *m); +static int fw_msg_not_handled(struct adapter *, const __be64 *); int t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h); static unsigned int getpf(struct adapter *sc); static int prep_firmware(struct adapter *sc); @@ -139,7 +143,12 @@ static int upload_config_file(struct adapter *sc, uint32_t *mt, uint32_t *ma); static int partition_resources(struct adapter *sc); static int get_params__pre_init(struct adapter *sc); static int get_params__post_init(struct adapter *sc); +static int set_params__post_init(struct adapter *); static void setup_memwin(struct adapter *sc); +static int validate_mt_off_len(struct adapter *, int, uint32_t, int, + uint32_t *); +void memwin_info(struct adapter *, int, uint32_t *, uint32_t *); +uint32_t position_memwin(struct adapter *, int, uint32_t); static int prop_lookup_int_array(struct adapter *sc, char *name, int *data, uint_t count); static int prop_lookup_int_array(struct adapter *sc, char *name, int *data, @@ -151,6 +160,8 @@ static int cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, static int add_child_node(struct adapter *sc, int idx); static int remove_child_node(struct adapter *sc, int idx); static kstat_t *setup_kstats(struct adapter *sc); +static kstat_t *setup_wc_kstats(struct adapter *); +static int update_wc_kstats(kstat_t *, int); #ifndef TCP_OFFLOAD_DISABLE static int toe_capability(struct port_info *pi, int enable); static int activate_uld(struct adapter *sc, int id, struct uld_softc *usc); @@ -274,7 +285,12 @@ t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC, .devacc_attr_dataorder = DDI_UNORDERED_OK_ACC }; - + ddi_device_acc_attr_t da1 = { + .devacc_attr_version = DDI_DEVICE_ATTR_V0, + .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC, + .devacc_attr_dataorder = DDI_MERGING_OK_ACC + }; + if (cmd != DDI_ATTACH) return (DDI_FAILURE); @@ -309,6 +325,10 @@ t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) } sc->mbox = sc->pf; + /* Initialize the driver properties */ + prp = &sc->props; + (void)init_driver_props(sc, prp); + /* * Enable access to the PCI config space. */ @@ -340,6 +360,10 @@ t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) sc->cpl_handler[i] = cpl_not_handled; } + for (i = 0; i < ARRAY_SIZE(sc->fw_msg_handler); i++) { + sc->fw_msg_handler[i] = fw_msg_not_handled; + } + /* * Prepare the adapter for operation. */ @@ -350,6 +374,36 @@ t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) } /* + * Enable BAR1 access. + */ + sc->doorbells |= DOORBELL_KDB; + rc = ddi_regs_map_setup(dip, 2, &sc->reg1p, 0, 0, &da1, &sc->reg1h); + if (rc != DDI_SUCCESS) { + cxgb_printf(dip, CE_WARN, + "failed to map BAR1 device registers: %d", rc); + goto done; + } else { + if (is_t5(sc->params.chip)) { + sc->doorbells |= DOORBELL_UDB; + if (prp->wc) { + /* + * Enable write combining on BAR2. This is the + * userspace doorbell BAR and is split into 128B + * (UDBS_SEG_SIZE) doorbell regions, each associated + * with an egress queue. The first 64B has the doorbell + * and the second 64B can be used to submit a tx work + * request with an implicit doorbell. + */ + sc->doorbells &= ~DOORBELL_UDB; + sc->doorbells |= (DOORBELL_WCWR | + DOORBELL_UDBWC); + t4_write_reg(sc, A_SGE_STAT_CFG, + V_STATSOURCE_T5(7) | V_STATMODE(0)); + } + } + } + + /* * Do this really early. Note that minor number = instance. */ (void) snprintf(name, sizeof (name), "%s,%d", T4_NEXUS_NAME, instance); @@ -361,10 +415,6 @@ t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) rc = DDI_SUCCESS; /* carry on */ } - /* Initialize the driver properties */ - prp = &sc->props; - (void) init_driver_props(sc, prp); - /* Do this early. Memory window is required for loading config file. */ setup_memwin(sc); @@ -393,6 +443,10 @@ t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) if (rc != 0) goto done; /* error message displayed already */ + rc = set_params__post_init(sc); + if (rc != 0) + goto done; /* error message displayed already */ + /* * TODO: This is the place to call t4_set_filter_mode() */ @@ -445,7 +499,7 @@ t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) mutex_init(&pi->lock, NULL, MUTEX_DRIVER, NULL); pi->mtu = ETHERMTU; - if (is_10G_port(pi) != 0) { + if (is_10G_port(pi) || is_40G_port(pi)) { n10g++; pi->tmr_idx = prp->tmr_idx_10g; pi->pktc_idx = prp->pktc_idx_10g; @@ -528,12 +582,13 @@ t4_devo_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) /* LINTED: E_ASSIGN_NARROW_CONV */ pi->first_rxq = rqidx; /* LINTED: E_ASSIGN_NARROW_CONV */ - pi->nrxq = is_10G_port(pi) ? iaq.nrxq10g : iaq.nrxq1g; - + pi->nrxq = (is_10G_port(pi) || is_40G_port(pi)) ? iaq.nrxq10g + : iaq.nrxq1g; /* LINTED: E_ASSIGN_NARROW_CONV */ pi->first_txq = tqidx; /* LINTED: E_ASSIGN_NARROW_CONV */ - pi->ntxq = is_10G_port(pi) ? iaq.ntxq10g : iaq.ntxq1g; + pi->ntxq = (is_10G_port(pi) || is_40G_port(pi)) ? iaq.ntxq10g + : iaq.ntxq1g; rqidx += pi->nrxq; tqidx += pi->ntxq; @@ -669,6 +724,7 @@ ofld_queues: } sc->ksp = setup_kstats(sc); + sc->ksp_stat = setup_wc_kstats(sc); done: if (rc != DDI_SUCCESS) { @@ -713,6 +769,8 @@ t4_devo_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) if (sc->ksp != NULL) kstat_delete(sc->ksp); + if (sc->ksp_stat != NULL) + kstat_delete(sc->ksp_stat); s = &sc->sge; if (s->rxq != NULL) @@ -762,6 +820,9 @@ t4_devo_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) if (sc->flags & FW_OK) (void) t4_fw_bye(sc, sc->mbox); + if (sc->reg1h != NULL) + ddi_regs_map_free(&sc->reg1h); + if (sc->regh != NULL) ddi_regs_map_free(&sc->regh); @@ -1009,30 +1070,52 @@ prep_firmware(struct adapter *sc) rc = t4_check_fw_version(sc); if (rc != 0) { uint32_t v; + if (is_t4(sc->params.chip)) { + /* This is what the driver has */ + v = V_FW_HDR_FW_VER_MAJOR(T4FW_VERSION_MAJOR) | + V_FW_HDR_FW_VER_MINOR(T4FW_VERSION_MINOR) | + V_FW_HDR_FW_VER_MICRO(T4FW_VERSION_MICRO) | + V_FW_HDR_FW_VER_BUILD(T4FW_VERSION_BUILD); - /* This is what the driver has */ - v = V_FW_HDR_FW_VER_MAJOR(T4FW_VERSION_MAJOR) | - V_FW_HDR_FW_VER_MINOR(T4FW_VERSION_MINOR) | - V_FW_HDR_FW_VER_MICRO(T4FW_VERSION_MICRO) | - V_FW_HDR_FW_VER_BUILD(T4FW_VERSION_BUILD); - - /* - * Always upgrade, even for minor/micro/build mismatches. - * Downgrade only for a major version mismatch. - */ - if (rc < 0 || v > sc->params.fw_vers) { - cxgb_printf(sc->dip, CE_NOTE, - "installing firmware %d.%d.%d.%d on card.", - T4FW_VERSION_MAJOR, T4FW_VERSION_MINOR, - T4FW_VERSION_MICRO, T4FW_VERSION_BUILD); - rc = -t4_load_fw(sc, t4fw_data, t4fw_size); - if (rc != 0) { - cxgb_printf(sc->dip, CE_WARN, - "failed to install firmware: %d", rc); - return (rc); - } else { - /* refresh */ - (void) t4_check_fw_version(sc); + /* + * Always upgrade, even for minor/micro/build mismatches. + * Downgrade only for a major version mismatch. + */ + if (rc < 0 || v > sc->params.fw_vers) { + cxgb_printf(sc->dip, CE_NOTE, + "installing firmware %d.%d.%d.%d on card.", + T4FW_VERSION_MAJOR, T4FW_VERSION_MINOR, + T4FW_VERSION_MICRO, T4FW_VERSION_BUILD); + rc = -t4_load_fw(sc, t4fw_data, t4fw_size); + if (rc != 0) { + cxgb_printf(sc->dip, CE_WARN, + "failed to install firmware: %d", rc); + return (rc); + } else { + /* refresh */ + (void) t4_check_fw_version(sc); + } + } + } else { + v = V_FW_HDR_FW_VER_MAJOR(T5FW_VERSION_MAJOR) | + V_FW_HDR_FW_VER_MINOR(T5FW_VERSION_MINOR) | + V_FW_HDR_FW_VER_MICRO(T5FW_VERSION_MICRO) | + V_FW_HDR_FW_VER_BUILD(T5FW_VERSION_BUILD); + if (rc < 0 || v > sc->params.fw_vers) { + cxgb_printf(sc->dip, CE_NOTE, + "installing firmware %d.%d.%d.%d on card.", + T5FW_VERSION_MAJOR, T5FW_VERSION_MINOR, + T5FW_VERSION_MICRO, T5FW_VERSION_BUILD); + rc = -t4_load_fw(sc, t5fw_data, t5fw_size); + if (rc != 0) { + cxgb_printf(sc->dip, CE_WARN, + "failed to install firmware: %d", rc); + return (rc); + } else { + /* refresh */ + (void) t4_check_fw_version(sc); + } + } } } @@ -1075,6 +1158,18 @@ err: } +static const struct memwin t4_memwin[] = { + { MEMWIN0_BASE, MEMWIN0_APERTURE }, + { MEMWIN1_BASE, MEMWIN1_APERTURE }, + { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 } +}; + +static const struct memwin t5_memwin[] = { + { MEMWIN0_BASE, MEMWIN0_APERTURE }, + { MEMWIN1_BASE, MEMWIN1_APERTURE }, + { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 }, +}; + #define FW_PARAM_DEV(param) \ (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) @@ -1083,14 +1178,90 @@ err: V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)) /* + * Verify that the memory range specified by the memtype/offset/len pair is + * valid and lies entirely within the memtype specified. The global address of + * the start of the range is returned in addr. + */ +int +validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len, + uint32_t *addr) +{ + uint32_t em, addr_len, maddr, mlen; + + /* Memory can only be accessed in naturally aligned 4 byte units */ + if (off & 3 || len & 3 || len == 0) + return (EINVAL); + + em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); + switch (mtype) { + case MEM_EDC0: + if (!(em & F_EDRAM0_ENABLE)) + return (EINVAL); + addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR); + maddr = G_EDRAM0_BASE(addr_len) << 20; + mlen = G_EDRAM0_SIZE(addr_len) << 20; + break; + case MEM_EDC1: + if (!(em & F_EDRAM1_ENABLE)) + return (EINVAL); + addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR); + maddr = G_EDRAM1_BASE(addr_len) << 20; + mlen = G_EDRAM1_SIZE(addr_len) << 20; + break; + case MEM_MC: + if (!(em & F_EXT_MEM_ENABLE)) + return (EINVAL); + addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); + maddr = G_EXT_MEM_BASE(addr_len) << 20; + mlen = G_EXT_MEM_SIZE(addr_len) << 20; + break; + case MEM_MC1: + if (is_t4(sc->params.chip) || !(em & F_EXT_MEM1_ENABLE)) + return (EINVAL); + addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR); + maddr = G_EXT_MEM1_BASE(addr_len) << 20; + mlen = G_EXT_MEM1_SIZE(addr_len) << 20; + break; + default: + return (EINVAL); + } + + if (mlen > 0 && off < mlen && off + len <= mlen) { + *addr = maddr + off; /* global address */ + return (0); + } + + return (EFAULT); +} + +void +memwin_info(struct adapter *sc, int win, uint32_t *base, uint32_t *aperture) +{ + const struct memwin *mw; + + if (is_t4(sc->params.chip)) { + mw = &t4_memwin[win]; + } else { + mw = &t5_memwin[win]; + } + + if (base != NULL) + *base = mw->base; + if (aperture != NULL) + *aperture = mw->aperture; +} + +/* * Upload configuration file to card's memory. */ static int upload_config_file(struct adapter *sc, uint32_t *mt, uint32_t *ma) { - int rc, i; - uint32_t param, val, mtype, maddr, bar, off, win, remaining; - const uint32_t *b; + int rc = 0, cflen; + u_int i, n; + uint32_t param, val, addr, mtype, maddr; + uint32_t off, mw_base, mw_aperture; + const uint32_t *cfdata; /* Figure out where the firmware wants us to upload it. */ param = FW_PARAM_DEV(CF); @@ -1104,76 +1275,43 @@ upload_config_file(struct adapter *sc, uint32_t *mt, uint32_t *ma) *mt = mtype = G_FW_PARAMS_PARAM_Y(val); *ma = maddr = G_FW_PARAMS_PARAM_Z(val) << 16; - if (maddr & 3) { + if (is_t4(sc->params.chip)) { + cflen = t4cfg_size & ~3; + /* LINTED: E_BAD_PTR_CAST_ALIGN */ + cfdata = (const uint32_t *)t4cfg_data; + } else { + cflen = t5cfg_size & ~3; + /* LINTED: E_BAD_PTR_CAST_ALIGN */ + cfdata = (const uint32_t *)t5cfg_data; + } + + if (cflen > FLASH_CFG_MAX_SIZE) { cxgb_printf(sc->dip, CE_WARN, - "cannot upload config file (type %u, addr %x).\n", - mtype, maddr); - return (EFAULT); + "config file too long (%d, max allowed is %d). ", + cflen, FLASH_CFG_MAX_SIZE); + return (EFBIG); } - /* Translate mtype/maddr to an address suitable for the PCIe window */ - val = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE); - val &= F_EDRAM0_ENABLE | F_EDRAM1_ENABLE | F_EXT_MEM_ENABLE; - switch (mtype) { - case FW_MEMTYPE_CF_EDC0: - if (!(val & F_EDRAM0_ENABLE)) - goto err; - bar = t4_read_reg(sc, A_MA_EDRAM0_BAR); - maddr += G_EDRAM0_BASE(bar) << 20; - break; - - case FW_MEMTYPE_CF_EDC1: - if (!(val & F_EDRAM1_ENABLE)) - goto err; - bar = t4_read_reg(sc, A_MA_EDRAM1_BAR); - maddr += G_EDRAM1_BASE(bar) << 20; - break; - - case FW_MEMTYPE_CF_EXTMEM: - if (!(val & F_EXT_MEM_ENABLE)) - goto err; - bar = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR); - maddr += G_EXT_MEM_BASE(bar) << 20; - break; + rc = validate_mt_off_len(sc, mtype, maddr, cflen, &addr); + if (rc != 0) { - default: -err: cxgb_printf(sc->dip, CE_WARN, - "cannot upload config file (type %u, enabled %u).\n", - mtype, val); + "%s: addr (%d/0x%x) or len %d is not valid: %d. " + "Will try to use the config on the card, if any.\n", + __func__, mtype, maddr, cflen, rc); return (EFAULT); } - /* - * Position the PCIe window (we use memwin2) to the 16B aligned area - * just at/before the upload location. - */ - win = maddr & ~0xf; - off = maddr - win; /* offset from the start of the window. */ - t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2), win); - (void) t4_read_reg(sc, - PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2)); - - remaining = t4cfg_size; - if (remaining > FLASH_CFG_MAX_SIZE || - remaining > MEMWIN2_APERTURE - off) { - cxgb_printf(sc->dip, CE_WARN, "cannot upload config file all at" - " once (size %u, max %u, room %u).\n", - remaining, FLASH_CFG_MAX_SIZE, MEMWIN2_APERTURE - off); - return (EFBIG); + memwin_info(sc, 2, &mw_base, &mw_aperture); + while (cflen) { + off = position_memwin(sc, 2, addr); + n = min(cflen, mw_aperture - off); + for (i = 0; i < n; i += 4) + t4_write_reg(sc, mw_base + off + i, *cfdata++); + cflen -= n; + addr += n; } - /* - * TODO: sheer laziness. We deliberately added 4 bytes of useless - * stuffing/comments at the end of the config file so it's ok to simply - * throw away the last remaining bytes when the config file is not an - * exact multiple of 4. - */ - /* LINTED: E_BAD_PTR_CAST_ALIGN */ - b = (const uint32_t *)t4cfg_data; - for (i = 0; remaining >= 4; i += 4, remaining -= 4) - t4_write_reg(sc, MEMWIN2_BASE + off + i, *b++); - return (rc); } @@ -1304,7 +1442,9 @@ get_params__post_init(struct adapter *sc) param[1] = FW_PARAM_PFVF(EQ_START); param[2] = FW_PARAM_PFVF(FILTER_START); param[3] = FW_PARAM_PFVF(FILTER_END); - rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val); + param[4] = FW_PARAM_PFVF(L2T_START); + param[5] = FW_PARAM_PFVF(L2T_END); + rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val); if (rc != 0) { cxgb_printf(sc->dip, CE_WARN, "failed to query parameters (post_init): %d.\n", rc); @@ -1316,6 +1456,8 @@ get_params__post_init(struct adapter *sc) sc->sge.eq_start = val[1]; sc->tids.ftid_base = val[2]; sc->tids.nftids = val[3] - val[2] + 1; + sc->vres.l2t.start = val[4]; + sc->vres.l2t.size = val[5] - val[4] + 1; /* get capabilites */ bzero(&caps, sizeof (caps)); @@ -1362,6 +1504,19 @@ get_params__post_init(struct adapter *sc) return (rc); } +static int +set_params__post_init(struct adapter *sc) +{ + uint32_t param, val; + + /* ask for encapsulated CPLs */ + param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); + val = 1; + (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); + + return (0); +} + /* TODO: verify */ static void setup_memwin(struct adapter *sc) @@ -1370,6 +1525,8 @@ setup_memwin(struct adapter *sc) int rc; uint_t n; uintptr_t bar0; + uintptr_t mem_win0_base, mem_win1_base, mem_win2_base; + uintptr_t mem_win2_aperture; rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, sc->dip, DDI_PROP_DONTPASS, "assigned-addresses", (int **)&data, &n); @@ -1383,20 +1540,69 @@ setup_memwin(struct adapter *sc) bar0 = ((uint64_t)data[0].pci_phys_mid << 32) | data[0].pci_phys_low; ddi_prop_free(data); + if (is_t4(sc->params.chip)) { + mem_win0_base = bar0 + MEMWIN0_BASE; + mem_win1_base = bar0 + MEMWIN1_BASE; + mem_win2_base = bar0 + MEMWIN2_BASE_T4; + mem_win2_aperture = MEMWIN2_APERTURE_T4; + } else { + /* For T5, only relative offset inside the PCIe BAR is passed */ + mem_win0_base = MEMWIN0_BASE; + mem_win1_base = MEMWIN1_BASE; + mem_win2_base = MEMWIN2_BASE_T5; + mem_win2_aperture = MEMWIN2_APERTURE_T5; + } + t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 0), - (bar0 + MEMWIN0_BASE) | V_BIR(0) | + mem_win0_base | V_BIR(0) | V_WINDOW(ilog2(MEMWIN0_APERTURE) - 10)); t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 1), - (bar0 + MEMWIN1_BASE) | V_BIR(0) | + mem_win1_base | V_BIR(0) | V_WINDOW(ilog2(MEMWIN1_APERTURE) - 10)); t4_write_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2), - (bar0 + MEMWIN2_BASE) | V_BIR(0) | - V_WINDOW(ilog2(MEMWIN2_APERTURE) - 10)); + mem_win2_base | V_BIR(0) | + V_WINDOW(ilog2(mem_win2_aperture) - 10)); + + /* flush */ + (void)t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2)); } /* + * Positions the memory window such that it can be used to access the specified + * address in the chip's address space. The return value is the offset of addr + * from the start of the window. + */ +uint32_t +position_memwin(struct adapter *sc, int n, uint32_t addr) +{ + uint32_t start, pf; + uint32_t reg; + + if (addr & 3) { + cxgb_printf(sc->dip, CE_WARN, + "addr (0x%x) is not at a 4B boundary.\n", addr); + return (EFAULT); + } + + if (is_t4(sc->params.chip)) { + pf = 0; + start = addr & ~0xf; /* start must be 16B aligned */ + } else { + pf = V_PFNUM(sc->pf); + start = addr & ~0x7f; /* start must be 128B aligned */ + } + reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, n); + + t4_write_reg(sc, reg, start | pf); + (void) t4_read_reg(sc, reg); + + return (addr - start); +} + + +/* * Reads the named property and fills up the "data" array (which has at least * "count" elements). We first try and lookup the property for our dev_t and * then retry with DDI_DEV_T_ANY if it's not found. @@ -1612,6 +1818,19 @@ init_driver_props(struct adapter *sc, struct driver_properties *p) "interrupt-forwarding", NULL, 0); } + /* + * Write combining + * 0 to disable, 1 to enable + */ + p->wc = prop_lookup_int(sc, "write-combine", 1); + cxgb_printf(dip, CE_WARN, "write-combine: using of %d", p->wc); + if (p->wc != 0 && p->wc != 1) { + cxgb_printf(dip, CE_WARN, + "write-combine: using 1 instead of %d", p->wc); + p->wc = 1; + } + (void) ddi_prop_update_int(dev, dip, "write-combine", p->wc); + return (0); } @@ -1938,7 +2157,8 @@ setup_kstats(struct adapter *sc) t4_os_pci_read_cfg2(sc, PCI_CONF_DEVID, &pci_device); KS_C_SET(pci_device_id, "0x%x", pci_device); -#define PSTR(pi) (pi ? (is_10G_port(pi) ? "10G" : "1G") : "-") +#define PSTR(pi) (pi ? (is_40G_port(pi) ? "40G" : \ + (is_10G_port(pi) ? "10G" : "1G")) : "-") KS_C_SET(port_type, "%s/%s/%s/%s", PSTR(sc->port[0]), PSTR(sc->port[1]), PSTR(sc->port[2]), PSTR(sc->port[3])); #undef PSTR @@ -1952,6 +2172,66 @@ setup_kstats(struct adapter *sc) return (ksp); } +/* + * t4nex:X:stat + */ +struct t4_wc_kstats { + kstat_named_t write_coal_success; + kstat_named_t write_coal_failure; +}; +static kstat_t * +setup_wc_kstats(struct adapter *sc) +{ + kstat_t *ksp; + struct t4_wc_kstats *kstatp; + int ndata; + + ndata = sizeof(struct t4_wc_kstats) / sizeof(kstat_named_t); + ksp = kstat_create(T4_NEXUS_NAME, ddi_get_instance(sc->dip), "stats", + "nexus", KSTAT_TYPE_NAMED, ndata, 0); + if (ksp == NULL) { + cxgb_printf(sc->dip, CE_WARN, "failed to initialize kstats."); + return (NULL); + } + + kstatp = (struct t4_wc_kstats *)ksp->ks_data; + + KS_UINIT(write_coal_success); + KS_UINIT(write_coal_failure); + + ksp->ks_update = update_wc_kstats; + /* Install the kstat */ + ksp->ks_private = (void *)sc; + kstat_install(ksp); + + return (ksp); +} + +static int +update_wc_kstats(kstat_t *ksp, int rw) +{ + struct t4_wc_kstats *kstatp = (struct t4_wc_kstats *)ksp->ks_data; + struct adapter *sc = ksp->ks_private; + uint32_t wc_total, wc_success, wc_failure; + + if (rw == KSTAT_WRITE) + return (0); + + if (is_t5(sc->params.chip)) { + wc_total = t4_read_reg(sc, A_SGE_STAT_TOTAL); + wc_failure = t4_read_reg(sc, A_SGE_STAT_MATCH); + wc_success = wc_total - wc_failure; + } else { + wc_success = 0; + wc_failure = 0; + } + + KS_U_SET(write_coal_success, wc_success); + KS_U_SET(write_coal_failure, wc_failure); + + return (0); +} + int adapter_full_init(struct adapter *sc) { @@ -2235,6 +2515,38 @@ t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h) return (0); } +static int +fw_msg_not_handled(struct adapter *sc, const __be64 *data) +{ + struct cpl_fw6_msg *cpl = container_of(data, struct cpl_fw6_msg, data); + + cxgb_printf(sc->dip, CE_WARN, "%s fw_msg type %d", __func__, cpl->type); + return (0); +} + +int +t4_register_fw_msg_handler(struct adapter *sc, int type, fw_msg_handler_t h) +{ + fw_msg_handler_t *loc, new; + + if (type >= ARRAY_SIZE(sc->fw_msg_handler)) + return (EINVAL); + + /* + * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL + * handler dispatch table. Reject any attempt to install a handler for + * this subtype. + */ + if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL) + return (EINVAL); + + new = h ? h : fw_msg_not_handled; + loc = &sc->fw_msg_handler[type]; + (void)atomic_swap_ptr(loc, (void *)new); + + return (0); +} + #ifndef TCP_OFFLOAD_DISABLE static int toe_capability(struct port_info *pi, int enable) diff --git a/usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c b/usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c index d2f7161b82..016329f076 100644 --- a/usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c +++ b/usr/src/uts/common/io/cxgbe/t4nex/t4_sge.c @@ -75,8 +75,8 @@ static int service_iq(struct sge_iq *iq, int budget); static inline void init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int8_t pktc_idx, int qsize, uint8_t esize); static inline void init_fl(struct sge_fl *fl, uint16_t qsize); -static inline void init_eq(struct sge_eq *eq, uint16_t eqtype, uint16_t qsize, - uint8_t tx_chan, uint16_t iqid); +static inline void init_eq(struct adapter *sc, struct sge_eq *eq, + uint16_t eqtype, uint16_t qsize,uint8_t tx_chan, uint16_t iqid); static int alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, int intr_idx, int cong); static int free_iq_fl(struct port_info *pi, struct sge_iq *iq, @@ -295,6 +295,8 @@ t4_sge_init(struct adapter *sc) (void) t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_rpl); (void) t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_rpl); (void) t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx); + (void) t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, + t4_handle_fw_rpl); } /* @@ -368,7 +370,7 @@ first_vector(struct port_info *pi) * NIC queues exist and they'd better be taking direct * interrupts. */ - KASSERT(!(sc->flags & INTR_FWD)); + ASSERT(!(sc->flags & INTR_FWD)); rc += p->nrxq; #endif } @@ -528,7 +530,7 @@ t4_setup_port_queues(struct port_info *pi) uint16_t iqid; iqid = port_intr_iq(pi, j)->cntxt_id; - init_eq(&txq->eq, EQ_ETH, p->qsize_txq, pi->tx_chan, iqid); + init_eq(sc, &txq->eq, EQ_ETH, p->qsize_txq, pi->tx_chan, iqid); rc = alloc_txq(pi, txq, i); if (rc != 0) goto done; @@ -539,7 +541,7 @@ t4_setup_port_queues(struct port_info *pi) uint16_t iqid; iqid = port_intr_iq(pi, j)->cntxt_id; - init_eq(&ofld_txq->eq, EQ_OFLD, p->qsize_txq, pi->tx_chan, + init_eq(sc, &ofld_txq->eq, EQ_OFLD, p->qsize_txq, pi->tx_chan, iqid); rc = alloc_wrq(sc, pi, ofld_txq, i); if (rc != 0) @@ -552,7 +554,7 @@ t4_setup_port_queues(struct port_info *pi) */ ctrlq = &sc->sge.ctrlq[pi->port_id]; iqid = port_intr_iq(pi, 0)->cntxt_id; - init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid); + init_eq(sc, &ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid); rc = alloc_wrq(sc, pi, ctrlq, 0); done: @@ -922,7 +924,7 @@ t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, mblk_t *m0) /* Header of a tx LSO WR, before SGL of first packet (in flits) */ #define TXPKT_LSO_WR_HDR ((\ sizeof (struct fw_eth_tx_pkt_wr) + \ - sizeof (struct cpl_tx_pkt_lso) + \ + sizeof(struct cpl_tx_pkt_lso_core) + \ sizeof (struct cpl_tx_pkt_core)) / 8) mblk_t * @@ -1070,12 +1072,22 @@ init_fl(struct sge_fl *fl, uint16_t qsize) } static inline void -init_eq(struct sge_eq *eq, uint16_t eqtype, uint16_t qsize, uint8_t tx_chan, - uint16_t iqid) +init_eq(struct adapter *sc, struct sge_eq *eq, uint16_t eqtype, uint16_t qsize, + uint8_t tx_chan, uint16_t iqid) { + struct sge *s = &sc->sge; + uint32_t r; + ASSERT(tx_chan < NCHAN); ASSERT(eqtype <= EQ_TYPEMASK); + if (is_t5(sc->params.chip)) { + r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); + r >>= S_QUEUESPERPAGEPF0 + + (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf; + s->s_qpp = r & M_QUEUESPERPAGEPF0; + } + eq->flags = eqtype & EQ_TYPEMASK; eq->tx_chan = tx_chan; eq->iqid = iqid; @@ -1098,7 +1110,7 @@ static int alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, int intr_idx, int cong) { - int rc, cntxt_id; + int rc, i, cntxt_id; size_t len; struct fw_iq_cmd c; struct adapter *sc = iq->adapter; @@ -1217,6 +1229,31 @@ alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl, iq->flags |= IQ_HAS_FL; } + if (is_t5(sc->params.chip) && cong >= 0) { + uint32_t param, val; + + param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | + V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) | + V_FW_PARAMS_PARAM_YZ(iq->cntxt_id); + if (cong == 0) + val = 1 << 19; + else { + val = 2 << 19; + for (i = 0; i < 4; i++) { + if (cong & (1 << i)) + val |= 1 << (i << 2); + } + } + + rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val); + if (rc != 0) { + /* report error but carry on */ + cxgb_printf(sc->dip, CE_WARN, + "failed to set congestion manager context for " + "ingress queue %d: %d", iq->cntxt_id, rc); + } + } + /* Enable IQ interrupts */ iq->state = IQS_IDLE; t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) | @@ -1314,7 +1351,7 @@ alloc_mgmtq(struct adapter *sc) int rc; struct sge_wrq *mgmtq = &sc->sge.mgmtq; - init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, + init_eq(sc, &mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan, sc->sge.fwq.cntxt_id); rc = alloc_wrq(sc, NULL, mgmtq, 0); if (rc != 0) { @@ -1536,6 +1573,7 @@ alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) eq->spg = (void *)&eq->desc[eq->cap]; eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */ eq->pidx = eq->cidx = 0; + eq->doorbells = sc->doorbells; switch (eq->flags & EQ_TYPEMASK) { case EQ_CTRL: @@ -1556,6 +1594,25 @@ alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq) panic("%s: invalid eq type %d.", __func__, eq->flags & EQ_TYPEMASK); } + + if (eq->doorbells & + (DOORBELL_UDB | DOORBELL_UDBWC | DOORBELL_WCWR)) { + uint32_t s_qpp = sc->sge.s_qpp; + uint32_t mask = (1 << s_qpp) - 1; + volatile uint8_t *udb; + + udb = (volatile uint8_t *)sc->reg1p + UDBS_DB_OFFSET; + udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */ + eq->udb_qid = eq->cntxt_id & mask; /* id in page */ + if (eq->udb_qid > PAGE_SIZE / UDBS_SEG_SIZE) + eq->doorbells &= ~DOORBELL_WCWR; + else { + udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */ + eq->udb_qid = 0; + } + eq->udb = (volatile void *)udb; + } + if (rc != 0) { cxgb_printf(sc->dip, CE_WARN, "failed to allocate egress queue(%d): %d", @@ -2578,7 +2635,7 @@ write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, mblk_t *m, ctrl = sizeof (struct cpl_tx_pkt_core); if (txinfo->flags & HW_LSO) { nflits = TXPKT_LSO_WR_HDR; - ctrl += sizeof (struct cpl_tx_pkt_lso); + ctrl += sizeof(struct cpl_tx_pkt_lso_core); } else nflits = TXPKT_WR_HDR; if (txinfo->nsegs > 0) @@ -2602,7 +2659,7 @@ write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, mblk_t *m, wr->r3 = 0; if (txinfo->flags & HW_LSO) { - struct cpl_tx_pkt_lso *lso = (void *)(wr + 1); + struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1); char *p = (void *)m->b_rptr; ctrl = V_LSO_OPCODE((u32)CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE; @@ -2625,7 +2682,10 @@ write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, mblk_t *m, lso->ipid_ofst = cpu_to_be16(0); lso->mss = cpu_to_be16(txinfo->mss); lso->seqno_offset = cpu_to_be32(0); - lso->len = cpu_to_be32(txinfo->len); + if (is_t4(pi->adapter->params.chip)) + lso->len = cpu_to_be32(txinfo->len); + else + lso->len = cpu_to_be32(V_LSO_T5_XFER_SIZE(txinfo->len)); cpl = (void *)(lso + 1); @@ -2800,6 +2860,12 @@ copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len) static inline void ring_tx_db(struct adapter *sc, struct sge_eq *eq) { + int val, db_mode; + u_int db = eq->doorbells; + + if (eq->pending > 1) + db &= ~DOORBELL_WCWR; + if (eq->pending > eq->pidx) { int offset = eq->cap - (eq->pending - eq->pidx); @@ -2820,9 +2886,50 @@ ring_tx_db(struct adapter *sc, struct sge_eq *eq) membar_producer(); - t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), - V_QID(eq->cntxt_id) | V_PIDX(eq->pending)); + if (is_t4(sc->params.chip)) + val = V_PIDX(eq->pending); + else + val = V_PIDX_T5(eq->pending); + + db_mode = (1 << (ffs(db) - 1)); + switch (db_mode) { + case DOORBELL_UDB: + *eq->udb = LE_32(V_QID(eq->udb_qid) | val); + break; + + case DOORBELL_WCWR: + { + volatile uint64_t *dst, *src; + int i; + /* + * Queues whose 128B doorbell segment fits in + * the page do not use relative qid + * (udb_qid is always 0). Only queues with + * doorbell segments can do WCWR. + */ + ASSERT(eq->udb_qid == 0 && eq->pending == 1); + + dst = (volatile void *)((uintptr_t)eq->udb + + UDBS_WR_OFFSET - UDBS_DB_OFFSET); + i = eq->pidx ? eq->pidx - 1 : eq->cap - 1; + src = (void *)&eq->desc[i]; + while (src != (void *)&eq->desc[i + 1]) + *dst++ = *src++; + membar_producer(); + break; + } + + case DOORBELL_UDBWC: + *eq->udb = LE_32(V_QID(eq->udb_qid) | val); + membar_producer(); + break; + case DOORBELL_KDB: + t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), + V_QID(eq->cntxt_id) | val); + break; + } + eq->pending = 0; } @@ -2964,6 +3071,7 @@ static inline void ring_fl_db(struct adapter *sc, struct sge_fl *fl) { int desc_start, desc_last, ndesc; + uint32_t v; ndesc = FL_HW_IDX(fl->pending); @@ -2999,10 +3107,15 @@ ring_fl_db(struct adapter *sc, struct sge_fl *fl) ndesc * RX_FL_ESIZE, DDI_DMA_SYNC_FORDEV); } + if (is_t4(sc->params.chip)) + v = V_PIDX(ndesc); + else + v = V_PIDX_T5(ndesc) | F_DBTYPE; + v |= F_DBPRIO | V_QID(fl->cntxt_id) | V_PIDX(ndesc); + membar_producer(); - t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), F_DBPRIO | - V_QID(fl->cntxt_id) | V_PIDX(ndesc)); + t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v); /* * Update pending count: @@ -3015,14 +3128,18 @@ ring_fl_db(struct adapter *sc, struct sge_fl *fl) static int handle_fw_rpl(struct sge_iq *iq, const struct rss_header *rss, mblk_t *m) { + struct adapter *sc = iq->adapter; const struct cpl_fw6_msg *cpl = (const void *)(rss + 1); ASSERT(m == NULL); - if (cpl->type == FW6_TYPE_CMD_RPL) - (void) t4_handle_fw_rpl(iq->adapter, cpl->data); + if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) { + const struct rss_header *rss2; - return (0); + rss2 = (const struct rss_header *)&cpl->data[0]; + return (sc->cpl_handler[rss2->opcode](iq, rss2, m)); + } + return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0])); } int diff --git a/usr/src/uts/common/io/cxgbe/t4nex/t4nex.h b/usr/src/uts/common/io/cxgbe/t4nex/t4nex.h index dd48e6c48b..5e8cd96a36 100644 --- a/usr/src/uts/common/io/cxgbe/t4nex/t4nex.h +++ b/usr/src/uts/common/io/cxgbe/t4nex/t4nex.h @@ -55,6 +55,7 @@ struct t4_reg32_cmd { }; #define T4_REGDUMP_SIZE (160 * 1024) +#define T5_REGDUMP_SIZE (332 * 1024) struct t4_regdump { uint32_t version; uint32_t len; @@ -103,10 +104,12 @@ struct t4_edc { }; struct t4_cim_qcfg { - uint16_t base[6]; - uint16_t size[6]; + uint16_t base[14]; + uint16_t size[14]; uint16_t thres[6]; - uint32_t stat[4 * (6)]; + uint32_t stat[4 * (6 + 8)]; + uint32_t obq_wr[2 * (8)]; + uint32_t num_obq; }; #define T4_DEVLOG_SIZE 32768 |