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| author | Hans Rosenfeld <hans.rosenfeld@joyent.com> | 2017-12-04 15:14:24 +0100 |
|---|---|---|
| committer | Robert Mustacchi <rm@joyent.com> | 2019-08-19 17:40:33 +0000 |
| commit | 9b3f4fe3313810d1280baca5f5801796a0800d2b (patch) | |
| tree | f11548dad45bc5e31674b68dd55aa83f6e97fb23 | |
| parent | 662dc8a578c4b6decf73ecc776c43128bac8dc83 (diff) | |
| download | illumos-joyent-9b3f4fe3313810d1280baca5f5801796a0800d2b.tar.gz | |
11368 pcie changes for bhyve ppt
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>
Reviewed by: Mike Gerdts <mike.gerdts@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Reviewed by: Andy Fiddaman <andy@omniosce.org>
Reviewed by: Norm Jacobs <naj@snapcon.com>
Approved by: Richard Lowe <richlowe@richlowe.net>
| -rw-r--r-- | usr/src/uts/common/io/pciex/pcie.c | 5 | ||||
| -rw-r--r-- | usr/src/uts/common/sys/pcie.h | 5 | ||||
| -rw-r--r-- | usr/src/uts/common/sys/pcie_impl.h | 1 |
3 files changed, 9 insertions, 2 deletions
diff --git a/usr/src/uts/common/io/pciex/pcie.c b/usr/src/uts/common/io/pciex/pcie.c index 427663e4f5..5e3d92d5a4 100644 --- a/usr/src/uts/common/io/pciex/pcie.c +++ b/usr/src/uts/common/io/pciex/pcie.c @@ -1490,14 +1490,15 @@ pcie_get_rc_dip(dev_info_t *dip) return (rcdip); } -static boolean_t +boolean_t pcie_is_pci_device(dev_info_t *dip) { dev_info_t *pdip; char *device_type; pdip = ddi_get_parent(dip); - ASSERT(pdip); + if (pdip == NULL) + return (B_FALSE); if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, "device_type", &device_type) != DDI_PROP_SUCCESS) diff --git a/usr/src/uts/common/sys/pcie.h b/usr/src/uts/common/sys/pcie.h index d1b633a040..0e5f929164 100644 --- a/usr/src/uts/common/sys/pcie.h +++ b/usr/src/uts/common/sys/pcie.h @@ -143,6 +143,8 @@ extern "C" { #define PCIE_DEVCAP_PLMT_SCL_1_BY_1000 0xC000000 /* 0.001x Scale */ #define PCIE_DEVCAP_PLMT_SCL_MASK 0xC000000 /* Power Limit Scale */ +#define PCIE_DEVCAP_FLR 0x10000000 /* Function Level Reset */ + /* * Device Control Register (2 bytes) */ @@ -177,6 +179,8 @@ extern "C" { #define PCIE_DEVCTL_MAX_READ_REQ_MASK 0x7000 /* Max_Read_Request_Size */ #define PCIE_DEVCTL_MAX_READ_REQ_SHIFT 0xC +#define PCIE_DEVCTL_INITIATE_FLR 0x8000 + /* * Device Status Register (2 bytes) */ @@ -398,6 +402,7 @@ extern "C" { /* * Device Control 2 Register (2 bytes) */ +#define PCIE_DEVCTL2_COM_TO_RANGE_MASK 0xf #define PCIE_DEVCTL2_COM_TO_RANGE_0 0x0 #define PCIE_DEVCTL2_COM_TO_RANGE_1 0x1 #define PCIE_DEVCTL2_COM_TO_RANGE_2 0x2 diff --git a/usr/src/uts/common/sys/pcie_impl.h b/usr/src/uts/common/sys/pcie_impl.h index 9dfa8ce067..9e9e96e8fd 100644 --- a/usr/src/uts/common/sys/pcie_impl.h +++ b/usr/src/uts/common/sys/pcie_impl.h @@ -560,6 +560,7 @@ extern void pcie_enable_errors(dev_info_t *dip); extern void pcie_disable_errors(dev_info_t *dip); extern int pcie_enable_ce(dev_info_t *dip); extern boolean_t pcie_bridge_is_link_disabled(dev_info_t *); +extern boolean_t pcie_is_pci_device(dev_info_t *dip); extern pcie_bus_t *pcie_init_bus(dev_info_t *dip, pcie_req_id_t bdf, uint8_t flags); |