OS-7010 update sys/elf.h for recent processors like aarch64/risc-v

Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Richard Lowe <richlowe@richlowe.net>
Reviewed by: Jake Saferstein <jake.saferstein@joyent.com>
Approved by: Jerry Jelinek <jerry.jelinek@joyent.com>

4 files changed, 939 insertions, 221 deletions

diff --git a/usr/src/cmd/file/file.c b/usr/src/cmd/file/file.c
index 6c7989d735..64379f3919 100644
--- a/usr/src/cmd/file/file.c
+++ b/usr/src/cmd/file/file.c
@@ -28,6 +28,7 @@
 /*
  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
+ * Copyright (c) 2018, Joyent, Inc.
  */
 
 #define	_LARGEFILE64_SOURCE
@@ -980,104 +981,188 @@ print_elf_machine(int machine)
 	 * in /usr/include/sys/elf.h.
 	 */
 	static const char *mach_str[EM_NUM] = {
-		"unknown machine",		/* 0 - EM_NONE */
-		"WE32100",			/* 1 - EM_M32 */
-		"SPARC",			/* 2 - EM_SPARC */
-		"80386",			/* 3 - EM_386 */
-		"M68000",			/* 4 - EM_68K */
-		"M88000",			/* 5 - EM_88K */
-		"80486",			/* 6 - EM_486 */
-		"i860",				/* 7 - EM_860 */
-		"MIPS RS3000 Big-Endian",	/* 8 - EM_MIPS */
-		"S/370",			/* 9 - EM_S370 */
-		"MIPS RS3000 Little-Endian",	/* 10 - EM_MIPS_RS3_LE */
-		"MIPS RS6000",			/* 11 - EM_RS6000 */
-		NULL,				/* 12 - EM_UNKNOWN12 */
-		NULL,				/* 13 - EM_UNKNOWN13 */
-		NULL,				/* 14 - EM_UNKNOWN14 */
-		"PA-RISC",			/* 15 - EM_PA_RISC */
-		"nCUBE",			/* 16 - EM_nCUBE */
-		"VPP500",			/* 17 - EM_VPP500 */
-		"SPARC32PLUS",			/* 18 - EM_SPARC32PLUS */
-		"i960",				/* 19 - EM_960 */
-		"PowerPC",			/* 20 - EM_PPC */
-		"PowerPC64",			/* 21 - EM_PPC64 */
-		"S/390",			/* 22 - EM_S390 */
-		NULL,				/* 23 - EM_UNKNOWN23 */
-		NULL,				/* 24 - EM_UNKNOWN24 */
-		NULL,				/* 25 - EM_UNKNOWN25 */
-		NULL,				/* 26 - EM_UNKNOWN26 */
-		NULL,				/* 27 - EM_UNKNOWN27 */
-		NULL,				/* 28 - EM_UNKNOWN28 */
-		NULL,				/* 29 - EM_UNKNOWN29 */
-		NULL,				/* 30 - EM_UNKNOWN30 */
-		NULL,				/* 31 - EM_UNKNOWN31 */
-		NULL,				/* 32 - EM_UNKNOWN32 */
-		NULL,				/* 33 - EM_UNKNOWN33 */
-		NULL,				/* 34 - EM_UNKNOWN34 */
-		NULL,				/* 35 - EM_UNKNOWN35 */
-		"V800",				/* 36 - EM_V800 */
-		"FR20",				/* 37 - EM_FR20 */
-		"RH32",				/* 38 - EM_RH32 */
-		"RCE",				/* 39 - EM_RCE */
-		"ARM",				/* 40 - EM_ARM */
-		"Alpha",			/* 41 - EM_ALPHA */
-		"S/390",			/* 42 - EM_SH */
-		"SPARCV9",			/* 43 - EM_SPARCV9 */
-		"Tricore",			/* 44 - EM_TRICORE */
-		"ARC",				/* 45 - EM_ARC */
-		"H8/300",			/* 46 - EM_H8_300 */
-		"H8/300H",			/* 47 - EM_H8_300H */
-		"H8S",				/* 48 - EM_H8S */
-		"H8/500",			/* 49 - EM_H8_500 */
-		"IA64",				/* 50 - EM_IA_64 */
-		"MIPS-X",			/* 51 - EM_MIPS_X */
-		"Coldfire",			/* 52 - EM_COLDFIRE */
-		"M68HC12",			/* 53 - EM_68HC12 */
-		"MMA",				/* 54 - EM_MMA */
-		"PCP",				/* 55 - EM_PCP */
-		"nCPU",				/* 56 - EM_NCPU */
-		"NDR1",				/* 57 - EM_NDR1 */
-		"Starcore",			/* 58 - EM_STARCORE */
-		"ME16",				/* 59 - EM_ME16 */
-		"ST100",			/* 60 - EM_ST100 */
-		"TINYJ",			/* 61 - EM_TINYJ */
-		"AMD64",			/* 62 - EM_AMD64 */
-		"PDSP",				/* 63 - EM_PDSP */
-		NULL,				/* 64 - EM_UNKNOWN64 */
-		NULL,				/* 65 - EM_UNKNOWN65 */
-		"FX66",				/* 66 - EM_FX66 */
-		"ST9 PLUS",			/* 67 - EM_ST9PLUS */
-		"ST7",				/* 68 - EM_ST7 */
-		"68HC16",			/* 69 - EM_68HC16 */
-		"68HC11",			/* 70 - EM_68HC11 */
-		"68H08",			/* 71 - EM_68HC08 */
-		"68HC05",			/* 72 - EM_68HC05 */
-		"SVX",				/* 73 - EM_SVX */
-		"ST19",				/* 74 - EM_ST19 */
-		"VAX",				/* 75 - EM_VAX */
-		"CRIS",				/* 76 - EM_CRIS */
-		"Javelin",			/* 77 - EM_JAVELIN */
-		"Firepath",			/* 78 - EM_FIREPATH */
-		"ZSP",				/* 79 - EM_ZSP */
-		"MMIX",				/* 80 - EM_MMIX */
-		"HUANY",			/* 81 - EM_HUANY */
-		"Prism",			/* 82 - EM_PRISM */
-		"AVR",				/* 83 - EM_AVR */
-		"FR30",				/* 84 - EM_FR30 */
-		"D10V",				/* 85 - EM_D10V */
-		"D30V",				/* 86 - EM_D30V */
-		"V850",				/* 87 - EM_V850 */
-		"M32R",				/* 88 - EM_M32R */
-		"MN10300",			/* 89 - EM_MN10300 */
-		"MN10200",			/* 90 - EM_MN10200 */
-		"picoJava",			/* 91 - EM_PJ */
-		"OpenRISC",			/* 92 - EM_OPENRISC */
-		"Tangent-A5",			/* 93 - EM_ARC_A5 */
-		"Xtensa"			/* 94 - EM_XTENSA */
+		[EM_NONE] = "unknown machine",
+		[EM_M32] = "WE32100",
+		[EM_SPARC] = "SPARC",
+		[EM_386] = "80386",
+		[EM_68K] = "M68000",
+		[EM_88K] = "M88000",
+		[EM_486] = "80486",
+		[EM_860] = "i860",
+		[EM_MIPS] = "MIPS RS3000 Big-Endian",
+		[EM_S370] = "S/370",
+		[EM_MIPS_RS3_LE] = "MIPS RS3000 Little-Endian",
+		[EM_RS6000] = "MIPS RS6000",
+		[EM_PA_RISC] = "PA-RISC",
+		[EM_nCUBE] = "nCUBE",
+		[EM_VPP500] = "VPP500",
+		[EM_SPARC32PLUS] = "SPARC32PLUS",
+		[EM_960] = "i960",
+		[EM_PPC] = "PowerPC",
+		[EM_PPC64] = "PowerPC64",
+		[EM_S390] = "S/390",
+		[EM_V800] = "V800",
+		[EM_FR20] = "FR20",
+		[EM_RH32] = "RH32",
+		[EM_RCE] = "RCE",
+		[EM_ARM] = "ARM",
+		[EM_ALPHA] = "Alpha",
+		[EM_SH] = "S/390",
+		[EM_SPARCV9] = "SPARCV9",
+		[EM_TRICORE] = "Tricore",
+		[EM_ARC] = "ARC",
+		[EM_H8_300] = "H8/300",
+		[EM_H8_300H] = "H8/300H",
+		[EM_H8S] = "H8S",
+		[EM_H8_500] = "H8/500",
+		[EM_IA_64] = "IA64",
+		[EM_MIPS_X] = "MIPS-X",
+		[EM_COLDFIRE] = "Coldfire",
+		[EM_68HC12] = "M68HC12",
+		[EM_MMA] = "MMA",
+		[EM_PCP] = "PCP",
+		[EM_NCPU] = "nCPU",
+		[EM_NDR1] = "NDR1",
+		[EM_STARCORE] = "Starcore",
+		[EM_ME16] = "ME16",
+		[EM_ST100] = "ST100",
+		[EM_TINYJ] = "TINYJ",
+		[EM_AMD64] = "AMD64",
+		[EM_PDSP] = "PDSP",
+		[EM_FX66] = "FX66",
+		[EM_ST9PLUS] = "ST9 PLUS",
+		[EM_ST7] = "ST7",
+		[EM_68HC16] = "68HC16",
+		[EM_68HC11] = "68HC11",
+		[EM_68HC08] = "68H08",
+		[EM_68HC05] = "68HC05",
+		[EM_SVX] = "SVX",
+		[EM_ST19] = "ST19",
+		[EM_VAX] = "VAX",
+		[EM_CRIS] = "CRIS",
+		[EM_JAVELIN] = "Javelin",
+		[EM_FIREPATH] = "Firepath",
+		[EM_ZSP] = "ZSP",
+		[EM_MMIX] = "MMIX",
+		[EM_HUANY] = "HUANY",
+		[EM_PRISM] = "Prism",
+		[EM_AVR] = "AVR",
+		[EM_FR30] = "FR30",
+		[EM_D10V] = "D10V",
+		[EM_D30V] = "D30V",
+		[EM_V850] = "V850",
+		[EM_M32R] = "M32R",
+		[EM_MN10300] = "MN10300",
+		[EM_MN10200] = "MN10200",
+		[EM_PJ] = "picoJava",
+		[EM_OPENRISC] = "OpenRISC",
+		[EM_ARC_A5] = "Tangent-A5",
+		[EM_XTENSA] = "Xtensa",
+
+		[EM_VIDEOCORE] = "Videocore",
+		[EM_TMM_GPP] = "TMM_GPP",
+		[EM_NS32K] = "NS32K",
+		[EM_TPC] = "TPC",
+		[EM_SNP1K] = "SNP1K",
+		[EM_ST200] = "ST200",
+		[EM_IP2K] = "IP2K",
+		[EM_MAX] = "MAX",
+		[EM_CR] = "CompactRISC",
+		[EM_F2MC16] = "F2MC16",
+		[EM_MSP430] = "MSP430",
+		[EM_BLACKFIN] = "Blackfin",
+		[EM_SE_C33] = "S1C33",
+		[EM_SEP] = "SEP",
+		[EM_ARCA] = "Arca",
+		[EM_UNICORE] = "Unicore",
+		[EM_EXCESS] = "eXcess",
+		[EM_DXP] = "DXP",
+		[EM_ALTERA_NIOS2] = "Nios 2",
+		[EM_CRX] = "CompactRISC CRX",
+		[EM_XGATE] = "XGATE",
+		[EM_C166] = "C16x/XC16x",
+		[EM_M16C] = "M16C",
+		[EM_DSPIC30F] = "dsPIC30F",
+		[EM_CE] = "CE RISC",
+		[EM_M32C] = "M32C",
+		[EM_TSK3000] = "TSK3000",
+		[EM_RS08] = "RS08",
+		[EM_SHARC] = "SHARC",
+		[EM_ECOG2] = "eCOG2",
+		[EM_SCORE7] = "SCORE7",
+		[EM_DSP24] = "DSP24",
+		[EM_VIDEOCORE3] = "Videocore III",
+		[EM_LATTICEMICO32] = "LATTICEMICO32",
+		[EM_SE_C17] = "SE_C17",
+		[EM_TI_C6000] = "TMS320C6000",
+		[EM_TI_C2000] = "TMS320C2000",
+		[EM_TI_C5500] = "TMS320C55x",
+		[EM_TI_ARP32] = "ASRP32",
+		[EM_TI_PRU] = "TI_PRU",
+		[EM_MMDSP_PLUS] = "MMDSP_PLUS",
+		[EM_CYPRESS_M8C] = "M8C",
+		[EM_R32C] = "R32C",
+		[EM_TRIMEDIA] = "TriMedia",
+		[EM_QDSP6] = "QDSP6",
+		[EM_8051] = "8051",
+		[EM_STXP7X] = "STxP7x",
+		[EM_NDS32] = "NDS32",
+		[EM_ECOG1] = "eCOG1X",
+		[EM_MAXQ30] = "MAXQ30",
+		[EM_XIMO16] = "XIMO16",
+		[EM_MANIK] = "M2000",
+		[EM_CRAYNV2] = "CRAYNV2",
+		[EM_RX] = "RX",
+		[EM_METAG] = "METAG",
+		[EM_MCST_ELBRUS] = "Elbrus",
+		[EM_ECOG16] = "eCOG16",
+		[EM_CR16] = "CR16",
+		[EM_ETPU] = "ETPU",
+		[EM_SLE9X] = "SLE9X",
+		[EM_L10M] = "L10M",
+		[EM_K10M] = "K10M",
+
+		[EM_AARCH64] = "aarch64",
+
+		[EM_AVR32] = "AVR32",
+		[EM_STM8] = "STM8",
+		[EM_TILE64] = "TILE64",
+		[EM_TILEPRO] = "TILEPRO",
+		[EM_MICROBLAZE] = "MicroBlaze",
+		[EM_CUDA] = "CUDA",
+		[EM_TILEGX] = "TILE-Gx",
+		[EM_CLOUDSHIELD] = "CloudShield",
+		[EM_COREA_1ST] = "CORE-A 1st",
+		[EM_COREA_2ND] = "CORE-A 2nd",
+		[EM_ARC_COMPACT2] = "ARCompact V2",
+		[EM_OPEN8] = "Open8",
+		[EM_RL78] = "RL78",
+		[EM_VIDEOCORE5] = "VideoCore V",
+		[EM_78KOR] = "78KOR",
+		[EM_56800EX] = "56800EX",
+		[EM_BA1] = "BA1",
+		[EM_BA2] = "BA2",
+		[EM_XCORE] = "xCORE",
+		[EM_MCHP_PIC] = "MCHP_PIC",
+		[EM_KM32] = "KM32",
+		[EM_KMX32] = "KMX32",
+		[EM_KMX16] = "KMX16",
+		[EM_KMX8] = "KMX8",
+		[EM_KVARC] = "KVARC",
+		[EM_CDP] = "CDP",
+		[EM_COGE] = "COGE",
+		[EM_COOL] = "CoolEngine",
+		[EM_NORC] = "NORC",
+		[EM_CSR_KALIMBA] = "Kalimba",
+		[EM_Z80] = "Zilog Z80",
+		[EM_VISIUM] = "VISIUMcore",
+		[EM_FT32] = "FT32",
+		[EM_MOXIE] = "Moxie",
+		[EM_AMDGPU] = "AMD GPU",
+		[EM_RISCV] = "RISC-V"
 	};
 	/* If new machine is added, refuse to compile until we're updated */
-#if EM_NUM != 95
+#if EM_NUM != 244
 #error "Number of known ELF machine constants has changed"
 #endif
 
diff --git a/usr/src/cmd/sgs/libconv/common/elf.c b/usr/src/cmd/sgs/libconv/common/elf.c
index 73469c3506..4808b887b2 100644
--- a/usr/src/cmd/sgs/libconv/common/elf.c
+++ b/usr/src/cmd/sgs/libconv/common/elf.c
@@ -21,6 +21,7 @@
 
 /*
  * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2018, Joyent, Inc.
  */
 
 /*
@@ -265,7 +266,7 @@ ehdr_mach_strings(Conv_fmt_flags_t fmt_flags)
 	    CONV_DS_MSG_INIT(EM_V800, mach_36_63_dmp) };
 
 
-	static const Msg mach_66_94_cf[] = {
+	static const Msg mach_66_120_cf[] = {
 		MSG_EM_FX66_CF,		MSG_EM_ST9PLUS_CF,
 		MSG_EM_ST7_CF,		MSG_EM_68HC16_CF,
 		MSG_EM_68HC11_CF,	MSG_EM_68HC08_CF,
@@ -280,9 +281,22 @@ ehdr_mach_strings(Conv_fmt_flags_t fmt_flags)
 		MSG_EM_M32R_CF,		MSG_EM_MN10300_CF,
 		MSG_EM_MN10200_CF,	MSG_EM_PJ_CF,
 		MSG_EM_OPENRISC_CF,	MSG_EM_ARC_A5_CF,
-		MSG_EM_XTENSA_CF
+		MSG_EM_XTENSA_CF,	MSG_EM_VIDEOCORE_CF,
+		MSG_EM_TMM_GPP_CF,	MSG_EM_NS32K_CF,
+		MSG_EM_TPC_CF,		MSG_EM_SNP1K_CF,
+		MSG_EM_ST200_CF,	MSG_EM_IP2K_CF,
+		MSG_EM_MAX_CF,		MSG_EM_CR_CF,
+		MSG_EM_F2MC16_CF,	MSG_EM_MSP430_CF,
+		MSG_EM_BLACKFIN_CF,	MSG_EM_SE_C33_CF,
+		MSG_EM_SEP_CF,		MSG_EM_ARCA_CF,
+		MSG_EM_UNICORE_CF,	MSG_EM_EXCESS_CF,
+		MSG_EM_DXP_CF,		MSG_EM_ALTERA_NIOS2_CF,
+		MSG_EM_CRX_CF,		MSG_EM_XGATE_CF,
+		MSG_EM_C166_CF,		MSG_EM_M16C_CF,
+		MSG_EM_DSPIC30F_CF,	MSG_EM_CE_CF,
+		MSG_EM_M32C_CF
 	};
-	static const Msg mach_66_94_nf[] = {
+	static const Msg mach_66_120_nf[] = {
 		MSG_EM_FX66_NF,		MSG_EM_ST9PLUS_NF,
 		MSG_EM_ST7_NF,		MSG_EM_68HC16_NF,
 		MSG_EM_68HC11_NF,	MSG_EM_68HC08_NF,
@@ -297,9 +311,28 @@ ehdr_mach_strings(Conv_fmt_flags_t fmt_flags)
 		MSG_EM_M32R_NF,		MSG_EM_MN10300_NF,
 		MSG_EM_MN10200_NF,	MSG_EM_PJ_NF,
 		MSG_EM_OPENRISC_NF,	MSG_EM_ARC_A5_NF,
-		MSG_EM_XTENSA_NF
+		MSG_EM_XTENSA_NF,	MSG_EM_VIDEOCORE_NF,
+		MSG_EM_TMM_GPP_NF,	MSG_EM_NS32K_NF,
+		MSG_EM_TPC_NF,		MSG_EM_SNP1K_NF,
+		MSG_EM_ST200_NF,	MSG_EM_IP2K_NF,
+		MSG_EM_MAX_NF,		MSG_EM_CR_NF,
+		MSG_EM_F2MC16_NF,	MSG_EM_MSP430_NF,
+		MSG_EM_BLACKFIN_NF,	MSG_EM_SE_C33_NF,
+		MSG_EM_SEP_NF,		MSG_EM_ARCA_NF,
+		MSG_EM_UNICORE_NF,	MSG_EM_EXCESS_NF,
+		MSG_EM_DXP_NF,		MSG_EM_ALTERA_NIOS2_NF,
+		MSG_EM_CRX_NF,		MSG_EM_XGATE_NF,
+		MSG_EM_C166_NF,		MSG_EM_M16C_NF,
+		MSG_EM_DSPIC30F_NF,	MSG_EM_CE_NF,
+		MSG_EM_TSK3000_NF,	MSG_EM_RS08_NF,
+		MSG_EM_SHARC_NF,	MSG_EM_ECOG2_NF,
+		MSG_EM_SCORE7_NF,	MSG_EM_DSP24_NF,
+		MSG_EM_VIDEOCORE3_NF,	MSG_EM_LATTICEMICO32_NF,
+		MSG_EM_SE_C17_NF,	MSG_EM_TI_C6000_NF,
+		MSG_EM_TI_C2000_NF,	MSG_EM_TI_C5500_NF,
+		MSG_EM_TI_ARP32_NF,	MSG_EM_TI_PRU_NF
 	};
-	static const Msg mach_66_94_dmp[] = {
+	static const Msg mach_66_120_dmp[] = {
 		MSG_EM_FX66_CF,		MSG_EM_ST9PLUS_CF,
 		MSG_EM_ST7_CF,		MSG_EM_68HC16_CF,
 		MSG_EM_68HC11_CF,	MSG_EM_68HC08_CF,
@@ -314,34 +347,256 @@ ehdr_mach_strings(Conv_fmt_flags_t fmt_flags)
 		MSG_EM_M32R_CF,		MSG_EM_MN10300_CF,
 		MSG_EM_MN10200_CF,	MSG_EM_PJ_CF,
 		MSG_EM_OPENRISC_CF,	MSG_EM_ARC_A5_CF,
-		MSG_EM_XTENSA_CF
+		MSG_EM_XTENSA_CF,	MSG_EM_VIDEOCORE_CF,
+		MSG_EM_TMM_GPP_CF,	MSG_EM_NS32K_CF,
+		MSG_EM_TPC_CF,		MSG_EM_SNP1K_CF,
+		MSG_EM_ST200_CF,	MSG_EM_IP2K_CF,
+		MSG_EM_MAX_CF,		MSG_EM_CR_CF,
+		MSG_EM_F2MC16_CF,	MSG_EM_MSP430_CF,
+		MSG_EM_BLACKFIN_CF,	MSG_EM_SE_C33_CF,
+		MSG_EM_SEP_CF,		MSG_EM_ARCA_CF,
+		MSG_EM_UNICORE_CF,	MSG_EM_EXCESS_CF,
+		MSG_EM_DXP_CF,		MSG_EM_ALTERA_NIOS2_CF,
+		MSG_EM_CRX_CF,		MSG_EM_XGATE_CF,
+		MSG_EM_C166_CF,		MSG_EM_M16C_CF,
+		MSG_EM_DSPIC30F_CF,	MSG_EM_CE_CF,
+		MSG_EM_M32C_CF
+	};
+
+	static const conv_ds_msg_t ds_mach_66_120_cf = {
+	    CONV_DS_MSG_INIT(EM_FX66, mach_66_120_cf) };
+	static const conv_ds_msg_t ds_mach_66_120_nf = {
+	    CONV_DS_MSG_INIT(EM_FX66, mach_66_120_nf) };
+	static const conv_ds_msg_t ds_mach_66_120_dmp = {
+	    CONV_DS_MSG_INIT(EM_FX66, mach_66_120_dmp) };
+
+	static const Msg mach_131_144_cf[] = {
+		MSG_EM_TSK3000_CF,	MSG_EM_RS08_CF,
+		MSG_EM_SHARC_CF,	MSG_EM_ECOG2_CF,
+		MSG_EM_SCORE7_CF,	MSG_EM_DSP24_CF,
+		MSG_EM_VIDEOCORE3_CF,	MSG_EM_LATTICEMICO32_CF,
+		MSG_EM_SE_C17_CF,	MSG_EM_TI_C6000_CF,
+		MSG_EM_TI_C2000_CF,	MSG_EM_TI_C5500_CF,
+		MSG_EM_TI_ARP32_CF,	MSG_EM_TI_PRU_CF
+	};
+	static const Msg mach_131_144_nf[] = {
+		MSG_EM_TSK3000_NF,	MSG_EM_RS08_NF,
+		MSG_EM_SHARC_NF,	MSG_EM_ECOG2_NF,
+		MSG_EM_SCORE7_NF,	MSG_EM_DSP24_NF,
+		MSG_EM_VIDEOCORE3_NF,	MSG_EM_LATTICEMICO32_NF,
+		MSG_EM_SE_C17_NF,	MSG_EM_TI_C6000_NF,
+		MSG_EM_TI_C2000_NF,	MSG_EM_TI_C5500_NF,
+		MSG_EM_TI_ARP32_NF,	MSG_EM_TI_PRU_NF
+	};
+	static const Msg mach_131_144_dmp[] = {
+		MSG_EM_TSK3000_CF,	MSG_EM_RS08_CF,
+		MSG_EM_SHARC_CF,	MSG_EM_ECOG2_CF,
+		MSG_EM_SCORE7_CF,	MSG_EM_DSP24_CF,
+		MSG_EM_VIDEOCORE3_CF,	MSG_EM_LATTICEMICO32_CF,
+		MSG_EM_SE_C17_CF,	MSG_EM_TI_C6000_CF,
+		MSG_EM_TI_C2000_CF,	MSG_EM_TI_C5500_CF,
+		MSG_EM_TI_ARP32_CF,	MSG_EM_TI_PRU_CF
+	};
+	static const conv_ds_msg_t ds_mach_131_144_cf = {
+	    CONV_DS_MSG_INIT(EM_TSK3000, mach_131_144_cf) };
+	static const conv_ds_msg_t ds_mach_131_144_nf = {
+	    CONV_DS_MSG_INIT(EM_TSK3000, mach_131_144_nf) };
+	static const conv_ds_msg_t ds_mach_131_144_dmp = {
+	    CONV_DS_MSG_INIT(EM_TSK3000, mach_131_144_dmp) };
+
+	static const Msg mach_160_181_cf[] = {
+		MSG_EM_MMDSP_PLUS_CF,	MSG_EM_CYPRESS_M8C_CF,
+		MSG_EM_R32C_CF,		MSG_EM_TRIMEDIA_CF,
+		MSG_EM_QDSP6_CF,	MSG_EM_8051_CF,
+		MSG_EM_STXP7X_CF,	MSG_EM_NDS32_CF,
+		MSG_EM_ECOG1_CF,	MSG_EM_MAXQ30_CF,
+		MSG_EM_XIMO16_CF,	MSG_EM_MANIK_CF,
+		MSG_EM_CRAYNV2_CF,	MSG_EM_RX_CF,
+		MSG_EM_METAG_CF,	MSG_EM_MCST_ELBRUS_CF,
+		MSG_EM_ECOG16_CF,	MSG_EM_CR16_CF,
+		MSG_EM_ETPU_CF,		MSG_EM_SLE9X_CF,
+		MSG_EM_L10M_CF,		MSG_EM_K10M_CF,
+	};
+	static const Msg mach_160_181_nf[] = {
+		MSG_EM_MMDSP_PLUS_NF,	MSG_EM_CYPRESS_M8C_NF,
+		MSG_EM_R32C_NF,		MSG_EM_TRIMEDIA_NF,
+		MSG_EM_QDSP6_NF,	MSG_EM_8051_NF,
+		MSG_EM_STXP7X_NF,	MSG_EM_NDS32_NF,
+		MSG_EM_ECOG1_NF,	MSG_EM_MAXQ30_NF,
+		MSG_EM_XIMO16_NF,	MSG_EM_MANIK_NF,
+		MSG_EM_CRAYNV2_NF,	MSG_EM_RX_NF,
+		MSG_EM_METAG_NF,	MSG_EM_MCST_ELBRUS_NF,
+		MSG_EM_ECOG16_NF,	MSG_EM_CR16_NF,
+		MSG_EM_ETPU_NF,		MSG_EM_SLE9X_NF,
+		MSG_EM_L10M_NF,		MSG_EM_K10M_NF,
+	};
+	static const Msg mach_160_181_dmp[] = {
+		MSG_EM_MMDSP_PLUS_CF,	MSG_EM_CYPRESS_M8C_CF,
+		MSG_EM_R32C_CF,		MSG_EM_TRIMEDIA_CF,
+		MSG_EM_QDSP6_CF,	MSG_EM_8051_CF,
+		MSG_EM_STXP7X_CF,	MSG_EM_NDS32_CF,
+		MSG_EM_ECOG1_CF,	MSG_EM_MAXQ30_CF,
+		MSG_EM_XIMO16_CF,	MSG_EM_MANIK_CF,
+		MSG_EM_CRAYNV2_CF,	MSG_EM_RX_CF,
+		MSG_EM_METAG_CF,	MSG_EM_MCST_ELBRUS_CF,
+		MSG_EM_ECOG16_CF,	MSG_EM_CR16_CF,
+		MSG_EM_ETPU_CF,		MSG_EM_SLE9X_CF,
+		MSG_EM_L10M_CF,		MSG_EM_K10M_CF,
+	};
+	static const conv_ds_msg_t ds_mach_160_181_cf = {
+	    CONV_DS_MSG_INIT(EM_MMDSP_PLUS, mach_160_181_cf) };
+	static const conv_ds_msg_t ds_mach_160_181_nf = {
+	    CONV_DS_MSG_INIT(EM_MMDSP_PLUS, mach_160_181_nf) };
+	static const conv_ds_msg_t ds_mach_160_181_dmp = {
+	    CONV_DS_MSG_INIT(EM_MMDSP_PLUS, mach_160_181_dmp) };
+
+	static const Msg mach_183_cf[] = {
+		MSG_EM_AARCH64_CF
+	};
+	static const Msg mach_183_nf[] = {
+		MSG_EM_AARCH64_NF
+	};
+	static const Msg mach_183_dmp[] = {
+		MSG_EM_AARCH64_CF
+	};
+	static const conv_ds_msg_t ds_mach_183_cf = {
+	    CONV_DS_MSG_INIT(EM_AARCH64, mach_183_cf) };
+	static const conv_ds_msg_t ds_mach_183_nf = {
+	    CONV_DS_MSG_INIT(EM_AARCH64, mach_183_nf) };
+	static const conv_ds_msg_t ds_mach_183_dmp = {
+	    CONV_DS_MSG_INIT(EM_AARCH64, mach_183_dmp) };
+
+	static const Msg mach_185_224_cf[] = {
+		MSG_EM_AVR32_CF,	MSG_EM_STM8_CF,
+		MSG_EM_TILE64_CF,	MSG_EM_TILEPRO_CF,
+		MSG_EM_MICROBLAZE_CF,	MSG_EM_CUDA_CF,
+		MSG_EM_TILEGX_CF,	MSG_EM_CLOUDSHIELD_CF,
+		MSG_EM_COREA_1ST_CF,	MSG_EM_COREA_2ND_CF,
+		MSG_EM_ARC_COMPACT2_CF,	MSG_EM_OPEN8_CF,
+		MSG_EM_RL78_CF,		MSG_EM_VIDEOCORE5_CF,
+		MSG_EM_78KOR_CF,	MSG_EM_56800EX_CF,
+		MSG_EM_BA1_CF,		MSG_EM_BA2_CF,
+		MSG_EM_XCORE_CF,	MSG_EM_MCHP_PIC_CF,
+		MSG_EM_INTEL205_CF,	MSG_EM_INTEL206_CF,
+		MSG_EM_INTEL207_CF,	MSG_EM_INTEL208_CF,
+		MSG_EM_INTEL209_CF,	MSG_EM_KM32_CF,
+		MSG_EM_KMX32_CF,	MSG_EM_KMX16_CF,
+		MSG_EM_KMX8_CF,		MSG_EM_KVARC_CF,
+		MSG_EM_CDP_CF,		MSG_EM_COGE_CF,
+		MSG_EM_COOL_CF,		MSG_EM_NORC_CF,
+		MSG_EM_CSR_KALIMBA_CF,	MSG_EM_Z80_CF,
+		MSG_EM_VISIUM_CF,	MSG_EM_FT32_CF,
+		MSG_EM_MOXIE_CF,	MSG_EM_AMDGPU_CF
+	};
+	static const Msg mach_185_224_nf[] = {
+		MSG_EM_AVR32_NF,	MSG_EM_STM8_NF,
+		MSG_EM_TILE64_NF,	MSG_EM_TILEPRO_NF,
+		MSG_EM_MICROBLAZE_NF,	MSG_EM_CUDA_NF,
+		MSG_EM_TILEGX_NF,	MSG_EM_CLOUDSHIELD_NF,
+		MSG_EM_COREA_1ST_NF,	MSG_EM_COREA_2ND_NF,
+		MSG_EM_ARC_COMPACT2_NF,	MSG_EM_OPEN8_NF,
+		MSG_EM_RL78_NF,		MSG_EM_VIDEOCORE5_NF,
+		MSG_EM_78KOR_NF,	MSG_EM_56800EX_NF,
+		MSG_EM_BA1_NF,		MSG_EM_BA2_NF,
+		MSG_EM_XCORE_NF,	MSG_EM_MCHP_PIC_NF,
+		MSG_EM_INTEL205_NF,	MSG_EM_INTEL206_NF,
+		MSG_EM_INTEL207_NF,	MSG_EM_INTEL208_NF,
+		MSG_EM_INTEL209_NF,	MSG_EM_KM32_NF,
+		MSG_EM_KMX32_NF,	MSG_EM_KMX16_NF,
+		MSG_EM_KMX8_NF,		MSG_EM_KVARC_NF,
+		MSG_EM_CDP_NF,		MSG_EM_COGE_NF,
+		MSG_EM_COOL_NF,		MSG_EM_NORC_NF,
+		MSG_EM_CSR_KALIMBA_NF,	MSG_EM_Z80_NF,
+		MSG_EM_VISIUM_NF,	MSG_EM_FT32_NF,
+		MSG_EM_MOXIE_NF,	MSG_EM_AMDGPU_NF
+	};
+	static const Msg mach_185_224_dmp[] = {
+		MSG_EM_AVR32_CF,	MSG_EM_STM8_CF,
+		MSG_EM_TILE64_CF,	MSG_EM_TILEPRO_CF,
+		MSG_EM_MICROBLAZE_CF,	MSG_EM_CUDA_CF,
+		MSG_EM_TILEGX_CF,	MSG_EM_CLOUDSHIELD_CF,
+		MSG_EM_COREA_1ST_CF,	MSG_EM_COREA_2ND_CF,
+		MSG_EM_ARC_COMPACT2_CF,	MSG_EM_OPEN8_CF,
+		MSG_EM_RL78_CF,		MSG_EM_VIDEOCORE5_CF,
+		MSG_EM_78KOR_CF,	MSG_EM_56800EX_CF,
+		MSG_EM_BA1_CF,		MSG_EM_BA2_CF,
+		MSG_EM_XCORE_CF,	MSG_EM_MCHP_PIC_CF,
+		MSG_EM_INTEL205_CF,	MSG_EM_INTEL206_CF,
+		MSG_EM_INTEL207_CF,	MSG_EM_INTEL208_CF,
+		MSG_EM_INTEL209_CF,	MSG_EM_KM32_CF,
+		MSG_EM_KMX32_CF,	MSG_EM_KMX16_CF,
+		MSG_EM_KMX8_CF,		MSG_EM_KVARC_CF,
+		MSG_EM_CDP_CF,		MSG_EM_COGE_CF,
+		MSG_EM_COOL_CF,		MSG_EM_NORC_CF,
+		MSG_EM_CSR_KALIMBA_CF,	MSG_EM_Z80_CF,
+		MSG_EM_VISIUM_CF,	MSG_EM_FT32_CF,
+		MSG_EM_MOXIE_CF,	MSG_EM_AMDGPU_CF
+	};
+
+	static const conv_ds_msg_t ds_mach_185_224_cf = {
+	    CONV_DS_MSG_INIT(EM_AVR32, mach_185_224_cf) };
+	static const conv_ds_msg_t ds_mach_185_224_nf = {
+	    CONV_DS_MSG_INIT(EM_AVR32, mach_185_224_nf) };
+	static const conv_ds_msg_t ds_mach_185_224_dmp = {
+	    CONV_DS_MSG_INIT(EM_AVR32, mach_185_224_dmp) };
+
+
+	static const Msg mach_243_cf[] = {
+		MSG_EM_RISCV_CF
+	};
+	static const Msg mach_243_nf[] = {
+		MSG_EM_RISCV_NF
+	};
+	static const Msg mach_243_dmp[] = {
+		MSG_EM_RISCV_CF
 	};
-#if	(EM_NUM != (EM_XTENSA + 1))
-#error	"EM_NUM has grown"
-#endif
-	static const conv_ds_msg_t ds_mach_66_94_cf = {
-	    CONV_DS_MSG_INIT(EM_FX66, mach_66_94_cf) };
-	static const conv_ds_msg_t ds_mach_66_94_nf = {
-	    CONV_DS_MSG_INIT(EM_FX66, mach_66_94_nf) };
-	static const conv_ds_msg_t ds_mach_66_94_dmp = {
-	    CONV_DS_MSG_INIT(EM_FX66, mach_66_94_dmp) };
 
+	static const conv_ds_msg_t ds_mach_243_cf = {
+	    CONV_DS_MSG_INIT(EM_RISCV, mach_243_cf) };
+	static const conv_ds_msg_t ds_mach_243_nf = {
+	    CONV_DS_MSG_INIT(EM_RISCV, mach_243_nf) };
+	static const conv_ds_msg_t ds_mach_243_dmp = {
+	    CONV_DS_MSG_INIT(EM_RISCV, mach_243_dmp) };
 
+#if	(EM_NUM != (EM_RISCV + 1))
+#error	"EM_NUM has grown"
+#endif
 	/* Build NULL terminated return arrays for each string style */
 	static const conv_ds_t	*ds_cf[] = {
-		CONV_DS_ADDR(ds_mach_0_11_cf), CONV_DS_ADDR(ds_mach_15_22_cf),
-		CONV_DS_ADDR(ds_mach_36_63_cf), CONV_DS_ADDR(ds_mach_66_94_cf),
+		CONV_DS_ADDR(ds_mach_0_11_cf),
+		CONV_DS_ADDR(ds_mach_15_22_cf),
+		CONV_DS_ADDR(ds_mach_36_63_cf),
+		CONV_DS_ADDR(ds_mach_66_120_cf),
+		CONV_DS_ADDR(ds_mach_131_144_cf),
+		CONV_DS_ADDR(ds_mach_160_181_cf),
+		CONV_DS_ADDR(ds_mach_183_cf),
+		CONV_DS_ADDR(ds_mach_185_224_cf),
+		CONV_DS_ADDR(ds_mach_243_cf),
 		NULL
 	};
 	static const conv_ds_t	*ds_nf[] = {
-		CONV_DS_ADDR(ds_mach_0_11_nf), CONV_DS_ADDR(ds_mach_15_22_nf),
-		CONV_DS_ADDR(ds_mach_36_63_nf), CONV_DS_ADDR(ds_mach_66_94_nf),
+		CONV_DS_ADDR(ds_mach_0_11_nf),
+		CONV_DS_ADDR(ds_mach_15_22_nf),
+		CONV_DS_ADDR(ds_mach_36_63_nf),
+		CONV_DS_ADDR(ds_mach_66_120_nf),
+		CONV_DS_ADDR(ds_mach_131_144_nf),
+		CONV_DS_ADDR(ds_mach_160_181_nf),
+		CONV_DS_ADDR(ds_mach_183_nf),
+		CONV_DS_ADDR(ds_mach_185_224_nf),
+		CONV_DS_ADDR(ds_mach_243_nf),
 		NULL
 	};
 	static const conv_ds_t	*ds_dmp[] = {
-		CONV_DS_ADDR(ds_mach_0_11_dmp), CONV_DS_ADDR(ds_mach_15_22_dmp),
+		CONV_DS_ADDR(ds_mach_0_11_dmp),
+		CONV_DS_ADDR(ds_mach_15_22_dmp),
 		CONV_DS_ADDR(ds_mach_36_63_dmp),
-		CONV_DS_ADDR(ds_mach_66_94_dmp), NULL
+		CONV_DS_ADDR(ds_mach_66_120_dmp),
+		CONV_DS_ADDR(ds_mach_131_144_dmp),
+		CONV_DS_ADDR(ds_mach_160_181_dmp),
+		CONV_DS_ADDR(ds_mach_183_dmp),
+		CONV_DS_ADDR(ds_mach_185_224_dmp),
+		CONV_DS_ADDR(ds_mach_243_dmp),
+		NULL
 	};
 
 
@@ -753,33 +1008,39 @@ ehdr_osabi_strings(Conv_fmt_flags_t fmt_flags)
 	    CONV_DS_MSG_INIT(ELFOSABI_NONE, osabi_0_3_dmp) };
 
 
-	static const Msg osabi_6_15_cf[] = {
+	static const Msg osabi_6_18_cf[] = {
 		MSG_OSABI_SOLARIS_CF,	MSG_OSABI_AIX_CF,
 		MSG_OSABI_IRIX_CF,	MSG_OSABI_FREEBSD_CF,
 		MSG_OSABI_TRU64_CF,	MSG_OSABI_MODESTO_CF,
 		MSG_OSABI_OPENBSD_CF,	MSG_OSABI_OPENVMS_CF,
-		MSG_OSABI_NSK_CF,	MSG_OSABI_AROS_CF
+		MSG_OSABI_NSK_CF,	MSG_OSABI_AROS_CF,
+		MSG_OSABI_FENIXOS_CF,	MSG_OSABI_CLOUDABI_CF,
+		MSG_OSABI_OPENVOS_CF
 	};
-	static const Msg osabi_6_15_nf[] = {
+	static const Msg osabi_6_18_nf[] = {
 		MSG_OSABI_SOLARIS_NF,	MSG_OSABI_AIX_NF,
 		MSG_OSABI_IRIX_NF,	MSG_OSABI_FREEBSD_NF,
 		MSG_OSABI_TRU64_NF,	MSG_OSABI_MODESTO_NF,
 		MSG_OSABI_OPENBSD_NF,	MSG_OSABI_OPENVMS_NF,
-		MSG_OSABI_NSK_NF,	MSG_OSABI_AROS_NF
+		MSG_OSABI_NSK_NF,	MSG_OSABI_AROS_NF,
+		MSG_OSABI_FENIXOS_NF,	MSG_OSABI_CLOUDABI_NF,
+		MSG_OSABI_OPENVOS_NF
 	};
-	static const Msg osabi_6_15_dmp[] = {
+	static const Msg osabi_6_18_dmp[] = {
 		MSG_OSABI_SOLARIS_DMP,	MSG_OSABI_AIX_DMP,
 		MSG_OSABI_IRIX_DMP,	MSG_OSABI_FREEBSD_DMP,
 		MSG_OSABI_TRU64_DMP,	MSG_OSABI_MODESTO_DMP,
 		MSG_OSABI_OPENBSD_DMP,	MSG_OSABI_OPENVMS_DMP,
-		MSG_OSABI_NSK_DMP,	MSG_OSABI_AROS_DMP
+		MSG_OSABI_NSK_DMP,	MSG_OSABI_AROS_DMP,
+		MSG_OSABI_FENIXOS_DMP,	MSG_OSABI_CLOUDABI_DMP,
+		MSG_OSABI_OPENVOS_DMP
 	};
-	static const conv_ds_msg_t ds_osabi_6_15_cf = {
-	    CONV_DS_MSG_INIT(ELFOSABI_SOLARIS, osabi_6_15_cf) };
-	static const conv_ds_msg_t ds_osabi_6_15_nf = {
-	    CONV_DS_MSG_INIT(ELFOSABI_SOLARIS, osabi_6_15_nf) };
-	static const conv_ds_msg_t ds_osabi_6_15_dmp = {
-	    CONV_DS_MSG_INIT(ELFOSABI_SOLARIS, osabi_6_15_dmp) };
+	static const conv_ds_msg_t ds_osabi_6_18_cf = {
+	    CONV_DS_MSG_INIT(ELFOSABI_SOLARIS, osabi_6_18_cf) };
+	static const conv_ds_msg_t ds_osabi_6_18_nf = {
+	    CONV_DS_MSG_INIT(ELFOSABI_SOLARIS, osabi_6_18_nf) };
+	static const conv_ds_msg_t ds_osabi_6_18_dmp = {
+	    CONV_DS_MSG_INIT(ELFOSABI_SOLARIS, osabi_6_18_dmp) };
 
 
 	static const Val_desc osabi_misc_cf[] = {
@@ -806,13 +1067,13 @@ ehdr_osabi_strings(Conv_fmt_flags_t fmt_flags)
 
 	/* Build NULL terminated return arrays for each string style */
 	static const conv_ds_t	*ds_cf[] = {
-		CONV_DS_ADDR(ds_osabi_0_3_cf), CONV_DS_ADDR(ds_osabi_6_15_cf),
+		CONV_DS_ADDR(ds_osabi_0_3_cf), CONV_DS_ADDR(ds_osabi_6_18_cf),
 		CONV_DS_ADDR(ds_osabi_misc_cf), NULL };
 	static const conv_ds_t	*ds_nf[] = {
-		CONV_DS_ADDR(ds_osabi_0_3_nf), CONV_DS_ADDR(ds_osabi_6_15_nf),
+		CONV_DS_ADDR(ds_osabi_0_3_nf), CONV_DS_ADDR(ds_osabi_6_18_nf),
 		CONV_DS_ADDR(ds_osabi_misc_nf), NULL };
 	static const conv_ds_t	*ds_dmp[] = {
-		CONV_DS_ADDR(ds_osabi_0_3_dmp), CONV_DS_ADDR(ds_osabi_6_15_dmp),
+		CONV_DS_ADDR(ds_osabi_0_3_dmp), CONV_DS_ADDR(ds_osabi_6_18_dmp),
 		CONV_DS_ADDR(ds_osabi_misc_dmp), NULL };
 
 	/* Select the strings to use */
diff --git a/usr/src/cmd/sgs/libconv/common/elf.msg b/usr/src/cmd/sgs/libconv/common/elf.msg
index 24325f05cd..95a36a09f4 100644
--- a/usr/src/cmd/sgs/libconv/common/elf.msg
+++ b/usr/src/cmd/sgs/libconv/common/elf.msg
@@ -22,6 +22,7 @@
 #
 # Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
 # Use is subject to license terms.
+# Copyright (c) 2018, Joyent, Inc.
 #
 
 @ MSG_ELFCLASSNONE_CF		"ELFCLASSNONE"			# 0
@@ -224,6 +225,216 @@
 @ MSG_EM_XTENSA_CF		"EM_XTENSA"			# 94
 @ MSG_EM_XTENSA_NF			"xtensa"
 
+@ MSG_EM_VIDEOCORE_CF 		"EM_VIDEOCORE"			# 95
+@ MSG_EM_VIDEOCORE_NF			"videocore"
+@ MSG_EM_TMM_GPP_CF 		"EM_TMM_GPP"			# 96
+@ MSG_EM_TMM_GPP_NF			"tmm_gpp"
+@ MSG_EM_NS32K_CF 		"EM_NS32K"			# 97
+@ MSG_EM_NS32K_NF			"ns32k"
+@ MSG_EM_TPC_CF 		"EM_TPC"			# 98
+@ MSG_EM_TPC_NF				"tpc"
+@ MSG_EM_SNP1K_CF 		"EM_SNP1K"			# 99
+@ MSG_EM_SNP1K_NF			"snp1k"
+@ MSG_EM_ST200_CF 		"EM_ST200"			# 100
+@ MSG_EM_ST200_NF			"st200"
+@ MSG_EM_IP2K_CF 		"EM_IP2K"			# 101
+@ MSG_EM_IP2K_NF			"ip2k"
+@ MSG_EM_MAX_CF 		"EM_MAX"			# 102
+@ MSG_EM_MAX_NF				"max"
+@ MSG_EM_CR_CF 			"EM_CR"				# 103
+@ MSG_EM_CR_NF				"CR"
+@ MSG_EM_F2MC16_CF 		"EM_F2MC16"			# 104
+@ MSG_EM_F2MC16_NF			"f2mc16"
+@ MSG_EM_MSP430_CF 		"EM_MSP430"			# 105
+@ MSG_EM_MSP430_NF			"msp430"
+@ MSG_EM_BLACKFIN_CF 		"EM_BLACKFIN"			# 106
+@ MSG_EM_BLACKFIN_NF			"blackfin"
+@ MSG_EM_SE_C33_CF 		"EM_SE_C33"			# 107
+@ MSG_EM_SE_C33_NF			"se_c33"
+@ MSG_EM_SEP_CF 		"EM_SEP"			# 108
+@ MSG_EM_SEP_NF				"sep"
+@ MSG_EM_ARCA_CF 		"EM_ARCA"			# 109
+@ MSG_EM_ARCA_NF			"arca"
+@ MSG_EM_UNICORE_CF 		"EM_UNICORE"			# 110
+@ MSG_EM_UNICORE_NF			"unicore"
+@ MSG_EM_EXCESS_CF 		"EM_EXCESS"			# 111
+@ MSG_EM_EXCESS_NF			"excess"
+@ MSG_EM_DXP_CF 		"EM_DXP"			# 112
+@ MSG_EM_DXP_NF				"dxp"
+@ MSG_EM_ALTERA_NIOS2_CF 	"EM_ALTERA_NIOS2"		# 113
+@ MSG_EM_ALTERA_NIOS2_NF		"altera_nios2"
+@ MSG_EM_CRX_CF 		"EM_CRX"			# 114
+@ MSG_EM_CRX_NF				"crx"
+@ MSG_EM_XGATE_CF 		"EM_XGATE"			# 115
+@ MSG_EM_XGATE_NF			"xgate"
+@ MSG_EM_C166_CF 		"EM_C166"			# 116
+@ MSG_EM_C166_NF			"c166"
+@ MSG_EM_M16C_CF 		"EM_M16C"			# 117
+@ MSG_EM_M16C_NF			"m16c"
+@ MSG_EM_DSPIC30F_CF 		"EM_DSPIC30F"			# 118
+@ MSG_EM_DSPIC30F_NF			"dspic30f"
+@ MSG_EM_CE_CF 			"EM_CE"				# 119
+@ MSG_EM_CE_NF				"ce"
+@ MSG_EM_M32C_CF		"EM_M32C"			# 120
+@ MSG_EM_M32C_NF			"m32c"
+@ MSG_EM_TSK3000_CF 		"EM_TSK3000"			# 131
+@ MSG_EM_TSK3000_NF			"tsk3000"
+@ MSG_EM_RS08_CF 		"EM_RS08"			# 132
+@ MSG_EM_RS08_NF			"rs08"
+@ MSG_EM_SHARC_CF 		"EM_SHARC"			# 133
+@ MSG_EM_SHARC_NF			"sharc"
+@ MSG_EM_ECOG2_CF 		"EM_ECOG2"			# 134
+@ MSG_EM_ECOG2_NF			"ecog2"
+@ MSG_EM_SCORE7_CF 		"EM_SCORE7"			# 135
+@ MSG_EM_SCORE7_NF			"score7"
+@ MSG_EM_DSP24_CF 		"EM_DSP24"			# 136
+@ MSG_EM_DSP24_NF			"dsp24"
+@ MSG_EM_VIDEOCORE3_CF 		"EM_VIDEOCORE3"			# 137
+@ MSG_EM_VIDEOCORE3_NF			"videocore3"
+@ MSG_EM_LATTICEMICO32_CF 	"EM_LATTICEMICO32"		# 138
+@ MSG_EM_LATTICEMICO32_NF		"latticemico32"
+@ MSG_EM_SE_C17_CF 		"EM_SE_C17"			# 139
+@ MSG_EM_SE_C17_NF			"se_c17"
+@ MSG_EM_TI_C6000_CF 		"EM_TI_C6000"			# 140
+@ MSG_EM_TI_C6000_NF			"ti_c6000"
+@ MSG_EM_TI_C2000_CF 		"EM_TI_C2000"			# 141
+@ MSG_EM_TI_C2000_NF			"ti_c2000"
+@ MSG_EM_TI_C5500_CF 		"EM_TI_C5500"			# 142
+@ MSG_EM_TI_C5500_NF			"ti_c5500"
+@ MSG_EM_TI_ARP32_CF 		"EM_TI_ARP32"			# 143
+@ MSG_EM_TI_ARP32_NF			"ti_arp32"
+@ MSG_EM_TI_PRU_CF 		"EM_TI_PRU"			# 144
+@ MSG_EM_TI_PRU_NF			"ti_pru"
+
+@ MSG_EM_MMDSP_PLUS_CF 		"EM_MMDSP_PLUS"			# 160
+@ MSG_EM_MMDSP_PLUS_NF			"mmdsp_plus"
+@ MSG_EM_CYPRESS_M8C_CF 	"EM_CYPRESS_M8C"		# 161
+@ MSG_EM_CYPRESS_M8C_NF			"cypress_m8c"
+@ MSG_EM_R32C_CF 		"EM_R32C"			# 162
+@ MSG_EM_R32C_NF			"r32c"
+@ MSG_EM_TRIMEDIA_CF 		"EM_TRIMEDIA"			# 163
+@ MSG_EM_TRIMEDIA_NF			"trimedia"
+@ MSG_EM_QDSP6_CF 		"EM_QDSP6"			# 164
+@ MSG_EM_QDSP6_NF			"qdsp6"
+@ MSG_EM_8051_CF 		"EM_8051"			# 165
+@ MSG_EM_8051_NF			"8051"
+@ MSG_EM_STXP7X_CF 		"EM_STXP7X"			# 166
+@ MSG_EM_STXP7X_NF			"stxp7x"
+@ MSG_EM_NDS32_CF 		"EM_NDS32"			# 167
+@ MSG_EM_NDS32_NF			"nds32"
+@ MSG_EM_ECOG1_CF 		"EM_ECOG1"			# 168
+@ MSG_EM_ECOG1_NF			"ecog1"
+@ MSG_EM_MAXQ30_CF 		"EM_MAXQ30"			# 169
+@ MSG_EM_MAXQ30_NF			"maxq30"
+@ MSG_EM_XIMO16_CF 		"EM_XIMO16"			# 170
+@ MSG_EM_XIMO16_NF			"ximo16"
+@ MSG_EM_MANIK_CF 		"EM_MANIK"			# 171
+@ MSG_EM_MANIK_NF			"manik"
+@ MSG_EM_CRAYNV2_CF 		"EM_CRAYNV2"			# 172
+@ MSG_EM_CRAYNV2_NF			"craynv2"
+@ MSG_EM_RX_CF 			"EM_RX"				# 173
+@ MSG_EM_RX_NF				"rx"
+@ MSG_EM_METAG_CF 		"EM_METAG"			# 174
+@ MSG_EM_METAG_NF			"metag"
+@ MSG_EM_MCST_ELBRUS_CF 	"EM_MCST_ELBRUS"		# 175
+@ MSG_EM_MCST_ELBRUS_NF			"mcst_elbrus"
+@ MSG_EM_ECOG16_CF 		"EM_ECOG16"			# 176
+@ MSG_EM_ECOG16_NF			"ecog16"
+@ MSG_EM_CR16_CF 		"EM_CR16"			# 177
+@ MSG_EM_CR16_NF			"cr16"
+@ MSG_EM_ETPU_CF 		"EM_ETPU"			# 178
+@ MSG_EM_ETPU_NF			"etpu"
+@ MSG_EM_SLE9X_CF 		"EM_SLE9X"			# 179
+@ MSG_EM_SLE9X_NF			"sle9x"
+@ MSG_EM_L10M_CF 		"EM_L10M"			# 180
+@ MSG_EM_L10M_NF			"l10m"
+@ MSG_EM_K10M_CF 		"EM_K10M"			# 181
+@ MSG_EM_K10M_NF			"k10m"
+@ MSG_EM_AARCH64_CF 		"EM_AARCH64"			# 183
+@ MSG_EM_AARCH64_NF			"aarch64"
+@ MSG_EM_AVR32_CF 		"EM_AVR32"			# 185
+@ MSG_EM_AVR32_NF			"avr32"
+@ MSG_EM_STM8_CF 		"EM_STM8"			# 186
+@ MSG_EM_STM8_NF			"stm8"
+@ MSG_EM_TILE64_CF 		"EM_TILE64"			# 187
+@ MSG_EM_TILE64_NF			"tile64"
+@ MSG_EM_TILEPRO_CF 		"EM_TILEPRO"			# 188
+@ MSG_EM_TILEPRO_NF			"tilepro"
+@ MSG_EM_MICROBLAZE_CF 		"EM_MICROBLAZE"			# 189
+@ MSG_EM_MICROBLAZE_NF			"microblaze"
+@ MSG_EM_CUDA_CF 		"EM_CUDA"			# 190
+@ MSG_EM_CUDA_NF			"cuda"
+@ MSG_EM_TILEGX_CF 		"EM_TILEGX"			# 191
+@ MSG_EM_TILEGX_NF			"tilegx"
+@ MSG_EM_CLOUDSHIELD_CF 	"EM_CLOUDSHIELD"		# 192
+@ MSG_EM_CLOUDSHIELD_NF			"cloudshield"
+@ MSG_EM_COREA_1ST_CF 		"EM_COREA_1ST"			# 193
+@ MSG_EM_COREA_1ST_NF			"corea_1st"
+@ MSG_EM_COREA_2ND_CF 		"EM_COREA_2ND"			# 194
+@ MSG_EM_COREA_2ND_NF			"corea_2nd"
+@ MSG_EM_ARC_COMPACT2_CF 	"EM_ARC_COMPACT2"		# 195
+@ MSG_EM_ARC_COMPACT2_NF		"arc_compact2"
+@ MSG_EM_OPEN8_CF 		"EM_OPEN8"			# 196
+@ MSG_EM_OPEN8_NF			"open8"
+@ MSG_EM_RL78_CF 		"EM_RL78"			# 197
+@ MSG_EM_RL78_NF			"rl78"
+@ MSG_EM_VIDEOCORE5_CF 		"EM_VIDEOCORE5"			# 198
+@ MSG_EM_VIDEOCORE5_NF			"videocore5"
+@ MSG_EM_78KOR_CF 		"EM_78KOR"			# 199
+@ MSG_EM_78KOR_NF			"78kor"
+@ MSG_EM_56800EX_CF 		"EM_56800EX"			# 200
+@ MSG_EM_56800EX_NF			"56800ex"
+@ MSG_EM_BA1_CF 		"EM_BA1"			# 201
+@ MSG_EM_BA1_NF				"ba1"
+@ MSG_EM_BA2_CF 		"EM_BA2"			# 202
+@ MSG_EM_BA2_NF				"ba2"
+@ MSG_EM_XCORE_CF 		"EM_XCORE"			# 203
+@ MSG_EM_XCORE_NF			"xcore"
+@ MSG_EM_MCHP_PIC_CF 		"EM_MCHP_PIC"			# 204
+@ MSG_EM_MCHP_PIC_NF			"mchp_pic"
+@ MSG_EM_INTEL205_CF 		"EM_INTEL205"			# 205
+@ MSG_EM_INTEL205_NF			"intel205"
+@ MSG_EM_INTEL206_CF 		"EM_INTEL206"			# 206
+@ MSG_EM_INTEL206_NF			"intel206"
+@ MSG_EM_INTEL207_CF 		"EM_INTEL207"			# 207
+@ MSG_EM_INTEL207_NF			"intel207"
+@ MSG_EM_INTEL208_CF 		"EM_INTEL208"			# 208
+@ MSG_EM_INTEL208_NF			"intel208"
+@ MSG_EM_INTEL209_CF 		"EM_INTEL209"			# 209
+@ MSG_EM_INTEL209_NF			"intel209"
+@ MSG_EM_KM32_CF 		"EM_KM32"			# 210
+@ MSG_EM_KM32_NF			"km32"
+@ MSG_EM_KMX32_CF 		"EM_KMX32"			# 211
+@ MSG_EM_KMX32_NF			"kmx32"
+@ MSG_EM_KMX16_CF 		"EM_KMX16"			# 212
+@ MSG_EM_KMX16_NF			"kmx16"
+@ MSG_EM_KMX8_CF 		"EM_KMX8"			# 213
+@ MSG_EM_KMX8_NF			"kmx8"
+@ MSG_EM_KVARC_CF 		"EM_KVARC"			# 214
+@ MSG_EM_KVARC_NF			"kvarc"
+@ MSG_EM_CDP_CF 		"EM_CDP"			# 215
+@ MSG_EM_CDP_NF				"cdp"
+@ MSG_EM_COGE_CF 		"EM_COGE"			# 216
+@ MSG_EM_COGE_NF			"coge"
+@ MSG_EM_COOL_CF 		"EM_COOL"			# 217
+@ MSG_EM_COOL_NF			"cool"
+@ MSG_EM_NORC_CF 		"EM_NORC"			# 218
+@ MSG_EM_NORC_NF			"norc"
+@ MSG_EM_CSR_KALIMBA_CF 	"EM_CSR_KALIMBA"		# 219
+@ MSG_EM_CSR_KALIMBA_NF			"csr_kalimba"
+@ MSG_EM_Z80_CF 		"EM_Z80"			# 220
+@ MSG_EM_Z80_NF				"z80"
+@ MSG_EM_VISIUM_CF 		"EM_VISIUM"			# 221
+@ MSG_EM_VISIUM_NF			"visium"
+@ MSG_EM_FT32_CF 		"EM_FT32"			# 222
+@ MSG_EM_FT32_NF			"ft32"
+@ MSG_EM_MOXIE_CF 		"EM_MOXIE"			# 223
+@ MSG_EM_MOXIE_NF			"moxie"
+@ MSG_EM_AMDGPU_CF 		"EM_AMDGPU"			# 224
+@ MSG_EM_AMDGPU_NF			"amdgpu"
+
+@ MSG_EM_RISCV_CF 		"EM_RISCV"			# 243
+@ MSG_EM_RISCV_NF			"riscv"
 
 @ MSG_EI_MAG0_CF		"EI_MAG0"			# 0
 @ MSG_EI_MAG0_NF			"mag0"
@@ -331,6 +542,15 @@
 @ MSG_OSABI_AROS_CF		"ELFOSABI_AROS"			#15
 @ MSG_OSABI_AROS_NF			"aros"
 @ MSG_OSABI_AROS_DMP			"Amiga Research OS"
+@ MSG_OSABI_FENIXOS_CF		"ELFOSABI_FENIXOS"		#16
+@ MSG_OSABI_FENIXOS_NF			"fenixos"
+@ MSG_OSABI_FENIXOS_DMP			"FenixOS"
+@ MSG_OSABI_CLOUDABI_CF		"ELFOSABI_CLOUDABI"		#17
+@ MSG_OSABI_CLOUDABI_NF			"cloudabi"
+@ MSG_OSABI_CLOUDABI_DMP		"CloudABI"
+@ MSG_OSABI_OPENVOS_CF		"ELFOASBI_OPENVOS"		#18
+@ MSG_OSABI_OPENVOS_NF			"openvos"
+@ MSG_OSABI_OPENVOS_DMP			"OpenVOS"
 @ MSG_OSABI_ARM_CF		"ELFOSABI_ARM"			#97
 @ MSG_OSABI_ARM_NF			"arm"
 @ MSG_OSABI_ARM_DMP			"ARM"
diff --git a/usr/src/uts/common/sys/elf.h b/usr/src/uts/common/sys/elf.h
index ec9a0f160a..0dd4f2d17e 100644
--- a/usr/src/uts/common/sys/elf.h
+++ b/usr/src/uts/common/sys/elf.h
@@ -20,7 +20,7 @@
  */
 /*
  * Copyright 2012 DEY Storage Systems, Inc.  All rights reserved.
- * Copyright (c) 2015, Joyent, Inc. All rights reserved.
+ * Copyright (c) 2018, Joyent, Inc.
  */
 /*
  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
@@ -148,30 +148,30 @@ typedef struct {
 #define	ET_LOPROC	0xff00		/* processor specific range */
 #define	ET_HIPROC	0xffff
 
-#define	EM_NONE		0		/* e_machine */
-#define	EM_M32		1		/* AT&T WE 32100 */
-#define	EM_SPARC	2		/* Sun SPARC */
-#define	EM_386		3		/* Intel 80386 */
-#define	EM_68K		4		/* Motorola 68000 */
-#define	EM_88K		5		/* Motorola 88000 */
-#define	EM_486		6		/* Intel 80486 */
-#define	EM_860		7		/* Intel i860 */
-#define	EM_MIPS		8		/* MIPS RS3000 Big-Endian */
-#define	EM_S370		9		/* IBM System/370 Processor */
-#define	EM_MIPS_RS3_LE	10		/* MIPS RS3000 Little-Endian */
-#define	EM_RS6000	11		/* RS6000 */
+#define	EM_NONE		0	/* e_machine */
+#define	EM_M32		1	/* AT&T WE 32100 */
+#define	EM_SPARC	2	/* Sun SPARC */
+#define	EM_386		3	/* Intel 80386 */
+#define	EM_68K		4	/* Motorola 68000 */
+#define	EM_88K		5	/* Motorola 88000 */
+#define	EM_486		6	/* Intel 80486 */
+#define	EM_860		7	/* Intel i860 */
+#define	EM_MIPS		8	/* MIPS RS3000 Big-Endian */
+#define	EM_S370		9	/* IBM System/370 Processor */
+#define	EM_MIPS_RS3_LE	10	/* MIPS RS3000 Little-Endian */
+#define	EM_RS6000	11	/* RS6000 */
 #define	EM_UNKNOWN12	12
 #define	EM_UNKNOWN13	13
 #define	EM_UNKNOWN14	14
-#define	EM_PA_RISC	15		/* PA-RISC */
+#define	EM_PA_RISC	15	/* PA-RISC */
 #define	EM_PARISC	EM_PA_RISC	/* Alias: GNU compatibility */
-#define	EM_nCUBE	16		/* nCUBE */
-#define	EM_VPP500	17		/* Fujitsu VPP500 */
-#define	EM_SPARC32PLUS	18		/* Sun SPARC 32+ */
-#define	EM_960		19		/* Intel 80960 */
-#define	EM_PPC		20		/* PowerPC */
-#define	EM_PPC64	21		/* 64-bit PowerPC */
-#define	EM_S390		22		/* IBM System/390 Processor */
+#define	EM_nCUBE	16	/* nCUBE */
+#define	EM_VPP500	17	/* Fujitsu VPP500 */
+#define	EM_SPARC32PLUS	18	/* Sun SPARC 32+ */
+#define	EM_960		19	/* Intel 80960 */
+#define	EM_PPC		20	/* PowerPC */
+#define	EM_PPC64	21	/* 64-bit PowerPC */
+#define	EM_S390		22	/* IBM System/390 Processor */
 #define	EM_UNKNOWN22	EM_S390		/* Alias: Older published name */
 #define	EM_UNKNOWN23	23
 #define	EM_UNKNOWN24	24
@@ -186,78 +186,226 @@ typedef struct {
 #define	EM_UNKNOWN33	33
 #define	EM_UNKNOWN34	34
 #define	EM_UNKNOWN35	35
-#define	EM_V800		36		/* NEX V800 */
-#define	EM_FR20		37		/* Fujitsu FR20 */
-#define	EM_RH32		38		/* TRW RH-32 */
-#define	EM_RCE		39		/* Motorola RCE */
-#define	EM_ARM		40		/* Advanced RISC Marchines ARM */
-#define	EM_ALPHA	41		/* Digital Alpha */
-#define	EM_SH		42		/* Hitachi SH */
-#define	EM_SPARCV9	43		/* Sun SPARC V9 (64-bit) */
-#define	EM_TRICORE	44		/* Siemens Tricore embedded processor */
-#define	EM_ARC		45		/* Argonaut RISC Core, */
-					/*	Argonaut Technologies Inc. */
-#define	EM_H8_300	46		/* Hitachi H8/300 */
-#define	EM_H8_300H	47		/* Hitachi H8/300H */
-#define	EM_H8S		48		/* Hitachi H8S */
-#define	EM_H8_500	49		/* Hitachi H8/500 */
-#define	EM_IA_64	50		/* Intel IA64 */
-#define	EM_MIPS_X	51		/* Stanford MIPS-X */
-#define	EM_COLDFIRE	52		/* Motorola ColdFire */
-#define	EM_68HC12	53		/* Motorola M68HC12 */
-#define	EM_MMA		54		/* Fujitsu MMA Mulimedia Accelerator */
-#define	EM_PCP		55		/* Siemens PCP */
-#define	EM_NCPU		56		/* Sony nCPU embedded RISC processor */
-#define	EM_NDR1		57		/* Denso NDR1 microprocessor */
-#define	EM_STARCORE	58		/* Motorola Star*Core processor */
-#define	EM_ME16		59		/* Toyota ME16 processor */
-#define	EM_ST100	60		/* STMicroelectronics ST100 processor */
-#define	EM_TINYJ	61		/* Advanced Logic Corp. TinyJ */
-					/*	embedded processor family */
-#define	EM_AMD64	62		/* AMDs x86-64 architecture */
+#define	EM_V800		36	/* NEX V800 */
+#define	EM_FR20		37	/* Fujitsu FR20 */
+#define	EM_RH32		38	/* TRW RH-32 */
+#define	EM_RCE		39	/* Motorola RCE */
+#define	EM_ARM		40	/* Advanced RISC Marchines ARM */
+#define	EM_ALPHA	41	/* Digital Alpha */
+#define	EM_SH		42	/* Hitachi SH */
+#define	EM_SPARCV9	43	/* Sun SPARC V9 (64-bit) */
+#define	EM_TRICORE	44	/* Siemens Tricore embedded processor */
+#define	EM_ARC		45	/* Argonaut RISC Core, */
+				/*	Argonaut Technologies Inc. */
+#define	EM_H8_300	46	/* Hitachi H8/300 */
+#define	EM_H8_300H	47	/* Hitachi H8/300H */
+#define	EM_H8S		48	/* Hitachi H8S */
+#define	EM_H8_500	49	/* Hitachi H8/500 */
+#define	EM_IA_64	50	/* Intel IA64 */
+#define	EM_MIPS_X	51	/* Stanford MIPS-X */
+#define	EM_COLDFIRE	52	/* Motorola ColdFire */
+#define	EM_68HC12	53	/* Motorola M68HC12 */
+#define	EM_MMA		54	/* Fujitsu MMA Mulimedia Accelerator */
+#define	EM_PCP		55	/* Siemens PCP */
+#define	EM_NCPU		56	/* Sony nCPU embedded RISC processor */
+#define	EM_NDR1		57	/* Denso NDR1 microprocessor */
+#define	EM_STARCORE	58	/* Motorola Star*Core processor */
+#define	EM_ME16		59	/* Toyota ME16 processor */
+#define	EM_ST100	60	/* STMicroelectronics ST100 processor */
+#define	EM_TINYJ	61	/* Advanced Logic Corp. TinyJ */
+				/*	embedded processor family */
+#define	EM_AMD64	62	/* AMDs x86-64 architecture */
 #define	EM_X86_64	EM_AMD64	/* (compatibility) */
 
-#define	EM_PDSP		63		/* Sony DSP Processor */
+#define	EM_PDSP		63	/* Sony DSP Processor */
 #define	EM_UNKNOWN64	64
 #define	EM_UNKNOWN65	65
-#define	EM_FX66		66		/* Siemens FX66 microcontroller */
-#define	EM_ST9PLUS	67		/* STMicroelectronics ST9+8/16 bit */
-					/*	microcontroller */
-#define	EM_ST7		68		/* STMicroelectronics ST7 8-bit */
-					/*	microcontroller */
-#define	EM_68HC16	69		/* Motorola MC68HC16 Microcontroller */
-#define	EM_68HC11	70		/* Motorola MC68HC11 Microcontroller */
-#define	EM_68HC08	71		/* Motorola MC68HC08 Microcontroller */
-#define	EM_68HC05	72		/* Motorola MC68HC05 Microcontroller */
-#define	EM_SVX		73		/* Silicon Graphics SVx */
-#define	EM_ST19		74		/* STMicroelectronics ST19 8-bit */
-					/*	microcontroller */
-#define	EM_VAX		75		/* Digital VAX */
-#define	EM_CRIS		76		/* Axis Communications 32-bit */
-					/*	embedded processor */
-#define	EM_JAVELIN	77		/* Infineon Technologies 32-bit */
-					/*	embedded processor */
-#define	EM_FIREPATH	78		/* Element 14 64-bit DSP Processor */
-#define	EM_ZSP		79		/* LSI Logic 16-bit DSP Processor */
-#define	EM_MMIX		80		/* Donald Knuth's educational */
-					/*	64-bit processor */
-#define	EM_HUANY	81		/* Harvard University */
-					/*	machine-independent */
-					/*	object files */
-#define	EM_PRISM	82		/* SiTera Prism */
-#define	EM_AVR		83		/* Atmel AVR 8-bit microcontroller */
-#define	EM_FR30		84		/* Fujitsu FR30 */
-#define	EM_D10V		85		/* Mitsubishi D10V */
-#define	EM_D30V		86		/* Mitsubishi D30V */
-#define	EM_V850		87		/* NEC v850 */
-#define	EM_M32R		88		/* Mitsubishi M32R */
-#define	EM_MN10300	89		/* Matsushita MN10300 */
-#define	EM_MN10200	90		/* Matsushita MN10200 */
-#define	EM_PJ		91		/* picoJava */
-#define	EM_OPENRISC	92		/* OpenRISC 32-bit embedded processor */
-#define	EM_ARC_A5	93		/* ARC Cores Tangent-A5 */
-#define	EM_XTENSA	94		/* Tensilica Xtensa architecture */
-#define	EM_NUM		95
+#define	EM_FX66		66	/* Siemens FX66 microcontroller */
+#define	EM_ST9PLUS	67	/* STMicroelectronics ST9+8/16 bit */
+				/*	microcontroller */
+#define	EM_ST7		68	/* STMicroelectronics ST7 8-bit */
+				/*	microcontroller */
+#define	EM_68HC16	69	/* Motorola MC68HC16 Microcontroller */
+#define	EM_68HC11	70	/* Motorola MC68HC11 Microcontroller */
+#define	EM_68HC08	71	/* Motorola MC68HC08 Microcontroller */
+#define	EM_68HC05	72	/* Motorola MC68HC05 Microcontroller */
+#define	EM_SVX		73	/* Silicon Graphics SVx */
+#define	EM_ST19		74	/* STMicroelectronics ST19 8-bit */
+				/*	microcontroller */
+#define	EM_VAX		75	/* Digital VAX */
+#define	EM_CRIS		76	/* Axis Communications 32-bit */
+				/*	embedded processor */
+#define	EM_JAVELIN	77	/* Infineon Technologies 32-bit */
+				/*	embedded processor */
+#define	EM_FIREPATH	78	/* Element 14 64-bit DSP Processor */
+#define	EM_ZSP		79	/* LSI Logic 16-bit DSP Processor */
+#define	EM_MMIX		80	/* Donald Knuth's educational */
+				/*	64-bit processor */
+#define	EM_HUANY	81	/* Harvard University */
+				/*	machine-independent */
+				/*	object files */
+#define	EM_PRISM	82	/* SiTera Prism */
+#define	EM_AVR		83	/* Atmel AVR 8-bit microcontroller */
+#define	EM_FR30		84	/* Fujitsu FR30 */
+#define	EM_D10V		85	/* Mitsubishi D10V */
+#define	EM_D30V		86	/* Mitsubishi D30V */
+#define	EM_V850		87	/* NEC v850 */
+#define	EM_M32R		88	/* Mitsubishi M32R */
+#define	EM_MN10300	89	/* Matsushita MN10300 */
+#define	EM_MN10200	90	/* Matsushita MN10200 */
+#define	EM_PJ		91	/* picoJava */
+#define	EM_OPENRISC	92	/* OpenRISC 32-bit embedded processor */
+#define	EM_ARC_A5	93	/* ARC Cores Tangent-A5 */
+#define	EM_XTENSA	94	/* Tensilica Xtensa architecture */
+
+#define	EM_VIDEOCORE	95	/* Alphamosaic VideoCore processor */
+#define	EM_TMM_GPP	96	/* Thompson Multimedia General Purpose */
+				/* Processor */
+#define	EM_NS32K	97	/* National Semiconductor 32000 series */
+#define	EM_TPC		98	/* Tenor Network TPC processor */
+#define	EM_SNP1K	99	/* Trebia SNP 1000 processor */
+#define	EM_ST200	100	/* STMicroelectronics (www.st.com) ST200 */
+				/* microcontroller */
+#define	EM_IP2K		101	/* Ubicom IP2xxx microcontroller family */
+#define	EM_MAX		102	/* MAX Processor */
+#define	EM_CR		103	/* National Semiconductor CompactRISC */
+				/* microprocessor */
+#define	EM_F2MC16	104	/* Fujitsu F2MC16 */
+#define	EM_MSP430	105	/* Texas Instruments embedded microcontroller */
+				/* msp430 */
+#define	EM_BLACKFIN	106	/* Analog Devices Blackfin (DSP) processor */
+#define	EM_SE_C33	107	/* S1C33 Family of Seiko Epson processors */
+#define	EM_SEP		108	/* Sharp embedded microprocessor */
+#define	EM_ARCA		109	/* Arca RISC Microprocessor */
+#define	EM_UNICORE	110	/* Microprocessor series from PKU-Unity Ltd. */
+				/* and MPRC of Peking University */
+#define	EM_EXCESS	111	/* eXcess: 16/32/64-bit configurable embedded */
+				/* CPU */
+#define	EM_DXP		112	/* Icera Semiconductor Inc. Deep Execution */
+				/* Processor */
+#define	EM_ALTERA_NIOS2	113	/* Altera Nios II soft-core processor */
+#define	EM_CRX		114	/* National Semiconductor CompactRISC CRX */
+				/* microprocessor */
+#define	EM_XGATE	115	/* Motorola XGATE embedded processor */
+#define	EM_C166		116	/* Infineon C16x/XC16x processor */
+#define	EM_M16C		117	/* Renesas M16C series microprocessors */
+#define	EM_DSPIC30F	118	/* Microchip Technology dsPIC30F Digital */
+				/* Signal Controller */
+#define	EM_CE		119	/* Freescale Communication Engine RISC core */
+#define	EM_M32C		120	/* Renesas M32C series microprocessors */
+
+#define	EM_TSK3000	131	/* Altium TSK3000 core */
+#define	EM_RS08		132	/* Freescale RS08 embedded processor */
+#define	EM_SHARC	133	/* Analog Devices SHARC family of 32-bit DSP */
+				/* processors */
+#define	EM_ECOG2	134	/* Cyan Technology eCOG2 microprocessor */
+#define	EM_SCORE7	135	/* Sunplus S+core7 RISC processor */
+#define	EM_DSP24	136	/* New Japan Radio (NJR) 24-bit DSP Processor */
+#define	EM_VIDEOCORE3	137	/* Broadcom VideoCore III processor */
+#define	EM_LATTICEMICO32	138	/* RISC processor for Lattice FPGA */
+					/* architecture */
+#define	EM_SE_C17	139	/* Seiko Epson C17 family */
+#define	EM_TI_C6000	140	/* The Texas Instruments TMS320C6000 DSP */
+				/* family */
+#define	EM_TI_C2000	141	/* The Texas Instruments TMS320C2000 DSP */
+				/* family */
+#define	EM_TI_C5500	142	/* The Texas Instruments TMS320C55x DSP */
+				/* family */
+#define	EM_TI_ARP32	143	/* Texas Instruments Application Specific */
+				/* RISC Processor, 32bit fetch */
+#define	EM_TI_PRU	144	/* Texas Instruments Programmable Realtime */
+				/* Unit */
+
+#define	EM_MMDSP_PLUS	160	/* STMicroelectronics 64bit VLIW Data Signal */
+				/* Processor */
+#define	EM_CYPRESS_M8C	161	/* Cypress M8C microprocessor */
+#define	EM_R32C		162	/* Renesas R32C series microprocessors */
+#define	EM_TRIMEDIA	163	/* NXP Semiconductors TriMedia architecture */
+				/* family */
+#define	EM_QDSP6	164	/* QUALCOMM DSP6 Processor */
+#define	EM_8051		165	/* Intel 8051 and variants */
+#define	EM_STXP7X	166	/* STMicroelectronics STxP7x family of */
+				/* configurable and extensible RISC */
+				/* processors */
+#define	EM_NDS32	167	/* Andes Technology compact code size */
+				/* embedded RISC processor family */
+#define	EM_ECOG1	168	/* Cyan Technology eCOG1X family */
+#define	EM_ECOG1X	EM_EC0G1X	/* Cyan Technology eCOG1X family */
+#define	EM_MAXQ30	169	/* Dallas Semiconductor MAXQ30 Core */
+				/* Micro-controllers */
+#define	EM_XIMO16	170	/* New Japan Radio (NJR) 16-bit DSP Processor */
+#define	EM_MANIK	171	/* M2000 Reconfigurable RISC Microprocessor */
+#define	EM_CRAYNV2	172	/* Cray Inc. NV2 vector architecture */
+#define	EM_RX		173	/* Renesas RX family */
+#define	EM_METAG	174	/* Imagination Technologies META processor */
+				/* architecture */
+#define	EM_MCST_ELBRUS	175	/* MCST Elbrus general purpose hardware */
+				/* architecture */
+#define	EM_ECOG16	176	/* Cyan Technology eCOG16 family */
+#define	EM_CR16		177	/* National Semiconductor CompactRISC */
+				/* CR16 16-bit microprocessor */
+#define	EM_ETPU		178	/* Freescale Extended Time Processing Unit */
+#define	EM_SLE9X	179	/* Infineon Technologies SLE9X core */
+#define	EM_L10M		180	/* Intel L10M */
+#define	EM_K10M		181	/* Intel K10M */
+
+#define	EM_AARCH64	183	/* ARM 64-bit architecture (AARCH64) */
+
+#define	EM_AVR32	185	/* Atmel Corporation 32-bit microprocessor */
+				/* family */
+#define	EM_STM8		186	/* STMicroeletronics STM8 8-bit */
+				/* microcontroller */
+#define	EM_TILE64	187	/* Tilera TILE64 multicore architecture */
+				/* family */
+#define	EM_TILEPRO	188	/* Tilera TILEPro multicore architecture */
+				/* family */
+#define	EM_MICROBLAZE	189	/* Xilinx MicroBlaze 32-bit RISC soft */
+				/* processor core */
+#define	EM_CUDA		190	/* NVIDIA CUDA architecture */
+#define	EM_TILEGX	191	/* Tilera TILE-Gx multicore architecture */
+				/* family */
+#define	EM_CLOUDSHIELD	192	/* CloudShield architecture family */
+#define	EM_COREA_1ST	193	/* KIPO-KAIST Core-A 1st generation processor */
+				/* family */
+#define	EM_COREA_2ND	194	/* KIPO-KAIST Core-A 2nd generation processor */
+				/* family */
+#define	EM_ARC_COMPACT2	195	/* Synopsys ARCompact V2 */
+#define	EM_OPEN8	196	/* Open8 8-bit RISC soft processor core */
+#define	EM_RL78		197	/* Renesas RL78 family */
+#define	EM_VIDEOCORE5	198	/* Broadcom VideoCore V processor */
+#define	EM_78KOR	199	/* Renesas 78KOR family */
+#define	EM_56800EX	200	/* Freescale 56800EX Digital Signal */
+				/* Controller (DSC) */
+#define	EM_BA1		201	/* Beyond BA1 CPU architecture */
+#define	EM_BA2		202	/* Beyond BA2 CPU architecture */
+#define	EM_XCORE	203	/* XMOS xCORE processor family */
+#define	EM_MCHP_PIC	204	/* Microchip 8-bit PIC(r) family */
+#define	EM_INTEL205	205	/* Reserved by Intel */
+#define	EM_INTEL206	206	/* Reserved by Intel */
+#define	EM_INTEL207	207	/* Reserved by Intel */
+#define	EM_INTEL208	208	/* Reserved by Intel */
+#define	EM_INTEL209	209	/* Reserved by Intel */
+#define	EM_KM32		210	/* KM211 KM32 32-bit processor */
+#define	EM_KMX32	211	/* KM211 KMX32 32-bit processor */
+#define	EM_KMX16	212	/* KM211 KMX16 16-bit processor */
+#define	EM_KMX8		213	/* KM211 KMX8 8-bit processor */
+#define	EM_KVARC	214	/* KM211 KVARC processor */
+#define	EM_CDP		215	/* Paneve CDP architecture family */
+#define	EM_COGE		216	/* Cognitive Smart Memory Processor */
+#define	EM_COOL		217	/* Bluechip Systems CoolEngine */
+#define	EM_NORC		218	/* Nanoradio Optimized RISC */
+#define	EM_CSR_KALIMBA	219	/* CSR Kalimba architecture family */
+#define	EM_Z80		220	/* Zilog Z80 */
+#define	EM_VISIUM	221	/* Controls and Data Services VISIUMcore */
+				/* processor */
+#define	EM_FT32		222	/* FTDI Chip FT32 high performance 32-bit */
+				/* RISC architecture */
+#define	EM_MOXIE	223	/* Moxie processor family */
+#define	EM_AMDGPU	224	/* AMD GPU architecture */
+
+#define	EM_RISCV	243	/* RISC-V */
+
+#define	EM_NUM		244
 
 #define	EV_NONE		0		/* e_version, EI_VERSION */
 #define	EV_CURRENT	1
@@ -281,6 +429,10 @@ typedef struct {
 #define	ELFOSABI_OPENVMS	13	/* Open VMS */
 #define	ELFOSABI_NSK		14	/* Hewlett-Packard Non-Stop Kernel */
 #define	ELFOSABI_AROS		15	/* Amiga Research OS */
+#define	ELFOSABI_FENIXOS 	16 	/* The FenixOS highly scalable */
+					/* multi-core OS */
+#define	ELFOSABI_CLOUDABI 	17 	/* Nuxi CloudABI */
+#define	ELFOSABI_OPENVOS 	18 	/* Stratus Technologies OpenVOS */
 #define	ELFOSABI_ARM		97	/* ARM */
 #define	ELFOSABI_STANDALONE	255	/* standalone (embedded) application */