9827 clean up some space-tab sequences

Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Garrett D'Amore <garrett@damore.org>

9 files changed, 69 insertions, 69 deletions

diff --git a/usr/src/uts/common/sys/pci.h b/usr/src/uts/common/sys/pci.h
index 364fd0f37e..f5f0b23764 100644
--- a/usr/src/uts/common/sys/pci.h
+++ b/usr/src/uts/common/sys/pci.h
@@ -488,23 +488,23 @@ extern "C" {
 /*
  * Programming interfaces for class 0xC / subclass 0x0 (Firewire)
  */
-#define	PCI_SERIAL_FIRE_WIRE  		0x00	/* IEEE 1394 (Firewire) */
-#define	PCI_SERIAL_FIRE_1394_HCI 	0x10	/* 1394 OpenHCI Host Cntrlr */
+#define	PCI_SERIAL_FIRE_WIRE		0x00	/* IEEE 1394 (Firewire) */
+#define	PCI_SERIAL_FIRE_1394_HCI	0x10	/* 1394 OpenHCI Host Cntrlr */
 
 /*
  * Programming interfaces for class 0xC / subclass 0x3 (USB controller)
  */
-#define	PCI_SERIAL_USB_IF_UHCI 		0x00	/* UHCI Compliant */
-#define	PCI_SERIAL_USB_IF_OHCI 		0x10	/* OHCI Compliant */
-#define	PCI_SERIAL_USB_IF_EHCI 		0x20	/* EHCI Compliant */
-#define	PCI_SERIAL_USB_IF_GENERIC 	0x80	/* no specific HCD */
-#define	PCI_SERIAL_USB_IF_DEVICE 	0xFE	/* not a HCD */
+#define	PCI_SERIAL_USB_IF_UHCI		0x00	/* UHCI Compliant */
+#define	PCI_SERIAL_USB_IF_OHCI		0x10	/* OHCI Compliant */
+#define	PCI_SERIAL_USB_IF_EHCI		0x20	/* EHCI Compliant */
+#define	PCI_SERIAL_USB_IF_GENERIC	0x80	/* no specific HCD */
+#define	PCI_SERIAL_USB_IF_DEVICE	0xFE	/* not a HCD */
 
 /*
  * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller)
  */
-#define	PCI_SERIAL_IPMI_IF_SMIC 	0x0	/* SMIC Interface */
-#define	PCI_SERIAL_IPMI_IF_KBD 		0x1	/* Keyboard Ctrl Style Intfc */
+#define	PCI_SERIAL_IPMI_IF_SMIC		0x0	/* SMIC Interface */
+#define	PCI_SERIAL_IPMI_IF_KBD		0x1	/* Keyboard Ctrl Style Intfc */
 #define	PCI_SERIAL_IPMI_IF_BTI		0x2	/* Block Transfer Interface */
 
 /*
@@ -522,8 +522,8 @@ extern "C" {
 /*
  * Programming interfaces for class 0xD / subclass 0x1 (Consumer IR controller)
  */
-#define	PCI_WIRELESS_IR_CONSUMER 	0x00	/* Consumer IR Controller */
-#define	PCI_WIRELESS_IR_UWB_RC 		0x10	/* UWB Radio Controller */
+#define	PCI_WIRELESS_IR_CONSUMER	0x00	/* Consumer IR Controller */
+#define	PCI_WIRELESS_IR_UWB_RC		0x10	/* UWB Radio Controller */
 
 /*
  * PCI Sub-class codes - base class 0xE (Intelligent I/O controllers)
diff --git a/usr/src/uts/common/sys/pci_impl.h b/usr/src/uts/common/sys/pci_impl.h
index 429d6860bd..bdd3116469 100644
--- a/usr/src/uts/common/sys/pci_impl.h
+++ b/usr/src/uts/common/sys/pci_impl.h
@@ -37,7 +37,7 @@ extern "C" {
 
 /*
  * There are two ways to access the PCI configuration space on X86
- * 	Access method 2 is the older method
+ *	Access method 2 is the older method
  *	Access method 1 is the newer method and is preferred because
  *	  of the problems in trying to lock the configuration space
  *	  for MP machines using method 2.  See PCI Local BUS Specification
@@ -50,7 +50,7 @@ extern "C" {
 #define	PCI_MECHANISM_UNKNOWN		-1
 #define	PCI_MECHANISM_NONE		0
 #if defined(__i386) || defined(__amd64)
-#define	PCI_MECHANISM_1 		1
+#define	PCI_MECHANISM_1			1
 #define	PCI_MECHANISM_2			2
 #else
 #error "Unknown processor type"
@@ -82,7 +82,7 @@ extern "C" {
 #define	PCI_CADDR2(device, indx) \
 		(0xc000 | (((device) & 0xf) <<  8) | (indx))
 
-typedef struct 	pci_acc_cfblk {
+typedef struct	pci_acc_cfblk {
 	uchar_t	c_busnum;		/* bus number */
 	uchar_t c_devnum;		/* device number */
 	uchar_t c_funcnum;		/* function number */
diff --git a/usr/src/uts/i86pc/io/apix/apix.c b/usr/src/uts/i86pc/io/apix/apix.c
index 0e8d4f5fd1..87e4b2fe04 100644
--- a/usr/src/uts/i86pc/io/apix/apix.c
+++ b/usr/src/uts/i86pc/io/apix/apix.c
@@ -654,7 +654,7 @@ apix_send_eoi(void)
  *	Called at the beginning of the interrupt service routine, but unlike
  *	pcplusmp, does not mask interrupts. An EOI is given to the interrupt
  *	controller to enable other HW interrupts but interrupts are still
- * 	masked by the IF flag.
+ *	masked by the IF flag.
  *
  *	Return -1 for spurious interrupts
  *
@@ -2175,10 +2175,10 @@ apix_level_intr_pre_eoi(int irq)
 	if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC) {
 		/*
 		 * This is a IOxAPIC and there is EOI register:
-		 * 	Change the vector to reserved unused vector, so that
-		 * 	the EOI	from Local APIC won't clear the Remote IRR for
-		 * 	this level trigger interrupt. Instead, we'll manually
-		 * 	clear it in apix_post_hardint() after ISR handling.
+		 *	Change the vector to reserved unused vector, so that
+		 *	the EOI	from Local APIC won't clear the Remote IRR for
+		 *	this level trigger interrupt. Instead, we'll manually
+		 *	clear it in apix_post_hardint() after ISR handling.
 		 */
 		WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
 		    (irqp->airq_rdt_entry & (~0xff)) | APIX_RESV_VECTOR);
diff --git a/usr/src/uts/i86pc/io/pcplusmp/apic_common.c b/usr/src/uts/i86pc/io/pcplusmp/apic_common.c
index 4eedcbcf02..6e37c2ed59 100644
--- a/usr/src/uts/i86pc/io/pcplusmp/apic_common.c
+++ b/usr/src/uts/i86pc/io/pcplusmp/apic_common.c
@@ -251,13 +251,13 @@ apic_ioapic_method_probe()
 
 	/*
 	 * Set IOAPIC EOI handling method. The priority from low to high is:
-	 * 	1. IOxAPIC: with EOI register
-	 * 	2. IOMMU interrupt mapping
+	 *	1. IOxAPIC: with EOI register
+	 *	2. IOMMU interrupt mapping
 	 *	3. Mask-Before-EOI method for systems without boot
 	 *	interrupt routing, such as systems with only one IOAPIC;
 	 *	NVIDIA CK8-04/MCP55 systems; systems with bridge solution
 	 *	which disables the boot interrupt routing already.
-	 * 	4. Directed EOI
+	 *	4. Directed EOI
 	 */
 	if (apic_io_ver[0] >= 0x20)
 		apix_mul_ioapic_method = APIC_MUL_IOAPIC_IOXAPIC;
@@ -539,7 +539,7 @@ int
 apic_cpu_stop(processorid_t cpun, caddr_t arg)
 {
 	int		rc;
-	cpu_t 		*cp;
+	cpu_t		*cp;
 	extern cpuset_t cpu_ready_set;
 	extern void cpu_idle_intercept_cpu(cpu_t *cp);
 
diff --git a/usr/src/uts/i86pc/os/cpuid.c b/usr/src/uts/i86pc/os/cpuid.c
index e11ee5b70e..4ab084749b 100644
--- a/usr/src/uts/i86pc/os/cpuid.c
+++ b/usr/src/uts/i86pc/os/cpuid.c
@@ -3815,7 +3815,7 @@ cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
 	eax = cpi->cpi_std[1].cp_eax;
 
 #define	SH_B0(eax)	(eax == 0xf40 || eax == 0xf50)
-#define	SH_B3(eax) 	(eax == 0xf51)
+#define	SH_B3(eax)	(eax == 0xf51)
 #define	B(eax)		(SH_B0(eax) || SH_B3(eax))
 
 #define	SH_C0(eax)	(eax == 0xf48 || eax == 0xf58)
@@ -4119,9 +4119,9 @@ static const char sl3_cache_str[] = "sectored-l3-cache";
 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k";
 
 static const struct cachetab {
-	uint8_t 	ct_code;
+	uint8_t	ct_code;
 	uint8_t		ct_assoc;
-	uint16_t 	ct_line_size;
+	uint16_t	ct_line_size;
 	size_t		ct_size;
 	const char	*ct_label;
 } intel_ctab[] = {
diff --git a/usr/src/uts/i86pc/os/trap.c b/usr/src/uts/i86pc/os/trap.c
index be5ad49f0e..49d41f770c 100644
--- a/usr/src/uts/i86pc/os/trap.c
+++ b/usr/src/uts/i86pc/os/trap.c
@@ -25,10 +25,10 @@
 
 /*	Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
 /*	Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T   */
-/*		All Rights Reserved   				*/
+/*		All Rights Reserved				*/
 /*								*/
-/*	Copyright (c) 1987, 1988 Microsoft Corporation  	*/
-/*		All Rights Reserved   				*/
+/*	Copyright (c) 1987, 1988 Microsoft Corporation		*/
+/*		All Rights Reserved				*/
 /*								*/
 
 /*
@@ -113,24 +113,24 @@ static const char *trap_type_mnemonic[] = {
 };
 
 static const char *trap_type[] = {
-	"Divide error",				/* trap id 0 	*/
+	"Divide error",				/* trap id 0	*/
 	"Debug",				/* trap id 1	*/
 	"NMI interrupt",			/* trap id 2	*/
-	"Breakpoint",				/* trap id 3 	*/
-	"Overflow",				/* trap id 4 	*/
-	"BOUND range exceeded",			/* trap id 5 	*/
-	"Invalid opcode",			/* trap id 6 	*/
-	"Device not available",			/* trap id 7 	*/
-	"Double fault",				/* trap id 8 	*/
-	"Coprocessor segment overrun",		/* trap id 9 	*/
-	"Invalid TSS",				/* trap id 10 	*/
-	"Segment not present",			/* trap id 11 	*/
-	"Stack segment fault",			/* trap id 12 	*/
-	"General protection",			/* trap id 13 	*/
-	"Page fault",				/* trap id 14 	*/
-	"Reserved",				/* trap id 15 	*/
-	"x87 floating point error",		/* trap id 16 	*/
-	"Alignment check",			/* trap id 17 	*/
+	"Breakpoint",				/* trap id 3	*/
+	"Overflow",				/* trap id 4	*/
+	"BOUND range exceeded",			/* trap id 5	*/
+	"Invalid opcode",			/* trap id 6	*/
+	"Device not available",			/* trap id 7	*/
+	"Double fault",				/* trap id 8	*/
+	"Coprocessor segment overrun",		/* trap id 9	*/
+	"Invalid TSS",				/* trap id 10	*/
+	"Segment not present",			/* trap id 11	*/
+	"Stack segment fault",			/* trap id 12	*/
+	"General protection",			/* trap id 13	*/
+	"Page fault",				/* trap id 14	*/
+	"Reserved",				/* trap id 15	*/
+	"x87 floating point error",		/* trap id 16	*/
+	"Alignment check",			/* trap id 17	*/
 	"Machine check",			/* trap id 18	*/
 	"SIMD floating point exception",	/* trap id 19	*/
 };
diff --git a/usr/src/uts/intel/io/pci/pci_boot.c b/usr/src/uts/intel/io/pci/pci_boot.c
index 35d5013072..730aee72e1 100644
--- a/usr/src/uts/intel/io/pci/pci_boot.c
+++ b/usr/src/uts/intel/io/pci/pci_boot.c
@@ -881,9 +881,9 @@ list_is_vga_only(struct memlist *l, enum io_mem io)
 /*
  * Assign valid resources to unconfigured pci(e) bridges. We are trying
  * to reprogram the bridge when its
- * 		i)   SECBUS == SUBBUS	||
- * 		ii)  IOBASE > IOLIM	||
- * 		iii) MEMBASE > MEMLIM
+ *		i)   SECBUS == SUBBUS	||
+ *		ii)  IOBASE > IOLIM	||
+ *		iii) MEMBASE > MEMLIM
  * This must be done after one full pass through the PCI tree to collect
  * all BIOS-configured resources, so that we know what resources are
  * free and available to assign to the unconfigured PPBs.
@@ -1362,11 +1362,11 @@ pci_reprogram(void)
 		 * 3. Exclude <1M address range here in case below reserved
 		 * ranges for BIOS data area, ROM area etc are wrongly reported
 		 * in ACPI resource producer entries for PCI root bus.
-		 * 	00000000 - 000003FF	RAM
-		 * 	00000400 - 000004FF	BIOS data area
-		 * 	00000500 - 0009FFFF	RAM
-		 * 	000A0000 - 000BFFFF	VGA RAM
-		 * 	000C0000 - 000FFFFF	ROM area
+		 *	00000000 - 000003FF	RAM
+		 *	00000400 - 000004FF	BIOS data area
+		 *	00000500 - 0009FFFF	RAM
+		 *	000A0000 - 000BFFFF	VGA RAM
+		 *	000C0000 - 000FFFFF	ROM area
 		 */
 		(void) memlist_remove(&pci_bus_res[bus].mem_avail, 0, 0x100000);
 		(void) memlist_remove(&pci_bus_res[bus].pmem_avail,
diff --git a/usr/src/uts/intel/io/pci/pci_pci.c b/usr/src/uts/intel/io/pci/pci_pci.c
index 9f0ed4d67f..b15c057371 100644
--- a/usr/src/uts/intel/io/pci/pci_pci.c
+++ b/usr/src/uts/intel/io/pci/pci_pci.c
@@ -111,15 +111,15 @@ struct bus_ops ppb_bus_ops = {
 	0,			/* (*bus_remove_eventcall)();	*/
 	0,			/* (*bus_post_event)();		*/
 	0,			/* (*bus_intr_ctl)();		*/
-	0,			/* (*bus_config)(); 		*/
-	0,			/* (*bus_unconfig)(); 		*/
-	ppb_fm_init,		/* (*bus_fm_init)(); 		*/
-	NULL,			/* (*bus_fm_fini)(); 		*/
-	NULL,			/* (*bus_fm_access_enter)(); 	*/
-	NULL,			/* (*bus_fm_access_exit)(); 	*/
-	NULL,			/* (*bus_power)(); 	*/
-	ppb_intr_ops,		/* (*bus_intr_op)(); 		*/
-	pcie_hp_common_ops	/* (*bus_hp_op)(); 		*/
+	0,			/* (*bus_config)();		*/
+	0,			/* (*bus_unconfig)();		*/
+	ppb_fm_init,		/* (*bus_fm_init)();		*/
+	NULL,			/* (*bus_fm_fini)();		*/
+	NULL,			/* (*bus_fm_access_enter)();	*/
+	NULL,			/* (*bus_fm_access_exit)();	*/
+	NULL,			/* (*bus_power)();	*/
+	ppb_intr_ops,		/* (*bus_intr_op)();		*/
+	pcie_hp_common_ops	/* (*bus_hp_op)();		*/
 };
 
 /*
@@ -448,7 +448,7 @@ ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
 /*ARGSUSED*/
 static int
 ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
-	off_t offset, off_t len, caddr_t *vaddrp)
+    off_t offset, off_t len, caddr_t *vaddrp)
 {
 	dev_info_t *pdip;
 	ppb_devstate_t *ppb = ddi_get_soft_state(ppb_state,
@@ -471,7 +471,7 @@ ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
 /*ARGSUSED*/
 static int
 ppb_ctlops(dev_info_t *dip, dev_info_t *rdip,
-	ddi_ctl_enum_t ctlop, void *arg, void *result)
+    ddi_ctl_enum_t ctlop, void *arg, void *result)
 {
 	pci_regspec_t *drv_regp;
 	int	reglen;
@@ -979,7 +979,7 @@ ppb_close(dev_t dev, int flags, int otyp, cred_t *credp)
 /* ARGSUSED */
 static int
 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
-	int *rvalp)
+    int *rvalp)
 {
 	int		instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
 	ppb_devstate_t	*ppb_p = ddi_get_soft_state(ppb_state, instance);
diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h
index 6276bbd2c9..b863a8e592 100644
--- a/usr/src/uts/intel/sys/x86_archext.h
+++ b/usr/src/uts/intel/sys/x86_archext.h
@@ -90,7 +90,7 @@ extern "C" {
  */
 
 #define	CPUID_INTC_ECX_SSE3	0x00000001	/* Yet more SSE extensions */
-#define	CPUID_INTC_ECX_PCLMULQDQ 0x00000002 	/* PCLMULQDQ insn */
+#define	CPUID_INTC_ECX_PCLMULQDQ 0x00000002	/* PCLMULQDQ insn */
 #define	CPUID_INTC_ECX_DTES64	0x00000004	/* 64-bit DS area */
 #define	CPUID_INTC_ECX_MON	0x00000008	/* MONITOR/MWAIT */
 #define	CPUID_INTC_ECX_DSCPL	0x00000010	/* CPL-qualified debug store */
@@ -322,10 +322,10 @@ extern "C" {
 #define	MSR_PRP4_LBSTK_FROM_5	0x685
 #define	MSR_PRP4_LBSTK_FROM_6	0x686
 #define	MSR_PRP4_LBSTK_FROM_7	0x687
-#define	MSR_PRP4_LBSTK_FROM_8 	0x688
+#define	MSR_PRP4_LBSTK_FROM_8	0x688
 #define	MSR_PRP4_LBSTK_FROM_9	0x689
 #define	MSR_PRP4_LBSTK_FROM_10	0x68a
-#define	MSR_PRP4_LBSTK_FROM_11 	0x68b
+#define	MSR_PRP4_LBSTK_FROM_11	0x68b
 #define	MSR_PRP4_LBSTK_FROM_12	0x68c
 #define	MSR_PRP4_LBSTK_FROM_13	0x68d
 #define	MSR_PRP4_LBSTK_FROM_14	0x68e
@@ -339,7 +339,7 @@ extern "C" {
 #define	MSR_PRP4_LBSTK_TO_6	0x6c6
 #define	MSR_PRP4_LBSTK_TO_7	0x6c7
 #define	MSR_PRP4_LBSTK_TO_8	0x6c8
-#define	MSR_PRP4_LBSTK_TO_9 	0x6c9
+#define	MSR_PRP4_LBSTK_TO_9	0x6c9
 #define	MSR_PRP4_LBSTK_TO_10	0x6ca
 #define	MSR_PRP4_LBSTK_TO_11	0x6cb
 #define	MSR_PRP4_LBSTK_TO_12	0x6cc