[illumos-gate merge]

commit 1f1540205fa6366266184180654434272c425ac2
    9820 Want risc-v disassembler
commit 856f620e96e5413932a6607aea5094db2ece172f
    9819 update sys/elf.h for recent processors like aarch64/risc-v

	Conflicts:
	usr/src/lib/libdisasm/common/dis_riscv.c
	usr/src/lib/libdisasm/Makefile.com

6 files changed, 198 insertions, 126 deletions

diff --git a/usr/src/cmd/dis/dis_main.c b/usr/src/cmd/dis/dis_main.c
index 77377c4673..db785eff7b 100644
--- a/usr/src/cmd/dis/dis_main.c
+++ b/usr/src/cmd/dis/dis_main.c
@@ -584,7 +584,7 @@ dis_file(const char *filename)
 			/*
 			 * RISC-V is defined to be litle endian. The current ISA
 			 * makes it clear that the 64-bit instructions can
-			 * co-eixst with the 32-bit ones and therefore we don't
+			 * co-exist with the 32-bit ones and therefore we don't
 			 * need a separate elf class at this time.
 			 */
 			if (ehdr.e_ident[EI_DATA] != ELFDATA2LSB) {
diff --git a/usr/src/cmd/file/Makefile b/usr/src/cmd/file/Makefile
index 0c9f5dd3fd..e05f3e4689 100644
--- a/usr/src/cmd/file/Makefile
+++ b/usr/src/cmd/file/Makefile
@@ -37,6 +37,9 @@ SRCS=	file.c elf_read.c magicutils.c $(ELFCAP)/elfcap.c
 
 include ../Makefile.cmd
 
+CSTD=	$(CSTD_GNU99)
+C99LMODE= -Xc99=%all
+
 CERRWARN += -_gcc=-Wno-uninitialized
 CERRWARN += -_gcc=-Wno-type-limits
 
diff --git a/usr/src/lib/libdisasm/Makefile.com b/usr/src/lib/libdisasm/Makefile.com
index 4bb5cf6964..2afa0e3499 100644
--- a/usr/src/lib/libdisasm/Makefile.com
+++ b/usr/src/lib/libdisasm/Makefile.com
@@ -89,7 +89,7 @@ SRCS_library=		$(SRCS_common) \
 			$(SRCS_i386) \
 			$(SRCS_sparc) \
 			$(SRCS_s390x) \
-			$(SRCS_riscv) \
+			$(SRCS_riscv)
 SRCS_standalone=	$(SRCS_common) \
 			$(SRCS_$(MACH))
 SRCS=			$(SRCS_$(CURTYPE))
diff --git a/usr/src/lib/libdisasm/common/dis_riscv.c b/usr/src/lib/libdisasm/common/dis_riscv.c
index a7cc4b0917..fa7cc30610 100644
--- a/usr/src/lib/libdisasm/common/dis_riscv.c
+++ b/usr/src/lib/libdisasm/common/dis_riscv.c
@@ -25,7 +25,7 @@
 
 #include <stdio.h>
 
-extern size_t strcmp(const char *, const char *);
+extern int strcmp(const char *, const char *);
 
 /*
  * Register names based on their ABI name.
@@ -53,9 +53,9 @@ static const char *dis_riscv_c_fpregs[8] = {
 };
 
 /*
- * RM names have the leading comma in them because the last value represents that
- * the hardware register decides the rounding mode and therefore nothing should
- * be appended to the instruction.
+ * RM names have the leading comma in them because the last value represents
+ * that the hardware register decides the rounding mode and therefore nothing
+ * should be appended to the instruction.
  */
 static const char *dis_riscv_rm[8] = {
 	",rne", ",rtz", ",rdn", ",rup", ",rmm", ",???", ",???", ""
@@ -322,6 +322,7 @@ typedef struct dis_riscv_instr {
 	uint_t			drv_funct2;
 } dis_riscv_instr_t;
 
+/*ARGSUSED*/
 static void
 dis_riscv_rtype_32(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -407,6 +408,7 @@ dis_riscv_stype_32(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 	}
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_utype_32(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -474,6 +476,7 @@ dis_riscv_shift_64(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 	}
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_csr(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -638,6 +641,7 @@ dis_riscv_csri(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 #define	DIS_RISCV_FENCE_W	0x1
 #define	DIS_RISCV_FENCE_IORW	0xf
 
+/*ARGSUSED*/
 static void
 dis_riscv_fence(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -669,6 +673,7 @@ dis_riscv_fence(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 	    succ & DIS_RISCV_FENCE_W ? "w" : "");
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_name(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -676,6 +681,7 @@ dis_riscv_name(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 	(void) dis_snprintf(buf, buflen, "%s", table->drv_name);
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_rs1_rs2(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -685,6 +691,7 @@ dis_riscv_rs1_rs2(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 	    dis_riscv_regs[DIS_RISCV_RS2(instr)]);
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_rv32a_load(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_instr_t *table, char *buf, size_t buflen)
@@ -704,6 +711,7 @@ dis_riscv_rv32a_load(dis_handle_t *dhp, uint32_t instr,
 	    dis_riscv_regs[DIS_RISCV_RS1(instr)]);
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_rv32a(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -761,6 +769,7 @@ dis_riscv_fp_store(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 	}
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_fp_r(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -774,6 +783,7 @@ dis_riscv_fp_r(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 /*
  * Variant of fp_r type that goes to integer destination registers.
  */
+/*ARGSUSED*/
 static void
 dis_riscv_fp_r_fpi(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -784,7 +794,7 @@ dis_riscv_fp_r_fpi(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 	    dis_riscv_fpregs[DIS_RISCV_RS2(instr)]);
 }
 
-
+/*ARGSUSED*/
 static void
 dis_riscv_fp_r4(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -797,6 +807,7 @@ dis_riscv_fp_r4(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 	    dis_riscv_rm[DIS_RISCV_FUNCT3(instr)]);
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_fp_rs2_fp(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
     char *buf, size_t buflen)
@@ -807,6 +818,7 @@ dis_riscv_fp_rs2_fp(dis_handle_t *dhp, uint32_t instr, dis_riscv_instr_t *table,
 	    dis_riscv_rm[DIS_RISCV_FUNCT3(instr)]);
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_fp_rs2_fp_nr(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_instr_t *table, char *buf, size_t buflen)
@@ -816,7 +828,7 @@ dis_riscv_fp_rs2_fp_nr(dis_handle_t *dhp, uint32_t instr,
 	    dis_riscv_fpregs[DIS_RISCV_RS1(instr)]);
 }
 
-
+/*ARGSUSED*/
 static void
 dis_riscv_fp_rs2_fpi(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_instr_t *table, char *buf, size_t buflen)
@@ -827,6 +839,7 @@ dis_riscv_fp_rs2_fpi(dis_handle_t *dhp, uint32_t instr,
 	    dis_riscv_rm[DIS_RISCV_FUNCT3(instr)]);
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_fp_rs2_ifp(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_instr_t *table, char *buf, size_t buflen)
@@ -837,6 +850,7 @@ dis_riscv_fp_rs2_ifp(dis_handle_t *dhp, uint32_t instr,
 	    dis_riscv_rm[DIS_RISCV_FUNCT3(instr)]);
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_fp_rs2_fpi_nr(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_instr_t *table, char *buf, size_t buflen)
@@ -846,6 +860,7 @@ dis_riscv_fp_rs2_fpi_nr(dis_handle_t *dhp, uint32_t instr,
 	    dis_riscv_fpregs[DIS_RISCV_RS1(instr)]);
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_fp_rs2_ifp_nr(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_instr_t *table, char *buf, size_t buflen)
@@ -856,6 +871,7 @@ dis_riscv_fp_rs2_ifp_nr(dis_handle_t *dhp, uint32_t instr,
 }
 
 
+/*ARGSUSED*/
 static void
 dis_riscv_fp_rm(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_instr_t *table, char *buf, size_t buflen)
@@ -1340,6 +1356,7 @@ typedef struct dis_riscv_c_instr {
 #define	DIS_RISCV_C_A4_2(x)	(((x) & 0x0040) >> 4)
 #define	DIS_RISCV_C_A4_3(x)	(((x) & 0x0020) >> 2)
 
+/*ARGSUSED*/
 static void
 dis_riscv_c_name(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_c_instr_t *table, char *buf, size_t buflen)
@@ -1528,6 +1545,7 @@ dis_riscv_c_j(dis_handle_t *dhp, uint32_t instr,
 	}
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_c_jr(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_c_instr_t *table, char *buf, size_t buflen)
@@ -1639,6 +1657,7 @@ dis_riscv_c_zext_immint(dis_handle_t *dhp, uint32_t instr,
 	    dis_riscv_c_regs[DIS_RISCV_C_RS1P(instr)], "", imm, buf, buflen);
 }
 
+/*ARGSUSED*/
 static void
 dis_riscv_c_bigint(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_c_instr_t *table, char *buf, size_t buflen)
@@ -1649,6 +1668,7 @@ dis_riscv_c_bigint(dis_handle_t *dhp, uint32_t instr,
 }
 
 
+/*ARGSUSED*/
 static void
 dis_riscv_c_int(dis_handle_t *dhp, uint32_t instr,
     dis_riscv_c_instr_t *table, char *buf, size_t buflen)
@@ -1935,12 +1955,14 @@ dis_riscv_disassemble(dis_handle_t *dhp, uint64_t addr, char *buf,
 	return (0);
 }
 
+/*ARGSUSED*/
 static int
 dis_riscv_min_instrlen(dis_handle_t *dhp)
 {
 	return (2);
 }
 
+/*ARGSUSED*/
 static int
 dis_riscv_max_instrlen(dis_handle_t *dhp)
 {
diff --git a/usr/src/pkg/manifests/system-test-utiltest.mf b/usr/src/pkg/manifests/system-test-utiltest.mf
index 8ba9bf48bc..ea1a72989c 100644
--- a/usr/src/pkg/manifests/system-test-utiltest.mf
+++ b/usr/src/pkg/manifests/system-test-utiltest.mf
@@ -28,6 +28,8 @@ dir path=opt/util-tests/runfiles
 dir path=opt/util-tests/tests
 dir path=opt/util-tests/tests/dis
 dir path=opt/util-tests/tests/dis/i386
+dir path=opt/util-tests/tests/dis/risc-v
+dir path=opt/util-tests/tests/dis/risc-v-c
 dir path=opt/util-tests/tests/dis/sparc
 dir path=opt/util-tests/tests/files
 dir path=opt/util-tests/tests/libnvpair_json
@@ -1115,124 +1117,168 @@ file path=opt/util-tests/tests/awk/tests/T.sub mode=0555
 file path=opt/util-tests/tests/awk/tests/T.system mode=0555
 file path=opt/util-tests/tests/date_test mode=0555
 file path=opt/util-tests/tests/dis/distest mode=0555
-file path=opt/util-tests/tests/dis/i386/32.adx.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.adx.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.aes.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.aes.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.avx.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.avx.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.avx2.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.avx2.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.avx512.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.avx512.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.bmi1.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.bmi1.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.bmi2.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.bmi2.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.f16c.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.f16c.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.fma-pd.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.fma-pd.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.fma-ps.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.fma-ps.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.fma-sd.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.fma-sd.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.fma-ss.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.fma-ss.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.lzcnt.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.lzcnt.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.movbe.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.movbe.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.opmask.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.opmask.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.pclmulqdq.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.pclmulqdq.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.popcnt.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.popcnt.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.sha.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.sha.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.sse-3.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.sse-3.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.sse-4.1.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.sse-4.1.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.sse-4.2.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.sse-4.2.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.ssse3.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.ssse3.s mode=0555
-file path=opt/util-tests/tests/dis/i386/32.xsave.out mode=0555
-file path=opt/util-tests/tests/dis/i386/32.xsave.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.adx.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.adx.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.aes.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.aes.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.avx.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.avx.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.avx2.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.avx2.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.avx512.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.avx512.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.bmi1.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.bmi1.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.bmi2.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.bmi2.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.ept.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.ept.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.f16c.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.f16c.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.fma-pd.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.fma-pd.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.fma-ps.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.fma-ps.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.fma-sd.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.fma-sd.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.fma-ss.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.fma-ss.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.lzcnt.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.lzcnt.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.movbe.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.movbe.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.opmask.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.opmask.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.pclmulqdq.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.pclmulqdq.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.popcnt.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.popcnt.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.random.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.random.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.sha.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.sha.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.sse-3.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.sse-3.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.sse-4.1.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.sse-4.1.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.sse-4.2.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.sse-4.2.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.ssse3.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.ssse3.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.vmx.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.vmx.s mode=0555
-file path=opt/util-tests/tests/dis/i386/64.xsave.out mode=0555
-file path=opt/util-tests/tests/dis/i386/64.xsave.s mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.cpuid.out mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.cpuid.s mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.fence.out mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.fence.s mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.msr.out mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.msr.s mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.mwait.out mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.mwait.s mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.random.out mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.random.s mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.sep.out mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.sep.s mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.smap.out mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.smap.s mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.tsc.out mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.tsc.s mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.vmx.out mode=0555
-file path=opt/util-tests/tests/dis/i386/tst.vmx.s mode=0555
-file path=opt/util-tests/tests/dis/sparc/tst.regs.out mode=0555
-file path=opt/util-tests/tests/dis/sparc/tst.regs.s mode=0555
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+file path=opt/util-tests/tests/dis/i386/32.sha.out mode=0444
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+file path=opt/util-tests/tests/dis/i386/32.xsave.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.adx.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.adx.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.aes.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.aes.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.avx.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.avx.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.avx2-gather.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.avx2-gather.s mode=0444
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+file path=opt/util-tests/tests/dis/i386/64.bmi2.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.ept.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.ept.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.f16c.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.f16c.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.fma-pd.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.fma-pd.s mode=0444
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+file path=opt/util-tests/tests/dis/i386/64.fma-ps.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.fma-sd.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.fma-sd.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.fma-ss.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.fma-ss.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.lzcnt.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.lzcnt.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.movbe.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.movbe.s mode=0444
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+file path=opt/util-tests/tests/dis/i386/64.opmask.s mode=0444
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+file path=opt/util-tests/tests/dis/i386/64.pclmulqdq.s mode=0444
+file path=opt/util-tests/tests/dis/i386/64.popcnt.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.popcnt.s mode=0444
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+file path=opt/util-tests/tests/dis/i386/64.sse-3.out mode=0444
+file path=opt/util-tests/tests/dis/i386/64.sse-3.s mode=0444
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+file path=opt/util-tests/tests/dis/i386/64.sse-4.1.s mode=0444
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+file path=opt/util-tests/tests/dis/i386/64.xsave.s mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.cpuid.out mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.cpuid.s mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.fence.out mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.fence.s mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.msr.out mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.msr.s mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.mwait.out mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.mwait.s mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.random.out mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.random.s mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.sep.out mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.sep.s mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.smap.out mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.smap.s mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.tsc.out mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.tsc.s mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.vmx.out mode=0444
+file path=opt/util-tests/tests/dis/i386/tst.vmx.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v-c/32.ldsr.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v-c/32.ldsr.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v-c/64.int.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v-c/64.int.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v-c/64.ldsr.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v-c/64.ldsr.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v-c/tst.int.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v-c/tst.int.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v-c/tst.ldsr.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v-c/tst.ldsr.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/64.rv64a.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/64.rv64a.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/64.rv64d.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/64.rv64d.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/64.rv64f.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/64.rv64f.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/64.rv64i.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/64.rv64i.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/64.rv64m.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/64.rv64m.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.csr.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.csr.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.fpregs.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.fpregs.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.pseudo.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.pseudo.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.regs.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.regs.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.rv32a.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.rv32a.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.rv32d.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.rv32d.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.rv32f.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.rv32f.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.rv32i.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.rv32i.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.rv32m.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.rv32m.s mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.supervisor.out mode=0444
+file path=opt/util-tests/tests/dis/risc-v/tst.supervisor.s mode=0444
+file path=opt/util-tests/tests/dis/sparc/tst.regs.out mode=0444
+file path=opt/util-tests/tests/dis/sparc/tst.regs.s mode=0444
 file path=opt/util-tests/tests/files/gout0 mode=0444
 file path=opt/util-tests/tests/files/gout1 mode=0444
 file path=opt/util-tests/tests/files/gout10 mode=0444
diff --git a/usr/src/test/util-tests/tests/dis/Makefile b/usr/src/test/util-tests/tests/dis/Makefile
index 753c285e9b..3c4c8a5773 100644
--- a/usr/src/test/util-tests/tests/dis/Makefile
+++ b/usr/src/test/util-tests/tests/dis/Makefile
@@ -37,6 +37,7 @@ include $(SRC)/test/Makefile.com
 
 ARCHDIRS = $(ARCHS:%=$(TESTDIR)/%)
 CMDS = $(PROG:%=$(TESTDIR)/%)
+FILEMODE=0444
 $(CMDS) := FILEMODE = 0555
 
 install: $(CMDS) $(ROOTFILES)