12996 bhyve kernel should be wscheck clean

Reviewed by: Andy Fiddaman <andy@omniosce.org>
Approved by: Robert Mustacchi <rm@fingolfin.org>

29 files changed, 140 insertions, 167 deletions

diff --git a/exception_lists/wscheck b/exception_lists/wscheck
index 9b1c5f93be..48893a7a1b 100644
--- a/exception_lists/wscheck
+++ b/exception_lists/wscheck
@@ -86,26 +86,6 @@ usr/src/cmd/bhyve/usb_mouse.c
 usr/src/cmd/bhyve/vga.[ch]
 usr/src/cmd/bhyve/virtio.[ch]
 usr/src/cmd/bhyve/xmsr.[ch]
-usr/src/cmd/bhyveconsole/bhyveconsole.c
 usr/src/cmd/bhyvectl/bhyvectl.c
-usr/src/compat/bhyve/*
 usr/src/contrib/bhyve/*
 usr/src/lib/libvmmapi/common/vmmapi.[ch]
-usr/src/uts/i86pc/io/vmm/amd/*.[ch]
-usr/src/uts/i86pc/io/vmm/intel/*.[chs]
-usr/src/uts/i86pc/io/vmm/io/*.[ch]
-usr/src/uts/i86pc/io/vmm/vmm.c
-usr/src/uts/i86pc/io/vmm/vmm_host.[ch]
-usr/src/uts/i86pc/io/vmm/vmm_instruction_emul.c
-usr/src/uts/i86pc/io/vmm/vmm_ioport.[ch]
-usr/src/uts/i86pc/io/vmm/vmm_ipi.h
-usr/src/uts/i86pc/io/vmm/vmm_ktr.h
-usr/src/uts/i86pc/io/vmm/vmm_lapic.[ch]
-usr/src/uts/i86pc/io/vmm/vmm_mem.[ch]
-usr/src/uts/i86pc/io/vmm/vmm_sol_glue.c
-usr/src/uts/i86pc/io/vmm/vmm_stat.[ch]
-usr/src/uts/i86pc/io/vmm/vmm_util.[ch]
-usr/src/uts/i86pc/io/vmm/vmx_assym.s
-usr/src/uts/i86pc/io/vmm/x86.[ch]
-usr/src/uts/i86pc/sys/vmm.h
-usr/src/uts/i86pc/sys/vmm_dev.h
diff --git a/usr/src/compat/bhyve/amd64/machine/cpufunc.h b/usr/src/compat/bhyve/amd64/machine/cpufunc.h
index 0b7bcdaa59..bb79ac3ce9 100644
--- a/usr/src/compat/bhyve/amd64/machine/cpufunc.h
+++ b/usr/src/compat/bhyve/amd64/machine/cpufunc.h
@@ -116,7 +116,7 @@ static __inline uint64_t
 rdmsr(u_int msr)
 {
 	uint32_t low, high;
- 
+
 	__asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
 	return (low | ((uint64_t)high << 32));
 }
@@ -150,7 +150,7 @@ static __inline u_long
 rcr0(void)
 {
 	u_long  data;
- 
+
 	__asm __volatile("movq %%cr0,%0" : "=r" (data));
 	return (data);
 }
@@ -174,7 +174,7 @@ static __inline u_long
 rcr4(void)
 {
 	u_long  data;
- 
+
 	__asm __volatile("movq %%cr4,%0" : "=r" (data));
 	return (data);
 }
diff --git a/usr/src/compat/bhyve/amd64/machine/pmap.h b/usr/src/compat/bhyve/amd64/machine/pmap.h
index ce3185629b..3b94d1b1a9 100644
--- a/usr/src/compat/bhyve/amd64/machine/pmap.h
+++ b/usr/src/compat/bhyve/amd64/machine/pmap.h
@@ -153,7 +153,7 @@
 #define PGEX_RSV	0x08	/* reserved PTE field is non-zero */
 #define PGEX_I		0x10	/* during an instruction fetch */
 
-/* 
+/*
  * undef the PG_xx macros that define bits in the regular x86 PTEs that
  * have a different position in nested PTEs. This is done when compiling
  * code that needs to be aware of the differences between regular x86 and
diff --git a/usr/src/compat/bhyve/net/ieee_oui.h b/usr/src/compat/bhyve/net/ieee_oui.h
index 068328d833..115e6a44f8 100644
--- a/usr/src/compat/bhyve/net/ieee_oui.h
+++ b/usr/src/compat/bhyve/net/ieee_oui.h
@@ -37,14 +37,14 @@
 #define OUI_FREEBSD_BASE 0x589cfc000000
 #define OUI_FREEBSD(nic) (OUI_FREEBSD_BASE | (nic))
 
-/* 
+/*
  * OUIs are most often used to uniquely identify network interfaces
  * and occupy the first 3 bytes of both destination and source MAC
  * addresses.  The following allocations exist so that various
  * software systems associated with FreeBSD can have unique IDs in the
  * absence of hardware.  The use of OUIs for this purpose is not fully
  * fleshed out but is now in common use in virtualization technology.
- * 
+ *
  * Allocations from this range are expected to be made using COMMON
  * SENSE by developers.  Do NOT take a large range just because
  * they're currently wide open.  Take the smallest useful range for
@@ -53,7 +53,7 @@
  *
  * In the event of a conflict arbitration of allocation in this file
  * is subject to core@ approval.
- * 
+ *
  * Applications are differentiated based on the high order bit(s) of
  * the remaining three bytes.  Our first allocation has all 0s, the
  * next allocation has the highest bit set.  Allocating in this way
diff --git a/usr/src/compat/bhyve/x86/_types.h b/usr/src/compat/bhyve/x86/_types.h
index 8bbae549d8..0263c33d5f 100644
--- a/usr/src/compat/bhyve/x86/_types.h
+++ b/usr/src/compat/bhyve/x86/_types.h
@@ -33,7 +33,7 @@ typedef long long		__int64_t;
 typedef unsigned long long	__uint64_t;
 #endif
 
-/* 
+/*
  * Standard type definitions.
  */
 #ifdef	_LP64
diff --git a/usr/src/uts/i86pc/io/vmm/amd/amdvi_hw.c b/usr/src/uts/i86pc/io/vmm/amd/amdvi_hw.c
index 9cf9200b3d..a01b06446d 100644
--- a/usr/src/uts/i86pc/io/vmm/amd/amdvi_hw.c
+++ b/usr/src/uts/i86pc/io/vmm/amd/amdvi_hw.c
@@ -1003,8 +1003,8 @@ amdvi_teardown_hw(struct amdvi_softc *softc)
 
 	dev = softc->dev;
 
-	/* 
-	 * Called after disable, h/w is stopped by now, free all the resources. 
+	/*
+	 * Called after disable, h/w is stopped by now, free all the resources.
 	 */
 	amdvi_free_evt_intr_res(dev);
 
@@ -1026,7 +1026,7 @@ amdvi_init(void)
 	}
 	if (!amdvi_enable_user && ivhd_count) {
 		printf("bhyve: Found %d AMD-Vi/IOMMU device(s), "
-		    	"use hw.vmm.amdvi.enable=1 to enable pass-through.\n",
+		    "use hw.vmm.amdvi.enable=1 to enable pass-through.\n",
 		    ivhd_count);
 		return (EINVAL);
 	}
@@ -1304,7 +1304,7 @@ amdvi_set_dte(struct amdvi_domain *domain, uint16_t devid, bool enable)
 	struct amdvi_dte* temp;
 
 	KASSERT(domain, ("domain is NULL for pci_rid:0x%x\n", devid));
-	
+
 	softc = amdvi_find_iommu(devid);
 	KASSERT(softc, ("softc is NULL for pci_rid:0x%x\n", devid));
 
@@ -1397,11 +1397,11 @@ amdvi_enable(void)
 		ctrl = softc->ctrl;
 		KASSERT(ctrl, ("ctrl is NULL\n"));
 
-		val = (	AMDVI_CTRL_EN 		|
-			AMDVI_CTRL_CMD 		|
-		    	AMDVI_CTRL_ELOG 	|
-		    	AMDVI_CTRL_ELOGINT 	|
-		    	AMDVI_CTRL_INV_TO_1S);
+		val = (	AMDVI_CTRL_EN		|
+			AMDVI_CTRL_CMD		|
+			AMDVI_CTRL_ELOG		|
+			AMDVI_CTRL_ELOGINT	|
+			AMDVI_CTRL_INV_TO_1S);
 
 		if (softc->ivhd_flag & IVHD_FLAG_COH)
 			val |= AMDVI_CTRL_COH;
diff --git a/usr/src/uts/i86pc/io/vmm/amd/amdvi_priv.h b/usr/src/uts/i86pc/io/vmm/amd/amdvi_priv.h
index 2db6914f08..5d47142a72 100644
--- a/usr/src/uts/i86pc/io/vmm/amd/amdvi_priv.h
+++ b/usr/src/uts/i86pc/io/vmm/amd/amdvi_priv.h
@@ -35,7 +35,7 @@
 
 #define	BIT(n)			(1ULL << (n))
 /* Return value of bits[n:m] where n and (n >= ) m are bit positions. */
-#define REG_BITS(x, n, m)	(((x) >> (m)) & 		\
+#define REG_BITS(x, n, m)	(((x) >> (m)) &			\
 				((1 << (((n) - (m)) + 1)) - 1))
 
 /*
@@ -111,10 +111,10 @@ CTASSERT(sizeof(struct amdvi_dte) == 32);
  * IOMMU command entry.
  */
 struct amdvi_cmd {
-	uint32_t 	word0;
-	uint32_t 	word1:28;
+	uint32_t	word0;
+	uint32_t	word1:28;
 	uint8_t		opcode:4;
-	uint64_t 	addr;
+	uint64_t	addr;
 } __attribute__((__packed__));
 
 /* Command opcodes. */
@@ -150,12 +150,12 @@ struct amdvi_cmd {
  * IOMMU event entry.
  */
 struct amdvi_event {
-	uint16_t 	devid;
-	uint16_t 	pasid_hi;
-	uint16_t 	pasid_domid;	/* PASID low or DomainID */
-	uint16_t 	flag:12;
+	uint16_t	devid;
+	uint16_t	pasid_hi;
+	uint16_t	pasid_domid;	/* PASID low or DomainID */
+	uint16_t	flag:12;
 	uint8_t		opcode:4;
-	uint64_t 	addr;
+	uint64_t	addr;
 } __attribute__((__packed__));
 CTASSERT(sizeof(struct amdvi_event) == 16);
 
@@ -210,8 +210,8 @@ struct amdvi_ctrl {
 		uint64_t limit:40;
 		uint16_t :12;
 	} excl;
-	/* 
-	 * Revision 2 only. 
+	/*
+	 * Revision 2 only.
 	 */
 	uint64_t ex_feature;
 	struct {
@@ -252,8 +252,8 @@ CTASSERT(offsetof(struct amdvi_ctrl, pad2)== 0x2028);
 CTASSERT(offsetof(struct amdvi_ctrl, pad3)== 0x2040);
 
 #define AMDVI_MMIO_V1_SIZE	(4 * PAGE_SIZE)	/* v1 size */
-/* 
- * AMF IOMMU v2 size including event counters 
+/*
+ * AMF IOMMU v2 size including event counters
  */
 #define AMDVI_MMIO_V2_SIZE	(8 * PAGE_SIZE)
 
@@ -374,38 +374,38 @@ enum IvrsType
  */
 struct amdvi_softc {
 	struct amdvi_ctrl *ctrl;	/* Control area. */
-	device_t 	dev;		/* IOMMU device. */
+	device_t	dev;		/* IOMMU device. */
 	enum IvrsType   ivhd_type;	/* IOMMU IVHD type. */
 	bool		iotlb;		/* IOTLB supported by IOMMU */
 	struct amdvi_cmd *cmd;		/* Command descriptor area. */
-	int 		cmd_max;	/* Max number of commands. */
+	int		cmd_max;	/* Max number of commands. */
 	uint64_t	cmp_data;	/* Command completion write back. */
 	struct amdvi_event *event;	/* Event descriptor area. */
 	struct resource *event_res;	/* Event interrupt resource. */
-	void   		*event_tag;	/* Event interrupt tag. */
+	void		*event_tag;	/* Event interrupt tag. */
 	int		event_max;	/* Max number of events. */
 	int		event_irq;
 	int		event_rid;
 	/* ACPI various flags. */
-	uint32_t 	ivhd_flag;	/* ACPI IVHD flag. */
-	uint32_t 	ivhd_feature;	/* ACPI v1 Reserved or v2 attribute. */
-	uint64_t 	ext_feature;	/* IVHD EFR */
+	uint32_t	ivhd_flag;	/* ACPI IVHD flag. */
+	uint32_t	ivhd_feature;	/* ACPI v1 Reserved or v2 attribute. */
+	uint64_t	ext_feature;	/* IVHD EFR */
 	/* PCI related. */
-	uint16_t 	cap_off;	/* PCI Capability offset. */
+	uint16_t	cap_off;	/* PCI Capability offset. */
 	uint8_t		pci_cap;	/* PCI capability. */
-	uint16_t 	pci_seg;	/* IOMMU PCI domain/segment. */
-	uint16_t 	pci_rid;	/* PCI BDF of IOMMU */
+	uint16_t	pci_seg;	/* IOMMU PCI domain/segment. */
+	uint16_t	pci_rid;	/* PCI BDF of IOMMU */
 	/* Device range under this IOMMU. */
-	uint16_t 	start_dev_rid;	/* First device under this IOMMU. */
-	uint16_t 	end_dev_rid;	/* Last device under this IOMMU. */
+	uint16_t	start_dev_rid;	/* First device under this IOMMU. */
+	uint16_t	end_dev_rid;	/* Last device under this IOMMU. */
 
 	/* BIOS provided device configuration for end points. */
-	struct 		ivhd_dev_cfg dev_cfg[10];
+	struct		ivhd_dev_cfg dev_cfg[10];
 	int		dev_cfg_cnt;
 
 	/* Software statistics. */
-	uint64_t 	event_intr_cnt;	/* Total event INTR count. */
-	uint64_t 	total_cmd;	/* Total number of commands. */
+	uint64_t	event_intr_cnt;	/* Total event INTR count. */
+	uint64_t	total_cmd;	/* Total number of commands. */
 };
 
 int	amdvi_setup_hw(struct amdvi_softc *softc);
diff --git a/usr/src/uts/i86pc/io/vmm/amd/ivrs_drv.c b/usr/src/uts/i86pc/io/vmm/amd/ivrs_drv.c
index b754058c07..11925582ef 100644
--- a/usr/src/uts/i86pc/io/vmm/amd/ivrs_drv.c
+++ b/usr/src/uts/i86pc/io/vmm/amd/ivrs_drv.c
@@ -50,11 +50,11 @@ __FBSDID("$FreeBSD$");
 
 device_t *ivhd_devs;			/* IVHD or AMD-Vi device list. */
 int	ivhd_count;			/* Number of IVHD header. */
-/* 
+/*
  * Cached IVHD header list.
  * Single entry for each IVHD, filtered the legacy one.
  */
-ACPI_IVRS_HARDWARE1 *ivhd_hdrs[10];	
+ACPI_IVRS_HARDWARE1 *ivhd_hdrs[10];
 
 extern int amdvi_ptp_level;		/* Page table levels. */
 
@@ -218,7 +218,7 @@ ivhd_dev_parse(ACPI_IVRS_HARDWARE1 *ivhd, struct amdvi_softc *softc)
 			break;
 
 		default:
-			device_printf(softc->dev, 
+			device_printf(softc->dev,
 				"unknown type: 0x%x\n", ivhd->Header.Type);
 			return (-1);
 	}
@@ -346,7 +346,7 @@ ivhd_identify(driver_t *driver, device_t parent)
 	ivrs_ivinfo = ivrs->Info;
 	printf("AMD-Vi: IVRS Info VAsize = %d PAsize = %d GVAsize = %d"
 	       " flags:%b\n",
-		REG_BITS(ivrs_ivinfo, 21, 15), REG_BITS(ivrs_ivinfo, 14, 8), 
+		REG_BITS(ivrs_ivinfo, 21, 15), REG_BITS(ivrs_ivinfo, 14, 8),
 		REG_BITS(ivrs_ivinfo, 7, 5), REG_BITS(ivrs_ivinfo, 22, 22),
 		"\020\001EFRSup");
 
@@ -360,17 +360,17 @@ ivhd_identify(driver_t *driver, device_t parent)
 		ivhd_hdrs[i] = ivhd;
 	}
 
-        /* 
+        /*
 	 * Scan for presence of legacy and non-legacy device type
 	 * for same AMD-Vi device and override the old one.
 	 */
 	for (i = ivhd_count - 1 ; i > 0 ; i--){
-       		if (ivhd_is_newer(&ivhd_hdrs[i-1]->Header, 
+		if (ivhd_is_newer(&ivhd_hdrs[i-1]->Header,
 			&ivhd_hdrs[i]->Header)) {
 			ivhd_hdrs[i-1] = ivhd_hdrs[i];
 			ivhd_count--;
 		}
-       }	       
+       }
 
 	ivhd_devs = malloc(sizeof(device_t) * ivhd_count, M_DEVBUF,
 		M_WAITOK | M_ZERO);
@@ -415,7 +415,7 @@ ivhd_probe(device_t dev)
 		return (ENXIO);
 
 	unit = device_get_unit(dev);
-	KASSERT((unit < ivhd_count), 
+	KASSERT((unit < ivhd_count),
 		("ivhd unit %d > count %d", unit, ivhd_count));
 	ivhd = ivhd_hdrs[unit];
 	KASSERT(ivhd, ("ivhd is NULL"));
@@ -424,7 +424,7 @@ ivhd_probe(device_t dev)
 	case IVRS_TYPE_HARDWARE_EFR:
 		device_set_desc(dev, "AMD-Vi/IOMMU ivhd with EFR");
 		break;
-	
+
 	case IVRS_TYPE_HARDWARE_MIXED:
 		device_set_desc(dev, "AMD-Vi/IOMMU ivhd in mixed format");
 		break;
@@ -482,7 +482,7 @@ ivhd_print_flag(device_t dev, enum IvrsType ivhd_type, uint8_t flag)
  * Feature in legacy IVHD type(0x10) and attribute in newer type(0x11 and 0x40).
  */
 static void
-ivhd_print_feature(device_t dev, enum IvrsType ivhd_type, uint32_t feature) 
+ivhd_print_feature(device_t dev, enum IvrsType ivhd_type, uint32_t feature)
 {
 	switch (ivhd_type) {
 	case IVRS_TYPE_HARDWARE_LEGACY:
@@ -576,9 +576,9 @@ ivhd_print_ext_feature(device_t dev, uint64_t ext_feature)
 		"\020AttrFWSup"
 		"\021HDSup"
 		"\023InvIotlbSup",
-	    	REG_BITS(ext_high, 5, 0),
-	    	REG_BITS(ext_high, 8, 7),
-	    	REG_BITS(ext_high, 11, 10));
+		REG_BITS(ext_high, 5, 0),
+		REG_BITS(ext_high, 8, 7),
+		REG_BITS(ext_high, 11, 10));
 }
 
 static int
@@ -588,7 +588,7 @@ ivhd_print_cap(struct amdvi_softc *softc, ACPI_IVRS_HARDWARE1 * ivhd)
 	int max_ptp_level;
 
 	dev = softc->dev;
-	
+
 	ivhd_print_flag(dev, softc->ivhd_type, softc->ivhd_flag);
 	ivhd_print_feature(dev, softc->ivhd_type, softc->ivhd_feature);
 	ivhd_print_ext_feature(dev, softc->ext_feature);
@@ -600,7 +600,7 @@ ivhd_print_cap(struct amdvi_softc *softc, ACPI_IVRS_HARDWARE1 * ivhd)
 		return (EINVAL);
 	} else {
 		device_printf(softc->dev, "supported paging level:%d, will use only: %d\n",
-	    		max_ptp_level, amdvi_ptp_level);
+			max_ptp_level, amdvi_ptp_level);
 	}
 
 	device_printf(softc->dev, "device range: 0x%x - 0x%x\n",
@@ -618,7 +618,7 @@ ivhd_attach(device_t dev)
 	int status, unit;
 
 	unit = device_get_unit(dev);
-	KASSERT((unit < ivhd_count), 
+	KASSERT((unit < ivhd_count),
 		("ivhd unit %d > count %d", unit, ivhd_count));
 	/* Make sure its same device for which attach is called. */
 	KASSERT((ivhd_devs[unit] == dev),
@@ -633,12 +633,12 @@ ivhd_attach(device_t dev)
 	softc->pci_seg = ivhd->PciSegmentGroup;
 	softc->pci_rid = ivhd->Header.DeviceId;
 	softc->ivhd_flag = ivhd->Header.Flags;
-	/* 
+	/*
 	 * On lgeacy IVHD type(0x10), it is documented as feature
 	 * but in newer type it is attribute.
 	 */
 	softc->ivhd_feature = ivhd->FeatureReporting;
-	/* 
+	/*
 	 * PCI capability has more capabilities that are not part of IVRS.
 	 */
 	softc->cap_off = ivhd->CapabilityOffset;
@@ -669,7 +669,7 @@ ivhd_attach(device_t dev)
 
 	status = amdvi_setup_hw(softc);
 	if (status != 0) {
-		device_printf(dev, "couldn't be initialised, error=%d\n", 
+		device_printf(dev, "couldn't be initialised, error=%d\n",
 		    status);
 		return (status);
 	}
diff --git a/usr/src/uts/i86pc/io/vmm/amd/npt.c b/usr/src/uts/i86pc/io/vmm/amd/npt.c
index 862f6a0ecf..3f143a5d8f 100644
--- a/usr/src/uts/i86pc/io/vmm/amd/npt.c
+++ b/usr/src/uts/i86pc/io/vmm/amd/npt.c
@@ -61,28 +61,25 @@ svm_npt_init(int ipinum)
 	npt_flags = ipinum & NPT_IPIMASK;
 	TUNABLE_INT_FETCH("hw.vmm.npt.enable_superpage", &enable_superpage);
 	if (enable_superpage)
-		npt_flags |= PMAP_PDE_SUPERPAGE; 
-	
+		npt_flags |= PMAP_PDE_SUPERPAGE;
+
 	return (0);
 }
 
 static int
 npt_pinit(pmap_t pmap)
 {
-
 	return (pmap_pinit_type(pmap, PT_RVI, npt_flags));
 }
 
 struct vmspace *
 svm_npt_alloc(vm_offset_t min, vm_offset_t max)
 {
-	
 	return (vmspace_alloc(min, max, npt_pinit));
 }
 
 void
 svm_npt_free(struct vmspace *vmspace)
 {
-
 	vmspace_free(vmspace);
 }
diff --git a/usr/src/uts/i86pc/io/vmm/amd/npt.h b/usr/src/uts/i86pc/io/vmm/amd/npt.h
index 35530d7833..d90a1b14b2 100644
--- a/usr/src/uts/i86pc/io/vmm/amd/npt.h
+++ b/usr/src/uts/i86pc/io/vmm/amd/npt.h
@@ -31,7 +31,7 @@
 #ifndef _SVM_NPT_H_
 #define _SVM_NPT_H_
 
-int 	svm_npt_init(int ipinum);
+int	svm_npt_init(int ipinum);
 struct	vmspace *svm_npt_alloc(vm_offset_t min, vm_offset_t max);
 void	svm_npt_free(struct vmspace *vmspace);
 
diff --git a/usr/src/uts/i86pc/io/vmm/amd/svm.c b/usr/src/uts/i86pc/io/vmm/amd/svm.c
index e78d401e68..1046a54126 100644
--- a/usr/src/uts/i86pc/io/vmm/amd/svm.c
+++ b/usr/src/uts/i86pc/io/vmm/amd/svm.c
@@ -104,7 +104,7 @@ SYSCTL_NODE(_hw_vmm, OID_AUTO, svm, CTLFLAG_RW | CTLFLAG_MPSAFE, NULL,
 #define AMD_CPUID_SVM_PAUSE_FTH		BIT(12) /* Pause filter threshold */
 #define	AMD_CPUID_SVM_AVIC		BIT(13)	/* AVIC present */
 
-#define	VMCB_CACHE_DEFAULT	(VMCB_CACHE_ASID 	|	\
+#define	VMCB_CACHE_DEFAULT	(VMCB_CACHE_ASID	|	\
 				VMCB_CACHE_IOPM		|	\
 				VMCB_CACHE_I		|	\
 				VMCB_CACHE_TPR		|	\
@@ -139,7 +139,7 @@ SYSCTL_UINT(_hw_vmm_svm, OID_AUTO, num_asids, CTLFLAG_RDTUN, &nasid, 0,
 /* Current ASID generation for each host cpu */
 static struct asid asid[MAXCPU];
 
-/* 
+/*
  * SVM host state saved area of size 4KB for each core.
  */
 static uint8_t hsave[MAXCPU][PAGE_SIZE] __aligned(PAGE_SIZE);
@@ -154,14 +154,12 @@ static int svm_setreg(void *arg, int vcpu, int ident, uint64_t val);
 static __inline int
 flush_by_asid(void)
 {
-
 	return (svm_feature & AMD_CPUID_SVM_FLUSH_BY_ASID);
 }
 
 static __inline int
 decode_assist(void)
 {
-
 	return (svm_feature & AMD_CPUID_SVM_DECODE_ASSIST);
 }
 
@@ -307,7 +305,7 @@ svm_restore(void)
 {
 
 	svm_enable(NULL);
-}		
+}
 #else /* __FreeBSD__ */
 static int
 svm_cleanup(void)
@@ -335,14 +333,14 @@ svm_restore(void)
 #endif /* __FreeBSD__ */
 
 /* Pentium compatible MSRs */
-#define MSR_PENTIUM_START 	0	
-#define MSR_PENTIUM_END 	0x1FFF
+#define MSR_PENTIUM_START	0
+#define MSR_PENTIUM_END		0x1FFF
 /* AMD 6th generation and Intel compatible MSRs */
-#define MSR_AMD6TH_START 	0xC0000000UL	
-#define MSR_AMD6TH_END 		0xC0001FFFUL	
+#define MSR_AMD6TH_START	0xC0000000UL
+#define MSR_AMD6TH_END		0xC0001FFFUL
 /* AMD 7th and 8th generation compatible MSRs */
-#define MSR_AMD7TH_START 	0xC0010000UL	
-#define MSR_AMD7TH_END 		0xC0011FFFUL	
+#define MSR_AMD7TH_START	0xC0010000UL
+#define MSR_AMD7TH_END		0xC0011FFFUL
 
 /*
  * Get the index and bit position for a MSR in permission bitmap.
@@ -362,12 +360,12 @@ svm_msr_index(uint64_t msr, int *index, int *bit)
 		return (0);
 	}
 
-	base += (MSR_PENTIUM_END - MSR_PENTIUM_START + 1); 
+	base += (MSR_PENTIUM_END - MSR_PENTIUM_START + 1);
 	if (msr >= MSR_AMD6TH_START && msr <= MSR_AMD6TH_END) {
-		off = (msr - MSR_AMD6TH_START); 
+		off = (msr - MSR_AMD6TH_START);
 		*index = (off + base) / 4;
 		return (0);
-	} 
+	}
 
 	base += (MSR_AMD6TH_END - MSR_AMD6TH_START + 1);
 	if (msr >= MSR_AMD7TH_START && msr <= MSR_AMD7TH_END) {
@@ -985,7 +983,7 @@ svm_save_intinfo(struct svm_softc *svm_sc, int vcpu)
 	uint64_t intinfo;
 
 	ctrl  = svm_get_vmcb_ctrl(svm_sc, vcpu);
-	intinfo = ctrl->exitintinfo;	
+	intinfo = ctrl->exitintinfo;
 	if (!VMCB_EXITINTINFO_VALID(intinfo))
 		return;
 
@@ -1459,7 +1457,7 @@ svm_vmexit(struct svm_softc *svm_sc, int vcpu, struct vm_exit *vmexit)
 		eax = state->rax;
 		ecx = ctx->sctx_rcx;
 		edx = ctx->sctx_rdx;
-		retu = false;	
+		retu = false;
 
 		if (info1) {
 			vmm_stat_incr(svm_sc->vm, vcpu, VMEXIT_WRMSR, 1);
@@ -1970,7 +1968,7 @@ svm_dr_leave_guest(struct svm_regctx *gctx)
  * Start vcpu with specified RIP.
  */
 static int
-svm_vmrun(void *arg, int vcpu, register_t rip, pmap_t pmap, 
+svm_vmrun(void *arg, int vcpu, register_t rip, pmap_t pmap,
 	struct vm_eventinfo *evinfo)
 {
 	struct svm_regctx *gctx;
@@ -2124,7 +2122,7 @@ svm_vmrun(void *arg, int vcpu, register_t rip, pmap_t pmap,
 		/* Restore host LDTR. */
 		lldt(ldt_sel);
 
-		/* #VMEXIT disables interrupts so re-enable them here. */ 
+		/* #VMEXIT disables interrupts so re-enable them here. */
 		enable_gintr();
 
 		/* Update 'nextrip' */
diff --git a/usr/src/uts/i86pc/io/vmm/amd/svm_msr.c b/usr/src/uts/i86pc/io/vmm/amd/svm_msr.c
index 75502d3c8e..ea344165dd 100644
--- a/usr/src/uts/i86pc/io/vmm/amd/svm_msr.c
+++ b/usr/src/uts/i86pc/io/vmm/amd/svm_msr.c
@@ -72,7 +72,7 @@ static uint64_t host_msrs[HOST_MSR_NUM];
 void
 svm_msr_init(void)
 {
-	/* 
+	/*
 	 * It is safe to cache the values of the following MSRs because they
 	 * don't change based on curcpu, curproc or curthread.
 	 */
diff --git a/usr/src/uts/i86pc/io/vmm/amd/svm_softc.h b/usr/src/uts/i86pc/io/vmm/amd/svm_softc.h
index b5ac1903e7..0b996d0ab4 100644
--- a/usr/src/uts/i86pc/io/vmm/amd/svm_softc.h
+++ b/usr/src/uts/i86pc/io/vmm/amd/svm_softc.h
@@ -72,9 +72,9 @@ struct svm_vcpu {
 struct svm_softc {
 	uint8_t apic_page[VM_MAXCPU][PAGE_SIZE];
 	struct svm_vcpu vcpu[VM_MAXCPU];
-	vm_offset_t 	nptp;			    /* nested page table */
-	uint8_t		*iopm_bitmap;    /* shared by all vcpus */
-	uint8_t		*msr_bitmap;    /* shared by all vcpus */
+	vm_offset_t	nptp;		/* nested page table */
+	uint8_t		*iopm_bitmap;	/* shared by all vcpus */
+	uint8_t		*msr_bitmap;	/* shared by all vcpus */
 	struct vm	*vm;
 #ifndef __FreeBSD__
 	uint64_t	host_msrs[VM_MAXCPU][SVM_HOST_MSR_NUM];
diff --git a/usr/src/uts/i86pc/io/vmm/intel/ept.c b/usr/src/uts/i86pc/io/vmm/intel/ept.c
index dcc4e3c330..5e5253780e 100644
--- a/usr/src/uts/i86pc/io/vmm/intel/ept.c
+++ b/usr/src/uts/i86pc/io/vmm/intel/ept.c
@@ -157,7 +157,7 @@ ept_dump(uint64_t *ptp, int nlevels)
 
 		if (ptpval == 0)
 			continue;
-		
+
 		for (t = 0; t < tabs; t++)
 			printf("\t");
 		printf("%3d 0x%016lx\n", i, ptpval);
diff --git a/usr/src/uts/i86pc/io/vmm/intel/vmcs.c b/usr/src/uts/i86pc/io/vmm/intel/vmcs.c
index bb7ee45048..f1a08cc57d 100644
--- a/usr/src/uts/i86pc/io/vmm/intel/vmcs.c
+++ b/usr/src/uts/i86pc/io/vmm/intel/vmcs.c
@@ -388,7 +388,7 @@ vmcs_init(struct vmcs *vmcs)
 	cr0 = vmm_get_host_cr0();
 	if ((error = vmwrite(VMCS_HOST_CR0, cr0)) != 0)
 		goto done;
-	
+
 	cr4 = vmm_get_host_cr4() | CR4_VMXE;
 	if ((error = vmwrite(VMCS_HOST_CR4, cr4)) != 0)
 		goto done;
diff --git a/usr/src/uts/i86pc/io/vmm/intel/vmx.c b/usr/src/uts/i86pc/io/vmm/intel/vmx.c
index 8156121571..d07e57aa7f 100644
--- a/usr/src/uts/i86pc/io/vmm/intel/vmx.c
+++ b/usr/src/uts/i86pc/io/vmm/intel/vmx.c
@@ -117,7 +117,7 @@ __FBSDID("$FreeBSD$");
 	 PROCBASED_CR8_STORE_EXITING)
 #else
 /* We consider TSC offset a necessity for unsynched TSC handling */
-#define	PROCBASED_CTLS_ONE_SETTING 					\
+#define	PROCBASED_CTLS_ONE_SETTING					\
 	(PROCBASED_SECONDARY_CONTROLS	|				\
 	 PROCBASED_TSC_OFFSET		|				\
 	 PROCBASED_MWAIT_EXITING	|				\
diff --git a/usr/src/uts/i86pc/io/vmm/intel/vmx_msr.c b/usr/src/uts/i86pc/io/vmm/intel/vmx_msr.c
index 9121e46b40..6c37c9c234 100644
--- a/usr/src/uts/i86pc/io/vmm/intel/vmx_msr.c
+++ b/usr/src/uts/i86pc/io/vmm/intel/vmx_msr.c
@@ -451,7 +451,7 @@ vmx_wrmsr(struct vmx *vmx, int vcpuid, u_int num, uint64_t val, bool *retu)
 	uint64_t *guest_msrs;
 	uint64_t changed;
 	int error;
-	
+
 	guest_msrs = vmx->guest_msrs[vcpuid];
 	error = 0;
 
diff --git a/usr/src/uts/i86pc/io/vmm/intel/vtd.c b/usr/src/uts/i86pc/io/vmm/intel/vtd.c
index 41c2c5b2f8..50c0934ace 100644
--- a/usr/src/uts/i86pc/io/vmm/intel/vtd.c
+++ b/usr/src/uts/i86pc/io/vmm/intel/vtd.c
@@ -176,7 +176,7 @@ domain_id(void)
 		if (dom == NULL)
 			break;		/* found it */
 	}
-	
+
 	if (id >= max_domains)
 		panic("domain ids exhausted");
 
@@ -279,7 +279,7 @@ vtd_iotlb_global_invalidate(struct vtdmap *vtdmap)
 
 	offset = VTD_ECAP_IRO(vtdmap->ext_cap) * 16;
 	iotlb_reg = (volatile uint64_t *)((caddr_t)vtdmap + offset + 8);
-	
+
 	*iotlb_reg =  VTD_IIR_IVT | VTD_IIR_IIRG_GLOBAL |
 		      VTD_IIR_DRAIN_READS | VTD_IIR_DRAIN_WRITES;
 
@@ -851,7 +851,7 @@ static void
 vtd_destroy_domain(void *arg)
 {
 	struct domain *dom;
-	
+
 	dom = arg;
 
 	SLIST_REMOVE(&domhead, dom, domain, next);
diff --git a/usr/src/uts/i86pc/io/vmm/io/ppt.c b/usr/src/uts/i86pc/io/vmm/io/ppt.c
index a71ce86c2d..2f715bcc42 100644
--- a/usr/src/uts/i86pc/io/vmm/io/ppt.c
+++ b/usr/src/uts/i86pc/io/vmm/io/ppt.c
@@ -1321,7 +1321,7 @@ ppt_setup_msix(struct vm *vm, int vcpu, int pptfd, int idx, uint64_t addr,
 
 	/*
 	 * First-time configuration:
-	 * 	Allocate the MSI-X table
+	 *	Allocate the MSI-X table
 	 *	Allocate the IRQ resources
 	 *	Set up some variables in ppt->msix
 	 */
diff --git a/usr/src/uts/i86pc/io/vmm/io/vatpic.c b/usr/src/uts/i86pc/io/vmm/io/vatpic.c
index 817c815fd6..b81259647c 100644
--- a/usr/src/uts/i86pc/io/vmm/io/vatpic.c
+++ b/usr/src/uts/i86pc/io/vmm/io/vatpic.c
@@ -720,11 +720,11 @@ vatpic_master_handler(struct vm *vm, int vcpuid, bool in, uint16_t port,
 
 	if (bytes != 1)
 		return (-1);
- 
+
 	if (in) {
 		return (vatpic_read(vatpic, atpic, in, port, bytes, eax));
 	}
- 
+
 	return (vatpic_write(vatpic, atpic, in, port, bytes, eax));
 }
 
diff --git a/usr/src/uts/i86pc/io/vmm/io/vhpet.c b/usr/src/uts/i86pc/io/vmm/io/vhpet.c
index c82b4626bd..29e9188b77 100644
--- a/usr/src/uts/i86pc/io/vmm/io/vhpet.c
+++ b/usr/src/uts/i86pc/io/vmm/io/vhpet.c
@@ -61,10 +61,10 @@ static MALLOC_DEFINE(M_VHPET, "vhpet", "bhyve virtual hpet");
 #define	FS_PER_S	1000000000000000ul
 
 /* Timer N Configuration and Capabilities Register */
-#define	HPET_TCAP_RO_MASK	(HPET_TCAP_INT_ROUTE 	|		\
-				 HPET_TCAP_FSB_INT_DEL	|		\
-				 HPET_TCAP_SIZE		|		\
-				 HPET_TCAP_PER_INT)
+#define	HPET_TCAP_RO_MASK	(HPET_TCAP_INT_ROUTE	|	\
+				HPET_TCAP_FSB_INT_DEL	|	\
+				HPET_TCAP_SIZE		|	\
+				HPET_TCAP_PER_INT)
 /*
  * HPET requires at least 3 timers and up to 32 timers per block.
  */
@@ -242,7 +242,7 @@ vhpet_timer_interrupt(struct vhpet *vhpet, int n)
 		lapic_intr_msi(vhpet->vm, vhpet->timer[n].msireg >> 32,
 		    vhpet->timer[n].msireg & 0xffffffff);
 		return;
-	}	
+	}
 
 	pin = vhpet_timer_ioapic_pin(vhpet, n);
 	if (pin == 0) {
@@ -504,7 +504,7 @@ vhpet_mmio_write(void *vm, int vcpuid, uint64_t gpa, uint64_t val, int size,
 		if ((offset & 0x4) != 0) {
 			mask <<= 32;
 			data <<= 32;
-		} 
+		}
 		break;
 	default:
 		VM_CTR2(vhpet->vm, "hpet invalid mmio write: "
@@ -658,7 +658,7 @@ vhpet_mmio_read(void *vm, int vcpuid, uint64_t gpa, uint64_t *rval, int size,
 
 	if (offset == HPET_CAPABILITIES || offset == HPET_CAPABILITIES + 4) {
 		data = vhpet_capabilities();
-		goto done;	
+		goto done;
 	}
 
 	if (offset == HPET_CONFIG || offset == HPET_CONFIG + 4) {
diff --git a/usr/src/uts/i86pc/io/vmm/io/vhpet.h b/usr/src/uts/i86pc/io/vmm/io/vhpet.h
index 8e28241b32..e6ded31a66 100644
--- a/usr/src/uts/i86pc/io/vmm/io/vhpet.h
+++ b/usr/src/uts/i86pc/io/vmm/io/vhpet.h
@@ -40,7 +40,7 @@
 #define	VHPET_SIZE	1024
 
 struct vhpet *vhpet_init(struct vm *vm);
-void 	vhpet_cleanup(struct vhpet *vhpet);
+void	vhpet_cleanup(struct vhpet *vhpet);
 int	vhpet_mmio_write(void *vm, int vcpuid, uint64_t gpa, uint64_t val,
 	    int size, void *arg);
 int	vhpet_mmio_read(void *vm, int vcpuid, uint64_t gpa, uint64_t *val,
diff --git a/usr/src/uts/i86pc/io/vmm/io/vlapic.c b/usr/src/uts/i86pc/io/vmm/io/vlapic.c
index 60fc907b85..c1825f4264 100644
--- a/usr/src/uts/i86pc/io/vmm/io/vlapic.c
+++ b/usr/src/uts/i86pc/io/vmm/io/vlapic.c
@@ -164,7 +164,7 @@ void
 vlapic_id_write_handler(struct vlapic *vlapic)
 {
 	struct LAPIC *lapic;
-	
+
 	/*
 	 * We don't allow the ID register to be modified so reset it back to
 	 * its default value.
@@ -214,7 +214,7 @@ vlapic_get_ccr(struct vlapic *vlapic)
 	struct bintime bt_now, bt_rem;
 	struct LAPIC *lapic;
 	uint32_t ccr;
-	
+
 	ccr = 0;
 	lapic = vlapic->apic_page;
 
@@ -250,7 +250,7 @@ vlapic_dcr_write_handler(struct vlapic *vlapic)
 {
 	struct LAPIC *lapic;
 	int divisor;
-	
+
 	lapic = vlapic->apic_page;
 	VLAPIC_TIMER_LOCK(vlapic);
 
@@ -275,7 +275,7 @@ void
 vlapic_esr_write_handler(struct vlapic *vlapic)
 {
 	struct LAPIC *lapic;
-	
+
 	lapic = vlapic->apic_page;
 	lapic->esr = vlapic->esr_pending;
 	vlapic->esr_pending = 0;
@@ -333,7 +333,7 @@ static __inline uint32_t *
 vlapic_get_lvtptr(struct vlapic *vlapic, uint32_t offset)
 {
 	struct LAPIC	*lapic = vlapic->apic_page;
-	int 		 i;
+	int		i;
 
 	switch (offset) {
 	case APIC_OFFSET_CMCI_LVT:
@@ -405,9 +405,9 @@ vlapic_lvt_write_handler(struct vlapic *vlapic, uint32_t offset)
 	uint32_t *lvtptr, mask, val;
 	struct LAPIC *lapic;
 	int idx;
-	
+
 	lapic = vlapic->apic_page;
-	lvtptr = vlapic_get_lvtptr(vlapic, offset);	
+	lvtptr = vlapic_get_lvtptr(vlapic, offset);
 	val = *lvtptr;
 	idx = lvt_off_to_idx(offset);
 
@@ -635,7 +635,7 @@ static __inline int
 vlapic_periodic_timer(struct vlapic *vlapic)
 {
 	uint32_t lvt;
-	
+
 	lvt = vlapic_get_lvt(vlapic, APIC_OFFSET_TIMER_LVT);
 
 	return (vlapic_get_lvt_field(lvt, APIC_LVTT_TM_PERIODIC));
@@ -1110,7 +1110,7 @@ int
 vlapic_pending_intr(struct vlapic *vlapic, int *vecptr)
 {
 	struct LAPIC	*lapic = vlapic->apic_page;
-	int	  	 idx, i, bitpos, vector;
+	int		 idx, i, bitpos, vector;
 	uint32_t	*irrptr, val;
 
 	vlapic_update_ppr(vlapic);
@@ -1131,7 +1131,7 @@ vlapic_pending_intr(struct vlapic *vlapic, int *vecptr)
 				if (vecptr != NULL)
 					*vecptr = vector;
 				return (1);
-			} else 
+			} else
 				break;
 		}
 	}
@@ -1149,7 +1149,7 @@ vlapic_intr_accepted(struct vlapic *vlapic, int vector)
 		return ((*vlapic->ops.intr_accepted)(vlapic, vector));
 
 	/*
-	 * clear the ready bit for vector being accepted in irr 
+	 * clear the ready bit for vector being accepted in irr
 	 * and set the vector as in service in isr.
 	 */
 	idx = (vector / 32) * 4;
@@ -1240,7 +1240,7 @@ vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 		*data = 0;
 		goto done;
 	}
-	
+
 	offset &= ~3;
 	switch(offset)
 	{
@@ -1289,17 +1289,17 @@ vlapic_read(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 		case APIC_OFFSET_ESR:
 			*data = lapic->esr;
 			break;
-		case APIC_OFFSET_ICR_LOW: 
+		case APIC_OFFSET_ICR_LOW:
 			*data = lapic->icr_lo;
 			if (x2apic(vlapic))
 				*data |= (uint64_t)lapic->icr_hi << 32;
 			break;
-		case APIC_OFFSET_ICR_HI: 
+		case APIC_OFFSET_ICR_HI:
 			*data = lapic->icr_hi;
 			break;
 		case APIC_OFFSET_CMCI_LVT:
 		case APIC_OFFSET_TIMER_LVT ... APIC_OFFSET_ERROR_LVT:
-			*data = vlapic_get_lvt(vlapic, offset);	
+			*data = vlapic_get_lvt(vlapic, offset);
 #ifdef INVARIANTS
 			reg = vlapic_get_lvtptr(vlapic, offset);
 			KASSERT(*data == *reg, ("inconsistent lvt value at "
@@ -1394,7 +1394,7 @@ vlapic_write(struct vlapic *vlapic, int mmio_access, uint64_t offset,
 			lapic->svr = data;
 			vlapic_svr_write_handler(vlapic);
 			break;
-		case APIC_OFFSET_ICR_LOW: 
+		case APIC_OFFSET_ICR_LOW:
 			lapic->icr_lo = data;
 			if (x2apic(vlapic))
 				lapic->icr_hi = data >> 32;
@@ -1448,7 +1448,7 @@ static void
 vlapic_reset(struct vlapic *vlapic)
 {
 	struct LAPIC *lapic;
-	
+
 	lapic = vlapic->apic_page;
 	bzero(lapic, sizeof(struct LAPIC));
 
diff --git a/usr/src/uts/i86pc/io/vmm/io/vrtc.c b/usr/src/uts/i86pc/io/vmm/io/vrtc.c
index 7a98cd75ad..343ad9c37a 100644
--- a/usr/src/uts/i86pc/io/vmm/io/vrtc.c
+++ b/usr/src/uts/i86pc/io/vmm/io/vrtc.c
@@ -359,7 +359,7 @@ rtc_to_secs(struct vrtc *vrtc)
 
 	/*
 	 * Ignore 'rtc->dow' because some guests like Linux don't bother
-	 * setting it at all while others like OpenBSD/i386 set it incorrectly. 
+	 * setting it at all while others like OpenBSD/i386 set it incorrectly.
 	 *
 	 * clock_ct_to_ts() does not depend on 'ct.dow' anyways so ignore it.
 	 */
diff --git a/usr/src/uts/i86pc/io/vmm/vmm.c b/usr/src/uts/i86pc/io/vmm/vmm.c
index f4c22c13dd..7a47cd0cd1 100644
--- a/usr/src/uts/i86pc/io/vmm/vmm.c
+++ b/usr/src/uts/i86pc/io/vmm/vmm.c
@@ -109,7 +109,7 @@ struct vlapic;
  * (x) initialized before use
  */
 struct vcpu {
-	struct mtx 	mtx;		/* (o) protects 'state' and 'hostcpu' */
+	struct mtx	mtx;		/* (o) protects 'state' and 'hostcpu' */
 	enum vcpu_state	state;		/* (o) vcpu state */
 #ifndef __FreeBSD__
 	kcondvar_t	vcpu_cv;	/* (o) cpu waiter cv */
@@ -186,7 +186,7 @@ struct vm {
 	volatile cpuset_t active_cpus;		/* (i) active vcpus */
 	volatile cpuset_t debug_cpus;		/* (i) vcpus stopped for debug */
 	int		suspend;		/* (i) stop VM execution */
-	volatile cpuset_t suspended_cpus; 	/* (i) suspended vcpus */
+	volatile cpuset_t suspended_cpus;	/* (i) suspended vcpus */
 	volatile cpuset_t halted_cpus;		/* (x) cpus in a hard halt */
 	struct mem_map	mem_maps[VM_MAX_MEMMAPS]; /* (i) guest address space */
 	struct mem_seg	mem_segs[VM_MAX_MEMSEGS]; /* (o) guest memory regions */
@@ -1222,7 +1222,6 @@ vm_set_register(struct vm *vm, int vcpuid, int reg, uint64_t val)
 static bool
 is_descriptor_table(int reg)
 {
-
 	switch (reg) {
 	case VM_REG_GUEST_IDTR:
 	case VM_REG_GUEST_GDTR:
@@ -1235,7 +1234,6 @@ is_descriptor_table(int reg)
 static bool
 is_segment_register(int reg)
 {
-	
 	switch (reg) {
 	case VM_REG_GUEST_ES:
 	case VM_REG_GUEST_CS:
@@ -2916,7 +2914,7 @@ vmm_is_pptdev(int bus, int slot, int func)
 				found = true;
 				break;
 			}
-		
+
 			if (cp2 != NULL)
 				*cp2++ = ' ';
 
@@ -3326,7 +3324,7 @@ vm_copyin(struct vm *vm, int vcpuid, struct vm_copyinfo *copyinfo, void *kaddr,
 {
 	char *dst;
 	int idx;
-	
+
 	dst = kaddr;
 	idx = 0;
 	while (len > 0) {
@@ -3367,8 +3365,8 @@ vm_get_rescnt(struct vm *vm, int vcpu, struct vmm_stat_type *stat)
 
 	if (vcpu == 0) {
 		vmm_stat_set(vm, vcpu, VMM_MEM_RESIDENT,
-	       	    PAGE_SIZE * vmspace_resident_count(vm->vmspace));
-	}	
+		    PAGE_SIZE * vmspace_resident_count(vm->vmspace));
+	}
 }
 
 static void
@@ -3377,8 +3375,8 @@ vm_get_wiredcnt(struct vm *vm, int vcpu, struct vmm_stat_type *stat)
 
 	if (vcpu == 0) {
 		vmm_stat_set(vm, vcpu, VMM_MEM_WIRED,
-	      	    PAGE_SIZE * pmap_wired_count(vmspace_pmap(vm->vmspace)));
-	}	
+		    PAGE_SIZE * pmap_wired_count(vmspace_pmap(vm->vmspace)));
+	}
 }
 
 VMM_STAT_FUNC(VMM_MEM_RESIDENT, "Resident memory", vm_get_rescnt);
diff --git a/usr/src/uts/i86pc/io/vmm/vmm_mem.c b/usr/src/uts/i86pc/io/vmm/vmm_mem.c
index a736d94bba..cd894dc84d 100644
--- a/usr/src/uts/i86pc/io/vmm/vmm_mem.c
+++ b/usr/src/uts/i86pc/io/vmm/vmm_mem.c
@@ -100,7 +100,7 @@ vmm_mmio_alloc(struct vmspace *vmspace, vm_paddr_t gpa, size_t len,
 	 * has incremented the reference count on the sglist. Dropping the
 	 * initial reference count ensures that the sglist will be freed
 	 * when the object is deallocated.
-	 * 
+	 *
 	 * If the object could not be allocated then we end up freeing the
 	 * sglist.
 	 */
diff --git a/usr/src/uts/i86pc/io/vmm/vmm_sol_glue.c b/usr/src/uts/i86pc/io/vmm/vmm_sol_glue.c
index 2401774ab7..4dcaba8a82 100644
--- a/usr/src/uts/i86pc/io/vmm/vmm_sol_glue.c
+++ b/usr/src/uts/i86pc/io/vmm/vmm_sol_glue.c
@@ -572,7 +572,7 @@ vmm_sol_glue_cleanup(void)
  */
 
 #define	FEBRUARY	2
-#define	days_in_year(y) 	(leapyear(y) ? 366 : 365)
+#define	days_in_year(y)		(leapyear(y) ? 366 : 365)
 #define	days_in_month(y, m) \
 	(month_days[(m) - 1] + (m == FEBRUARY ? leapyear(y) : 0))
 /* Day of week. Days are counted from 1/1/1970, which was a Thursday */
@@ -644,7 +644,7 @@ clock_ct_to_ts(struct clocktime *ct, struct timespec *ts)
 
 	/* Months */
 	for (i = 1; i < ct->mon; i++)
-	  	days += days_in_month(year, i);
+		days += days_in_month(year, i);
 	days += (ct->day - 1);
 
 	ts->tv_sec = (((time_t)days * 24 + ct->hour) * 60 + ct->min) * 60 +
diff --git a/usr/src/uts/i86pc/io/vmm/vmm_stat.h b/usr/src/uts/i86pc/io/vmm/vmm_stat.h
index bfe35e9f67..a214ba0fe9 100644
--- a/usr/src/uts/i86pc/io/vmm/vmm_stat.h
+++ b/usr/src/uts/i86pc/io/vmm/vmm_stat.h
@@ -73,7 +73,7 @@ void	vmm_stat_register(void *arg);
 	};								\
 	SYSINIT(type##_stat, SI_SUB_KLD, SI_ORDER_ANY, vmm_stat_register, type)
 
-#define VMM_STAT_DEFINE(type, nelems, desc, scope) 			\
+#define	VMM_STAT_DEFINE(type, nelems, desc, scope)			\
 	VMM_STAT_FDEFINE(type, nelems, desc, NULL, scope)
 
 #define	VMM_STAT_DECLARE(type)						\
@@ -94,7 +94,7 @@ void	vmm_stat_register(void *arg);
 
 void	*vmm_stat_alloc(void);
 void	vmm_stat_init(void *vp);
-void 	vmm_stat_free(void *vp);
+void	vmm_stat_free(void *vp);
 
 /*
  * 'buf' should be at least fit 'MAX_VMM_STAT_TYPES' entries
@@ -108,7 +108,7 @@ vmm_stat_array_incr(struct vm *vm, int vcpu, struct vmm_stat_type *vst,
 {
 #ifdef VMM_KEEP_STATS
 	uint64_t *stats;
-	
+
 	stats = vcpu_stats(vm, vcpu);
 
 	if (vst->index >= 0 && statidx < vst->nelems)
@@ -122,7 +122,7 @@ vmm_stat_array_set(struct vm *vm, int vcpu, struct vmm_stat_type *vst,
 {
 #ifdef VMM_KEEP_STATS
 	uint64_t *stats;
-	
+
 	stats = vcpu_stats(vm, vcpu);
 
 	if (vst->index >= 0 && statidx < vst->nelems)
diff --git a/usr/src/uts/i86pc/sys/vmm_dev.h b/usr/src/uts/i86pc/sys/vmm_dev.h
index 4e89b712dc..090e82ed29 100644
--- a/usr/src/uts/i86pc/sys/vmm_dev.h
+++ b/usr/src/uts/i86pc/sys/vmm_dev.h
@@ -199,7 +199,7 @@ struct vm_suspend {
 
 struct vm_gla2gpa {
 	int		vcpuid;		/* inputs */
-	int 		prot;		/* PROT_READ or PROT_WRITE */
+	int		prot;		/* PROT_READ or PROT_WRITE */
 	uint64_t	gla;
 	struct vm_guest_paging paging;
 	int		fault;		/* outputs */
@@ -307,8 +307,8 @@ _Static_assert(sizeof(struct vm_readwrite_kernemu_device) == 24, "ABI");
 #define	VM_GET_MEMSEG			(VMM_IOC_BASE | 0x02)
 #define	VM_MMAP_GETNEXT			(VMM_IOC_BASE | 0x03)
 
-#define	VM_LAPIC_IRQ 			(VMM_IOC_BASE | 0x04)
-#define	VM_LAPIC_LOCAL_IRQ 		(VMM_IOC_BASE | 0x05)
+#define	VM_LAPIC_IRQ			(VMM_IOC_BASE | 0x04)
+#define	VM_LAPIC_LOCAL_IRQ		(VMM_IOC_BASE | 0x05)
 #define	VM_LAPIC_MSI			(VMM_IOC_BASE | 0x06)
 
 #define	VM_IOAPIC_ASSERT_IRQ		(VMM_IOC_BASE | 0x07)