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| author | Patrick Mooney <pmooney@pfmooney.com> | 2020-07-29 22:37:40 +0000 |
|---|---|---|
| committer | Patrick Mooney <pmooney@oxide.computer> | 2020-07-30 18:25:58 +0000 |
| commit | da2b26b186539432c4bee88ce2f08f41574e009f (patch) | |
| tree | 94971e29524b2f8d040b74a2367659f2131c0035 | |
| parent | 84b52440bb17285d25cdba822f4ed46754e76f37 (diff) | |
| download | illumos-joyent-da2b26b186539432c4bee88ce2f08f41574e009f.tar.gz | |
12999 MSR_AMD_DE_CFG is twice defined
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Approved by: Dan McDonald <danmcd@joyent.com>
| -rw-r--r-- | usr/src/uts/i86pc/os/cpuid.c | 14 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/controlregs.h | 8 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/x86_archext.h | 7 |
3 files changed, 14 insertions, 15 deletions
diff --git a/usr/src/uts/i86pc/os/cpuid.c b/usr/src/uts/i86pc/os/cpuid.c index 059930352b..461db5226f 100644 --- a/usr/src/uts/i86pc/os/cpuid.c +++ b/usr/src/uts/i86pc/os/cpuid.c @@ -2746,8 +2746,8 @@ cpuid_use_amd_retpoline(struct cpuid_info *cpi) /* * We need to determine whether or not lfence is serializing. It always * is on families 0xf and 0x11. On others, it's controlled by - * MSR_AMD_DECODE_CONFIG (MSRC001_1029). If some hypervisor gives us a - * crazy old family, don't try and do anything. + * MSR_AMD_DE_CFG (MSRC001_1029). If some hypervisor gives us a crazy + * old family, don't try and do anything. */ if (cpi->cpi_family < 0xf) return (B_FALSE); @@ -2762,16 +2762,16 @@ cpuid_use_amd_retpoline(struct cpuid_info *cpi) * for it. */ if (!on_trap(&otd, OT_DATA_ACCESS)) { - val = rdmsr(MSR_AMD_DECODE_CONFIG); - val |= AMD_DECODE_CONFIG_LFENCE_DISPATCH; - wrmsr(MSR_AMD_DECODE_CONFIG, val); - val = rdmsr(MSR_AMD_DECODE_CONFIG); + val = rdmsr(MSR_AMD_DE_CFG); + val |= AMD_DE_CFG_LFENCE_DISPATCH; + wrmsr(MSR_AMD_DE_CFG, val); + val = rdmsr(MSR_AMD_DE_CFG); } else { val = 0; } no_trap(); - if ((val & AMD_DECODE_CONFIG_LFENCE_DISPATCH) != 0) + if ((val & AMD_DE_CFG_LFENCE_DISPATCH) != 0) return (B_TRUE); return (B_FALSE); } diff --git a/usr/src/uts/intel/sys/controlregs.h b/usr/src/uts/intel/sys/controlregs.h index 0be7b3b650..9c02a4b809 100644 --- a/usr/src/uts/intel/sys/controlregs.h +++ b/usr/src/uts/intel/sys/controlregs.h @@ -238,9 +238,15 @@ extern "C" { #define AMD_BU_CFG_E298 (UINT64_C(1) << 1) +/* + * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction + * decoding. Most notably, for the AMD variant of retpolines, we must improve + * the serializability of lfence for the lfence based method to work. + */ #define MSR_AMD_DE_CFG 0xc0011029 -#define AMD_DE_CFG_E721 (UINT64_C(1)) +#define AMD_DE_CFG_E721 (1UL << 0) +#define AMD_DE_CFG_LFENCE_DISPATCH (1UL << 1) /* AMD's osvw MSRs */ #define MSR_AMD_OSVW_ID_LEN 0xc0010140 diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h index 0c20330297..f5e4a4b153 100644 --- a/usr/src/uts/intel/sys/x86_archext.h +++ b/usr/src/uts/intel/sys/x86_archext.h @@ -603,13 +603,6 @@ extern "C" { #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000 -/* - * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction - * decoding. Most notably, for the AMD variant of retpolines, we must improve - * the serializability of lfence for the lfence based method to work. - */ -#define MSR_AMD_DECODE_CONFIG 0xc0011029 -#define AMD_DECODE_CONFIG_LFENCE_DISPATCH 0x02 #define MCI_CTL_VALUE 0xffffffff |