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| author | Bill Taylor <William.Taylor@Oracle.COM> | 2010-07-29 22:10:26 -0700 |
|---|---|---|
| committer | Bill Taylor <William.Taylor@Oracle.COM> | 2010-07-29 22:10:26 -0700 |
| commit | 17a2b317610f531d565bf4e940433aab2d9e6985 (patch) | |
| tree | 2fac484854d5b188df9db68683b15c91bae78f4b /usr/src/uts/common/sys | |
| parent | e7236f70bdab68b00ddef7b22dc58fcdb7875deb (diff) | |
| download | illumos-joyent-17a2b317610f531d565bf4e940433aab2d9e6985.tar.gz | |
PSARC/2010/234 IBTF 2010.Q2 Enhancements
6538821 add Base Memory Management to ibtl and hermon
6893126 Add OFED ib_get_dma_mr() equivalent memory registration interface to IBTF
6937574 move FMANOTE messages to msgbuf or ibtf buf only
6954821 Expose IB interrupt handles and device info for perf optimization
6955695 IBTF V4 interfaces
Diffstat (limited to 'usr/src/uts/common/sys')
23 files changed, 2091 insertions, 553 deletions
diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon.h index 7ffef9b05f..88496c21df 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon.h @@ -64,6 +64,7 @@ #include <sys/ib/adapters/hermon/hermon_cmd.h> #include <sys/ib/adapters/hermon/hermon_cq.h> #include <sys/ib/adapters/hermon/hermon_event.h> +#include <sys/ib/adapters/hermon/hermon_fcoib.h> #include <sys/ib/adapters/hermon/hermon_ioctl.h> #include <sys/ib/adapters/hermon/hermon_misc.h> #include <sys/ib/adapters/hermon/hermon_mr.h> @@ -99,7 +100,7 @@ extern "C" { #define HERMON_ONCLOSE_FLASH_INPROGRESS (1 << 0) -#define HERMON_MSIX_MAX 8 /* max # of interrupt vectors */ +#define HERMON_MSIX_MAX 256 /* max # of interrupt vectors */ /* * VPD header size - or more rightfully, the area of interest for fwflash @@ -139,17 +140,16 @@ extern "C" { /* * Macro used to output HCA warning messages. Note: HCA warning messages * are only generated when an unexpected condition has been detected. This - * can be the result of a software bug or some other problem, but it is more - * often an indication that the HCA firmware (and/or hardware) has done - * something unexpected. This warning message means that the driver state - * in unpredictable and that shutdown/restart is suggested. + * can be the result of a software bug or some other problem. Previously + * this was used for hardware errors, but those now use HERMON_FMANOTE + * instead, indicating that the driver state is more likely in an + * unpredictable state, and that shutdown/restart is suggested. + * + * HERMON_WARNING messages are not considered important enough to print + * to the console, just to the message log. */ #define HERMON_WARNING(state, string) \ - cmn_err(CE_WARN, "hermon%d: %s\n", (state)->hs_instance, string) - - -#define HERMON_NOTE(state, string) \ - cmn_err(CE_CONT, "hermon%d: %s\n", (state)->hs_instance, string) + cmn_err(CE_CONT, "!hermon%d: %s\n", (state)->hs_instance, string) /* * Macro used to set attach failure messages. Also, the attach message buf @@ -352,27 +352,17 @@ _NOTE(MUTEX_PROTECTS_DATA(hermon_cmd_reg_t::hcr_lock, struct hermon_state_s { dev_info_t *hs_dip; int hs_instance; -int hs_debug; /* for debug, a way of tracing */ -uint32_t hs_debug_lev; /* for controlling prints, a bit mask */ - /* see hermon.c for setting it */ + /* PCI device, vendor, and revision IDs */ uint16_t hs_vendor_id; uint16_t hs_device_id; uint8_t hs_revision_id; -struct hermon_hw_qpc_s hs_debug_qpc; -struct hermon_hw_cqc_s hs_debug_cqc; -struct hermon_hw_eqc_s hs_debug_eqc; - - hermon_hw_sm_perfcntr_t hs_debug_perf; - - /* * DMA information for the InfiniHost Context Memory (ICM), * ICM Auxiliary allocation and the firmware. Also, record * of ICM and ICMA sizes, in bytes. */ - /* JBDB -- store here hs_icm_table, with hs_icm_dma in */ uint64_t hs_icm_sz; hermon_icm_table_t *hs_icm; @@ -389,9 +379,17 @@ struct hermon_hw_eqc_s hs_debug_eqc; ddi_intr_handle_t hs_intrmsi_hdl[HERMON_MSIX_MAX]; uint_t hs_intrmsi_pri; int hs_intrmsi_cap; + ddi_cb_handle_t hs_intr_cb_hdl; - /* assign EQs to CQs in a round robin fashion */ - uint_t hs_eq_dist; /* increment when used */ + /* Do not use reserved EQs */ + uint_t hs_rsvd_eqs; + uint_t hs_cq_erreqnum; + + /* cq_sched data */ + kmutex_t hs_cq_sched_lock; + hermon_cq_sched_t *hs_cq_sched_array; + hermon_cq_sched_t hs_cq_sched_default; + uint_t hs_cq_sched_array_size; /* hermon HCA name and HCA part number */ char hs_hca_name[64]; @@ -555,9 +553,6 @@ struct hermon_hw_eqc_s hs_debug_eqc; */ hermon_pdhdl_t hs_pdhdl_internal; hermon_eqhdl_t hs_eqhdl[HERMON_NUM_EQ]; - hermon_cqhdl_t *hs_cqhdl; - hermon_qphdl_t *hs_qphdl; - hermon_srqhdl_t *hs_srqhdl; kmutex_t hs_dbr_lock; /* lock for dbr mgmt */ /* linked list of kernel dbr resources */ @@ -706,6 +701,10 @@ struct hermon_hw_eqc_s hs_debug_eqc; mod_hash_t *hs_fm_test_hash; /* testset */ mod_hash_t *hs_fm_id_hash; /* testid */ #endif + /* FCoIB data */ + hermon_fcoib_t hs_fcoib; + boolean_t hs_fcoib_may_be_running; /* cq_poll test */ + /* * Hermon fastreboot support. To sw-reset Hermon HCA, the driver * needs to save/restore MSI-X tables and PBA. Those members are @@ -889,7 +888,7 @@ typedef struct hermon_devmap_track_s { #define HERMON_ICM_SPLIT 64 #define HERMON_ICM_SPAN 4096 -#define hermon_bitmap(bitmap, dma_info, icm_table, split_index) \ +#define hermon_bitmap(bitmap, dma_info, icm_table, split_index, num_to_hdl) \ bitmap = (icm_table)->icm_bitmap[split_index]; \ if (bitmap == NULL) { \ _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*(icm_table))) \ @@ -901,6 +900,12 @@ typedef struct hermon_devmap_track_s { (icm_table)->icm_dma[split_index] = \ kmem_zalloc(num_spans * sizeof (hermon_dma_info_t), \ KM_SLEEP); \ + if (num_to_hdl) { \ + ASSERT((icm_table)->num_to_hdl[split_index] == NULL); \ + (icm_table)->num_to_hdl[split_index] = \ + kmem_zalloc(num_spans * \ + sizeof (void **), KM_SLEEP); \ + } \ } \ dma_info = (icm_table)->icm_dma[split_index] @@ -934,9 +939,10 @@ struct hermon_icm_table_s { uint32_t rsrc_mask; uint16_t log_num_entries; uint16_t log_object_size; - /* two arrays of pointers, each pointer points to arrays */ + /* three arrays of pointers, each pointer points to arrays */ uint8_t *icm_bitmap[HERMON_ICM_SPLIT]; hermon_dma_info_t *icm_dma[HERMON_ICM_SPLIT]; + void ***num_to_hdl[HERMON_ICM_SPLIT]; /* qp/cq/srq */ }; /* * Split the rsrc index into three pieces: @@ -959,6 +965,10 @@ int hermon_icm_alloc(hermon_state_t *state, hermon_rsrc_type_t type, uint32_t icm_index1, uint32_t icm_index2); void hermon_icm_free(hermon_state_t *state, hermon_rsrc_type_t type, uint32_t icm_index1, uint32_t icm_index2); +void *hermon_icm_num_to_hdl(hermon_state_t *state, hermon_rsrc_type_t type, + uint32_t idx); +void hermon_icm_set_num_to_hdl(hermon_state_t *state, hermon_rsrc_type_t type, + uint32_t idx, void *hdl); int hermon_device_mode(hermon_state_t *state); /* Defined in hermon_umap.c */ diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_cmd.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_cmd.h index e2a4ce84ac..50a041d3d3 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_cmd.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_cmd.h @@ -20,8 +20,7 @@ */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_ADAPTERS_HERMON_CMD_H @@ -149,10 +148,13 @@ extern "C" { #define SW2HW_SRQ 0x35 #define HW2SW_SRQ 0x36 #define QUERY_SRQ 0x37 -/* new in hermon, replaces part of modifyMPT */ +/* new in hermon, replaces part of modify MPT */ #define RESIZE_SRQ 0X44 /* new in hermon, set limit water mark */ #define ARM_RQ 0X40 +/* new in hermon (PRM 0.36) configure interrupt moderation */ +#define CONFIG_INT_MOD 0X45 +#define HW_HEALTH_CHECK 0X50 /* Multicast Group Commands */ #define READ_MGM 0x25 @@ -167,6 +169,14 @@ extern "C" { #define DIAG_RPRT 0x30 #define CMD_NOP 0x31 +#define SET_VLAN_FLTR 0x47 +#define SET_MCAST_FLTR 0x48 + +#define CONFIG_FC 0x4A +#define QUERY_FC 0x4B +#define HEART_BEAT_RQ 0x4C + +#define SENSE_PORT 0x4D /* ICM and related commands - w/out LAM commands from Arbel */ #define RUN_FW 0xFF6 @@ -182,7 +192,6 @@ extern "C" { * Commands mentioned but not defined in PRM v35 * REL_ICM_AUX * INIT_VM - * HEART_BEAT_RQ */ /* @@ -731,6 +740,7 @@ int hermon_cmn_qp_cmd_post(hermon_state_t *state, uint_t opcode, * commands: * QUERY_DEV_LIM/CAP, QUERY_FW, QUERY_ADAPTER, QUERY_HCA, QUERY_MPT, * QUERY_EQ, QUERY_CQ, and QUERY_QP. + * New with FCoIB, QUERY_FC */ int hermon_cmn_query_cmd_post(hermon_state_t *state, uint_t opcode, uint_t opmod, uint_t queryindx, void *query, uint_t size, uint_t sleepflag); @@ -800,6 +810,12 @@ int hermon_conf_special_qp_cmd_post(hermon_state_t *state, uint_t qpindx, uint_t qptype, uint_t sleepflag, uint_t opmod); /* + * Get FEXCH HEART BEAT + */ +int hermon_get_heart_beat_rq_cmd_post(hermon_state_t *state, uint_t qpindx, + uint64_t *outparm); + +/* * MGID_HASH, READ_MGM, and WRITE_MGM - used for manipulation of the * hardware resource tables for multicast groups. * NOTE: for intial implementation these functions retain their original @@ -833,7 +849,6 @@ int hermon_modify_mpt_cmd_post(hermon_state_t *state, hermon_hw_dmpt_t *mpt, * to resize the SRQ, by passing the new information in the same format as * the original srqc, which the HCA will update appropriately */ - int hermon_resize_srq_cmd_post(hermon_state_t *state, hermon_hw_srqc_t *srq, uint_t srqnum, uint_t sleepflag); @@ -842,12 +857,40 @@ int hermon_resize_srq_cmd_post(hermon_state_t *state, hermon_hw_srqc_t *srq, */ int hermon_nop_post(hermon_state_t *state, uint_t interval, uint_t sleep); int hermon_setdebug_post(hermon_state_t *state); + /* * READ_MTT - used to read an mtt entry at address. */ int hermon_read_mtt_cmd_post(hermon_state_t *state, uint64_t mtt_addr, hermon_hw_mtt_t *mtt); +/* + * SENSE_PORT - used to send protocol running on a port + */ +int hermon_sense_port_post(hermon_state_t *state, uint_t portnum, + uint32_t *protocol); + +/* + * CONFIG_FC - used to do either a basic config passing in + * *hermon_hw_config_fc_basic_s, or config the N_Port table. + * passing in pointer to an array of 32-bit id's + * Note that either one needs to be cast to void * + */ +int hermon_config_fc_cmd_post(hermon_state_t *state, void *cfginfo, int enable, + int selector, int n_ports, int portnum, uint_t sleepflag); + +/* + * CONFIG_INT_MOD - used to configure INTERRUPT moderation + */ +int hermon_config_int_mod(hermon_state_t *state, uint_t min_delay, + uint_t vector); + +/* + * HW_HEALTH_CHECK - tests state of the HCA + * if command fails, *health is invalid/undefined + */ +int hermon_hw_health_check(hermon_state_t *state, int *health); + #ifdef __cplusplus } #endif diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_cq.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_cq.h index cb6a405615..72c47b8644 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_cq.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_cq.h @@ -20,8 +20,7 @@ */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_ADAPTERS_HERMON_CQ_H @@ -57,18 +56,10 @@ extern "C" { * The following defines the default number of Completion Queues. This * is controllable via the "hermon_log_num_cq" configuration variable. * We also have a define for the minimum size of a CQ. CQs allocated - * with size 0, 1, 2, or 3 will always get back a CQ of size 4. - */ -#define HERMON_NUM_CQ_SHIFT 0x10 -/* - * #define HERMON_CQ_MIN_SIZE 0x3 - */ - -/* - * #define HERMON_CQ_MIN_SIZE 0xFF testing, try min 1 page + * with size "less than a page" will always get back a page. */ +#define HERMON_NUM_CQ_SHIFT 0x12 -/* page div 32 (cqe size) minus 1, for min size */ #define HERMON_CQ_MIN_SIZE ((PAGESIZE / 32) - 1) /* @@ -97,7 +88,7 @@ extern "C" { * the associated QP. */ #define HERMON_CQE_SND_NOP 0x0 -#define HERMON_CQE_SND_SND_INV 0x1 +#define HERMON_CQE_SND_SEND_INV 0x1 #define HERMON_CQE_SND_RDMAWR 0x8 #define HERMON_CQE_SND_RDMAWR_IMM 0x9 #define HERMON_CQE_SND_SEND 0xA @@ -116,7 +107,7 @@ extern "C" { #define HERMON_CQE_RCV_RDMAWR_IMM 0x00 #define HERMON_CQE_RCV_SEND 0x01 #define HERMON_CQE_RCV_SEND_IMM 0x02 -#define HERMON_CQE_RCV_SND_INV 0x03 +#define HERMON_CQE_RCV_SEND_INV 0x03 #define HERMON_CQE_RCV_ERROR_CODE 0x1E #define HERMON_CQE_RCV_RESIZE_CODE 0x16 @@ -124,25 +115,56 @@ extern "C" { /* Define for maximum CQ number mask (CQ number is 24 bits) */ #define HERMON_CQ_MAXNUMBER_MSK 0xFFFFFF +/* + * CQ Sched Management + * + * Each hermon_cq_sched struct defines a range of cq handler_id's + * assigned to the cq_sched instance. Also, the "next_alloc" + * member is used to allocate handler_id's in a round robin fashion. + * + * Valid cq handler_id's are in the range of 1 to hs_intrmsi_allocd. + * They are indexes into the hs_intrmsi_hdl array. + */ +#define HERMON_CQH_MAX 32 +typedef struct hermon_cq_sched_s { + char cqs_name[HERMON_CQH_MAX]; + uint_t cqs_start_hid; + uint_t cqs_len; + uint_t cqs_next_alloc; + uint_t cqs_desired; + uint_t cqs_minimum; + uint_t cqs_refcnt; /* could be alloc'ed more than once */ +} hermon_cq_sched_t; /* * new EQ mgmt - per domain (when it gets there). - * The first N are for CQ Completions. Following that are: + * The first hs_rsvd_eqs are reserved by the firmware. + * The next hs_intrmsi_allocd are for CQ Completions. + * Each of these "completion" EQs has a unique interrupt vector. + * The EQs following that are: * * 1 for CQ Errors * 1 for Asyncs and Command Completions, and finally * 1 for All Other events. * - * hs_intrmsi_allocd is the N in the above. + * share the last of the interrupt vectors. */ +#define HERMON_CQSCHED_NEXT_HID(cq_schedp) \ + ((atomic_inc_uint_nv(&(cq_schedp)->cqs_next_alloc) % \ + (cq_schedp)->cqs_len) + (cq_schedp)->cqs_start_hid) + +#define HERMON_HID_TO_EQNUM(state, hid) \ + ((state)->hs_rsvd_eqs + (hid) - 1) -#define HERMON_CQ_EQNUM_GET(state) \ - (state->hs_devlim.num_rsvd_eq + \ - (atomic_inc_uint_nv(&state->hs_eq_dist) % \ - state->hs_intrmsi_allocd)) +#define HERMON_HID_VALID(state, hid) \ + ((uint_t)((hid) - 1) < (state)->hs_intrmsi_allocd) + +#define HERMON_EQNUM_TO_HID(state, eqnum) \ + ((eqnum) - (state)->hs_rsvd_eqs + 1) #define HERMON_CQ_ERREQNUM_GET(state) \ - (state->hs_devlim.num_rsvd_eq + state->hs_intrmsi_allocd) + (state)->hs_cq_erreqnum + /* * The following defines are used for Hermon CQ error handling. Note: For * CQEs which correspond to error events, the Hermon device requires some @@ -151,8 +173,6 @@ extern "C" { * code (above), doorbell count, and whether a error completion is for a * send or receive work request. */ - - #define HERMON_CQE_ERR_STATUS_SHIFT 0 #define HERMON_CQE_ERR_STATUS_MASK 0xFF #define HERMON_CQE_ERR_DBDCNT_MASK 0xFFFF @@ -223,7 +243,6 @@ struct hermon_sw_cq_s { struct hermon_qalloc_info_s cq_cqinfo; }; _NOTE(READ_ONLY_DATA(hermon_sw_cq_s::cq_cqnum - hermon_sw_cq_s::cq_eqnum hermon_sw_cq_s::cq_erreqnum hermon_sw_cq_s::cq_cqcrsrcp hermon_sw_cq_s::cq_rsrcp @@ -235,6 +254,7 @@ _NOTE(DATA_READABLE_WITHOUT_LOCK(hermon_sw_cq_s::cq_bufsz hermon_sw_cq_s::cq_cqinfo)) _NOTE(MUTEX_PROTECTS_DATA(hermon_sw_cq_s::cq_lock, hermon_sw_cq_s::cq_buf + hermon_sw_cq_s::cq_eqnum hermon_sw_cq_s::cq_mrhdl hermon_sw_cq_s::cq_refcnt hermon_sw_cq_s::cq_is_special @@ -257,6 +277,9 @@ int hermon_cq_notify(hermon_state_t *state, hermon_cqhdl_t cqhdl, ibt_cq_notify_flags_t flags); int hermon_cq_poll(hermon_state_t *state, hermon_cqhdl_t cqhdl, ibt_wc_t *wc_p, uint_t num_wc, uint_t *num_polled); +int hermon_cq_sched_alloc(hermon_state_t *state, ibt_cq_sched_attr_t *attr, + hermon_cq_sched_t **cq_sched_pp); +int hermon_cq_sched_free(hermon_state_t *state, hermon_cq_sched_t *cq_schedp); int hermon_cq_handler(hermon_state_t *state, hermon_eqhdl_t eq, hermon_hw_eqe_t *eqe); int hermon_cq_err_handler(hermon_state_t *state, hermon_eqhdl_t eq, @@ -266,6 +289,8 @@ void hermon_cq_refcnt_dec(hermon_cqhdl_t cq); hermon_cqhdl_t hermon_cqhdl_from_cqnum(hermon_state_t *state, uint_t cqnum); void hermon_cq_entries_flush(hermon_state_t *state, hermon_qphdl_t qp); void hermon_cq_resize_helper(hermon_state_t *state, hermon_cqhdl_t cq); +int hermon_cq_sched_init(hermon_state_t *state); +void hermon_cq_sched_fini(hermon_state_t *state); #ifdef __cplusplus } diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_event.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_event.h index 618b80ea92..450395796b 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_event.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_event.h @@ -20,8 +20,7 @@ */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_ADAPTERS_HERMON_EVENT_H @@ -116,7 +115,7 @@ extern "C" { #define HERMON_EVT_PATH_MIGRATED 0x01 #define HERMON_EVT_COMM_ESTABLISHED 0x02 #define HERMON_EVT_SEND_QUEUE_DRAINED 0x03 -#define HERMON_EVT_SRQ_LAST_WQE_REACHED 0x13 +#define HERMON_EVT_SRQ_LAST_WQE_REACHED 0x13 #define HERMON_EVT_SRQ_LIMIT 0x14 /* QP Affiliated Asynch Event */ #define HERMON_EVT_CQ_ERRORS 0x04 /* overrun, protection */ @@ -127,6 +126,9 @@ extern "C" { #define HERMON_EVT_LOCAL_ACC_VIO_WQ_ERROR 0x11 #define HERMON_EVT_SRQ_CATASTROPHIC_ERROR 0x12 #define HERMON_EVT_SPOOF_FAIL 0x16 /* enet only */ +/* FEXCH Errors (QP Affiliated) */ +#define HERMON_EVT_FEXCH_ERROR 0x0B + /* Unaffiliated Asynch Events/Errors */ #define HERMON_EVT_PORT_STATE_CHANGE 0x09 #define HERMON_EVT_GPIO 0x15 @@ -134,11 +136,6 @@ extern "C" { #define HERMON_EVT_COMMAND_INTF_COMP 0x0A /* Miscellaneous */ #define HERMON_EVT_LOCAL_CAT_ERROR 0x08 -/* LEGACY - no longer supported */ -#define HERMON_EVT_WQE_PG_FAULT 0x0B -#define HERMON_EVT_UNSUPPORTED_PG_FAULT 0x0C -#define HERMON_EVT_ECC_DETECTION 0x0E -#define HERMON_EVT_EQ_OVERFLOW 0x0F #define HERMON_EVT_MSK_COMPLETION \ @@ -152,10 +149,10 @@ extern "C" { (1 << HERMON_EVT_SEND_QUEUE_DRAINED) #define HERMON_EVT_MSK_SRQ_LAST_WQE_REACHED \ (1 << HERMON_EVT_SRQ_LAST_WQE_REACHED) -#define HERMON_EVT_MSK_SRQ_LIMIT \ +#define HERMON_EVT_MSK_SRQ_LIMIT \ (1 << HERMON_EVT_SRQ_LIMIT) -#define HERMON_EVT_MSK_CQ_ERRORS \ +#define HERMON_EVT_MSK_CQ_ERRORS \ (1 << HERMON_EVT_CQ_ERRORS) #define HERMON_EVT_MSK_LOCAL_WQ_CAT_ERROR \ (1 << HERMON_EVT_LOCAL_WQ_CAT_ERROR) @@ -169,37 +166,29 @@ extern "C" { (1 << HERMON_EVT_LOCAL_ACC_VIO_WQ_ERROR) #define HERMON_EVT_MSK_SRQ_CATASTROPHIC_ERROR \ (1 << HERMON_EVT_SRQ_CATASTROPHIC_ERROR) -#define HERMON_EVT_MSK_SPOOF_FAIL \ +#define HERMON_EVT_MSK_SPOOF_FAIL \ (1 << HERMON_EVT_SPOOF_FAIL) -#define HERMON_EVT_MSK_PORT_STATE_CHANGE \ +#define HERMON_EVT_MSK_FEXCH_ERROR \ + (1 << HERMON_EVT_FEXCH_ERROR) + +#define HERMON_EVT_MSK_PORT_STATE_CHANGE \ (1 << HERMON_EVT_PORT_STATE_CHANGE) -#define HERMON_EVT_MSK_GPIO \ +#define HERMON_EVT_MSK_GPIO \ (1 << HERMON_EVT_GPIO) -#define HERMON_EVT_MSK_COMMAND_INTF_COMP \ +#define HERMON_EVT_MSK_COMMAND_INTF_COMP \ (1 << HERMON_EVT_COMMAND_INTF_COMP) #define HERMON_EVT_MSK_LOCAL_CAT_ERROR \ (1 << HERMON_EVT_LOCAL_CAT_ERROR) -#define HERMON_EVT_MSK_WQE_PG_FAULT \ - (1 << HERMON_EVT_WQE_PG_FAULT) -#define HERMON_EVT_MSK_UNSUPPORTED_PG_FAULT \ - (1 << HERMON_EVT_UNSUPPORTED_PG_FAULT) -#define HERMON_EVT_MSK_ECC_DETECTION \ - (1 << HERMON_EVT_ECC_DETECTION) - #define HERMON_EVT_NO_MASK 0 -/* - * WAS in Tavor & Arbel, but now two bits - 0x1000 and 0x0800 (0x0B & 0x00C) - * are no longer supported, so the catchall will be just 0x0040 (0x06) - * Loc QPC cat - * #define HERMON_EVT_CATCHALL_MASK 0x1840 - */ +/* For now, "catchall" is just HERMON_EVT_LOCAL_QPC_CAT_ERROR. */ #define HERMON_EVT_CATCHALL_MASK 0x0040 + /* * The last defines are used by hermon_eqe_sync() to indicate whether or not * to force a DMA sync. The case for forcing a DMA sync on a EQE comes from @@ -270,9 +259,8 @@ extern "C" { * Specifically, it has a consumer index and a lock to ensure single threaded * access to it. It has pointers to the various resources allocated for the * event queue, i.e. an EQC resource and the memory for the event queue - * itself. It has flags to indicate whether the EQ requires ddi_dma_sync() - * ("eq_sync") or to indicate which type of event class(es) the EQ has been - * mapped to (eq_evttypemask). + * itself. It has flags to indicate which type of event class(es) the EQ + * has been mapped to (eq_evttypemask). * * It also has a pointer to the associated MR handle (for the mapped queue * memory) and a function pointer that points to the handler that should @@ -288,11 +276,10 @@ struct hermon_sw_eq_s { uint32_t eq_consindx; uint32_t eq_eqnum; hermon_hw_eqe_t *eq_buf; + uint32_t *eq_doorbell; hermon_mrhdl_t eq_mrhdl; uint32_t eq_bufsz; uint32_t eq_log_eqsz; - uint32_t eq_nexteqe; - uint_t eq_sync; uint_t eq_evttypemask; hermon_rsrc_t *eq_eqcrsrcp; hermon_rsrc_t *eq_rsrcp; @@ -310,6 +297,7 @@ void hermon_eq_doorbell(hermon_state_t *state, uint32_t eq_cmd, uint32_t eqn, uint32_t eq_param); void hermon_eq_overflow_handler(hermon_state_t *state, hermon_eqhdl_t eq, hermon_hw_eqe_t *eqe); +void hermon_eq_reset_uar_baseaddr(hermon_state_t *state); #ifdef __cplusplus } diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_fcoib.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_fcoib.h new file mode 100644 index 0000000000..4af751238e --- /dev/null +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_fcoib.h @@ -0,0 +1,104 @@ +/* + * CDDL HEADER START + * + * The contents of this file are subject to the terms of the + * Common Development and Distribution License (the "License"). + * You may not use this file except in compliance with the License. + * + * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE + * or http://www.opensolaris.org/os/licensing. + * See the License for the specific language governing permissions + * and limitations under the License. + * + * When distributing Covered Code, include this CDDL HEADER in each + * file and include the License file at usr/src/OPENSOLARIS.LICENSE. + * If applicable, add the following below this CDDL HEADER, with the + * fields enclosed by brackets "[]" replaced with your own identifying + * information: Portions Copyright [yyyy] [name of copyright owner] + * + * CDDL HEADER END + */ + +/* + * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. + */ + +#ifndef _SYS_IB_ADAPTERS_HERMON_FCOIB_H +#define _SYS_IB_ADAPTERS_HERMON_FCOIB_H + +/* + * hermon_fcoib.h + */ + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct hermon_fcoib_qp_s { + hermon_rsrc_t hfc_qp_rsrc; + vmem_t *hfc_qp_vmp; +} hermon_fcoib_qp_t; + +typedef struct hermon_fcoib_s { + uint8_t hfc_log2_max_port_ids_queried; + uint8_t hfc_log2_max_fexch_queried; + uint8_t hfc_log2_max_rfci_queried; + kmutex_t hfc_lock; + hermon_rsrc_t *hfc_mpt_rsrc; /* FEXCH MPTs for all ports */ + hermon_rsrc_t *hfc_mtt_rsrc; /* FEXCH MTTs for all MPTs */ + hermon_rsrc_t *hfc_fexch_rsrc; /* FEXCH QPs for all ports */ + hermon_rsrc_t *hfc_rfci_rsrc; /* RFCI QPs for all ports */ + uint8_t hfc_nports; /* #HCA ports */ + uint8_t hfc_port_enabled[HERMON_MAX_PORTS]; + uint_t hfc_mpts_per_port; + uint_t hfc_mtts_per_mpt; + uint_t hfc_fexch_qps_per_port; + uint_t hfc_rfci_qps_per_port; + vmem_t *hfc_rfci_vmemp[HERMON_MAX_PORTS]; + vmem_t *hfc_fexch_vmemp[HERMON_MAX_PORTS]; + uintptr_t hfc_vmemstart; + uint32_t *hfc_n_port_ids[HERMON_MAX_PORTS]; + + /* Convenient, but redundant values */ + uint32_t hfc_mpt_base[HERMON_MAX_PORTS]; + uint32_t hfc_mtt_base[HERMON_MAX_PORTS]; + uint32_t hfc_fexch_base[HERMON_MAX_PORTS]; + uint32_t hfc_rfci_base[HERMON_MAX_PORTS]; +} hermon_fcoib_t; + +_NOTE(DATA_READABLE_WITHOUT_LOCK(hermon_fcoib_s::hfc_fexch_rsrc + hermon_fcoib_s::hfc_nports + hermon_fcoib_s::hfc_mpts_per_port + hermon_fcoib_s::hfc_mtts_per_mpt + hermon_fcoib_s::hfc_fexch_qps_per_port + hermon_fcoib_s::hfc_rfci_qps_per_port + hermon_fcoib_s::hfc_mpt_base + hermon_fcoib_s::hfc_mtt_base + hermon_fcoib_s::hfc_fexch_base + hermon_fcoib_s::hfc_rfci_base)) + +int hermon_fcoib_set_id(hermon_state_t *state, int port, uint32_t rfci_qpn, + uint32_t src_id); +int hermon_fcoib_get_id_idx(hermon_state_t *state, int port, + ibt_fc_attr_t *fcp); +int hermon_fcoib_check_exch_base_off(hermon_state_t *state, int port, + ibt_fc_attr_t *fcp); +uint_t hermon_fcoib_qpnum_from_fexch(hermon_state_t *state, int port, + uint16_t fexch); +int hermon_fcoib_is_fexch_qpn(hermon_state_t *state, uint_t qpnum); +uint32_t hermon_fcoib_qpn_to_mkey(hermon_state_t *state, uint_t qpnum); +int hermon_fcoib_fexch_mkey_init(hermon_state_t *state, hermon_pdhdl_t pd, + uint8_t port, uint32_t qp_indx, uint_t sleep); +int hermon_fcoib_fexch_mkey_fini(hermon_state_t *state, hermon_pdhdl_t pd, + uint32_t qpnum, uint_t sleep); +uint32_t hermon_fcoib_fexch_relative_qpn(hermon_state_t *state, uint8_t port, + uint32_t qpnum); +int hermon_fcoib_init(hermon_state_t *state); +void hermon_fcoib_fini(hermon_state_t *state); + + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_IB_ADAPTERS_HERMON_FCOIB_H */ diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_fm.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_fm.h index b95f45ad87..2039658ddc 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_fm.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_fm.h @@ -20,8 +20,7 @@ */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_ADAPTERS_HERMON_FM_H @@ -119,10 +118,13 @@ typedef struct i_hca_fm_test hermon_test_t; * At each place where the planned FMA error matrix specifies that * an ereport will be generated, for now there is a HERMON_FMANOTE() * call generating an appropriate message string. + * + * This has been revised since it has been realized that FMA is only + * to be used for hardware errors. HERMON_FMANOTE() is used to report + * errors that are likely to be hardware, but possibly are not. */ - #define HERMON_FMANOTE(state, string) \ - cmn_err(CE_NOTE, "hermon%d: Device Error: %s", \ + cmn_err(CE_WARN, "hermon%d: Device Error: %s", \ (state)->hs_instance, string) /* CQE Syndrome errors - see hermon_cq.c */ diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_hw.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_hw.h index 0845906238..111ea877ed 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_hw.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_hw.h @@ -127,7 +127,7 @@ struct hermon_hw_hcr_s { #define HERMON_HCR_CMD_OPMOD_SHFT 12 /* - * Arbel "QUERY_DEV_LIM" command - Hermon, "QUERY_DEV_CAP" - Same hex code + * Arbel/tavor "QUERY_DEV_LIM" == Hermon "QUERY_DEV_CAP" - Same hex code * same function as tavor/arbel QUERY_DEV_LIM, just renamed (whatever). * The QUERY_DEV_LIM command returns the device limits and capabilities * supported by the Hermon device. This command must be run before @@ -175,8 +175,8 @@ struct hermon_hw_querydevlim_s { uint32_t :2; uint32_t log_rsvd_dmpt :4; uint32_t :4; - uint32_t log_max_mrw_sz :8; - uint32_t :4; + uint32_t log_max_mrw_sz :7; + uint32_t :5; uint32_t log_rsvd_mtt :4; uint32_t log_max_ra_glob :6; @@ -196,22 +196,25 @@ struct hermon_hw_querydevlim_s { uint32_t num_ports :4; uint32_t :12; uint32_t ca_ack_delay :5; - uint32_t :11; + uint32_t cqmep :3; /* cq moderation policies */ + uint32_t :4; + uint32_t :1; + uint32_t :3; - uint32_t mod_wr_srq :1; + uint32_t mod_wr_srq :1; /* resize SRQ supported */ uint32_t :31; - uint32_t :4; - uint32_t :12; + uint32_t :16; uint32_t stat_rate_sup :16; + uint32_t :8; + uint32_t :4; uint32_t :4; - uint32_t :12; uint32_t :8; uint32_t log_max_msg :5; uint32_t :3; - uint32_t rc :1; + uint32_t rc :1; /* 0x44 */ uint32_t uc :1; uint32_t ud :1; uint32_t xrc :1; @@ -222,21 +225,39 @@ struct hermon_hw_querydevlim_s { uint32_t pkey_v :1; uint32_t qkey_v :1; uint32_t vmm :1; - uint32_t :5; + uint32_t fcoe :1; + uint32_t dpdp :1; /* dual port diff protocol */ + uint32_t raw_etype :1; + uint32_t raw_ipv4 :1; + uint32_t blh :1; /* big LSO header, bit in WQE */ uint32_t mem_win :1; uint32_t apm :1; uint32_t atomic :1; uint32_t raw_multi :1; uint32_t avp :1; uint32_t ud_multi :1; - uint32_t :2; + uint32_t udm_ipv4 :1; + uint32_t dif :1; /* DIF supported */ uint32_t pg_on_demand :1; uint32_t router :1; - uint32_t :6; + uint32_t l2mc :1; /* lev 2 enet multicast */ + uint32_t :1; + uint32_t ud_swp :1; /* sw parse for UD xport */ + uint32_t ipv6_ex :1; /* offload w/ IPV6 ext hdrs */ + uint32_t lle :1; /* low latency enet */ + uint32_t fcoe_t11 :1; /* fcoenet T11 frame support */ - uint32_t :32; + /* 0x40 */ + uint32_t eth_uc_lb :1; /* enet unicast loopback */ + uint32_t :3; + uint32_t hdr_split :1; + uint32_t hdr_lookahead :1; + uint32_t :2; + uint32_t rss_udp :1; + uint32_t :7; + uint32_t :16; - uint32_t log_max_bf_page :6; + uint32_t log_max_bf_page :6; /* 0x4c */ uint32_t :2; uint32_t log_max_bf_req_ppg :6; uint32_t :2; @@ -244,30 +265,37 @@ struct hermon_hw_querydevlim_s { uint32_t :10; uint32_t blu_flm :1; - uint32_t log_pg_sz :8; + uint32_t log_pg_sz :8; /* 0x48 */ uint32_t :8; uint32_t log_max_uar_sz :6; uint32_t :6; uint32_t num_rsvd_uar :4; - uint32_t max_desc_sz_rq :16; + uint32_t max_desc_sz_rq :16; /* 0x54 */ uint32_t max_sg_rq :8; uint32_t :8; - uint32_t max_desc_sz_sq :16; + uint32_t max_desc_sz_sq :16; /* 0x50 */ uint32_t max_sg_sq :8; uint32_t :8; - uint32_t rsvd_fcoib[2]; - uint32_t log_max_srcd :4; - uint32_t :8; - uint32_t num_rsvd_srcds :4; + uint32_t rsvd_fcoib; /* 0x5C */ + + uint32_t :1; /* 0x58 */ + uint32_t fexch_base_mpt :7; /* FC exch base mpt num */ + uint32_t fcp_ud_base_qp :16; /* RC UD base qp num */ + uint32_t fexch_base_qp :8; /* FC exch base qp num */ + + + uint32_t log_max_xrcd :5; /* 0x64 */ + uint32_t :7; + uint32_t num_rsvd_xrcds :4; uint32_t log_max_pd :5; uint32_t :7; uint32_t num_rsvd_pd :4; - uint32_t log_max_mcg :8; + uint32_t log_max_mcg :8; /* 0x60 */ uint32_t num_rsvd_mcg :4; uint32_t :4; uint32_t log_max_qp_mcg :8; @@ -275,19 +303,19 @@ struct hermon_hw_querydevlim_s { uint32_t rsrv2[6]; - uint32_t altc_entry_sz :16; + uint32_t altc_entry_sz :16; /* 0x84 */ uint32_t aux_entry_sz :16; - uint32_t qpc_entry_sz :16; + uint32_t qpc_entry_sz :16; /* 0x80 */ uint32_t rdmardc_entry_sz :16; - uint32_t cmpt_entry_sz :16; + uint32_t cmpt_entry_sz :16; /* 0x8C */ uint32_t srq_entry_sz :16; - uint32_t cqc_entry_sz :16; + uint32_t cqc_entry_sz :16; /* 0x88 */ uint32_t eqc_entry_sz :16; - uint32_t bmme :1; + uint32_t bmme :1; /* 0x94 */ uint32_t win_type :1; uint32_t mps :1; uint32_t bl :1; @@ -301,13 +329,13 @@ struct hermon_hw_querydevlim_s { uint32_t fast_reg_wr :1; uint32_t :20; - uint32_t dmpt_entry_sz :16; + uint32_t dmpt_entry_sz :16; /* 0x90 */ uint32_t mtt_entry_sz :16; uint32_t :32; uint32_t rsv_lkey; - + /* 0xA0 */ uint64_t max_icm_size; uint32_t rsrv3[22]; @@ -349,8 +377,8 @@ struct hermon_hw_querydevlim_s { uint32_t log_max_eq :4; uint32_t log_rsvd_mtt :4; - uint32_t :4; - uint32_t log_max_mrw_sz :8; + uint32_t :5; + uint32_t log_max_mrw_sz :7; uint32_t :4; uint32_t log_rsvd_dmpt :4; uint32_t :2; @@ -373,37 +401,56 @@ struct hermon_hw_querydevlim_s { uint32_t log_max_ra_glob :6; uint32_t :31; - uint32_t mod_wr_srq :1; + uint32_t mod_wr_srq :1; /* resize SRQ supported */ - uint32_t :11; + uint32_t :3; + uint32_t :1; + uint32_t :4; + uint32_t cqmep :3; /* cq moderation policies */ uint32_t ca_ack_delay :5; - /* PRM 0.35, stuff moved to per port info */ uint32_t :12; uint32_t num_ports :4; uint32_t :3; uint32_t log_max_msg :5; uint32_t :8; - uint32_t :12; uint32_t :4; - - uint32_t stat_rate_sup :16; - uint32_t :12; uint32_t :4; + uint32_t :8; - uint32_t :32; + uint32_t stat_rate_sup :16; + uint32_t :16; - uint32_t :6; + uint32_t :16; /* 0x40 */ + uint32_t :7; + uint32_t rss_udp :1; + uint32_t :2; + uint32_t hdr_lookahead :1; + uint32_t hdr_split :1; + uint32_t :3; + uint32_t eth_uc_lb :1; /* enet unicast loopback */ + /* 0x44 */ + uint32_t fcoe_t11 :1; /* fcoenet T11 frame support */ + uint32_t lle :1; /* low latency enet */ + uint32_t ipv6_ex :1; /* offload w/ IPV6 ext hdrs */ + uint32_t ud_swp :1; /* sw parse for UD xport */ + uint32_t :1; + uint32_t l2mc :1; /* lev 2 enet multicast */ uint32_t router :1; uint32_t pg_on_demand :1; - uint32_t :2; + uint32_t dif :1; /* DIF supported */ + uint32_t udm_ipv4 :1; uint32_t ud_multi :1; uint32_t avp :1; uint32_t raw_multi :1; uint32_t atomic :1; uint32_t apm :1; uint32_t mem_win :1; - uint32_t :5; + uint32_t blh :1; /* big LSO header, bit in WQE */ + uint32_t raw_ipv4 :1; + uint32_t raw_etype :1; + uint32_t dpdp :1; /* dual port diff protocol */ + uint32_t fcoe :1; uint32_t vmm :1; uint32_t qkey_v :1; uint32_t pkey_v :1; @@ -416,13 +463,13 @@ struct hermon_hw_querydevlim_s { uint32_t uc :1; uint32_t rc :1; - uint32_t num_rsvd_uar :4; + uint32_t num_rsvd_uar :4; /* 0x48 */ uint32_t :6; uint32_t log_max_uar_sz :6; uint32_t :8; uint32_t log_pg_sz :8; - uint32_t blu_flm :1; + uint32_t blu_flm :1; /* 0x4c */ uint32_t :10; uint32_t log_bf_reg_sz :5; uint32_t :2; @@ -430,47 +477,53 @@ struct hermon_hw_querydevlim_s { uint32_t :2; uint32_t log_max_bf_page :6; - uint32_t :8; + uint32_t :8; /* 0x50 */ uint32_t max_sg_sq :8; uint32_t max_desc_sz_sq :16; - uint32_t :8; + uint32_t :8; /* 0x54 */ uint32_t max_sg_rq :8; uint32_t max_desc_sz_rq :16; - uint32_t rsvd_fcoib[2]; + /* 0x58 */ + uint32_t fexch_base_qp :8; /* FC exch base qp num */ + uint32_t fcp_ud_base_qp :16; /* RC UD base qp num */ + uint32_t fexch_base_mpt :7; /* FC exch base mpt num */ + uint32_t :1; - uint32_t :8; + uint32_t rsvd_fcoib; /* 0x5C */ + + uint32_t :8; /* 0x60 */ uint32_t log_max_qp_mcg :8; uint32_t :4; uint32_t num_rsvd_mcg :4; uint32_t log_max_mcg :8; - uint32_t num_rsvd_pd :4; + uint32_t num_rsvd_pd :4; /* 0x64 */ uint32_t :7; uint32_t log_max_pd :5; - uint32_t num_rsvd_srcds :4; - uint32_t :8; - uint32_t log_max_srcd :4; + uint32_t num_rsvd_xrcds :4; + uint32_t :7; + uint32_t log_max_xrcd :5; uint32_t rsrv2[6]; - uint32_t rdmardc_entry_sz :16; + uint32_t rdmardc_entry_sz :16; /* 0x80 */ uint32_t qpc_entry_sz :16; - uint32_t aux_entry_sz :16; + uint32_t aux_entry_sz :16; /* 0x84 */ uint32_t altc_entry_sz :16; - uint32_t eqc_entry_sz :16; + uint32_t eqc_entry_sz :16; /* 0x88 */ uint32_t cqc_entry_sz :16; - uint32_t srq_entry_sz :16; + uint32_t srq_entry_sz :16; /* 0x8C */ uint32_t cmpt_entry_sz :16; - uint32_t mtt_entry_sz :16; + uint32_t mtt_entry_sz :16; /* 0x90 */ uint32_t dmpt_entry_sz :16; - uint32_t :20; + uint32_t :20; /* 0x94 */ uint32_t fast_reg_wr :1; uint32_t reserved_lkey :1; uint32_t win_type2 :1; @@ -489,7 +542,7 @@ struct hermon_hw_querydevlim_s { uint32_t :32; uint64_t max_icm_size; - + /* 0xA0 */ uint32_t rsrv3[22]; }; #endif @@ -520,16 +573,16 @@ struct hermon_hw_queryfw_s { uint32_t cmd_intf_rev :16; uint32_t :16; - uint32_t fw_day :8; + uint32_t fw_day :8; uint32_t fw_month :8; - uint32_t fw_year :16; + uint32_t fw_year :16; uint32_t :1; - uint32_t ccq :1; + uint32_t ccq :1; /* currently not def'd */ uint32_t :6; - uint32_t fw_sec :8; - uint32_t fw_min :8; - uint32_t fw_hour :8; + uint32_t fw_sec :8; + uint32_t fw_min :8; + uint32_t fw_hour :8; uint32_t rsrv0[2]; @@ -547,9 +600,16 @@ struct hermon_hw_queryfw_s { uint32_t error_buf_sz; - uint32_t rsrv2[48]; + uint64_t vf_com_ch_addr; + + uint32_t :32; + + uint32_t :30; + uint32_t vf_com_ch_bar :2; + + uint32_t rsrv2[44]; }; -#else +#else /* BIG ENDIAN */ struct hermon_hw_queryfw_s { uint32_t fw_pages :16; uint32_t fw_rev_major :16; @@ -564,16 +624,16 @@ struct hermon_hw_queryfw_s { uint32_t :23; uint32_t log_max_cmd :8; - uint32_t fw_hour :8; - uint32_t fw_min :8; - uint32_t fw_sec :8; + uint32_t fw_hour :8; + uint32_t fw_min :8; + uint32_t fw_sec :8; uint32_t :6; - uint32_t ccq :1; + uint32_t ccq :1; /* currently not def'd */ uint32_t :1; - uint32_t fw_year :16; + uint32_t fw_year :16; uint32_t fw_month :8; - uint32_t fw_day :8; + uint32_t fw_day :8; uint32_t rsrv1[2]; @@ -591,7 +651,14 @@ struct hermon_hw_queryfw_s { uint32_t err_buf_bar :2; uint32_t :30; - uint32_t rsrv2[48]; + uint64_t vf_com_ch_addr; + + uint32_t vf_com_ch_bar :2; + uint32_t :30; + + uint32_t :32; + + uint32_t rsrv2[44]; }; #endif @@ -662,23 +729,27 @@ struct hermon_hw_queryadapter_s { struct hermon_hw_vpm_s { uint32_t :12; uint32_t vaddr_l :20; + uint32_t vaddr_h; - uint32_t log2sz :5; + uint32_t log2sz :5; /* in 4KB pages */ uint32_t :7; uint32_t paddr_l :20; + uint32_t paddr_h; }; #else struct hermon_hw_vpm_s { uint32_t vaddr_h; + uint32_t vaddr_l :20; uint32_t :12; uint32_t paddr_h; + uint32_t paddr_l :20; uint32_t :7; - uint32_t log2sz :5; + uint32_t log2sz :5; /* in 4KB pages */ }; #endif @@ -751,7 +822,7 @@ typedef struct hermon_hw_qp_ee_cq_eq_rdb_s { uint32_t rsrv6[2]; } hermon_hw_qp_ee_cq_eq_rdb_t; -#else +#else /* BIG ENDIAN */ typedef struct hermon_hw_qp_ee_cq_eq_rdb_s { uint32_t rsrv0[4]; @@ -816,7 +887,7 @@ typedef struct hermon_multicast_param_s { uint32_t mc_hash_fn :3; uint32_t :5; } hermon_multicast_param_t; -#else +#else /* BIG ENDIAN */ typedef struct hermon_multicast_param_s { uint64_t mc_baseaddr; @@ -844,6 +915,7 @@ typedef struct hermon_tpt_param_s { uint64_t dmpt_baseaddr; uint32_t :32; + uint32_t log_dmpt_sz :6; uint32_t :2; uint32_t pgfault_rnr_to :5; @@ -853,7 +925,7 @@ typedef struct hermon_tpt_param_s { uint64_t cmpt_baseaddr; } hermon_tpt_param_t; -#else +#else /* BIG ENDIAN */ typedef struct hermon_tpt_param_s { uint64_t dmpt_baseaddr; @@ -861,6 +933,7 @@ typedef struct hermon_tpt_param_s { uint32_t pgfault_rnr_to :5; uint32_t :2; uint32_t log_dmpt_sz :6; + uint32_t :32; uint64_t mtt_baseaddr; @@ -899,6 +972,10 @@ typedef struct hermon_uar_param_s { /* * NEW for Hermon * QP Allocation Params + * NOTE: as of PRM v0.50 no longer needed (ccq not supported + * leave structure here, just in case ccq comes back ) + * but adjust the overall structure + * not to use it * */ @@ -926,12 +1003,13 @@ typedef struct hermon_qp_alloc_param_s { } hermon_qp_alloc_param_t; #endif + #ifdef _LITTLE_ENDIAN struct hermon_hw_initqueryhca_s { uint32_t :32; uint32_t :24; - uint32_t version :8; + uint32_t version :8; uint32_t :13; uint32_t log2_cacheline :3; @@ -941,9 +1019,11 @@ struct hermon_hw_initqueryhca_s { uint32_t udav_port_chk :1; uint32_t big_endian :1; - uint32_t :1; + uint32_t qos :1; uint32_t chsum_en :1; - uint32_t :28; + uint32_t :12; + uint32_t cqpm_short_pkt_lim :14; /* short pkt limit for qpm */ + uint32_t cqmp :2; /* cq moderation policy */ uint32_t router_qp :24; uint32_t :5; @@ -957,7 +1037,7 @@ struct hermon_hw_initqueryhca_s { uint32_t rsrv2[8]; - hermon_multicast_param_t multi; + hermon_multicast_param_t multi; uint32_t rsrv3[4]; @@ -967,15 +1047,22 @@ struct hermon_hw_initqueryhca_s { hermon_uar_param_t uar; - uint32_t rsrv5[4]; + uint32_t rsrv5[36]; + + hermon_multicast_param_t enet_multi; - hermon_qp_alloc_param_t qp_alloc; + uint32_t rsrv6[24]; /* to 0x24C */ - uint32_t rsrv6[100]; /* from 0x16c to 0x2fc offsets */ + uint32_t :32; + + uint32_t fcoe_t11 :1; /* fcoe t11 frame enable */ + uint32_t :31; + + uint32_t rsrv7[42]; /* 0x254 - 0x2FC */ }; #else /* BIG ENDIAN */ struct hermon_hw_initqueryhca_s { - uint32_t version :8; + uint32_t version :8; uint32_t :24; uint32_t :32; @@ -992,9 +1079,11 @@ struct hermon_hw_initqueryhca_s { uint32_t :5; uint32_t router_qp :24; - uint32_t :28; + uint32_t cqmp :2; /* cq moderation policy */ + uint32_t cqpm_short_pkt_lim :14; /* short pkt limit for qpm */ + uint32_t :12; uint32_t chsum_en :1; - uint32_t :1; + uint32_t qos :1; uint32_t big_endian :1; uint32_t udav_port_chk :1; @@ -1004,7 +1093,7 @@ struct hermon_hw_initqueryhca_s { uint32_t rsrv2[8]; - hermon_multicast_param_t multi; + hermon_multicast_param_t multi; uint32_t rsrv3[4]; @@ -1014,11 +1103,18 @@ struct hermon_hw_initqueryhca_s { hermon_uar_param_t uar; - uint32_t rsrv5[4]; + uint32_t rsrv5[36]; + + hermon_multicast_param_t enet_multi; + + uint32_t rsrv6[24]; /* to 0x24C */ - hermon_qp_alloc_param_t qp_alloc; + uint32_t :31; + uint32_t fcoe_t11 :1; /* fcoe t11 frame enable */ + + uint32_t :32; - uint32_t rsrv6[100]; /* from 0x16c to 0x2fc offsets */ + uint32_t rsrv7[42]; /* 0x254 - 0x2FC */ }; #endif #define HERMON_UDAV_PROTECT_DISABLED 0x0 @@ -1057,82 +1153,131 @@ struct hermon_hw_initqueryhca_s { * directly as was done for the previous HCAs). */ +/* + * PRM 0.4X and 0.50 changed the query_port to integrate the ethernet + * stuff as well, so this is a signficant change to the structure + */ + #ifdef _LITTLE_ENDIAN struct hermon_hw_query_port_s { + /* 0x04 */ uint32_t log_max_pkey :4; /* pkey table size */ uint32_t log_max_gid :4; /* max gids / port */ - /* was max_port_width arbel: long list of values */ - uint32_t ib_port_wid :4; - uint32_t :4; - uint32_t :4; /* other types possibly */ - uint32_t :4; + uint32_t ib_port_wid :8; /* - * 0x1=2.5G, 0x3=2.5 or 5.0G, 0x5=2.5 or 10G - * 0x7=2.5, 5.0, or 10G, others rsvd + * Enet link speed - 0x0 10Gb XAUI, 0x01 10Gb XFI, + * 0x02 1Gb, 0xF other */ - uint32_t ib_link_spd :4; - + uint32_t eth_link_spd :4; uint32_t :4; + /* + * IB Link speed - bit 0 SDR, bit1 DDR, Bit 2 QDR + */ + uint32_t ib_link_spd :8; - uint32_t :16; /* used for other types (?) */ - uint32_t ib_mtu :4; + /* 0x00 */ + uint32_t eth_mtu :16; /* in bytes */ /* - * 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 - * 0x5=4096, others rsvd + * IB MTU - 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x4=2048, 0x5=4096 */ + uint32_t ib_mtu :4; uint32_t :4; - uint32_t port_type :8; /* 0x00, 0x01 IB, others TBD */ + /* + * for next two if link down + * -> what port supports, if up + * -> what port is running + */ + + uint32_t ib_link :1; + uint32_t eth_link :1; + uint32_t :1; + uint32_t vpi :1; + uint32_t :3; + uint32_t link_up :1; + + + uint32_t :32; /* 0x0C */ - uint32_t :32; /* max vl's supported (not incl vl_15) */ - uint32_t max_vl :4; + uint32_t max_vl :4; /* 0x08 */ uint32_t :4; - uint32_t :8; /* but others possibly */ + uint32_t log_max_mac :4; + uint32_t log_max_vlan :4; + uint32_t :16; + + uint32_t mac_lo; + + uint32_t mac_hi :16; uint32_t :16; - uint32_t rsvd0[2]; /* but for other types */ - uint32_t rsvd1[504]; + uint32_t rsvd1[2]; }; + #else /* BIG ENDIAN */ struct hermon_hw_query_port_s { - uint32_t port_type :8; /* 0x00, 0x01 IB, others TBD */ + /* 0x00 */ + uint32_t link_up :1; + uint32_t :3; + uint32_t vpi :1; + uint32_t :1; + /* + * for next two if link down + * -> what port supports, if up + * -> what port is running + */ + uint32_t eth_link :1; + uint32_t ib_link :1; uint32_t :4; /* - * 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 - * 0x1=256, 0x2=512, 0x3=1024, 0x5=2048 + * IB MTU - 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x4=2048, 0x5=4096 */ uint32_t ib_mtu :4; - /* 0x5=4096, others rsvd */ - uint32_t :16; /* used for other types (?) */ + uint32_t eth_mtu :16; /* in bytes */ - uint32_t :4; - uint32_t ib_link_spd :4; + /* 0x04 */ /* - * 0x1=2.5G, 0x3=2.5 or 5.0G, 0x5=2.5 or 10G - * 0x7=2.5, 5.0, or 10G, others rsvd + * IB Link speed - bit 0 SDR, bit1 DDR, Bit 2 QDR */ + uint32_t ib_link_spd :8; uint32_t :4; - uint32_t :4; /* other types possibly */ - uint32_t :4; - /* was max_port_width arbel: long list of values */ - uint32_t ib_port_wid :4; + /* + * Enet link speed - 0x0 10Gb XAUI, 0x01 10Gb XFI, + * 0x02 1Gb, 0xF other + */ + uint32_t eth_link_spd :4; + uint32_t ib_port_wid :8; uint32_t log_max_gid :4; /* max gids / port */ uint32_t log_max_pkey :4; /* pkey table size */ - uint32_t :16; - uint32_t :8; /* but others possibly */ + uint32_t :16; /* 0x08 */ + uint32_t log_max_vlan :4; + uint32_t log_max_mac :4; uint32_t :4; /* max vl's supported (not incl vl_15) */ uint32_t max_vl :4; - uint32_t :32; + uint32_t :32; /* 0x0C */ + + uint32_t :16; + uint32_t mac_hi :16; - uint32_t rsvd0[2]; /* but for other types */ - uint32_t rsvd1[504]; + uint32_t mac_lo; + + uint32_t rsvd1[2]; }; #endif +/* + * the following structure is used for IB set port + * others following are for ethernet set port + */ + +#define HERMON_HW_OPMOD_SETPORT_IB 0x0 +#define HERMON_HW_OPMOD_SETPORT_EN 0x1 +#define HERMON_HW_OPMOD_SETPORT_EXT 0x2 + + #ifdef _LITTLE_ENDIAN struct hermon_hw_set_port_s { uint32_t cap_mask; @@ -1158,20 +1303,17 @@ struct hermon_hw_set_port_s { uint64_t node_guid; - uint32_t sniff_qpn_base :24; - uint32_t ge :1; /* glob egress sniff enabled */ - uint32_t gi :1; /* glob ingress sniff enabled */ - uint32_t qe :1; /* qp-egress sniff enable */ - uint32_t qi :1; /* qp-ingress sniff enabled */ - uint32_t :4; + uint32_t ingress_sniff_qpn :24; + uint32_t ingress_sniff_mode :1; + uint32_t :7; - uint32_t router_qpn_base :24; - uint32_t routermode :1; - uint32_t :7; + uint32_t egress_sniff_qpn :24; + uint32_t egress_sniff_mode :1; + uint32_t :7; uint32_t :32; - uint32_t max_guid :16; /* valid if noted above */ + uint32_t max_gid :16; /* valid if noted above */ uint32_t max_pkey :16; /* valid if noted above */ uint32_t rsrd0[500]; @@ -1201,19 +1343,17 @@ struct hermon_hw_set_port_s { uint64_t node_guid; - uint32_t :7; - uint32_t routermode :1; - uint32_t router_qpn_base :24; + uint32_t :7; + uint32_t egress_sniff_mode :1; + uint32_t egress_sniff_qpn :24; + + uint32_t :7; + uint32_t ingress_sniff_mode :1; + uint32_t ingress_sniff_qpn :24; - uint32_t :4; - uint32_t qi :1; /* qp-ingress sniff enabled */ - uint32_t qe :1; /* qp-egress sniff enable */ - uint32_t gi :1; /* glob ingress sniff enabled */ - uint32_t ge :1; /* glob egress sniff enabled */ - uint32_t sniff_qpn_base :24; uint32_t max_pkey :16; /* valid if noted above */ - uint32_t max_guid :16; /* valid if noted above */ + uint32_t max_gid :16; /* valid if noted above */ uint32_t :32; @@ -1221,6 +1361,292 @@ struct hermon_hw_set_port_s { }; #endif +/* + * structures for ethernet setport + * Which structure is used depends on low-16 of opmod + * Low 8 == port number, 15:8 == selector + * Or the following with port number + */ + +#define HERMON_HW_ENET_OPMOD_SELECT_GEN 0x0000 /* general params */ +#define HERMON_HW_ENET_OPMOD_SELECT_RQN 0x0100 /* rcv qpn calc */ +#define HERMON_HW_ENET_OPMOD_SELECT_MAC 0x0200 /* MAC table conf */ +#define HERMON_HW_ENET_OPMOD_SELECT_VLAN 0x0300 /* VLAN table conf */ +#define HERMON_HW_ENET_OPMOD_SELECT_PRIO 0x0400 /* Priority table */ +#define HERMON_HW_ENET_OPMOD_SELECT_GID 0x0500 /* GID Table */ + +/* + * set port for enthernet, general parameters + * Which structure + */ + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_set_port_en_s { + uint32_t mtu :16; + uint32_t :16; + + uint32_t v_mtu :1; + uint32_t v_pprx :1; + uint32_t v_pptx :1; + uint32_t :29; + + uint32_t :16; + uint32_t pfcrx :8; + uint32_t :7; + uint32_t pprx :1; + + uint32_t :16; + uint32_t pfctx :8; + uint32_t :7; + uint32_t pptx :1; + + uint32_t rsvd0[4]; +}; + +#else /* BIG ENDIAN */ +struct hermon_hw_set_port_en_s { + uint32_t :29; + uint32_t v_pptx :1; + uint32_t v_pprx :1; + uint32_t v_mtu :1; + + uint32_t :16; + uint32_t mtu :16; + + uint32_t pptx :1; + uint32_t :7; + uint32_t pfctx :8; + uint32_t :16; + + uint32_t pprx :1; + uint32_t :7; + uint32_t pfcrx :8; + uint32_t :16; + + uint32_t rsvd0[4]; + +}; +#endif + +/* set_port for enet, RX QPM calculations Parameters */ + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_set_port_en_rqpn_s { + uint32_t n_p :2; + uint32_t :6; + uint32_t n_v :3; + uint32_t :5; + uint32_t n_m :4; + uint32_t :12; + + uint32_t base_qpn :24; + uint32_t :8; + + uint32_t vlan_miss_idx :7; + uint32_t :8; + uint32_t intra_vlan_miss :1; + uint32_t no_vlan_idx :7; + uint32_t :8; + uint32_t intra_no_vlan :1; + + uint32_t mac_miss_idx :8; + uint32_t :24; + + uint32_t promisc_qpn :24; + uint32_t :7; + uint32_t en_uc_promisc :1; + + uint32_t no_vlan_prio :3; + uint32_t :29; + + uint32_t :32; + + uint32_t def_mcast_qpn :24; + uint32_t :5; + uint32_t mc_by_vlan :1; + uint32_t mc_promisc_mode :2; + + uint32_t rsvd0[4]; +}; + +#else /* BIG ENDIAN */ +struct hermon_hw_set_port_en_rqpn_s { + uint32_t :8; + uint32_t base_qpn :24; + + uint32_t :12; + uint32_t n_m :4; + uint32_t :5; + uint32_t n_v :3; + uint32_t :6; + uint32_t n_p :2; + + uint32_t :24; + uint32_t mac_miss_idx :8; + + uint32_t intra_no_vlan :1; + uint32_t :8; + uint32_t no_vlan_idx :7; + uint32_t intra_vlan_miss :1; + uint32_t :8; + uint32_t vlan_miss_idx :7; + + uint32_t :29; + uint32_t no_vlan_prio :3; + + uint32_t en_uc_promisc :1; + uint32_t :7; + uint32_t promisc_qpn :24; + + uint32_t mc_promisc_mode :2; + uint32_t mc_by_vlan :1; + uint32_t :5; + uint32_t def_mcast_qpn :24; + + uint32_t :32; + + uint32_t rsvd0[4]; +}; +#endif + + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_set_port_mact_entry_s { + uint32_t mac_lo :32; + + uint32_t mac_hi :16; + uint32_t :7; + uint32_t mac_valid :1; +}; +#else /* BIG ENDIAN */ +struct hermon_hw_set_port_mact_entry_s { + uint32_t mac_valid :1; + uint32_t :7; + uint32_t mac_hi :16; + + uint32_t mac_lo :32; + +}; +#endif + + +/* set_port for enet, MAC Table Configuration */ + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_set_port_en_mact_s { + struct hermon_hw_set_port_mact_entry_s mtable[128]; +}; +#else /* BIG ENDIAN */ +struct hermon_hw_set_port_en_mact_s { + struct hermon_hw_set_port_mact_entry_s mtable[128]; +}; +#endif + + +/* set_port for enet, VLAN Table Configuration */ + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_set_port_vlant_entry_s { + uint32_t vlan_id :12; + uint32_t :18; + uint32_t intra :1; + uint32_t valid :1; +}; +#else /* BIG ENDIAN */ +struct hermon_hw_set_port_vlant_entry_s { + uint32_t valid :1; + uint32_t intra :1; + uint32_t :18; + uint32_t vlan_id :12; +}; +#endif + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_set_port_en_vlant_s { + uint32_t rsvd[2]; + struct hermon_hw_set_port_vlant_entry_s table[126]; +}; +#else /* BIG ENDIAN */ +struct hermon_hw_set_port_en_vlant_s { + uint32_t rsvd[2]; + struct hermon_hw_set_port_vlant_entry_s table[126]; +}; +#endif + +/* set_port for enet, Priority table Parameters */ + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_set_port_en_priot_s { + uint32_t :32; + + uint32_t prio0 :3; + uint32_t :1; + uint32_t prio1 :3; + uint32_t :1; + uint32_t prio2 :3; + uint32_t :1; + uint32_t prio3 :3; + uint32_t :1; + uint32_t prio4 :3; + uint32_t :1; + uint32_t prio5 :3; + uint32_t :1; + uint32_t prio6 :3; + uint32_t :1; + uint32_t prio7 :3; + uint32_t :1; + + uint32_t rsvd[2]; +}; +#else /* BIG ENDIAN */ +struct hermon_hw_set_port_en_priot_s { + uint32_t :1; + uint32_t prio7 :3; + uint32_t :1; + uint32_t prio6 :3; + uint32_t :1; + uint32_t prio5 :3; + uint32_t :1; + uint32_t prio4 :3; + uint32_t :1; + uint32_t prio3 :3; + uint32_t :1; + uint32_t prio2 :3; + uint32_t :1; + uint32_t prio1 :3; + uint32_t :1; + uint32_t prio0 :3; + + uint32_t :32; + + uint32_t rsvd[2]; + +}; +#endif + + +/* note: GID table is same BIG or LITTLE ENDIAN */ + +struct hermon_hw_set_port_gidtable_s { + uint64_t gid[128]; +}; + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_conf_int_mod_s { + uint32_t :32; + + uint32_t int_vect :16; + uint32_t min_delay :16; +}; +#else /* BIG ENDIAN */ +struct hermon_hw_conf_int_mod_s { + uint32_t min_delay :16; + uint32_t int_vect :16; + + uint32_t :32; +}; +#endif + @@ -1286,6 +1712,7 @@ struct hermon_hw_dmpt_s { uint32_t :1; /* dw 2, byte 0xc-f */ uint32_t mem_key; + uint64_t start_addr; /* dw 4-5, byte 0x10-17 */ uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ @@ -1315,15 +1742,16 @@ struct hermon_hw_dmpt_s { uint32_t entity_sz :21; uint32_t :11; /* dw 14, byte 0x38-3b */ -#ifdef HERMON_NOTIMPL + uint32_t dif_m_atag :16; uint32_t :16; /* dw 17, 0x44-47 */ uint32_t dif_a_msk :16; uint32_t dif_v_msk :2; uint32_t dif_rep :2; - uint32_t :9; - uint32_t dif_err :3; /* dw 16, 0x40-43 */ + uint32_t :4; + uint32_t dif_err :3; + uint32_t :5; /* dw 16, 0x40-43 */ uint32_t dif_w_atag :16; uint32_t :16; /* dw 19, 0x4c-4f */ @@ -1333,7 +1761,9 @@ struct hermon_hw_dmpt_s { uint32_t :32; uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */ -#endif /* HERMON_NOTIMPL */ + + uint32_t rsvd[10]; + }; #else /* BIG ENDIAN */ @@ -1399,10 +1829,10 @@ struct hermon_hw_dmpt_s { uint32_t :11; uint32_t mtt_fbo :21; /* dw 15, byte 0x3c-3f */ -#ifdef HERMON_NOTIMPL + uint32_t :5; uint32_t dif_err :3; - uint32_t :9; + uint32_t :4; uint32_t dif_rep :2; uint32_t dif_v_msk :2; uint32_t dif_a_msk :16; /* dw 16, 0x40-43 */ @@ -1418,7 +1848,9 @@ struct hermon_hw_dmpt_s { uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */ uint32_t :32; -#endif /* HERMON_NOTIMPL */ + + uint32_t rsvd[10]; + }; #endif @@ -1469,7 +1901,7 @@ struct hermon_hw_cmpt_s { uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */ - uint32_t win_cnt :24; + uint32_t win_cnt :24; uint32_t :8; /* dw 9, byte 0x24-27 */ uint32_t lkey; /* dw 8, byte 0x20-23 */ @@ -1480,8 +1912,8 @@ struct hermon_hw_cmpt_s { uint32_t mtt_rep :4; uint32_t :17; uint32_t blk_mode :1; - uint32_t len_b64 :1; /* bit 64 of length */ - uint32_t fbo_en :1; + uint32_t len_b64 :1; /* bit 64 of length */ + uint32_t fbo_en :1; uint32_t :8; /* dw 10, byte 0x28-2b */ uint32_t mtt_size; /* dw 13, byte 0x34-37 */ @@ -1489,7 +1921,7 @@ struct hermon_hw_cmpt_s { uint32_t :3; uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */ - uint32_t mtt_fbo :21; + uint32_t mtt_fbo :21; uint32_t :11; /* dw 15, byte 0x3c-3f */ uint32_t entity_sz :21; @@ -1500,24 +1932,24 @@ struct hermon_hw_cmpt_s { #else /* BIG ENDIAN */ struct hermon_hw_cmpt_s { - uint32_t status :4; + uint32_t status :4; uint32_t :8; uint32_t no_snoop :1; uint32_t :1; uint32_t atc_xlat :1; - uint32_t atc_req :1; - uint32_t en_bind :1; - uint32_t atomic :1; + uint32_t atc_req :1; + uint32_t en_bind :1; + uint32_t atomic :1; uint32_t rw :1; uint32_t rr :1; uint32_t lw :1; uint32_t lr :1; uint32_t phys_addr :1; - uint32_t reg_win :1; + uint32_t reg_win :1; uint32_t :8; /* dw 0, byte 0x0-3 */ uint32_t qpn :24; - uint32_t bnd_qp :1; + uint32_t bnd_qp :1; uint32_t :7; /* dw 1, byte 0x4-7 */ uint32_t mem_key; /* dw 2, byte 0x8-b */ @@ -1539,14 +1971,14 @@ struct hermon_hw_cmpt_s { uint32_t lkey; /* dw 8, bytd 0x20-23 */ uint32_t :8; - uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */ + uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */ uint32_t :8; - uint32_t fbo_en :1; - uint32_t len_b64 :1; /* bit 64 of length */ + uint32_t fbo_en :1; + uint32_t len_b64 :1; /* bit 64 of length */ uint32_t blk_mode :1; uint32_t :17; - uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */ + uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */ uint32_t :24; uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */ @@ -1558,6 +1990,9 @@ struct hermon_hw_cmpt_s { uint32_t :11; uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */ + + uint32_t :11; /* dw 15, byte 0x3c-3f */ + uint32_t mtt_fbo :21; }; #endif @@ -1862,6 +2297,22 @@ typedef struct hermon_hw_eqe_operr_s { #define HERMON_ERREVT_INTERNAL_PARITY 0x5 +typedef struct hermon_hw_eqe_fcerr_s { + uint32_t :14; + uint32_t port :2; + uint32_t fexch :16; /* fexch number */ + + uint32_t :32; + + uint32_t :24; + uint32_t fcsyndrome :8; + + uint32_t rsvd[3]; +} hermon_hw_eqe_fcerr_t; + +#define HERMON_ERR_FC_BADIU 0x0 +#define HERMON_ERR_FC_SEQUENCE 0x01 + typedef struct hermon_hw_eqe_pgflt_s { uint32_t rsrv0[2]; uint32_t :24; @@ -1901,6 +2352,7 @@ struct hermon_hw_eqe_s { hermon_hw_eqe_cmdcmpl_t eqe_cmdcmpl; hermon_hw_eqe_operr_t eqe_operr; hermon_hw_eqe_pgflt_t eqe_pgflt; + hermon_hw_eqe_fcerr_t eqe_fcerr; } event_data; uint32_t :24; uint32_t owner :1; @@ -1914,6 +2366,7 @@ struct hermon_hw_eqe_s { #define eqe_cmdcmpl event_data.eqe_cmdcmpl #define eqe_operr event_data.eqe_operr #define eqe_pgflt event_data.eqe_pgflt +#define eqe_fcerr event_data.eqe_fcerr /* * The following macros are used for extracting (and in some cases filling in) @@ -1953,6 +2406,13 @@ struct hermon_hw_eqe_s { (((uint8_t *)(eqe))[0xf]) #define HERMON_EQE_OPERRDATA_GET(eq, eqe) \ htonl(((uint32_t *)(eqe))[4]) +#define HERMON_EQE_FEXCH_PORTNUM_GET(eq, eqe) \ + (((uint8_t *)(eqe))[5] & 0x3) +#define HERMON_EQE_FEXCH_FEXCH_GET(eq, eqe) \ + htons(((uint16_t *)(eqe))[3]) +#define HERMON_EQE_FEXCH_SYNDROME_GET(eq, eqe) \ + (((uint8_t *)(eqe))[15]) + /* * Hermon does ownership of CQ and EQ differently from Arbel & Tavor. * Now, you keep track of the TOTAL number of CQE's or EQE's that have been @@ -1964,10 +2424,9 @@ struct hermon_hw_eqe_s { * does not consume it. */ -#define HERMON_EQE_OWNER_IS_SW(eq, eqe) \ +#define HERMON_EQE_OWNER_IS_SW(eq, eqe, consindx, shift) \ ((((uint8_t *)(eqe))[0x1f] & HERMON_EQE_OWNER_MASK) == \ - (((eq->eq_nexteqe) & eq->eq_bufsz) >> \ - (eq->eq_log_eqsz - HERMON_EQE_OWNER_SHIFT))) + (((consindx) & eq->eq_bufsz) >> (shift))) /* * Hermon Completion Queue Context Table (CQC) entries @@ -2049,7 +2508,7 @@ struct hermon_hw_cqc_s { }; #else struct hermon_hw_cqc_s { - uint32_t status :4; + uint32_t status :4; uint32_t :9; uint32_t cqe_coalesc :1; uint32_t overrun_ignore :1; @@ -2125,9 +2584,9 @@ struct hermon_hw_cqc_s { struct hermon_hw_cqe_s { uint32_t dife :1; - uint32_t :2; + uint32_t vlan :2; uint32_t fl :1; - uint32_t fccrc_sd :1; + uint32_t fcrc_sd :1; uint32_t d2s :1; uint32_t :2; uint32_t my_qpn :24; @@ -2139,10 +2598,10 @@ struct hermon_hw_cqe_s { uint32_t srq_rqpn :24; uint32_t sl :4; - uint32_t :12; - uint32_t slid :16; + uint32_t vid :12; + uint32_t slid :16; /* SMAC 47:32 or SLID */ - uint32_t ipoib_status; + uint32_t ipoib_status; /* SMAC 31:0 or enet/ipoib/EoIB status */ uint32_t byte_cnt; @@ -2235,6 +2694,9 @@ struct hermon_hw_cqe_s { #define HERMON_CQE_ERROR_SYNDROME_GET(cq, cqe) \ (((uint8_t *)(cqe))[27]) +#define HERMON_CQE_ERROR_VENDOR_SYNDROME_GET(cq, cqe) \ + (((uint8_t *)(cqe))[26]) + #define HERMON_CQE_OPCODE_GET(cq, cqe) \ ((((uint8_t *)(cqe))[31]) & HERMON_CQE_OPCODE_MASK) @@ -2242,12 +2704,30 @@ struct hermon_hw_cqe_s { (((((uint8_t *)(cqe))[31]) & HERMON_CQE_SENDRECV_MASK) >> \ HERMON_CQE_SENDRECV_SHIFT) +#define HERMON_CQE_FEXCH_SEQ_CNT(cq, cqe) \ + HERMON_CQE_CKSUM(cq, cqe) + +#define HERMON_CQE_FEXCH_TX_BYTES(cq, cqe) \ + htonl(((uint32_t *)(cqe))[3]) + +#define HERMON_CQE_FEXCH_RX_BYTES(cq, cqe) \ + htonl(((uint32_t *)(cqe))[4]) + +#define HERMON_CQE_FEXCH_SEQ_ID(cq, cqe) \ + (((uint8_t *)(cqe))[8]) + +#define HERMON_CQE_FEXCH_DETAIL(cq, cqe) \ + htonl(((uint32_t *)(cqe))[0]) + +#define HERMON_CQE_FEXCH_DIFE(cq, cqe) \ + ((((uint8_t *)(cqe))[0]) & 0x80) + /* See Comment above for EQE - ownership of CQE is handled the same */ -#define HERMON_CQE_OWNER_IS_SW(cq, cqe, considx) \ +#define HERMON_CQE_OWNER_IS_SW(cq, cqe, considx, shift, mask) \ (((((uint8_t *)(cqe))[31] & HERMON_CQE_OWNER_MASK) >> \ HERMON_CQE_OWNER_SHIFT) == \ - (((considx) & cq->cq_bufsz) >> cq->cq_log_cqsz)) + (((considx) & (mask)) >> (shift))) /* * Hermon Shared Receive Queue (SRQ) Context Entry Format @@ -2297,7 +2777,7 @@ struct hermon_hw_srqc_s { uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */ }; -#else +#else /* BIG ENDIAN */ struct hermon_hw_srqc_s { uint32_t state :4; uint32_t log_srq_size :4; @@ -2349,9 +2829,17 @@ struct hermon_hw_srqc_s { #ifdef _LITTLE_ENDIAN struct hermon_hw_mod_stat_cfg_s { - uint32_t rsvd0; + uint32_t :16; + uint32_t qdr_rx_op :4; + uint32_t :3; + uint32_t qdr_rx_opt_m :1; + uint32_t qdr_tx_op :4; + uint32_t :3; + uint32_t qdr_tx_opt_m :1; - uint32_t :14; + uint32_t log_pg_sz :8; + uint32_t log_pg_sz_m :1; + uint32_t :5; uint32_t dife :1; uint32_t dife_m :1; uint32_t rx_options :4; @@ -2368,7 +2856,7 @@ struct hermon_hw_mod_stat_cfg_s { uint32_t port_en_m :1; uint32_t :10; - uint32_t rsvd1; + uint32_t :32; uint32_t guid_hi; @@ -2376,8 +2864,8 @@ struct hermon_hw_mod_stat_cfg_s { uint32_t guid_hi_m :1; uint32_t guid_lo; - uint32_t :31; + uint32_t :31; uint32_t guid_lo_m :1; uint32_t rsvd[4]; @@ -2405,7 +2893,13 @@ struct hermon_hw_mod_stat_cfg_s { uint32_t :2; uint32_t serdes_m :1; - uint32_t reserved[50]; + uint32_t reserved[22]; + + uint32_t mac_lo :32; + + uint32_t mac_hi :16; + uint32_t :15; + uint32_t mac_m :1; }; #else /* BIG ENDIAN */ struct hermon_hw_mod_stat_cfg_s { @@ -2417,11 +2911,19 @@ struct hermon_hw_mod_stat_cfg_s { uint32_t rx_options :4; uint32_t dife_m :1; uint32_t dife :1; - uint32_t :14; + uint32_t :5; + uint32_t log_pg_sz_m :1; + uint32_t log_pg_sz :8; - uint32_t rsvd0; + uint32_t qdr_tx_opt_m :1; + uint32_t :3; + uint32_t qdr_tx_op :4; + uint32_t qdr_rx_opt_m :1; + uint32_t :3; + uint32_t qdr_rx_op :4; + uint32_t :16; - uint32_t rsvd1; + uint32_t :32; uint32_t :10; uint32_t port_en_m :1; @@ -2465,13 +2967,20 @@ struct hermon_hw_mod_stat_cfg_s { uint32_t :1; uint32_t inbuf_ind_en :3; - uint32_t reserved[50]; + uint32_t reserved[22]; /* get to new enet stuff */ + + uint32_t mac_m :1; + uint32_t :15; + uint32_t mac_hi :16; + + uint32_t mac_lo :32; }; #endif - /* * Hermon MOD_STAT_CFG input modifier structure + * NOTE: this might end up defined ONLY one way, + * if usage is access via macros */ struct hermon_hw_msg_in_mod_s { #ifdef _LITTLE_ENDIAN @@ -2506,14 +3015,14 @@ struct hermon_hw_msg_in_mod_s { #ifdef _LITTLE_ENDIAN struct hermon_hw_udav_s { uint32_t rlid :16; - uint32_t ml_path :7; + uint32_t ml_path :7; /* mlid or SMAC idx */ uint32_t grh :1; uint32_t :8; uint32_t pd :24; uint32_t portnum :2; uint32_t :5; - uint32_t force_lp :1; + uint32_t force_lb :1; uint32_t flow_label :20; uint32_t tclass :8; @@ -2537,7 +3046,7 @@ struct hermon_hw_udav_s { uint32_t :8; uint32_t grh :1; - uint32_t ml_path :7; + uint32_t ml_path :7; /* mlid or SMAC idx */ uint32_t rlid :16; uint32_t :9; @@ -2557,6 +3066,75 @@ struct hermon_hw_udav_s { #define HERMON_UDAV_MODIFY_MASK0 0xFCFFFFFFFF000000ULL #define HERMON_UDAV_MODIFY_MASK1 0xFF80F00000000000ULL +/* UDAV for enthernet */ + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_udav_enet_s { + uint32_t :16; + uint32_t smac_idx :7; + uint32_t :9; + + uint32_t pd :24; + uint32_t portnum :2; + uint32_t :3; + uint32_t cv :1; + uint32_t :1; + uint32_t force_lb :1; + + uint32_t flow_label :20; + uint32_t tclass :8; + uint32_t sl :4; + + uint32_t hop_limit :8; + uint32_t max_stat_rate :4; + uint32_t :4; + uint32_t mgid_index :7; + uint32_t :9; + + uint64_t rgid_h; + uint64_t rgid_l; + + uint32_t rsrv[2]; + + uint32_t dmac_lo; + + uint32_t dmac_hi :16; + uint32_t vlan :16; +}; +#else +struct hermon_hw_udav_enet_s { + uint32_t force_lb :1; + uint32_t :1; + uint32_t cv :1; + uint32_t :3; + uint32_t portnum :2; + uint32_t pd :24; + + uint32_t :9; + uint32_t smac_idx :7; + uint32_t :16; + + uint32_t :9; + uint32_t mgid_index :7; + uint32_t :4; + uint32_t max_stat_rate :4; + uint32_t hop_limit :8; + + uint32_t sl :4; + uint32_t tclass :8; + uint32_t flow_label :20; + + uint64_t rgid_h; + uint64_t rgid_l; + + uint32_t rsrv[2]; + + uint32_t vlan :16; + uint32_t dmac_hi :16; + + uint32_t dmac_low; +}; +#endif /* * Hermon Queue Pair Context Table (QPC) entries @@ -2588,61 +3166,185 @@ struct hermon_hw_udav_s { #ifdef _LITTLE_ENDIAN struct hermon_hw_addr_path_s { uint32_t rlid :16; - uint32_t mlid :7; + uint32_t mlid :7; /* mlid or SMAC idx */ uint32_t grh :1; uint32_t cntr_idx :8; uint32_t pkey_indx :7; uint32_t :22; - uint32_t :2; /* but may be used for enet */ + uint32_t :1; /* but may be used for enet */ + uint32_t cv :1; uint32_t force_lb :1; uint32_t flow_label :20; uint32_t tclass :8; - uint32_t :4; + uint32_t sniff_s_in :1; + uint32_t sniff_s_out :1; + uint32_t sniff_r_in :1; + uint32_t sniff_r_out :1; /* sniff-rcv-egress */ uint32_t hop_limit :8; uint32_t max_stat_rate :4; uint32_t :4; uint32_t mgid_index :7; - uint32_t :4; + uint32_t :1; + uint32_t link_type :3; uint32_t ack_timeout :5; uint64_t rgid_h; uint64_t rgid_l; - uint32_t :32; /* but may be used for enet */ + uint32_t dmac_hi :16; + uint32_t :16; - uint32_t :12; /* but may be used for enet */ + uint32_t :8; /* but may be used for enet */ + uint32_t sp :1; + uint32_t :2; + uint32_t fvl :1; uint32_t fsip :1; - uint32_t :3; - uint32_t :7; + uint32_t fsm :1; + uint32_t :2; + uint32_t vlan_idx :7; uint32_t :1; uint32_t sched_q :8; - - uint32_t :32; + uint32_t dmac_lo :32; }; #else struct hermon_hw_addr_path_s { uint32_t force_lb :1; - uint32_t :2; /* but may be used for enet */ + uint32_t cv :1; + uint32_t :1; /* but may be used for enet */ uint32_t :22; uint32_t pkey_indx :7; uint32_t cntr_idx :8; uint32_t grh :1; - uint32_t mlid :7; + uint32_t mlid :7; /* mlid or SMAC idx */ uint32_t rlid :16; uint32_t ack_timeout :5; - uint32_t :4; + uint32_t link_type :3; + uint32_t :1; uint32_t mgid_index :7; uint32_t :4; uint32_t max_stat_rate :4; uint32_t hop_limit :8; + uint32_t sniff_r_out :1; /* sniff-rcv-egress */ + uint32_t sniff_r_in :1; + uint32_t sniff_s_out :1; + uint32_t sniff_s_in :1; + uint32_t tclass :8; + uint32_t flow_label :20; + + uint64_t rgid_h; + uint64_t rgid_l; + + uint32_t sched_q :8; + uint32_t :1; + uint32_t vlan_idx :7; + uint32_t :2; + uint32_t fsm :1; + uint32_t fsip :1; + uint32_t fvl :1; + uint32_t :2; + uint32_t sp :1; + uint32_t :8; /* but may be used for enet */ + + uint32_t :16; + uint32_t dmac_hi :16; + + uint32_t dmac_lo :32; +}; +#endif /* LITTLE ENDIAN */ + +/* The addr path includes RSS fields for RSS QPs */ +#ifdef _LITTLE_ENDIAN +struct hermon_hw_rss_s { + uint32_t rlid :16; + uint32_t mlid :7; + uint32_t grh :1; + uint32_t cntr_idx :8; + + uint32_t pkey_indx :7; + uint32_t :22; + uint32_t :1; /* but may be used for enet */ + uint32_t cv :1; + uint32_t force_lb :1; + + uint32_t flow_label :20; + uint32_t tclass :8; + uint32_t sniff_s_in :1; + uint32_t sniff_s_out :1; + uint32_t sniff_r_in :1; + uint32_t sniff_r_out :1; /* sniff-rcv-egress */ + + uint32_t hop_limit :8; + uint32_t max_stat_rate :4; uint32_t :4; + uint32_t mgid_index :7; + uint32_t :1; + uint32_t link_type :3; + uint32_t ack_timeout :5; + + uint64_t rgid_h; + uint64_t rgid_l; + + uint32_t base_qpn :24; + uint32_t log2_tbl_sz :4; + uint32_t :4; + + uint32_t :8; /* but may be used for enet */ + uint32_t sp :1; + uint32_t :2; + uint32_t fvl :1; + uint32_t fsip :1; + uint32_t fsm :1; + uint32_t :2; + uint32_t vlan_idx :7; + uint32_t :1; + uint32_t sched_q :8; + + uint32_t :2; + uint32_t tcp_ipv6 :1; + uint32_t ipv6 :1; + uint32_t tcp_ipv4 :1; + uint32_t ipv4 :1; + uint32_t :2; + uint32_t hash_fn :2; + uint32_t :22; + + uint32_t default_qpn :24; + uint32_t :8; + + uint8_t rss_key[40]; +}; +#else /* BIG ENDIAN */ +struct hermon_hw_rss_s { + uint32_t force_lb :1; + uint32_t cv :1; + uint32_t :1; /* but may be used for enet */ + uint32_t :22; + uint32_t pkey_indx :7; + + uint32_t cntr_idx :8; + uint32_t grh :1; + uint32_t mlid :7; + uint32_t rlid :16; + + uint32_t ack_timeout :5; + uint32_t link_type :3; + uint32_t :1; + uint32_t mgid_index :7; + uint32_t :4; + uint32_t max_stat_rate :4; + uint32_t hop_limit :8; + + uint32_t sniff_r_out :1; /* sniff-rcv-egress */ + uint32_t sniff_r_in :1; + uint32_t sniff_s_out :1; + uint32_t sniff_s_in :1; uint32_t tclass :8; uint32_t flow_label :20; @@ -2651,14 +3353,32 @@ struct hermon_hw_addr_path_s { uint32_t sched_q :8; uint32_t :1; - uint32_t :7; - uint32_t :3; + uint32_t vlan_idx :7; + uint32_t :2; + uint32_t fsm :1; uint32_t fsip :1; - uint32_t :12; /* but may be used for enet */ + uint32_t fvl :1; + uint32_t :2; + uint32_t sp :1; + uint32_t :8; /* but may be used for enet */ - uint32_t :32; /* but may be used for enet */ + uint32_t :4; + uint32_t log2_tbl_sz :4; + uint32_t base_qpn :24; - uint32_t :32; + uint32_t :8; + uint32_t default_qpn :24; + + uint32_t :22; + uint32_t hash_fn :2; + uint32_t :2; + uint32_t ipv4 :1; + uint32_t tcp_ipv4 :1; + uint32_t ipv6 :1; + uint32_t tcp_ipv6 :1; + uint32_t :2; + + uint8_t rss_key[40]; }; #endif /* LITTLE ENDIAN */ @@ -2756,7 +3476,7 @@ struct hermon_hw_qpc_s { uint32_t cqn_rcv :24; uint32_t :8; - uint32_t srcd :16; + uint32_t xrcd :16; uint32_t :16; uint32_t :2; @@ -2785,7 +3505,7 @@ struct hermon_hw_qpc_s { uint32_t rmc_parent_qpn :24; uint32_t header_sep :1; - uint32_t inline_scatter :1; /* m/b 0 for srq */ + uint32_t inline_scatter :1; /* m/b 0 for srq */ uint32_t :1; uint32_t rmc_enable :2; uint32_t :2; /* may use one bit for enet */ @@ -2799,7 +3519,22 @@ struct hermon_hw_qpc_s { uint32_t log2_pgsz :6; uint32_t :2; - uint32_t rsvd[12]; /* may/will be used for FCoIB */ + uint32_t exch_base :16; + uint32_t exch_size :4; + uint32_t :12; + + uint32_t vft_vf_id :12; + uint32_t vft_prior :3; + uint32_t :16; + uint32_t ve :1; + + uint32_t :32; + + uint32_t :16; + uint32_t my_fc_id_idx :8; + uint32_t vft_hop_cnt :8; + + uint32_t rsvd[8]; }; #else /* BIG ENDIAN */ struct hermon_hw_qpc_s { @@ -2886,7 +3621,7 @@ struct hermon_hw_qpc_s { uint32_t next_rcv_psn :24; uint32_t :16; - uint32_t srcd :16; + uint32_t xrcd :16; uint32_t :8; uint32_t cqn_rcv :24; @@ -2916,7 +3651,7 @@ struct hermon_hw_qpc_s { uint32_t :2; /* may use one bit for enet */ uint32_t rmc_enable :2; uint32_t :1; - uint32_t inline_scatter :1; /* m/b 0 for srq */ + uint32_t inline_scatter :1; /* m/b 0 for srq */ uint32_t header_sep :1; uint32_t rmc_parent_qpn :24; @@ -2931,7 +3666,22 @@ struct hermon_hw_qpc_s { uint32_t mtt_base_addrl :29; uint32_t :3; - uint32_t rsvd[12]; /* may/will be used for FCoIB */ + uint32_t ve :1; + uint32_t :16; + uint32_t vft_prior :3; + uint32_t vft_vf_id :12; + + uint32_t :12; + uint32_t exch_size :4; + uint32_t exch_base :16; + + uint32_t vft_hop_cnt :8; + uint32_t my_fc_id_idx :8; + uint32_t :16; + + uint32_t :32; + + uint32_t rsvd[8]; }; #endif /* LITTLE ENDIAN */ @@ -2951,7 +3701,11 @@ struct hermon_hw_qpc_s { #define HERMON_QP_RC 0x0 #define HERMON_QP_UC 0x1 #define HERMON_QP_UD 0x3 +#define HERMON_QP_FCMND 0x4 +#define HERMON_QP_FEXCH 0x5 +#define HERMON_QP_XRC 0x6 #define HERMON_QP_MLX 0x7 +#define HERMON_QP_RFCI 0x9 #define HERMON_QP_PMSTATE_MIGRATED 0x3 #define HERMON_QP_PMSTATE_ARMED 0x0 @@ -2999,7 +3753,8 @@ struct hermon_hw_qpc_s { #ifdef _LITTLE_ENDIAN struct hermon_hw_mcg_s { uint32_t member_cnt :24; - uint32_t :8; + uint32_t :6; + uint32_t protocol :2; uint32_t :6; uint32_t next_gid_indx :26; @@ -3015,7 +3770,8 @@ struct hermon_hw_mcg_s { uint32_t next_gid_indx :26; uint32_t :6; - uint32_t :8; + uint32_t protocol :2; + uint32_t :6; uint32_t member_cnt :24; uint32_t :32; @@ -3026,6 +3782,58 @@ struct hermon_hw_mcg_s { }; #endif +#ifdef _LITTLE_ENDIAN +struct hermon_hw_mcg_en_s { + uint32_t member_cnt :24; + uint32_t :6; + uint32_t protocol :2; + + uint32_t :6; + uint32_t next_gid_indx :26; + + uint32_t :32; + uint32_t :32; + + uint32_t vlan_present :1; + uint32_t :31; + + uint32_t :32; + + uint32_t mac_lo :32; + + uint32_t mac_hi :16; + uint32_t vlan_id :12; + uint32_t vlan_cfi :1; + uint32_t vlan_prior :3; + +}; +#else +struct hermon_hw_mcg_en_s { + uint32_t next_gid_indx :26; + uint32_t :6; + + uint32_t protocol :2; + uint32_t :6; + uint32_t member_cnt :24; + + uint32_t :32; + uint32_t :32; + + uint32_t :32; + + uint32_t :31; + uint32_t vlan_present :1; + + uint32_t vlan_prior :3; + uint32_t vlan_cfi :1; + uint32_t vlan_id :12; + uint32_t mac_hi :16; + + uint32_t mac_lo :32; + +}; +#endif + /* Multicast Group Member - QP List entries */ #ifdef _LITTLE_ENDIAN @@ -3047,6 +3855,152 @@ struct hermon_hw_mcg_qp_list_s { #define HERMON_MCG_QPN_BLOCK_LB 0x40000000 /* + * ETHERNET ONLY Commands + * The follow are new commands, used only for an Ethernet Port + */ + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_set_mcast_fltr_s { + uint32_t mac_lo; + + uint32_t mac_hi :16; + uint32_t :15; + uint32_t sfs :1; +}; +#else /* BIG ENDIAN */ +struct hermon_hw_set_mcast_fltr_s { + uint32_t sfs :1; + uint32_t :15; + uint32_t mac_hi :16; + + uint32_t mac_lo; +}; +#endif + +/* opmod for set_mcast_fltr */ +#define HERMON_SET_MCAST_FLTR_CONF 0x0 +#define HERMON_SET_MCAST_FLTR_DIS 0x1 +#define HERMON_SET_MCAST_FLTR_EN 0x2 + + +/* + * FC Command structures + */ + + + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_config_fc_basic_s { + uint32_t n_p :2; + uint32_t :6; + uint32_t n_v :3; + uint32_t :5; + uint32_t n_m :4; + uint32_t :12; + + uint32_t :16; + uint32_t fexch_base_hi :8; + uint32_t :8; + + uint32_t rfci_base :24; + uint32_t log2_num_rfci :3; + uint32_t :5; + + uint32_t fx_base_mpt_lo :8; + uint32_t :17; + uint32_t fx_base_mpt_hi :7; + + uint32_t fcoe_prom_qpn :24; + uint32_t uint32_t :8; + + uint32_t :32; + + uint32_t rsrv[58]; +}; +#else +struct hermon_hw_config_fc_basic_s { + uint32_t :8; + uint32_t fexch_base_hi :8; + uint32_t :16; + + uint32_t :12; + uint32_t n_m :4; + uint32_t :5; + uint32_t n_v :3; + uint32_t :6; + uint32_t n_p :2; + + uint32_t fx_base_mpt_hi :7; + uint32_t :17; + uint32_t fx_base_mpt_lo :8; + + uint32_t :5; + uint32_t log2_num_rfci :3; + uint32_t rfci_base :24; + + uint32_t :32; + + uint32_t uint32_t :8; + uint32_t fcoe_prom_qpn :24; + + uint32_t rsrv[58]; +}; +#endif + +#define HERMON_HW_FC_PORT_ENABLE 0x0 +#define HERMON_HW_FC_PORT_DISABLE 0x1 +#define HERMON_HW_FC_CONF_BASIC 0x0000 +#define HERMON_HW_FC_CONF_NPORT 0x0100 + +#ifdef _LITTLE_ENDIAN +struct hermon_hw_query_fc_s { + uint32_t :32; + + uint32_t log2_max_rfci :3; + uint32_t :5; + uint32_t log2_max_fexch :5; + uint32_t :3; + uint32_t log2_max_nports :3; + uint32_t :13; + + uint32_t rsrv[62]; +}; +#else +struct hermon_hw_query_fc_s { + uint32_t :13; + uint32_t log2_max_nports :3; + uint32_t :3; + uint32_t log2_max_fexch :5; + uint32_t :5; + uint32_t log2_max_rfci :3; + + uint32_t :32; + + uint32_t rsrv[62]; +}; +#endif + + + + +/* ARM_RQ - limit water mark for srq & rq */ +#ifdef _LITTLE_ENDIAN +struct hermon_hw_arm_req_s { + uint32_t lwm :16; + uint32_t :16; + + uint32_t :32; +}; +#else +struct hermon_hw_arm_req_s { + uint32_t :32; + + uint32_t :16; + uint32_t lwm :16; +}; +#endif + +/* * Structure for getting the peformance counters from the HCA */ @@ -3380,25 +4334,39 @@ typedef struct hermon_hw_cq_arm_db_s { struct hermon_hw_snd_wqe_ctrl_s { uint32_t owner :1; - /* NOTE: some/many may be used by enet */ - uint32_t :26; + uint32_t :1; + uint32_t nec :1; + uint32_t :5; + uint32_t fceof :8; + uint32_t :9; + uint32_t rr :1; + uint32_t :1; uint32_t opcode :5; - /* NOTE: some will be used by enet */ - uint32_t :25; + + uint32_t vlan :16; + uint32_t :1; + uint32_t cv :1; + uint32_t :7; uint32_t fence :1; - /* WQE size in octowords */ - uint32_t ds :6; - /* SRC remote buffer if impl */ - uint32_t src_rem_buf :24; + uint32_t ds :6; /* WQE size in octowords */ + + /* + * XRC remote buffer if impl + * XRC 23:0, or DMAC 47:32& 8 bits of pad + */ + uint32_t xrc_rem_buf :24; uint32_t so :1; - uint32_t :1; /* FCoIB only */ + uint32_t fcrc :1; /* fc crc calc */ uint32_t tcp_udp :1; /* Checksumming */ uint32_t ip :1; /* Checksumming */ uint32_t cq_gen :2; /* 00=no cqe, 11= gen cqe */ - /* set means solicit bit in last packet */ + /* s-bit set means solicit bit in last packet */ uint32_t s :1; uint32_t force_lb :1; + /* + * immediate OR invalidation key OR DMAC 31:0 depending + */ uint32_t immediate :32; }; @@ -3410,6 +4378,96 @@ struct hermon_hw_srq_wqe_next_s { }; +struct hermonw_hw_fcp3_ctrl_s { + uint32_t owner :1; + uint32_t :1; + uint32_t nec :1; + uint32_t :24; + uint32_t opcode :5; + + uint32_t :24; + uint32_t sit :1; + uint32_t :1; + uint32_t ds :6; + + uint32_t seq_id :8; + uint32_t info :4; + uint32_t :3; + uint32_t ls :1; + uint32_t :8; + uint32_t so :1; + uint32_t :3; + uint32_t cq_gen :2; + uint32_t :2; + + uint32_t param :32; +}; + +struct hermon_hw_fcp3_init_s { + uint32_t :8; + uint32_t pe :1; + uint32_t :23; + + uint32_t csctl_prior :8; + uint32_t seqid_tx :8; + uint32_t :6; + uint32_t mtu :10; + + uint32_t rem_id :24; + uint32_t abort :2; + uint32_t :1; + uint32_t op :2; + uint32_t :1; + uint32_t org :1; + uint32_t :1; + + uint32_t rem_exch :16; + uint32_t loc_exch_idx :16; +}; + +struct hermon_hw_fcmd_o_enet_s { + uint32_t :4; + uint32_t stat_rate :4; + uint32_t :24; + + uint32_t :32; + + uint32_t :16; + uint32_t dmac_hi :16; + + uint32_t dmac_lo :32; +}; + +struct hermon_hw_fcmd_o_ib_s { + uint32_t :32; + + uint32_t :8; + uint32_t grh :1; + uint32_t :7; + uint32_t rlid :16; + + uint32_t :20; + uint32_t stat_rate :4; + uint32_t hop_limit :8; + + uint32_t sl :4; + uint32_t tclass :8; + uint32_t flow_label :20; + + uint64_t rgid_hi; + + uint64_t rgid_lo; + + uint32_t :8; + uint32_t rqp :24; + + uint32_t rsrv[3]; +}; + + + + + #define HERMON_WQE_SEND_FENCE_MASK 0x40 #define HERMON_WQE_SEND_NOPCODE_NOP 0x00 @@ -3418,6 +4476,7 @@ struct hermon_hw_srq_wqe_next_s { #define HERMON_WQE_SEND_NOPCODE_RDMAWI 0x9 #define HERMON_WQE_SEND_NOPCODE_SEND 0xA #define HERMON_WQE_SEND_NOPCODE_SENDI 0xB +#define HERMON_WQE_SEND_NOPCODE_INIT_AND_SEND 0xD #define HERMON_WQE_SEND_NOPCODE_LSO 0xE #define HERMON_WQE_SEND_NOPCODE_RDMAR 0x10 #define HERMON_WQE_SEND_NOPCODE_ATMCS 0x11 @@ -3429,6 +4488,9 @@ struct hermon_hw_srq_wqe_next_s { #define HERMON_WQE_SEND_NOPCODE_LCL_INV 0x1B #define HERMON_WQE_SEND_NOPCODE_CONFIG 0x1F /* for ccq only */ +#define HERMON_WQE_FCP_OPCODE_INIT_AND_SEND 0xD +#define HERMON_WQE_FCP_OPCODE_INIT_FEXCH 0xC + #define HERMON_WQE_SEND_SIGNALED_MASK 0x0000000C00000000ull #define HERMON_WQE_SEND_SOLICIT_MASK 0x0000000200000000ull #define HERMON_WQE_SEND_IMMEDIATE_MASK 0x0000000100000000ull @@ -3438,9 +4500,13 @@ struct hermon_hw_snd_wqe_ud_s { uint32_t :8; uint32_t dest_qp :24; + uint32_t qkey :32; - uint32_t :32; - uint32_t :32; + + uint32_t vlan :16; + uint32_t dmac_hi :16; + + uint32_t dmac_lo :32; }; #define HERMON_WQE_SENDHDR_UD_AV_MASK 0xFFFFFFFFFFFFFFE0ull #define HERMON_WQE_SENDHDR_UD_DQPN_MASK 0xFFFFFF @@ -3466,6 +4532,12 @@ struct hermon_hw_snd_wqe_bind_s { #define HERMON_WQE_SENDHDR_BIND_WR 0x4000000000000000ull #define HERMON_WQE_SENDHDR_BIND_RD 0x2000000000000000ull +struct hermon_hw_snd_wqe_lso_s { + uint32_t mss :16; + uint32_t :6; + uint32_t hdr_size :10; +}; + struct hermon_hw_snd_wqe_remaddr_s { uint64_t vaddr; uint32_t rkey; @@ -3484,8 +4556,6 @@ struct hermon_hw_snd_wqe_atomic_ext_s { uint64_t cmpmask; }; - - struct hermon_hw_snd_wqe_local_inv_s { uint32_t :6; uint32_t atc_shoot :1; @@ -3495,16 +4565,25 @@ struct hermon_hw_snd_wqe_local_inv_s { uint32_t mkey; + uint32_t rsrv0; + + uint32_t rsrv1; uint32_t :25; uint32_t guest_id :7; /* for atc shootdown */ - uint32_t rsrv0[6]; - uint32_t p_addrh; uint32_t p_addrl :23; uint32_t :9; }; +struct hermon_hw_snd_rem_addr_s { + uint64_t rem_vaddr; + + uint32_t rkey; + uint32_t rsrv; +}; + + struct hermon_hw_snd_wqe_frwr_s { uint32_t rem_atomic :1; uint32_t rem_write :1; @@ -3513,7 +4592,8 @@ struct hermon_hw_snd_wqe_frwr_s { uint32_t loc_read :1; uint32_t fbo_en :1; uint32_t len_64 :1; - uint32_t :3; /* but some for FCoIB */ + uint32_t :2; + uint32_t dif :1; /* FCoIB */ uint32_t bind_en :1; uint32_t blk_pg_mode :1; uint32_t mtt_rep :4; @@ -3521,10 +4601,7 @@ struct hermon_hw_snd_wqe_frwr_s { uint32_t mkey; /* swapped w/ addrh relative to arbel */ - uint32_t pbl_addrh; - - uint32_t pbl_addrl :26; - uint32_t :6; + uint64_t pbl_addr; uint64_t start_addr; @@ -3539,15 +4616,25 @@ struct hermon_hw_snd_wqe_frwr_s { uint32_t rsrv0[2]; }; -/* - * NOTE: Some hermon-PRM defined Send WQE segments are not defined here - * because they will not be used initially: they should be added and - * used later on: - * FCP-3 init - * FCP-3 Control - * Large Send Offload - * - */ +struct hermon_hw_snd_wqe_frwr_ext_s { + uint32_t dif_in_mem :1; + uint32_t dif_on_wire :1; + uint32_t valid_ref :1; + uint32_t valid_crc :1; + uint32_t repl_ref_tag :1; + uint32_t repl_app_tag :1; + uint32_t :10; + uint32_t app_mask :16; + + uint32_t wire_app_tag :16; + uint32_t mem_app_tag :16; + + uint32_t wire_ref_tag_base; + + uint32_t mem_ref_tag_base; +}; + + /* * Hermon "MLX transport" Work Queue Element (WQE) @@ -3704,7 +4791,7 @@ struct hermon_hw_wqe_sgl_s { tmp[1] = htonll((uint64_t)(wr_rdma)->rdma_rkey << 32); \ } -#define HERMON_WQE_BUILD_RC_ATOMIC_REMADDR(qp, rc, wr) \ +#define HERMON_WQE_BUILD_RC_ATOMIC_REMADDR(qp, rc, wr) \ { \ uint64_t *tmp; \ \ @@ -3713,7 +4800,7 @@ struct hermon_hw_wqe_sgl_s { tmp[1] = htonll((uint64_t)(wr)->wr.rc.rcwr.atomic->atom_rkey << 32); \ } -#define HERMON_WQE_BUILD_ATOMIC(qp, at, wr_atom) \ +#define HERMON_WQE_BUILD_ATOMIC(qp, at, wr_atom) \ { \ uint64_t *tmp; \ \ @@ -3722,7 +4809,7 @@ struct hermon_hw_wqe_sgl_s { tmp[1] = htonll((wr_atom)->atom_arg1); \ } -#define HERMON_WQE_BUILD_BIND(qp, bn, wr_bind) \ +#define HERMON_WQE_BUILD_BIND(qp, bn, wr_bind) \ { \ uint64_t *tmp; \ uint64_t bn0_tmp; \ @@ -3743,16 +4830,67 @@ struct hermon_hw_wqe_sgl_s { tmp[3] = htonll((wr_bind)->bind_len); \ } -#define HERMON_WQE_BUILD_DATA_SEG_RECV(ds, sgl) \ +#define HERMON_WQE_BUILD_FRWR(qp, frwr_arg, pmr_arg) \ +{ \ + ibt_mr_flags_t flags; \ + ibt_lkey_t lkey; \ + ibt_wr_reg_pmr_t *pmr = (pmr_arg); \ + uint64_t *frwr64 = (uint64_t *)(frwr_arg); \ + \ + flags = pmr->pmr_flags; \ + ((uint32_t *)frwr64)[0] = htonl(0x08000000 | \ + ((flags & IBT_MR_ENABLE_REMOTE_ATOMIC) ? 0x80000000 : 0) | \ + ((flags & IBT_MR_ENABLE_REMOTE_WRITE) ? 0x40000000 : 0) | \ + ((flags & IBT_MR_ENABLE_REMOTE_READ) ? 0x20000000 : 0) | \ + ((flags & IBT_MR_ENABLE_LOCAL_WRITE) ? 0x10000000 : 0) | \ + ((flags & IBT_MR_ENABLE_WINDOW_BIND) ? 0x00200000 : 0)); \ + lkey = (pmr->pmr_lkey & ~0xff) | pmr->pmr_key; \ + pmr->pmr_rkey = pmr->pmr_lkey = lkey; \ + ((uint32_t *)frwr64)[1] = htonl(lkey); \ + frwr64[1] = htonll(pmr->pmr_addr_list->p_laddr); \ + frwr64[2] = htonll(pmr->pmr_iova); \ + frwr64[3] = htonll(pmr->pmr_len); \ + ((uint32_t *)frwr64)[8] = htonl(pmr->pmr_offset); \ + ((uint32_t *)frwr64)[9] = htonl(pmr->pmr_buf_sz); \ + frwr64[5] = 0; \ +} + +#define HERMON_WQE_BUILD_LI(qp, li_arg, wr_li) \ +{ \ + uint64_t *li64 = (uint64_t *)(void *)(li_arg); \ + \ + li64[0] = 0; \ + ((uint32_t *)li64)[2] = htonl((wr_li)->li_rkey); \ + ((uint32_t *)li64)[3] = 0; \ + li64[2] = 0; \ + li64[3] = 0; \ +} + +#define HERMON_WQE_BUILD_FCP3_INIT(ds, fctl, cs_pri, seq_id, mtu, \ + dest_id, op, rem_exch, local_exch_idx) \ +{ \ + uint32_t *fc_init; \ + \ + fc_init = (uint32_t *)ds; \ + fc_init[1] = htonl((cs_pri) << 24 | (seq_id) << 16 | (mtu)); \ + fc_init[2] = htonl((dest_id) << 8 | \ + IBT_FCTL_GET_ABORT_FIELD(fctl) << 6 | (op) << 3 | 0x2); \ + fc_init[3] = htonl((rem_exch) << 16 | (local_exch_idx)); \ + membar_producer(); /* fc_init[0] is where the stamping is */ \ + fc_init[0] = htonl(((fctl) & IBT_FCTL_PRIO) << 6); \ +} + +#define HERMON_WQE_BUILD_DATA_SEG_RECV(ds, sgl) \ { \ uint64_t *tmp; \ \ tmp = (uint64_t *)(ds); \ - tmp[0] = htonll((((uint64_t)((sgl)->ds_len & \ + tmp[0] = htonll((((uint64_t)((sgl)->ds_len & \ HERMON_WQE_SGL_BYTE_CNT_MASK) << 32) | (sgl)->ds_key)); \ - tmp[1] = htonll((sgl)->ds_va); \ + tmp[1] = htonll((sgl)->ds_va); \ } -#define HERMON_WQE_BUILD_DATA_SEG_SEND(ds, sgl) \ + +#define HERMON_WQE_BUILD_DATA_SEG_SEND(ds, sgl) \ { \ ((uint64_t *)(ds))[1] = htonll((sgl)->ds_va); \ ((uint32_t *)(ds))[1] = htonl((sgl)->ds_key); \ @@ -3764,17 +4902,18 @@ struct hermon_hw_wqe_sgl_s { #define HERMON_WQE_BUILD_INLINE(qp, ds, sz) \ *(uint32_t *)(ds) = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz)) -#define HERMON_WQE_BUILD_INLINE_ICRC(qp, ds, sz, icrc) \ +#define HERMON_WQE_BUILD_INLINE_ICRC(qp, ds, sz, icrc) \ { \ uint32_t *tmp; \ \ tmp = (uint32_t *)(ds); \ - tmp[0] = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz)); \ tmp[1] = htonl(icrc); \ + membar_producer(); \ + tmp[0] = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz)); \ } #define HERMON_WQE_SET_CTRL_SEGMENT(desc, desc_sz, fence, \ - imm, sol, sig, ip_cksum, qp) \ + imm, sol, sig, cksum, qp, strong, fccrc) \ { \ uint32_t *tmp; \ uint32_t cntr_tmp; \ @@ -3783,11 +4922,7 @@ struct hermon_hw_wqe_sgl_s { tmp = (uint32_t *)desc; \ cntr_tmp = (fence << 6) | desc_sz; \ tmp[1] = ntohl(cntr_tmp); \ - cntr_tmp = 0; \ - if ((sol) != 0) cntr_tmp |= 0x02; \ - if ((sig) != 0) cntr_tmp |= 0x0C; \ - /*LINTED*/ \ - if (ip_cksum) cntr_tmp |= 0x30; \ + cntr_tmp = strong | fccrc | sol | sig | cksum; \ tmp[2] = ntohl(cntr_tmp); \ tmp[3] = ntohl(imm); \ } @@ -3804,13 +4939,11 @@ struct hermon_hw_wqe_sgl_s { cntr_tmp |= HERMON_WQE_SEND_NOPCODE_SEND; \ tmp[0] = ntohl(cntr_tmp); \ tmp[1] = ntohl(desc_sz); \ - cntr_tmp = ((maxstat << 4) | (sl & 0xff)) << 8; \ + cntr_tmp = (((maxstat << 4) | (sl & 0xff)) << 8) | sig; \ if (qp->qp_is_special == HERMON_QP_SMI) \ cntr_tmp |= (0x02 << 16); \ if (lid == IB_LID_PERMISSIVE) \ cntr_tmp |= (0x01 << 16); \ - if ((sig) != 0) \ - cntr_tmp |= 0xC; \ tmp[2] = ntohl(cntr_tmp); \ tmp[3] = ntohl((lid) << 16); \ } @@ -3851,7 +4984,7 @@ struct hermon_hw_wqe_sgl_s { * Also note: Filling in the GIDs in the way we do below is helpful because * it avoids potential alignment restrictions and/or conflicts. */ -#define HERMON_WQE_BUILD_MLX_GRH(state, grh, qp, udav, pktlen) \ +#define HERMON_WQE_BUILD_MLX_GRH(state, grh, qp, udav, pktlen) \ { \ uint32_t *tmp; \ uint32_t grh_tmp; \ @@ -3877,7 +5010,7 @@ struct hermon_hw_wqe_sgl_s { bcopy(&(udav)->rgid_h, &tmp[6], sizeof (ib_gid_t)); \ } -#define HERMON_WQE_BUILD_MLX_BTH(state, bth, qp, wr) \ +#define HERMON_WQE_BUILD_MLX_BTH(state, bth, qp, wr) \ { \ uint32_t *tmp; \ uint32_t bth_tmp; \ @@ -3900,7 +5033,7 @@ struct hermon_hw_wqe_sgl_s { tmp[2] = 0x0; \ } -#define HERMON_WQE_BUILD_MLX_DETH(deth, qp) \ +#define HERMON_WQE_BUILD_MLX_DETH(deth, qp) \ { \ uint32_t *tmp; \ \ @@ -3916,10 +5049,6 @@ struct hermon_hw_wqe_sgl_s { } - - - - /* * Flash interface: * Below we have PCI config space space offsets for flash interface diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_misc.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_misc.h index 7b137259cd..8defda65a8 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_misc.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_misc.h @@ -20,8 +20,7 @@ */ /* - * Copyright 2010 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_ADAPTERS_HERMON_MISC_H @@ -566,56 +565,61 @@ typedef struct hermon_loopback_state_s { * Mellanox FMR */ typedef struct hermon_fmr_list_s { - avl_node_t fmr_avlnode; struct hermon_fmr_list_s *fmr_next; hermon_mrhdl_t fmr; - ibt_pmr_desc_t fmr_desc; hermon_fmrhdl_t fmr_pool; - uint_t fmr_refcnt; uint_t fmr_remaps; - uint_t fmr_in_cache; + uint_t fmr_remap_gen; /* generation */ } hermon_fmr_list_t; struct hermon_sw_fmr_s { hermon_state_t *fmr_state; kmutex_t fmr_lock; - ddi_taskq_t *fmr_taskq; + hermon_fmr_list_t *fmr_free_list; + hermon_fmr_list_t **fmr_free_list_tail; + int fmr_free_len; + int fmr_pool_size; + int fmr_max_pages; + int fmr_flags; + int fmr_stat_register; ibt_fmr_flush_handler_t fmr_flush_function; void *fmr_flush_arg; - int fmr_pool_size; - int fmr_max_pages; + int fmr_max_remaps; + uint_t fmr_remap_gen; /* generation */ int fmr_page_sz; - int fmr_dirty_watermark; - int fmr_dirty_len; - int fmr_flags; - hermon_fmr_list_t *fmr_free_list; - hermon_fmr_list_t *fmr_dirty_list; + kmutex_t remap_lock; + hermon_fmr_list_t *fmr_remap_list; + hermon_fmr_list_t **fmr_remap_list_tail; + int fmr_remap_watermark; + int fmr_remap_len; - int fmr_cache; - avl_tree_t fmr_cache_avl; - kmutex_t fmr_cachelock; + kmutex_t dirty_lock; + hermon_fmr_list_t *fmr_dirty_list; + hermon_fmr_list_t **fmr_dirty_list_tail; + int fmr_dirty_watermark; + int fmr_dirty_len; }; _NOTE(MUTEX_PROTECTS_DATA(hermon_sw_fmr_s::fmr_lock, - hermon_sw_fmr_s::fmr_state hermon_sw_fmr_s::fmr_pool_size - hermon_sw_fmr_s::fmr_max_pages hermon_sw_fmr_s::fmr_page_sz + hermon_sw_fmr_s::fmr_flags + hermon_sw_fmr_s::fmr_free_list)) +_NOTE(MUTEX_PROTECTS_DATA(hermon_sw_fmr_s::dirty_lock, hermon_sw_fmr_s::fmr_dirty_watermark hermon_sw_fmr_s::fmr_dirty_len - hermon_sw_fmr_s::fmr_flags - hermon_sw_fmr_s::fmr_free_list - hermon_sw_fmr_s::fmr_dirty_list - hermon_sw_fmr_s::fmr_cache)) - -_NOTE(MUTEX_PROTECTS_DATA(hermon_sw_fmr_s::fmr_cachelock, - hermon_sw_fmr_s::fmr_cache_avl)) + hermon_sw_fmr_s::fmr_dirty_list)) +_NOTE(DATA_READABLE_WITHOUT_LOCK(hermon_sw_fmr_s::fmr_remap_gen + hermon_sw_fmr_s::fmr_state + hermon_sw_fmr_s::fmr_max_pages + hermon_sw_fmr_s::fmr_max_remaps)) -#define HERMON_FMR_MAX_REMAPS 128 +/* FRWR guarantees 8 bits of key; avoid corner cases by using "-2" */ +#define HERMON_FMR_MAX_REMAPS (256 - 2) /* Hermon doorbell record routines */ diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_mr.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_mr.h index 0f8b80fd60..cdfaa47a40 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_mr.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_mr.h @@ -20,8 +20,7 @@ */ /* - * Copyright 2010 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_ADAPTERS_HERMON_MR_H @@ -61,7 +60,7 @@ extern "C" { * MTTs per MPT. We also define a log MTT size, since it's not likely * to change. */ -#define HERMON_NUM_MTT_SHIFT 0x1a +#define HERMON_NUM_MTT_SHIFT 0x1d #define HERMON_MTT_SIZE_SHIFT 0x3 /* @@ -172,6 +171,7 @@ typedef struct hermon_bind_info_s { #define HERMON_BINDHDL_VADDR 1 #define HERMON_BINDHDL_BUF 2 #define HERMON_BINDHDL_UBUF 3 +#define HERMON_BINDHDL_LKEY 4 /* * The hermon_sw_mr_s structure is also referred to using the "hermon_mrhdl_t" @@ -288,6 +288,8 @@ _NOTE(SCHEME_PROTECTS_DATA("safe sharing", ibc_mem_alloc_s::ibc_dma_hdl ibc_mem_alloc_s::ibc_acc_hdl)) +int hermon_dma_mr_register(hermon_state_t *state, hermon_pdhdl_t pdhdl, + ibt_dmr_attr_t *attr_p, hermon_mrhdl_t *mrhdl); int hermon_mr_register(hermon_state_t *state, hermon_pdhdl_t pdhdl, ibt_mr_attr_t *attr_p, hermon_mrhdl_t *mrhdl, hermon_mr_options_t *op, hermon_mpt_rsrc_type_t mpt_type); @@ -324,8 +326,12 @@ int hermon_mr_alloc_fmr(hermon_state_t *state, hermon_pdhdl_t pd, int hermon_mr_dealloc_fmr(hermon_state_t *state, hermon_mrhdl_t *mrhdl); int hermon_mr_register_physical_fmr(hermon_state_t *state, ibt_pmr_attr_t *mem_pattr_p, hermon_mrhdl_t mr, ibt_pmr_desc_t *mem_desc_p); -int hermon_mr_invalidate_fmr(hermon_state_t *state, hermon_mrhdl_t mr); -int hermon_mr_deregister_fmr(hermon_state_t *state, hermon_mrhdl_t mr); +int hermon_mr_alloc_lkey(hermon_state_t *state, hermon_pdhdl_t pd, + ibt_lkey_flags_t flags, uint_t sz, hermon_mrhdl_t *mr); +int hermon_mr_fexch_mpt_init(hermon_state_t *state, hermon_pdhdl_t pd, + uint32_t mpt_indx, uint_t nummtt, uint64_t mtt_addr, uint_t sleep); +int hermon_mr_fexch_mpt_fini(hermon_state_t *state, hermon_pdhdl_t pd, + uint32_t mpt_indx, uint_t sleep); #ifdef __cplusplus diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_qp.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_qp.h index c88385de64..0086ee93a0 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_qp.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_qp.h @@ -20,8 +20,7 @@ */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_ADAPTERS_HERMON_QP_H @@ -55,9 +54,11 @@ extern "C" { * controlled via the "hermon_log_num_qp" configuration variables. * We also have a define for the minimum size of a QP. QPs allocated * with size 0, 1, 2, or 3 will always get back a QP of size 4. + * + * Note: Increasing #QPs from 64K to 256K for reserved ranges for FCoIB. */ -#define HERMON_NUM_QP_SHIFT 0x10 -#define HERMON_NUM_QPS (1 << HERMON_NUM_QP_SHIFT) /* 65,536 */ +#define HERMON_NUM_QP_SHIFT 0x12 +#define HERMON_NUM_QPS (1 << HERMON_NUM_QP_SHIFT) /* 256K */ #define HERMON_QP_MIN_SIZE 0xf /* @@ -80,7 +81,7 @@ extern "C" { * as recommended by the PRM. All XRC QPs will have this bit set. */ #define HERMON_QP_MAXNUMBER_MSK 0x7FFFFF -#define HERMON_QP_XRC 0x800000 +#define HERMON_QP_XRC_MSK 0x800000 /* * This define and the following macro are used to find a schedule queue for @@ -134,8 +135,10 @@ extern "C" { * to ensure the types match. */ #define HERMON_QP_TYPE_VALID(qp_trans, qp_serv) \ - ((qp_trans == IBT_UD_SRV && qp_serv == HERMON_QP_UD) || \ - (qp_trans == IBT_RC_SRV && qp_serv == HERMON_QP_RC) || \ + ((qp_trans == IBT_RC_SRV && qp_serv == HERMON_QP_RC) || \ + (qp_trans == IBT_UD_SRV && (qp_serv == HERMON_QP_UD || \ + qp_serv == HERMON_QP_RFCI || qp_serv == HERMON_QP_FCMND || \ + qp_serv == HERMON_QP_FEXCH)) || \ (qp_trans == IBT_UC_SRV && qp_serv == HERMON_QP_UC)) /* @@ -165,6 +168,17 @@ typedef enum { /* + * The hermon_qp_range_t is used to manage a qp_range for RSS and FEXCH. + * It has a reference count. When the reference count goes to 0, + * the qpc resource can be freed. + */ +typedef struct hermon_qp_range_s { + kmutex_t hqpr_lock; + hermon_rsrc_t *hqpr_qpcrsrc; + uint_t hqpr_refcnt; +} hermon_qp_range_t; + +/* * The hermon_qp_info_t structure is used internally by the Hermon driver to * pass information to and from the hermon_qp_alloc() and * hermon_special_qp_alloc() routines. It contains placeholders for all of the @@ -231,11 +245,12 @@ struct hermon_sw_qp_s { uint32_t qp_qpnum; hermon_pdhdl_t qp_pdhdl; uint_t qp_serv_type; + ibt_qp_type_t qp_type; uint_t qp_sl; /* service level */ hermon_mrhdl_t qp_mrhdl; uint_t qp_sq_sigtype; uint_t qp_is_special; - uint_t qp_is_umap; + ibt_qp_alloc_flags_t qp_alloc_flags; uint32_t qp_uarpg; devmap_cookie_t qp_umap_dhp; uint_t qp_portnum; /* port 0/1 for HCA */ @@ -260,9 +275,9 @@ struct hermon_sw_qp_s { uint32_t qp_sq_sgl; uint_t qp_uses_lso; uint32_t qp_ring; + uint_t qp_state_for_post_send; /* copy of qp_state */ /* Receive Work Queue - not used when SRQ is used */ - kmutex_t qp_rq_lock; hermon_cqhdl_t qp_rq_cqhdl; hermon_workq_avl_t qp_rq_wqavl; /* needed for srq */ hermon_workq_hdr_t *qp_rq_wqhdr; @@ -290,7 +305,6 @@ struct hermon_sw_qp_s { /* Shared Receive Queue */ hermon_srqhdl_t qp_srqhdl; - uint_t qp_srq_en; /* Refcnt of QP belongs to an MCG */ uint_t qp_mcg_refcnt; @@ -301,6 +315,12 @@ struct hermon_sw_qp_s { struct hermon_qalloc_info_s qp_wqinfo; + ibt_fc_attr_t qp_fc_attr; + + struct hermon_qp_range_s *qp_rangep; + + /* Beware: 8-byte alignment needed here */ + struct hermon_hw_qpc_s qpc; }; _NOTE(READ_ONLY_DATA(hermon_sw_qp_s::qp_qpnum @@ -324,7 +344,7 @@ _NOTE(READ_ONLY_DATA(hermon_sw_qp_s::qp_qpnum hermon_sw_qp_s::qp_sq_sigtype hermon_sw_qp_s::qp_serv_type hermon_sw_qp_s::qp_is_special - hermon_sw_qp_s::qp_is_umap + hermon_sw_qp_s::qp_alloc_flags hermon_sw_qp_s::qp_uarpg hermon_sw_qp_s::qp_sq_wqhdr hermon_sw_qp_s::qp_rq_wqhdr @@ -341,12 +361,19 @@ _NOTE(SCHEME_PROTECTS_DATA("safe sharing", hermon_sw_qp_s::qp_pkeyindx hermon_sw_qp_s::qp_portnum)) +#define HERMON_SET_QP_POST_SEND_STATE(qp, state) \ + mutex_enter(&qp->qp_sq_lock); \ + qp->qp_state_for_post_send = state; \ + mutex_exit(&qp->qp_sq_lock) /* Defined in hermon_qp.c */ int hermon_qp_alloc(hermon_state_t *state, hermon_qp_info_t *qpinfo, uint_t sleepflag); int hermon_special_qp_alloc(hermon_state_t *state, hermon_qp_info_t *qpinfo, uint_t sleepflag); +int hermon_qp_alloc_range(hermon_state_t *state, uint_t log2, + hermon_qp_info_t *qpinfo, ibtl_qp_hdl_t *ibtl_qp_p, ibc_cq_hdl_t *send_cq_p, + ibc_cq_hdl_t *recv_cq_p, hermon_qphdl_t *qp_p, uint_t sleepflag); int hermon_qp_free(hermon_state_t *state, hermon_qphdl_t *qphdl, ibc_free_qp_flags_t free_qp_flags, ibc_qpn_hdl_t *qpnh, uint_t sleepflag); int hermon_qp_query(hermon_state_t *state, hermon_qphdl_t qphdl, diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_rsrc.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_rsrc.h index 533e46aa42..c3faf29b74 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_rsrc.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_rsrc.h @@ -20,8 +20,7 @@ */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_ADAPTERS_HERMON_RSRC_H @@ -166,6 +165,10 @@ typedef enum { HERMON_UARPG, HERMON_INTR_IN_MBOX, HERMON_INTR_OUT_MBOX, /* type 0x1B */ + HERMON_QPC_FEXCH_PORT1, + HERMON_QPC_FEXCH_PORT2, + HERMON_QPC_RFCI_PORT1, + HERMON_QPC_RFCI_PORT2, HERMON_NUM_RESOURCES } hermon_rsrc_type_t; @@ -374,6 +377,9 @@ int hermon_rsrc_init_phase2(hermon_state_t *state); void hermon_rsrc_fini(hermon_state_t *state, hermon_rsrc_cleanup_level_t clean); +/* Exporting resource reservation capabilitity to FCoIB */ +int hermon_rsrc_reserve(hermon_state_t *state, hermon_rsrc_type_t rsrc, + uint_t num, uint_t sleepflag, hermon_rsrc_t **hdl); #ifdef __cplusplus } diff --git a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_typedef.h b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_typedef.h index 5a1f1b5fa9..b9748f7f0b 100644 --- a/usr/src/uts/common/sys/ib/adapters/hermon/hermon_typedef.h +++ b/usr/src/uts/common/sys/ib/adapters/hermon/hermon_typedef.h @@ -20,8 +20,7 @@ */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_ADAPTERS_HERMON_TYPEDEF_H @@ -57,6 +56,17 @@ typedef struct hermon_hw_hcr_s hermon_hw_hcr_t; typedef struct hermon_hw_querydevlim_s hermon_hw_querydevlim_t; typedef struct hermon_hw_query_port_s hermon_hw_query_port_t; typedef struct hermon_hw_set_port_s hermon_hw_set_port_t; +typedef struct hermon_hw_set_port_en_s hermon_hw_set_port_en_t; +typedef struct hermon_hw_set_port_en_rqpn_s hermon_hw_set_port_en_rqpn_t; +typedef struct hermon_hw_set_port_en_mact_s hermon_hw_set_port_en_mact_t; +typedef struct hermon_hw_set_port_en_vlant_s hermon_hw_set_port_en_vlant_t; +typedef struct hermon_hw_set_port_en_priot_s hermon_hw_set_port_en_priot_t; +typedef struct hermon_fw_set_port_gidtable_s hermon_fw_set_port_gidtable_t; +typedef struct hermon_hw_set_mcast_fltr_s hermon_hw_set_mcast_fltr_t; +typedef struct hermon_hw_arm_req_s hermon_hw_arm_req_t; +typedef struct hermon_hw_config_fc_basic_s hermon_hw_config_fc_basic_t; +typedef struct hermon_hw_query_fc_s hermon_hw_query_fc_t; + typedef struct hermon_hw_queryfw_s hermon_hw_queryfw_t; typedef struct hermon_hw_queryadapter_s hermon_hw_queryadapter_t; typedef struct hermon_hw_initqueryhca_s hermon_hw_initqueryhca_t; @@ -73,20 +83,32 @@ typedef struct hermon_hw_addr_path_s hermon_hw_addr_path_t; typedef struct hermon_hw_mod_stat_cfg_s hermon_hw_mod_stat_cfg_t; typedef struct hermon_hw_msg_in_mod_s hermon_hw_msg_in_mod_t; typedef struct hermon_hw_udav_s hermon_hw_udav_t; +typedef struct hermon_hw_udav_enet_s hermon_hw_udav_enet_t; typedef struct hermon_hw_qpc_s hermon_hw_qpc_t; typedef struct hermon_hw_mcg_s hermon_hw_mcg_t; +typedef struct hermon_hw_mcg_en_s hermon_hw_mcg_en_t; typedef struct hermon_hw_mcg_qp_list_s hermon_hw_mcg_qp_list_t; typedef struct hermon_hw_sm_perfcntr_s hermon_hw_sm_perfcntr_t; typedef struct hermon_hw_sm_extperfcntr_s hermon_hw_sm_extperfcntr_t; -typedef struct hermon_hw_snd_wqe_ctrl_s hermon_hw_snd_wqe_ctrl_t; -typedef struct hermon_hw_srq_wqe_next_s hermon_hw_srq_wqe_next_t; -typedef struct hermon_hw_snd_wqe_ud_s hermon_hw_snd_wqe_ud_t; -typedef struct hermon_hw_snd_wqe_bind_s hermon_hw_snd_wqe_bind_t; + +typedef struct hermon_hw_snd_wqe_ud_s hermon_hw_snd_wqe_ud_t; +typedef struct hermon_hw_snd_wqe_bind_s hermon_hw_snd_wqe_bind_t; typedef struct hermon_hw_snd_wqe_remaddr_s hermon_hw_snd_wqe_remaddr_t; typedef struct hermon_hw_snd_wqe_atomic_s hermon_hw_snd_wqe_atomic_t; +typedef struct hermon_hw_snd_wqe_frwr_s hermon_hw_snd_wqe_frwr_t; +typedef struct hermon_hw_snd_wqe_frwr_ext_s hermon_hw_snd_wqe_frwr_ext_t; +typedef struct hermon_hw_snd_wqe_local_inv_s hermon_hw_snd_wqe_local_inv_t; +typedef struct hermon_hw_snd_rem_addr_s hermon_hw_snd_rem_addr_t; +typedef struct hermon_sw_send_wqe_lso_s hermon_sw_send_wqe_lso_t; typedef struct hermon_hw_mlx_wqe_nextctrl_s hermon_hw_mlx_wqe_nextctrl_t; typedef struct hermon_hw_rcv_wqe_nextctrl_s hermon_hw_rcv_wqe_nextctrl_t; typedef struct hermon_hw_wqe_sgl_s hermon_hw_wqe_sgl_t; +typedef struct hermon_hw_snd_wqe_ctrl_s hermon_hw_snd_wqe_ctrl_t; +typedef struct hermon_hw_srq_wqe_next_s hermon_hw_srq_wqe_next_t; +typedef struct hermonw_hw_fcp3_ctrl_s hermonw_hw_fcp3_ctrl_t; +typedef struct hermon_hw_fcp3_init_s hermon_hw_fcp3_init_t; +typedef struct hermon_hw_fcmd_o_enet_s hermon_hw_fcmd_o_enet_t; +typedef struct hermon_hw_fcmd_o_ib_s hermon_hw_fcmd_o_ib_t; typedef struct hermon_sw_mr_s *hermon_mrhdl_t; typedef struct hermon_sw_mr_s *hermon_mwhdl_t; diff --git a/usr/src/uts/common/sys/ib/adapters/tavor/tavor_mr.h b/usr/src/uts/common/sys/ib/adapters/tavor/tavor_mr.h index c9d736e0e9..079c686e45 100644 --- a/usr/src/uts/common/sys/ib/adapters/tavor/tavor_mr.h +++ b/usr/src/uts/common/sys/ib/adapters/tavor/tavor_mr.h @@ -20,8 +20,7 @@ */ /* - * Copyright 2010 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_ADAPTERS_TAVOR_MR_H @@ -307,6 +306,8 @@ typedef struct tavor_mr_options_s { #define TAVOR_BINDMEM_NORMAL 1 #define TAVOR_BINDMEM_BYPASS 0 +int tavor_dma_mr_register(tavor_state_t *state, tavor_pdhdl_t pdhdl, + ibt_dmr_attr_t *attr_p, tavor_mrhdl_t *mrhdl); int tavor_mr_register(tavor_state_t *state, tavor_pdhdl_t pdhdl, ibt_mr_attr_t *attr_p, tavor_mrhdl_t *mrhdl, tavor_mr_options_t *op); int tavor_mr_register_buf(tavor_state_t *state, tavor_pdhdl_t pdhdl, diff --git a/usr/src/uts/common/sys/ib/clients/of/rdma/ib_verbs.h b/usr/src/uts/common/sys/ib/clients/of/rdma/ib_verbs.h index 35ff93d9d6..00f7495c88 100644 --- a/usr/src/uts/common/sys/ib/clients/of/rdma/ib_verbs.h +++ b/usr/src/uts/common/sys/ib/clients/of/rdma/ib_verbs.h @@ -721,15 +721,14 @@ int ib_destroy_qp(struct ib_qp *qp); * @cq_context: Context associated with the CQ returned to the user via * the associated completion and event handlers. * @cqe: The minimum size of the CQ. - * @comp_vector - Completion vector used to signal completion events. - * Must be >= 0 and < context->num_comp_vectors. + * @comp_vector - Completion queue sched handle. * * Users can examine the cq structure to determine the actual CQ size. */ struct ib_cq *ib_create_cq(struct ib_device *device, ib_comp_handler comp_handler, void (*event_handler)(struct ib_event *, void *), - void *cq_context, int cqe, int comp_vector); + void *cq_context, int cqe, void *comp_vector); /* * ib_destroy_cq - Destroys the specified CQ. diff --git a/usr/src/uts/common/sys/ib/ibtl/ibci.h b/usr/src/uts/common/sys/ib/ibtl/ibci.h index 63c77fae25..b620b51e11 100644 --- a/usr/src/uts/common/sys/ib/ibtl/ibci.h +++ b/usr/src/uts/common/sys/ib/ibtl/ibci.h @@ -19,8 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2010 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_IBTL_IBCI_H @@ -64,6 +63,7 @@ typedef struct ibc_cq_s *ibc_cq_hdl_t; /* Completion Queue Handle */ typedef struct ibc_eec_s *ibc_eec_hdl_t; /* End-to-End Context Handle */ typedef struct ibc_mem_alloc_s *ibc_mem_alloc_hdl_t; /* Memory Handle */ +#define ibc_sched_hdl_t ibt_sched_hdl_t /* CQ Sched Handle */ #define ibc_fmr_pool_hdl_t ibt_fmr_pool_hdl_t /* FMR Pool Handle */ #define ibc_mr_hdl_t ibt_mr_hdl_t /* Memory Region Handle */ #define ibc_mw_hdl_t ibt_mw_hdl_t /* Memory Window Handle */ @@ -142,11 +142,11 @@ typedef struct ibtl_hca_devinfo_s *ibc_clnt_hdl_t; /* ibc_attach() */ /* Channel Interface version */ -typedef enum ibc_version_e { - IBCI_V1 = 1, - IBCI_V2 = 2, /* FMR Support */ - IBCI_V3 = 3 -} ibc_version_t; +typedef int ibc_version_t; +#define IBCI_V1 1 +#define IBCI_V2 2 +#define IBCI_V3 3 +#define IBCI_V4 4 typedef enum ibc_free_qp_flags_e { @@ -176,24 +176,6 @@ typedef enum ibc_eec_flags_e { IBT_EEC_DEFER_ALLOC = (1 << 1) } ibc_eec_flags_t; - -/* - * Completion Queues - * - */ - -/* - * CQ handler attribute structure. - */ -typedef struct ibc_cq_handler_attr_s { - ibt_cq_handler_id_t h_id; /* Valid ID != NULL */ - int h_flags; /* Flags of ddi_intr_get_cap */ - int h_pri; /* priority from */ - /* ddi_intr_get_pri */ - void *h_bind; /* unknown intrd stuff */ -} ibc_cq_handler_attr_t; - - /* * Event data for asynchronous events and errors. The QP/EEC/CQ/SRQ handle, * or port number associated with the Event/Error is passed as an argument @@ -207,6 +189,7 @@ typedef struct ibc_async_event_s { ibt_srq_hdl_t ev_srq_hdl; /* SRQ handle */ ibt_port_change_t ev_port_flags; /* Port Change flags */ uint8_t ev_port; /* For PORT UP/DOWN/CHANGE events */ + ibt_fc_syndrome_t ev_fc; /* FEXCH syndrome */ } ibc_async_event_t; @@ -272,9 +255,11 @@ typedef struct ibc_operations_s { ibt_status_t (*ibc_modify_cq)(ibc_hca_hdl_t hca, ibc_cq_hdl_t cq, uint_t count, uint_t usec, ibt_cq_handler_id_t hid); ibt_status_t (*ibc_alloc_cq_sched)(ibc_hca_hdl_t hca, - ibt_cq_sched_flags_t flags, ibc_cq_handler_attr_t *handler_attrs_p); + ibt_cq_sched_attr_t *attr, ibc_sched_hdl_t *sched_hdl_p); ibt_status_t (*ibc_free_cq_sched)(ibc_hca_hdl_t hca, - ibt_cq_handler_id_t id); + ibc_sched_hdl_t sched_hdl); + ibt_status_t (*ibc_query_cq_handler_id)(ibc_hca_hdl_t hca, + ibt_cq_handler_id_t hid, ibt_cq_handler_attr_t *attrs); /* EE Context */ ibt_status_t (*ibc_alloc_eec)(ibc_hca_hdl_t hca, ibc_eec_flags_t flags, @@ -409,6 +394,17 @@ typedef struct ibc_operations_s { ibt_status_t (*ibc_free_xrc_tgt_qp)(); ibt_status_t (*ibc_query_xrc_tgt_qp)(); ibt_status_t (*ibc_modify_xrc_tgt_qp)(); + + /* DMA memory region */ + ibt_status_t (*ibc_register_dma_mr)(ibc_hca_hdl_t hca, ibc_pd_hdl_t pd, + ibt_dmr_attr_t *attr_p, void *ibtl_reserved, ibc_mr_hdl_t *mr_p, + ibt_mr_desc_t *mem_desc); + + /* OPS extensions for next round of enhancements */ + ibt_status_t (*ibc_enhancement1)(); + ibt_status_t (*ibc_enhancement2)(); + ibt_status_t (*ibc_enhancement3)(); + ibt_status_t (*ibc_enhancement4)(); } ibc_operations_t; @@ -421,12 +417,10 @@ typedef struct ibc_operations_s { */ typedef struct ibc_hca_info_s { ibc_version_t hca_ci_vers; /* CI Version */ - dev_info_t *hca_dip; /* HCA dev_info */ ibc_hca_hdl_t hca_handle; /* used for call through */ /* "hca_ops" */ ibc_operations_t *hca_ops; ibt_hca_attr_t *hca_attr; - ibc_cq_handler_attr_t hca_def_cq_handler_attr; } ibc_hca_info_t; diff --git a/usr/src/uts/common/sys/ib/ibtl/ibti.h b/usr/src/uts/common/sys/ib/ibtl/ibti.h index 49d50e7940..9d8407d39a 100644 --- a/usr/src/uts/common/sys/ib/ibtl/ibti.h +++ b/usr/src/uts/common/sys/ib/ibtl/ibti.h @@ -19,8 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_IBTL_IBTI_H @@ -47,7 +46,12 @@ typedef enum ibt_chan_alloc_flags_e { IBT_ACHAN_USER_MAP = (1 << 1), IBT_ACHAN_DEFER_ALLOC = (1 << 2), IBT_ACHAN_USES_SRQ = (1 << 3), - IBT_ACHAN_USES_RSS = (1 << 4) + IBT_ACHAN_USES_RSS = (1 << 4), + + /* UD variants for FC support */ + IBT_ACHAN_USES_RFCI = (1 << 5), /* from RFCI pool */ + IBT_ACHAN_USES_FCMD = (1 << 6), + IBT_ACHAN_USES_FEXCH = (1 << 7) /* from FEXCH pool */ } ibt_chan_alloc_flags_t; @@ -151,6 +155,7 @@ typedef struct ibt_ud_chan_alloc_args_s { ibt_channel_hdl_t ud_clone_chan; /* Optional clone handle */ ibt_srq_hdl_t ud_srq; /* Optional Shared Rcv Queue */ ibt_rss_attr_t ud_rss; + ibt_fc_attr_t ud_fc; } ibt_ud_chan_alloc_args_t; /* @@ -170,6 +175,8 @@ typedef struct ibt_ud_chan_query_attr_s { ibt_attr_flags_t ud_flags; /* Signaling Type etc */ ibt_srq_hdl_t ud_srq; /* Optional Shared Rcv Queue */ ibt_rss_attr_t ud_rss; + ibt_fc_attr_t ud_fc; + ibt_fexch_query_attr_t ud_query_fc; /* query only set */ } ibt_ud_chan_query_attr_t; /* @@ -187,6 +194,7 @@ typedef struct ibt_ud_chan_modify_attr_s { uint_t ud_rq_sz; /* Set RQ Max outstanding WRs */ ib_qkey_t ud_qkey; /* Set Q_Key */ ibt_rss_attr_t ud_rss; /* Set RSS stuff */ + ibt_fc_attr_t ud_fc; } ibt_ud_chan_modify_attr_t; diff --git a/usr/src/uts/common/sys/ib/ibtl/ibti_common.h b/usr/src/uts/common/sys/ib/ibtl/ibti_common.h index 94e696cecc..e71c12b659 100644 --- a/usr/src/uts/common/sys/ib/ibtl/ibti_common.h +++ b/usr/src/uts/common/sys/ib/ibtl/ibti_common.h @@ -57,12 +57,12 @@ extern "C" { /* Transport Interface version */ -typedef enum ibt_version_e { - IBTI_V1 = 1, - IBTI_V2 = 2, /* FMR Support */ - IBTI_V3 = 3, - IBTI_V_CURR = IBTI_V3 -} ibt_version_t; +typedef int ibt_version_t; +#define IBTI_V1 1 +#define IBTI_V2 2 +#define IBTI_V3 3 +#define IBTI_V4 4 +#define IBTI_V_CURR IBTI_V4 /* * Driver class type. Identifies a type of client driver so that @@ -128,6 +128,7 @@ typedef struct ibt_async_event_s { ibt_srq_hdl_t ev_srq_hdl; /* SRQ handle */ ibt_port_change_t ev_port_flags; /* Port Change flags */ uint8_t ev_port; /* HCA port */ + ibt_fc_syndrome_t ev_fc; /* FEXCH syndrome */ } ibt_async_event_t; /* @@ -205,48 +206,6 @@ typedef enum ibt_qflags_e { IBT_RECV_Q = 1 << 1 /* Op applies to the Recv Q */ } ibt_qflags_t; -/* - * CQ priorities - * The IBTF will attempt to implement a coarse 3 level priority scheme - * (IBT_CQ_LOW, IBT_CQ_MEDIUM, IBT_CQ_HIGH) based on the class of client - * driver. The requested priority is not guaranteed. If a CI implementation - * has the ability to implement priority CQs, then the IBTF will take advantage - * of that when calling the CI to create a CQ by passing a priority indicator - * to the CI. - */ -typedef enum ibt_cq_priority_e { - IBT_CQ_DEFAULT = 0x0, - IBT_CQ_LOW = 0x1, - IBT_CQ_MEDIUM = 0x2, - IBT_CQ_HIGH = 0x3, - IBT_CQ_OPAQUE_1 = 0x4, - IBT_CQ_OPAQUE_2 = 0x5, - IBT_CQ_OPAQUE_3 = 0x6, - IBT_CQ_OPAQUE_4 = 0x7, - IBT_CQ_OPAQUE_5 = 0x8, - IBT_CQ_OPAQUE_6 = 0x9, - IBT_CQ_OPAQUE_7 = 0xA, - IBT_CQ_OPAQUE_8 = 0xB, - IBT_CQ_OPAQUE_9 = 0xC, - IBT_CQ_OPAQUE_10 = 0xD, - IBT_CQ_OPAQUE_11 = 0xE, - IBT_CQ_OPAQUE_12 = 0xF, - IBT_CQ_OPAQUE_13 = 0x10, - IBT_CQ_OPAQUE_14 = 0x11, - IBT_CQ_OPAQUE_15 = 0x12, - IBT_CQ_OPAQUE_16 = 0x13 -} ibt_cq_priority_t; - -/* - * Attributes when creating a Completion Queue Scheduling Handle. - */ -typedef struct ibt_cq_sched_attr_s { - ibt_cq_sched_flags_t cqs_flags; - ibt_cq_priority_t cqs_priority; - uint_t cqs_load; - ibt_sched_hdl_t cqs_affinity_hdl; -} ibt_cq_sched_attr_t; - /* * ibt_cq_handler_t @@ -1113,7 +1072,7 @@ ibt_status_t ibt_alloc_cq_sched(ibt_hca_hdl_t hca_hdl, ibt_cq_sched_attr_t *attr, ibt_sched_hdl_t *sched_hdl_p); ibt_status_t ibt_free_cq_sched(ibt_hca_hdl_t hca_hdl, - ibt_sched_hdl_t sched_hdl, uint_t load); + ibt_sched_hdl_t sched_hdl); /* * ibt_alloc_cq() @@ -1172,6 +1131,13 @@ ibt_status_t ibt_query_cq(ibt_cq_hdl_t ibt_cq, uint_t *entries, uint_t *count_p, uint_t *usec_p, ibt_cq_handler_id_t *hid_p); /* + * ibt_query_cq_handler_id() + * Return interrupt characteristics of the CQ handler + */ +ibt_status_t ibt_query_cq_handler_id(ibt_hca_hdl_t hca_hdl, + ibt_cq_handler_id_t hid, ibt_cq_handler_attr_t *attrs); + +/* * ibt_resize_cq() * Change the size of a CQ. */ @@ -1303,6 +1269,13 @@ ibt_status_t ibt_reregister_phys_mr(ibt_hca_hdl_t hca_hdl, ibt_mr_hdl_t mr_hdl, /* + * Register DMA Memory Region + */ +ibt_status_t ibt_register_dma_mr(ibt_hca_hdl_t hca_hdl, ibt_pd_hdl_t pd, + ibt_dmr_attr_t *mem_attr, ibt_mr_hdl_t *mr_hdl_p, ibt_mr_desc_t *mem_desc); + + +/* * Address Translation. */ @@ -1741,6 +1714,7 @@ typedef struct ibt_ip_path_attr_s { uint_t ipa_flow:20; /* Optional */ uint8_t ipa_hop; /* Optional */ uint8_t ipa_tclass; /* Optional */ + zoneid_t ipa_zoneid; /* Default 0 = Global Zone */ } ibt_ip_path_attr_t; /* @@ -1756,8 +1730,51 @@ ibt_status_t ibt_get_ip_paths(ibt_clnt_hdl_t ibt_hdl, ibt_path_flags_t flags, ibt_ip_path_attr_t *attr, ibt_path_info_t *paths_p, uint8_t *num_paths_p, ibt_path_ip_src_t *src_ip_p); -ibt_status_t ibt_get_src_ip(ib_gid_t gid, ib_pkey_t pkey, - ibt_ip_addr_t *src_ip); +/* + * ibt_get_src_ip() + * Get List of IP-Address that matches the parameters specified in + * srcip_attr. As a given MAC address can have both IPv4 and IPv6 + * addressed configured, caller can optional request to return only + * the desired family by specifying the "sip_family" field. If + * "sip_family" is AF_UNSPEC, then all assigned IP address (IPv4 + * and/or IPv6) will be returned. In case of IPv6 address, scope_id + * for that specific address will also be returned. + * "sip_zoneid" will specify the zones the user is interested in. + * + * Information on each ip-address is returned to the caller in the + * form of an array of ibt_srcip_info_t. ibt_get_src_ip() allocates the + * memory for this array and returns a pointer to the array (src_info_p) + * and the number of entries in the array (entries_p). This memory + * should be freed by the client using ibt_free_srcip_info(). + * + * ibt_free_srcip_info() + * Free the memory allocated by successful ibt_get_src_ip() + */ +typedef struct ibt_srcip_attr_s { + ib_gid_t sip_gid; /* REQUIRED: Local Port GID */ + zoneid_t sip_zoneid; /* Zero means Global Zone */ + ib_pkey_t sip_pkey; /* Optional */ + sa_family_t sip_family; /* Optional : IPv4 or IPv6 */ +} ibt_srcip_attr_t; + +/* + * ip_flag : Flag to indicate whether the returned list of ip-address + * has any duplicate records. + */ +#define IBT_IPADDR_NO_FLAGS 0 +#define IBT_IPADDR_DUPLICATE 1 + +typedef struct ibt_srcip_info_s { + ibt_ip_addr_t ip_addr; + zoneid_t ip_zoneid; /* ZoneId of this ip-addr */ + uint_t ip_flag; /* Flag to indicate any gotchas */ +} ibt_srcip_info_t; + +ibt_status_t ibt_get_src_ip(ibt_srcip_attr_t *srcip_attr, + ibt_srcip_info_t **src_info_p, uint_t *entries_p); + +void ibt_free_srcip_info(ibt_srcip_info_t *src_info, uint_t entries); + /* * Callback function that can be used in ibt_aget_ip_paths(), a Non-Blocking @@ -1832,6 +1849,7 @@ typedef struct ibt_alt_ip_path_attr_s { uint8_t apa_sl:4; uint8_t apa_hop; uint8_t apa_tclass; + zoneid_t apa_zoneid; /* Default 0 = Global Zone */ } ibt_alt_ip_path_attr_t; ibt_status_t ibt_get_ip_alt_path(ibt_channel_hdl_t rc_chan, @@ -1934,6 +1952,14 @@ ibt_status_t ibt_get_part_attr(datalink_id_t, ibt_part_attr_t *); ibt_status_t ibt_get_all_part_attr(ibt_part_attr_t **, int *); ibt_status_t ibt_free_part_attr(ibt_part_attr_t *, int); + +/* + * ibt_lid_to_node_info() + * Retrieve node record information for the specified LID. + */ +ibt_status_t ibt_lid_to_node_info(ib_lid_t lid, ibt_node_info_t *node_info_p); + + #ifdef __cplusplus } #endif diff --git a/usr/src/uts/common/sys/ib/ibtl/ibtl_ci_types.h b/usr/src/uts/common/sys/ib/ibtl/ibtl_ci_types.h index 4163ec69c9..ab77ba3fbb 100644 --- a/usr/src/uts/common/sys/ib/ibtl/ibtl_ci_types.h +++ b/usr/src/uts/common/sys/ib/ibtl/ibtl_ci_types.h @@ -19,8 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2010 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_IBTL_IBTL_CI_TYPES_H @@ -228,7 +227,12 @@ typedef enum ibt_qp_alloc_flags_e { IBT_QP_USER_MAP = (1 << 0), IBT_QP_DEFER_ALLOC = (1 << 1), IBT_QP_USES_SRQ = (1 << 2), - IBT_QP_USES_RSS = (1 << 3) + IBT_QP_USES_RSS = (1 << 3), + + /* FC variants of UD */ + IBT_QP_USES_RFCI = (1 << 4), + IBT_QP_USES_FCMD = (1 << 5), + IBT_QP_USES_FEXCH = (1 << 6) } ibt_qp_alloc_flags_t; /* @@ -248,6 +252,7 @@ typedef struct ibt_qp_alloc_attr_s { ibt_opaque1_t qp_opaque2; ibt_srq_hdl_t qp_srq_hdl; /* SRQ ibt hdl */ ibt_opaque2_t qp_opaque3; + ibt_fc_attr_t qp_fc; } ibt_qp_alloc_attr_t; @@ -305,6 +310,7 @@ typedef struct ibt_qp_ud_attr_s { uint16_t ud_pkey_ix; /* P_Key Index */ uint8_t ud_port; /* port */ ibt_rss_attr_t ud_rss; /* RSS stuff */ + ibt_fc_attr_t ud_fc; } ibt_qp_ud_attr_t; /* @@ -326,7 +332,6 @@ typedef struct ibt_qp_info_s { } qp_transport; } ibt_qp_info_t; - /* * QP Query Attributes definition. */ @@ -340,6 +345,7 @@ typedef struct ibt_qp_query_attr_s { ibt_qp_info_t qp_info; /* Modifiable attributes */ ibt_srq_hdl_t qp_srq; /* SRQ hdl or NULL */ ibt_attr_flags_t qp_flags; + ibt_fexch_query_attr_t qp_query_fexch; /* FEXCH query only set */ } ibt_qp_query_attr_t; diff --git a/usr/src/uts/common/sys/ib/ibtl/ibtl_status.h b/usr/src/uts/common/sys/ib/ibtl/ibtl_status.h index b2258de411..5afb2a76a8 100644 --- a/usr/src/uts/common/sys/ib/ibtl/ibtl_status.h +++ b/usr/src/uts/common/sys/ib/ibtl/ibtl_status.h @@ -224,6 +224,9 @@ typedef enum ibt_status_e { IBT_CQ_EMPTY = 503, /* Completion Queue Empty */ IBT_CQ_NOTIFY_TYPE_INVALID = 504, /* Invalid notification type */ IBT_CQ_INVALID_PRIORITY = 505, /* Invalid CQ Priority */ + IBT_CQ_SCHED_INVALID = 550, /* Invalid CQ Sched Handle */ + IBT_CQ_NO_SCHED_GROUP = 551, /* Schedule group not found */ + IBT_CQ_HID_INVALID = 552, /* CQ Handler ID invalid */ /* * Reserved for future use. @@ -315,8 +318,8 @@ typedef uint8_t ibt_wc_status_t; /* for posted WR */ #define IBT_WC_WR_FLUSHED_ERR 14 /* WR was in process when the */ /* chan went to error state */ -#define IBT_WC_MEM_WIN_BIND_ERR 15 /* Consumer had insufficient */ - /* access rights */ +#define IBT_WC_MEM_MGT_OP_ERR 15 /* bind plus 1.2 mem ext */ +#define IBT_WC_MEM_WIN_BIND_ERR IBT_WC_MEM_MGT_OP_ERR /* * Errors that are only reported for Reliable Queue Pairs. diff --git a/usr/src/uts/common/sys/ib/ibtl/ibtl_types.h b/usr/src/uts/common/sys/ib/ibtl/ibtl_types.h index 89d9c040ad..67d890c81e 100644 --- a/usr/src/uts/common/sys/ib/ibtl/ibtl_types.h +++ b/usr/src/uts/common/sys/ib/ibtl/ibtl_types.h @@ -19,8 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2010 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_IBTL_IBTL_TYPES_H @@ -386,7 +385,9 @@ typedef enum ibt_hca_flags2_e { IBT_HCA2_RSS_XOR_ALG = 1 << 7, /* RSS: XOR algorithm */ IBT_HCA2_XRC = 1 << 8, /* Extended RC (XRC) */ IBT_HCA2_XRC_SRQ_RESIZE = 1 << 9, /* resize XRC SRQ */ - IBT_HCA2_MEM_MGT_EXT = 1 << 10 /* FMR-WR, send-inv, local-inv */ + IBT_HCA2_MEM_MGT_EXT = 1 << 10, /* FMR-WR, send-inv, local-inv */ + IBT_HCA2_DMA_MR = 1 << 11, /* DMA MR */ + IBT_HCA2_FC = 1 << 12 /* FCoIB or FCoE offload */ } ibt_hca_flags2_t; /* @@ -535,7 +536,16 @@ typedef struct ibt_hca_attr_s { uint_t hca_recv_sgl_sz; /* detailed SGL sizes */ uint_t hca_ud_send_sgl_sz; uint_t hca_conn_send_sgl_sz; + uint_t hca_conn_rdma_read_sgl_sz; + uint_t hca_conn_rdma_write_sgl_sz; uint_t hca_conn_rdma_sgl_overhead; + + /* FC Support */ + uint8_t hca_rfci_max_log2_qp; /* max log2 RFCI QPs */ + uint8_t hca_fexch_max_log2_qp; /* max log2 FEXCH QPs */ + uint8_t hca_fexch_max_log2_mem; /* max log2 mem per FEXCH */ + + dev_info_t *hca_dip; /* HCA dev_info */ } ibt_hca_attr_t; /* @@ -745,6 +755,9 @@ typedef uint8_t ibt_tran_srv_t; #define IBT_UD_SRV 3 #define IBT_RAWIP_SRV 4 #define IBT_RAWETHER_SRV 5 +#define IBT_RFCI_SRV 6 +#define IBT_FCMD_SRV 7 +#define IBT_FEXCH_SRV 8 /* * Channel (QP/EEC) state definitions. @@ -818,7 +831,8 @@ typedef enum ibt_cep_modify_flags_e { IBT_CEP_SET_OPAQUE6 = (1 << 21), IBT_CEP_SET_OPAQUE7 = (1 << 22), IBT_CEP_SET_OPAQUE8 = (1 << 23), - IBT_CEP_SET_RSS = (1 << 24) + IBT_CEP_SET_RSS = (1 << 24), + IBT_CEP_SET_FEXCH_RANGE = (1 << 25) } ibt_cep_modify_flags_t; /* @@ -837,22 +851,35 @@ typedef enum ibt_cq_flags_e { IBT_CQ_HANDLER_IN_THREAD = 1 << 0, /* A thread calls the */ /* CQ handler */ IBT_CQ_USER_MAP = 1 << 1, - IBT_CQ_DEFER_ALLOC = 1 << 2 + IBT_CQ_DEFER_ALLOC = 1 << 2, + IBT_CQ_HID = 1 << 3 } ibt_cq_flags_t; -/* - * CQ types shared across TI and CI. - */ typedef enum ibt_cq_sched_flags_e { IBT_CQS_NO_FLAGS = 0, IBT_CQS_WARM_CACHE = 1 << 0, /* run on same CPU */ - IBT_CQS_AFFINITY = 1 << 1, + IBT_CQS_EXACT_SCHED_GROUP = 1 << 1, IBT_CQS_SCHED_GROUP = 1 << 2, IBT_CQS_USER_MAP = 1 << 3, IBT_CQS_DEFER_ALLOC = 1 << 4 } ibt_cq_sched_flags_t; /* + * Attributes when creating a Completion Queue Scheduling Handle. + */ +typedef struct ibt_cq_sched_attr_s { + ibt_cq_sched_flags_t cqs_flags; + char *cqs_pool_name; +} ibt_cq_sched_attr_t; + +typedef void *ibt_intr_handle_t; + +typedef struct ibt_cq_handler_attr_s { + dev_info_t *cha_dip; + ibt_intr_handle_t cha_ih; +} ibt_cq_handler_attr_t; + +/* * Attributes when creating a Completion Queue. * * Note: @@ -863,6 +890,7 @@ typedef struct ibt_cq_attr_s { ibt_sched_hdl_t cq_sched; /* 0 = no hint, */ /* other = cq_sched value */ ibt_cq_flags_t cq_flags; + ibt_cq_handler_id_t cq_hid; } ibt_cq_attr_t; /* @@ -894,7 +922,8 @@ typedef enum ibt_mr_flags_e { /* Additional physical registration flags */ IBT_MR_CONSUMER_KEY = (1 << 13), /* Consumer owns key */ /* portion of keys */ - IBT_MR_DISABLE_RO = (1 << 14) + IBT_MR_DISABLE_RO = (1 << 14), + IBT_MR_USER_BUF = (1 << 15) /* ibt_(re)register_buf */ } ibt_mr_flags_t; @@ -995,6 +1024,13 @@ typedef struct ibt_pmr_attr_s { uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ } ibt_pmr_attr_t; +/* DMA Memory Region */ +typedef struct ibt_dmr_attr_s { + uint64_t dmr_paddr; /* starting physical addr */ + ib_memlen_t dmr_len; /* length in bytes */ + ibt_mr_flags_t dmr_flags; /* no sleep, memory permissions */ +} ibt_dmr_attr_t; + /* addr/length pair */ typedef struct ibt_iov_s { caddr_t iov_addr; /* Beginning address */ @@ -1006,7 +1042,9 @@ typedef enum ibt_iov_flags_e { IBT_IOV_SLEEP = 0, IBT_IOV_NOSLEEP = (1 << 0), IBT_IOV_BUF = (1 << 1), - IBT_IOV_RECV = (1 << 2) + IBT_IOV_RECV = (1 << 2), + IBT_IOV_USER_BUF = (1 << 3), + IBT_IOV_ALT_LKEY = (1 << 4) } ibt_iov_flags_t; typedef struct ibt_iov_attr_s { @@ -1016,6 +1054,7 @@ typedef struct ibt_iov_attr_s { uint32_t iov_list_len; uint32_t iov_wr_nds; ib_msglen_t iov_lso_hdr_sz; + ibt_lkey_t iov_alt_lkey; ibt_iov_flags_t iov_flags; } ibt_iov_attr_t; @@ -1090,7 +1129,8 @@ typedef enum ibt_va_flags_e { IBT_VA_FMR = (1 << 2), IBT_VA_BLOCK_MODE = (1 << 3), IBT_VA_BUF = (1 << 4), - IBT_VA_REG_FN = (1 << 5) + IBT_VA_REG_FN = (1 << 5), + IBT_VA_USER_BUF = (1 << 6) } ibt_va_flags_t; @@ -1127,6 +1167,29 @@ typedef struct ibt_fmr_pool_attr_s { void *fmr_func_arg; } ibt_fmr_pool_attr_t; +/* + * Define types for Fibre Channel over IB (fcoib) + */ +typedef enum ibt_fexch_query_flags_e { + IBT_FEXCH_NO_FLAGS = 0, + IBT_FEXCH_HEART_BEAT_OK = (1 << 0) /* FEXCH only */ +} ibt_fexch_query_flags_t; + +typedef struct ibt_fexch_query_attr_s { + ibt_pmr_desc_t fq_uni_mem_desc; /* FEXCH: uni-directional MR attrs */ + ibt_pmr_desc_t fq_bi_mem_desc; /* FEXCH: bi-directional MR attrs */ + ibt_fexch_query_flags_t fq_flags; +} ibt_fexch_query_attr_t; + +typedef struct ibt_fc_attr_s { + uint32_t fc_src_id; /* S_ID assigned to the RFCI QP */ + /* FCMD, FEXCH: matching RFCI QP = RFCI base + idx */ + ib_qpn_t fc_rfci_qpn; + uint16_t fc_exch_base_off; /* FCMD: FEXCH usable base */ + uint8_t fc_exch_log2_sz; /* FCMD: FEXCH log2 size */ + uint8_t fc_hca_port; /* RFCI, FEXCH: HCA port number */ +} ibt_fc_attr_t; + /* * WORK REQUEST AND WORK REQUEST COMPLETION DEFINITIONS. @@ -1156,6 +1219,8 @@ typedef uint8_t ibt_wrc_opcode_t; #define IBT_WRC_FAST_REG_PMR 9 /* Fast Register Physical mem region */ #define IBT_WRC_LOCAL_INVALIDATE 10 #define IBT_WRC_SEND_LSO 11 +#define IBT_WRC_INIT_SEND_FCMD 12 /* Init & Send for FCMD initiator */ +#define IBT_WRC_INIT_FEXCH 13 /* Init for FEXCH target */ /* @@ -1169,6 +1234,8 @@ typedef uint8_t ibt_wc_flags_t; #define IBT_WC_IMMED_DATA_PRESENT (1 << 1) #define IBT_WC_RKEY_INVALIDATED (1 << 2) #define IBT_WC_CKSUM_OK (1 << 3) +#define IBT_WC_FEXCH_FMT (1 << 4) +#define IBT_WC_DIF_ERROR (1 << 5) /* IPoIB flags for wc_detail field */ #define IBT_WC_DETAIL_ALL_FLAGS_MASK (0x0FC00000) @@ -1185,6 +1252,12 @@ typedef uint8_t ibt_wc_flags_t; #define IBT_WC_DETAIL_RSS_TCP_IPV4 (1 << 20) #define IBT_WC_DETAIL_RSS_IPV4 (1 << 21) +/* FEXCH flags for wc_detail field */ +#define IBT_WC_DETAIL_FC_MATCH_MASK (0xE000000) +#define IBT_WC_DETAIL_FEXCH_INIT_XFER (1 << 25) +#define IBT_WC_DETAIL_FEXCH_LAST (1 << 26) +#define IBT_WC_DETAIL_RFCI_CRC_OK (1 << 27) + /* * Work Request Completion - This structure encapsulates the information * necessary to define a work request completion. @@ -1211,6 +1284,13 @@ typedef struct ibt_wc_s { ib_path_bits_t wc_opaque4; } ibt_wc_t; +/* FC format alternative field names */ +#define wc_fexch_seq_cnt wc_cksum +#define wc_fexch_tx_bytes_xfer wc_immed_data +#define wc_fexch_rx_bytes_xfer wc_res_hash +#define wc_fexch_seq_id wc_opaque2 + + /* * WR Flags. Common for both RC and UD * @@ -1225,6 +1305,7 @@ typedef uint8_t ibt_wr_flags_t; #define IBT_WR_SEND_SOLICIT (1 << 3) /* Solicited Event Indicator */ #define IBT_WR_SEND_REMOTE_INVAL (1 << 4) /* Remote Invalidate */ #define IBT_WR_SEND_CKSUM (1 << 5) /* Checksum offload Indicator */ +#define IBT_WR_SEND_FC_CRC IBT_WR_SEND_CKSUM /* RFCI: FC CRC */ #define IBT_WR_SEND_INLINE (1 << 6) /* INLINE required (no lkey) */ /* @@ -1433,11 +1514,75 @@ typedef struct ibt_wr_lso_s { ib_msglen_t lso_mss; } ibt_wr_lso_t; +/* FC WR definitions */ +typedef enum ibt_fctl_flags_e { /* F_CTL flags */ + IBT_FCTL_NO_FLAGS = 0, + IBT_FCTL_SIT = (1 << 16), /* seq initiative transfer */ + IBT_FCTL_PRIO = (1 << 17), /* InitAndSend WR: priority */ + IBT_FCTL_LAST_SEQ = (1 << 20), + /* InitAndSend WR: Exchange Originator, set = initiator, off = tgt */ + IBT_FCTL_ORIG_INIT = (1 << 23) +} ibt_fctl_flags_t; +#define IBT_FCTL_SET_ABORT_FIELD(VAL) (((VAL) & 0x3) << 4) /* InitAndSend WR */ +#define IBT_FCTL_GET_ABORT_FIELD(FCTL) (((FCTL) & 0x30) >> 4) + +/* FC information category value, low 4 bits of routing control */ +#define IBT_FC_INFO_SOL_DATA 1 /* solicited data */ +#define IBT_FC_INFO_DATA_DESC 5 /* data descriptor */ +#define IBT_FC_INFO_UNSOL_CMD 6 /* unsolicited command */ +#define IBT_FC_INFO_CMD_STAT 7 /* command status */ + +typedef struct ibt_fc_ctl_s { + ibt_ud_dest_hdl_t fc_dest; + ibt_fctl_flags_t fc_frame_ctrl; + uint32_t fc_parameter; + uint8_t fc_seq_id; + /* FC R_CTL containing information category */ + uint8_t fc_routing_ctrl; +} ibt_fc_ctl_t; + +/* RFCI version of send */ +typedef struct ibt_wr_rfci_send_s { + ibt_ud_dest_hdl_t rfci_dest; + uint8_t rfci_eof; /* RFCI: when FC CRC set */ +} ibt_wr_rfci_send_t; + +typedef uint8_t ibt_init_send_op_t; +#define IBT_IS_OP_TARGET 0x0 /* target mode or no IO initiator op */ +#define IBT_IS_OP_NO_IO IBT_IS_OP_TARGET +#define IBT_IS_OP_IO_READ 0x1 /* IO read */ +#define IBT_IS_OP_IO_WRITE 0x2 /* IO write */ +#define IBT_IS_OP_BIDIR 0x3 /* bidirectional command */ + +/* Init and Send for FCMD initiator and also Init for FEXCH target */ +typedef struct ibt_wr_init_send_s { + ibt_fc_ctl_t is_ctl; + uint32_t is_dest_id; /* FC hdr: D_ID, low 24 bits */ + uint16_t is_fc_mtu; /* packet MTU (4B), low 10 bits */ + uint16_t is_rem_exch; /* target: remote exchange */ + uint16_t is_exch_qp_idx; /* FEXCH index for ULP */ + uint8_t is_cs_priority; /* FC hdr: CS_CTL/Priority */ + uint8_t is_tx_seq_id; /* initiator: FCP_DATA seq_id */ + ibt_init_send_op_t is_op; +} ibt_wr_init_send_t; + +typedef union ibt_wr_fc_u { + ibt_wr_rfci_send_t rfci_send; /* RFCI send */ + ibt_wr_init_send_t *fc_is; /* FCMD, FEXCH */ + ibt_wr_reg_pmr_t *reg_pmr; /* FCMD */ +} ibt_wr_fc_t; + + /* * Send Work Request (WR) attributes structure. * * Operation type in ibt_wrc_opcode_t. * Immediate Data indicator in ibt_wr_flags_t. + * + * RFCI initiator QP: send (FCP_CONF) + * FCMD initiator QP: init & send (FCP_CMND), FRWR + * FEXCH target QP: init, FRWR, RDMA-R (FCP_XFER_RDY), RDMA-W (FCP_DATA), + * Send (FCP_RSP) */ typedef struct ibt_send_wr_s { ibt_wrid_t wr_id; /* WR ID */ @@ -1456,11 +1601,17 @@ typedef struct ibt_send_wr_s { ibt_wr_reth_t reth; /* Reserved For Future Use */ ibt_wr_ripv6_t ripv6; /* Reserved For Future Use */ ibt_wr_lso_t ud_lso; + ibt_wr_fc_t fc; /* RFCI, FCMD, FEXCH */ } wr; /* operation specific */ } ibt_send_wr_t; /* * Receive Work Request (WR) attributes structure. + * + * also used by these FC QP types: + * RFCI initiator QP + * FEXCH initiator QP (FCP_RSP) + * RFCI target QP (FCP_CMND) */ typedef struct ibt_recv_wr_s { ibt_wrid_t wr_id; /* WR ID */ @@ -1514,7 +1665,8 @@ typedef enum ibt_async_code_e { IBT_ERROR_CATASTROPHIC_SRQ = 0x080000, IBT_PORT_CHANGE_EVENT = 0x100000, - IBT_CLNT_REREG_EVENT = 0x200000 + IBT_CLNT_REREG_EVENT = 0x200000, + IBT_FEXCH_ERROR = 0x400000 } ibt_async_code_t; #define IBT_PORT_EVENTS (IBT_EVENT_PORT_UP|IBT_PORT_CHANGE_EVENT|\ @@ -1530,6 +1682,10 @@ typedef enum ibt_port_change_e { IBT_PORT_CHANGE_REREG = 0x000040 /* IsClientReregSupport */ } ibt_port_change_t; +typedef uint8_t ibt_fc_syndrome_t; +#define IBT_FC_BAD_IU 0x0 +#define IBT_FC_BROKEN_SEQ 0x1 + /* * ibt_ci_data_in() and ibt_ci_data_out() flags. */ diff --git a/usr/src/uts/common/sys/ib/ibtl/ibvti.h b/usr/src/uts/common/sys/ib/ibtl/ibvti.h index 93dfbb68a9..64f7563f13 100644 --- a/usr/src/uts/common/sys/ib/ibtl/ibvti.h +++ b/usr/src/uts/common/sys/ib/ibtl/ibvti.h @@ -19,8 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_IBTL_IBVTI_H @@ -89,26 +88,6 @@ extern "C" { */ #define ibt_qp_hdl_t ibt_channel_hdl_t -/* - * ibt_cq_priority_t - * VTI clients have full control over CQ priorities. - */ -#define IBT_CQ_PRI_1 IBT_CQ_OPAQUE_1 /* Lowest priority */ -#define IBT_CQ_PRI_2 IBT_CQ_OPAQUE_2 -#define IBT_CQ_PRI_3 IBT_CQ_OPAQUE_3 -#define IBT_CQ_PRI_4 IBT_CQ_OPAQUE_4 -#define IBT_CQ_PRI_5 IBT_CQ_OPAQUE_5 -#define IBT_CQ_PRI_6 IBT_CQ_OPAQUE_6 -#define IBT_CQ_PRI_7 IBT_CQ_OPAQUE_7 -#define IBT_CQ_PRI_8 IBT_CQ_OPAQUE_8 -#define IBT_CQ_PRI_9 IBT_CQ_OPAQUE_9 -#define IBT_CQ_PRI_10 IBT_CQ_OPAQUE_10 -#define IBT_CQ_PRI_11 IBT_CQ_OPAQUE_11 -#define IBT_CQ_PRI_12 IBT_CQ_OPAQUE_12 -#define IBT_CQ_PRI_13 IBT_CQ_OPAQUE_13 -#define IBT_CQ_PRI_14 IBT_CQ_OPAQUE_14 -#define IBT_CQ_PRI_15 IBT_CQ_OPAQUE_15 -#define IBT_CQ_PRI_16 IBT_CQ_OPAQUE_16 /* Highest priority */ /* * FUNCTION PROTOTYPES. diff --git a/usr/src/uts/common/sys/ib/mgt/ibcm/ibcm_arp.h b/usr/src/uts/common/sys/ib/mgt/ibcm/ibcm_arp.h index 873b45b175..8c3cc3021a 100644 --- a/usr/src/uts/common/sys/ib/mgt/ibcm/ibcm_arp.h +++ b/usr/src/uts/common/sys/ib/mgt/ibcm/ibcm_arp.h @@ -90,6 +90,7 @@ typedef struct ibcm_arp_ip_s { } ip_sin; #define ip_cm_sin ip_sin.ip_sockaddr #define ip_cm_sin6 ip_sin.ip_sockaddr6 + zoneid_t ip_zoneid; } ibcm_arp_ip_t; typedef struct ibcm_arp_ibd_insts_s { diff --git a/usr/src/uts/common/sys/ib/mgt/ibcm/ibcm_impl.h b/usr/src/uts/common/sys/ib/mgt/ibcm/ibcm_impl.h index fb5c4aed0d..2fb6454396 100644 --- a/usr/src/uts/common/sys/ib/mgt/ibcm/ibcm_impl.h +++ b/usr/src/uts/common/sys/ib/mgt/ibcm/ibcm_impl.h @@ -19,8 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_IB_MGT_IBCM_IBCM_IMPL_H @@ -493,7 +492,7 @@ _NOTE(SCHEME_PROTECTS_DATA("Serailized access by block_client_cv", close_ret_priv_data_len close_ret_status})) _NOTE(DATA_READABLE_WITHOUT_LOCK(ibcm_state_data_s::{timedout_state - cm_handler mra_msg abort_flag})) + cm_handler mra_msg abort_flag local_qp_rnr_cnt})) /* * Definitions for send mad flags. Respective bits in send_mad_flags or |