diff options
| author | kchow <none@none> | 2008-05-22 13:30:16 -0700 |
|---|---|---|
| committer | kchow <none@none> | 2008-05-22 13:30:16 -0700 |
| commit | 512cf780ac27649047e2ce8d1aff51e92780765f (patch) | |
| tree | ff69aa472b5259e50149cb436d8dcfd260f48176 /usr/src/uts/intel/sys/controlregs.h | |
| parent | 4853e976fadf3d55239638b6a1fee20681fde314 (diff) | |
| download | illumos-joyent-512cf780ac27649047e2ce8d1aff51e92780765f.tar.gz | |
6671130 Shanghai provides better TLB management for 1GB pages
6679225 erratum 298 detection needed
6692442 errata updates needed for griffin processors (family 0x11)
Diffstat (limited to 'usr/src/uts/intel/sys/controlregs.h')
| -rw-r--r-- | usr/src/uts/intel/sys/controlregs.h | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/usr/src/uts/intel/sys/controlregs.h b/usr/src/uts/intel/sys/controlregs.h index d91c6a16b3..23e04d3286 100644 --- a/usr/src/uts/intel/sys/controlregs.h +++ b/usr/src/uts/intel/sys/controlregs.h @@ -19,7 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2007 Sun Microsystems, Inc. All rights reserved. + * Copyright 2008 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -196,6 +196,7 @@ extern "C" { #define MSR_AMD_HWCR 0xc0010015 +#define AMD_HWCR_TLBCACHEDIS (UINT64_C(1) << 3) #define AMD_HWCR_FFDIS 0x00040 /* disable TLB Flush Filter */ #define AMD_HWCR_MCI_STATUS_WREN 0x40000 /* enable write of MCi_STATUS */ @@ -203,11 +204,21 @@ extern "C" { #define MSR_AMD_NB_CFG 0xc001001f -#define MSR_BU_CFG 0xc0011023 - #define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20) #define AMD_NB_CFG_SRQ_SPR (UINT64_C(1) << 32) +#define MSR_AMD_BU_CFG 0xc0011023 + +#define AMD_BU_CFG_E298 (UINT64_C(1) << 1) + +/* AMD's osvw MSRs */ +#define MSR_AMD_OSVW_ID_LEN 0xc0010140 +#define MSR_AMD_OSVW_STATUS 0xc0010141 + + +#define OSVW_ID_LEN_MASK 0xffffULL +#define OSVW_ID_CNT_PER_MSR 64 + /* * Enable PCI Extended Configuration Space (ECS) on Greyhound */ |