PSARC 2007/591 Generic x86 Machine Check Architecture

PSARC 2007/594 Intel CPU and 5000/7300 Series Chipset FMA
6443855 x86 modinfo slots being wasted during cpu module path search
6475380 cmi_load() should unload unused CPU module
6520280 MCA status bits not properly being cleared for intel processors
6558878 topo_node_hash returns out of range hash
6567218 FMA for Intel processors and 5000/7300 series memory controller
6567634 generic x86 MCA support needs to be improved
6607616 prepare FMA/x86 for xVM
6607626 eversholt Makefile.com lacks a default target
6607637 Add number of cpus and cores per chip to cpu_info kstat
6607643 x86 on_trap handler jumps from frying pan into the fire
6616180 topo should translate slashes in authority fields

--HG--
rename : usr/src/uts/i86pc/cpu/amd_opteron/ao_mc.c => deleted_files/usr/src/uts/i86pc/cpu/amd_opteron/ao_mc.c
rename : usr/src/uts/i86xpv/generic_cpu/Makefile => deleted_files/usr/src/uts/i86xpv/generic_cpu/Makefile

12 files changed, 1124 insertions, 407 deletions

diff --git a/usr/src/uts/intel/sys/Makefile b/usr/src/uts/intel/sys/Makefile
index a90cb05ca6..3296cb5735 100644
--- a/usr/src/uts/intel/sys/Makefile
+++ b/usr/src/uts/intel/sys/Makefile
@@ -56,9 +56,9 @@ HDRS	=			\
 	machtypes.h		\
 	mc.h			\
 	mc_amd.h		\
+	mc_intel.h		\
 	mca_amd.h		\
 	mca_x86.h		\
-	memtest.h		\
 	mii.h			\
 	miipriv.h		\
 	mutex_impl.h		\
@@ -95,6 +95,7 @@ HDRS	=			\
 	x86_archext.h
 
 CLOSEDHDRS = \
+	memtest.h \
 	sbpro.h
 
 SUBHDRS	=			\
diff --git a/usr/src/uts/intel/sys/fm/cpu/AMD.h b/usr/src/uts/intel/sys/fm/cpu/AMD.h
index df66719ad3..7908c872a7 100644
--- a/usr/src/uts/intel/sys/fm/cpu/AMD.h
+++ b/usr/src/uts/intel/sys/fm/cpu/AMD.h
@@ -20,7 +20,7 @@
  */
 
 /*
- * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -33,153 +33,134 @@
 extern "C" {
 #endif
 
+/*
+ * AMD model-specific ereports.  These supplement the generic ereport
+ * members specified in GMCA.h.
+ */
+
 /* Ereport class subcategory for AMD processors */
 #define	FM_EREPORT_CPU_AMD	"amd"
 
 /*
  * Ereport payload definitions
  */
-#define	FM_EREPORT_PAYLOAD_NAME_BANK_STAT	"bank-status"
-#define	FM_EREPORT_PAYLOAD_NAME_BANK_NUM	"bank-number"
-#define	FM_EREPORT_PAYLOAD_NAME_ADDR		"addr"
-#define	FM_EREPORT_PAYLOAD_NAME_ADDR_VALID	"addr-valid"
-#define	FM_EREPORT_PAYLOAD_NAME_BANK_MISC	"bank-misc"
 #define	FM_EREPORT_PAYLOAD_NAME_SYND		"syndrome"
 #define	FM_EREPORT_PAYLOAD_NAME_SYND_TYPE	"syndrome-type"
-#define	FM_EREPORT_PAYLOAD_NAME_IP		"ip"
-#define	FM_EREPORT_PAYLOAD_NAME_PRIV		"privileged"
 #define	FM_EREPORT_PAYLOAD_NAME_RESOURCE	"resource"
 
-#define	FM_EREPORT_PAYLOAD_FLAG_BANK_STAT	0x0000000000000001
-#define	FM_EREPORT_PAYLOAD_FLAG_BANK_NUM	0x0000000000000002
-#define	FM_EREPORT_PAYLOAD_FLAG_ADDR		0x0000000000000004
-#define	FM_EREPORT_PAYLOAD_FLAG_ADDR_VALID	0x0000000000000008
-#define	FM_EREPORT_PAYLOAD_FLAG_SYND		0x0000000000000010
-#define	FM_EREPORT_PAYLOAD_FLAG_SYND_TYPE	0x0000000000000020
-#define	FM_EREPORT_PAYLOAD_FLAG_IP		0x0000000000000040
-#define	FM_EREPORT_PAYLOAD_FLAG_PRIV		0x0000000000000080
-#define	FM_EREPORT_PAYLOAD_FLAG_RESOURCE	0x0000000000000100
-#define	FM_EREPORT_PAYLOAD_FLAG_STACK		0x0000000000000200
-#define	FM_EREPORT_PAYLOAD_FLAG_BANK_MISC	0x0000000000000400
-
-#define	FM_EREPORT_PAYLOAD_FLAGS_BANK \
-	(FM_EREPORT_PAYLOAD_FLAG_BANK_STAT | FM_EREPORT_PAYLOAD_FLAG_BANK_NUM)
-#define	FM_EREPORT_PAYLOAD_FLAGS_ADDR \
-	(FM_EREPORT_PAYLOAD_FLAG_ADDR | FM_EREPORT_PAYLOAD_FLAG_ADDR_VALID)
+#define	FM_EREPORT_PAYLOAD_FLAG_SYND		0x0000000000000001
+#define	FM_EREPORT_PAYLOAD_FLAG_SYND_TYPE	0x0000000000000002
+#define	FM_EREPORT_PAYLOAD_FLAG_RESOURCE	0x0000000000000004
+#define	FM_EREPORT_PAYLOAD_FLAG_STACK		0x0000000000000008
+
+/*
+ * Model specific payload for each ereport type is specified using the
+ * following groupings of the individual flag values above.
+ */
+#define	FM_EREPORT_PAYLOAD_FLAGS_COMMON 0x0ULL	/* empty */
+
 #define	FM_EREPORT_PAYLOAD_FLAGS_SYND \
 	(FM_EREPORT_PAYLOAD_FLAG_SYND | FM_EREPORT_PAYLOAD_FLAG_SYND_TYPE)
 #define	FM_EREPORT_PAYLOAD_FLAGS_RESOURCE \
 	(FM_EREPORT_PAYLOAD_FLAG_RESOURCE)
-#define	FM_EREPORT_PAYLOAD_FLAGS_COMMON \
-	(FM_EREPORT_PAYLOAD_FLAGS_BANK | FM_EREPORT_PAYLOAD_FLAG_IP | \
-	FM_EREPORT_PAYLOAD_FLAG_PRIV)
 #define	FM_EREPORT_PAYLOAD_FLAGS_NB \
-	(FM_EREPORT_PAYLOAD_FLAG_STACK)
-#define	FM_EREPORT_PAYLOAD_FLAGS_BANK_MISC \
-	(FM_EREPORT_PAYLOAD_FLAG_BANK_MISC)
+	FM_EREPORT_PAYLOAD_FLAG_STACK
 
 #define	FM_EREPORT_PAYLOAD_FLAGS_1(f1) \
 	(FM_EREPORT_PAYLOAD_FLAGS_COMMON | FM_EREPORT_PAYLOAD_FLAGS_##f1)
 #define	FM_EREPORT_PAYLOAD_FLAGS_2(f1, f2) \
 	(FM_EREPORT_PAYLOAD_FLAGS_COMMON | FM_EREPORT_PAYLOAD_FLAGS_##f1 | \
 	FM_EREPORT_PAYLOAD_FLAGS_##f2)
-#define	FM_EREPORT_PAYLOAD_FLAGS_3(f1, f2, f3) \
-	(FM_EREPORT_PAYLOAD_FLAGS_COMMON | FM_EREPORT_PAYLOAD_FLAGS_##f1 | \
-	FM_EREPORT_PAYLOAD_FLAGS_##f2 | FM_EREPORT_PAYLOAD_FLAGS_##f3)
-#define	FM_EREPORT_PAYLOAD_FLAGS_4(f1, f2, f3, f4) \
-	(FM_EREPORT_PAYLOAD_FLAGS_COMMON | FM_EREPORT_PAYLOAD_FLAGS_##f1 | \
-	FM_EREPORT_PAYLOAD_FLAGS_##f2 | FM_EREPORT_PAYLOAD_FLAGS_##f3 | \
-	FM_EREPORT_PAYLOAD_FLAGS_##f4)
 
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_SYS_ECC1 \
-	FM_EREPORT_PAYLOAD_FLAGS_3(ADDR, SYND, RESOURCE)
+	FM_EREPORT_PAYLOAD_FLAGS_2(SYND, RESOURCE)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_L2_ECC1 \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+	FM_EREPORT_PAYLOAD_FLAGS_1(SYND)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_SYS_ECCM \
-	FM_EREPORT_PAYLOAD_FLAGS_3(ADDR, SYND, RESOURCE)
+	FM_EREPORT_PAYLOAD_FLAGS_2(SYND, RESOURCE)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_INF_L2_ECCM \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+	FM_EREPORT_PAYLOAD_FLAGS_1(SYND)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECC1 \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+	FM_EREPORT_PAYLOAD_FLAGS_1(SYND)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECC1_UC \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+	FM_EREPORT_PAYLOAD_FLAGS_1(SYND)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_DATA_ECCM \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+	FM_EREPORT_PAYLOAD_FLAGS_1(SYND)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_TAG_PAR \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_STAG_PAR \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L1TLB_PAR \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_DC_L2TLB_PAR \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_SYS_ECC1 \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_L2_ECC1 \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_SYS_ECCM \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_INF_L2_ECCM \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_DATA_PAR \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_TAG_PAR \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_STAG_PAR \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L1TLB_PAR \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_L2TLB_PAR \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_IC_RDDE \
 	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2D_ECC1 \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+	FM_EREPORT_PAYLOAD_FLAGS_1(SYND)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2D_ECCM \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+	FM_EREPORT_PAYLOAD_FLAGS_1(SYND)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_PAR \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_ECC1 \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+	FM_EREPORT_PAYLOAD_FLAGS_1(SYND)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_L2T_ECCM \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, SYND)
+	FM_EREPORT_PAYLOAD_FLAGS_1(SYND)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_RDE \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECC1 \
-	FM_EREPORT_PAYLOAD_FLAGS_3(ADDR, SYND, RESOURCE)
+	FM_EREPORT_PAYLOAD_FLAGS_2(SYND, RESOURCE)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_BU_S_ECCM \
-	FM_EREPORT_PAYLOAD_FLAGS_3(ADDR, SYND, RESOURCE)
+	FM_EREPORT_PAYLOAD_FLAGS_2(SYND, RESOURCE)
 
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_LS_S_RDE \
 	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_CE \
-	FM_EREPORT_PAYLOAD_FLAGS_4(ADDR, SYND, RESOURCE, BANK_MISC)
+	FM_EREPORT_PAYLOAD_FLAGS_2(SYND, RESOURCE)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MEM_UE \
-	FM_EREPORT_PAYLOAD_FLAGS_4(ADDR, SYND, RESOURCE, BANK_MISC)
+	FM_EREPORT_PAYLOAD_FLAGS_2(SYND, RESOURCE)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_HT_CRC \
 	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_HT_SYNC \
 	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_MA \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, NB)
+	FM_EREPORT_PAYLOAD_FLAGS_1(NB)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_TA \
-	FM_EREPORT_PAYLOAD_FLAGS_2(ADDR, NB)
+	FM_EREPORT_PAYLOAD_FLAGS_1(NB)
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_GART_WALK \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_RMW \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_WDOG \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_NB_DRAMADDR_PAR \
 	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_MC_TESTFAIL \
 	FM_EREPORT_PAYLOAD_FLAG_RESOURCE
 
 #define	FM_EREPORT_PAYLOAD_FLAGS_CPU_AMD_UNKNOWN \
-	FM_EREPORT_PAYLOAD_FLAGS_1(ADDR)
+	FM_EREPORT_PAYLOAD_FLAGS_COMMON
 
 #define	FM_EREPORT_CPU_AMD_DC_INF_SYS_ECC1	"dc.inf_sys_ecc1"
 #define	FM_EREPORT_CPU_AMD_DC_INF_SYS_ECCM	"dc.inf_sys_eccm"
diff --git a/usr/src/uts/intel/sys/fm/cpu/GENAMD.h b/usr/src/uts/intel/sys/fm/cpu/GENAMD.h
new file mode 100644
index 0000000000..7654877976
--- /dev/null
+++ b/usr/src/uts/intel/sys/fm/cpu/GENAMD.h
@@ -0,0 +1,91 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_FM_CPU_GENAMD_H
+#define	_SYS_FM_CPU_GENAMD_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+/* Ereport class subcategory - same as in GMCA.h */
+#define	FM_EREPORT_CPU_GENAMD	"generic-x86"
+
+/* Ereport leaf classes */
+#define	FM_EREPORT_CPU_GENAMD_MEM_CE		"mem_ce"
+#define	FM_EREPORT_CPU_GENAMD_MEM_UE		"mem_ue"
+#define	FM_EREPORT_CPU_GENAMD_CKMEM_CE		"mem_ce"
+#define	FM_EREPORT_CPU_GENAMD_CKMEM_UE		"mem_ue"
+#define	FM_EREPORT_CPU_GENADM_GARTTBLWLK	"gart_tbl_walk"
+
+#define	_FM_EREPORT_FLAG(n) (1ULL << (n))
+
+#define	FM_EREPORT_GENAMD_PAYLOAD_NAME_SYND		"syndrome"
+#define	FM_EREPORT_GENAMD_PAYLOAD_FLAG_SYND		_FM_EREPORT_FLAG(1)
+
+#define	FM_EREPORT_GENAMD_PAYLOAD_NAME_CKSYND		"syndrome"
+#define	FM_EREPORT_GENAMD_PAYLOAD_FLAG_CKSYND		_FM_EREPORT_FLAG(2)
+
+#define	FM_EREPORT_GENAMD_PAYLOAD_NAME_SYNDTYPE		"syndrome-type"
+#define	FM_EREPORT_GENAMD_PAYLOAD_FLAG_SYNDTYPE		_FM_EREPORT_FLAG(3)
+
+#define	FM_EREPORT_GENAMD_PAYLOAD_NAME_RESOURCE		"resource"
+#define	FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCE		_FM_EREPORT_FLAG(4)
+
+#define	FM_EREPORT_GENAMD_PAYLOAD_NAME_RESOURCECNT	"resource_counts"
+#define	FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCECNT	_FM_EREPORT_FLAG(5)
+
+#define	FM_EREPORT_GENAMD_PAYLOAD_FLAGS_MEM_CE \
+	(FM_EREPORT_GENAMD_PAYLOAD_FLAG_SYND | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_SYNDTYPE | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCE | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCECNT)
+
+#define	FM_EREPORT_GENAMD_PAYLOAD_FLAGS_MEM_UE \
+	(FM_EREPORT_GENAMD_PAYLOAD_FLAG_SYND | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_SYNDTYPE | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCE | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCECNT)
+
+#define	FM_EREPORT_GENAMD_PAYLOAD_FLAGS_CKMEM_CE \
+	(FM_EREPORT_GENAMD_PAYLOAD_FLAG_CKSYND | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_SYNDTYPE | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCE | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCECNT)
+
+#define	FM_EREPORT_GENAMD_PAYLOAD_FLAGS_CKMEM_UE \
+	(FM_EREPORT_GENAMD_PAYLOAD_FLAG_CKSYND | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_SYNDTYPE | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCE | \
+	FM_EREPORT_GENAMD_PAYLOAD_FLAG_RESOURCECNT)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_FM_CPU_GENAMD_H */
diff --git a/usr/src/uts/intel/sys/fm/cpu/GMCA.h b/usr/src/uts/intel/sys/fm/cpu/GMCA.h
new file mode 100644
index 0000000000..c677efad87
--- /dev/null
+++ b/usr/src/uts/intel/sys/fm/cpu/GMCA.h
@@ -0,0 +1,201 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef	_SYS_FM_CPU_GMCA_H
+#define	_SYS_FM_CPU_GMCA_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Generic x86 cpu ereports.
+ *
+ * On a machine-check exception, or on a periodic poll for error status
+ * of a cpu, we read through all the MCA banks of the processor and
+ * log an ereport for each MCA bank that contains valid error telemetry.
+ * These ereports will all share the same detector FMRI and ENA.
+ *
+ * Since we have no model-specific knowledge of the cpu we cannot
+ * decode all details of the error, so we'll stick to the "architectural"
+ * bits.  Similarly since we have no associated memory-controller driver
+ * or detailed topology information we cannot produce "resource" ereport
+ * FMRIs.
+ */
+
+/* Ereport class subcategory for generic x86 processors */
+#define	FM_EREPORT_CPU_GENERIC	"generic-x86"
+
+/*
+ * Simple error code ereport leaf classes
+ */
+#define	FM_EREPORT_CPU_GENERIC_UNCLASSIFIED	"unclassified"
+#define	FM_EREPORT_CPU_GENERIC_MC_CODE_PARITY	"microcode_rom_parity"
+#define	FM_EREPORT_CPU_GENERIC_EXTERNAL		"external"
+#define	FM_EREPORT_CPU_GENERIC_FRC		"frc"
+#define	FM_EREPORT_CPU_GENERIC_INTERNAL_TIMER	"internal_timer"
+#define	FM_EREPORT_CPU_GENERIC_INTERNAL_UNCLASS	"internal_unclassified"
+
+/*
+ * Leaf class to be used when we can match no simple or compound class
+ */
+#define	FM_EREPORT_CPU_GENERIC_UNKNOWN		"unknown"
+
+/*
+ * Compound error code ereport leaf classes.  The arguments for snprintf
+ * will appear in the following order:
+ *
+ *	1 - TT interpretation
+ *	2 - LL interpretation
+ *	3 - RRRR interpretation
+ *	4 - PP interpretation
+ *	5 - II interpretation
+ *	6 - T interpretation
+ *	7 - "_uc" if this is a compound error with MCi_STATUS.UC set, else ""
+ *
+ * They can be selected in the format string using the %n$s specifier form.
+ *
+ * The set of interpretations that we expand to will not be exactly the
+ * same as the set of mnemonics described in Vol 3A (see the
+ * FM_EREPORT_PAYLOAD_NAME_COMPOUND_ERR ereport payload member for that).
+ * Instead we wish to compress the possible ereport classes that can
+ * be generated by pushing things such as "LG" for generic cache level
+ * down to "".
+ *
+ *
+ * "Memory Hierarchy" in compound errors actually refers to CPU cache
+ * memory.
+ */
+#define	FM_EREPORT_CPU_GENERIC_GENMEMHIER	"%2$s" "cache" "%7$s"
+#define	FM_EREPORT_CPU_GENERIC_TLB		"%2$s" "%1$s" "tlb" "%7$s"
+#define	FM_EREPORT_CPU_GENERIC_MEMHIER		"%2$s" "%1$s" "cache" "%7$s"
+#define	FM_EREPORT_CPU_GENERIC_BUS_INTERCONNECT	"bus_interconnect" "%5$s" "%7$s"
+
+/*
+ * The "interpretation" expansions for the above ereport leaf subclasses.
+ */
+#define	FM_EREPORT_CPU_GENERIC_TT_INSTR		"i"
+#define	FM_EREPORT_CPU_GENERIC_TT_DATA		"d"
+#define	FM_EREPORT_CPU_GENERIC_TT_GEN		""
+
+#define	FM_EREPORT_CPU_GENERIC_LL_L0		"l0"
+#define	FM_EREPORT_CPU_GENERIC_LL_L1		"l1"
+#define	FM_EREPORT_CPU_GENERIC_LL_L2		"l2"
+#define	FM_EREPORT_CPU_GENERIC_LL_LG		""
+
+#define	FM_EREPORT_CPU_GENERIC_RRRR_ERR		""
+#define	FM_EREPORT_CPU_GENERIC_RRRR_RD		""
+#define	FM_EREPORT_CPU_GENERIC_RRRR_WR		""
+#define	FM_EREPORT_CPU_GENERIC_RRRR_DRD		""
+#define	FM_EREPORT_CPU_GENERIC_RRRR_DWR		""
+#define	FM_EREPORT_CPU_GENERIC_RRRR_IRD		""
+#define	FM_EREPORT_CPU_GENERIC_RRRR_PREFETCH	""
+#define	FM_EREPORT_CPU_GENERIC_RRRR_EVICT	""
+#define	FM_EREPORT_CPU_GENERIC_RRRR_SNOOP	""
+
+#define	FM_EREPORT_CPU_GENERIC_PP_SRC		""
+#define	FM_EREPORT_CPU_GENERIC_PP_RES		""
+#define	FM_EREPORT_CPU_GENERIC_PP_OBS		""
+#define	FM_EREPORT_CPU_GENERIC_PP_GEN		""
+
+#define	FM_EREPORT_CPU_GENERIC_II_MEM		"_memory"
+#define	FM_EREPORT_CPU_GENERIC_II_IO		"_io"
+#define	FM_EREPORT_CPU_GENERIC_II_GEN		""
+
+#define	FM_EREPORT_CPU_GENERIC_T_NOTIMEOUT	""
+#define	FM_EREPORT_CPU_GENERIC_T_TIMEOUT	""
+
+/*
+ * Ereport payload member names together with bitmask values to select
+ * their inclusion in ereports.
+ */
+
+#define	_FM_EREPORT_FLAG(n) (1ULL << (n))
+
+#define	FM_EREPORT_PAYLOAD_FLAG_COMPOUND_ERR _FM_EREPORT_FLAG(1)
+#define	FM_EREPORT_PAYLOAD_NAME_COMPOUND_ERR	"compound_errorname"
+
+#define	FM_EREPORT_PAYLOAD_FLAG_MCG_STATUS _FM_EREPORT_FLAG(2)
+#define	FM_EREPORT_PAYLOAD_NAME_MCG_STATUS	"IA32_MCG_STATUS"
+#define	FM_EREPORT_PAYLOAD_NAME_MCG_STATUS_MCIP	"machine_check_in_progress"
+
+#define	FM_EREPORT_PAYLOAD_FLAG_IP _FM_EREPORT_FLAG(3)
+#define	FM_EREPORT_PAYLOAD_NAME_IP		"ip"
+
+#define	FM_EREPORT_PAYLOAD_FLAG_PRIV _FM_EREPORT_FLAG(4)
+#define	FM_EREPORT_PAYLOAD_NAME_PRIV		"privileged"
+
+#define	FM_EREPORT_PAYLOAD_FLAG_BANK_NUM _FM_EREPORT_FLAG(5)
+#define	FM_EREPORT_PAYLOAD_NAME_BANK_NUM	"bank_number"
+#define	FM_EREPORT_PAYLOAD_NAME_BANK_MSR_OFFSET	"bank_msr_offset"
+
+#define	FM_EREPORT_PAYLOAD_FLAG_MC_STATUS _FM_EREPORT_FLAG(6)
+#define	FM_EREPORT_PAYLOAD_NAME_MC_STATUS	"IA32_MCi_STATUS"
+#define	FM_EREPORT_PAYLOAD_NAME_MC_STATUS_OVER	"overflow"
+#define	FM_EREPORT_PAYLOAD_NAME_MC_STATUS_UC	"error_uncorrected"
+#define	FM_EREPORT_PAYLOAD_NAME_MC_STATUS_EN	"error_enabled"
+#define	FM_EREPORT_PAYLOAD_NAME_MC_STATUS_PCC	"processor_context_corrupt"
+#define	FM_EREPORT_PAYLOAD_NAME_MC_STATUS_TES	"threshold_based_error_status"
+#define	FM_EREPORT_PAYLOAD_NAME_MC_STATUS_ERRCODE "error_code"
+#define	FM_EREPORT_PAYLOAD_NAME_MC_STATUS_EXTERRCODE "model_specific_error_code"
+
+#define	FM_EREPORT_PAYLOAD_FLAG_MC_ADDR _FM_EREPORT_FLAG(7)
+#define	FM_EREPORT_PAYLOAD_NAME_MC_ADDR		"IA32_MCi_ADDR"
+
+#define	FM_EREPORT_PAYLOAD_FLAG_MC_MISC _FM_EREPORT_FLAG(8)
+#define	FM_EREPORT_PAYLOAD_NAME_MC_MISC		"IA32_MCi_MISC"
+
+#define	FM_EREPORT_PAYLOAD_FLAG_DISP	_FM_EREPORT_FLAG(9)
+#define	FM_EREPORT_PAYLOAD_NAME_DISP		"disp"
+
+/*
+ * Common combinations of payload members
+ */
+#define	FM_EREPORT_PAYLOAD_FLAGS_GLOBAL \
+	(FM_EREPORT_PAYLOAD_FLAG_MCG_STATUS | \
+	FM_EREPORT_PAYLOAD_FLAG_IP | \
+	FM_EREPORT_PAYLOAD_FLAG_PRIV)
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_BANK \
+	(FM_EREPORT_PAYLOAD_FLAG_BANK_NUM | \
+	FM_EREPORT_PAYLOAD_FLAG_MC_STATUS | \
+	FM_EREPORT_PAYLOAD_FLAG_MC_ADDR | \
+	FM_EREPORT_PAYLOAD_FLAG_MC_MISC | \
+	FM_EREPORT_PAYLOAD_FLAG_DISP)
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_COMMON \
+	(FM_EREPORT_PAYLOAD_FLAGS_GLOBAL | FM_EREPORT_PAYLOAD_FLAGS_BANK)
+
+#define	FM_EREPORT_PAYLOAD_FLAGS_COMPOUND_ERR \
+	(FM_EREPORT_PAYLOAD_FLAGS_COMMON | FM_EREPORT_PAYLOAD_FLAG_COMPOUND_ERR)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_FM_CPU_GMCA_H */
diff --git a/usr/src/uts/intel/sys/mc.h b/usr/src/uts/intel/sys/mc.h
index 4e1ab003ee..27ef52684d 100644
--- a/usr/src/uts/intel/sys/mc.h
+++ b/usr/src/uts/intel/sys/mc.h
@@ -18,7 +18,7 @@
  *
  * CDDL HEADER END
  *
- * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -41,12 +41,13 @@ extern "C" {
 #define	MC_UNUM_NDIMM		2
 
 typedef struct mc_unum {
-	int unum_board;
-	int unum_chip;
-	int unum_mc;
-	int unum_cs;
-	int unum_rank;
-	uint64_t unum_offset;
+	int unum_board;			/* system board */
+	int unum_chip;			/* chip/socket */
+	int unum_mc;			/* memory-controller or branch */
+	int unum_chan;			/* DRAM channel */
+	int unum_cs;			/* chip-select */
+	int unum_rank;			/* rank */
+	uint64_t unum_offset;		/* row, column, bank-select etc */
 	int unum_dimms[MC_UNUM_NDIMM];
 } mc_unum_t;
 
@@ -55,8 +56,6 @@ typedef struct mc_unum {
  */
 #define	MC_INVALNUM		((uint32_t)-1)
 
-#define	MC_AMD_DEV_OFFSET	24	/* node ID + offset == PCI dev num */
-
 /*
  * /dev/mc/mc* ioctl cmds
  */
diff --git a/usr/src/uts/intel/sys/mc_amd.h b/usr/src/uts/intel/sys/mc_amd.h
index 6e799b2cf2..79b03d9e70 100644
--- a/usr/src/uts/intel/sys/mc_amd.h
+++ b/usr/src/uts/intel/sys/mc_amd.h
@@ -28,6 +28,7 @@
 #pragma ident	"%Z%%M%	%I%	%E% SMI"
 
 #include <sys/mc.h>
+#include <sys/isa_defs.h>
 #include <sys/x86_archext.h>
 
 #ifdef __cplusplus
@@ -124,13 +125,16 @@ extern "C" {
 
 /*
  * Memory controller registers are read via PCI config space accesses on
- * bus 0, device 24 + NodeId, and function as follows:
+ * bus 0, device 0x18 + NodeId, and function as follows:
  *
  * Function 0: HyperTransport Technology Configuration
  * Function 1: Address Map
  * Function 2: DRAM Controller & HyperTransport Technology Trace Mode
  * Function 3: Miscellaneous Control
  */
+
+#define	MC_AMD_DEV_OFFSET	0x18	/* node ID + offset == PCI dev num */
+
 enum mc_funcnum {
 	MC_FUNC_HTCONFIG = 0,
 	MC_FUNC_ADDRMAP	= 1,
@@ -197,7 +201,17 @@ enum mc_funcnum {
 #define	MC_CTL_REG_SPARECTL	0xb0	/* On-line spare control register */
 
 /*
- * Registers will be represented as unions, with one fixed-width unsigned
+ * MC4_MISC MSR and MC4_MISCj MSRs
+ */
+#define	MC_MSR_NB_MISC0		0x413
+#define	MC_MSR_NB_MISC1		0xc0000408
+#define	MC_MSR_NB_MISC2		0xc0000409
+#define	MC_MSR_NB_MISC3		0xc000040a
+#define	MC_MSR_NB_MISC(j) \
+	((j) == 0 ? MC_MSR_NB_MISC0 : MC_MSR_NB_MISC1 + (j) - 1)
+
+/*
+ * PCI registers will be represented as unions, with one fixed-width unsigned
  * integer member providing access to the raw register value and one or more
  * structs breaking the register out into bitfields (more than one struct if
  * the register definitions varies across processor revisions).
@@ -209,8 +223,9 @@ enum mc_funcnum {
  * processor revision to which it applies.  At this point the only xxx
  * values in use are:
  *			'cmn' - applies to all revisions
- *			'preF' - applies to revisions E and earlier
- *			'revFG' - applies to revisions F and G
+ *			'f_preF' - applies to revisions E and earlier
+ *			'f_revFG' - applies to revisions F and G
+ *
  * Variants such as 'preD', 'revDE', 'postCG' etc should be introduced
  * as requirements arise.  The MC_REV_* and MC_REV_MATCH etc macros
  * will also need to grow to match.  Use MCREG_FIELD_* to access the
@@ -222,20 +237,26 @@ enum mc_funcnum {
  */
 
 #define	MC_REV_UNKNOWN	X86_CHIPREV_UNKNOWN
-#define	MC_REV_B	X86_CHIPREV_AMD_F_REV_B
-#define	MC_REV_C	(X86_CHIPREV_AMD_F_REV_C0 | X86_CHIPREV_AMD_F_REV_CG)
-#define	MC_REV_D	X86_CHIPREV_AMD_F_REV_D
-#define	MC_REV_E	X86_CHIPREV_AMD_F_REV_E
-#define	MC_REV_F	X86_CHIPREV_AMD_F_REV_F
-#define	MC_REV_G	X86_CHIPREV_AMD_F_REV_G
+
+#define	MC_F_REV_B	X86_CHIPREV_AMD_F_REV_B
+#define	MC_F_REV_C	(X86_CHIPREV_AMD_F_REV_C0 | X86_CHIPREV_AMD_F_REV_CG)
+#define	MC_F_REV_D	X86_CHIPREV_AMD_F_REV_D
+#define	MC_F_REV_E	X86_CHIPREV_AMD_F_REV_E
+#define	MC_F_REV_F	X86_CHIPREV_AMD_F_REV_F
+#define	MC_F_REV_G	X86_CHIPREV_AMD_F_REV_G
+
+#define	MC_10_REV_A	X86_CHIPREV_AMD_10_REV_A
+#define	MC_10_REV_B	X86_CHIPREV_AMD_10_REV_B
 
 /*
  * The most common groupings for memory controller features.
  */
-#define	MC_REVS_BC	(MC_REV_B | MC_REV_C)
-#define	MC_REVS_DE	(MC_REV_D | MC_REV_E)
-#define	MC_REVS_BCDE	(MC_REVS_BC | MC_REVS_DE)
-#define	MC_REVS_FG	(MC_REV_F | MC_REV_G)
+#define	MC_F_REVS_BC	(MC_F_REV_B | MC_F_REV_C)
+#define	MC_F_REVS_DE	(MC_F_REV_D | MC_F_REV_E)
+#define	MC_F_REVS_BCDE	(MC_F_REVS_BC | MC_F_REVS_DE)
+#define	MC_F_REVS_FG	(MC_F_REV_F | MC_F_REV_G)
+
+#define	MC_10_REVS_AB	(MC_10_REV_A | MC_10_REV_B)
 
 /*
  * Is 'rev' included in the 'revmask' bitmask?
@@ -251,9 +272,30 @@ enum mc_funcnum {
 
 #define	MCREG_VAL32(up) ((up)->_val32)
 
+/*
+ * Access a field that has the same structure in all families and revisions
+ */
 #define	MCREG_FIELD_CMN(up, field)	_MCREG_FIELD(up, cmn, field)
-#define	MCREG_FIELD_preF(up, field)	_MCREG_FIELD(up, preF, field)
-#define	MCREG_FIELD_revFG(up, field)	_MCREG_FIELD(up, revFG, field)
+
+/*
+ * Access a field as defined for family 0xf prior to revision F
+ */
+#define	MCREG_FIELD_F_preF(up, field)	_MCREG_FIELD(up, f_preF, field)
+
+/*
+ * Access a field as defined for family 0xf revisions F and G
+ */
+#define	MCREG_FIELD_F_revFG(up, field)	_MCREG_FIELD(up, f_revFG, field)
+
+/*
+ * Access a field as defined for family 0x10 revisions A and
+ */
+#define	MCREG_FIELD_10_revAB(up, field)	_MCREG_FIELD(up, 10_revAB, field)
+
+/*
+ * We will only define the register bitfields for little-endian order
+ */
+#ifdef	_BIT_FIELDS_LTOH
 
 /*
  * Function 0 - HT Configuration: Routing Table Node Register
@@ -370,7 +412,7 @@ union mcreg_dramhole {
 union mcreg_csbase {
 	uint32_t	_val32;
 	/*
-	 * Register format in revisions E and earlier
+	 * Register format in family 0xf revisions E and earlier
 	 */
 	struct {
 		uint32_t	CSEnable:1;	/*  0:0  - CS Bank Enable */
@@ -378,9 +420,9 @@ union mcreg_csbase {
 		uint32_t	BaseAddrLo:7;	/* 15:9  - Base Addr 19:13 */
 		uint32_t	reserved2:5;	/* 20:16 */
 		uint32_t	BaseAddrHi:11;	/* 31:21 - Base Addr 35:25 */
-	} _fmt_preF;
+	} _fmt_f_preF;
 	/*
-	 * Register format in revisions F and G
+	 * Register format in family 0xf revisions F and G
 	 */
 	struct {
 		uint32_t	CSEnable:1;	/*  0:0  - CS Bank Enable */
@@ -391,14 +433,14 @@ union mcreg_csbase {
 		uint32_t	reserved2:5;	/* 18:14 */
 		uint32_t	BaseAddrHi:10;	/* 28:19 - Base Addr 36:27 */
 		uint32_t	reserved3:3;	/* 31:39 */
-	} _fmt_revFG;
+	} _fmt_f_revFG;
 };
 
-#define	MC_CSBASE(up, rev) (MC_REV_MATCH(rev, MC_REVS_FG) ?	\
-	(uint64_t)MCREG_FIELD_revFG(up, BaseAddrHi) << 27 |		\
-	(uint64_t)MCREG_FIELD_revFG(up, BaseAddrLo) << 13 :		\
-	(uint64_t)MCREG_FIELD_preF(up, BaseAddrHi) << 25 |		\
-	(uint64_t)MCREG_FIELD_preF(up, BaseAddrLo) << 13)
+#define	MC_CSBASE(up, rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ?	\
+	(uint64_t)MCREG_FIELD_F_revFG(up, BaseAddrHi) << 27 |		\
+	(uint64_t)MCREG_FIELD_F_revFG(up, BaseAddrLo) << 13 :		\
+	(uint64_t)MCREG_FIELD_F_preF(up, BaseAddrHi) << 25 |		\
+	(uint64_t)MCREG_FIELD_F_preF(up, BaseAddrLo) << 13)
 
 /*
  * Function 2 - DRAM Controller: DRAM CS Mask Registers
@@ -407,7 +449,7 @@ union mcreg_csbase {
 union mcreg_csmask {
 	uint32_t	_val32;
 	/*
-	 * Register format in revisions E and earlier
+	 * Register format in family 0xf revisions E and earlier
 	 */
 	struct {
 		uint32_t	reserved1:9;	/*  8:0 */
@@ -415,9 +457,9 @@ union mcreg_csmask {
 		uint32_t	reserved2:5;	/* 20:16 */
 		uint32_t	AddrMaskHi:9;	/* 29:21 - Addr Mask 33:25 */
 		uint32_t	reserved3:2;	/* 31:30 */
-	} _fmt_preF;
+	} _fmt_f_preF;
 	/*
-	 * Register format in revisions F and G
+	 * Register format in family 0xf revisions F and G
 	 */
 	struct {
 		uint32_t	reserved1:5;	/*  4:0 */
@@ -425,22 +467,22 @@ union mcreg_csmask {
 		uint32_t	reserved2:5;	/* 18:14 */
 		uint32_t	AddrMaskHi:10;	/* 28:19 - Addr Mask 36:27 */
 		uint32_t	reserved3:3;	/* 31:29 */
-	} _fmt_revFG;
+	} _fmt_f_revFG;
 };
 
-#define	MC_CSMASKLO_LOBIT(rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? 13 : 13)
-#define	MC_CSMASKLO_HIBIT(rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? 21 : 19)
+#define	MC_CSMASKLO_LOBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 13 : 13)
+#define	MC_CSMASKLO_HIBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 21 : 19)
 
-#define	MC_CSMASKHI_LOBIT(rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? 27 : 25)
-#define	MC_CSMASKHI_HIBIT(rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? 36 : 33)
+#define	MC_CSMASKHI_LOBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 27 : 25)
+#define	MC_CSMASKHI_HIBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 36 : 33)
 
-#define	MC_CSMASK_UNMASKABLE(rev) (MC_REV_MATCH(rev, MC_REVS_FG) ? 0 : 2)
+#define	MC_CSMASK_UNMASKABLE(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 0 : 2)
 
-#define	MC_CSMASK(up, rev) (MC_REV_MATCH(rev, MC_REVS_FG) ?		\
-	(uint64_t)MCREG_FIELD_revFG(up, AddrMaskHi) << 27 |		\
-	(uint64_t)MCREG_FIELD_revFG(up, AddrMaskLo) << 13 | 0x7c01fff :	\
-	(uint64_t)MCREG_FIELD_preF(up, AddrMaskHi) << 25 |		\
-	(uint64_t)MCREG_FIELD_preF(up, AddrMaskLo) << 13 | 0x1f01fff)
+#define	MC_CSMASK(up, rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? \
+	(uint64_t)MCREG_FIELD_F_revFG(up, AddrMaskHi) << 27 | \
+	(uint64_t)MCREG_FIELD_F_revFG(up, AddrMaskLo) << 13 | 0x7c01fff : \
+	(uint64_t)MCREG_FIELD_F_preF(up, AddrMaskHi) << 25 | \
+	(uint64_t)MCREG_FIELD_F_preF(up, AddrMaskLo) << 13 | 0x1f01fff)
 
 /*
  * Function 2 - DRAM Controller: DRAM Bank Address Mapping Registers
@@ -449,7 +491,7 @@ union mcreg_csmask {
 union mcreg_bankaddrmap {
 	uint32_t	_val32;
 	/*
-	 * Register format in revisions E and earlier
+	 * Register format in family 0xf revisions E and earlier
 	 */
 	struct {
 		uint32_t	cs10:4;			/*  3:0  - CS1/0 */
@@ -459,9 +501,9 @@ union mcreg_bankaddrmap {
 		uint32_t	reserved1:14;		/* 29:16 */
 		uint32_t	BankSwizzleMode:1;	/* 30:30 */
 		uint32_t	reserved2:1;		/* 31:31 */
-	} _fmt_preF;
+	} _fmt_f_preF;
 	/*
-	 * Register format in revisions F and G
+	 * Register format in family 0xf revisions F and G
 	 */
 	struct {
 		uint32_t	cs10:4;			/*  3:0  - CS1/0 */
@@ -469,7 +511,7 @@ union mcreg_bankaddrmap {
 		uint32_t	cs54:4;			/* 11:8  - CS5/4 */
 		uint32_t	cs76:4;			/* 15:12 - CS7/6 */
 		uint32_t	reserved1:16;		/* 31:16 */
-	} _fmt_revFG;
+	} _fmt_f_revFG;
 	/*
 	 * Accessing all mode encodings as one uint16
 	 */
@@ -492,7 +534,7 @@ union mcreg_bankaddrmap {
 union mcreg_dramcfg_lo {
 	uint32_t _val32;
 	/*
-	 * Register format in revisions E and earlier.
+	 * Register format in family 0xf revisions E and earlier.
 	 * Bit 7 is a BIOS ScratchBit in revs D and earlier,
 	 * PwrDwnTriEn in revision E;  we don't use it so
 	 * we'll call it ambig1.
@@ -523,9 +565,9 @@ union mcreg_dramcfg_lo {
 		uint32_t	En2T:1;		/* 28 */
 		uint32_t	UpperCSMap:1;	/* 29 */
 		uint32_t	PwrDownCtl:2;	/* 31:30 */
-	} _fmt_preF;
+	} _fmt_f_preF;
 	/*
-	 * Register format in revisions F and G
+	 * Register format in family 0xf revisions F and G
 	 */
 	struct {
 		uint32_t	InitDram:1;		/* 0 */
@@ -543,7 +585,7 @@ union mcreg_dramcfg_lo {
 		uint32_t	reserved3:2;		/* 18:17 */
 		uint32_t	DimmEccEn:1;		/* 19 */
 		uint32_t	reserved4:12;		/* 31:20 */
-	} _fmt_revFG;
+	} _fmt_f_revFG;
 };
 
 /*
@@ -553,7 +595,7 @@ union mcreg_dramcfg_lo {
 union mcreg_drammisc {
 	uint32_t _val32;
 	/*
-	 * Register format in revisions F and G
+	 * Register format in family 0xf revisions F and G
 	 */
 	struct {
 		uint32_t	reserved2:1;		/* 0 */
@@ -566,13 +608,13 @@ union mcreg_drammisc {
 		uint32_t	PwrSavingsEn:1;		/* 10 */
 		uint32_t	reserved1:13;		/* 23:11 */
 		uint32_t	MemClkDis:8;		/* 31:24 */
-	} _fmt_revFG;
+	} _fmt_f_revFG;
 };
 
 union mcreg_dramcfg_hi {
 	uint32_t _val32;
 	/*
-	 * Register format in revisions E and earlier.
+	 * Register format in family 0xf revisions E and earlier.
 	 */
 	struct {
 		uint32_t	AsyncLat:4;		/* 3:0 */
@@ -592,9 +634,9 @@ union mcreg_dramcfg_hi {
 		uint32_t	MC3_EN:1;		/* 29 */
 		uint32_t	reserved4:1;		/* 30 */
 		uint32_t	OddDivisorCorrect:1;	/* 31 */
-	} _fmt_preF;
+	} _fmt_f_preF;
 	/*
-	 * Register format in revisions F and G
+	 * Register format in family 0xf revisions F and G
 	 */
 	struct {
 		uint32_t	MemClkFreq:3;		/* 2:0 */
@@ -615,7 +657,7 @@ union mcreg_dramcfg_hi {
 		uint32_t	undocumented1:1;	/* 23 */
 		uint32_t	DcqBypassMax:4;		/* 27:24 */
 		uint32_t	FourActWindow:4;	/* 31:28 */
-	} _fmt_revFG;
+	} _fmt_f_revFG;
 };
 
 /*
@@ -634,6 +676,23 @@ union mcreg_scrubctl {
 	} _fmt_cmn;
 };
 
+union mcreg_dramscrublo {
+	uint32_t _val32;
+	struct {
+		uint32_t	ScrubReDirEn:1;		/* 0 */
+		uint32_t	reserved:5;		/* 5:1 */
+		uint32_t	ScrubAddrLo:26;		/* 31:6 */
+	} _fmt_cmn;
+};
+
+union mcreg_dramscrubhi {
+	uint32_t _val32;
+	struct {
+		uint32_t	ScrubAddrHi:8;		/* 7:0 */
+		uint32_t	reserved:24;		/* 31:8 */
+	} _fmt_cmn;
+};
+
 /*
  * Function 3 - Miscellaneous Control: On-Line Spare Control Register
  */
@@ -641,7 +700,7 @@ union mcreg_scrubctl {
 union mcreg_nbcfg {
 	uint32_t _val32;
 	/*
-	 * Register format in revisions E and earlier.
+	 * Register format in family 0xf revisions E and earlier.
 	 */
 	struct {
 		uint32_t	CpuEccErrEn:1;			/* 0 */
@@ -668,9 +727,9 @@ union mcreg_nbcfg {
 		uint32_t	reserved2:1;			/* 26 */
 		uint32_t	NbMcaToMstCpuEn:1;		/* 27 */
 		uint32_t	reserved3:4;			/* 31:28 */
-	} _fmt_preF;
+	} _fmt_f_preF;
 	/*
-	 * Register format in revisions F and G
+	 * Register format in family 0xf revisions F and G
 	 */
 	struct {
 		uint32_t	CpuEccErrEn:1;			/* 0 */
@@ -701,7 +760,7 @@ union mcreg_nbcfg {
 		uint32_t	SyncOnDramAdrParErrEn:1;	/* 30 */
 		uint32_t	reserved3:1;			/* 31 */
 
-	} _fmt_revFG;
+	} _fmt_f_revFG;
 };
 
 /*
@@ -711,7 +770,7 @@ union mcreg_nbcfg {
 union mcreg_sparectl {
 	uint32_t _val32;
 	/*
-	 * Register format in revisions F and G
+	 * Register format in family 0xf revisions F and G
 	 */
 	struct {
 		uint32_t	SwapEn:1;		/* 0 */
@@ -728,9 +787,126 @@ union mcreg_sparectl {
 		uint32_t	EccErrCntWrEn:1;	/* 23 */
 		uint32_t	EccErrCnt:4;		/* 27:24 */
 		uint32_t	reserved5:4;		/* 31:28 */
-	} _fmt_revFG;
+	} _fmt_f_revFG;
+	/*
+	 * Regiser format in family 0x10 revisions A and B
+	 */
+	struct {
+		uint32_t	SwapEn0:1;		/* 0 */
+		uint32_t	SwapDone0:1;		/* 1 */
+		uint32_t	SwapEn1:1;		/* 2 */
+		uint32_t	SwapDone1:1;		/* 3 */
+		uint32_t	BadDramCs0:3;		/* 6:4 */
+		uint32_t	reserved1:1;		/* 7 */
+		uint32_t	BadDramCs1:3;		/* 10:8 */
+		uint32_t	reserved2:1;		/* 11 */
+		uint32_t	SwapDoneInt:2;		/* 13:12 */
+		uint32_t	EccErrInt:2;		/* 15:14 */
+		uint32_t	EccErrCntDramCs:4;	/* 19:16 */
+		uint32_t	EccErrCntDramChan:2;	/* 21:20 */
+		uint32_t	reserved4:1;		/* 22 */
+		uint32_t	EccErrCntWrEn:1;	/* 23 */
+		uint32_t	EccErrCnt:4;		/* 27:24 */
+		uint32_t	LvtOffset:4;		/* 31:28 */
+	} _fmt_10_revAB;
 };
 
+/*
+ * Since the NB is on-chip some registers are also accessible as MSRs.
+ * We will represent such registers as bitfields as in the 32-bit PCI
+ * registers above, with the restriction that we must compile for 32-bit
+ * kernels and so 64-bit bitfields cannot be used.
+ */
+
+#define	_MCMSR_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field)
+
+#define	MCMSR_VAL(up) ((up)->_val64)
+
+#define	MCMSR_FIELD_CMN(up, field)	_MCMSR_FIELD(up, cmn, field)
+#define	MCMSR_FIELD_F_preF(up, field)	_MCMSR_FIELD(up, f_preF, field)
+#define	MCMSR_FIELD_F_revFG(up, field)	_MCMSR_FIELD(up, f_revFG, field)
+#define	MCMSR_FIELD_10_revAB(up, field)	_MCMSR_FIELD(up, 10_revAB, field)
+
+/*
+ * The NB MISC registers.  On family 0xf rev F this was introduced with
+ * a 12-bit ECC error count of all ECC errors observed on this memory-
+ * controller (regardless of channel or chip-select) and the ability to
+ * raise an interrupt or SMI on overflow.  In family 0x10 it has a similar
+ * purpose, but the register is is split into 4 misc registers
+ * MC4_MISC{0,1,2,3} accessible via both MSRs and PCI config space;
+ * they perform thresholding for dram, l3, HT errors.
+ */
+
+union mcmsr_nbmisc {
+	uint64_t _val64;
+	/*
+	 * MSR format in family 0xf revision F and later
+	 */
+	struct {
+		/*
+		 * Lower 32 bits
+		 */
+		struct {
+			uint32_t _reserved;			/* 31:0 */
+		} _mcimisc_lo;
+		/*
+		 * Upper 32 bits
+		 */
+		struct {
+			uint32_t _ErrCount:12;			/* 43:32 */
+			uint32_t _reserved1:4;			/* 47:44 */
+			uint32_t _Ovrflw:1;			/* 48 */
+			uint32_t _IntType:2;			/* 50:49 */
+			uint32_t _CntEn:1;			/* 51 */
+			uint32_t _LvtOff:4;			/* 55:52 */
+			uint32_t _reserved2:5;			/* 60:56 */
+			uint32_t _Locked:1;			/* 61 */
+			uint32_t _CntP:1;			/* 62 */
+			uint32_t _Valid:1;			/* 63 */
+		} _mcimisc_hi;
+	} _fmt_f_revFG;
+	/*
+	 * MSR format in family 0x10 revisions A and B
+	 */
+	struct {
+		/*
+		 * Lower 32 bits
+		 */
+		struct {
+			uint32_t _reserved:24;			/* 23:0 */
+			uint32_t _BlkPtr:8;			/* 31:24 */
+		} _mcimisc_lo;
+		/*
+		 * Upper 32 bits
+		 */
+		struct {
+			uint32_t _ErrCnt:12;			/* 43:32 */
+			uint32_t _reserved1:4;			/* 47:44 */
+			uint32_t _Ovrflw:1;			/* 48 */
+			uint32_t _IntType:2;			/* 50:49 */
+			uint32_t _CntEn:1;			/* 51 */
+			uint32_t _LvtOff:4;			/* 55:52 */
+			uint32_t _reserved2:5;			/* 60:56 */
+			uint32_t _Locked:1;			/* 61 */
+			uint32_t _CntP:1;			/* 62 */
+			uint32_t _Valid:1;			/* 63 */
+
+		} _mcimisc_hi;
+	} _fmt_10_revAB;
+};
+
+#define	mcmisc_BlkPtr	_mcimisc_lo._BlkPtr
+#define	mcmisc_ErrCount	_mcimisc_hi._ErrCount
+#define	mcmisc_Ovrflw	_mcimisc_hi._Ovrflw
+#define	mcmisc_IntType	_mcimisc_hi._IntType
+#define	mcmisc_CntEn	_mcimisc_hi._CntEn
+#define	mcmisc_LvtOff	_mcimisc_hi._LvtOff
+#define	mcmisc_Locked	_mcimisc_hi._Locked
+#define	mcmisc_CntP	_mcimisc_hi._CntP
+#define	mcmisc_Valid	_mcimisc_hi._Valid
+
+#endif /* _BIT_FIELDS_LTOH */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/usr/src/uts/intel/sys/mc_intel.h b/usr/src/uts/intel/sys/mc_intel.h
new file mode 100644
index 0000000000..1ade228526
--- /dev/null
+++ b/usr/src/uts/intel/sys/mc_intel.h
@@ -0,0 +1,186 @@
+/*
+ * CDDL HEADER START
+ *
+ * The contents of this file are subject to the terms of the
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
+ *
+ * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
+ * or http://www.opensolaris.org/os/licensing.
+ * See the License for the specific language governing permissions
+ * and limitations under the License.
+ *
+ * When distributing Covered Code, include this CDDL HEADER in each
+ * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
+ * If applicable, add the following below this CDDL HEADER, with the
+ * fields enclosed by brackets "[]" replaced with your own identifying
+ * information: Portions Copyright [yyyy] [name of copyright owner]
+ *
+ * CDDL HEADER END
+ */
+
+/*
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Use is subject to license terms.
+ */
+
+#ifndef _MC_INTEL_H
+#define	_MC_INTEL_H
+
+#pragma ident	"%Z%%M%	%I%	%E% SMI"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define	FM_EREPORT_CPU_INTEL	"intel"
+
+#define	MCINTEL_NVLIST_VERSTR	"mcintel-nvlist-version"
+#define	MCINTEL_NVLIST_VERS0	0
+
+#define	MCINTEL_NVLIST_VERS	MCINTEL_NVLIST_VERS0
+
+#define	MCINTEL_NVLIST_MC	"memory-channels"
+#define	MCINTEL_NVLIST_DIMMS	"memory-dimms"
+#define	MCINTEL_NVLIST_DIMMSZ	"memory-dimm-size"
+#define	MCINTEL_NVLIST_RANKS	"dimm-ranks"
+#define	MCINTEL_NVLIST_ROWS	"dimm-rows"
+#define	MCINTEL_NVLIST_COL	"dimm-column"
+#define	MCINTEL_NVLIST_BANK	"dimm-banks"
+#define	MCINTEL_NVLIST_WIDTH	"dimm-width"
+#define	MCINTEL_NVLIST_MID	"dimm-manufacture-id"
+#define	MCINTEL_NVLIST_MLOC	"dimm-manufacture-location"
+#define	MCINTEL_NVLIST_MWEEK	"dimm-manufacture-week"
+#define	MCINTEL_NVLIST_MYEAR	"dimm-manufacture-year"
+#define	MCINTEL_NVLIST_SERIALNO	"dimm-serial-number"
+#define	MCINTEL_NVLIST_PARTNO	"dimm-part-number"
+#define	MCINTEL_NVLIST_REV	"dimm-part-rev"
+
+#define	FM_EREPORT_PAYLOAD_NAME_FERR_GLOBAL		"ferr_global"
+#define	FM_EREPORT_PAYLOAD_NAME_NERR_GLOBAL		"nerr_global"
+#define	FM_EREPORT_PAYLOAD_NAME_FSB			"fsb"
+#define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_FSB		"ferr_fat_fsb"
+#define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FSB		"nerr_fat_fsb"
+#define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_FSB		"ferr_nf_fsb"
+#define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_FSB		"nerr_nf_fsb"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECFSB			"nrecfsb"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECFSB_ADDR		"nrecfsb_addr"
+#define	FM_EREPORT_PAYLOAD_NAME_RECFSB			"recfsb"
+#define	FM_EREPORT_PAYLOAD_NAME_PEX			"pex"
+#define	FM_EREPORT_PAYLOAD_NAME_PEX_FAT_FERR		"pex_fat_ferr"
+#define	FM_EREPORT_PAYLOAD_NAME_PEX_FAT_NERR		"pex_fat_nerr"
+#define	FM_EREPORT_PAYLOAD_NAME_PEX_NF_CORR_FERR	"pex_nf_corr_ferr"
+#define	FM_EREPORT_PAYLOAD_NAME_PEX_NF_CORR_NERR	"pex_nf_corr_nerr"
+#define	FM_EREPORT_PAYLOAD_NAME_UNCERRSEV		"uncerrsev"
+#define	FM_EREPORT_PAYLOAD_NAME_RPERRSTS		"rperrsts"
+#define	FM_EREPORT_PAYLOAD_NAME_RPERRSID		"rperrsid"
+#define	FM_EREPORT_PAYLOAD_NAME_UNCERRSTS		"uncerrsts"
+#define	FM_EREPORT_PAYLOAD_NAME_AERRCAPCTRL		"aerrcapctrl"
+#define	FM_EREPORT_PAYLOAD_NAME_CORERRSTS		"corerrsts"
+#define	FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS		"pexdevsts"
+#define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_INT		"ferr_fat_int"
+#define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_INT		"ferr_nf_int"
+#define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_INT		"nerr_fat_int"
+#define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_INT		"nerr_nf_int"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECINT			"nrecint"
+#define	FM_EREPORT_PAYLOAD_NAME_RECINT			"recint"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECSF			"nrecsf"
+#define	FM_EREPORT_PAYLOAD_NAME_RECSF			"recsf"
+#define	FM_EREPORT_PAYLOAD_NAME_RANK			"rank"
+#define	FM_EREPORT_PAYLOAD_NAME_BANK			"bank"
+#define	FM_EREPORT_PAYLOAD_NAME_CAS			"cas"
+#define	FM_EREPORT_PAYLOAD_NAME_RAS			"ras"
+#define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_FBD		"ferr_fat_fbd"
+#define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FBD		"nerr_fat_fbd"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECMEMA		"nrecmema"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECMEMB		"nrecmemb"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECFGLOG		"nrecfglog"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECFBDA		"nrecfbda"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECFBDB		"nrecfbdb"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECFBDC		"nrecfbdc"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECFBDD		"nrecfbdd"
+#define	FM_EREPORT_PAYLOAD_NAME_NRECFBDE		"nrecfbde"
+#define	FM_EREPORT_PAYLOAD_NAME_SPCPC			"spcpc"
+#define	FM_EREPORT_PAYLOAD_NAME_SPCPS			"spcps"
+#define	FM_EREPORT_PAYLOAD_NAME_UERRCNT			"uerrcnt"
+#define	FM_EREPORT_PAYLOAD_NAME_UERRCNT_LAST		"uerrcnt_last"
+#define	FM_EREPORT_PAYLOAD_NAME_BADRAMA			"badrama"
+#define	FM_EREPORT_PAYLOAD_NAME_BADRAMB			"badramb"
+#define	FM_EREPORT_PAYLOAD_NAME_BADCNT			"badcnt"
+#define	FM_EREPORT_PAYLOAD_NAME_MC			"mc"
+#define	FM_EREPORT_PAYLOAD_NAME_MCA			"mca"
+#define	FM_EREPORT_PAYLOAD_NAME_TOLM			"tolm"
+#define	FM_EREPORT_PAYLOAD_NAME_MIR			"mir"
+#define	FM_EREPORT_PAYLOAD_NAME_MTR			"mtr"
+#define	FM_EREPORT_PAYLOAD_NAME_DMIR			"dmir"
+#define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_FBD		"ferr_nf_fbd"
+#define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_FBD		"nerr_nf_fbd"
+#define	FM_EREPORT_PAYLOAD_NAME_RECMEMA			"recmema"
+#define	FM_EREPORT_PAYLOAD_NAME_RECMEMB			"recmemb"
+#define	FM_EREPORT_PAYLOAD_NAME_RECFGLOG		"recfglog"
+#define	FM_EREPORT_PAYLOAD_NAME_RECFBDA			"recfbda"
+#define	FM_EREPORT_PAYLOAD_NAME_RECFBDB			"recfbdb"
+#define	FM_EREPORT_PAYLOAD_NAME_RECFBDC			"recfbdc"
+#define	FM_EREPORT_PAYLOAD_NAME_RECFBDD			"recfbdd"
+#define	FM_EREPORT_PAYLOAD_NAME_RECFBDE			"recfbde"
+#define	FM_EREPORT_PAYLOAD_NAME_CERRCNT			"cerrcnt"
+#define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_LAST		"cerrcnt_last"
+#define	FM_EREPORT_PAYLOAD_NAME_PCISTS			"pcists"
+#define	FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS		"pexdevsts"
+#define	FM_EREPORT_PAYLOAD_NAME_ERROR_NO		"intel-error-list"
+
+#define	FM_EREPORT_PAYLOAD_NAME_ADDR			"addr"
+#define	FM_EREPORT_PAYLOAD_NAME_BANK_NUM		"bank-number"
+#define	FM_EREPORT_PAYLOAD_NAME_BANK_MISC		"bank-misc"
+#define	FM_EREPORT_PAYLOAD_NAME_BANK_STAT		"bank-status"
+#define	FM_EREPORT_PAYLOAD_NAME_BANK_OFFSET		"bank-offset"
+#define	FM_EREPORT_PAYLOAD_NAME_MC_TYPE			"mc-type"
+#define	FM_EREPORT_PAYLOAD_CPUID			"cpuid"
+
+#define	FM_EREPORT_PAYLOAD_BQR				"Bus-queue-request"
+#define	FM_EREPORT_PAYLOAD_BQET				"Bus-queue-error-type"
+#define	FM_EREPORT_PAYLOAD_FRC				"FRC-error"
+#define	FM_EREPORT_PAYLOAD_BERR				"BERR"
+#define	FM_EREPORT_PAYLOAD_INT_BINT			"Internal-BINT"
+#define	FM_EREPORT_PAYLOAD_EXT_BINT			"External-BINT"
+#define	FM_EREPORT_PAYLOAD_BUS_BINT			"Bus-BINT"
+#define	FM_EREPORT_PAYLOAD_TO_BINT			"Timeout-BINT"
+#define	FM_EREPORT_PAYLOAD_HARD				"Hard-error"
+#define	FM_EREPORT_PAYLOAD_IERR				"IERR"
+#define	FM_EREPORT_PAYLOAD_AERR				"AERR"
+#define	FM_EREPORT_PAYLOAD_UERR				"UERR"
+#define	FM_EREPORT_PAYLOAD_CECC				"CECC"
+#define	FM_EREPORT_PAYLOAD_UECC				"UECC"
+#define	FM_EREPORT_PAYLOAD_ECC_SYND			"ECC-syndrome"
+
+#define	FM_EREPORT_PAYLOAD_FSB_PARITY			"fsb-address-parity"
+#define	FM_EREPORT_PAYLOAD_RESP_HF			"response-hard-fail"
+#define	FM_EREPORT_PAYLOAD_RESP_PARITY			"response-parity"
+#define	FM_EREPORT_PAYLOAD_DATA_PARITY			"bus-data-parity"
+#define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
+#define	FM_EREPORT_PAYLOAD_PAD_SM			"pad-state-machine"
+#define	FM_EREPORT_PAYLOAD_PAD_SG			"pad-strobe-glitch"
+
+#define	FM_EREPORT_PAYLOAD_TAG				"tag-error"
+#define	FM_EREPORT_PAYLOAD_TAG_CLEAN			"clean"
+#define	FM_EREPORT_PAYLOAD_TAG_HIT			"hit"
+#define	FM_EREPORT_PAYLOAD_TAG_MISS			"miss"
+#define	FM_EREPORT_PAYLOAD_DATA				"data-error"
+#define	FM_EREPORT_PAYLOAD_DATA_SINGLE			"single-bit"
+#define	FM_EREPORT_PAYLOAD_DATA_DBL_CLEAN		"double-bit-clean"
+#define	FM_EREPORT_PAYLOAD_DATA_DBL_MOD			"double-bit-modified"
+#define	FM_EREPORT_PAYLOAD_L3				"l3-cache"
+#define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
+#define	FM_EREPORT_PAYLOAD_CACHE_NERRORS		"cache-error-count"
+
+#define	INTEL_NB_5000P	0x25d88086
+#define	INTEL_NB_5000V	0x25d48086
+#define	INTEL_NB_5000X	0x25c08086
+#define	INTEL_NB_5000Z	0x25d08086
+#define	INTEL_NB_7300	0x36008086
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MC_INTEL_H */
diff --git a/usr/src/uts/intel/sys/mca_amd.h b/usr/src/uts/intel/sys/mca_amd.h
index 5adbf02965..d583b71221 100644
--- a/usr/src/uts/intel/sys/mca_amd.h
+++ b/usr/src/uts/intel/sys/mca_amd.h
@@ -29,8 +29,10 @@
 
 #pragma ident	"%Z%%M%	%I%	%E% SMI"
 
+#include <sys/mca_x86.h>
+
 /*
- * Constants the Memory Check Architecture as implemented on AMD CPUs.
+ * Constants for the Machine Check Architecture as implemented on AMD CPUs.
  */
 
 #ifdef __cplusplus
@@ -83,9 +85,6 @@ extern "C" {
 #define	AMD_MCG_EN_BU			0x04
 #define	AMD_MCG_EN_LS			0x08
 #define	AMD_MCG_EN_NB			0x10
-#define	AMD_MCG_EN_ALL \
-	(AMD_MCG_EN_DC | AMD_MCG_EN_IC | AMD_MCG_EN_BU | AMD_MCG_EN_LS | \
-	AMD_MCG_EN_NB)
 
 /*
  * Data Cache (DC) bank error-detection enabling bits and CTL register
@@ -298,14 +297,18 @@ extern "C" {
 #define	AMD_NB_CFG_GENCRCERRBYTE0	0x00010000
 #define	AMD_NB_CFG_GENCRCERRBYTE1	0x00020000
 
-/* Generic bank status register bits */
-#define	AMD_BANK_STAT_VALID		0x8000000000000000ULL
-#define	AMD_BANK_STAT_OVER		0x4000000000000000ULL
-#define	AMD_BANK_STAT_UC		0x2000000000000000ULL
-#define	AMD_BANK_STAT_EN		0x1000000000000000ULL
-#define	AMD_BANK_STAT_MISCV		0x0800000000000000ULL
-#define	AMD_BANK_STAT_ADDRV		0x0400000000000000ULL
-#define	AMD_BANK_STAT_PCC		0x0200000000000000ULL
+/*
+ * The AMD extended error code is just one nibble of the upper 16 bits
+ * of the bank status (the resy being used for syndrome etc).  So we use
+ * AMD_EXT_ERRCODE to retrieve that extended error code, not the generic
+ * MCAX86_MSERRCODE.
+ */
+#define	_AMD_ERREXT_MASK		0x00000000000f0000ULL
+#define	_AMD_ERREXT_SHIFT		16
+#define	AMD_EXT_ERRCODE(stat) \
+	(((stat) & _AMD_ERREXT_MASK) >> _AMD_ERREXT_SHIFT)
+#define	AMD_EXT_MKERRCODE(errcode) \
+	(((errcode) << _AMD_ERREXT_SHIFT) & _AMD_ERREXT_MASK)
 
 #define	AMD_BANK_STAT_CECC		0x0000400000000000ULL
 #define	AMD_BANK_STAT_UECC		0x0000200000000000ULL
@@ -338,87 +341,26 @@ extern "C" {
 	((((uint64_t)(synd) << AMD_NB_STAT_CKSYND_SHIFT) & \
 	AMD_NB_STAT_CKSYND_MASK) | AMD_BANK_MKSYND(synd))
 
-#define	AMD_ERRCODE_MASK		0x000000000000ffffULL
 #define	AMD_ERREXT_MASK			0x00000000000f0000ULL
 #define	AMD_ERREXT_SHIFT		16
 
-#define	AMD_ERRCODE_TT_MASK		0x000c
-#define	AMD_ERRCODE_TT_SHIFT		2
-#define	AMD_ERRCODE_TT_INSTR		0x0
-#define	AMD_ERRCODE_TT_DATA		0x1
-#define	AMD_ERRCODE_TT_GEN		0x2
-
-#define	AMD_ERRCODE_LL_MASK		0x0003
-#define	AMD_ERRCODE_LL_L0		0x0
-#define	AMD_ERRCODE_LL_L1		0x1
-#define	AMD_ERRCODE_LL_L2		0x2
-#define	AMD_ERRCODE_LL_LG		0x3
-
-#define	AMD_ERRCODE_R4_MASK		0x00f0
-#define	AMD_ERRCODE_R4_SHIFT		4
-#define	AMD_ERRCODE_R4_GEN		0x0
-#define	AMD_ERRCODE_R4_RD		0x1
-#define	AMD_ERRCODE_R4_WR		0x2
-#define	AMD_ERRCODE_R4_DRD		0x3
-#define	AMD_ERRCODE_R4_DWR		0x4
-#define	AMD_ERRCODE_R4_IRD		0x5
-#define	AMD_ERRCODE_R4_PREFETCH		0x6
-#define	AMD_ERRCODE_R4_EVICT		0x7
-#define	AMD_ERRCODE_R4_SNOOP		0x8
-
-#define	AMD_ERRCODE_PP_MASK		0x0600
-#define	AMD_ERRCODE_PP_SHIFT		9
-#define	AMD_ERRCODE_PP_SRC		0x0
-#define	AMD_ERRCODE_PP_RSP		0x1
-#define	AMD_ERRCODE_PP_OBS		0x2
-#define	AMD_ERRCODE_PP_GEN		0x3
-
-#define	AMD_ERRCODE_T_MASK		0x0100
-#define	AMD_ERRCODE_T_SHIFT		8
-#define	AMD_ERRCODE_T_NONE		0x0
-#define	AMD_ERRCODE_T_TIMEOUT		0x1
-
-#define	AMD_ERRCODE_II_MASK		0x000c
-#define	AMD_ERRCODE_II_SHIFT		2
-#define	AMD_ERRCODE_II_MEM		0x0
-#define	AMD_ERRCODE_II_IO		0x2
-#define	AMD_ERRCODE_II_GEN		0x3
-
 #define	AMD_ERRCODE_TLB_BIT		4
 #define	AMD_ERRCODE_MEM_BIT		8
 #define	AMD_ERRCODE_BUS_BIT		11
 
 #define	AMD_ERRCODE_TLB_MASK		0xfff0
-#define	AMD_ERRCODE_TLB_VAL		0x0010
 #define	AMD_ERRCODE_MEM_MASK		0xff00
-#define	AMD_ERRCODE_MEM_VAL		0x0100
 #define	AMD_ERRCODE_BUS_MASK		0xf800
-#define	AMD_ERRCODE_BUS_VAL		0x0800
-
-#define	AMD_ERRCODE_MKTLB(tt, ll) \
-	(AMD_ERRCODE_TLB_VAL | \
-	(((tt) << AMD_ERRCODE_TT_SHIFT) & AMD_ERRCODE_TT_MASK) | \
-	((ll) & AMD_ERRCODE_LL_MASK))
-#define	AMD_ERRCODE_ISTLB(code) \
-	(((code) & AMD_ERRCODE_TLB_MASK) == AMD_ERRCODE_TLB_VAL)
-
-#define	AMD_ERRCODE_MKMEM(r4, tt, ll) \
-	(AMD_ERRCODE_MEM_VAL | \
-	(((r4) << AMD_ERRCODE_R4_SHIFT) & AMD_ERRCODE_R4_MASK) | \
-	(((tt) << AMD_ERRCODE_TT_SHIFT) & AMD_ERRCODE_TT_MASK) | \
-	((ll) & AMD_ERRCODE_LL_MASK))
-#define	AMD_ERRCODE_ISMEM(code) \
-	(((code) & AMD_ERRCODE_MEM_MASK) == AMD_ERRCODE_MEM_VAL)
+
+#define	AMD_ERRCODE_MKTLB(tt, ll) MCAX86_MKERRCODE_TLB(tt, ll)
+#define	AMD_ERRCODE_ISTLB(code) MCAX86_ERRCODE_ISTLB(code)
+
+#define	AMD_ERRCODE_MKMEM(r4, tt, ll) MCAX86_MKERRCODE_MEMHIER(r4, tt, ll)
+#define	AMD_ERRCODE_ISMEM(code) MCAX86_ERRCODE_ISMEMHIER(code)
 
 #define	AMD_ERRCODE_MKBUS(pp, t, r4, ii, ll) \
-	(AMD_ERRCODE_BUS_VAL | \
-	(((pp) << AMD_ERRCODE_PP_SHIFT) & AMD_ERRCODE_PP_MASK) | \
-	(((t) << AMD_ERRCODE_T_SHIFT) & AMD_ERRCODE_T_MASK) | \
-	(((r4) << AMD_ERRCODE_R4_SHIFT) & AMD_ERRCODE_R4_MASK) | \
-	(((ii) << AMD_ERRCODE_II_SHIFT) & AMD_ERRCODE_II_MASK) | \
-	((ll) & AMD_ERRCODE_LL_MASK))
-#define	AMD_ERRCODE_ISBUS(code) \
-	(((code) & AMD_ERRCODE_BUS_MASK) == AMD_ERRCODE_BUS_VAL)
+	MCAX86_MKERRCODE_BUS_INTERCONNECT(pp, t, r4, ii, ll)
+#define	AMD_ERRCODE_ISBUS(code) MCAX86_ERRCODE_ISBUS_INTERCONNECT(code)
 
 #define	AMD_NB_ADDRLO_MASK		0xfffffff8
 #define	AMD_NB_ADDRHI_MASK		0x000000ff
@@ -437,11 +379,12 @@ extern "C" {
 #define	AMD_NB_SCRUBCTL_RATE_MAX	0x16
 
 #define	AMD_NB_SCRUBADDR_LO_MASK	0xffffffc0
+#define	AMD_NB_SCRUBADDR_LO_SHIFT	6
 #define	AMD_NB_SCRUBADDR_LO_SCRUBREDIREN 0x1
 #define	AMD_NB_SCRUBADDR_HI_MASK	0x000000ff
 
 #define	AMD_NB_SCRUBADDR_MKLO(addr) \
-	((addr) & AMD_NB_SCRUBADDR_LO_MASK)
+	(((addr) & AMD_NB_SCRUBADDR_LO_MASK) >> AMD_NB_SCRUBADDR_LO_SHIFT)
 
 #define	AMD_NB_SCRUBADDR_MKHI(addr) \
 	(((addr) >> 32) & AMD_NB_SCRUBADDR_HI_MASK)
diff --git a/usr/src/uts/intel/sys/mca_x86.h b/usr/src/uts/intel/sys/mca_x86.h
index 78066bdc63..91b9a5bbfc 100644
--- a/usr/src/uts/intel/sys/mca_x86.h
+++ b/usr/src/uts/intel/sys/mca_x86.h
@@ -2,9 +2,8 @@
  * CDDL HEADER START
  *
  * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
  *
  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  * or http://www.opensolaris.org/os/licensing.
@@ -19,7 +18,7 @@
  *
  * CDDL HEADER END
  *
- * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -33,91 +32,350 @@
  * CPUs.
  */
 
+#include <sys/types.h>
+#include <sys/isa_defs.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /*
- * Intel has defined a number of MSRs as part of the IA32 architecture.  The
- * MCG registers are part of that set, as are the first four banks (0-3) as
- * implemented by the P4 processor.  Bank MSRs were laid out slightly
- * differently on the P6 family of processors, and thus have their own #defines
- * following the architecture-generic ones.
+ * Architectural MSRs from the IA-32 Software Developer's Manual - IA32_MSR_*
  */
 #define	IA32_MSR_MCG_CAP		0x179
 #define	IA32_MSR_MCG_STATUS		0x17a
 #define	IA32_MSR_MCG_CTL		0x17b
 
-#define	MCG_CAP_COUNT_MASK		0x000000ffULL
 #define	MCG_CAP_CTL_P			0x00000100ULL
 #define	MCG_CAP_EXT_P			0x00000200ULL
+#define	MCG_CAP_TES_P			0x00000800ULL
+
+#define	MCG_CAP_COUNT_MASK		0x000000ffULL
+#define	MCG_CAP_COUNT(cap) ((cap) & MCG_CAP_COUNT_MASK)
+
 #define	MCG_CAP_EXT_CNT_MASK		0x00ff0000ULL
 #define	MCG_CAP_EXT_CNT_SHIFT		16
+#define	MCG_CAP_EXT_CNT(cap) \
+	(((cap) & MCG_CAP_EXT_CNT_MASK) >> MCG_CAP_EXT_CNT_SHIFT)
 
 #define	MCG_STATUS_RIPV			0x01
 #define	MCG_STATUS_EIPV			0x02
 #define	MCG_STATUS_MCIP			0x04
 
-#define	IA32_MSR_MC0_CTL		0x400
-#define	IA32_MSR_MC0_STATUS		0x401
-#define	IA32_MSR_MC0_ADDR		0x402
-#define	IA32_MSR_MC0_MISC		0x403
+/*
+ * There are as many error detector "banks" as indicated by
+ * IA32_MSR_MCG_CAP.COUNT.  Each bank has a minimum of 3 associated
+ * registers (MCi_CTL, MCi_STATUS, and MCi_ADDR) and some banks
+ * may implement a fourth (MCi_MISC) which should only be read
+ * when MCi_STATUS.MISCV indicates that it exists and has valid data.
+ *
+ * The first bank features at MSR offsets 0x400 to 0x403, the next at
+ * 0x404 to 0x407, and so on.  Current processors implement up to 6
+ * banks (sixth one at 0x414 to 0x417).
+ *
+ * It is, sadly, not the case that the i'th set of 4 registers starting
+ * at 0x400 corresponds to MCi_{CTL,STATUS,ADDR,MISC} - for some Intel
+ * processors, for example, the order is 0/1/2/4/3.  Nonetheless, we can
+ * still iterate through the banks and read all telemetry - there'll just
+ * be some potential confusion as to which processor unit a bank is
+ * associated with.  Error reports should seek to disambiguate.
+ *
+ * IA32_MSR_MC(i, which) calculates the MSR address for th i'th bank
+ * of registers (not for MCi_*, as above) and one of CTL, STATUS, ADDR, MISC
+ */
+
+#define	_IA32_MSR_MC0_CTL		0x400ULL /* first/base reg */
+#define	_IA32_MSR_OFFSET_CTL		0x0	/* offset within a bank */
+#define	_IA32_MSR_OFFSET_STATUS		0x1	/* offset within a bank */
+#define	_IA32_MSR_OFFSET_ADDR		0x2	/* offset within a bank */
+#define	_IA32_MSR_OFFSET_MISC		0x3	/* offset within a bank */
+
+
+#define	IA32_MSR_MC(i, which) \
+	(_IA32_MSR_MC0_CTL + (i) * 4 + _IA32_MSR_OFFSET_##which)
+
+/*
+ * IA32_MSR_MCG_CAP.MCG_EXT_P indicates that a processor implements
+ * a set of extended machine-check registers starting at MSR 0x180;
+ * when that is set, IA32_MSR_MCG_CAP.MCG_EXT_CNT indicates how
+ * many of these extended registers (addresses 0x180, 0x181, ...)
+ * are present.  Which registers are present depends on whether support
+ * for 64-bit architecture is present.
+ */
 
-#define	IA32_MSR_MC1_CTL		0x404
-#define	IA32_MSR_MC1_STATUS		0x405
-#define	IA32_MSR_MC1_ADDR		0x406
-#define	IA32_MSR_MC1_MISC		0x407
+#define	_IA32_MCG_RAX			0x180ULL /* first/base extended reg */
 
-#define	IA32_MSR_MC2_CTL		0x408
-#define	IA32_MSR_MC2_STATUS		0x409
-#define	IA32_MSR_MC2_ADDR		0x40a
-#define	IA32_MSR_MC2_MISC		0x40b
+#define	IA32_MSR_EXT(i)	(_IA32_MCG_RAX + (i))
 
-#define	IA32_MSR_MC3_CTL		0x40c
-#define	IA32_MSR_MC3_STATUS		0x40d
-#define	IA32_MSR_MC3_ADDR		0x40e
-#define	IA32_MSR_MC3_MISC		0x40f
+#ifdef _BIT_FIELDS_LTOH
+typedef union mca_x86_mcistatus {
+	uint64_t _val64;
+	struct {
+		/*
+		 * Lower 32 bits of MCi_STATUS
+		 */
+		struct {
+			uint32_t _errcode:16;		/* <15:0> */
+			uint32_t _ms_errcode:16;	/* <31:16> */
+		} _mcis_lo;
+		/*
+		 * Upper 32 bits of MCi_STATUS
+		 */
+		union {
+			/*
+			 * If IA32_MCG_CAP.MCG_TES_P is set then <54:53>
+			 * and <56:55> are architectural.
+			 */
+			struct {
+				uint32_t _otherinfo:21;		/* <52:32> */
+				uint32_t _tbes:2;		/* <54:53> */
+				uint32_t _reserved:2;		/* <56:55> */
+				uint32_t _pcc:1;		/* <57> */
+				uint32_t _addrv:1;		/* <58> */
+				uint32_t _miscv:1;		/* <59> */
+				uint32_t _en:1;			/* <60> */
+				uint32_t _uc:1;			/* <61> */
+				uint32_t _over:1;		/* <62> */
+				uint32_t _val:1;		/* <63> */
+			} _mcis_hi_tes_p;
+			/*
+			 * If IA32_MCG_CAP.MCG_TES_P is clear then <56:53>
+			 * are model-specific.
+			 */
+			struct {
+				uint32_t _otherinfo:25;		/* <56:32> */
+				uint32_t _pcc:1;		/* <57> */
+				uint32_t _addrv:1;		/* <58> */
+				uint32_t _miscv:1;		/* <59> */
+				uint32_t _en:1;			/* <60> */
+				uint32_t _uc:1;			/* <61> */
+				uint32_t _over:1;		/* <62> */
+				uint32_t _val:1;		/* <63> */
+			} _mcis_hi_tes_np;
+		} _mcis_hi;
+	} _mcis_hilo;
+} mca_x86_mcistatus_t;
+
+#define	mcistatus_errcode	_mcis_hilo._mcis_lo._errcode
+#define	mcistatus_mserrcode	_mcis_hilo._mcis_lo._ms_errcode
+#define	mcistatus_pcc	_mcis_hilo._mcis_hi._mcis_hi_tes_np._pcc
+#define	mcistatus_addrv	_mcis_hilo._mcis_hi._mcis_hi_tes_np._addrv
+#define	mcistatus_miscv	_mcis_hilo._mcis_hi._mcis_hi_tes_np._miscv
+#define	mcistatus_en	_mcis_hilo._mcis_hi._mcis_hi_tes_np._en
+#define	mcistatus_uc	_mcis_hilo._mcis_hi._mcis_hi_tes_np._uc
+#define	mcistatus_over	_mcis_hilo._mcis_hi._mcis_hi_tes_np._over
+#define	mcistatus_val	_mcis_hilo._mcis_hi._mcis_hi_tes_np._val
+
+/*
+ * The consumer must check for TES_P before using these.
+ */
+#define	mcistatus_tbes	_mcis_hilo._mcis_hi._mcis_hi_tes_p._tbes
+#define	mcistatus_reserved \
+	_mcis_hilo._mcis_hi._mcis_hi_tes_p._reserved
+#define	mcistatus_otherinfo_tes_p \
+	_mcis_hilo._mcis_hi._mcis_hi_tes_p._otherinfo
+#define	mcistatus_otherinfo_tes_np \
+	_mcis_hilo._mcis_hi._mcis_hi_tes_np._otherinfo
+
+#endif /* _BIT_FIELDS_LTOH */
 
 #define	MSR_MC_STATUS_VAL		0x8000000000000000ULL
-#define	MSR_MC_STATUS_O			0x4000000000000000ULL
+#define	MSR_MC_STATUS_OVER		0x4000000000000000ULL
 #define	MSR_MC_STATUS_UC		0x2000000000000000ULL
 #define	MSR_MC_STATUS_EN		0x1000000000000000ULL
 #define	MSR_MC_STATUS_MISCV		0x0800000000000000ULL
 #define	MSR_MC_STATUS_ADDRV		0x0400000000000000ULL
 #define	MSR_MC_STATUS_PCC		0x0200000000000000ULL
-#define	MSR_MC_STATUS_OTHER_MASK	0x01ffffff00000000ULL
-#define	MSR_MC_STATUS_OTHER_SHIFT	32
+#define	MSR_MC_STATUS_RESERVED_MASK	0x0180000000000000ULL
+#define	MSR_MC_STATUS_TBES_MASK		0x0060000000000000ULL
+#define	MSR_MC_STATUS_TBES_SHIFT	53
 #define	MSR_MC_STATUS_MSERR_MASK	0x00000000ffff0000ULL
 #define	MSR_MC_STATUS_MSERR_SHIFT	16
 #define	MSR_MC_STATUS_MCAERR_MASK	0x000000000000ffffULL
 
 /*
- * P6 MCA bank MSRs.  Note that the ordering is 0, 1, 2, *4*, 3.  Yes, really.
+ * Macros to extract error code and model-specific error code.
+ */
+#define	MCAX86_ERRCODE(stat)		((stat) & MSR_MC_STATUS_MCAERR_MASK)
+#define	MCAX86_MSERRCODE(stat) \
+	(((stat) & MSR_MC_STATUS_MSERR_MASK) >> MSR_MC_STATUS_MSERR_SHIFT)
+
+/*
+ * Macro to extract threshold based error state (if MCG_CAP.TES_P)
  */
-#define	P6_MSR_MC0_CTL			0x400
-#define	P6_MSR_MC0_STATUS		0x401
-#define	P6_MSR_MC0_ADDR			0x402
-#define	P6_MSR_MC0_MISC			0x403
-
-#define	P6_MSR_MC1_CTL			0x404
-#define	P6_MSR_MC1_STATUS		0x405
-#define	P6_MSR_MC1_ADDR			0x406
-#define	P6_MSR_MC1_MISC			0x407
-
-#define	P6_MSR_MC2_CTL			0x408
-#define	P6_MSR_MC2_STATUS		0x409
-#define	P6_MSR_MC2_ADDR			0x40a
-#define	P6_MSR_MC2_MISC			0x40b
-
-#define	P6_MSR_MC4_CTL			0x40c
-#define	P6_MSR_MC4_STATUS		0x40d
-#define	P6_MSR_MC4_ADDR			0x40e
-#define	P6_MSR_MC4_MISC			0x40f
-
-#define	P6_MSR_MC3_CTL			0x410
-#define	P6_MSR_MC3_STATUS		0x411
-#define	P6_MSR_MC3_ADDR			0x412
-#define	P6_MSR_MC3_MISC			0x413
+#define	MCAX86_TBES_VALUE(stat) \
+	(((stat) & MSR_MC_STATUS_TBES_MASK) >> MSR_MC_STATUS_TBES_SHIFT)
+
+/*
+ * Bit definitions for the architectural error code.
+ */
+
+#define	MCAX86_ERRCODE_TT_MASK		0x000c
+#define	MCAX86_ERRCODE_TT_SHIFT		2
+#define	MCAX86_ERRCODE_TT_INSTR		0x0
+#define	MCAX86_ERRCODE_TT_DATA		0x1
+#define	MCAX86_ERRCODE_TT_GEN		0x2
+#define	MCAX86_ERRCODE_TT(code) \
+	(((code) & MCAX86_ERRCODE_TT_MASK) >> MCAX86_ERRCODE_TT_SHIFT)
+
+#define	MCAX86_ERRCODE_LL_MASK		0x0003
+#define	MCAX86_ERRCODE_LL_SHIFT		0
+#define	MCAX86_ERRCODE_LL_L0		0x0
+#define	MCAX86_ERRCODE_LL_L1		0x1
+#define	MCAX86_ERRCODE_LL_L2		0x2
+#define	MCAX86_ERRCODE_LL_LG		0x3
+#define	MCAX86_ERRCODE_LL(code) \
+	((code) & MCAX86_ERRCODE_LL_MASK)
+
+#define	MCAX86_ERRCODE_RRRR_MASK	0x00f0
+#define	MCAX86_ERRCODE_RRRR_SHIFT	4
+#define	MCAX86_ERRCODE_RRRR_ERR		0x0
+#define	MCAX86_ERRCODE_RRRR_RD		0x1
+#define	MCAX86_ERRCODE_RRRR_WR		0x2
+#define	MCAX86_ERRCODE_RRRR_DRD		0x3
+#define	MCAX86_ERRCODE_RRRR_DWR		0x4
+#define	MCAX86_ERRCODE_RRRR_IRD		0x5
+#define	MCAX86_ERRCODE_RRRR_PREFETCH	0x6
+#define	MCAX86_ERRCODE_RRRR_EVICT	0x7
+#define	MCAX86_ERRCODE_RRRR_SNOOP	0x8
+#define	MCAX86_ERRCODE_RRRR(code) \
+	(((code) & MCAX86_ERRCODE_RRRR_MASK) >> MCAX86_ERRCODE_RRRR_SHIFT)
+
+#define	MCAX86_ERRCODE_PP_MASK		0x0600
+#define	MCAX86_ERRCODE_PP_SHIFT		9
+#define	MCAX86_ERRCODE_PP_SRC		0x0
+#define	MCAX86_ERRCODE_PP_RES		0x1
+#define	MCAX86_ERRCODE_PP_OBS		0x2
+#define	MCAX86_ERRCODE_PP_GEN		0x3
+#define	MCAX86_ERRCODE_PP(code) \
+	(((code) & MCAX86_ERRCODE_PP_MASK) >> MCAX86_ERRCODE_PP_SHIFT)
+
+#define	MCAX86_ERRCODE_II_MASK		0x000c
+#define	MCAX86_ERRCODE_II_SHIFT		2
+#define	MCAX86_ERRCODE_II_MEM		0x0
+#define	MCAX86_ERRCODE_II_IO		0x2
+#define	MCAX86_ERRCODE_II_GEN		0x3
+#define	MCAX86_ERRCODE_II(code) \
+	(((code) & MCAX86_ERRCODE_II_MASK) >> MCAX86_ERRCODE_II_SHIFT)
+
+#define	MCAX86_ERRCODE_T_MASK		0x0100
+#define	MCAX86_ERRCODE_T_SHIFT		8
+#define	MCAX86_ERRCODE_T_NONE		0x0
+#define	MCAX86_ERRCODE_T_TIMEOUT	0x1
+#define	MCAX86_ERRCODE_T(code) \
+	(((code) & MCAX86_ERRCODE_T_MASK) >> MCAX86_ERRCODE_T_SHIFT)
+
+/*
+ * Simple error encoding.  MASKON are bits that must be set for a match
+ * at the same time bits indicated by MASKOFF are clear.
+ */
+#define	MCAX86_SIMPLE_UNCLASSIFIED_MASKON		0x0001
+#define	MCAX86_SIMPLE_UNCLASSIFIED_MASKOFF		0xfffe
+
+#define	MCAX86_SIMPLE_MC_CODE_PARITY_MASKON		0x0002
+#define	MCAX86_SIMPLE_MC_CODE_PARITY_MASKOFF		0xfffd
+
+#define	MCAX86_SIMPLE_EXTERNAL_MASKON			0x0003
+#define	MCAX86_SIMPLE_EXTERNAL_MASKOFF			0xfffc
+
+#define	MCAX86_SIMPLE_FRC_MASKON			0x0004
+#define	MCAX86_SIMPLE_FRC_MASKOFF			0xfffb
+
+#define	MCAX86_SIMPLE_INTERNAL_TIMER_MASKON		0x0400
+#define	MCAX86_SIMPLE_INTERNAL_TIMER_MASKOFF		0xfbff
+
+#define	MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON	0x0400
+#define	MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKOFF	0xf800
+#define	MCAX86_SIMPLE_INTERNAL_UNCLASS_VALUE_MASK	0x03ff
+
+/*
+ * Macros to make an internal unclassified error code, and to test if
+ * a given code is internal unclassified.
+ */
+#define	MCAX86_MKERRCODE_INTERNAL_UNCLASS(val) \
+	(MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON | \
+	((val) & MCAX86_SIMPLE_INTERNAL_UNCLASS_VALUE_MASK))
+#define	MCAX86_ERRCODE_ISSIMPLE_INTERNAL_UNCLASS(code) \
+	(((code) & MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON) == \
+	MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON && \
+	((code) & MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKOFF) == 0 && \
+	((code) & MCAX86_SIMPLE_INTERNAL_UNCLASS_VALUE_MASK) != 0)
+
+/*
+ * Is the given error code a simple error encoding?
+ */
+#define	MCAX86_ERRCODE_ISSIMPLE(code) \
+	((code) >= MCAX86_SIMPLE_UNCLASSIFIED_MASKON && \
+	(code) <= MCAX86_SIMPLE_FRC_MASKON || \
+	(code) == MCAX86_SIMPLE_INTERNAL_TIMER_MASKON || \
+	MCAX86_ERRCODE_ISSIMPLE_INTERNAL_UNCLASS(code))
+
+/*
+ * Compound error encoding.  We always ignore the 'F' bit (which indicates
+ * "correction report filtering") in classifying the error type.
+ */
+#define	MCAX86_COMPOUND_GENERIC_MEMHIER_MASKON		0x000c
+#define	MCAX86_COMPOUND_GENERIC_MEMHIER_MASKOFF		0xeff0
+
+#define	MCAX86_COMPOUND_TLB_MASKON			0x0010
+#define	MCAX86_COMPOUND_TLB_MASKOFF			0xefe0
+
+#define	MCAX86_COMPOUND_MEMHIER_MASKON			0x0100
+#define	MCAX86_COMPOUND_MEMHIER_MASKOFF			0xee00
+
+#define	MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON		0x0800
+#define	MCAX86_COMPOUND_BUS_INTERCONNECT_MASKOFF	0xe000
+
+/*
+ * Macros to make compound error codes and to test for each type.
+ */
+#define	MCAX86_MKERRCODE_GENERIC_MEMHIER(ll) \
+	(MCAX86_COMPOUND_GENERIC_MEMHIER_MASKON | \
+	((ll) & MCAX86_ERRCODE_LL_MASK))
+#define	MCAX86_ERRCODE_ISGENERIC_MEMHIER(code) \
+	(((code) & MCAX86_COMPOUND_GENERIC_MEMHIER_MASKON) == \
+	MCAX86_COMPOUND_GENERIC_MEMHIER_MASKON && \
+	((code) & MCAX86_COMPOUND_GENERIC_MEMHIER_MASKOFF) == 0)
+
+#define	MCAX86_MKERRCODE_TLB(tt, ll) \
+	(MCAX86_COMPOUND_TLB_MASKON | \
+	((tt) << MCAX86_ERRCODE_TT_SHIFT & MCAX86_ERRCODE_TT_MASK) | \
+	((ll) & MCAX86_ERRCODE_LL_MASK))
+#define	MCAX86_ERRCODE_ISTLB(code) \
+	(((code) & MCAX86_COMPOUND_TLB_MASKON) == \
+	MCAX86_COMPOUND_TLB_MASKON && \
+	((code) & MCAX86_COMPOUND_TLB_MASKOFF) == 0)
+
+#define	MCAX86_MKERRCODE_MEMHIER(rrrr, tt, ll) \
+	(MCAX86_COMPOUND_MEMHIER_MASKON | \
+	((rrrr) << MCAX86_ERRCODE_RRRR_SHIFT & MCAX86_ERRCODE_RRRR_MASK) | \
+	((tt) << MCAX86_ERRCODE_TT_SHIFT & MCAX86_ERRCODE_TT_MASK) | \
+	((ll) & MCAX86_ERRCODE_LL_MASK))
+#define	MCAX86_ERRCODE_ISMEMHIER(code) \
+	(((code) & MCAX86_COMPOUND_MEMHIER_MASKON) == \
+	MCAX86_COMPOUND_MEMHIER_MASKON && \
+	((code) & MCAX86_COMPOUND_MEMHIER_MASKOFF) == 0)
+
+#define	MCAX86_MKERRCODE_BUS_INTERCONNECT(pp, t, rrrr, ii, ll) \
+	(MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON | \
+	((pp) << MCAX86_ERRCODE_PP_SHIFT & MCAX86_ERRCODE_PP_MASK) | \
+	((t) << MCAX86_ERRCODE_T_SHIFT & MCAX86_ERRCODE_T_MASK) | \
+	((rrrr) << MCAX86_ERRCODE_RRRR_SHIFT & MCAX86_ERRCODE_RRRR_MASK) | \
+	((ii) << MCAX86_ERRCODE_II_SHIFT & MCAX86_ERRCODE_II_MASK) | \
+	((ll) & MCAX86_ERRCODE_LL_MASK))
+#define	MCAX86_ERRCODE_ISBUS_INTERCONNECT(code) \
+	(((code) & MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON) == \
+	MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON && \
+	((code) & MCAX86_COMPOUND_BUS_INTERCONNECT_MASKOFF) == 0)
+
+#define	MCAX86_ERRCODE_ISCOMPOUND(code) \
+	(MCAX86_ERRCODE_ISGENERIC_MEMHIER(code) || \
+	MCAX86_ERRCODE_ISTLB(code) || \
+	MCAX86_ERRCODE_ISMEMHIER(code) \
+	MCAX86_ERRCODE_ISBUS_INTERCONNECT(code))
+
+#define	MCAX86_ERRCODE_UNKNOWN(code) \
+	(!MCAX86_ERRCODE_ISSIMPLE(code) && !MCAX86_ERRCODE_ISCOMPOUND(code))
 
 #ifdef __cplusplus
 }
diff --git a/usr/src/uts/intel/sys/memtest.h b/usr/src/uts/intel/sys/memtest.h
deleted file mode 100644
index 8e9d4fc8ef..0000000000
--- a/usr/src/uts/intel/sys/memtest.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- */
-
-#ifndef _MEMTEST_H
-#define	_MEMTEST_H
-
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-/*
- * Interfaces for the memory error injection driver (memtest).  This driver is
- * intended for use only by mtst.
- */
-
-#include <sys/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define	MEMTEST_DEVICE		"/devices/pseudo/memtest@0:memtest"
-
-#define	MEMTEST_VERSION		1
-
-#define	MEMTESTIOC		('M' << 8)
-#define	MEMTESTIOC_INQUIRE	(MEMTESTIOC | 0)
-#define	MEMTESTIOC_CONFIG	(MEMTESTIOC | 1)
-#define	MEMTESTIOC_INJECT	(MEMTESTIOC | 2)
-#define	MEMTESTIOC_MEMREQ	(MEMTESTIOC | 3)
-#define	MEMTESTIOC_MEMREL	(MEMTESTIOC | 4)
-
-#define	MEMTEST_F_DEBUG		0x1
-
-typedef struct memtest_inq {
-	uint_t minq_version;		/* [out] driver version */
-} memtest_inq_t;
-
-/*
- * Used by the userland injector to request a memory region from the driver.
- * This region (or a portion thereof) will be used for the error.  The caller
- * is expected to fill in the restrictions, if any, that are to be applied to
- * the region.  If the driver cannot allocate a region that meets the supplied
- * restrictions, the ioctl will fail.  Upon success, all members will be filled
- * in with values that reflect the allocated area.
- */
-
-#define	MEMTEST_MEMREQ_MAXNUM	5	/* maximum number of open allocations */
-#define	MEMTEST_MEMREQ_MAXSIZE	8192	/* maximum size of each allocation */
-
-#define	MEMTEST_MEMREQ_UNSPEC	((uint64_t)-1)
-
-typedef struct memtest_memreq {
-	int mreq_cpuid;			/* cpu restriction (opt, -1 if unset) */
-	uint32_t mreq_size;		/* size of allocation */
-	uint64_t mreq_vaddr;		/* [out] VA of allocation */
-	uint64_t mreq_paddr;		/* [out] PA of allocation */
-} memtest_memreq_t;
-
-/*
- * Arrays of statements are passed to the memtest driver for error injection.
- */
-#define	MEMTEST_INJECT_MAXNUM	20	/* Max # of stmts per INJECT ioctl */
-
-#define	MEMTEST_INJ_STMT_MSR	0x1	/* an MSR to be written */
-#define	MEMTEST_INJ_STMT_PCICFG	0x2	/* address in PCI config space */
-#define	MEMTEST_INJ_STMT_INT	0x3	/* a specific interrupt to be raised */
-#define	MEMTEST_INJ_STMT_POLL	0x4	/* tell CPU module to poll for CEs */
-
-/* Must be kept in sync with mtst_inj_statement in mtst_cpumod_api.h */
-typedef struct memtest_inj_stmt {
-	int mis_cpuid;			/* target CPU for statement */
-	uint_t mis_type;		/* MEMTEST_INJ_STMT_* */
-	union {
-		struct {		/* MEMTEST_INJ_STMT_MSR */
-			uint32_t _mis_msrnum;	/* MSR number */
-			uint32_t _mis_pad;	/* reserved */
-			uint64_t _mis_msrval;	/* value for MSR */
-		} _mis_msr;
-		struct {		/* MEMTEST_INJ_STMT_PCICFG */
-			uint32_t _mis_pciaddr;	/* address in config space */
-			uint32_t _mis_pcival;	/* value for PCI config reg */
-		} _mis_pci;
-		uint8_t _mis_int;	/* MEMTEST_INJ_STMT_INT; int num */
-	} _mis_data;
-} memtest_inj_stmt_t;
-
-#define	mis_msrnum	_mis_data._mis_msr._mis_msrnum
-#define	mis_msrval	_mis_data._mis_msr._mis_msrval
-#define	mis_pciaddr	_mis_data._mis_pci._mis_pciaddr
-#define	mis_pcival	_mis_data._mis_pci._mis_pcival
-#define	mis_int		_mis_data._mis_int
-
-typedef struct memtest_inject {
-	int mi_nstmts;
-	uint32_t mi_pad;
-	memtest_inj_stmt_t mi_stmts[1];
-} memtest_inject_t;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _MEMTEST_H */
diff --git a/usr/src/uts/intel/sys/pcb.h b/usr/src/uts/intel/sys/pcb.h
index 63325e4cc2..ebc3b4e222 100644
--- a/usr/src/uts/intel/sys/pcb.h
+++ b/usr/src/uts/intel/sys/pcb.h
@@ -69,6 +69,7 @@ typedef struct pcb {
 #define	CPC_OVERFLOW	0x40	/* performance counters overflowed */
 #define	REQUEST_STEP	0x100	/* request pending to single-step this lwp */
 #define	REQUEST_NOSTEP	0x200	/* request pending to disable single-step */
+#define	ASYNC_HWERR	0x400	/* hardware error has corrupted context  */
 
 /* fpu_flags */
 #define	FPU_EN		0x1	/* flag signifying fpu in use */
diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h
index 90cec07b3a..ff785bca1f 100644
--- a/usr/src/uts/intel/sys/x86_archext.h
+++ b/usr/src/uts/intel/sys/x86_archext.h
@@ -412,8 +412,8 @@ extern "C" {
 #define	X86_CHIPREV_UNKNOWN	0x0
 
 /*
- * Definitions for AMD Family 0xf and AMD Family 0x10. Minor revisions C0 and
- * CG are sufficiently different that we will distinguish them; in all other
+ * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
+ * sufficiently different that we will distinguish them; in all other
  * case we will identify the major revision.
  */
 #define	X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
@@ -423,8 +423,14 @@ extern "C" {
 #define	X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
 #define	X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
 #define	X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
-#define	X86_CHIPREV_AMD_10_REV_B \
+
+/*
+ * Definitions for AMD Family 0x10.  Rev A was Engineering Samples only.
+ */
+#define	X86_CHIPREV_AMD_10_REV_A \
 	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
+#define	X86_CHIPREV_AMD_10_REV_B \
+	_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
 
 /*
  * Various socket/package types, extended as the need to distinguish