OS-6500 Want modern Intel IMC driver

OS-6629 x86 PCI enumeration should not rely on bios max bus
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Rob Johnston <rob.johnston@joyent.com>
Approved by: Jerry Jelinek <jerry.jelinek@joyent.com>

3 files changed, 86 insertions, 4 deletions

diff --git a/usr/src/uts/intel/sys/cpu_module.h b/usr/src/uts/intel/sys/cpu_module.h
index c227acacd2..ad5308d28a 100644
--- a/usr/src/uts/intel/sys/cpu_module.h
+++ b/usr/src/uts/intel/sys/cpu_module.h
@@ -22,7 +22,7 @@
 /*
  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
- * Copyright (c) 2018, Joyent, Inc.
+ * Copyright 2019 Joyent, Inc.
  */
 
 #ifndef _SYS_CPU_MODULE_H
@@ -67,7 +67,8 @@ typedef enum cmi_errno {
 	CMIERR_MC_RSRCNOTPRESENT,	/* Resource not present in system */
 	CMIERR_MC_ADDRBITS,		/* Too few valid addr bits */
 	CMIERR_MC_INVALUNUM,		/* Invalid input unum */
-	CMIERR_MC_PARTIALUNUMTOPA	/* unum to pa reflected physaddr */
+	CMIERR_MC_PARTIALUNUMTOPA,	/* unum to pa reflected physaddr */
+	CMIERR_MC_NOTDIMMADDR		/* Address not backed by DRAM */
 } cmi_errno_t;
 
 /*
diff --git a/usr/src/uts/intel/sys/mc.h b/usr/src/uts/intel/sys/mc.h
index 27ef52684d..d4815b515f 100644
--- a/usr/src/uts/intel/sys/mc.h
+++ b/usr/src/uts/intel/sys/mc.h
@@ -21,12 +21,13 @@
  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
+/*
+ * Copyright 2019 Joyent, Inc.
+ */
 
 #ifndef _SYS_MC_H
 #define	_SYS_MC_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * Public interfaces exposed by the memory controller driver
  */
@@ -63,6 +64,9 @@ typedef struct mc_unum {
 #define	MC_IOC_SNAPSHOT_INFO	(MC_IOC | 1)
 #define	MC_IOC_SNAPSHOT		(MC_IOC | 2)
 #define	MC_IOC_ONLINESPARE_EN	(MC_IOC | 4)
+#define	MC_IOC_DECODE_PA	(MC_IOC | 5)
+#define	MC_IOC_DECODE_SNAPSHOT_INFO	(MC_IOC | 6)
+#define	MC_IOC_DECODE_SNAPSHOT	(MC_IOC | 7)
 
 /*
  * Prior to requesting a copy of the snapshot, consumers are advised to request
@@ -81,6 +85,25 @@ typedef struct mc_snapshot_info {
 	uint_t mcs_gen;		/* snapshot generation number */
 } mc_snapshot_info_t;
 
+/*
+ * Data used to simulate encoding or decoding of a physical / DIMM address.
+ */
+typedef struct mc_encode_ioc {
+	uint64_t	mcei_pa;
+	uint64_t	mcei_errdata;
+	uint32_t	mcei_err;
+	uint32_t	mcei_board;
+	uint32_t	mcei_chip;
+	uint32_t	mcei_mc;
+	uint32_t	mcei_chan;
+	uint32_t	mcei_dimm;
+	uint64_t	mcei_rank_addr;
+	uint32_t	mcei_rank;
+	uint32_t	mcei_row;
+	uint32_t	mcei_column;
+	uint32_t	mcei_pad;
+} mc_encode_ioc_t;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/usr/src/uts/intel/sys/mc_intel.h b/usr/src/uts/intel/sys/mc_intel.h
index f0c83b1d8b..4c43d3d695 100644
--- a/usr/src/uts/intel/sys/mc_intel.h
+++ b/usr/src/uts/intel/sys/mc_intel.h
@@ -22,6 +22,7 @@
 /*
  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
+ * Copyright 2019 Joyent, Inc.
  */
 
 #ifndef _MC_INTEL_H
@@ -35,6 +36,7 @@ extern "C" {
 
 #define	MCINTEL_NVLIST_VERSTR	"mcintel-nvlist-version"
 #define	MCINTEL_NVLIST_VERS0	0
+#define	MCINTEL_NVLIST_VERS1	1
 
 #define	MCINTEL_NVLIST_VERS	MCINTEL_NVLIST_VERS0
 
@@ -60,6 +62,62 @@ extern "C" {
 #define	MCINTEL_NVLIST_PARTNO	"dimm-part-number"
 #define	MCINTEL_NVLIST_REV	"dimm-part-rev"
 
+/*
+ * Version 1 payload. Whereas the version 0 payload uses a flat name space, we
+ * instead opt to use a hierarchical name space. This means that we can know how
+ * many devices there are at any level, as each level has this. Effectively,
+ * this means that we have an nvlist structure, for a socket that looks like:
+ *
+ * socket
+ *	string	version
+ *	uint8_t num-memory-controllers
+ *	nvlist array memory-controller[]
+ *		uint8_t num-channels
+ *		boolean ecc
+ *		string page policy
+ *		string lockstep || independent
+ *		nvlist array channel[]
+ *			uint8_t dpc
+ *			nvlist array dimm[]
+ *				boolean_t present;
+ *				uint32_t ncolumns
+ *				uint32_t nrows
+ *				uint64_t density (in bytes)
+ *				uint32_t width
+ *				uint32_t ranks
+ *				uint32_t banks
+ *				boolean_t array ranks_disabled
+ *				boolean_t hdrl-enabled
+ *				boolean_t hdrl-parity
+ *				uint32_t 3dnumranks
+ */
+
+#define	MCINTEL_NVLIST_V1_NMC		"num-memory-controllers"
+#define	MCINTEL_NVLIST_V1_MCS		"memory-controllers"
+#define	MCINTEL_NVLIST_V1_MC_NCHAN	"num-memory-channels"
+#define	MCINTEL_NVLIST_V1_MC_CHANNELS	"memory-controller-channels"
+#define	MCINTEL_NVLIST_V1_MC_ECC	"memory-controller-ecc"
+#define	MCINTEL_NVLIST_V1_MC_POLICY	"memory-controller-page-policy"
+#define	MCINTEL_NVLIST_V1_MC_POLICY_OPEN	"open-page"
+#define	MCINTEL_NVLIST_V1_MC_POLICY_CLOSED	"closed-page"
+#define	MCINTEL_NVLIST_V1_MC_CHAN_MODE	"memory-controller-channel-mode"
+#define	MCINTEL_NVLIST_V1_MC_CHAN_MODE_LOCK	"lockstep"
+#define	MCINTEL_NVLIST_V1_MC_CHAN_MODE_INDEP	"independent"
+#define	MCINTEL_NVLIST_V1_CHAN_NDPC	"memory-channel-dimms-per-channel"
+#define	MCINTEL_NVLIST_V1_CHAN_DIMMS	"memory-channel-dimms"
+#define	MCINTEL_NVLIST_V1_DIMM_PRESENT	"dimm-present"
+#define	MCINTEL_NVLIST_V1_DIMM_SIZE	"dimm-size"
+#define	MCINTEL_NVLIST_V1_DIMM_NCOLS	"dimm-num-columns"
+#define	MCINTEL_NVLIST_V1_DIMM_NROWS	"dimm-num-rows"
+#define	MCINTEL_NVLIST_V1_DIMM_DENSITY	"dimm-density"
+#define	MCINTEL_NVLIST_V1_DIMM_WIDTH	"dimm-width"
+#define	MCINTEL_NVLIST_V1_DIMM_RANKS	"dimm-ranks"
+#define	MCINTEL_NVLIST_V1_DIMM_BANKS	"dimm-banks"
+#define	MCINTEL_NVLIST_V1_DIMM_RDIS	"dimm-ranks-disabled"
+#define	MCINTEL_NVLIST_V1_DIMM_HDRL	"dimm-hdrl-enabled"
+#define	MCINTEL_NVLIST_V1_DIMM_HDRLP	"dimm-hdrl-parity-enabled"
+#define	MCINTEL_NVLIST_V1_DIMM_3DRANK	"dimm-3dranks"
+
 #define	FM_EREPORT_PAYLOAD_NAME_FERR_GLOBAL		"ferr_global"
 #define	FM_EREPORT_PAYLOAD_NAME_NERR_GLOBAL		"nerr_global"
 #define	FM_EREPORT_PAYLOAD_NAME_FSB			"fsb"