diff options
| author | Jerry Jelinek <jerry.jelinek@joyent.com> | 2020-04-09 11:32:39 +0000 |
|---|---|---|
| committer | Jerry Jelinek <jerry.jelinek@joyent.com> | 2020-04-09 11:32:39 +0000 |
| commit | bddd9bf04a29664ca9425e80b9404c61bbc4283e (patch) | |
| tree | 46d28e233d11382437b7354e4d9f97bdc1c80aab /usr/src/uts/intel/sys | |
| parent | 6b564a7014af2d4d9f000ed39a4fed77fd5245e0 (diff) | |
| parent | 72a6dc127431d372b6b6136087c736300544f8b7 (diff) | |
| download | illumos-joyent-bddd9bf04a29664ca9425e80b9404c61bbc4283e.tar.gz | |
[illumos-gate merge]
commit 72a6dc127431d372b6b6136087c736300544f8b7
7637 restorecontext(ucontext_t *ucp) leaves all maskable signals blocked in curthread->t_hold
commit a47ab03e261661b7326ab0b642649034886be632
12467 Add support for AMD PPIN
12468 Remove generic_cpu -Wno-parentheses gag
commit 6a0b121754dbd27d5d72dcddcb6465aab4092ba1
11909 THREAD_KPRI_RELEASE does nothing of the sort
Conflicts:
usr/src/uts/common/sys/ts.h
usr/src/uts/common/sys/ia.h
usr/src/uts/common/sys/fss.h
usr/src/uts/common/os/pid.c
Diffstat (limited to 'usr/src/uts/intel/sys')
| -rw-r--r-- | usr/src/uts/intel/sys/x86_archext.h | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h index d0efa8c384..0c20330297 100644 --- a/usr/src/uts/intel/sys/x86_archext.h +++ b/usr/src/uts/intel/sys/x86_archext.h @@ -209,6 +209,7 @@ extern "C" { #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */ #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */ #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */ +#define CPUID_AMD_EBX_PPIN 0x000800000 /* AMD: PPIN Support */ #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */ #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */ #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ @@ -455,13 +456,21 @@ extern "C" { #define MSR_PRP4_LBSTK_TO_15 0x6cf /* - * General Xeon based MSRs + * PPIN definitions for Intel and AMD. Unfortunately, Intel and AMD use + * different MSRS for this and different MSRS to control whether or not it + * should be readable. */ -#define MSR_PPIN_CTL 0x04e -#define MSR_PPIN 0x04f +#define MSR_PPIN_CTL_INTC 0x04e +#define MSR_PPIN_INTC 0x04f #define MSR_PLATFORM_INFO 0x0ce - #define MSR_PLATFORM_INFO_PPIN (1 << 23) + +#define MSR_PPIN_CTL_AMD 0xC00102F0 +#define MSR_PPIN_AMD 0xC00102F1 + +/* + * These values are currently the same between Intel and AMD. + */ #define MSR_PPIN_CTL_MASK 0x03 #define MSR_PPIN_CTL_LOCKED 0x01 #define MSR_PPIN_CTL_ENABLED 0x02 @@ -732,6 +741,7 @@ extern "C" { #define X86FSET_PKG_THERMAL 96 #define X86FSET_TSX_CTRL 97 #define X86FSET_TAA_NO 98 +#define X86FSET_PPIN 99 /* * Intel Deep C-State invariant TSC in leaf 0x80000007. @@ -1109,7 +1119,7 @@ extern "C" { #if defined(_KERNEL) || defined(_KMEMUSER) -#define NUM_X86_FEATURES 99 +#define NUM_X86_FEATURES 100 extern uchar_t x86_featureset[]; extern void free_x86_featureset(void *featureset); |