PSARC 2008/527 FMA for Intel integrated memory controller and Nehalem CPUs

6706543 FMA for Intel Nehalem
6726376 generic machine check retires wrong virtual cpu
6695950 dimm fmri string contains garbage characters in x4450

4 files changed, 132 insertions, 14 deletions

diff --git a/usr/src/uts/intel/sys/archsystm.h b/usr/src/uts/intel/sys/archsystm.h
index 3caa017acd..9ce5b4031a 100644
--- a/usr/src/uts/intel/sys/archsystm.h
+++ b/usr/src/uts/intel/sys/archsystm.h
@@ -19,15 +19,13 @@
  * CDDL HEADER END
  */
 /*
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef _SYS_ARCHSYSTM_H
 #define	_SYS_ARCHSYSTM_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * A selection of ISA-dependent interfaces
  */
@@ -71,6 +69,7 @@ extern int interrupts_enabled(void);
 extern void int3(void);
 extern void int18(void);
 extern void int20(void);
+extern void int_cmci(void);
 
 #if defined(__amd64)
 extern void sys_syscall();
diff --git a/usr/src/uts/intel/sys/fm/cpu/GMCA.h b/usr/src/uts/intel/sys/fm/cpu/GMCA.h
index c677efad87..0e5a5cf82d 100644
--- a/usr/src/uts/intel/sys/fm/cpu/GMCA.h
+++ b/usr/src/uts/intel/sys/fm/cpu/GMCA.h
@@ -20,15 +20,13 @@
  */
 
 /*
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef	_SYS_FM_CPU_GMCA_H
 #define	_SYS_FM_CPU_GMCA_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -58,6 +56,7 @@ extern "C" {
 #define	FM_EREPORT_CPU_GENERIC_MC_CODE_PARITY	"microcode_rom_parity"
 #define	FM_EREPORT_CPU_GENERIC_EXTERNAL		"external"
 #define	FM_EREPORT_CPU_GENERIC_FRC		"frc"
+#define	FM_EREPORT_CPU_GENERIC_INTERNAL_PARITY	"internal_parity"
 #define	FM_EREPORT_CPU_GENERIC_INTERNAL_TIMER	"internal_timer"
 #define	FM_EREPORT_CPU_GENERIC_INTERNAL_UNCLASS	"internal_unclassified"
 
@@ -77,6 +76,8 @@ extern "C" {
  *	5 - II interpretation
  *	6 - T interpretation
  *	7 - "_uc" if this is a compound error with MCi_STATUS.UC set, else ""
+ *	8 - CCCC interpretation
+ *	9 - MMM interpretation
  *
  * They can be selected in the format string using the %n$s specifier form.
  *
@@ -95,6 +96,7 @@ extern "C" {
 #define	FM_EREPORT_CPU_GENERIC_TLB		"%2$s" "%1$s" "tlb" "%7$s"
 #define	FM_EREPORT_CPU_GENERIC_MEMHIER		"%2$s" "%1$s" "cache" "%7$s"
 #define	FM_EREPORT_CPU_GENERIC_BUS_INTERCONNECT	"bus_interconnect" "%5$s" "%7$s"
+#define	FM_EREPORT_CPU_GENERIC_MEMORY_CONTROLLER "mc"
 
 /*
  * The "interpretation" expansions for the above ereport leaf subclasses.
@@ -130,6 +132,13 @@ extern "C" {
 #define	FM_EREPORT_CPU_GENERIC_T_NOTIMEOUT	""
 #define	FM_EREPORT_CPU_GENERIC_T_TIMEOUT	""
 
+#define	FM_EREPORT_CPU_GENERIC_CCCC		""
+
+#define	FM_EREPORT_CPU_GENERIC_MMM_ERR		""
+#define	FM_EREPORT_CPU_GENERIC_MMM_RD		""
+#define	FM_EREPORT_CPU_GENERIC_MMM_WR		""
+#define	FM_EREPORT_CPU_GENERIC_MMM_ADRCMD	""
+
 /*
  * Ereport payload member names together with bitmask values to select
  * their inclusion in ereports.
diff --git a/usr/src/uts/intel/sys/mc_intel.h b/usr/src/uts/intel/sys/mc_intel.h
index c7f17a03c1..1fae78927c 100644
--- a/usr/src/uts/intel/sys/mc_intel.h
+++ b/usr/src/uts/intel/sys/mc_intel.h
@@ -27,8 +27,6 @@
 #ifndef _MC_INTEL_H
 #define	_MC_INTEL_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -40,9 +38,12 @@ extern "C" {
 
 #define	MCINTEL_NVLIST_VERS	MCINTEL_NVLIST_VERS0
 
+#define	MCINTEL_NVLIST_MEM	"memory-controller"
+#define	MCINTEL_NVLIST_NMEM	"memory-controllers"
 #define	MCINTEL_NVLIST_MC	"memory-channels"
 #define	MCINTEL_NVLIST_DIMMS	"memory-dimms"
 #define	MCINTEL_NVLIST_DIMMSZ	"memory-dimm-size"
+#define	MCINTEL_NVLIST_NRANKS	"dimm-max-ranks"
 #define	MCINTEL_NVLIST_RANKS	"dimm-ranks"
 #define	MCINTEL_NVLIST_ROWS	"dimm-rows"
 #define	MCINTEL_NVLIST_COL	"dimm-column"
@@ -190,6 +191,10 @@ extern "C" {
 #define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
 #define	FM_EREPORT_PAYLOAD_CACHE_NERRORS		"cache-error-count"
 
+#define	FM_EREPORT_PAYLOAD_NAME_RESOURCE		"resource"
+#define	FM_EREPORT_PAYLOAD_MEM_ECC_COUNTER_THIS	"mem_cor_ecc_counter"
+#define	FM_EREPORT_PAYLOAD_MEM_ECC_COUNTER_LAST	"mem_cor_ecc_counter_last"
+
 #define	INTEL_NB_5000P	0x25d88086
 #define	INTEL_NB_5000V	0x25d48086
 #define	INTEL_NB_5000X	0x25c08086
@@ -199,6 +204,57 @@ extern "C" {
 #define	INTEL_NB_5400B	0x40038086
 #define	INTEL_NB_7300	0x36008086
 
+#define	INTEL_NHM	0x2c408086
+#define	INTEL_QP_IO	0x34008086
+#define	INTEL_QP_36D	0x34068086
+#define	INTEL_QP_24D	0x34038086
+
+/* Intel QuickPath Bus Interconnect Errors */
+
+#define	MSR_MC_STATUS_QP_HEADER_PARITY		(1 << 16)
+#define	MSR_MC_STATUS_QP_DATA_PARITY		(1 << 17)
+#define	MSR_MC_STATUS_QP_RETRIES_EXCEEDED	(1 << 18)
+#define	MSR_MC_STATUS_QP_POISON		(1 << 19)
+
+#define	MSR_MC_STATUS_QP_UNSUPPORTED_MSG	(1 << 22)
+#define	MSR_MC_STATUS_QP_UNSUPPORTED_CREDIT	(1 << 23)
+#define	MSR_MC_STATUS_QP_FLIT_BUF_OVER		(1 << 24)
+#define	MSR_MC_STATUS_QP_FAILED_RESPONSE	(1 << 25)
+#define	MSR_MC_STATUS_QP_CLOCK_JITTER		(1 << 26)
+
+#define	MSR_MC_MISC_QP_CLASS		0x000000ff
+#define	MSR_MC_MISC_QP_RTID		0x00003f00
+#define	MSR_MC_MISC_QP_RHNID		0x00070000
+#define	MSR_MC_MISC_QP_IIB		0x01000000
+
+/* Intel QuickPath Memory Errors */
+
+#define	MCAX86_COMPOUND_BUS_MEMORY		0x0080
+#define	MCAX86_COMPOUND_BUS_MEMORY_MASK		0xff80
+#define	MCAX86_COMPOUND_BUS_MEMORY_TRANSACTION	0x0070
+#define	MCAX86_COMPOUND_BUS_MEMORY_READ		0x0010
+#define	MCAX86_COMPOUND_BUS_MEMORY_WRITE	0x0020
+#define	MCAX86_COMPOUND_BUS_MEMORY_CMD		0x0030
+#define	MCAX86_COMPOUND_BUS_MEMORY_CHANNEL	0x000f
+
+#define	MSR_MC_STATUS_MEM_ECC_READ	(1 << 16)
+#define	MSR_MC_STATUS_MEM_ECC_SCRUB	(1 << 17)
+#define	MSR_MC_STATUS_MEM_PARITY	(1 << 18)
+#define	MSR_MC_STATUS_MEM_REDUNDANT_MEM	(1 << 19)
+#define	MSR_MC_STATUS_MEM_SPARE_MEM	(1 << 20)
+#define	MSR_MC_STATUS_MEM_ILLEGAL_ADDR	(1 << 21)
+#define	MSR_MC_STATUS_MEM_BAD_ID	(1 << 22)
+#define	MSR_MC_STATUS_MEM_ADDR_PARITY	(1 << 23)
+#define	MSR_MC_STATUS_MEM_BYTE_PARITY	(1 << 24)
+
+#define	MSR_MC_MISC_MEM_RTID		0x00000000000000ffULL
+#define	MSR_MC_MISC_MEM_DIMM		0x0000000000030000ULL
+#define	MSR_MC_MISC_MEM_DIMM_SHIFT	16
+#define	MSR_MC_MISC_MEM_CHANNEL		0x00000000000c0000ULL
+#define	MSR_MC_MISC_MEM_CHANNEL_SHIFT	18
+#define	MSR_MC_MISC_MEM_SYNDROME	0xffffffff00000000ULL
+#define	MSR_MC_MISC_MEM_SYNDROME_SHIFT	32
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/usr/src/uts/intel/sys/mca_x86.h b/usr/src/uts/intel/sys/mca_x86.h
index 91b9a5bbfc..8e633f9a39 100644
--- a/usr/src/uts/intel/sys/mca_x86.h
+++ b/usr/src/uts/intel/sys/mca_x86.h
@@ -18,15 +18,13 @@
  *
  * CDDL HEADER END
  *
- * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
 #ifndef _SYS_MCA_X86_H
 #define	_SYS_MCA_X86_H
 
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
 /*
  * Constants for the Memory Check Architecture as implemented on generic x86
  * CPUs.
@@ -49,6 +47,7 @@ extern "C" {
 #define	MCG_CAP_CTL_P			0x00000100ULL
 #define	MCG_CAP_EXT_P			0x00000200ULL
 #define	MCG_CAP_TES_P			0x00000800ULL
+#define	MCG_CAP_MISC2_P			0x00000400ULL
 
 #define	MCG_CAP_COUNT_MASK		0x000000ffULL
 #define	MCG_CAP_COUNT(cap) ((cap) & MCG_CAP_COUNT_MASK)
@@ -90,10 +89,13 @@ extern "C" {
 #define	_IA32_MSR_OFFSET_ADDR		0x2	/* offset within a bank */
 #define	_IA32_MSR_OFFSET_MISC		0x3	/* offset within a bank */
 
+#define	_IA32_MSR_MC0_MISC2		0x280ULL /* first MCi_MISC2 reg */
 
 #define	IA32_MSR_MC(i, which) \
 	(_IA32_MSR_MC0_CTL + (i) * 4 + _IA32_MSR_OFFSET_##which)
 
+#define	IA32_MSR_MC_MISC2(i)	(_IA32_MSR_MC0_MISC2 + (i))
+
 /*
  * IA32_MSR_MCG_CAP.MCG_EXT_P indicates that a processor implements
  * a set of extended machine-check registers starting at MSR 0x180;
@@ -189,10 +191,16 @@ typedef union mca_x86_mcistatus {
 #define	MSR_MC_STATUS_RESERVED_MASK	0x0180000000000000ULL
 #define	MSR_MC_STATUS_TBES_MASK		0x0060000000000000ULL
 #define	MSR_MC_STATUS_TBES_SHIFT	53
+#define	MSR_MC_STATUS_CEC_MASK		0x001fffc000000000ULL
+#define	MSR_MC_STATUS_CEC_SHIFT	38
 #define	MSR_MC_STATUS_MSERR_MASK	0x00000000ffff0000ULL
 #define	MSR_MC_STATUS_MSERR_SHIFT	16
 #define	MSR_MC_STATUS_MCAERR_MASK	0x000000000000ffffULL
 
+#define	MSR_MC_MISC2_EN			0x0000000040000000ULL
+#define	MSR_MC_MISC2_THRESHOLD_MASK	0x0000000000007fffULL
+#define	MSR_MC_MISC2_THRESHOLD_OVERFLOW	0x0000000000004000ULL
+
 /*
  * Macros to extract error code and model-specific error code.
  */
@@ -265,6 +273,36 @@ typedef union mca_x86_mcistatus {
 #define	MCAX86_ERRCODE_T(code) \
 	(((code) & MCAX86_ERRCODE_T_MASK) >> MCAX86_ERRCODE_T_SHIFT)
 
+#define	MCAX86_ERRCODE_MMM_MASK		0x0070
+#define	MCAX86_ERRCODE_MMM_SHIFT	4
+#define	MCAX86_ERRCODE_MMM_GEN		0x0
+#define	MCAX86_ERRCODE_MMM_RD		0x1
+#define	MCAX86_ERRCODE_MMM_WR		0x2
+#define	MCAX86_ERRCODE_MMM_ADRCMD	0x3
+#define	MCAX86_ERRCODE_MMM(code) \
+	(((code) & MCAX86_ERRCODE_MMM_MASK) >> MCAX86_ERRCODE_MMM_SHIFT)
+
+#define	MCAX86_ERRCODE_CCCC_MASK	0x000f
+#define	MCAX86_ERRCODE_CCCC_SHIFT	0
+#define	MCAX86_ERRCODE_CCCC_CH0		0x0
+#define	MCAX86_ERRCODE_CCCC_CH1		0x1
+#define	MCAX86_ERRCODE_CCCC_CH2		0x2
+#define	MCAX86_ERRCODE_CCCC_CH3		0x3
+#define	MCAX86_ERRCODE_CCCC_CH4		0x4
+#define	MCAX86_ERRCODE_CCCC_CH5		0x5
+#define	MCAX86_ERRCODE_CCCC_CH6		0x6
+#define	MCAX86_ERRCODE_CCCC_CH7		0x7
+#define	MCAX86_ERRCODE_CCCC_CH8		0x8
+#define	MCAX86_ERRCODE_CCCC_CH9		0x9
+#define	MCAX86_ERRCODE_CCCC_CH10	0xa
+#define	MCAX86_ERRCODE_CCCC_CH11	0xb
+#define	MCAX86_ERRCODE_CCCC_CH12	0xc
+#define	MCAX86_ERRCODE_CCCC_CH13	0xd
+#define	MCAX86_ERRCODE_CCCC_CH14	0xe
+#define	MCAX86_ERRCODE_CCCC_GEN		0xf
+#define	MCAX86_ERRCODE_CCCC(code) \
+	(((code) & MCAX86_ERRCODE_CCCC_MASK) >> MCAX86_ERRCODE_CCCC_SHIFT)
+
 /*
  * Simple error encoding.  MASKON are bits that must be set for a match
  * at the same time bits indicated by MASKOFF are clear.
@@ -281,6 +319,9 @@ typedef union mca_x86_mcistatus {
 #define	MCAX86_SIMPLE_FRC_MASKON			0x0004
 #define	MCAX86_SIMPLE_FRC_MASKOFF			0xfffb
 
+#define	MCAX86_SIMPLE_INTERNAL_PARITY_MASKON		0x0005
+#define	MCAX86_SIMPLE_INTERNAL_PARITY_MASKOFF		0xfffa
+
 #define	MCAX86_SIMPLE_INTERNAL_TIMER_MASKON		0x0400
 #define	MCAX86_SIMPLE_INTERNAL_TIMER_MASKOFF		0xfbff
 
@@ -306,7 +347,7 @@ typedef union mca_x86_mcistatus {
  */
 #define	MCAX86_ERRCODE_ISSIMPLE(code) \
 	((code) >= MCAX86_SIMPLE_UNCLASSIFIED_MASKON && \
-	(code) <= MCAX86_SIMPLE_FRC_MASKON || \
+	(code) <= MCAX86_SIMPLE_INTERNAL_PARITY_MASKON || \
 	(code) == MCAX86_SIMPLE_INTERNAL_TIMER_MASKON || \
 	MCAX86_ERRCODE_ISSIMPLE_INTERNAL_UNCLASS(code))
 
@@ -326,6 +367,9 @@ typedef union mca_x86_mcistatus {
 #define	MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON		0x0800
 #define	MCAX86_COMPOUND_BUS_INTERCONNECT_MASKOFF	0xe000
 
+#define	MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKON	0x0080
+#define	MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKOFF	0xff00
+
 /*
  * Macros to make compound error codes and to test for each type.
  */
@@ -368,11 +412,21 @@ typedef union mca_x86_mcistatus {
 	MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON && \
 	((code) & MCAX86_COMPOUND_BUS_INTERCONNECT_MASKOFF) == 0)
 
+#define	MCAX86_MKERRCODE_MEMORY_CONTROLLER (mmm, cccc) \
+	(MCAX86_COMPOUNT_MEMORY_CONTROLLER_MASKON | \
+	((mmm) << MCAX86_ERRCODE_MMM_SHIFT & MCAX86_ERRCODE_MMM_MASK) | \
+	((cccc) << MCAX86_ERRCODE_CCCC_SHIFT & MCAX86_ERRCODE_CCCC_MASK))
+#define	MCAX86_ERRCODE_ISMEMORY_CONTROLLER(code) \
+	(((code) & MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKON) == \
+	MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKON && \
+	((code) & MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKOFF) == 0)
+
 #define	MCAX86_ERRCODE_ISCOMPOUND(code) \
 	(MCAX86_ERRCODE_ISGENERIC_MEMHIER(code) || \
 	MCAX86_ERRCODE_ISTLB(code) || \
-	MCAX86_ERRCODE_ISMEMHIER(code) \
-	MCAX86_ERRCODE_ISBUS_INTERCONNECT(code))
+	MCAX86_ERRCODE_ISMEMHIER(code) || \
+	MCAX86_ERRCODE_ISBUS_INTERCONNECT(code) || \
+	MCAX86_ERRCODE_ISMEMORY_CONTROLLER(code))
 
 #define	MCAX86_ERRCODE_UNKNOWN(code) \
 	(!MCAX86_ERRCODE_ISSIMPLE(code) && !MCAX86_ERRCODE_ISCOMPOUND(code))