[illumos-gate merge]release-20200409

commit 62366fbbe8edca853fee6c14327d822239ba914f
    12466 Enable IPv6 TSO Support for vioif
commit d240edaf609c558d5a1f981b09a577823b54fae2
    12465 vioif needs length for tso checksum
commit 425251fd07ab465313fb50dea0f1ac795be10e05
    9059 Simplify SMAP relocations with krtld
commit 28e0ac9c914344194ef919b0271895d33f83d396
    12433 efcode: NULL pointer errors
commit 31aa620247ae407b2bee2dccd71693d1938f54d6
    12452 Want support for AMD Zen 2 CPC Events

	Conflicts:
	usr/src/uts/i86pc/os/machdep.c
	usr/src/uts/common/io/dld/dld_proto.c
	usr/src/uts/common/inet/ip/ip_if.c

3 files changed, 47 insertions, 33 deletions

diff --git a/usr/src/uts/intel/ia32/ml/copy.s b/usr/src/uts/intel/ia32/ml/copy.s
index 8c23d794f9..5e5f822518 100644
--- a/usr/src/uts/intel/ia32/ml/copy.s
+++ b/usr/src/uts/intel/ia32/ml/copy.s
@@ -36,7 +36,7 @@
 /*         All Rights Reserved						*/
 
 /*
- * Copyright 2019 Joyent, Inc.
+ * Copyright 2020 Joyent, Inc.
  */
 
 #include <sys/errno.h>
@@ -66,11 +66,10 @@
  *
  * Rules and Constraints:
  *
- * 1. For anything that's not in copy.s, we have it do explicit calls to the
- * smap related code. It usually is in a position where it is able to. This is
- * restricted to the following three places: DTrace, resume() in swtch.s and
- * on_fault/no_fault. If you want to add it somewhere else, we should be
- * thinking twice.
+ * 1. For anything that's not in copy.s, we have it do explicit smap_disable()
+ * or smap_enable() calls.  This is restricted to the following three places:
+ * DTrace, resume() in swtch.s and on_fault/no_fault. If you want to add it
+ * somewhere else, we should be thinking twice.
  *
  * 2. We try to toggle this at the smallest window possible. This means that if
  * we take a fault, need to try to use a copyop in copyin() or copyout(), or any
@@ -81,33 +80,25 @@
  * explicitly only allowed to be called while in an on_fault()/no_fault() handler,
  * which already takes care of ensuring that SMAP is enabled and disabled. Note
  * this means that when under an on_fault()/no_fault() handler, one must not
- * call the non-*_noeer() routines.
+ * call the non-*_noerr() routines.
  *
  * 4. The first thing we should do after coming out of an lofault handler is to
- * make sure that we call smap_enable again to ensure that we are safely
+ * make sure that we call smap_enable() again to ensure that we are safely
  * protected, as more often than not, we will have disabled smap to get there.
  *
- * 5. The SMAP functions, smap_enable and smap_disable may not touch any
- * registers beyond those done by the call and ret. These routines may be called
- * from arbitrary contexts in copy.s where we have slightly more special ABIs in
- * place.
+ * 5. smap_enable() and smap_disable() don't exist: calls to these functions
+ * generate runtime relocations, that are then processed into the necessary
+ * clac/stac, via the krtld hotinlines mechanism and hotinline_smap().
  *
  * 6. For any inline user of SMAP, the appropriate SMAP_ENABLE_INSTR and
- * SMAP_DISABLE_INSTR macro should be used (except for smap_enable() and
- * smap_disable()). If the number of these is changed, you must update the
- * constants SMAP_ENABLE_COUNT and SMAP_DISABLE_COUNT below.
+ * SMAP_DISABLE_INSTR macro should be used. If the number of these is changed,
+ * you must update the constants SMAP_ENABLE_COUNT and SMAP_DISABLE_COUNT below.
  *
- * 7. Note, at this time SMAP is not implemented for the 32-bit kernel. There is
- * no known technical reason preventing it from being enabled.
- *
- * 8. Generally this .s file is processed by a K&R style cpp. This means that it
+ * 7. Generally this .s file is processed by a K&R style cpp. This means that it
  * really has a lot of feelings about whitespace. In particular, if you have a
  * macro FOO with the arguments FOO(1, 3), the second argument is in fact ' 3'.
  *
- * 9. The smap_enable and smap_disable functions should not generally be called.
- * They exist such that DTrace and on_trap() may use them, that's it.
- *
- * 10. In general, the kernel has its own value for rflags that gets used. This
+ * 8. In general, the kernel has its own value for rflags that gets used. This
  * is maintained in a few different places which vary based on how the thread
  * comes into existence and whether it's a user thread. In general, when the
  * kernel takes a trap, it always will set ourselves to a known set of flags,
diff --git a/usr/src/uts/intel/opteron_pcbe/Makefile b/usr/src/uts/intel/opteron_pcbe/Makefile
index 2d45ea3801..16cb0f41e5 100644
--- a/usr/src/uts/intel/opteron_pcbe/Makefile
+++ b/usr/src/uts/intel/opteron_pcbe/Makefile
@@ -33,7 +33,8 @@ UTSBASE = ../..
 # The following objects are autogenerated by cpcgen.
 #
 CPCGEN_OBJS	= \
-	opteron_pcbe_f17h.o
+	opteron_pcbe_f17h_zen1.o \
+	opteron_pcbe_f17h_zen2.o
 
 CPCGEN_COMMON	= opteron_pcbe_cpcgen.h
 CPCGEN_CMD	= $(CPCGEN) -d $(SRC)/data/amdpmc -o .
@@ -100,7 +101,7 @@ opteron_pcbe_cpcgen.h:
 opteron_pcbe_%.c: $(CPCGEN_COMMON)
 	$(CPCGEN_CMD) -c -p \
 	    $$(echo $@ | \
-	    $(SED) -e 's/opteron_pcbe_//g' -e 's/_/-/g' -e 's/.c$$//g')
+	    $(SED) -e 's/opteron_pcbe_//g' -e 's/.c$$//g')
 
 $(OBJS_DIR)/%.o: %.c
 	$(COMPILE.c) -I$(SRC)/uts/intel/pcbe/ -o $@ $<
diff --git a/usr/src/uts/intel/pcbe/opteron_pcbe.c b/usr/src/uts/intel/pcbe/opteron_pcbe.c
index 6a875ec681..c4496bf8ca 100644
--- a/usr/src/uts/intel/pcbe/opteron_pcbe.c
+++ b/usr/src/uts/intel/pcbe/opteron_pcbe.c
@@ -449,11 +449,11 @@ static const amd_generic_event_t family_10h_generic_events[] = {
 /*
  * For Family 17h, the cpcgen utility generates all of our events including ones
  * that need specific unit codes, therefore we leave all unit codes out of
- * these.
+ * these. Zen 1 and Zen 2 have different event sets that they support.
  */
-static const amd_generic_event_t family_17h_papi_events[] = {
+static const amd_generic_event_t family_17h_zen1_papi_events[] = {
 	{ "PAPI_br_cn",		"ExRetCond" },
-	{ "PAPI_br_ins",	"ExRetBrnMis" },
+	{ "PAPI_br_ins",	"ExRetBrn" },
 	{ "PAPI_fpu_idl",	"FpSchedEmpty" },
 	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
 	{ "PAPI_tot_ins",	"ExRetInstr" },
@@ -463,6 +463,18 @@ static const amd_generic_event_t family_17h_papi_events[] = {
 	GEN_EV_END
 };
 
+static const amd_generic_event_t family_17h_zen2_papi_events[] = {
+	{ "PAPI_br_cn",		"ExRetCond" },
+	{ "PAPI_br_ins",	"ExRetBrn" },
+	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
+	{ "PAPI_tot_ins",	"ExRetInstr" },
+	{ "PAPI_tlb_dm",	"LsL1DTlbMiss" },
+	{ "PAPI_tlb_im",	"BpL1TlbMissL2Miss" },
+	{ "PAPI_tot_cyc",	"LsNotHaltedCyc" },
+	GEN_EV_END
+};
+
+
 static char	*evlist;
 static size_t	evlist_sz;
 static const amd_event_t *amd_events = NULL;
@@ -477,9 +489,14 @@ static char amd_fam_10h_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
 "(BKDG) For AMD Family 10h Processors\" (AMD publication 31116)";
 static char amd_fam_11h_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
 "(BKDG) For AMD Family 11h Processors\" (AMD publication 41256)";
-static char amd_fam_17h_reg[] = "See \"Open-Source Register Reference For "
+static char amd_fam_17h_zen1_reg[] = "See \"Open-Source Register Reference For "
 "AMD Family 17h Processors Models 00h-2Fh\" (AMD publication 56255) and "
-"amd_f17h_events(3CPC)";
+"amd_f17h_zen1_events(3CPC)";
+static char amd_fam_17h_zen2_reg[] = "See \"Preliminary Processor Programming "
+"Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors\" "
+"(AMD publication 55803), \"Processor Programming Reference (PPR) for AMD "
+"Family 17h Model 71h, Revision B0 Processors\" (AMD publication 56176), and "
+"amd_f17h_zen2_events(3CPC)";
 
 static char amd_pcbe_impl_name[64];
 static char *amd_pcbe_cpuref;
@@ -582,9 +599,14 @@ opt_pcbe_init(void)
 		amd_events = family_11h_events;
 		amd_generic_events = opt_generic_events;
 	} else if (amd_family == 0x17 && amd_model <= 0x2f) {
-		amd_pcbe_cpuref = amd_fam_17h_reg;
-		amd_events = opteron_pcbe_f17h_events;
-		amd_generic_events = family_17h_papi_events;
+		amd_pcbe_cpuref = amd_fam_17h_zen1_reg;
+		amd_events = opteron_pcbe_f17h_zen1_events;
+		amd_generic_events = family_17h_zen1_papi_events;
+	} else if (amd_family == 0x17 && amd_model >= 0x30 &&
+	    amd_model <= 0x7f) {
+		amd_pcbe_cpuref = amd_fam_17h_zen2_reg;
+		amd_events = opteron_pcbe_f17h_zen2_events;
+		amd_generic_events = family_17h_zen2_papi_events;
 	} else {
 		/*
 		 * Different families have different meanings on events and even