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authorsethg <none@none>2005-11-23 12:13:42 -0800
committersethg <none@none>2005-11-23 12:13:42 -0800
commit1a48003f96d5bf304ca739198913e42e5adb9bcf (patch)
tree26c30e332d6317d04c3a5cf3aab4b2d8f8b9c035 /usr/src
parent1b605adac24e79b09fa73223048c17980b0a6068 (diff)
downloadillumos-joyent-1a48003f96d5bf304ca739198913e42e5adb9bcf.tar.gz
6354441 Ferrari 4000 hard hangs on reboot after 11/11
Diffstat (limited to 'usr/src')
-rw-r--r--usr/src/psm/stand/boot/i386/i86pc/asm.s28
-rw-r--r--usr/src/uts/intel/ia32/ml/i86_subr.s28
2 files changed, 32 insertions, 24 deletions
diff --git a/usr/src/psm/stand/boot/i386/i86pc/asm.s b/usr/src/psm/stand/boot/i386/i86pc/asm.s
index 5c42009b92..aaac774ec3 100644
--- a/usr/src/psm/stand/boot/i386/i86pc/asm.s
+++ b/usr/src/psm/stand/boot/i386/i86pc/asm.s
@@ -243,17 +243,6 @@ donetable:
/ under extreme circumstances.
ENTRY(reset)
- / Try the PCI (soft) reset vector (should work on all modern systems)
- / When resetting via this method, 2 writes are required. The first
- / targets bit 1 (0=hard reset without power cycle, 1=hard reset with power
- / cycle).
- / The reset occurs on the second write, during bit 2's transition from 0->1.
- movw $0xcf9, %dx
- movb $0x2, %al / Reset mode = hard, no power cycle
- outb (%dx)
- movb $0x6, %al
- outb (%dx)
-
/
/ Try the classic keyboard controller-triggered reset.
/
@@ -276,8 +265,23 @@ donetable:
orb $1, %al / Set bit 0
outb (%dx) / and reset the system
1:
+
+ / Try the PCI (soft) reset vector (should work on all modern systems,
+ / but has been shown to cause problems on 450NX systems, and some newer
+ / systems (e.g. ATI IXP400-equipped systems))
+ / When resetting via this method, 2 writes are required. The first
+ / targets bit 1 (0=hard reset without power cycle, 1=hard reset with
+ / power cycle).
+ / The reset occurs on the second write, during bit 2's transition from
+ / 0->1.
+ movw $0xcf9, %dx
+ movb $0x2, %al / Reset mode = hard, no power cycle
+ outb (%dx)
+ movb $0x6, %al
+ outb (%dx)
+
/
- / port 0x92 failed also. Last-ditch effort is to
+ / port 0xcf9 failed also. Last-ditch effort is to
/ triple-fault the CPU.
/
movw $0, IDTlimit / generate faulty table
diff --git a/usr/src/uts/intel/ia32/ml/i86_subr.s b/usr/src/uts/intel/ia32/ml/i86_subr.s
index dfc709759c..fd8f24cce6 100644
--- a/usr/src/uts/intel/ia32/ml/i86_subr.s
+++ b/usr/src/uts/intel/ia32/ml/i86_subr.s
@@ -1429,17 +1429,6 @@ pc_reset(void)
#else /* __lint */
ENTRY(pc_reset)
- / Try the PCI (soft) reset vector (should work on all modern systems)
- / When resetting via this method, 2 writes are required. The first
- / targets bit 1 (0=hard reset without power cycle, 1=hard reset with power
- / cycle).
- / The reset occurs on the second write, during bit 2's transition from 0->1.
- movw $0xcf9, %dx
- movb $0x2, %al / Reset mode = hard, no power cycle
- outb (%dx)
- movb $0x6, %al
- outb (%dx)
-
/
/ Try the classic keyboard controller-triggered reset.
/
@@ -1462,8 +1451,23 @@ pc_reset(void)
orb $1, %al / Set bit 0
outb (%dx) / and reset the system
1:
+
+ / Try the PCI (soft) reset vector (should work on all modern systems,
+ / but has been shown to cause problems on 450NX systems, and some newer
+ / systems (e.g. ATI IXP400-equipped systems))
+ / When resetting via this method, 2 writes are required. The first
+ / targets bit 1 (0=hard reset without power cycle, 1=hard reset with
+ / power cycle).
+ / The reset occurs on the second write, during bit 2's transition from
+ / 0->1.
+ movw $0xcf9, %dx
+ movb $0x2, %al / Reset mode = hard, no power cycle
+ outb (%dx)
+ movb $0x6, %al
+ outb (%dx)
+
/
- / port 0x92 failed also. Last-ditch effort is to
+ / port 0xcf9 failed also. Last-ditch effort is to
/ triple-fault the CPU.
/
#if defined(__amd64)