OS-7407 add new x86 CR4, EFER and debug register bit definitions

Reviewed by: John Levon <john.levon@joyent.com>
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>
Approved by: John Levon <john.levon@joyent.com>

3 files changed, 22 insertions, 8 deletions

diff --git a/usr/src/compat/freebsd/amd64/machine/specialreg.h b/usr/src/compat/freebsd/amd64/machine/specialreg.h
index 12bcbfd0a8..59fc064a4c 100644
--- a/usr/src/compat/freebsd/amd64/machine/specialreg.h
+++ b/usr/src/compat/freebsd/amd64/machine/specialreg.h
@@ -36,6 +36,7 @@
 #undef	CR4_PCE
 #undef	CR4_VMXE
 #undef	CR4_SMEP
+#undef	CR4_FSGSBASE
 #undef	CR4_PCIDE
 #endif /* _SYS_CONTROLREGS_H */
 
diff --git a/usr/src/uts/intel/sys/controlregs.h b/usr/src/uts/intel/sys/controlregs.h
index fe0cf687b4..babf036e0b 100644
--- a/usr/src/uts/intel/sys/controlregs.h
+++ b/usr/src/uts/intel/sys/controlregs.h
@@ -86,8 +86,8 @@ extern "C" {
 
 /* CR3 Register */
 
-#define	CR3_PCD	0x00000010		/* cache disable 		*/
-#define	CR3_PWT 0x00000008		/* write through 		*/
+#define	CR3_PCD	0x00000010		/* cache disable		*/
+#define	CR3_PWT 0x00000008		/* write through		*/
 #if defined(_ASM)
 #define	CR3_NOINVL_BIT	0x8000000000000000
 #else
@@ -110,18 +110,22 @@ extern "C" {
 #define	CR4_PCE		0x0100		/* perf-monitoring counter enable */
 #define	CR4_OSFXSR	0x0200		/* OS fxsave/fxrstor support	*/
 #define	CR4_OSXMMEXCPT	0x0400		/* OS unmasked exception support */
-					/* 0x0800 reserved */
+#define	CR4_UMIP	0x0800		/* user-mode instruction prevention */
 					/* 0x1000 reserved */
-#define	CR4_VMXE	0x2000
-#define	CR4_SMXE	0x4000
+#define	CR4_VMXE	0x2000		/* VMX enable */
+#define	CR4_SMXE	0x4000		/* SMX enable */
+					/* 0x8000 reserved */
+#define	CR4_FSGSBASE	0x10000		/* FSGSBASE enable */
 #define	CR4_PCIDE	0x20000		/* PCID enable */
 #define	CR4_OSXSAVE	0x40000		/* OS xsave/xrestore support	*/
 #define	CR4_SMEP	0x100000	/* NX for user pages in kernel */
 #define	CR4_SMAP	0x200000	/* kernel can't access user pages */
+#define	CR4_PKE		0x400000	/* protection key enable */
 
 #define	FMT_CR4						\
-	"\20\26smap\25smep\23osxsav\22pcide"		\
-	"\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge"	\
+	"\20\27pke\26smap\25smep\23osxsav"		\
+	"\22pcide\20fsgsbase\17smxe\16vmxe"		\
+	"\14umip\13xmme\12fxsr\11pce\10pge"		\
 	"\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
 
 /*
@@ -158,7 +162,9 @@ extern "C" {
 
 #define	MSR_AMD_EFER	0xc0000080	/* extended feature enable MSR */
 
+#define	AMD_EFER_TCE	0x8000		/* translation cache extension */
 #define	AMD_EFER_FFXSR	0x4000		/* fast fxsave/fxrstor		*/
+#define	AMD_EFER_LMSLE	0x2000		/* long mode segment limit enable */
 #define	AMD_EFER_SVME	0x1000		/* svm enable			*/
 #define	AMD_EFER_NXE	0x0800		/* no-execute enable		*/
 #define	AMD_EFER_LMA	0x0400		/* long mode active (read-only)	*/
@@ -166,7 +172,7 @@ extern "C" {
 #define	AMD_EFER_SCE	0x0001		/* system call extensions	*/
 
 #define	FMT_AMD_EFER \
-	"\20\17ffxsr\15svme\14nxe\13lma\11lme\1sce"
+	"\20\20tce\17ffxsr\16lmsle\15svme\14nxe\13lma\11lme\1sce"
 
 /* AMD's SYSCFG register */
 
diff --git a/usr/src/uts/intel/sys/debugreg.h b/usr/src/uts/intel/sys/debugreg.h
index b537076d26..8528a293ab 100644
--- a/usr/src/uts/intel/sys/debugreg.h
+++ b/usr/src/uts/intel/sys/debugreg.h
@@ -26,6 +26,9 @@
 /*	Copyright (c) 1990, 1991 UNIX System Laboratories, Inc.	*/
 /*	Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T	*/
 /*	  All Rights Reserved	*/
+/*
+ * Copyright (c) 2018, Joyent, Inc.  All rights reserved.
+ */
 
 #ifndef	_SYS_DEBUGREG_H
 #define	_SYS_DEBUGREG_H
@@ -57,6 +60,7 @@ extern "C" {
 #define	DR_ICEALSO	0x2000	/* Flag bit reserved for in-circuit-emulator */
 #define	DR_SINGLESTEP	0x4000	/* Trap resulting from the single-step flag */
 #define	DR_TASKSWITCH	0x8000	/* Trap resulting from a task-switch */
+#define	DR_IN_RTM	0x10000	/* Trap inside an RTM region */
 
 /*
  * dr7 controls the rest of the debug registers.
@@ -73,6 +77,8 @@ extern "C" {
 #define	DR_CONTROL_RESERVED	0xFC00	/* Bits reserved by Intel */
 #define	DR_LOCAL_SLOWDOWN	0x100	/* Slow the pipeline for ldt addrs */
 #define	DR_GLOBAL_SLOWDOWN	0x200	/* Slow the pipeline for gdt addrs */
+#define	DR_RTM			0x800	/* Restricted Transactional Memory */
+#define	DR_GENERAL_DETECT	0x2000	/* General Detect Enable */
 
 #define	DR_LOCAL_ENABLE_SHIFT	0	/* Additional shift: local enable  */
 #define	DR_GLOBAL_ENABLE_SHIFT	1	/* Additional shift: global enable */
@@ -95,6 +101,7 @@ extern "C" {
 #define	DR_LEN_1		0x0	/* Settings for data length */
 #define	DR_LEN_2		0x4
 #define	DR_LEN_4		0xC
+#define	DR_LEN_8		0x8
 
 #ifdef	__cplusplus
 }