diff options
author | Zhi-Jun Robin Fu <Zhijun.Fu@Sun.COM> | 2009-05-06 18:52:10 -0700 |
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committer | Zhi-Jun Robin Fu <Zhijun.Fu@Sun.COM> | 2009-05-06 18:52:10 -0700 |
commit | 3f9ec228364807fa87fd5d76aaffadf5d919c931 (patch) | |
tree | 1334b7c3f4dd28ed14e047a2afa8b3b7b90b071f /usr/src | |
parent | 6e3e9d9c7ec812d402e1c911922ec43d4047dec8 (diff) | |
download | illumos-joyent-3f9ec228364807fa87fd5d76aaffadf5d919c931.tar.gz |
6708175 Elara - Cannot hotplug and initialize Elara Module on x86 w/Nevada 105
6816350 Hot-plug with Hydra NEM shows memory allocation warning in ethernet BASE register
Diffstat (limited to 'usr/src')
-rw-r--r-- | usr/src/uts/common/io/pcie.c | 14 | ||||
-rw-r--r-- | usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c | 30 | ||||
-rw-r--r-- | usr/src/uts/sparc/os/driver_aliases | 1 | ||||
-rw-r--r-- | usr/src/uts/sun4/io/efcode/fcpci.c | 4 | ||||
-rw-r--r-- | usr/src/uts/sun4/io/pcicfg.e.c | 37 |
5 files changed, 70 insertions, 16 deletions
diff --git a/usr/src/uts/common/io/pcie.c b/usr/src/uts/common/io/pcie.c index cc661260e4..db8b7c8486 100644 --- a/usr/src/uts/common/io/pcie.c +++ b/usr/src/uts/common/io/pcie.c @@ -534,6 +534,7 @@ pcie_init_bus(dev_info_t *cdip) ddi_acc_handle_t eh = NULL; int range_size; dev_info_t *pdip; + const char *errstr = NULL; ASSERT(PCIE_DIP2UPBUS(cdip) == NULL); @@ -546,14 +547,17 @@ pcie_init_bus(dev_info_t *cdip) /* Create an config access special to error handling */ if (pci_config_setup(cdip, &eh) != DDI_SUCCESS) { + errstr = "Cannot setup config access"; goto fail; } bus_p->bus_cfg_hdl = eh; bus_p->bus_fm_flags = 0; /* get device's bus/dev/function number */ - if (pcie_get_bdf_from_dip(cdip, &bus_p->bus_bdf) != DDI_SUCCESS) + if (pcie_get_bdf_from_dip(cdip, &bus_p->bus_bdf) != DDI_SUCCESS) { + errstr = "Cannot get device BDF"; goto fail; + } /* Save the Vendor Id Device Id */ bus_p->bus_dev_ven_id = PCIE_GET(32, bus_p, PCI_CONF_VENID); @@ -599,8 +603,10 @@ pcie_init_bus(dev_info_t *cdip) range_size = sizeof (pci_bus_range_t); if (ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus_p->bus_bus_range, &range_size) - != DDI_PROP_SUCCESS) + != DDI_PROP_SUCCESS) { + errstr = "Cannot find \"bus-range\" property"; goto fail; + } /* get secondary bus number */ bus_p->bus_bdg_secbus = PCIE_GET(8, bus_p, PCI_BCNF_SECBUS); @@ -661,8 +667,8 @@ pcie_init_bus(dev_info_t *cdip) return (bus_p); fail: - cmn_err(CE_WARN, "PCIE init err info failed BDF 0x%x\n", - bus_p->bus_bdf); + cmn_err(CE_WARN, "PCIE init err info failed BDF 0x%x:%s\n", + bus_p->bus_bdf, errstr); if (eh) pci_config_teardown(&eh); kmem_free(bus_p, sizeof (pcie_bus_t)); diff --git a/usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c b/usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c index 7ca5da0bb4..86ab694cfe 100644 --- a/usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c +++ b/usr/src/uts/intel/io/hotplug/pcicfg/pcicfg.c @@ -19,7 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2008 Sun Microsystems, Inc. All rights reserved. + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -3911,6 +3911,34 @@ pf_setup_end: (void) pcicfg_set_bus_numbers(h, bus, new_bus, max_bus); /* + * Setup "ranges" and "bus-range" properties before onlining + * the bridge. + */ + bzero((caddr_t)range, sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); + + range[0].child_high = range[0].parent_high |= (PCI_REG_REL_M | + PCI_ADDR_IO); + range[0].child_low = range[0].parent_low = io_base; + range[1].child_high = range[1].parent_high |= + (PCI_REG_REL_M | PCI_ADDR_MEM32); + range[1].child_low = range[1].parent_low = mem_base; + range[2].child_high = range[2].parent_high |= + (PCI_REG_REL_M | PCI_ADDR_MEM64 | PCI_REG_PF_M); + range[2].child_low = range[2].parent_low = pf_mem_base; + + range[0].size_low = io_alen; + (void) pcicfg_update_ranges_prop(new_child, &range[0]); + range[1].size_low = mem_alen; + (void) pcicfg_update_ranges_prop(new_child, &range[1]); + range[2].size_low = pf_mem_alen; + (void) pcicfg_update_ranges_prop(new_child, &range[2]); + + bus_range[0] = new_bus; + bus_range[1] = max_bus; + (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, + "bus-range", bus_range, 2); + + /* * Reset the secondary bus */ pci_config_put16(h, PCI_BCNF_BCNTRL, diff --git a/usr/src/uts/sparc/os/driver_aliases b/usr/src/uts/sparc/os/driver_aliases index 20c7bc04d5..4c95e31eb4 100644 --- a/usr/src/uts/sparc/os/driver_aliases +++ b/usr/src/uts/sparc/os/driver_aliases @@ -153,6 +153,7 @@ pxb_plx "pciex10b5,8516" pxb_plx "pciex10b5,8548" pxb_plx "pciex10b5,8533" pxb_plx "pciex10b5,8517" +pxb_plx "pciex10b5,8518" pxb_plx "pciex108e,9010" pxb_plx "pciex108e,9020" vnex "SUNW,sun4v-virtual-devices" diff --git a/usr/src/uts/sun4/io/efcode/fcpci.c b/usr/src/uts/sun4/io/efcode/fcpci.c index 9b334f6b5c..2250291031 100644 --- a/usr/src/uts/sun4/io/efcode/fcpci.c +++ b/usr/src/uts/sun4/io/efcode/fcpci.c @@ -20,7 +20,7 @@ */ /* - * Copyright 2008 Sun Microsystems, Inc. All rights reserved. + * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -1334,6 +1334,8 @@ pci_alloc_resource(dev_info_t *dip, pci_regspec_t phys_spec) l = MAX(assigned[i].pci_size_low, phys_spec.pci_size_low); + phys_spec.pci_size_low = l; + (void) pci_free_resource(dip, assigned[i]); /* * Go on to allocate resources. diff --git a/usr/src/uts/sun4/io/pcicfg.e.c b/usr/src/uts/sun4/io/pcicfg.e.c index 432da990cb..5a66762757 100644 --- a/usr/src/uts/sun4/io/pcicfg.e.c +++ b/usr/src/uts/sun4/io/pcicfg.e.c @@ -4476,10 +4476,11 @@ pcicfg_probe_bridge(dev_info_t *new_child, ddi_acc_handle_t h, uint_t bus, pcicfg_set_bus_numbers(h, bus, new_bus, max_bus); - bus_range[0] = pci_config_get8(h, PCI_BCNF_SECBUS); - bus_range[1] = pci_config_get8(h, PCI_BCNF_SUBBUS); - DEBUG1("End of bridge probe: bus_range[0] = %d\n", bus_range[0]); - DEBUG1("End of bridge probe: bus_range[1] = %d\n", bus_range[1]); + /* + * Setup "bus-range" property before onlining the bridge. + */ + bus_range[0] = new_bus; + bus_range[1] = max_bus; if (ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, "bus-range", bus_range, 2) != DDI_SUCCESS) { @@ -4576,6 +4577,28 @@ pcicfg_probe_bridge(dev_info_t *new_child, ddi_acc_handle_t h, uint_t bus, } /* + * Setup "ranges" property before onlining the bridge. + */ + bzero((caddr_t)range, sizeof (pcicfg_range_t) * PCICFG_RANGE_LEN); + + range[0].child_hi = range[0].parent_hi |= (PCI_REG_REL_M | PCI_ADDR_IO); + range[0].child_lo = range[0].parent_lo = io_base; + range[1].child_hi = range[1].parent_hi |= + (PCI_REG_REL_M | PCI_ADDR_MEM32); + range[1].child_lo = range[1].parent_lo = mem_base; + + range[0].size_lo = io_alen; + if (pcicfg_update_ranges_prop(new_child, &range[0])) { + DEBUG0("Failed to update ranges (io)\n"); + return (PCICFG_FAILURE); + } + range[1].size_lo = mem_alen; + if (pcicfg_update_ranges_prop(new_child, &range[1])) { + DEBUG0("Failed to update ranges (memory)\n"); + return (PCICFG_FAILURE); + } + + /* * Clear status bits */ pci_config_put16(h, PCI_BCNF_SEC_STATUS, 0xffff); @@ -4834,12 +4857,6 @@ pcicfg_probe_bridge(dev_info_t *new_child, ddi_acc_handle_t h, uint_t bus, } /* - * Remove the bus-range property if it exists since we will create - * a new one. - */ - (void) ndi_prop_remove(DDI_DEV_T_NONE, new_child, "bus-range"); - - /* * Set bus numbers to ranges encountered during scan */ pcicfg_set_bus_numbers(h, bus, new_bus, *highest_bus); |