6401068 pcihp_impl.h header file missing from installation

6461283 IKP should program "cache-line-size" register for PCIe devices
6501533 Interrupts getting dropped during bobo DMA test
6502598 cfgadm -cconfigure of PCI-E I/O boat panics with snv_54

--HG--
rename : usr/src/uts/common/sys/hotplug/pci/pcihp_impl.h => deleted_files/usr/src/uts/common/sys/hotplug/pci/pcihp_impl.h

11 files changed, 121 insertions, 82 deletions

diff --git a/usr/src/uts/common/io/pcie.c b/usr/src/uts/common/io/pcie.c
index 55cc0e7a52..2d44c59d53 100644
--- a/usr/src/uts/common/io/pcie.c
+++ b/usr/src/uts/common/io/pcie.c
@@ -41,6 +41,7 @@
 
 static int pcie_get_bdf_from_dip(dev_info_t *dip, uint32_t *bdf);
 dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip);
+uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip);
 
 #ifdef  DEBUG
 uint_t pcie_debug_flags = 0;
@@ -534,6 +535,31 @@ pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip)
 	return (cdip);
 }
 
+uint32_t
+pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip)
+{
+	dev_info_t *cdip;
+
+	/*
+	 * As part of the probing, the PCI fcode interpreter may setup a DMA
+	 * request if a given card has a fcode on it using dip and rdip of the
+	 * AP (attachment point) i.e, dip and rdip of px/px_pci driver. In this
+	 * case, return zero for the bdf since we cannot get to the bdf value
+	 * of the actual device which will be initiating this DMA.
+	 */
+	if (rdip == dip)
+		return (0);
+
+	cdip = pcie_get_my_childs_dip(dip, rdip);
+
+	/*
+	 * For a given rdip, return the bdf value of dip's (px or px_pci)
+	 * immediate child or secondary bus-id if dip is a PCIe2PCI bridge.
+	 */
+	return (PCI_GET_SEC_BUS(cdip) ?
+	    PCI_GET_SEC_BUS(cdip) : PCI_GET_BDF(cdip));
+}
+
 #ifdef	DEBUG
 /*
  * This is a temporary stop gap measure.
diff --git a/usr/src/uts/common/sys/hotplug/pci/pcicfg.h b/usr/src/uts/common/sys/hotplug/pci/pcicfg.h
index 6bd5f55922..c800f90e5a 100644
--- a/usr/src/uts/common/sys/hotplug/pci/pcicfg.h
+++ b/usr/src/uts/common/sys/hotplug/pci/pcicfg.h
@@ -2,9 +2,8 @@
  * CDDL HEADER START
  *
  * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
+ * Common Development and Distribution License (the "License").
+ * You may not use this file except in compliance with the License.
  *
  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  * or http://www.opensolaris.org/os/licensing.
@@ -21,7 +20,7 @@
  */
 
 /*
- * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
+ * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
  * Use is subject to license terms.
  */
 
@@ -34,8 +33,6 @@
 extern "C" {
 #endif
 
-#include <sys/hotplug/pci/pcihp_impl.h>
-
 /*
  * Interfaces exported by PCI configurator module, kernel/misc/pcicfg.
  */
@@ -54,9 +51,6 @@ int pcicfg_unconfigure(dev_info_t *, uint_t);
 #define	PCICFG_CONF_INDIRECT_MAP	1
 #define	PCICFG_CONF_DIRECT_MAP		0
 
-#define	PCICFG_DEV_CONF_MAP_PROP	PCI_DEV_CONF_MAP_PROP
-#define	PCICFG_BUS_CONF_MAP_PROP	PCI_BUS_CONF_MAP_PROP
-
 #ifdef	__cplusplus
 }
 #endif
diff --git a/usr/src/uts/common/sys/hotplug/pci/pcihp.h b/usr/src/uts/common/sys/hotplug/pci/pcihp.h
index 00ad40be26..75a4ee0c2d 100644
--- a/usr/src/uts/common/sys/hotplug/pci/pcihp.h
+++ b/usr/src/uts/common/sys/hotplug/pci/pcihp.h
@@ -32,8 +32,6 @@
 extern "C" {
 #endif
 
-#include <sys/hotplug/pci/pcihp_impl.h>
-
 #ifdef	_KERNEL
 /*
  * Interfaces exported by PCI Nexus extension module, kernel/misc/pcihp.
diff --git a/usr/src/uts/common/sys/hotplug/pci/pcihp_impl.h b/usr/src/uts/common/sys/hotplug/pci/pcihp_impl.h
deleted file mode 100644
index 8a7d616ee8..0000000000
--- a/usr/src/uts/common/sys/hotplug/pci/pcihp_impl.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * CDDL HEADER START
- *
- * The contents of this file are subject to the terms of the
- * Common Development and Distribution License, Version 1.0 only
- * (the "License").  You may not use this file except in compliance
- * with the License.
- *
- * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
- * or http://www.opensolaris.org/os/licensing.
- * See the License for the specific language governing permissions
- * and limitations under the License.
- *
- * When distributing Covered Code, include this CDDL HEADER in each
- * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
- * If applicable, add the following below this CDDL HEADER, with the
- * fields enclosed by brackets "[]" replaced with your own identifying
- * information: Portions Copyright [yyyy] [name of copyright owner]
- *
- * CDDL HEADER END
- */
-
-/*
- * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
- * Use is subject to license terms.
- */
-
-#ifndef	_SYS_HOTPLUG_PCI_PCIHP_IMPL_H
-#define	_SYS_HOTPLUG_PCI_PCIHP_IMPL_H
-
-#pragma ident	"%Z%%M%	%I%	%E% SMI"
-
-#ifdef	__cplusplus
-extern "C" {
-#endif
-
-/*
- * we recognize the non transparent bridge child nodes with the
- * following property. This is specific to an implementation only.
- * This property is specific to AP nodes only.
- */
-#define	PCI_DEV_CONF_MAP_PROP	"pci-parent-indirect"
-
-/*
- * If a bridge device provides its own config space access services,
- * and supports a hotplug/hotswap bus below at any level, then
- * the following property must be defined for the node either by
- * the driver or the OBP.
- */
-#define	PCI_BUS_CONF_MAP_PROP	"pci-conf-indirect"
-
-#ifdef	__cplusplus
-}
-#endif
-
-#endif	/* _SYS_HOTPLUG_PCI_PCIHP_IMPL_H */
diff --git a/usr/src/uts/common/sys/pci.h b/usr/src/uts/common/sys/pci.h
index 858fdfa164..8eecb28c77 100644
--- a/usr/src/uts/common/sys/pci.h
+++ b/usr/src/uts/common/sys/pci.h
@@ -1018,6 +1018,21 @@ typedef struct pci_phys_spec pci_regspec_t;
 #define	PCI_PDS_CODE_TYPE_PCAT		0x0	/* Intel x86/PC-AT Type */
 #define	PCI_PDS_CODE_TYPE_OPEN_FW	0x1	/* Open Firmware */
 
+/*
+ * we recognize the non transparent bridge child nodes with the
+ * following property. This is specific to an implementation only.
+ * This property is specific to AP nodes only.
+ */
+#define	PCI_DEV_CONF_MAP_PROP	"pci-parent-indirect"
+
+/*
+ * If a bridge device provides its own config space access services,
+ * and supports a hotplug/hotswap bus below at any level, then
+ * the following property must be defined for the node either by
+ * the driver or the OBP.
+ */
+#define	PCI_BUS_CONF_MAP_PROP	"pci-conf-indirect"
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/usr/src/uts/common/sys/pcie_impl.h b/usr/src/uts/common/sys/pcie_impl.h
index 3b8ce839f1..30910e2318 100644
--- a/usr/src/uts/common/sys/pcie_impl.h
+++ b/usr/src/uts/common/sys/pcie_impl.h
@@ -51,6 +51,7 @@ extern void pcie_enable_errors(dev_info_t *dip,
 extern void pcie_disable_errors(dev_info_t *dip,
     ddi_acc_handle_t config_handle);
 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip);
+extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip);
 extern int pcie_enable_ce(dev_info_t *dip,
     ddi_acc_handle_t config_handle);
 
diff --git a/usr/src/uts/sun4/io/px/px_dma.c b/usr/src/uts/sun4/io/px/px_dma.c
index aa8f3e582d..48adba2a2e 100644
--- a/usr/src/uts/sun4/io/px/px_dma.c
+++ b/usr/src/uts/sun4/io/px/px_dma.c
@@ -117,7 +117,7 @@ px_dma_allocmp(dev_info_t *dip, dev_info_t *rdip, int (*waitfp)(caddr_t),
 	 * immediate child. As we move down the PCIe fabric, this field
 	 * may be modified by switch and bridge drivers.
 	 */
-	mp->dmai_bdf = PCI_GET_BDF(pcie_get_my_childs_dip(dip, rdip));
+	mp->dmai_bdf = pcie_get_bdf_for_dma_xfer(dip, rdip);
 
 	return (mp);
 }
diff --git a/usr/src/uts/sun4/io/px/px_intr.c b/usr/src/uts/sun4/io/px/px_intr.c
index 36c9a071bb..e83085f2d9 100644
--- a/usr/src/uts/sun4/io/px/px_intr.c
+++ b/usr/src/uts/sun4/io/px/px_intr.c
@@ -557,14 +557,14 @@ px_class_to_pil(dev_info_t *rdip)
 {
 	uint32_t pil;
 
-	/* default pil is 0 (uninitialized) */
+	/* Default pil is 1 */
 	pil = px_class_to_val(rdip,
 	    "pci-class-priorities", px_default_pil,
-	    sizeof (px_default_pil) / sizeof (px_class_val_t), 0);
+	    sizeof (px_default_pil) / sizeof (px_class_val_t), 1);
 
-	/* range check the result */
+	/* Range check the result */
 	if (pil >= 0xf)
-		pil = 0;
+		pil = 1;
 
 	return (pil);
 }
diff --git a/usr/src/uts/sun4/io/px/px_pci.c b/usr/src/uts/sun4/io/px/px_pci.c
index e8825ad99b..b156e7116a 100644
--- a/usr/src/uts/sun4/io/px/px_pci.c
+++ b/usr/src/uts/sun4/io/px/px_pci.c
@@ -92,7 +92,9 @@ static int pxb_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap,
 static int pxb_fm_err_callback(dev_info_t *dip, ddi_fm_error_t *derr,
     const void *impl_data);
 
-static int ppb_pcie_device_type(pxb_devstate_t *pxb_p);
+static int pxb_pcie_device_type(pxb_devstate_t *pxb_p);
+static void pxb_set_pci_perf_parameters(dev_info_t *dip,
+	ddi_acc_handle_t config_handle);
 #ifdef	PRINT_PLX_SEEPROM_CRC
 static void pxb_print_plx_seeprom_crc_data(pxb_devstate_t *pxb_p);
 #endif
@@ -391,7 +393,7 @@ pxb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
 	/*
 	 * Make sure the "device_type" property exists.
 	 */
-	if (ppb_pcie_device_type(pxb) == DDI_SUCCESS)
+	if (pxb_pcie_device_type(pxb) == DDI_SUCCESS)
 		(void) strcpy(device_type, "pciex");
 	else
 		(void) strcpy(device_type, "pci");
@@ -422,6 +424,8 @@ pxb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
 			    "ndi_prop_update_int() failed\n");
 			goto fail;
 		}
+
+		pxb_set_pci_perf_parameters(devi, config_handle);
 	}
 
 	/*
@@ -948,6 +952,9 @@ pxb_initchild(dev_info_t *child)
 	for (i = 0; i < pxb_tlp_count; i += 1)
 		reg |= pci_config_get16(config_handle, PCI_CONF_VENID);
 
+	if (pxb->pxb_port_type == PX_CAP_REG_DEV_TYPE_PCIE2PCI)
+		pxb_set_pci_perf_parameters(child, config_handle);
+
 	pci_config_teardown(&config_handle);
 #endif /* PX_PLX */
 
@@ -1781,7 +1788,7 @@ static int pxb_pcishpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle)
 
 /* check if this device has PCIe link underneath. */
 static int
-ppb_pcie_device_type(pxb_devstate_t *pxb_p)
+pxb_pcie_device_type(pxb_devstate_t *pxb_p)
 {
 	int port_type = pxb_p->pxb_port_type;
 
@@ -1798,6 +1805,55 @@ ppb_pcie_device_type(pxb_devstate_t *pxb_p)
 	return (DDI_FAILURE);
 }
 
+/*
+ * For PCI and PCI-X devices including PCIe2PCI bridge, initialize
+ * cache-line-size and latency timer configuration registers.
+ */
+static void
+pxb_set_pci_perf_parameters(dev_info_t *dip, ddi_acc_handle_t cfg_hdl)
+{
+	uint_t	n;
+
+	/* Initialize cache-line-size configuration register if needed */
+	if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
+	    "cache-line-size", 0) == 0) {
+		pci_config_put8(cfg_hdl, PCI_CONF_CACHE_LINESZ,
+		    PXB_CACHE_LINE_SIZE);
+		n = pci_config_get8(cfg_hdl, PCI_CONF_CACHE_LINESZ);
+		if (n != 0) {
+			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
+			    "cache-line-size", n);
+		}
+	}
+
+	/* Initialize latency timer configuration registers if needed */
+	if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
+	    "latency-timer", 0) == 0) {
+		uchar_t	min_gnt, latency_timer;
+		uchar_t header_type;
+
+		/* Determine the configuration header type */
+		header_type = pci_config_get8(cfg_hdl, PCI_CONF_HEADER);
+
+		if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) {
+			latency_timer = PXB_LATENCY_TIMER;
+			pci_config_put8(cfg_hdl, PCI_BCNF_LATENCY_TIMER,
+			    latency_timer);
+		} else {
+			min_gnt = pci_config_get8(cfg_hdl, PCI_CONF_MIN_G);
+			latency_timer = min_gnt * 8;
+		}
+
+		pci_config_put8(cfg_hdl, PCI_CONF_LATENCY_TIMER,
+		    latency_timer);
+		n = pci_config_get8(cfg_hdl, PCI_CONF_LATENCY_TIMER);
+		if (n != 0) {
+			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
+			    "latency-timer", n);
+		}
+	}
+}
+
 #ifdef	PRINT_PLX_SEEPROM_CRC
 static void
 pxb_print_plx_seeprom_crc_data(pxb_devstate_t *pxb_p)
@@ -1925,7 +1981,6 @@ pxb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
 	if ((ret = ddi_dma_allochdl(dip, rdip, attr_p, waitfp, arg,
 	    handlep)) == DDI_SUCCESS) {
 		ddi_dma_impl_t	*mp = (ddi_dma_impl_t *)*handlep;
-		dev_info_t	*cdip = pcie_get_my_childs_dip(dip, rdip);
 #ifdef	BCM_SW_WORKAROUNDS
 		mp->dmai_inuse |= PX_DMAI_FLAGS_MAP_BUFZONE;
 #endif	/* BCM_SW_WORKAROUNDS */
@@ -1934,8 +1989,7 @@ pxb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
 		 * of px_pci's immediate child or secondary bus-id of the
 		 * PCIe2PCI bridge.
 		 */
-		mp->dmai_minxfer = PCI_GET_SEC_BUS(cdip) ?
-		    PCI_GET_SEC_BUS(cdip) : PCI_GET_BDF(cdip);
+		mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip);
 	}
 
 	return (ret);
diff --git a/usr/src/uts/sun4/io/px/px_pci.h b/usr/src/uts/sun4/io/px/px_pci.h
index 862a5ee832..d276087930 100644
--- a/usr/src/uts/sun4/io/px/px_pci.h
+++ b/usr/src/uts/sun4/io/px/px_pci.h
@@ -199,6 +199,13 @@ extern void *pxb_state;
 
 #endif	/* BCM_SW_WORKAROUNDS */
 
+/*
+ * The following values are used to initialize the cache line size
+ * and latency timer registers for PCI, PCI-X and PCIe2PCI devices.
+ */
+#define	PXB_CACHE_LINE_SIZE	0x10	/* 64 bytes in # of DWORDs */
+#define	PXB_LATENCY_TIMER	0x40	/* 64 PCI cycles */
+
 #ifdef	__cplusplus
 }
 #endif
diff --git a/usr/src/uts/sun4u/io/pci/pci_intr.c b/usr/src/uts/sun4u/io/pci/pci_intr.c
index 3f4e6dfded..492601fd67 100644
--- a/usr/src/uts/sun4u/io/pci/pci_intr.c
+++ b/usr/src/uts/sun4u/io/pci/pci_intr.c
@@ -475,14 +475,14 @@ pci_class_to_pil(dev_info_t *rdip)
 {
 	uint32_t pil;
 
-	/* default pil is 0 (uninitialized) */
+	/* Default pil is 1 */
 	pil = pci_class_to_val(rdip,
 	    "pci-class-priorities", pci_default_pil,
-	    sizeof (pci_default_pil) / sizeof (pci_class_val_t), 0);
+	    sizeof (pci_default_pil) / sizeof (pci_class_val_t), 1);
 
-	/* range check the result */
+	/* Range check the result */
 	if (pil >= 0xf)
-		pil = 0;
+		pil = 1;
 
 	return (pil);
 }