12135 ECRC PCIe errors shouldn't be fatal

12136 Want hook to disable PCIe link monitoring
12134 Capture PCIe aspm status
Reviewed by: John Levon <john.levon@joyent.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Garrett D'Amore <garrett@damore.org>

3 files changed, 67 insertions, 4 deletions

diff --git a/usr/src/uts/common/io/pciex/pcie.c b/usr/src/uts/common/io/pciex/pcie.c
index 4eff14d563..22f191943c 100644
--- a/usr/src/uts/common/io/pciex/pcie.c
+++ b/usr/src/uts/common/io/pciex/pcie.c
@@ -145,6 +145,13 @@ int pcie_max_mps = PCIE_DEVCTL_MAX_PAYLOAD_4096 >> 5;
 int pcie_disable_ari = 0;
 
 /*
+ * On some platforms, such as the AMD B450 chipset, we've seen an odd
+ * relationship between enabling link bandwidth notifications and AERs about
+ * ECRC errors. This provides a mechanism to disable it.
+ */
+int pcie_disable_lbw = 0;
+
+/*
  * Amount of time to wait for an in-progress retraining. The default is to try
  * 500 times in 10ms chunks, thus a total of 5s.
  */
@@ -559,6 +566,56 @@ pcie_determine_serial(dev_info_t *dip)
 	    serial, sizeof (serial));
 }
 
+static void
+pcie_determine_aspm(dev_info_t *dip)
+{
+	pcie_bus_t	*bus_p = PCIE_DIP2BUS(dip);
+	uint32_t	linkcap;
+	uint16_t	linkctl;
+
+	if (!PCIE_IS_PCIE(bus_p))
+		return;
+
+	linkcap = PCIE_CAP_GET(32, bus_p, PCIE_LINKCAP);
+	linkctl = PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL);
+
+	switch (linkcap & PCIE_LINKCAP_ASPM_SUP_MASK) {
+	case PCIE_LINKCAP_ASPM_SUP_L0S:
+		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
+		    "pcie-aspm-support", "l0s");
+		break;
+	case PCIE_LINKCAP_ASPM_SUP_L1:
+		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
+		    "pcie-aspm-support", "l1");
+		break;
+	case PCIE_LINKCAP_ASPM_SUP_L0S_L1:
+		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
+		    "pcie-aspm-support", "l0s,l1");
+		break;
+	default:
+		return;
+	}
+
+	switch (linkctl & PCIE_LINKCTL_ASPM_CTL_MASK) {
+	case PCIE_LINKCTL_ASPM_CTL_DIS:
+		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
+		    "pcie-aspm-state", "disabled");
+		break;
+	case PCIE_LINKCTL_ASPM_CTL_L0S:
+		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
+		    "pcie-aspm-state", "l0s");
+		break;
+	case PCIE_LINKCTL_ASPM_CTL_L1:
+		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
+		    "pcie-aspm-state", "l1");
+		break;
+	case PCIE_LINKCTL_ASPM_CTL_L0S_L1:
+		(void) ndi_prop_update_string(DDI_DEV_T_NONE, dip,
+		    "pcie-aspm-state", "l0s,l1");
+		break;
+	}
+}
+
 /*
  * PCI-Express child device initialization.
  * This function enables generic pci-express interrupts and error
@@ -704,6 +761,8 @@ pcie_initchild(dev_info_t *cdip)
 
 		pcie_determine_serial(cdip);
 
+		pcie_determine_aspm(cdip);
+
 		pcie_capture_speeds(cdip);
 	}
 
@@ -2852,6 +2911,10 @@ pcie_link_bw_enable(dev_info_t *dip)
 	uint16_t linkctl;
 	pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
 
+	if (pcie_disable_lbw != 0) {
+		return (DDI_FAILURE);
+	}
+
 	if (!pcie_link_bw_supported(dip)) {
 		return (DDI_FAILURE);
 	}
diff --git a/usr/src/uts/common/io/pciex/pcie_fault.c b/usr/src/uts/common/io/pciex/pcie_fault.c
index 6a335db3e2..90563c1d1a 100644
--- a/usr/src/uts/common/io/pciex/pcie_fault.c
+++ b/usr/src/uts/common/io/pciex/pcie_fault.c
@@ -1207,7 +1207,7 @@ const pf_fab_err_tbl_t pcie_pcie_tbl[] = {
 	{PCIE_AER_UCE_MTLP,	pf_panic,
 	    PF_AFFECTED_PARENT, 0},
 
-	{PCIE_AER_UCE_ECRC,	pf_panic,
+	{PCIE_AER_UCE_ECRC,	pf_no_panic,
 	    PF_AFFECTED_SELF, 0},
 
 	{PCIE_AER_UCE_UR,	pf_analyse_ca_ur,
@@ -1248,7 +1248,7 @@ const pf_fab_err_tbl_t pcie_rp_tbl[] = {
 	    PF_AFFECTED_SELF | PF_AFFECTED_AER,
 	    PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN},
 
-	{PCIE_AER_UCE_ECRC,	pf_panic,
+	{PCIE_AER_UCE_ECRC,	pf_no_panic,
 	    PF_AFFECTED_AER, PF_AFFECTED_CHILDREN},
 
 	{PCIE_AER_UCE_UR,	pf_no_panic,
@@ -1289,7 +1289,7 @@ const pf_fab_err_tbl_t pcie_sw_tbl[] = {
 	    PF_AFFECTED_SELF | PF_AFFECTED_AER,
 	    PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN},
 
-	{PCIE_AER_UCE_ECRC,	pf_panic,
+	{PCIE_AER_UCE_ECRC,	pf_no_panic,
 	    PF_AFFECTED_AER, PF_AFFECTED_SELF | PF_AFFECTED_CHILDREN},
 
 	{PCIE_AER_UCE_UR,	pf_analyse_ca_ur,
diff --git a/usr/src/uts/common/io/pciex/pcieb.c b/usr/src/uts/common/io/pciex/pcieb.c
index c9d65748bb..d81a12b6c0 100644
--- a/usr/src/uts/common/io/pciex/pcieb.c
+++ b/usr/src/uts/common/io/pciex/pcieb.c
@@ -122,7 +122,7 @@
  * changes to the negotiated link bandwidth. These events are managed by
  * enabling support for the interrupts in the PCI Express Capability Structure.
  * This is all taken care of by the pcie driver through functions like
- * pcie_link_bw_enabled().
+ * pcie_link_bw_enable().
  *
  * The second aspect of link management the pcieb driver enables is the ability
  * to retrain the link and optionally limit the speed. This is enabled through a