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-rw-r--r--usr/src/pkgdefs/SUNWagp/postinstall5
-rw-r--r--usr/src/pkgdefs/SUNWdrmr/postinstall6
-rw-r--r--usr/src/uts/common/sys/agp/agpdefs.h8
-rw-r--r--usr/src/uts/intel/io/agpgart/agptarget.c11
-rw-r--r--usr/src/uts/intel/io/agpmaster/agpmaster.c13
-rw-r--r--usr/src/uts/intel/io/drm/drm_pciids.h6
-rw-r--r--usr/src/uts/intel/io/drm/i915_dma.c16
-rw-r--r--usr/src/uts/intel/io/drm/i915_drv.c25
-rw-r--r--usr/src/uts/intel/io/drm/i915_drv.h43
-rw-r--r--usr/src/uts/intel/io/drm/i915_irq.c4
10 files changed, 97 insertions, 40 deletions
diff --git a/usr/src/pkgdefs/SUNWagp/postinstall b/usr/src/pkgdefs/SUNWagp/postinstall
index c7727afec9..13858091e1 100644
--- a/usr/src/pkgdefs/SUNWagp/postinstall
+++ b/usr/src/pkgdefs/SUNWagp/postinstall
@@ -24,8 +24,6 @@
# Copyright 2008 Sun Microsystems, Inc. All rights reserved.
# Use is subject to license terms.
#
-#ident "%Z%%M% %I% %E% SMI"
-#
# SUNWagp postinstall script
PATH=/usr/bin:/usr/sbin:${PATH}
@@ -53,6 +51,9 @@ BRALIAS="\
\"pci8086,2a00\" \
\"pci8086,2a10\" \
\"pci8086,2a40\" \
+ \"pci8086,2e00\" \
+ \"pci8086,2e10\" \
+ \"pci8086,2e20\" \
\"pci8086,1130\" \
"
CPUGART='"pci1022,1103"'
diff --git a/usr/src/pkgdefs/SUNWdrmr/postinstall b/usr/src/pkgdefs/SUNWdrmr/postinstall
index 7bd01bf716..1155b58923 100644
--- a/usr/src/pkgdefs/SUNWdrmr/postinstall
+++ b/usr/src/pkgdefs/SUNWdrmr/postinstall
@@ -23,8 +23,6 @@
# Copyright 2008 Sun Microsystems, Inc. All rights reserved.
# Use is subject to license terms.
#
-# ident "%Z%%M% %I% %E% SMI"
-#
# SUNWdrmr postinstall script
PATH=/usr/bin:/usr/sbin:${PATH}
@@ -48,6 +46,10 @@ IGFX_ALIAS="\
\"pci8086,29d2\" \
\"pci8086,2a02\" \
\"pci8086,2a12\" \
+ \"pci8086,2a42\" \
+ \"pci8086,2e02.8086.2e02\" \
+ \"pci8086,2e12\" \
+ \"pci8086,2e22\" \
"
DRVPERM='* 0644 root sys'
diff --git a/usr/src/uts/common/sys/agp/agpdefs.h b/usr/src/uts/common/sys/agp/agpdefs.h
index ba27284320..0ddc082389 100644
--- a/usr/src/uts/common/sys/agp/agpdefs.h
+++ b/usr/src/uts/common/sys/agp/agpdefs.h
@@ -27,8 +27,6 @@
#ifndef _SYS_AGPDEFS_H
#define _SYS_AGPDEFS_H
-#pragma ident "%Z%%M% %I% %E% SMI"
-
#ifdef __cplusplus
extern "C" {
#endif
@@ -100,6 +98,9 @@ extern "C" {
#define INTEL_BR_G33 0x29c08086
#define INTEL_BR_Q33 0x29d08086
#define INTEL_BR_GM45 0x2a408086
+#define INTEL_BR_EL 0x2e008086
+#define INTEL_BR_Q45 0x2e108086
+#define INTEL_BR_G45 0x2e208086
/* AGP common register offset in pci configuration space */
#define AGP_CONF_MISC 0x51 /* one byte */
@@ -164,6 +165,9 @@ extern "C" {
#define INTEL_IGD_G33 0x29c28086
#define INTEL_IGD_Q33 0x29d28086
#define INTEL_IGD_GM45 0x2a428086
+#define INTEL_IGD_EL 0x2e028086
+#define INTEL_IGD_Q45 0x2e128086
+#define INTEL_IGD_G45 0x2e228086
/* register offsets in PCI config space */
#define I8XX_CONF_GMADR 0x10 /* GMADR of i8xx series */
diff --git a/usr/src/uts/intel/io/agpgart/agptarget.c b/usr/src/uts/intel/io/agpgart/agptarget.c
index c93adafaef..131353f577 100644
--- a/usr/src/uts/intel/io/agpgart/agptarget.c
+++ b/usr/src/uts/intel/io/agpgart/agptarget.c
@@ -320,6 +320,9 @@ static int gms_965GM[7] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16),
GMS_MB(32), GMS_MB(48), GMS_MB(64)};
static int gms_X33[9] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16),
GMS_MB(32), GMS_MB(48), GMS_MB(64), GMS_MB(128), GMS_MB(256)};
+static int gms_G4X[13] = {0, 0, 0, 0,
+ GMS_MB(32), GMS_MB(48), GMS_MB(64), GMS_MB(128), GMS_MB(256),
+ GMS_MB(96), GMS_MB(160), GMS_MB(224), GMS_MB(352)};
static gms_mode_t gms_modes[] = {
{INTEL_BR_810, I810_CONF_SMRAM, I810_GMS_MASK,
@@ -363,7 +366,13 @@ static gms_mode_t gms_modes[] = {
{INTEL_BR_Q33, I8XX_CONF_GC, IX33_GC_MODE_MASK,
GMS_SIZE(gms_X33), gms_X33},
{INTEL_BR_GM45, I8XX_CONF_GC, I8XX_GC_MODE_MASK,
- GMS_SIZE(gms_965GM), gms_965GM}
+ GMS_SIZE(gms_965GM), gms_965GM},
+ {INTEL_BR_EL, I8XX_CONF_GC, I8XX_GC_MODE_MASK,
+ GMS_SIZE(gms_G4X), gms_G4X},
+ {INTEL_BR_Q45, I8XX_CONF_GC, I8XX_GC_MODE_MASK,
+ GMS_SIZE(gms_G4X), gms_G4X},
+ {INTEL_BR_G45, I8XX_CONF_GC, I8XX_GC_MODE_MASK,
+ GMS_SIZE(gms_G4X), gms_G4X}
};
static int
get_chip_gms(uint32_t devid)
diff --git a/usr/src/uts/intel/io/agpmaster/agpmaster.c b/usr/src/uts/intel/io/agpmaster/agpmaster.c
index 7ab4db4fcf..55d448d56c 100644
--- a/usr/src/uts/intel/io/agpmaster/agpmaster.c
+++ b/usr/src/uts/intel/io/agpmaster/agpmaster.c
@@ -101,13 +101,18 @@ int agpm_debug = 0;
(agpmaster->agpm_id == INTEL_IGD_965G2) || \
(agpmaster->agpm_id == INTEL_IGD_965GM) || \
(agpmaster->agpm_id == INTEL_IGD_965GME) || \
- (agpmaster->agpm_id == INTEL_IGD_GM45))
+ (agpmaster->agpm_id == INTEL_IGD_GM45) || \
+ IS_INTEL_G4X(agpmaster))
/* Intel G33 series */
#define IS_INTEL_X33(agpmaster) ((agpmaster->agpm_id == INTEL_IGD_Q35) || \
(agpmaster->agpm_id == INTEL_IGD_G33) || \
(agpmaster->agpm_id == INTEL_IGD_Q33))
+/* Intel G4X series */
+#define IS_INTEL_G4X(agpmaster) ((agpmaster->agpm_id == INTEL_IGD_EL) || \
+ (agpmaster->agpm_id == INTEL_IGD_Q45) || \
+ (agpmaster->agpm_id == INTEL_IGD_G45))
static struct modlmisc modlmisc = {
&mod_miscops, "AGP master interfaces"
@@ -301,7 +306,8 @@ set_gtt_mmio(dev_info_t *devi, agp_master_softc_t *agpmaster,
&MMIO_BASE(agpmaster), 0, 0, &i8xx_dev_access,
&MMIO_HANDLE(agpmaster));
CHECK_STATUS(status);
- if (agpmaster->agpm_id == INTEL_IGD_GM45)
+ if ((agpmaster->agpm_id == INTEL_IGD_GM45) ||
+ IS_INTEL_G4X(agpmaster))
GTT_ADDR(agpmaster) =
MMIO_BASE(agpmaster) + GM45_GTT_OFFSET;
else
@@ -637,6 +643,9 @@ detect_i8xx_device(agp_master_softc_t *master_softc)
case INTEL_IGD_G33:
case INTEL_IGD_Q33:
case INTEL_IGD_GM45:
+ case INTEL_IGD_EL:
+ case INTEL_IGD_Q45:
+ case INTEL_IGD_G45:
master_softc->agpm_dev_type = DEVICE_IS_I830;
break;
default: /* unknown id */
diff --git a/usr/src/uts/intel/io/drm/drm_pciids.h b/usr/src/uts/intel/io/drm/drm_pciids.h
index 7667d18c5a..1951899485 100644
--- a/usr/src/uts/intel/io/drm/drm_pciids.h
+++ b/usr/src/uts/intel/io/drm/drm_pciids.h
@@ -7,8 +7,6 @@
* Use is subject to license terms.
*/
-#pragma ident "%Z%%M% %I% %E% SMI"
-
#ifndef _DRM_PCIIDS_H_
#define _DRM_PCIIDS_H_
@@ -203,6 +201,10 @@ extern "C" {
{0x8086, 0x29C2, CHIP_I9XX|CHIP_I915, "Intel G33"}, \
{0x8086, 0x29B2, CHIP_I9XX|CHIP_I915, "Intel Q35"}, \
{0x8086, 0x29D2, CHIP_I9XX|CHIP_I915, "Intel Q33"}, \
+ {0x8086, 0x2A42, CHIP_I9XX|CHIP_I965, "Intel GM45"}, \
+ {0x8086, 0x2E02, CHIP_I9XX|CHIP_I965, "Intel EL"}, \
+ {0x8086, 0x2E12, CHIP_I9XX|CHIP_I965, "Intel Q45"}, \
+ {0x8086, 0x2E22, CHIP_I9XX|CHIP_I965, "Intel G45"}, \
{0, 0, 0, NULL}
#ifdef __cplusplus
diff --git a/usr/src/uts/intel/io/drm/i915_dma.c b/usr/src/uts/intel/io/drm/i915_dma.c
index cf1326a5da..e9960dd020 100644
--- a/usr/src/uts/intel/io/drm/i915_dma.c
+++ b/usr/src/uts/intel/io/drm/i915_dma.c
@@ -33,8 +33,6 @@
* Use is subject to license terms.
*/
-#pragma ident "%Z%%M% %I% %E% SMI"
-
#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
@@ -194,7 +192,7 @@ static int i915_initialize(drm_device_t * dev,
dev_priv->allow_batchbuffer = 1;
- if (!IS_G33(dev)) {
+ if (!I915_NEED_GFX_HWS(dev)) {
/* Program Hardware Status Page */
dev_priv->status_page_dmah =
drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
@@ -253,7 +251,10 @@ static int i915_dma_resume(drm_device_t * dev)
}
DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
- I915_WRITE(0x02080, dev_priv->dma_status_page);
+ if (!I915_NEED_GFX_HWS(dev))
+ I915_WRITE(0x02080, dev_priv->dma_status_page);
+ else
+ I915_WRITE(0x02080, dev_priv->status_gfx_addr);
DRM_DEBUG("Enabled hardware status page\n");
return 0;
@@ -458,7 +459,7 @@ static void i915_emit_breadcrumb(drm_device_t *dev)
BEGIN_LP_RING(4);
OUT_RING(CMD_STORE_DWORD_IDX);
- OUT_RING(20);
+ OUT_RING(BREADCRUMB_OFFSET << 2);
OUT_RING(dev_priv->counter);
OUT_RING(0);
ADVANCE_LP_RING();
@@ -605,7 +606,7 @@ static int i915_dispatch_flip(drm_device_t * dev)
BEGIN_LP_RING(4);
OUT_RING(CMD_STORE_DWORD_IDX);
- OUT_RING(20);
+ OUT_RING(BREADCRUMB_OFFSET << 2);
OUT_RING(dev_priv->counter);
OUT_RING(0);
ADVANCE_LP_RING();
@@ -850,6 +851,9 @@ static int i915_set_status_page(DRM_IOCTL_ARGS)
drm_i915_private_t *dev_priv = dev->dev_private;
drm_i915_hws_addr_t hws;
+ if (!I915_NEED_GFX_HWS(dev))
+ return (EINVAL);
+
if (!dev_priv) {
DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
return (EINVAL);
diff --git a/usr/src/uts/intel/io/drm/i915_drv.c b/usr/src/uts/intel/io/drm/i915_drv.c
index e9fbe666c8..5d0e2cd313 100644
--- a/usr/src/uts/intel/io/drm/i915_drv.c
+++ b/usr/src/uts/intel/io/drm/i915_drv.c
@@ -327,7 +327,7 @@ i915_save_vga(struct drm_device *dev)
/* CRT controller regs */
i915_write_indexed(&regmap, cr_index, cr_data, 0x11,
i915_read_indexed(&regmap, cr_index, cr_data, 0x11) & (~0x80));
- for (i = 0; i < 0x24; i++)
+ for (i = 0; i <= 0x24; i++)
s3_priv->saveCR[i] =
i915_read_indexed(&regmap, cr_index, cr_data, i);
/* Make sure we don't turn off CR group 0 writes */
@@ -336,7 +336,7 @@ i915_save_vga(struct drm_device *dev)
/* Attribute controller registers */
(void) vga_reg_get8(&regmap, st01);
s3_priv->saveAR_INDEX = vga_reg_get8(&regmap, VGA_AR_INDEX);
- for (i = 0; i < 20; i++)
+ for (i = 0; i <= 0x14; i++)
s3_priv->saveAR[i] = i915_read_ar(&regmap, st01, i, 0);
(void) vga_reg_get8(&regmap, st01);
vga_reg_put8(&regmap, VGA_AR_INDEX, s3_priv->saveAR_INDEX);
@@ -403,7 +403,7 @@ i915_restore_vga(struct drm_device *dev)
/* Enable CR group 0 writes */
i915_write_indexed(&regmap, cr_index, cr_data,
0x11, s3_priv->saveCR[0x11]);
- for (i = 0; i < 0x24; i++)
+ for (i = 0; i <= 0x24; i++)
i915_write_indexed(&regmap, cr_index,
cr_data, i, s3_priv->saveCR[i]);
@@ -421,7 +421,7 @@ i915_restore_vga(struct drm_device *dev)
/* Attribute controller registers */
(void) vga_reg_get8(&regmap, st01); /* switch back to index mode */
- for (i = 0; i < 20; i++)
+ for (i = 0; i <= 0x14; i++)
i915_write_ar(&regmap, st01, i, s3_priv->saveAR[i], 0);
(void) vga_reg_get8(&regmap, st01); /* switch back to index mode */
vga_reg_put8(&regmap, VGA_AR_INDEX, s3_priv->saveAR_INDEX | 0x20);
@@ -453,6 +453,9 @@ i915_resume(struct drm_device *dev)
* see pci_pre_resume for detail.
*/
pci_config_put8(conf_hdl, LBB, s3_priv->saveLBB);
+
+ S3_WRITE(DSPARB, s3_priv->saveDSPARB);
+
/*
* Pipe & plane A info
* Prime the clock
@@ -570,7 +573,8 @@ i915_resume(struct drm_device *dev)
drv_usecwait(150);
/* Clock gating state */
- S3_WRITE (DSPCLK_GATE_D, s3_priv->saveDSPCLK_GATE_D);
+ S3_WRITE (D_STATE, s3_priv->saveD_STATE);
+ S3_WRITE (CG_2D_DIS, s3_priv->saveCG_2D_DIS);
/* Cache mode state */
S3_WRITE (CACHE_MODE_0, s3_priv->saveCACHE_MODE_0 | 0xffff0000);
@@ -612,6 +616,9 @@ i915_suspend(struct drm_device *dev)
*/
s3_priv->saveLBB = pci_config_get8(conf_hdl, LBB);
+ /* Display arbitration control */
+ s3_priv->saveDSPARB = S3_READ(DSPARB);
+
/*
* Pipe & plane A info.
*/
@@ -665,7 +672,7 @@ i915_suspend(struct drm_device *dev)
s3_priv->saveDSPBSIZE = S3_READ(DSPBSIZE);
s3_priv->saveDSPBPOS = S3_READ(DSPBPOS);
s3_priv->saveDSPBBASE = S3_READ(DSPBBASE);
- if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
+ if (IS_I965GM(dev) || IS_GM45(dev)) {
s3_priv->saveDSPBSURF = S3_READ(DSPBSURF);
s3_priv->saveDSPBTILEOFF = S3_READ(DSPBTILEOFF);
}
@@ -713,7 +720,8 @@ i915_suspend(struct drm_device *dev)
s3_priv->saveVGACNTRL = S3_READ(VGACNTRL);
/* Clock gating state */
- s3_priv->saveDSPCLK_GATE_D = S3_READ(DSPCLK_GATE_D);
+ s3_priv->saveD_STATE = S3_READ(D_STATE);
+ s3_priv->saveCG_2D_DIS = S3_READ(CG_2D_DIS);
/* Cache mode state */
s3_priv->saveCACHE_MODE_0 = S3_READ(CACHE_MODE_0);
@@ -763,7 +771,8 @@ i915_map_regs(dev_info_t *dip, caddr_t *save_addr, ddi_acc_handle_t *handlep)
for (rnumber = 1; rnumber < nregs; rnumber++) {
(void) ddi_dev_regsize(dip, rnumber, &size);
if ((size == 0x80000) ||
- (size == 0x100000))
+ (size == 0x100000) ||
+ (size == 0x400000))
break;
}
diff --git a/usr/src/uts/intel/io/drm/i915_drv.h b/usr/src/uts/intel/io/drm/i915_drv.h
index 913bcc002e..95f5804be9 100644
--- a/usr/src/uts/intel/io/drm/i915_drv.h
+++ b/usr/src/uts/intel/io/drm/i915_drv.h
@@ -37,8 +37,6 @@
#ifndef _I915_DRV_H
#define _I915_DRV_H
-#pragma ident "%Z%%M% %I% %E% SMI"
-
/* General customization:
*/
@@ -102,6 +100,7 @@ typedef struct s3_i915_private {
uint8_t saveLBB;
uint32_t saveDSPACNTR;
uint32_t saveDSPBCNTR;
+ uint32_t saveDSPARB;
uint32_t savePIPEACONF;
uint32_t savePIPEBCONF;
uint32_t savePIPEASRC;
@@ -168,7 +167,8 @@ typedef struct s3_i915_private {
uint32_t saveIER;
uint32_t saveIIR;
uint32_t saveIMR;
- uint32_t saveDSPCLK_GATE_D;
+ uint32_t saveD_STATE;
+ uint32_t saveCG_2D_DIS;
uint32_t saveMI_ARB_STATE;
uint32_t savePIPEASTAT;
uint32_t savePIPEBSTAT;
@@ -178,12 +178,12 @@ typedef struct s3_i915_private {
uint32_t saveSWF2[3];
uint8_t saveMSR;
uint8_t saveSR[8];
- uint8_t saveGR[24];
+ uint8_t saveGR[25];
uint8_t saveAR_INDEX;
- uint8_t saveAR[20];
+ uint8_t saveAR[21];
uint8_t saveDACMASK;
uint8_t saveDACDATA[256*3]; /* 256 3-byte colors */
- uint8_t saveCR[36];
+ uint8_t saveCR[37];
} s3_i915_private_t;
typedef struct drm_i915_private {
@@ -514,7 +514,8 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
-#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
+#define BREADCRUMB_OFFSET 32 /* dword offset 20h */
+#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[BREADCRUMB_OFFSET])
#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
/*
@@ -640,7 +641,10 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
#define FPB0 0x06048
#define FPB1 0x0604c
-#define DSPCLK_GATE_D 0x6200
+#define D_STATE 0x6104
+#define CG_2D_DIS 0x6200
+#define CG_3D_DIS 0x6204
+
#define MI_ARB_STATE 0x20e4
/*
@@ -814,6 +818,8 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
#define FBC_LL_SIZE (1536)
#define FBC_LL_PAD (32)
+#define DSPARB 0x70030
+
/*
* Some BIOS scratch area registers. The 845 (and 830?) store the amount
* of video memory available to the BIOS in SWF1.
@@ -846,6 +852,9 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
#define PCI_DEVICE_ID_INTEL_82Q35_IG 0x29b2
#define PCI_DEVICE_ID_INTEL_82Q33_IG 0x29d2
#define PCI_DEVICE_ID_INTEL_CANTIGA_IG 0x2a42
+#define PCI_DEVICE_ID_INTEL_EL_IG 0x2e02
+#define PCI_DEVICE_ID_INTEL_82Q45_IG 0x2e12
+#define PCI_DEVICE_ID_INTEL_82G45_IG 0x2e22
#define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC)
@@ -864,20 +873,30 @@ extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
(dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q963_IG || \
(dev)->pci_device == PCI_DEVICE_ID_INTEL_82G965_IG || \
(dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG || \
- (dev)->pci_device == PCI_DEVICE_ID_INTEL_GME965_IG)
+ (dev)->pci_device == PCI_DEVICE_ID_INTEL_GME965_IG || \
+ (dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG || \
+ (dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \
+ (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \
+ (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG)
#define IS_I965GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG)
+#define IS_GM45(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG)
+
+#define IS_G4X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \
+ (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \
+ (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG)
+
#define IS_G33(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82G33_IG || \
(dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q35_IG || \
(dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q33_IG)
#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
- IS_I945GM(dev) || IS_I965G(dev))
+ IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
- IS_I945GM(dev) || IS_I965GM(dev))
+ IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
-#define IS_IGD_GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG)
+#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
#endif /* _I915_DRV_H */
diff --git a/usr/src/uts/intel/io/drm/i915_irq.c b/usr/src/uts/intel/io/drm/i915_irq.c
index 7811799202..dd5c141c59 100644
--- a/usr/src/uts/intel/io/drm/i915_irq.c
+++ b/usr/src/uts/intel/io/drm/i915_irq.c
@@ -33,8 +33,6 @@
* Use is subject to license terms.
*/
-#pragma ident "%Z%%M% %I% %E% SMI"
-
#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
@@ -297,7 +295,7 @@ int i915_emit_irq(drm_device_t * dev)
BEGIN_LP_RING(6);
OUT_RING(CMD_STORE_DWORD_IDX);
- OUT_RING(20);
+ OUT_RING(BREADCRUMB_OFFSET << 2);
OUT_RING(dev_priv->counter);
OUT_RING(0);
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-15 17:41:35 +0000