diff options
34 files changed, 1079 insertions, 312 deletions
diff --git a/usr/src/cmd/fcinfo/printAttrs.c b/usr/src/cmd/fcinfo/printAttrs.c index 4f17f0236c..4961694526 100644 --- a/usr/src/cmd/fcinfo/printAttrs.c +++ b/usr/src/cmd/fcinfo/printAttrs.c @@ -21,6 +21,7 @@ /* * Copyright 2008 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ @@ -139,6 +140,10 @@ printPortSpeed(HBA_PORTSPEED portSpeed) { fprintf(stdout, "16Gb "); foundSpeed = 1; } + if ((portSpeed & HBA_PORTSPEED_32GBIT) == HBA_PORTSPEED_32GBIT) { + fprintf(stdout, "32Gb "); + foundSpeed = 1; + } if ((portSpeed & HBA_PORTSPEED_NOT_NEGOTIATED) == HBA_PORTSPEED_NOT_NEGOTIATED) { fprintf(stdout, "not established "); diff --git a/usr/src/lib/hbaapi/common/hbaapi.h b/usr/src/lib/hbaapi/common/hbaapi.h index b09fbc5b5a..44ad6e55ea 100644 --- a/usr/src/lib/hbaapi/common/hbaapi.h +++ b/usr/src/lib/hbaapi/common/hbaapi.h @@ -36,6 +36,10 @@ ******************************************************************************* */ +/* + * Copyright 2020 RackTop Systems, Inc. + */ + #ifdef __cplusplus extern "C" { #endif @@ -238,6 +242,7 @@ typedef HBA_UINT32 HBA_PORTSPEED; #define HBA_PORTSPEED_4GBIT 8 /* 4 GBit/sec */ #define HBA_PORTSPEED_8GBIT 16 /* 8 GBit/sec */ #define HBA_PORTSPEED_16GBIT 32 /* 16 GBit/sec */ +#define HBA_PORTSPEED_32GBIT 64 /* 32 GBit/sec */ #define HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) /* Speed not established */ diff --git a/usr/src/lib/libproc/common/Psymtab.c b/usr/src/lib/libproc/common/Psymtab.c index 3715d9b900..303755950d 100644 --- a/usr/src/lib/libproc/common/Psymtab.c +++ b/usr/src/lib/libproc/common/Psymtab.c @@ -2170,9 +2170,8 @@ Pbuild_file_symtab(struct ps_prochandle *P, file_info_t *fptr) * figure out where we might find this. Originally, GNU used the * .gnu_debuglink solely, but then they added a .note.gnu.build-id. The * build-id is some size, usually 16 or 20 bytes, often a SHA1 sum of - * the old, but not present file. All that you have to do to compare - * things is see if the sections are less, in theory saving you from - * doing lots of expensive I/O. + * parts of the original file. This is maintained across all versions of + * the subsequent file. * * For the .note.gnu.build-id, we're going to check a few things before * using it, first that the name is 4 bytes, and is GNU and that the diff --git a/usr/src/pkg/manifests/driver-network-emlxs.mf b/usr/src/pkg/manifests/driver-network-emlxs.mf index 338147c990..969c7547dd 100644 --- a/usr/src/pkg/manifests/driver-network-emlxs.mf +++ b/usr/src/pkg/manifests/driver-network-emlxs.mf @@ -21,6 +21,7 @@ # # Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. +# Copyright 2018 OmniOS Community Edition (OmniOSce) Association. # set name=pkg.fmri value=pkg:/driver/network/emlxs@$(PKGVERS) @@ -58,6 +59,7 @@ driver name=emlxs class=fibre-channel perms="* 0666 root sys" \ alias=pci10df,fd00 \ alias=pci10df,fe00 \ alias=pciex10df,e200 \ + alias=pciex10df,e300 \ alias=pciex10df,f100 \ alias=pciex10df,f111 \ alias=pciex10df,f112 \ @@ -65,6 +67,10 @@ driver name=emlxs class=fibre-channel perms="* 0666 root sys" \ alias=pciex10df,fc40 \ alias=pciex10df,fe00 \ alias=pciex10df,fe05 \ + alias=pciex117c,63 \ + alias=pciex117c,64 \ + alias=pciex117c,65 \ + alias=pciex117c,94 \ alias=pciex19a2,704 \ alias=pciex19a2,714 driver name=oce perms="* 0666 root sys" \ diff --git a/usr/src/pkg/manifests/system-test-ostest.mf b/usr/src/pkg/manifests/system-test-ostest.mf index 2c0f8e39bf..73a5235a19 100644 --- a/usr/src/pkg/manifests/system-test-ostest.mf +++ b/usr/src/pkg/manifests/system-test-ostest.mf @@ -12,7 +12,7 @@ # # Copyright (c) 2012, 2016 by Delphix. All rights reserved. # Copyright 2014, OmniTI Computer Consulting, Inc. All rights reserved. -# Copyright 2019 Joyent, Inc. +# Copyright 2020 Joyent, Inc. # set name=pkg.fmri value=pkg:/system/test/ostest@$(PKGVERS) @@ -84,6 +84,8 @@ file path=opt/os-tests/tests/sockfs/nosignal mode=0555 file path=opt/os-tests/tests/sockfs/sockpair mode=0555 file path=opt/os-tests/tests/spoof-ras mode=0555 file path=opt/os-tests/tests/stress/dladm-kstat mode=0555 +file path=opt/os-tests/tests/writev.32 mode=0555 +file path=opt/os-tests/tests/writev.64 mode=0555 license cr_Sun license=cr_Sun license lic_CDDL license=lic_CDDL depend fmri=system/io/tests type=require diff --git a/usr/src/test/os-tests/runfiles/default.run b/usr/src/test/os-tests/runfiles/default.run index 795f559c50..34c1c23625 100644 --- a/usr/src/test/os-tests/runfiles/default.run +++ b/usr/src/test/os-tests/runfiles/default.run @@ -11,7 +11,7 @@ # # Copyright (c) 2012 by Delphix. All rights reserved. -# Copyright 2019 Joyent, Inc. +# Copyright 2020 Joyent, Inc. # [DEFAULT] @@ -98,3 +98,6 @@ arch = i86pc [/opt/os-tests/tests/uccid] arch = i86pc tests = ['atrparse'] + +[/opt/os-tests/tests/writev.32] +[/opt/os-tests/tests/writev.64] diff --git a/usr/src/test/os-tests/tests/Makefile b/usr/src/test/os-tests/tests/Makefile index a0a5592ef1..e42bdea1fa 100644 --- a/usr/src/test/os-tests/tests/Makefile +++ b/usr/src/test/os-tests/tests/Makefile @@ -11,7 +11,7 @@ # # Copyright (c) 2012, 2016 by Delphix. All rights reserved. -# Copyright 2019 Joyent, Inc. +# Copyright 2020 Joyent, Inc. # SUBDIRS_i386 = i386 imc @@ -34,7 +34,8 @@ SUBDIRS = \ PROGS = \ odirectory \ - OS-6097 + OS-6097 \ + writev CPPFLAGS += -D_REENTRANT PROGS32 = $(PROGS:%=%.32) @@ -51,6 +52,10 @@ odirectory.64 := LDLIBS64 += -lsocket OS-6097.32 := LDLIBS += -ldlpi OS-6097.64 := LDLIBS64 += -ldlpi +writev.32 := CPPFLAGS += -D_FILE_OFFSET_BITS=64 +writev.32 := CSTD = $(CSTD_GNU99) +writev.64 := CSTD = $(CSTD_GNU99) + include $(SRC)/cmd/Makefile.cmd all := TARGET = all diff --git a/usr/src/test/os-tests/tests/writev.c b/usr/src/test/os-tests/tests/writev.c new file mode 100644 index 0000000000..e4f4bf0a66 --- /dev/null +++ b/usr/src/test/os-tests/tests/writev.c @@ -0,0 +1,109 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2020 Joyent, Inc. + */ + +/* + * Some simple testing of the read/writev() family: specifically we're checking + * IOV_MAX == 1024, and that a large-file compiled 32-bit binary can correctly + * access certain offsets. + */ + +#include <sys/uio.h> +#include <strings.h> +#include <limits.h> +#include <unistd.h> +#include <stdlib.h> +#include <stdio.h> +#include <errno.h> +#include <err.h> + +#define ONE_GIG ((off_t)1024 * 1024 * 1024) + +#define DATA_LEN (sizeof ("data")) + +char path[] = "/var/tmp/writev_test.XXXXXX"; + +static void +cleanup(void) +{ + (void) unlink(path); +} + +int +main(int argc, char *argv[]) +{ + char data[(IOV_MAX + 1) * DATA_LEN] = ""; + struct iovec iov[IOV_MAX + 1]; + + if (IOV_MAX != 1024) + errx(EXIT_FAILURE, "IOV_MAX != 1024"); + + int fd = mkstemp(path); + + if (fd == -1) + err(EXIT_FAILURE, "failed to create file"); + + (void) atexit(cleanup); + + int ret = ftruncate(fd, ONE_GIG * 8); + + if (ret != 0) + err(EXIT_FAILURE, "failed to truncate file"); + + for (int i = 0; i < IOV_MAX + 1; i++) { + (void) strcpy(data + i * DATA_LEN, "data"); + iov[i].iov_base = data + i * 5; + iov[i].iov_len = DATA_LEN; + } + + ssize_t written = writev(fd, iov, IOV_MAX + 1); + + if (written != -1 || errno != EINVAL) + errx(EXIT_FAILURE, "writev(IOV_MAX + 1) didn't fail properly"); + + written = writev(fd, iov, IOV_MAX); + + if (written == -1) + err(EXIT_FAILURE, "writev failed"); + + bzero(data, sizeof (data)); + + ssize_t read = preadv(fd, iov, IOV_MAX, 0); + + if (read != DATA_LEN * IOV_MAX) + err(EXIT_FAILURE, "preadv failed"); + + for (int i = 0; i < IOV_MAX; i++) { + if (strcmp(data + i * DATA_LEN, "data") != 0) + errx(EXIT_FAILURE, "bad read at 0x%lx", i * DATA_LEN); + } + + /* + * Now test various "interesting" offsets. + */ + + for (off_t off = 0; off < ONE_GIG * 8; off += ONE_GIG) { + if ((written = pwritev(fd, iov, 1, off)) != DATA_LEN) + err(EXIT_FAILURE, "pwritev(0x%lx) failed", off); + } + + for (off_t off = 0; off < ONE_GIG * 8; off += ONE_GIG) { + if ((read = preadv(fd, iov, 1, off)) != DATA_LEN) + err(EXIT_FAILURE, "preadv(0x%lx) failed", off); + if (strcmp(data, "data") != 0) + errx(EXIT_FAILURE, "bad read at 0x%lx", off); + } + + return (EXIT_SUCCESS); +} diff --git a/usr/src/uts/common/io/comstar/port/fct/fct.c b/usr/src/uts/common/io/comstar/port/fct/fct.c index 9f20636a27..8e5eee5d83 100644 --- a/usr/src/uts/common/io/comstar/port/fct/fct.c +++ b/usr/src/uts/common/io/comstar/port/fct/fct.c @@ -21,6 +21,7 @@ /* * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright 2016 Nexenta Systems, Inc. All rights reserved. + * Copyright 2020 RackTop Systems, Inc. */ #include <sys/conf.h> @@ -490,6 +491,8 @@ fct_get_adapter_port_attr(fct_i_local_port_t *ilport, uint8_t *pwwn, port_attr->PortSupportedSpeed |= FC_HBA_PORTSPEED_10GBIT; if (attr->supported_speed & PORT_SPEED_16G) port_attr->PortSupportedSpeed |= FC_HBA_PORTSPEED_16GBIT; + if (attr->supported_speed & PORT_SPEED_32G) + port_attr->PortSupportedSpeed |= FC_HBA_PORTSPEED_32GBIT; switch (iport->iport_link_info.port_speed) { case PORT_SPEED_1G: port_attr->PortSpeed = FC_HBA_PORTSPEED_1GBIT; @@ -509,6 +512,9 @@ fct_get_adapter_port_attr(fct_i_local_port_t *ilport, uint8_t *pwwn, case PORT_SPEED_16G: port_attr->PortSpeed = FC_HBA_PORTSPEED_16GBIT; break; + case PORT_SPEED_32G: + port_attr->PortSpeed = FC_HBA_PORTSPEED_32GBIT; + break; default: port_attr->PortSpeed = FC_HBA_PORTSPEED_UNKNOWN; break; diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_dfc.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_dfc.c index ffc72aed32..3b3e6064b8 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_dfc.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_dfc.c @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #include <emlxs.h> @@ -1254,7 +1255,8 @@ emlxs_fcio_get_adapter_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) (fc_hba_adapter_attributes32_t *)fcio->fcio_obuf; hba_attrs->version = FC_HBA_ADAPTER_ATTRIBUTES_VERSION; - (void) strncpy(hba_attrs->Manufacturer, "Emulex", + (void) strncpy(hba_attrs->Manufacturer, + hba->model_info.manufacturer, (sizeof (hba_attrs->Manufacturer)-1)); (void) strncpy(hba_attrs->SerialNumber, vpd->serial_num, (sizeof (hba_attrs->SerialNumber)-1)); @@ -1283,8 +1285,8 @@ emlxs_fcio_get_adapter_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) (void) strncpy(hba_attrs->DriverName, DRIVER_NAME, (sizeof (hba_attrs->DriverName)-1)); hba_attrs->VendorSpecificID = - ((hba->model_info.device_id << 16) | - PCI_VENDOR_ID_EMULEX); + (hba->model_info.device_id << 16) | + hba->model_info.vendor_id; hba_attrs->NumberOfPorts = hba->num_of_ports; } else { fc_hba_adapter_attributes_t *hba_attrs; @@ -1300,7 +1302,8 @@ emlxs_fcio_get_adapter_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) (fc_hba_adapter_attributes_t *)fcio->fcio_obuf; hba_attrs->version = FC_HBA_ADAPTER_ATTRIBUTES_VERSION; - (void) strncpy(hba_attrs->Manufacturer, "Emulex", + (void) strncpy(hba_attrs->Manufacturer, + hba->model_info.manufacturer, (sizeof (hba_attrs->Manufacturer)-1)); (void) strncpy(hba_attrs->SerialNumber, vpd->serial_num, (sizeof (hba_attrs->SerialNumber)-1)); @@ -1329,8 +1332,8 @@ emlxs_fcio_get_adapter_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) (void) strncpy(hba_attrs->DriverName, DRIVER_NAME, (sizeof (hba_attrs->DriverName)-1)); hba_attrs->VendorSpecificID = - ((hba->model_info.device_id << 16) | - PCI_VENDOR_ID_EMULEX); + (hba->model_info.device_id << 16) | + hba->model_info.vendor_id; hba_attrs->NumberOfPorts = hba->num_of_ports; } @@ -1447,6 +1450,10 @@ emlxs_fcio_get_adapter_port_attrs(emlxs_port_t *port, fcio_t *fcio, port_attrs->PortSpeed = HBA_PORTSPEED_16GBIT; break; + case LA_32GHZ_LINK: + port_attrs->PortSpeed = + HBA_PORTSPEED_32GBIT; + break; default: port_attrs->PortSpeed = HBA_PORTSPEED_UNKNOWN; @@ -1463,6 +1470,10 @@ emlxs_fcio_get_adapter_port_attrs(emlxs_port_t *port, fcio_t *fcio, (sizeof (port_attrs->PortSymbolicName)-1)); /* Set the hba speed limit */ + if (vpd->link_speed & LMT_32GB_CAPABLE) { + port_attrs->PortSupportedSpeed |= + FC_HBA_PORTSPEED_32GBIT; + } if (vpd->link_speed & LMT_16GB_CAPABLE) { port_attrs->PortSupportedSpeed |= FC_HBA_PORTSPEED_16GBIT; @@ -1593,6 +1604,10 @@ emlxs_fcio_get_adapter_port_attrs(emlxs_port_t *port, fcio_t *fcio, port_attrs->PortSpeed = HBA_PORTSPEED_16GBIT; break; + case LA_32GHZ_LINK: + port_attrs->PortSpeed = + HBA_PORTSPEED_32GBIT; + break; default: port_attrs->PortSpeed = HBA_PORTSPEED_UNKNOWN; @@ -1609,6 +1624,10 @@ emlxs_fcio_get_adapter_port_attrs(emlxs_port_t *port, fcio_t *fcio, (sizeof (port_attrs->PortSymbolicName)-1)); /* Set the hba speed limit */ + if (vpd->link_speed & LMT_32GB_CAPABLE) { + port_attrs->PortSupportedSpeed |= + FC_HBA_PORTSPEED_32GBIT; + } if (vpd->link_speed & LMT_16GB_CAPABLE) { port_attrs->PortSupportedSpeed |= FC_HBA_PORTSPEED_16GBIT; @@ -2226,6 +2245,10 @@ emlxs_fcio_get_disc_port_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) port_attrs->PortSpeed = HBA_PORTSPEED_16GBIT; break; + case LA_32GHZ_LINK: + port_attrs->PortSpeed = + HBA_PORTSPEED_32GBIT; + break; } } /* public loop */ @@ -2266,6 +2289,10 @@ emlxs_fcio_get_disc_port_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) port_attrs->PortSpeed = HBA_PORTSPEED_16GBIT; break; + case LA_32GHZ_LINK: + port_attrs->PortSpeed = + HBA_PORTSPEED_32GBIT; + break; } } } @@ -2358,6 +2385,10 @@ emlxs_fcio_get_disc_port_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) port_attrs->PortSpeed = HBA_PORTSPEED_16GBIT; break; + case LA_32GHZ_LINK: + port_attrs->PortSpeed = + HBA_PORTSPEED_32GBIT; + break; } } /* public loop */ @@ -2398,6 +2429,10 @@ emlxs_fcio_get_disc_port_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) port_attrs->PortSpeed = HBA_PORTSPEED_16GBIT; break; + case LA_32GHZ_LINK: + port_attrs->PortSpeed = + HBA_PORTSPEED_32GBIT; + break; } } } @@ -2520,6 +2555,10 @@ emlxs_fcio_get_port_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) port_attrs->PortSpeed = HBA_PORTSPEED_16GBIT; break; + case LA_32GHZ_LINK: + port_attrs->PortSpeed = + HBA_PORTSPEED_32GBIT; + break; } } /* public loop */ @@ -2560,6 +2599,10 @@ emlxs_fcio_get_port_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) port_attrs->PortSpeed = HBA_PORTSPEED_16GBIT; break; + case LA_32GHZ_LINK: + port_attrs->PortSpeed = + HBA_PORTSPEED_32GBIT; + break; } } } @@ -2659,6 +2702,10 @@ emlxs_fcio_get_port_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) port_attrs->PortSpeed = HBA_PORTSPEED_16GBIT; break; + case LA_32GHZ_LINK: + port_attrs->PortSpeed = + HBA_PORTSPEED_32GBIT; + break; } } /* public loop */ @@ -2699,6 +2746,10 @@ emlxs_fcio_get_port_attrs(emlxs_port_t *port, fcio_t *fcio, int32_t mode) port_attrs->PortSpeed = HBA_PORTSPEED_16GBIT; break; + case LA_32GHZ_LINK: + port_attrs->PortSpeed = + HBA_PORTSPEED_32GBIT; + break; } } } @@ -3795,9 +3846,7 @@ emlxs_dfc_get_hbainfo(emlxs_hba_t *hba, dfc_t *dfc, int32_t mode) (sizeof (hbainfo->vpd_id)-1)); hbainfo->device_id = hba->model_info.device_id; - hbainfo->vendor_id = - ddi_get32(hba->pci_acc_handle, - (uint32_t *)(hba->pci_addr + PCI_VENDOR_ID_REGISTER)) & 0xffff; + hbainfo->vendor_id = hba->model_info.vendor_id; hbainfo->ports = hba->num_of_ports; hbainfo->port_index = vpd->port_index; @@ -3959,6 +4008,8 @@ emlxs_dfc_get_hbainfo(emlxs_hba_t *hba, dfc_t *dfc, int32_t mode) hbainfo->port_speed = HBA_PORTSPEED_10GBIT; } else if (hba->linkspeed == LA_16GHZ_LINK) { hbainfo->port_speed = HBA_PORTSPEED_16GBIT; + } else if (hba->linkspeed == LA_32GHZ_LINK) { + hbainfo->port_speed = HBA_PORTSPEED_32GBIT; } else { hbainfo->port_speed = HBA_PORTSPEED_1GBIT; } @@ -3979,6 +4030,9 @@ emlxs_dfc_get_hbainfo(emlxs_hba_t *hba, dfc_t *dfc, int32_t mode) hbainfo->active_types[0] &= ~(LE_SWAP32(0x00000020)); } + if (vpd->link_speed & LMT_32GB_CAPABLE) { + hbainfo->supported_speeds |= FC_HBA_PORTSPEED_32GBIT; + } if (vpd->link_speed & LMT_16GB_CAPABLE) { hbainfo->supported_speeds |= FC_HBA_PORTSPEED_16GBIT; } @@ -4195,6 +4249,8 @@ emlxs_dfc_get_hbastats(emlxs_hba_t *hba, dfc_t *dfc, int32_t mode) stats->link_speed = HBA_PORTSPEED_10GBIT; } else if (hba->linkspeed == LA_16GHZ_LINK) { stats->link_speed = HBA_PORTSPEED_16GBIT; + } else if (hba->linkspeed == LA_32GHZ_LINK) { + stats->link_speed = HBA_PORTSPEED_32GBIT; } else { stats->link_speed = HBA_PORTSPEED_1GBIT; } @@ -4516,7 +4572,7 @@ emlxs_set_hba_mode(emlxs_hba_t *hba, uint32_t mode) break; case DDI_DIAGDI: - if (!(hba->model_info.chip & EMLXS_LANCER_CHIP)) { + if (!(hba->model_info.chip & EMLXS_LANCER_CHIPS)) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_dfc_error_msg, "set_hba_mode: Invalid mode. mode=%x", mode); @@ -5869,11 +5925,12 @@ emlxs_dfc_send_menlo(emlxs_hba_t *hba, dfc_t *dfc, int32_t mode) "%s: csize=%d rsize=%d", emlxs_dfc_xlate(dfc->cmd), dfc->buf1_size, dfc->buf2_size); - if (hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id != PCI_VENDOR_ID_EMULEX || + hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_dfc_error_msg, - "%s: Menlo device not present. device=%x,%x", - emlxs_dfc_xlate(dfc->cmd), hba->model_info.device_id, - hba->model_info.ssdid); + "%s: Menlo device not present. device=%x,%x,%x", + emlxs_dfc_xlate(dfc->cmd), hba->model_info.vendor_id, + hba->model_info.device_id, hba->model_info.ssdid); rval = DFC_INVALID_ADAPTER; goto done; @@ -6447,7 +6504,8 @@ emlxs_fcoe_attention_thread(emlxs_hba_t *hba, if (rsp->fru_data_valid == 0) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_adapter_error_msg, "Invalid FRU data found on adapter. " - "Return adapter to Emulex for repair."); + "Return adapter to %s for repair.", + hba->model_info.manufacturer); } switch (rsp->fw_type) { @@ -8586,7 +8644,8 @@ emlxs_dfc_loopback_mode(emlxs_hba_t *hba, dfc_t *dfc, int32_t mode) } #ifdef MENLO_SUPPORT - if (hba->model_info.device_id == PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id == PCI_VENDOR_ID_EMULEX && + hba->model_info.device_id == PCI_DEVICE_ID_HORNET) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_dfc_error_msg, "%s: Menlo support detected: mode:x%x", emlxs_dfc_xlate(dfc->cmd), new_mode); @@ -8730,7 +8789,8 @@ emlxs_dfc_loopback_mode(emlxs_hba_t *hba, dfc_t *dfc, int32_t mode) "%s: Node created. node=%p", emlxs_dfc_xlate(dfc->cmd), ndlp); #ifdef MENLO_SUPPORT - if (hba->model_info.device_id == PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id == PCI_VENDOR_ID_EMULEX && + hba->model_info.device_id == PCI_DEVICE_ID_HORNET) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_dfc_error_msg, "%s: Menlo support detected: mode:x%x", emlxs_dfc_xlate(dfc->cmd), new_mode); @@ -8798,7 +8858,8 @@ done: resetdone: /* Reset the adapter */ #ifdef MENLO_SUPPORT - if (hba->model_info.device_id == PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id == PCI_VENDOR_ID_EMULEX && + hba->model_info.device_id == PCI_DEVICE_ID_HORNET) { rval = emlxs_dfc_reset_menlo(hba); diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_dump.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_dump.c index 7551489f31..b1e0c1a7de 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_dump.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_dump.c @@ -47,7 +47,8 @@ emlxs_menlo_set_mode( menlo_rsp_t *rsp_buf = NULL; uint32_t rval = 0; - if (hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id != PCI_VENDOR_ID_EMULEX || + hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { return (DFC_INVALID_ADAPTER); } @@ -110,7 +111,8 @@ emlxs_menlo_reset( menlo_rsp_t *rsp_buf = NULL; uint32_t rval = 0; - if (hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id != PCI_VENDOR_ID_EMULEX || + hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { return (DFC_INVALID_ADAPTER); } @@ -171,7 +173,8 @@ emlxs_menlo_get_cfg( menlo_cmd_t *cmd_buf = NULL; uint32_t rval = 0; - if (hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id != PCI_VENDOR_ID_EMULEX || + hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { return (DFC_INVALID_ADAPTER); } @@ -229,7 +232,8 @@ emlxs_menlo_get_logcfg( menlo_cmd_t *cmd_buf = NULL; uint32_t rval = 0; - if (hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id != PCI_VENDOR_ID_EMULEX || + hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { return (DFC_INVALID_ADAPTER); } @@ -285,7 +289,8 @@ emlxs_menlo_get_log( menlo_cmd_t *cmd_buf = NULL; uint32_t rval = 0; - if (hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id != PCI_VENDOR_ID_EMULEX || + hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { return (DFC_INVALID_ADAPTER); } @@ -340,7 +345,8 @@ emlxs_menlo_get_paniclog( menlo_cmd_t *cmd_buf = NULL; uint32_t rval = 0; - if (hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id != PCI_VENDOR_ID_EMULEX || + hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { return (DFC_INVALID_ADAPTER); } @@ -2222,7 +2228,8 @@ emlxs_dump_file_create( if (fpCeeFile) { *fpCeeFile = NULL; - if ((hba->model_info.device_id == PCI_DEVICE_ID_HORNET) || + if ((hba->model_info.vendor_id == PCI_VENDOR_ID_EMULEX && + hba->model_info.device_id == PCI_DEVICE_ID_HORNET) || (hba->model_info.chip == EMLXS_BE2_CHIP) || (hba->model_info.chip == EMLXS_BE3_CHIP)) { if ((*fpCeeFile = @@ -2277,7 +2284,8 @@ emlxs_dump_file_terminate( } if (fpCeeFile) { - if (hba->model_info.device_id == PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id == PCI_VENDOR_ID_EMULEX && + hba->model_info.device_id == PCI_DEVICE_ID_HORNET) { (void) emlxs_fprintf(fpCeeFile, "Dump File End\n"); } @@ -3262,7 +3270,8 @@ emlxs_dump_menlo_log( uint32_t PanicLogEntryCount; uint32_t PanicLogEntrySize; - if (hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id != PCI_VENDOR_ID_EMULEX || + hba->model_info.device_id != PCI_DEVICE_ID_HORNET) { return (DFC_INVALID_ADAPTER); } diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_event.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_event.c index 115bb7a43d..117fbd3377 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_event.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_event.c @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #define DEF_EVENT_STRUCT /* Needed for emlxs_events.h in emlxs_event.h */ @@ -591,6 +592,8 @@ emlxs_log_link_event(emlxs_port_t *port) *linkspeed = HBA_PORTSPEED_10GBIT; } else if (hba->linkspeed == LA_16GHZ_LINK) { *linkspeed = HBA_PORTSPEED_16GBIT; + } else if (hba->linkspeed == LA_32GHZ_LINK) { + *linkspeed = HBA_PORTSPEED_32GBIT; } else { *linkspeed = HBA_PORTSPEED_1GBIT; } diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_fcp.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_fcp.c index 84590b2868..1fe1e3a096 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_fcp.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_fcp.c @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #include <emlxs.h> @@ -1554,6 +1555,10 @@ emlxs_port_online(emlxs_port_t *vport) (void) strlcpy(linkspeed, "16Gb", sizeof (linkspeed)); state |= FC_STATE_16GBIT_SPEED; break; + case LA_32GHZ_LINK: + (void) strlcpy(linkspeed, "32Gb", sizeof (linkspeed)); + state |= FC_STATE_32GBIT_SPEED; + break; default: (void) snprintf(linkspeed, sizeof (linkspeed), "unknown(0x%x)", hba->linkspeed); diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_fct.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_fct.c index 6621c6aa28..8c6863c139 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_fct.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_fct.c @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #include <emlxs.h> @@ -1371,7 +1372,8 @@ emlxs_fct_populate_hba_details(fct_local_port_t *fct_port, emlxs_hba_t *hba = HBA; emlxs_vpd_t *vpd = &VPD; - (void) strncpy(port_attrs->manufacturer, "Emulex", + (void) strncpy(port_attrs->manufacturer, + hba->model_info.manufacturer, (sizeof (port_attrs->manufacturer)-1)); (void) strncpy(port_attrs->serial_number, vpd->serial_num, (sizeof (port_attrs->serial_number)-1)); @@ -1395,12 +1397,15 @@ emlxs_fct_populate_hba_details(fct_local_port_t *fct_port, vpd->fw_label); (void) strncpy(port_attrs->driver_name, DRIVER_NAME, (sizeof (port_attrs->driver_name)-1)); - port_attrs->vendor_specific_id = - ((hba->model_info.device_id << 16) | PCI_VENDOR_ID_EMULEX); + port_attrs->vendor_specific_id = (hba->model_info.device_id << 16) | + hba->model_info.vendor_id; port_attrs->supported_cos = LE_SWAP32(FC_NS_CLASS3); port_attrs->max_frame_size = FF_FRAME_SIZE; + if (vpd->link_speed & LMT_32GB_CAPABLE) { + port_attrs->supported_speed |= PORT_SPEED_32G; + } if (vpd->link_speed & LMT_16GB_CAPABLE) { port_attrs->supported_speed |= PORT_SPEED_16G; } @@ -2006,6 +2011,9 @@ emlxs_fct_get_link_info(fct_local_port_t *fct_port, fct_link_info_t *link) case LA_16GHZ_LINK: link->port_speed = PORT_SPEED_16G; break; + case LA_32GHZ_LINK: + link->port_speed = PORT_SPEED_32G; + break; default: link->port_speed = PORT_SPEED_UNKNOWN; break; diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c index 118f08d45f..33f9cc2053 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_hba.c @@ -22,6 +22,8 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2018 OmniOS Community Edition (OmniOSce) Association. + * Copyright 2020 RackTop Systems, Inc. */ #define EMLXS_FW_TABLE_DEF @@ -990,6 +992,11 @@ emlxs_process_link_speed(emlxs_hba_t *hba) hi = 16; } + if (vpd->link_speed & LMT_32GB_CAPABLE) { + (void) strlcat(cfg->help, ", 32=32Gb", EMLXS_CFG_HELP_SIZE); + hi = 32; + } + (void) strlcat(cfg->help, "]", EMLXS_CFG_HELP_SIZE); cfg->hi = hi; @@ -1938,6 +1945,7 @@ emlxs_init_adapter_info(emlxs_hba_t *hba) uint32_t pci_id; uint32_t cache_line; uint32_t channels; + uint16_t vendor_id; uint16_t device_id; uint16_t ssdid; uint32_t i; @@ -1950,6 +1958,7 @@ emlxs_init_adapter_info(emlxs_hba_t *hba) bcopy(&emlxs_sbus_model[0], &hba->model_info, sizeof (emlxs_model_t)); + hba->model_info.vendor_id = 0; hba->model_info.device_id = 0; return (0); @@ -1959,11 +1968,13 @@ emlxs_init_adapter_info(emlxs_hba_t *hba) pci_id = ddi_get32(hba->pci_acc_handle, (uint32_t *)(hba->pci_addr + PCI_VENDOR_ID_REGISTER)); + vendor_id = (uint16_t)pci_id; device_id = (uint16_t)(pci_id >> 16); /* Find matching adapter model */ for (i = 1; i < EMLXS_SBUS_MODEL_COUNT; i++) { - if (emlxs_sbus_model[i].device_id == device_id) { + if (emlxs_sbus_model[i].vendor_id == vendor_id && + emlxs_sbus_model[i].device_id == device_id) { bcopy(&emlxs_sbus_model[i], &hba->model_info, sizeof (emlxs_model_t)); found = 1; @@ -1976,6 +1987,7 @@ emlxs_init_adapter_info(emlxs_hba_t *hba) bcopy(&emlxs_sbus_model[0], &hba->model_info, sizeof (emlxs_model_t)); + hba->model_info.vendor_id = vendor_id; hba->model_info.device_id = device_id; return (0); @@ -1986,12 +1998,17 @@ emlxs_init_adapter_info(emlxs_hba_t *hba) bcopy(&emlxs_pci_model[0], &hba->model_info, sizeof (emlxs_model_t)); + hba->model_info.vendor_id = 0; hba->model_info.device_id = 0; return (0); } - /* Read the PCI device id */ + /* Read the PCI vendor and device id */ + vendor_id = + ddi_get16(hba->pci_acc_handle, + (uint16_t *)(hba->pci_addr + PCI_VENDOR_ID_REGISTER)); + device_id = ddi_get16(hba->pci_acc_handle, (uint16_t *)(hba->pci_addr + PCI_DEVICE_ID_REGISTER)); @@ -2010,6 +2027,10 @@ emlxs_init_adapter_info(emlxs_hba_t *hba) ddi_get32(hba->pci_acc_handle, (uint32_t *)(hba->pci_addr + PCI_CACHE_LINE_REGISTER)); + EMLXS_MSGF(EMLXS_CONTEXT, + &emlxs_init_debug_msg, "Device IDs: %x/%x/%x/%x", + vendor_id, device_id, ssdid, cache_line); + /* Check for the multifunction bit being set */ if ((cache_line & 0x00ff0000) == 0x00800000) { channels = EMLXS_MULTI_CHANNEL; @@ -2021,11 +2042,11 @@ emlxs_init_adapter_info(emlxs_hba_t *hba) if (device_id != ssdid) { /* * Find matching adapter model using - * device_id, ssdid, and channels + * vendor_id, device_id, ssdid, and channels */ for (i = 1; i < emlxs_pci_model_count; i++) { - if (emlxs_pci_model[i].device_id == - device_id && + if (emlxs_pci_model[i].vendor_id == vendor_id && + emlxs_pci_model[i].device_id == device_id && emlxs_pci_model[i].ssdid == ssdid && emlxs_pci_model[i].channels == channels) { @@ -2042,10 +2063,11 @@ emlxs_init_adapter_info(emlxs_hba_t *hba) if (!found) { /* * Find matching adapter model using - * device_id and channels + * vendor_id, device_id and channels */ for (i = 1; i < emlxs_pci_model_count; i++) { - if (emlxs_pci_model[i].device_id == device_id && + if (emlxs_pci_model[i].vendor_id == vendor_id && + emlxs_pci_model[i].device_id == device_id && emlxs_pci_model[i].channels == channels) { bcopy(&emlxs_pci_model[i], &hba->model_info, @@ -2060,10 +2082,11 @@ emlxs_init_adapter_info(emlxs_hba_t *hba) if (!found) { /* * Find matching adapter model using - * device_id only + * vendor_id and device_id only */ for (i = 1; i < emlxs_pci_model_count; i++) { - if (emlxs_pci_model[i].device_id == device_id) { + if (emlxs_pci_model[i].vendor_id == vendor_id && + emlxs_pci_model[i].device_id == device_id) { bcopy(&emlxs_pci_model[i], &hba->model_info, sizeof (emlxs_model_t)); @@ -2078,6 +2101,7 @@ emlxs_init_adapter_info(emlxs_hba_t *hba) bcopy(&emlxs_pci_model[0], &hba->model_info, sizeof (emlxs_model_t)); + hba->model_info.vendor_id = vendor_id; hba->model_info.device_id = device_id; hba->model_info.ssdid = ssdid; diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_mbox.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_mbox.c index cbd0eb4091..7ddfa4fb57 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_mbox.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_mbox.c @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #include <emlxs.h> @@ -991,7 +992,7 @@ emlxs_mb_mq_create_ext(emlxs_hba_t *hba, MAILBOXQ *mbq) case 1: default: mb4->un.varSLIConfig.be.payload_length = - sizeof (IOCTL_COMMON_MQ_CREATE) + IOCTL_HEADER_SZ; + sizeof (IOCTL_COMMON_MQ_CREATE_EXT_V1) + IOCTL_HEADER_SZ; mb4->un.varSLIConfig.be.un_hdr.hdr_req.subsystem = IOCTL_SUBSYSTEM_COMMON; mb4->un.varSLIConfig.be.un_hdr.hdr_req.opcode = @@ -1591,7 +1592,8 @@ emlxs_read_la_mbcmpl(emlxs_hba_t *hba, MAILBOXQ *mbq) if ((la.attType == AT_LINK_UP) && (hba->state < FC_LINK_UP)) { #ifdef MENLO_SUPPORT - if ((hba->model_info.device_id == PCI_DEVICE_ID_HORNET) && + if (hba->model_info.vendor_id == PCI_VENDOR_ID_EMULEX && + hba->model_info.device_id == PCI_DEVICE_ID_HORNET && (hba->flag & (FC_ILB_MODE | FC_ELB_MODE))) { la.topology = TOPOLOGY_LOOP; la.granted_AL_PA = 0; @@ -1661,8 +1663,8 @@ emlxs_read_la_mbcmpl(emlxs_hba_t *hba, MAILBOXQ *mbq) } #ifdef MENLO_SUPPORT /* Check if Menlo maintenance mode is enabled */ - if (hba->model_info.device_id == - PCI_DEVICE_ID_HORNET) { + if (hba->model_info.vendor_id == PCI_VENDOR_ID_EMULEX && + hba->model_info.device_id == PCI_DEVICE_ID_HORNET) { if (la.mm == 1) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_link_atten_msg, @@ -2140,39 +2142,38 @@ emlxs_mb_init_link(emlxs_hba_t *hba, MAILBOXQ *mbq, uint32_t topology, break; case 1: - if (!(vpd->link_speed & LMT_1GB_CAPABLE)) { - linkspeed = 0; - } + linkspeed = (vpd->link_speed & LMT_1GB_CAPABLE) == 0 ? 0 : + LINK_SPEED_1G; break; case 2: - if (!(vpd->link_speed & LMT_2GB_CAPABLE)) { - linkspeed = 0; - } + linkspeed = (vpd->link_speed & LMT_2GB_CAPABLE) == 0 ? 0 : + LINK_SPEED_2G; break; case 4: - if (!(vpd->link_speed & LMT_4GB_CAPABLE)) { - linkspeed = 0; - } + linkspeed = (vpd->link_speed & LMT_4GB_CAPABLE) == 0 ? 0 : + LINK_SPEED_4G; break; case 8: - if (!(vpd->link_speed & LMT_8GB_CAPABLE)) { - linkspeed = 0; - } + linkspeed = (vpd->link_speed & LMT_8GB_CAPABLE) == 0 ? 0 : + LINK_SPEED_8G; break; case 10: - if (!(vpd->link_speed & LMT_10GB_CAPABLE)) { - linkspeed = 0; - } + linkspeed = (vpd->link_speed & LMT_10GB_CAPABLE) == 0 ? 0 : + LINK_SPEED_10G; break; case 16: - if (!(vpd->link_speed & LMT_16GB_CAPABLE)) { - linkspeed = 0; - } + linkspeed = (vpd->link_speed & LMT_16GB_CAPABLE) == 0 ? 0 : + LINK_SPEED_16G; + break; + + case 32: + linkspeed = (vpd->link_speed & LMT_32GB_CAPABLE) == 0 ? 0 : + LINK_SPEED_32G; break; default: diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_mem.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_mem.c index 6824682adc..d66150b488 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_mem.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_mem.c @@ -22,6 +22,8 @@ /* * Copyright (c) 2004-2011 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2018 OmniOS Community Edition (OmniOSce) Association. + * Copyright 2020 RackTop Systems, Inc. */ #include <emlxs.h> @@ -161,6 +163,42 @@ emlxs_mem_alloc_buffer(emlxs_hba_t *hba) seg->fc_step = 1; break; + case MEM_SGL1K: + (void) strlcpy(seg->fc_label, "1K SGL Pool", + sizeof (seg->fc_label)); + seg->fc_memtag = MEM_SGL1K; + seg->fc_memsize = 0x400; + seg->fc_memflag = FC_MBUF_DMA | FC_MBUF_SNGLSG; + seg->fc_memalign = 32; + seg->fc_hi_water = 0x5000; + seg->fc_lo_water = 0; + seg->fc_step = 0x100; + break; + + case MEM_SGL2K: + (void) strlcpy(seg->fc_label, "2K SGL Pool", + sizeof (seg->fc_label)); + seg->fc_memtag = MEM_SGL2K; + seg->fc_memsize = 0x800; + seg->fc_memflag = FC_MBUF_DMA | FC_MBUF_SNGLSG; + seg->fc_memalign = 32; + seg->fc_hi_water = 0x5000; + seg->fc_lo_water = 0; + seg->fc_step = 0x100; + break; + + case MEM_SGL4K: + (void) strlcpy(seg->fc_label, "4K SGL Pool", + sizeof (seg->fc_label)); + seg->fc_memtag = MEM_SGL4K; + seg->fc_memsize = 0x1000; + seg->fc_memflag = FC_MBUF_DMA | FC_MBUF_SNGLSG; + seg->fc_memalign = 32; + seg->fc_hi_water = 0x5000; + seg->fc_lo_water = 0; + seg->fc_step = 0x100; + break; + #ifdef SFCT_SUPPORT case MEM_FCTBUF: /* These are the unsolicited FCT buffers. */ @@ -708,7 +746,7 @@ emlxs_mem_pool_create(emlxs_hba_t *hba, MEMSEG *seg) seg->fc_total_memsize = 0; seg->fc_low = 0; - (void) emlxs_mem_pool_alloc(hba, seg, seg->fc_lo_water); + (void) emlxs_mem_pool_alloc(hba, seg, seg->fc_lo_water); seg->fc_memflag |= (FC_MEMSEG_PUT_ENABLED|FC_MEMSEG_GET_ENABLED); @@ -1038,7 +1076,7 @@ emlxs_mem_buf_alloc(emlxs_hba_t *hba, uint32_t size) bzero(buf_info, sizeof (MBUF_INFO)); buf_info->size = size; - buf_info->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG | FC_MBUF_DMA32; + buf_info->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG; buf_info->align = 32; (void) emlxs_mem_alloc(hba, buf_info); @@ -1053,7 +1091,7 @@ emlxs_mem_buf_alloc(emlxs_hba_t *hba, uint32_t size) buf_info->virt = (void *)mp; emlxs_mem_free(hba, buf_info); - return (0); + return (NULL); } bp = (uint8_t *)buf_info->virt; bzero(bp, buf_info->size); diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli3.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli3.c index 8756d1a642..532df73c5f 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli3.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli3.c @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #include <emlxs.h> @@ -309,7 +310,8 @@ reset: /* Check for PEGASUS (This is a special case) */ /* We need to check for dual channel adapter */ - if (hba->model_info.device_id == PCI_DEVICE_ID_PEGASUS) { + if (hba->model_info.vendor_id == PCI_VENDOR_ID_EMULEX && + hba->model_info.device_id == PCI_DEVICE_ID_PEGASUS) { /* Try to determine if this is a DC adapter */ if (emlxs_get_max_sram(hba, &MaxRbusSize, &MaxIbusSize) == 0) { if (MaxRbusSize == REDUCED_SRAM_CFG) { @@ -684,9 +686,10 @@ reset: if (hba->model_info.flags & EMLXS_NOT_SUPPORTED) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg, "Unsupported adapter found. " - "Id:%d Device id:0x%x SSDID:0x%x Model:%s", - hba->model_info.id, hba->model_info.device_id, - hba->model_info.ssdid, hba->model_info.model); + "Id:%d Vendor id:0x%x Device id:0x%x SSDID:0x%x " + "Model:%s", hba->model_info.id, hba->model_info.vendor_id, + hba->model_info.device_id, hba->model_info.ssdid, + hba->model_info.model); rval = EIO; goto failed; @@ -1795,7 +1798,7 @@ emlxs_sli3_map_hdw(emlxs_hba_t *hba) bzero(buf_info, sizeof (MBUF_INFO)); buf_info->size = SLI_SLIM2_SIZE; buf_info->flags = - FC_MBUF_DMA | FC_MBUF_SNGLSG | FC_MBUF_DMA32; + FC_MBUF_DMA | FC_MBUF_SNGLSG; buf_info->align = ddi_ptob(dip, 1L); (void) emlxs_mem_alloc(hba, buf_info); diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli4.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli4.c index 9919203788..71fb94f318 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli4.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_sli4.c @@ -22,6 +22,8 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2018 OmniOS Community Edition (OmniOSce) Association. + * Copyright 2020 RackTop Systems, Inc. */ #include <emlxs.h> @@ -40,15 +42,22 @@ static uint32_t emlxs_sli4_read_sema(emlxs_hba_t *hba); static uint32_t emlxs_sli4_read_mbdb(emlxs_hba_t *hba); -static void emlxs_sli4_write_mbdb(emlxs_hba_t *hba, uint32_t value); +static void emlxs_sli4_write_mbdb(emlxs_hba_t *hba, uint64_t phys, + boolean_t high); -static void emlxs_sli4_write_wqdb(emlxs_hba_t *hba, uint32_t value); +static void emlxs_sli4_write_wqdb(emlxs_hba_t *hba, uint16_t qid, + uint_t posted, uint_t index); -static void emlxs_sli4_write_mqdb(emlxs_hba_t *hba, uint32_t value); +static void emlxs_sli4_write_mqdb(emlxs_hba_t *hba, uint16_t qid, + uint_t count); -static void emlxs_sli4_write_rqdb(emlxs_hba_t *hba, uint32_t value); +static void emlxs_sli4_write_rqdb(emlxs_hba_t *hba, uint16_t qid, + uint_t count); -static void emlxs_sli4_write_cqdb(emlxs_hba_t *hba, uint32_t value); +static void emlxs_sli4_write_eqdb(emlxs_hba_t *hba, uint16_t qid, + uint32_t count, boolean_t arm); +static void emlxs_sli4_write_cqdb(emlxs_hba_t *hba, uint16_t qid, + uint32_t count, boolean_t arm); static int emlxs_sli4_create_queues(emlxs_hba_t *hba, MAILBOXQ *mbq); @@ -123,7 +132,7 @@ static void emlxs_sli4_timer_check_mbox(emlxs_hba_t *hba); static void emlxs_sli4_poll_erratt(emlxs_hba_t *hba); -extern XRIobj_t *emlxs_sli4_reserve_xri(emlxs_port_t *port, +extern XRIobj_t *emlxs_sli4_reserve_xri(emlxs_port_t *port, RPIobj_t *rpip, uint32_t type, uint16_t rx_id); static int emlxs_check_hdw_ready(emlxs_hba_t *); @@ -344,8 +353,7 @@ emlxs_sli4_online(emlxs_hba_t *hba) /* Initialize the local dump region buffer */ bzero(&hba->sli.sli4.dump_region, sizeof (MBUF_INFO)); hba->sli.sli4.dump_region.size = EMLXS_DUMP_REGION_SIZE; - hba->sli.sli4.dump_region.flags = FC_MBUF_DMA | FC_MBUF_SNGLSG - | FC_MBUF_DMA32; + hba->sli.sli4.dump_region.flags = FC_MBUF_DMA | FC_MBUF_SNGLSG; hba->sli.sli4.dump_region.align = ddi_ptob(hba->dip, 1L); (void) emlxs_mem_alloc(hba, &hba->sli.sli4.dump_region); @@ -537,7 +545,7 @@ reset: vpd->feaLevelLow = mb->un.varRdRev4.feaLevelLow; /* Decode FW labels */ - if (hba->model_info.chip == EMLXS_LANCER_CHIP) { + if ((hba->model_info.chip & EMLXS_LANCER_CHIPS) != 0) { bcopy(vpd->postKernName, vpd->sli4FwName, 16); } emlxs_decode_label(vpd->sli4FwName, vpd->sli4FwName, 0, @@ -556,6 +564,9 @@ reset: } else if (hba->model_info.chip == EMLXS_LANCER_CHIP) { (void) strlcpy(vpd->sli4FwLabel, "xe201.grp", sizeof (vpd->sli4FwLabel)); + } else if (hba->model_info.chip == EMLXS_LANCERG6_CHIP) { + (void) strlcpy(vpd->sli4FwLabel, "xe501.grp", + sizeof (vpd->sli4FwLabel)); } else { (void) strlcpy(vpd->sli4FwLabel, "sli4.fw", sizeof (vpd->sli4FwLabel)); @@ -703,9 +714,10 @@ reset: if (hba->model_info.flags & EMLXS_NOT_SUPPORTED) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg, "Unsupported adapter found. " - "Id:%d Device id:0x%x SSDID:0x%x Model:%s", - hba->model_info.id, hba->model_info.device_id, - hba->model_info.ssdid, hba->model_info.model); + "Id:%d Vendor id:0x%x Device id:0x%x SSDID:0x%x " + "Model:%s", hba->model_info.id, hba->model_info.vendor_id, + hba->model_info.device_id, hba->model_info.ssdid, + hba->model_info.model); rval = EIO; goto failed1; @@ -1360,13 +1372,18 @@ reset: bzero(mbq, sizeof (MAILBOXQ)); /* + * Interupts are enabled, start the timeout timers now. + */ + emlxs_timer_start(hba); + + /* * Setup and issue mailbox INITIALIZE LINK command * At this point, the interrupt will be generated by the HW */ emlxs_mb_init_link(hba, mbq, cfg[CFG_TOPOLOGY].current, cfg[CFG_LINK_SPEED].current); - rval = emlxs_sli4_issue_mbox_cmd(hba, mbq, MBX_NOWAIT, 0); + rval = emlxs_sli4_issue_mbox_cmd(hba, mbq, MBX_WAIT, 0); if ((rval != MBX_SUCCESS) && (rval != MBX_BUSY)) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg, "Unable to initialize link. " @@ -1374,7 +1391,7 @@ reset: mb->mbxCommand, mb->mbxStatus); rval = EIO; - goto failed3; + goto failed4; } /* Wait for link to come up */ @@ -1388,7 +1405,7 @@ reset: mb->mbxStatus); rval = EIO; - goto failed3; + goto failed4; } BUSYWAIT_MS(1000); @@ -1407,6 +1424,9 @@ done: } return (0); +failed4: + emlxs_timer_stop(hba); + failed3: EMLXS_STATE_CHANGE(hba, FC_ERROR); @@ -1620,8 +1640,7 @@ emlxs_sli4_map_hdw(emlxs_hba_t *hba) bzero(buf_info, sizeof (MBUF_INFO)); buf_info->size = EMLXS_BOOTSTRAP_MB_SIZE + MBOX_EXTENSION_SIZE; - buf_info->flags = - FC_MBUF_DMA | FC_MBUF_SNGLSG | FC_MBUF_DMA32; + buf_info->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG; buf_info->align = ddi_ptob(dip, 1L); (void) emlxs_mem_alloc(hba, buf_info); @@ -1935,17 +1954,32 @@ emlxs_sli4_read_mbdb(emlxs_hba_t *hba) static void -emlxs_sli4_write_mbdb(emlxs_hba_t *hba, uint32_t value) +emlxs_sli4_write_mbdb(emlxs_hba_t *hba, uint64_t phys, boolean_t high) { + uint32_t db; + uint_t shift; + + /* + * The bootstrap mailbox is posted as 2 x 30 bit values. + * It is required to be 16 bit aligned, and the 2 low order + * bits are used as flags. + */ + shift = high ? 32 : 2; + + db = (uint32_t)(phys >> shift) & BMBX_ADDR; + + if (high) + db |= BMBX_ADDR_HI; + switch (hba->sli_intf & SLI_INTF_IF_TYPE_MASK) { case SLI_INTF_IF_TYPE_0: ddi_put32(hba->sli.sli4.bar2_acc_handle, - hba->sli.sli4.MBDB_reg_addr, value); + hba->sli.sli4.MBDB_reg_addr, db); break; case SLI_INTF_IF_TYPE_2: ddi_put32(hba->sli.sli4.bar0_acc_handle, - hba->sli.sli4.MBDB_reg_addr, value); + hba->sli.sli4.MBDB_reg_addr, db); break; } @@ -1953,35 +1987,123 @@ emlxs_sli4_write_mbdb(emlxs_hba_t *hba, uint32_t value) static void -emlxs_sli4_write_cqdb(emlxs_hba_t *hba, uint32_t value) +emlxs_sli4_write_eqdb(emlxs_hba_t *hba, uint16_t qid, uint32_t count, + boolean_t arm) { + uint32_t db; + + /* + * Add the qid to the doorbell. It is split into a low and + * high component. + */ + + /* Initialize with the low bits */ + db = qid & EQ_DB_ID_LO_MASK; + + /* drop the low bits */ + qid >>= EQ_ID_LO_BITS; + + /* Add the high bits */ + db |= (qid << EQ_DB_ID_HI_SHIFT) & EQ_DB_ID_HI_MASK; + + /* + * Include the number of entries to be popped. + */ + db |= (count << EQ_DB_POP_SHIFT) & EQ_DB_POP_MASK; + + /* The doorbell is for an event queue */ + db |= EQ_DB_EVENT; + + /* Arm if asked to do so */ + if (arm) + db |= EQ_DB_CLEAR | EQ_DB_REARM; + +#ifdef DEBUG_FASTPATH + EMLXS_MSGF(&hba->port[0], _FILENO_, __LINE__, &emlxs_sli_detail_msg, + "EQE: CLEAR db=%08x pops=%d", db, count); +#endif /* DEBUG_FASTPATH */ + switch (hba->sli_intf & SLI_INTF_IF_TYPE_MASK) { case SLI_INTF_IF_TYPE_0: + /* The CQDB_reg_addr is also use for EQs */ ddi_put32(hba->sli.sli4.bar2_acc_handle, - hba->sli.sli4.CQDB_reg_addr, value); + hba->sli.sli4.CQDB_reg_addr, db); break; case SLI_INTF_IF_TYPE_2: + /* The CQDB_reg_addr is also use for EQs */ ddi_put32(hba->sli.sli4.bar0_acc_handle, - hba->sli.sli4.CQDB_reg_addr, value); + hba->sli.sli4.CQDB_reg_addr, db); break; } +} /* emlxs_sli4_write_eqdb() */ + +static void +emlxs_sli4_write_cqdb(emlxs_hba_t *hba, uint16_t qid, uint32_t count, + boolean_t arm) +{ + uint32_t db; + + /* + * Add the qid to the doorbell. It is split into a low and + * high component. + */ + + /* Initialize with the low bits */ + db = qid & CQ_DB_ID_LO_MASK; + + /* drop the low bits */ + qid >>= CQ_ID_LO_BITS; + + /* Add the high bits */ + db |= (qid << CQ_DB_ID_HI_SHIFT) & CQ_DB_ID_HI_MASK; + + /* + * Include the number of entries to be popped. + */ + db |= (count << CQ_DB_POP_SHIFT) & CQ_DB_POP_MASK; + + /* Arm if asked to do so */ + if (arm) + db |= CQ_DB_REARM; + +#ifdef DEBUG_FASTPATH + EMLXS_MSGF(&hba->port[0], _FILENO_, __LINE__, &emlxs_sli_detail_msg, + "CQE: CLEAR db=%08x: pops=%d", db, count); +#endif /* DEBUG_FASTPATH */ + + switch (hba->sli_intf & SLI_INTF_IF_TYPE_MASK) { + case SLI_INTF_IF_TYPE_0: + ddi_put32(hba->sli.sli4.bar2_acc_handle, + hba->sli.sli4.CQDB_reg_addr, db); + break; + case SLI_INTF_IF_TYPE_2: + ddi_put32(hba->sli.sli4.bar0_acc_handle, + hba->sli.sli4.CQDB_reg_addr, db); + break; + } } /* emlxs_sli4_write_cqdb() */ static void -emlxs_sli4_write_rqdb(emlxs_hba_t *hba, uint32_t value) +emlxs_sli4_write_rqdb(emlxs_hba_t *hba, uint16_t qid, uint_t count) { + emlxs_rqdbu_t rqdb; + + rqdb.word = 0; + rqdb.db.Qid = qid; + rqdb.db.NumPosted = count; + switch (hba->sli_intf & SLI_INTF_IF_TYPE_MASK) { case SLI_INTF_IF_TYPE_0: ddi_put32(hba->sli.sli4.bar2_acc_handle, - hba->sli.sli4.RQDB_reg_addr, value); + hba->sli.sli4.RQDB_reg_addr, rqdb.word); break; case SLI_INTF_IF_TYPE_2: ddi_put32(hba->sli.sli4.bar0_acc_handle, - hba->sli.sli4.RQDB_reg_addr, value); + hba->sli.sli4.RQDB_reg_addr, rqdb.word); break; } @@ -1989,17 +2111,22 @@ emlxs_sli4_write_rqdb(emlxs_hba_t *hba, uint32_t value) static void -emlxs_sli4_write_mqdb(emlxs_hba_t *hba, uint32_t value) +emlxs_sli4_write_mqdb(emlxs_hba_t *hba, uint16_t qid, uint_t count) { + uint32_t db; + + db = qid; + db |= (count << MQ_DB_POP_SHIFT) & MQ_DB_POP_MASK; + switch (hba->sli_intf & SLI_INTF_IF_TYPE_MASK) { case SLI_INTF_IF_TYPE_0: ddi_put32(hba->sli.sli4.bar2_acc_handle, - hba->sli.sli4.MQDB_reg_addr, value); + hba->sli.sli4.MQDB_reg_addr, db); break; case SLI_INTF_IF_TYPE_2: ddi_put32(hba->sli.sli4.bar0_acc_handle, - hba->sli.sli4.MQDB_reg_addr, value); + hba->sli.sli4.MQDB_reg_addr, db); break; } @@ -2007,20 +2134,31 @@ emlxs_sli4_write_mqdb(emlxs_hba_t *hba, uint32_t value) static void -emlxs_sli4_write_wqdb(emlxs_hba_t *hba, uint32_t value) +emlxs_sli4_write_wqdb(emlxs_hba_t *hba, uint16_t qid, uint_t posted, + uint_t index) { + uint32_t db; + + db = qid; + db |= (posted << WQ_DB_POST_SHIFT) & WQ_DB_POST_MASK; + db |= (index << WQ_DB_IDX_SHIFT) & WQ_DB_IDX_MASK; + switch (hba->sli_intf & SLI_INTF_IF_TYPE_MASK) { case SLI_INTF_IF_TYPE_0: ddi_put32(hba->sli.sli4.bar2_acc_handle, - hba->sli.sli4.WQDB_reg_addr, value); + hba->sli.sli4.WQDB_reg_addr, db); break; case SLI_INTF_IF_TYPE_2: ddi_put32(hba->sli.sli4.bar0_acc_handle, - hba->sli.sli4.WQDB_reg_addr, value); + hba->sli.sli4.WQDB_reg_addr, db); break; } +#ifdef DEBUG_FASTPATH + EMLXS_MSGF(&hba->port[0], _FILENO_, __LINE__, &emlxs_sli_detail_msg, + "WQ RING: %08x", db); +#endif /* DEBUG_FASTPATH */ } /* emlxs_sli4_write_wqdb() */ @@ -2081,7 +2219,6 @@ emlxs_issue_bootstrap_mb(emlxs_hba_t *hba, uint32_t tmo) { emlxs_port_t *port = &PPORT; uint32_t *iptr; - uint32_t addr30; /* * This routine assumes the bootstrap mbox is loaded @@ -2089,9 +2226,7 @@ emlxs_issue_bootstrap_mb(emlxs_hba_t *hba, uint32_t tmo) * * First, load the high 30 bits of bootstrap mailbox */ - addr30 = (uint32_t)((hba->sli.sli4.bootstrapmb.phys>>32) & 0xfffffffc); - addr30 |= BMBX_ADDR_HI; - emlxs_sli4_write_mbdb(hba, addr30); + emlxs_sli4_write_mbdb(hba, hba->sli.sli4.bootstrapmb.phys, B_TRUE); tmo = emlxs_check_bootstrap_ready(hba, tmo); if (tmo == 0) { @@ -2099,8 +2234,7 @@ emlxs_issue_bootstrap_mb(emlxs_hba_t *hba, uint32_t tmo) } /* Load the low 30 bits of bootstrap mailbox */ - addr30 = (uint32_t)((hba->sli.sli4.bootstrapmb.phys>>2) & 0xfffffffc); - emlxs_sli4_write_mbdb(hba, addr30); + emlxs_sli4_write_mbdb(hba, hba->sli.sli4.bootstrapmb.phys, B_FALSE); tmo = emlxs_check_bootstrap_ready(hba, tmo); if (tmo == 0) { @@ -2555,7 +2689,7 @@ emlxs_sli4_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp) wqe = &iocbq->wqe; pkt = PRIV2PKT(sbp); xrip = sbp->xrip; - sge = xrip->SGList.virt; + sge = xrip->SGList->virt; #if (EMLXS_MODREV >= EMLXS_MODREV3) cp_cmd = pkt->pkt_cmd_cookie; @@ -2705,7 +2839,7 @@ emlxs_sli4_fct_bde_setup(emlxs_port_t *port, emlxs_buf_t *sbp) return (1); } - sge = xrip->SGList.virt; + sge = xrip->SGList->virt; if (iocb->ULPCOMMAND == CMD_FCP_TRECEIVE64_CX) { @@ -2839,7 +2973,6 @@ emlxs_sli4_issue_iocb_cmd(emlxs_hba_t *hba, CHANNEL *cp, IOCBQ *iocbq) emlxs_wqe_t *wqeslot; WQ_DESC_t *wq; uint32_t flag; - uint32_t wqdb; uint16_t next_wqe; off_t offset; #ifdef NODE_THROTTLE_SUPPORT @@ -3075,23 +3208,15 @@ sendit: EMLXS_MPDATA_SYNC(wq->addr.dma_handle, offset, 4096, DDI_DMA_SYNC_FORDEV); - /* Ring the WQ Doorbell */ - wqdb = wq->qid; - wqdb |= ((1 << 24) | (wq->host_index << 16)); - /* * After this, the sbp / iocb / wqe should not be * accessed in the xmit path. */ - emlxs_sli4_write_wqdb(hba, wqdb); + /* Ring the WQ Doorbell */ + emlxs_sli4_write_wqdb(hba, wq->qid, 1, wq->host_index); wq->host_index = next_wqe; -#ifdef DEBUG_FASTPATH - EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, - "WQ RING: %08x", wqdb); -#endif /* DEBUG_FASTPATH */ - if (!sbp) { emlxs_mem_put(hba, MEM_IOCB, (void *)iocbq); } @@ -3148,7 +3273,6 @@ emlxs_sli4_issue_mq(emlxs_port_t *port, MAILBOX4 *mqe, MAILBOX *mb, MAILBOX4 *mb4; MATCHMAP *mp; uint32_t *iptr; - uint32_t mqdb; off_t offset; mbq = (MAILBOXQ *)mb; @@ -3212,15 +3336,12 @@ emlxs_sli4_issue_mq(emlxs_port_t *port, MAILBOX4 *mqe, MAILBOX *mb, } /* Ring the MQ Doorbell */ - mqdb = hba->sli.sli4.mq.qid; - mqdb |= ((1 << MQ_DB_POP_SHIFT) & MQ_DB_POP_MASK); - if (mb->mbxCommand != MBX_HEARTBEAT) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, - "MQ RING: %08x", mqdb); + "MQ RING: Qid %04x", hba->sli.sli4.mq.qid); } - emlxs_sli4_write_mqdb(hba, mqdb); + emlxs_sli4_write_mqdb(hba, hba->sli.sli4.mq.qid, 1); return (MBX_SUCCESS); @@ -3988,7 +4109,7 @@ emlxs_sli4_prep_fct_iocb(emlxs_port_t *port, emlxs_buf_t *cmd_sbp, int channel) sge_size = (sge_size + 3) & 0xfffffffc; } sge_addr = cp_cmd->dmac_laddress; - sge = xrip->SGList.virt; + sge = xrip->SGList->virt; stage_sge.addrHigh = PADDR_HI(sge_addr); stage_sge.addrLow = PADDR_LO(sge_addr); @@ -4180,7 +4301,6 @@ emlxs_sli4_prep_fcp_iocb(emlxs_port_t *port, emlxs_buf_t *sbp, int channel) NODELIST *node; uint16_t iotag; uint32_t did; - off_t offset; pkt = PRIV2PKT(sbp); did = LE_SWAP24_LO(pkt->pkt_cmd_fhdr.d_id); @@ -4242,22 +4362,18 @@ emlxs_sli4_prep_fcp_iocb(emlxs_port_t *port, emlxs_buf_t *sbp, int channel) /* DEBUG */ #ifdef DEBUG_FCP EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, - "FCP: SGLaddr virt %p phys %p size %d", xrip->SGList.virt, - xrip->SGList.phys, pkt->pkt_datalen); - emlxs_data_dump(port, "FCP: SGL", (uint32_t *)xrip->SGList.virt, 20, 0); + "FCP: SGLaddr virt %p phys %p size %d", xrip->SGList->virt, + xrip->SGList->phys, pkt->pkt_datalen); + emlxs_data_dump(port, "FCP: SGL", + (uint32_t *)xrip->SGList->virt, 20, 0); EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, "FCP: CMD virt %p len %d:%d:%d", pkt->pkt_cmd, pkt->pkt_cmdlen, pkt->pkt_rsplen, pkt->pkt_datalen); emlxs_data_dump(port, "FCP: CMD", (uint32_t *)pkt->pkt_cmd, 10, 0); #endif /* DEBUG_FCP */ - offset = (off_t)((uint64_t)((unsigned long) - xrip->SGList.virt) - - (uint64_t)((unsigned long) - hba->sli.sli4.slim2.virt)); - - EMLXS_MPDATA_SYNC(xrip->SGList.dma_handle, offset, - xrip->SGList.size, DDI_DMA_SYNC_FORDEV); + EMLXS_MPDATA_SYNC(xrip->SGList->dma_handle, 0, + xrip->SGList->size, DDI_DMA_SYNC_FORDEV); /* if device is FCP-2 device, set the following bit */ /* that says to run the FC-TAPE protocol. */ @@ -4342,7 +4458,6 @@ emlxs_sli4_prep_els_iocb(emlxs_port_t *port, emlxs_buf_t *sbp) ddi_dma_cookie_t *cp_cmd; ddi_dma_cookie_t *cp_resp; emlxs_node_t *node; - off_t offset; pkt = PRIV2PKT(sbp); did = LE_SWAP24_LO(pkt->pkt_cmd_fhdr.d_id); @@ -4436,7 +4551,7 @@ emlxs_sli4_prep_els_iocb(emlxs_port_t *port, emlxs_buf_t *sbp) sge->last = 1; /* Now sge is fully staged */ - sge = xrip->SGList.virt; + sge = xrip->SGList->virt; BE_SWAP32_BCOPY((uint8_t *)&stage_sge, (uint8_t *)sge, sizeof (ULP_SGE64)); @@ -4501,7 +4616,7 @@ emlxs_sli4_prep_els_iocb(emlxs_port_t *port, emlxs_buf_t *sbp) sge->last = 0; - sge = xrip->SGList.virt; + sge = xrip->SGList->virt; BE_SWAP32_BCOPY((uint8_t *)&stage_sge, (uint8_t *)sge, sizeof (ULP_SGE64)); @@ -4517,19 +4632,19 @@ emlxs_sli4_prep_els_iocb(emlxs_port_t *port, emlxs_buf_t *sbp) sge->last = 1; /* Now sge is fully staged */ - sge = xrip->SGList.virt; + sge = xrip->SGList->virt; sge++; BE_SWAP32_BCOPY((uint8_t *)&stage_sge, (uint8_t *)sge, sizeof (ULP_SGE64)); #ifdef DEBUG_ELS EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, "ELS: SGLaddr virt %p phys %p", - xrip->SGList.virt, xrip->SGList.phys); + xrip->SGList->virt, xrip->SGList->phys); EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, "ELS: PAYLOAD virt %p phys %p", pkt->pkt_cmd, cp_cmd->dmac_laddress); - emlxs_data_dump(port, "ELS: SGL", (uint32_t *)xrip->SGList.virt, - 12, 0); + emlxs_data_dump(port, "ELS: SGL", + (uint32_t *)xrip->SGList->virt, 12, 0); #endif /* DEBUG_ELS */ switch (cmd) { @@ -4635,13 +4750,8 @@ emlxs_sli4_prep_els_iocb(emlxs_port_t *port, emlxs_buf_t *sbp) } } - offset = (off_t)((uint64_t)((unsigned long) - xrip->SGList.virt) - - (uint64_t)((unsigned long) - hba->sli.sli4.slim2.virt)); - - EMLXS_MPDATA_SYNC(xrip->SGList.dma_handle, offset, - xrip->SGList.size, DDI_DMA_SYNC_FORDEV); + EMLXS_MPDATA_SYNC(xrip->SGList->dma_handle, 0, + xrip->SGList->size, DDI_DMA_SYNC_FORDEV); if (pkt->pkt_cmd_fhdr.f_ctl & F_CTL_CHAINED_SEQ) { wqe->CCPE = 1; @@ -4680,7 +4790,6 @@ emlxs_sli4_prep_ct_iocb(emlxs_port_t *port, emlxs_buf_t *sbp) RPIobj_t *rpip; XRIobj_t *xrip; uint32_t did; - off_t offset; pkt = PRIV2PKT(sbp); did = LE_SWAP24_LO(pkt->pkt_cmd_fhdr.d_id); @@ -4832,9 +4941,9 @@ emlxs_sli4_prep_ct_iocb(emlxs_port_t *port, emlxs_buf_t *sbp) #ifdef DEBUG_CT EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, - "CT: SGLaddr virt %p phys %p", xrip->SGList.virt, - xrip->SGList.phys); - emlxs_data_dump(port, "CT: SGL", (uint32_t *)xrip->SGList.virt, + "CT: SGLaddr virt %p phys %p", xrip->SGList->virt, + xrip->SGList->phys); + emlxs_data_dump(port, "CT: SGL", (uint32_t *)xrip->SGList->virt, 12, 0); EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, "CT: CMD virt %p len %d:%d", @@ -4858,13 +4967,8 @@ emlxs_sli4_prep_ct_iocb(emlxs_port_t *port, emlxs_buf_t *sbp) iocb->un.genreq64.w5.hcsw.Dfctl = pkt->pkt_cmd_fhdr.df_ctl; iocb->ULPPU = 1; /* Wd4 is relative offset */ - offset = (off_t)((uint64_t)((unsigned long) - xrip->SGList.virt) - - (uint64_t)((unsigned long) - hba->sli.sli4.slim2.virt)); - - EMLXS_MPDATA_SYNC(xrip->SGList.dma_handle, offset, - xrip->SGList.size, DDI_DMA_SYNC_FORDEV); + EMLXS_MPDATA_SYNC(xrip->SGList->dma_handle, 0, + xrip->SGList->size, DDI_DMA_SYNC_FORDEV); wqe->ContextTag = rpip->RPI; wqe->ContextType = WQE_RPI_CONTEXT; @@ -5897,17 +6001,13 @@ static void emlxs_sli4_rq_post(emlxs_port_t *port, uint16_t rqid) { emlxs_hba_t *hba = HBA; - emlxs_rqdbu_t rqdb; EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, "RQ POST: rqid=%d count=1", rqid); /* Ring the RQ doorbell once to repost the RQ buffer */ - rqdb.word = 0; - rqdb.db.Qid = rqid; - rqdb.db.NumPosted = 1; - emlxs_sli4_write_rqdb(hba, rqdb.word); + emlxs_sli4_write_rqdb(hba, rqid, 1); } /* emlxs_sli4_rq_post() */ @@ -6785,7 +6885,6 @@ emlxs_sli4_process_cq(emlxs_hba_t *hba, CQ_DESC_t *cq) emlxs_port_t *port = &PPORT; CQE_u *cqe; CQE_u cq_entry; - uint32_t cqdb; int num_entries = 0; off_t offset; @@ -6882,18 +6981,7 @@ emlxs_sli4_process_cq(emlxs_hba_t *hba, CQ_DESC_t *cq) if (cq->max_proc < num_entries) cq->max_proc = num_entries; - cqdb = cq->qid; - cqdb |= CQ_DB_REARM; - if (num_entries != 0) { - cqdb |= ((num_entries << CQ_DB_POP_SHIFT) & CQ_DB_POP_MASK); - } - -#ifdef DEBUG_FASTPATH - EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, - "CQE: CLEAR cqdb=%08x: pops=%d", cqdb, num_entries); -#endif /* DEBUG_FASTPATH */ - - emlxs_sli4_write_cqdb(hba, cqdb); + emlxs_sli4_write_cqdb(hba, cq->qid, num_entries, B_TRUE); /* EMLXS_PORT_LOCK must be held when exiting this routine */ @@ -6905,7 +6993,6 @@ static void emlxs_sli4_process_eq(emlxs_hba_t *hba, EQ_DESC_t *eq) { emlxs_port_t *port = &PPORT; - uint32_t eqdb; uint32_t *ptr; CHANNEL *cp; EQE_u eqe; @@ -6979,16 +7066,7 @@ emlxs_sli4_process_eq(emlxs_hba_t *hba, EQ_DESC_t *eq) eq->max_proc = num_entries; } - eqdb = eq->qid; - eqdb |= (EQ_DB_CLEAR | EQ_DB_EVENT | EQ_DB_REARM); - -#ifdef DEBUG_FASTPATH - EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, - "EQE: CLEAR eqdb=%08x pops=%d", eqdb, num_entries); -#endif /* DEBUG_FASTPATH */ - if (num_entries != 0) { - eqdb |= ((num_entries << EQ_DB_POP_SHIFT) & EQ_DB_POP_MASK); for (i = 0; i < hba->chan_count; i++) { cp = &hba->chan[i]; if (cp->chan_flag & EMLXS_NEEDS_TRIGGER) { @@ -6999,7 +7077,7 @@ emlxs_sli4_process_eq(emlxs_hba_t *hba, EQ_DESC_t *eq) } } - emlxs_sli4_write_cqdb(hba, eqdb); + emlxs_sli4_write_eqdb(hba, eq->qid, num_entries, B_TRUE); /* EMLXS_PORT_LOCK must be held when exiting this routine */ @@ -7163,7 +7241,6 @@ emlxs_sli4_enable_intr(emlxs_hba_t *hba) emlxs_config_t *cfg = &CFG; int i; int num_cq; - uint32_t data; hba->sli.sli4.flag |= EMLXS_SLI4_INTR_ENABLED; @@ -7172,14 +7249,11 @@ emlxs_sli4_enable_intr(emlxs_hba_t *hba) /* ARM EQ / CQs */ for (i = 0; i < num_cq; i++) { - data = hba->sli.sli4.cq[i].qid; - data |= CQ_DB_REARM; - emlxs_sli4_write_cqdb(hba, data); + emlxs_sli4_write_cqdb(hba, hba->sli.sli4.cq[i].qid, 0, B_TRUE); } + for (i = 0; i < hba->intr_count; i++) { - data = hba->sli.sli4.eq[i].qid; - data |= (EQ_DB_REARM | EQ_DB_EVENT); - emlxs_sli4_write_cqdb(hba, data); + emlxs_sli4_write_eqdb(hba, hba->sli.sli4.eq[i].qid, 0, B_TRUE); } } /* emlxs_sli4_enable_intr() */ @@ -7218,6 +7292,8 @@ emlxs_sli4_resource_free(emlxs_hba_t *hba) } if (hba->sli.sli4.XRIp) { + XRIobj_t *xrip; + if ((hba->sli.sli4.XRIinuse_f != (XRIobj_t *)&hba->sli.sli4.XRIinuse_f) || (hba->sli.sli4.XRIinuse_b != @@ -7228,6 +7304,17 @@ emlxs_sli4_resource_free(emlxs_hba_t *hba) hba->sli.sli4.XRIinuse_b, &hba->sli.sli4.XRIinuse_f); } + + xrip = hba->sli.sli4.XRIp; + for (i = 0; i < hba->sli.sli4.XRICount; i++) { + xrip->XRI = emlxs_sli4_index_to_xri(hba, i); + + if (xrip->XRI != 0) + emlxs_mem_put(hba, xrip->SGSeg, xrip->SGList); + + xrip++; + } + kmem_free(hba->sli.sli4.XRIp, (sizeof (XRIobj_t) * hba->sli.sli4.XRICount)); hba->sli.sli4.XRIp = NULL; @@ -7304,6 +7391,7 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) uint32_t hddr_size = 0; uint32_t align; uint32_t iotag; + uint32_t mseg; buf_info = &hba->sli.sli4.slim2; if (buf_info->virt) { @@ -7352,10 +7440,6 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) count += RQB_COUNT * (RQB_DATA_SIZE + RQB_HEADER_SIZE); count += (4096 - (count%4096)); /* Ensure 4K alignment */ - /* SGL */ - count += hba->sli.sli4.XRIExtSize * hba->sli.sli4.mem_sgl_size; - count += (4096 - (count%4096)); /* Ensure 4K alignment */ - /* RPI Header Templates */ if (hba->sli.sli4.param.HDRR) { /* Bytes per extent */ @@ -7373,9 +7457,12 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) /* Allocate slim2 for SLI4 */ buf_info = &hba->sli.sli4.slim2; buf_info->size = count; - buf_info->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG | FC_MBUF_DMA32; + buf_info->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG; buf_info->align = ddi_ptob(hba->dip, 1L); + EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg, + "Allocating memory for slim2: %d", count); + (void) emlxs_mem_alloc(hba, buf_info); if (buf_info->virt == NULL) { @@ -7389,7 +7476,7 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) EMLXS_MPDATA_SYNC(buf_info->dma_handle, 0, buf_info->size, DDI_DMA_SYNC_FORDEV); - /* Assign memory to SGL, Head Template, EQ, CQ, WQ, RQ and MQ */ + /* Assign memory to Head Template, EQ, CQ, WQ, RQ and MQ */ data_handle = buf_info->data_handle; dma_handle = buf_info->dma_handle; phys = buf_info->phys; @@ -7404,8 +7491,7 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) buf_info = &hba->sli.sli4.eq[i].addr; buf_info->size = size; - buf_info->flags = - FC_MBUF_DMA | FC_MBUF_SNGLSG | FC_MBUF_DMA32; + buf_info->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG; buf_info->align = ddi_ptob(hba->dip, 1L); buf_info->phys = phys; buf_info->virt = (void *)virt; @@ -7429,8 +7515,7 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) buf_info = &hba->sli.sli4.cq[i].addr; buf_info->size = cq_size; - buf_info->flags = - FC_MBUF_DMA | FC_MBUF_SNGLSG | FC_MBUF_DMA32; + buf_info->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG; buf_info->align = ddi_ptob(hba->dip, 1L); buf_info->phys = phys; buf_info->virt = (void *)virt; @@ -7452,8 +7537,7 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) buf_info = &hba->sli.sli4.wq[i].addr; buf_info->size = size; - buf_info->flags = - FC_MBUF_DMA | FC_MBUF_SNGLSG | FC_MBUF_DMA32; + buf_info->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG; buf_info->align = ddi_ptob(hba->dip, 1L); buf_info->phys = phys; buf_info->virt = (void *)virt; @@ -7475,8 +7559,7 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) buf_info = &hba->sli.sli4.mq.addr; buf_info->size = size; - buf_info->flags = - FC_MBUF_DMA | FC_MBUF_SNGLSG | FC_MBUF_DMA32; + buf_info->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG; buf_info->align = ddi_ptob(hba->dip, 1L); buf_info->phys = phys; buf_info->virt = (void *)virt; @@ -7505,8 +7588,7 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) buf_info = &hba->sli.sli4.rq[i].addr; buf_info->size = size; - buf_info->flags = - FC_MBUF_DMA | FC_MBUF_SNGLSG | FC_MBUF_DMA32; + buf_info->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG; buf_info->align = ddi_ptob(hba->dip, 1L); buf_info->phys = phys; buf_info->virt = (void *)virt; @@ -7544,8 +7626,7 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) rqb = &hba->sli.sli4.rq[i]. rqb[k + (j * RQB_COUNT)]; rqb->size = size; - rqb->flags = FC_MBUF_DMA | - FC_MBUF_SNGLSG | FC_MBUF_DMA32; + rqb->flags = FC_MBUF_DMA | FC_MBUF_SNGLSG; rqb->align = ddi_ptob(hba->dip, 1L); rqb->phys = phys; rqb->virt = (void *)virt; @@ -7579,7 +7660,25 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) phys += align; virt += align; + /* RPI Header Templates */ + if (hba->sli.sli4.param.HDRR) { + buf_info = &hba->sli.sli4.HeaderTmplate; + bzero(buf_info, sizeof (MBUF_INFO)); + buf_info->size = hddr_size; + buf_info->flags = FC_MBUF_DMA; + buf_info->align = ddi_ptob(hba->dip, 1L); + buf_info->phys = phys; + buf_info->virt = (void *)virt; + buf_info->data_handle = data_handle; + buf_info->dma_handle = dma_handle; + } + /* SGL */ + + EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_debug_msg, + "Allocating memory for %d SGLs: %d/%d", + hba->sli.sli4.XRICount, sizeof (XRIobj_t), size); + /* Initialize double linked lists */ hba->sli.sli4.XRIinuse_f = (XRIobj_t *)&hba->sli.sli4.XRIinuse_f; @@ -7591,14 +7690,31 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) (XRIobj_t *)&hba->sli.sli4.XRIfree_f; hba->sli.sli4.XRIfree_b = (XRIobj_t *)&hba->sli.sli4.XRIfree_f; - hba->sli.sli4.xria_count = 0; + hba->sli.sli4.xrif_count = 0; + + switch (hba->sli.sli4.mem_sgl_size) { + case 1024: + mseg = MEM_SGL1K; + break; + case 2048: + mseg = MEM_SGL2K; + break; + case 4096: + mseg = MEM_SGL4K; + break; + default: + EMLXS_MSGF(EMLXS_CONTEXT, + &emlxs_init_failed_msg, + "Unsupported SGL Size: %d", hba->sli.sli4.mem_sgl_size); + goto failed; + } hba->sli.sli4.XRIp = (XRIobj_t *)kmem_zalloc( (sizeof (XRIobj_t) * hba->sli.sli4.XRICount), KM_SLEEP); xrip = hba->sli.sli4.XRIp; - size = hba->sli.sli4.mem_sgl_size; iotag = 1; + for (i = 0; i < hba->sli.sli4.XRICount; i++) { xrip->XRI = emlxs_sli4_index_to_xri(hba, i); @@ -7621,38 +7737,19 @@ emlxs_sli4_resource_alloc(emlxs_hba_t *hba) hba->sli.sli4.xrif_count++; /* Allocate SGL for this xrip */ - buf_info = &xrip->SGList; - buf_info->size = size; - buf_info->flags = - FC_MBUF_DMA | FC_MBUF_SNGLSG | FC_MBUF_DMA32; - buf_info->align = size; - buf_info->phys = phys; - buf_info->virt = (void *)virt; - buf_info->data_handle = data_handle; - buf_info->dma_handle = dma_handle; + xrip->SGSeg = mseg; + xrip->SGList = emlxs_mem_get(hba, xrip->SGSeg); - phys += size; - virt += size; - - xrip++; - } + if (xrip->SGList == NULL) { + EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_failed_msg, + "Unable to allocate memory for SGL %d", i); + goto failed; + } - /* 4K Alignment */ - align = (4096 - (phys%4096)); - phys += align; - virt += align; + EMLXS_MPDATA_SYNC(xrip->SGList->dma_handle, 0, + xrip->SGList->size, DDI_DMA_SYNC_FORDEV); - /* RPI Header Templates */ - if (hba->sli.sli4.param.HDRR) { - buf_info = &hba->sli.sli4.HeaderTmplate; - bzero(buf_info, sizeof (MBUF_INFO)); - buf_info->size = hddr_size; - buf_info->flags = FC_MBUF_DMA | FC_MBUF_DMA32; - buf_info->align = ddi_ptob(hba->dip, 1L); - buf_info->phys = phys; - buf_info->virt = (void *)virt; - buf_info->data_handle = data_handle; - buf_info->dma_handle = dma_handle; + xrip++; } #ifdef FMA_SUPPORT @@ -8180,7 +8277,7 @@ emlxs_sli4_post_sgl_pages(emlxs_hba_t *hba, MAILBOXQ *mbq) emlxs_port_t *port = &PPORT; XRIobj_t *xrip; MATCHMAP *mp; - mbox_req_hdr_t *hdr_req; + mbox_req_hdr_t *hdr_req; uint32_t i; uint32_t cnt; uint32_t xri_cnt; @@ -8251,10 +8348,10 @@ emlxs_sli4_post_sgl_pages(emlxs_hba_t *hba, MAILBOXQ *mbq) post_sgl->params.request.xri_count++; post_sgl->params.request.pages[i].\ sgl_page0.addrLow = - PADDR_LO(xrip->SGList.phys); + PADDR_LO(xrip->SGList->phys); post_sgl->params.request.pages[i].\ sgl_page0.addrHigh = - PADDR_HI(xrip->SGList.phys); + PADDR_HI(xrip->SGList->phys); cnt--; xrip++; @@ -8287,8 +8384,8 @@ emlxs_sli4_post_hdr_tmplates(emlxs_hba_t *hba, MAILBOXQ *mbq) { MAILBOX4 *mb = (MAILBOX4 *)mbq; emlxs_port_t *port = &PPORT; - uint32_t j; - uint32_t k; + uint32_t j; + uint32_t k; uint64_t addr; IOCTL_FCOE_POST_HDR_TEMPLATES *post_hdr; uint16_t num_pages; @@ -8370,7 +8467,6 @@ emlxs_sli4_create_queues(emlxs_hba_t *hba, MAILBOXQ *mbq) IOCTL_FCOE_RQ_CREATE *rq; IOCTL_COMMON_MQ_CREATE *mq; IOCTL_COMMON_MQ_CREATE_EXT *mq_ext; - emlxs_rqdbu_t rqdb; uint16_t i, j; uint16_t num_cq, total_cq; uint16_t num_wq, total_wq; @@ -8530,11 +8626,9 @@ emlxs_sli4_create_queues(emlxs_hba_t *hba, MAILBOXQ *mbq) /* then post buffers using the header qid */ if ((i & 0x1)) { /* Ring the RQ doorbell to post buffers */ - rqdb.word = 0; - rqdb.db.Qid = hba->sli.sli4.rq[i-1].qid; - rqdb.db.NumPosted = RQB_COUNT; - emlxs_sli4_write_rqdb(hba, rqdb.word); + emlxs_sli4_write_rqdb(hba, hba->sli.sli4.rq[i-1].qid, + RQB_COUNT); EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, "RQ CREATE: Doorbell rang: qid=%d count=%d", @@ -8972,7 +9066,7 @@ emlxs_sli4_unreg_all_nodes(emlxs_port_t *port) { NODELIST *nlp; int i; - uint32_t found; + uint32_t found; /* Set the node tags */ /* We will process all nodes with this tag */ @@ -9113,6 +9207,9 @@ emlxs_sli4_handle_fc_link_att(emlxs_hba_t *hba, CQE_ASYNC_t *cqe) case 16: hba->linkspeed = LA_16GHZ_LINK; break; + case 32: + hba->linkspeed = LA_32GHZ_LINK; + break; default: EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_sli_detail_msg, "sli4_handle_fc_link_att: Unknown link speed=%x.", diff --git a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_solaris.c b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_solaris.c index 67ff78d03c..128773cbfd 100644 --- a/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_solaris.c +++ b/usr/src/uts/common/io/fibre-channel/fca/emlxs/emlxs_solaris.c @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #define DEF_ICFG 1 @@ -1647,6 +1648,10 @@ emlxs_fca_bind_port(dev_info_t *dip, fc_fca_port_info_t *port_info, (void) strlcpy(linkspeed, "16Gb", sizeof (linkspeed)); port_info->pi_port_state |= FC_STATE_16GBIT_SPEED; break; + case LA_32GHZ_LINK: + (void) strlcpy(linkspeed, "32Gb", sizeof (linkspeed)); + port_info->pi_port_state |= FC_STATE_32GBIT_SPEED; + break; default: (void) snprintf(linkspeed, sizeof (linkspeed), "unknown(0x%x)", hba->linkspeed); @@ -1794,7 +1799,7 @@ emlxs_fca_bind_port(dev_info_t *dip, fc_fca_port_info_t *port_info, (sizeof (port_info->pi_attrs.driver_name)-1)); port_info->pi_attrs.vendor_specific_id = - ((hba->model_info.device_id << 16) | PCI_VENDOR_ID_EMULEX); + (hba->model_info.device_id << 16) | hba->model_info.vendor_id; port_info->pi_attrs.supported_cos = LE_SWAP32(FC_NS_CLASS3); @@ -1803,7 +1808,7 @@ emlxs_fca_bind_port(dev_info_t *dip, fc_fca_port_info_t *port_info, #if (EMLXS_MODREV >= EMLXS_MODREV3) port_info->pi_rnid_params.params.num_attached = 0; - if (hba->model_info.chip == EMLXS_LANCER_CHIP) { + if ((hba->model_info.chip & EMLXS_LANCER_CHIPS) != 0) { uint8_t byte; uint8_t *wwpn; uint32_t i; @@ -1924,6 +1929,10 @@ emlxs_fca_bind_port(dev_info_t *dip, fc_fca_port_info_t *port_info, "%x", vpd->biuRev); /* Set the hba speed limit */ + if (vpd->link_speed & LMT_32GB_CAPABLE) { + port_info->pi_attrs.supported_speed |= + FC_HBA_PORTSPEED_32GBIT; + } if (vpd->link_speed & LMT_16GB_CAPABLE) { port_info->pi_attrs.supported_speed |= FC_HBA_PORTSPEED_16GBIT; @@ -4325,6 +4334,9 @@ emlxs_fca_port_manage(opaque_t fca_port_handle, fc_fca_pm_t *pm) case LA_16GHZ_LINK: *link_state |= FC_STATE_16GBIT_SPEED; break; + case LA_32GHZ_LINK: + *link_state |= FC_STATE_32GBIT_SPEED; + break; case LA_1GHZ_LINK: default: *link_state |= FC_STATE_1GBIT_SPEED; @@ -6844,9 +6856,9 @@ emlxs_drv_banner(emlxs_hba_t *hba) emlxs_revision); EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_attach_msg, - "%s Dev_id:%x Sub_id:%x Id:%d", hba->model_info.model, - hba->model_info.device_id, hba->model_info.ssdid, - hba->model_info.id); + "%s Ven_id:%x Dev_id:%x Sub_id:%x Id:%d", hba->model_info.model, + hba->model_info.vendor_id, hba->model_info.device_id, + hba->model_info.ssdid, hba->model_info.id); #ifdef EMLXS_I386 @@ -7172,9 +7184,10 @@ emlxs_hba_attach(dev_info_t *dip) if (rval == 0) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_attach_failed_msg, - "Unable to get adapter info. Id:%d Device id:0x%x " - "Model:%s", hba->model_info.id, - hba->model_info.device_id, hba->model_info.model); + "Unable to get adapter info. Id:%d Vendor id:0x%x " + "Device id:0x%x Model:%s", hba->model_info.id, + hba->model_info.vendor_id, hba->model_info.device_id, + hba->model_info.model); goto failed; } #define FILTER_ORACLE_BRANDED @@ -7189,9 +7202,9 @@ emlxs_hba_attach(dev_info_t *dip) /* Check if adapter is not supported */ if (hba->model_info.flags & EMLXS_NOT_SUPPORTED) { EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_attach_failed_msg, - "Unsupported adapter found. Id:%d Device id:0x%x " - "SSDID:0x%x Model:%s", hba->model_info.id, - hba->model_info.device_id, + "Unsupported adapter found. Id:%d Vendor id:0x%x " + "Device id:0x%x SSDID:0x%x Model:%s", hba->model_info.id, + hba->model_info.vendor_id, hba->model_info.device_id, hba->model_info.ssdid, hba->model_info.model); goto failed; } @@ -7804,6 +7817,18 @@ emlxs_check_parm(emlxs_hba_t *hba, uint32_t index, uint32_t new_value) } break; + case 32: + if (!(vpd->link_speed & LMT_32GB_CAPABLE)) { + new_value = 0; + + EMLXS_MSGF(EMLXS_CONTEXT, + &emlxs_init_msg, + "link-speed: 32Gb not supported " + "by adapter. Switching to auto " + "detect."); + } + break; + default: EMLXS_MSGF(EMLXS_CONTEXT, &emlxs_init_msg, "link-speed: Invalid value=%d provided. " @@ -8191,10 +8216,6 @@ emlxs_mem_alloc(emlxs_hba_t *hba, MBUF_INFO *buf_info) dma_attr.dma_attr_sgllen = 1; } - if (buf_info->flags & FC_MBUF_DMA32) { - dma_attr.dma_attr_addr_hi = (uint64_t)0xffffffff; - } - if (buf_info->flags & FC_MBUF_PHYSONLY) { if (buf_info->virt == NULL) { @@ -8282,7 +8303,7 @@ emlxs_mem_alloc(emlxs_hba_t *hba, MBUF_INFO *buf_info) EMLXS_MPDATA_SYNC((ddi_dma_handle_t)buf_info->dma_handle, (off_t)0, (size_t)buf_info->size, DDI_DMA_SYNC_FORDEV); - } else if (buf_info->flags & (FC_MBUF_DMA|FC_MBUF_DMA32)) { + } else if (buf_info->flags & FC_MBUF_DMA) { dma_attr.dma_attr_align = buf_info->align; @@ -8427,7 +8448,7 @@ emlxs_mem_free(emlxs_hba_t *hba, MBUF_INFO *buf_info) buf_info->dma_handle = NULL; } - } else if (buf_info->flags & (FC_MBUF_DMA|FC_MBUF_DMA32)) { + } else if (buf_info->flags & FC_MBUF_DMA) { if (buf_info->dma_handle) { (void) ddi_dma_unbind_handle(buf_info->dma_handle); diff --git a/usr/src/uts/common/io/fibre-channel/impl/fp.c b/usr/src/uts/common/io/fibre-channel/impl/fp.c index 016fe06839..acf4ecdf3f 100644 --- a/usr/src/uts/common/io/fibre-channel/impl/fp.c +++ b/usr/src/uts/common/io/fibre-channel/impl/fp.c @@ -20,6 +20,7 @@ */ /* * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright 2020 RackTop Systems, Inc. * * NOT a DDI compliant Sun Fibre Channel port driver(fp) * @@ -7895,6 +7896,9 @@ fp_fciocmd(fc_local_port_t *port, intptr_t data, int mode, fcio_t *fcio) case FC_STATE_16GBIT_SPEED: val->PortSpeed = FC_HBA_PORTSPEED_16GBIT; break; + case FC_STATE_32GBIT_SPEED: + val->PortSpeed = FC_HBA_PORTSPEED_32GBIT; + break; default: val->PortSpeed = FC_HBA_PORTSPEED_UNKNOWN; break; diff --git a/usr/src/uts/common/sys/fct.h b/usr/src/uts/common/sys/fct.h index 0bc201dc89..0960bbfb97 100644 --- a/usr/src/uts/common/sys/fct.h +++ b/usr/src/uts/common/sys/fct.h @@ -21,6 +21,7 @@ /* * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright 2016 Nexenta Systems, Inc. All rights reserved. + * Copyright 2020 RackTop Systems, Inc. */ #ifndef _FCT_H #define _FCT_H @@ -337,6 +338,7 @@ typedef struct fct_port_stat { #define PORT_SPEED_8G 8 #define PORT_SPEED_10G 16 #define PORT_SPEED_16G 32 +#define PORT_SPEED_32G 64 /* * Abort commands diff --git a/usr/src/uts/common/sys/fctio.h b/usr/src/uts/common/sys/fctio.h index 93e6128ccc..f9cda2d76e 100644 --- a/usr/src/uts/common/sys/fctio.h +++ b/usr/src/uts/common/sys/fctio.h @@ -21,6 +21,7 @@ /* * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #ifndef _FCTIO_H #define _FCTIO_H @@ -169,6 +170,7 @@ typedef struct fc_tgt_hba_adapter_port_stats { #define FC_HBA_PORTSPEED_4GBIT 8 /* 4 GBit/sec */ #define FC_HBA_PORTSPEED_8GBIT 16 /* 8 GBit/sec */ #define FC_HBA_PORTSPEED_16GBIT 32 /* 16 GBit/sec */ +#define FC_HBA_PORTSPEED_32GBIT 64 /* 32 GBit/sec */ #define FC_HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) /* Speed not established */ #define FCTIO_SUCCESS 0 diff --git a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_adapters.h b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_adapters.h index 694a2a9e59..19b3934b60 100644 --- a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_adapters.h +++ b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_adapters.h @@ -22,6 +22,8 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2018 OmniOS Community Edition (OmniOSce) Association. + * Copyright 2020 RackTop Systems, Inc. */ #ifndef _EMLXS_ADAPTERS_H @@ -100,7 +102,7 @@ typedef enum emlxs_adapter OCe11101, /* Generic Single Channel */ OCe11102, /* Generic Dual Channel */ - /* Lancer FC (45) */ + /* Lancer FC Gen5 HBAs (45) */ LPe16000, /* Generic Single Channel FC */ LPe1600X, /* Generic Multi Channel FC */ LPem16002_FC_O, /* Oracle branded */ @@ -108,7 +110,23 @@ typedef enum emlxs_adapter LPe16002_FC_SP1, /* Oracle excluded - Spare */ LPe16002_FC_SP2, /* Oracle excluded - Spare */ - /* Lancer FCoE (51) */ + /* Lancer FC Gen6 HBAs */ + LPe31000_M6_L, /* Single port 16Gb, Lenovo-branded */ + LPe32000, /* Generic Single Channel FC */ + LPe3200X, /* Generic Multi Channel FC */ + + /* Celerity 16 FC Gen5 */ + CelerityFC161E, + CelerityFC162E, + CelerityFC164E, + + /* Celerity 16 FC Gen6 */ + CelerityFC162P, + CelerityFC164P, + CelerityFC321E, + CelerityFC322E, + + /* Lancer FCoE */ OCe15100, /* Generic Single Channel FCOE */ OCe1510X, /* Generic Multi Channel FCOE */ LPem16002_FE_O, /* Oracle branded */ @@ -117,12 +135,13 @@ typedef enum emlxs_adapter LPe16002_FE_SP2, /* Oracle excluded - Spare */ /* BE4 (57) */ - OCe12104 /* 4-Port 2xNIC +2xFCoE */ - + OCe12104, /* 4-Port 2xNIC +2xFCoE */ } emlxs_adapter_t; #define PCI_VENDOR_ID_EMULEX 0x10df +#define PCI_VENDOR_ID_ATTO 0x117c +#define PCI_VENDOR_ID_OCE 0x19a2 /* Subsystem Vendor IDs */ #define PCI_SSVID_EMULEX 0x10df @@ -256,7 +275,7 @@ typedef enum emlxs_adapter #define PCI_DEVICE_ID_BE4 0x0724 #define PCI_SSDID_OCe12104 0xEF81 -/* E200: Lancer FC */ +/* E200: Lancer FC Gen5 */ #define PCI_DEVICE_ID_LANCER_FC 0xE200 #define PCI_SSDID_LPe16000 0xE200 #define PCI_SSDID_LPe1600X 0xE200 /* Identified by cache_line */ @@ -265,6 +284,12 @@ typedef enum emlxs_adapter #define PCI_SSDID_LPe16002_FC_SP1 0xE217 #define PCI_SSDID_LPe16002_FC_SP2 0xE219 +/* E300: Lancer FC Gen6 */ +#define PCI_DEVICE_ID_LANCER_G6_FC 0xE300 +#define PCI_SSDID_LPe31000_M6_L 0xE333 +#define PCI_SSDID_LPe32000 0xE300 +#define PCI_SSDID_LPe3200X 0xE300 + /* E260: Lancer FCoE */ #define PCI_DEVICE_ID_LANCER_FE 0xE260 #define PCI_SSDID_OCe15100 0xE260 @@ -274,7 +299,20 @@ typedef enum emlxs_adapter #define PCI_SSDID_LPe16002_FE_SP1 0xE217 #define PCI_SSDID_LPe16002_FE_SP2 0xE219 - +/* 0063: ATTO Celerity 16 FC Gen5 */ +#define PCI_DEVICE_ID_CLRTY_FC_161E 0x0063 +#define PCI_DEVICE_ID_CLRTY_FC_162E 0x0064 +#define PCI_DEVICE_ID_CLRTY_FC_164E 0x0065 +#define PCI_SSDID_CLRTY_FC_161E 0x0063 +#define PCI_SSDID_CLRTY_FC_162E 0x0064 +#define PCI_SSDID_CLRTY_FC_164E 0x0065 + +/* 0094 ATTO Celerity 16 FC Gen6 */ +#define PCI_DEVICE_ID_CLRTY_FC_G6 0x0094 +#define PCI_SSDID_CLRTY_FC_162P 0x0094 +#define PCI_SSDID_CLRTY_FC_164P 0x00A1 +#define PCI_SSDID_CLRTY_FC_321E 0x00A2 +#define PCI_SSDID_CLRTY_FC_322E 0x00A3 /* JEDEC codes */ #define FIREFLY_JEDEC_ID 0x1ACC @@ -296,6 +334,7 @@ typedef enum emlxs_adapter typedef struct emlxs_model { emlxs_adapter_t id; + uint16_t vendor_id; uint16_t device_id; uint16_t ssdid; @@ -331,6 +370,8 @@ typedef struct emlxs_model #define EMLXS_BE4_CHIP 0x00000800 #define EMLXS_BE_CHIPS (EMLXS_BE2_CHIP|EMLXS_BE3_CHIP|EMLXS_BE4_CHIP) #define EMLXS_LANCER_CHIP 0x00001000 +#define EMLXS_LANCERG6_CHIP 0x00002000 +#define EMLXS_LANCER_CHIPS (EMLXS_LANCER_CHIP | EMLXS_LANCERG6_CHIP) emlxs_fwid_t fwid; uint32_t intr_limit; @@ -378,6 +419,7 @@ emlxs_model_t emlxs_sbus_model[] = UNKNOWN_ADAPTER, 0, 0, + 0, "unknown", "Unknown Emulex LightPulse FC HBA", "Emulex", @@ -393,6 +435,7 @@ emlxs_model_t emlxs_sbus_model[] = /* Dragonfly midrange (QFLY) */ { LP8000S, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_DRAGONFLY_SBUS, PCI_SSDID_LP8000S, "LP8000S", @@ -418,6 +461,7 @@ emlxs_model_t emlxs_sbus_model[] = /* Centaur mid-range (RFLY, Rtaur) */ { LP9002S, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_CENTAUR_SBUS, PCI_SSDID_LP9002S, "LP9002S", @@ -454,6 +498,7 @@ emlxs_model_t emlxs_pci_model[] = UNKNOWN_ADAPTER, 0, 0, + 0, "unknown", "Unknown Emulex LightPulse FC HBA", "Emulex", @@ -469,6 +514,7 @@ emlxs_model_t emlxs_pci_model[] = /* Dragonfly */ { LP8000, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_DRAGONFLY, PCI_SSDID_LP8000, "LP8000", @@ -495,6 +541,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LP8000DC, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_DRAGONFLY, PCI_SSDID_LP8000DC, "LP8000DC", @@ -520,6 +567,7 @@ emlxs_model_t emlxs_pci_model[] = /* Centaur PCI */ { LP9002L, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_CENTAUR, PCI_SSDID_LP9002L, "LP9002L", @@ -545,6 +593,7 @@ emlxs_model_t emlxs_pci_model[] = /* Centaur cPCI */ { LP9002C, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_CENTAUR, PCI_SSDID_LP9002C, "LP9002C", @@ -571,6 +620,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LP9002DC, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_CENTAUR, PCI_SSDID_LP9002DC, "LP9002DC", @@ -597,6 +647,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LP9402DC, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_CENTAUR, PCI_SSDID_LP9402DC, "LP9402DC", @@ -622,6 +673,7 @@ emlxs_model_t emlxs_pci_model[] = /* Pegasus */ { LP9802, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PEGASUS, PCI_SSDID_LP9802, "LP9802", @@ -648,6 +700,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LP9802DC, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_PEGASUS, PCI_SSDID_LP9802DC, "LP9802DC", @@ -673,6 +726,7 @@ emlxs_model_t emlxs_pci_model[] = /* Thor */ { LP10000, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_THOR, PCI_SSDID_LP10000, "LP10000", @@ -699,6 +753,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LP10000DC, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_THOR, PCI_SSDID_LP10000DC, "LP10000DC", @@ -725,6 +780,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LP10000ExDC, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_THOR, PCI_SSDID_LP10000ExDC, "LP10000ExDC", @@ -750,6 +806,7 @@ emlxs_model_t emlxs_pci_model[] = /* Thor (Oracle Rainbow-E1) */ { LP10000_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_THOR_O, PCI_SSDID_LP10000_O, "LP10000-S", @@ -777,6 +834,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LP10000DC_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_THOR_O, PCI_SSDID_LP10000DC_O, "LP10000DC-S", @@ -803,6 +861,7 @@ emlxs_model_t emlxs_pci_model[] = /* Thor mid-range (MiniThor) */ { BLADE_2G, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_THOR_BLADE, PCI_SSDID_BLADE_2G, "2G Blade Adapter", @@ -828,6 +887,7 @@ emlxs_model_t emlxs_pci_model[] = /* Helios */ { LP11000, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HELIOS, PCI_SSDID_LP11000, "LP11000", @@ -854,6 +914,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LP11002, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HELIOS, PCI_SSDID_LP11002, "LP11002", @@ -879,6 +940,7 @@ emlxs_model_t emlxs_pci_model[] = /* Helios (Oracle Pyramid-E1) */ { LP11000_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HELIOS_O, PCI_SSDID_LP11000_O, "LP11000-S", @@ -905,6 +967,7 @@ emlxs_model_t emlxs_pci_model[] = /* Helios DC (Oracle Pyramid-E2) */ { LP11002_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HELIOS_O, PCI_SSDID_LP11002_O, "LP11002-S", @@ -931,6 +994,7 @@ emlxs_model_t emlxs_pci_model[] = /* Helios Enterprise (Spare) */ { LP11000_SP, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LP11000_SP, PCI_SSDID_LP11000_SP, "LP11000", @@ -956,6 +1020,7 @@ emlxs_model_t emlxs_pci_model[] = /* Helios DC Enterprise (Spare) */ { LP11002_SP, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LP11002_SP, PCI_SSDID_LP11002_SP, "LP11002", @@ -981,6 +1046,7 @@ emlxs_model_t emlxs_pci_model[] = /* Zephyr */ { LPe11000, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR, PCI_SSDID_LPe11000, "LPe11000", @@ -1007,6 +1073,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LPe1100X, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR, PCI_SSDID_LPe1100X, "LPe11000", @@ -1032,6 +1099,7 @@ emlxs_model_t emlxs_pci_model[] = /* Zephyr Hornet */ { LP21000, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HORNET, PCI_SSDID_LP21000, "LP21000", @@ -1058,6 +1126,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LP21002, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_HORNET, PCI_SSDID_LP21002, "LP21002", @@ -1083,6 +1152,7 @@ emlxs_model_t emlxs_pci_model[] = /* Zephyr (Oracle Summit-E1) */ { LPe11000_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR_O, PCI_SSDID_LPe11000_O, "LPe11000-S", @@ -1110,6 +1180,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LPe11002_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR_O, PCI_SSDID_LPe11002_O, "LPe11002-S", @@ -1137,6 +1208,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LPe11020_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR_O, PCI_SSDID_LPe11020_O, "LPe11020-S", @@ -1164,6 +1236,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LPem11002_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR_O, PCI_SSDID_LPem11002_O, "LPem11002-S", @@ -1191,6 +1264,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LPem11002E_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR_O, PCI_SSDID_LPem11002E_O, "LPem11002E-S", @@ -1218,6 +1292,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LPeA11002_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_ZEPHYR_O, PCI_SSDID_LPeA11002_O, "LPeA11002-S", @@ -1244,6 +1319,7 @@ emlxs_model_t emlxs_pci_model[] = /* Saturn */ { LPe12000, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SATURN, PCI_SSDID_LPe12000, "LPe12000", @@ -1271,6 +1347,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LPe12002, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SATURN, PCI_SSDID_LPe12002, "LPe12002", @@ -1297,6 +1374,7 @@ emlxs_model_t emlxs_pci_model[] = /* Saturn (Oracle) */ { LPe12000_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SATURN_O, PCI_SSDID_LPe12000_O, "LPe12000-S", @@ -1324,6 +1402,7 @@ emlxs_model_t emlxs_pci_model[] = /* Saturn DC (Oracle) */ { LPe12002_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SATURN_O, PCI_SSDID_LPe12002_O, "LPe12002-S", @@ -1351,6 +1430,7 @@ emlxs_model_t emlxs_pci_model[] = /* Saturn Express Module (Oracle) */ { LPem12002_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SATURN_O, PCI_SSDID_LPem12002_O, "LPem12002-S", @@ -1378,6 +1458,7 @@ emlxs_model_t emlxs_pci_model[] = /* Saturn Express Module (Oracle Metis) */ { LPem12002E_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_SATURN_O, PCI_SSDID_LPem12002E_O, "LPem12002E-S", @@ -1405,6 +1486,7 @@ emlxs_model_t emlxs_pci_model[] = /* Saturn */ { LPe12000_SP, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LPe12000_SP, PCI_SSDID_LPe12000_SP, "LPe12000", @@ -1431,6 +1513,7 @@ emlxs_model_t emlxs_pci_model[] = /* Saturn DC */ { LPe12002_SP, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LPe12002_SP, PCI_SSDID_LPe12002_SP, "LPe12002", @@ -1457,6 +1540,7 @@ emlxs_model_t emlxs_pci_model[] = /* BE2 (Tigershark) */ { OCe10101, + PCI_VENDOR_ID_OCE, PCI_DEVICE_ID_BE2, PCI_SSDID_OCe10101, "OCe10101", @@ -1476,6 +1560,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { OCe10102, + PCI_VENDOR_ID_OCE, PCI_DEVICE_ID_BE2, PCI_SSDID_OCe10102, "OCe10102", @@ -1494,6 +1579,7 @@ emlxs_model_t emlxs_pci_model[] = /* BE3 (TomCat) */ { OCe11101, + PCI_VENDOR_ID_OCE, PCI_DEVICE_ID_BE3, PCI_SSDID_OCe11101, "OCe11101", @@ -1513,6 +1599,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { OCe11102, + PCI_VENDOR_ID_OCE, PCI_DEVICE_ID_BE3, PCI_SSDID_OCe11102, "OCe11102", @@ -1531,6 +1618,7 @@ emlxs_model_t emlxs_pci_model[] = /* Lancer FC (Generic) */ { LPe16000, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC, PCI_SSDID_LPe16000, "LPe16000", @@ -1550,6 +1638,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { LPe1600X, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC, PCI_SSDID_LPe1600X, "LPe16000", @@ -1568,6 +1657,7 @@ emlxs_model_t emlxs_pci_model[] = /* Lancer FC DC Express Module (Oracle Ganymede) */ { LPem16002_FC_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC, PCI_SSDID_LPem16002_FC_O, "LPem16002-M6-O", @@ -1587,6 +1677,7 @@ emlxs_model_t emlxs_pci_model[] = /* Lancer FC DC (Oracle Ganymede) */ { LPe16002_FC_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC, PCI_SSDID_LPe16002_FC_O, "LPe16002-M6-O", @@ -1606,6 +1697,7 @@ emlxs_model_t emlxs_pci_model[] = /* Lancer FC DC (Oracle Excluded - Spare 1) */ { LPe16002_FC_SP1, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC, PCI_SSDID_LPe16002_FC_SP1, "LPe16002", @@ -1625,6 +1717,7 @@ emlxs_model_t emlxs_pci_model[] = /* Lancer FC DC (Oracle Excluded - Spare 2) */ { LPe16002_FC_SP2, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FC, PCI_SSDID_LPe16002_FC_SP2, "LPe16002", @@ -1641,9 +1734,211 @@ emlxs_model_t emlxs_pci_model[] = NULL_PROG_TYPES, }, + /* Lancer Gen6 16Gb FC Single-port, Lenovo-branded */ + { + LPe31000_M6_L, + PCI_VENDOR_ID_EMULEX, + PCI_DEVICE_ID_LANCER_G6_FC, + PCI_SSDID_LPe31000_M6_L, + "LPe31000", + "PCI_SSDID_LPe31000_M6_L", + "Emulex", + EMLXS_INTX_SUPPORTED | + EMLXS_MSI_SUPPORTED | EMLXS_MSIX_SUPPORTED | + EMLXS_E2E_SUPPORTED, + EMLXS_LANCERG6_CHIP, + FW_NOT_PROVIDED, + EMLXS_INTR_NO_LIMIT, + EMLXS_SLI4_MASK, + EMLXS_SINGLE_CHANNEL, + NULL_PROG_TYPES, + }, + + /* Lancer Gen6 FC (Generic) */ + { + LPe32000, + PCI_VENDOR_ID_EMULEX, + PCI_DEVICE_ID_LANCER_G6_FC, + PCI_SSDID_LPe32000, + "LPe32000", + "Emulex LightPulse LPe32000 32Gb 1-port FC HBA", + "Emulex", + EMLXS_INTX_SUPPORTED | + EMLXS_MSI_SUPPORTED | EMLXS_MSIX_SUPPORTED | + EMLXS_E2E_SUPPORTED, + EMLXS_LANCERG6_CHIP, + FW_NOT_PROVIDED, + EMLXS_INTR_NO_LIMIT, + EMLXS_SLI4_MASK, + EMLXS_SINGLE_CHANNEL, + NULL_PROG_TYPES, + }, + + /* Lancer Gen6 FC (Generic Multi-Channel) */ + /* !! Must always follow the single channel entry in list */ + { + LPe3200X, + PCI_VENDOR_ID_EMULEX, + PCI_DEVICE_ID_LANCER_G6_FC, + PCI_SSDID_LPe3200X, + "LPe32000", + "Emulex LightPulse LPe32000 32Gb Multi-port FC HBA", + "Emulex", + EMLXS_INTX_SUPPORTED | + EMLXS_MSI_SUPPORTED | EMLXS_MSIX_SUPPORTED | + EMLXS_E2E_SUPPORTED, + EMLXS_LANCERG6_CHIP, + FW_NOT_PROVIDED, + EMLXS_INTR_NO_LIMIT, + EMLXS_SLI4_MASK, + EMLXS_MULTI_CHANNEL, + NULL_PROG_TYPES, + }, + + /* ATTO Celerity 161E */ + { + CelerityFC161E, + PCI_VENDOR_ID_ATTO, + PCI_DEVICE_ID_CLRTY_FC_161E, + PCI_SSDID_CLRTY_FC_161E, + "Celerity FC 161E", + "ATTO Celerity 161E Single-Channel FC HBA", + "ATTO Technology", + EMLXS_INTX_SUPPORTED | + EMLXS_MSI_SUPPORTED | EMLXS_MSIX_SUPPORTED | + EMLXS_E2E_SUPPORTED, + EMLXS_LANCER_CHIP, + FW_NOT_PROVIDED, + EMLXS_INTR_NO_LIMIT, + EMLXS_SLI4_MASK, + EMLXS_SINGLE_CHANNEL, + NULL_PROG_TYPES, + }, + + /* ATTO Celerity 162E */ + { + CelerityFC162E, + PCI_VENDOR_ID_ATTO, + PCI_DEVICE_ID_CLRTY_FC_162E, + PCI_SSDID_CLRTY_FC_162E, + "Celerity FC 162E", + "ATTO Celerity 162E Dual-Channel FC HBA", + "ATTO Technology", + EMLXS_INTX_SUPPORTED | + EMLXS_MSI_SUPPORTED | EMLXS_MSIX_SUPPORTED | + EMLXS_E2E_SUPPORTED, + EMLXS_LANCER_CHIP, + FW_NOT_PROVIDED, + EMLXS_INTR_NO_LIMIT, + EMLXS_SLI4_MASK, + EMLXS_SINGLE_CHANNEL, + NULL_PROG_TYPES, + }, + + /* ATTO Celerity 164E */ + { + CelerityFC164E, + PCI_VENDOR_ID_ATTO, + PCI_DEVICE_ID_CLRTY_FC_164E, + PCI_SSDID_CLRTY_FC_164E, + "Celerity FC 164E", + "ATTO Celerity 164E Quad-Channel FC HBA", + "ATTO Technology", + EMLXS_INTX_SUPPORTED | + EMLXS_MSI_SUPPORTED | EMLXS_MSIX_SUPPORTED | + EMLXS_E2E_SUPPORTED, + EMLXS_LANCER_CHIP, + FW_NOT_PROVIDED, + EMLXS_INTR_NO_LIMIT, + EMLXS_SLI4_MASK, + EMLXS_SINGLE_CHANNEL, + NULL_PROG_TYPES, + }, + + /* ATTO Celerity 162P */ + { + CelerityFC162P, + PCI_VENDOR_ID_ATTO, + PCI_DEVICE_ID_CLRTY_FC_G6, + PCI_SSDID_CLRTY_FC_162P, + "Celerity FC 162P", + "ATTO Celerity 162P Dual-Channel FC HBA", + "ATTO Technology", + EMLXS_INTX_SUPPORTED | + EMLXS_MSI_SUPPORTED | EMLXS_MSIX_SUPPORTED | + EMLXS_E2E_SUPPORTED, + EMLXS_LANCERG6_CHIP, + FW_NOT_PROVIDED, + EMLXS_INTR_NO_LIMIT, + EMLXS_SLI4_MASK, + EMLXS_SINGLE_CHANNEL, + NULL_PROG_TYPES, + }, + + /* ATTO Celerity 164P */ + { + CelerityFC164P, + PCI_VENDOR_ID_ATTO, + PCI_DEVICE_ID_CLRTY_FC_G6, + PCI_SSDID_CLRTY_FC_164P, + "Celerity FC 164P", + "ATTO Celerity 164P Quad-Channel FC HBA", + "ATTO Technology", + EMLXS_INTX_SUPPORTED | + EMLXS_MSI_SUPPORTED | EMLXS_MSIX_SUPPORTED | + EMLXS_E2E_SUPPORTED, + EMLXS_LANCERG6_CHIP, + FW_NOT_PROVIDED, + EMLXS_INTR_NO_LIMIT, + EMLXS_SLI4_MASK, + EMLXS_SINGLE_CHANNEL, + NULL_PROG_TYPES, + }, + + /* ATTO Celerity 321E */ + { + CelerityFC321E, + PCI_VENDOR_ID_ATTO, + PCI_DEVICE_ID_CLRTY_FC_G6, + PCI_SSDID_CLRTY_FC_321E, + "Celerity FC 321E", + "ATTO Celerity 321E Single-Channel FC HBA", + "ATTO Technology", + EMLXS_INTX_SUPPORTED | + EMLXS_MSI_SUPPORTED | EMLXS_MSIX_SUPPORTED | + EMLXS_E2E_SUPPORTED, + EMLXS_LANCERG6_CHIP, + FW_NOT_PROVIDED, + EMLXS_INTR_NO_LIMIT, + EMLXS_SLI4_MASK, + EMLXS_SINGLE_CHANNEL, + NULL_PROG_TYPES, + }, + + /* ATTO Celerity 322E */ + { + CelerityFC322E, + PCI_VENDOR_ID_ATTO, + PCI_DEVICE_ID_CLRTY_FC_G6, + PCI_SSDID_CLRTY_FC_322E, + "Celerity FC 322E", + "ATTO Celerity 322E Dual-Channel FC HBA", + "ATTO Technology", + EMLXS_INTX_SUPPORTED | + EMLXS_MSI_SUPPORTED | EMLXS_MSIX_SUPPORTED | + EMLXS_E2E_SUPPORTED, + EMLXS_LANCERG6_CHIP, + FW_NOT_PROVIDED, + EMLXS_INTR_NO_LIMIT, + EMLXS_SLI4_MASK, + EMLXS_SINGLE_CHANNEL, + NULL_PROG_TYPES, + }, + /* Lancer FCOE (Generic) */ { OCe15100, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FE, PCI_SSDID_OCe15100, "OCe15100", @@ -1663,6 +1958,7 @@ emlxs_model_t emlxs_pci_model[] = /* !! Must always follow the single channel entry in list */ { OCe1510X, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FE, PCI_SSDID_OCe1510X, "OCe15100", @@ -1681,6 +1977,7 @@ emlxs_model_t emlxs_pci_model[] = /* Lancer FCOE DC Express Module (Oracle Ganymede) */ { LPem16002_FE_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FE, PCI_SSDID_LPem16002_FE_O, "LPem16002-M6-O", @@ -1700,6 +1997,7 @@ emlxs_model_t emlxs_pci_model[] = /* Lancer FCOE DC (Oracle Ganymede) */ { LPe16002_FE_O, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FE, PCI_SSDID_LPe16002_FE_O, "LPe16002-M6-O", @@ -1719,6 +2017,7 @@ emlxs_model_t emlxs_pci_model[] = /* Lancer FCOE DC (Oracle Excluded - Spare 1) */ { LPe16002_FE_SP1, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FE, PCI_SSDID_LPe16002_FE_SP1, "LPe16002", @@ -1738,6 +2037,7 @@ emlxs_model_t emlxs_pci_model[] = /* Lancer FCOE DC (Oracle Excluded - Spare 2) */ { LPe16002_FE_SP2, + PCI_VENDOR_ID_EMULEX, PCI_DEVICE_ID_LANCER_FE, PCI_SSDID_LPe16002_FE_SP2, "LPe16002", @@ -1757,6 +2057,7 @@ emlxs_model_t emlxs_pci_model[] = /* BE4 (Skyhawk) */ { OCe12104, + PCI_VENDOR_ID_OCE, PCI_DEVICE_ID_BE4, PCI_SSDID_OCe12104, "OCe12104", @@ -1770,8 +2071,7 @@ emlxs_model_t emlxs_pci_model[] = EMLXS_SLI4_MASK, EMLXS_MULTI_CHANNEL, NULL_PROG_TYPES, - }, - + } }; /* emlxs_pci_model[] */ int emlxs_pci_model_count = diff --git a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fc.h b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fc.h index 65492213cc..945c3cd52e 100644 --- a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fc.h +++ b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fc.h @@ -22,6 +22,8 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2018 OmniOS Community Edition (OmniOSce) Association. + * Copyright 2020 RackTop Systems, Inc. */ #ifndef _EMLXS_FC_H @@ -287,7 +289,6 @@ typedef struct emlxs_buf_info #define FC_MBUF_UNLOCK 0x08 /* called with driver unlocked */ #define FC_MBUF_SNGLSG 0x10 /* allocate a single contiguous */ /* physical memory */ -#define FC_MBUF_DMA32 0x20 uint64_t phys; /* specifies physical buffer pointer */ void *virt; /* specifies virtual buffer pointer */ @@ -494,12 +495,15 @@ typedef emlxs_fcip_nethdr_t NETHDR; #define MEM_IPBUF 5 /* memory segment to hold IP buffer data */ #define MEM_CTBUF 6 /* memory segment to hold CT buffer data */ #define MEM_FCTBUF 7 /* memory segment to hold FCT buffer data */ +#define MEM_SGL1K 8 /* memory segment to hold 1K SGL entries */ +#define MEM_SGL2K 9 /* memory segment to hold 2K SGL entries */ +#define MEM_SGL4K 10 /* memory segment to hold 4K SGL entries */ #ifdef SFCT_SUPPORT -#define FC_MAX_SEG 8 -#define MEM_FCTSEG 10 /* must be greater than FC_MAX_SEG */ +#define FC_MAX_SEG 11 +#define MEM_FCTSEG 13 /* must be greater than FC_MAX_SEG */ #else -#define FC_MAX_SEG 7 +#define FC_MAX_SEG 10 #endif /* SFCT_SUPPORT */ diff --git a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fcf.h b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fcf.h index c8c783482b..89c3b10655 100644 --- a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fcf.h +++ b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fcf.h @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2018 OmniOS Community Edition (OmniOSce) Association. */ #ifndef _EMLXS_FCF_H @@ -100,7 +101,8 @@ typedef struct XRIobj uint16_t sge_count; uint16_t iotag; - MBUF_INFO SGList; + MATCHMAP *SGList; + uint32_t SGSeg; struct RPIobj *rpip; struct RPIobj *reserved_rpip; emlxs_buf_t *sbp; diff --git a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fct.h b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fct.h index b80b9a8874..bfb2dbd8ca 100644 --- a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fct.h +++ b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_fct.h @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2011 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #ifndef _EMLXS_FCT_H @@ -63,6 +64,10 @@ extern "C" { #define PORT_SPEED_16G 0x20 #endif /* PORT_SPEED_16G */ +#ifndef PORT_SPEED_32G +#define PORT_SPEED_32G 0x40 +#endif /* PORT_SPEED_32G */ + /* * Number of ports that do not require a valid cmd handle * because they will not be sending any IO, ELS cmds ONLY. diff --git a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_hbaapi.h b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_hbaapi.h index c253af3921..387d204455 100644 --- a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_hbaapi.h +++ b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_hbaapi.h @@ -36,6 +36,10 @@ ******************************************************************************* */ +/* + * Copyright 2020 RackTop Systems, Inc. + */ + #ifndef _EMLXS_HBAAPI_H #define _EMLXS_HBAAPI_H @@ -239,6 +243,7 @@ typedef HBA_UINT32 HBA_PORTSPEED; #define HBA_PORTSPEED_4GBIT 8 /* 4 GBit/sec */ #define HBA_PORTSPEED_8GBIT 16 /* 8 GBit/sec */ #define HBA_PORTSPEED_16GBIT 32 /* 16 GBit/sec */ +#define HBA_PORTSPEED_32GBIT 64 /* 32 GBit/sec */ #define HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) /* Speed not established */ diff --git a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_hw.h b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_hw.h index 3755ffa7b3..ab4b4b4e6b 100644 --- a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_hw.h +++ b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_hw.h @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2011 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #ifndef _EMLXS_HW_H @@ -794,6 +795,10 @@ typedef SliCtRequest_t SLI_CT_REQUEST; #define CQ_DB_POP_SHIFT 16 /* shift for entries popped */ #define CQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ #define CQ_DB_REARM 0x20000000 /* Bit 29, rearm */ +#define CQ_ID_LO_BITS 10 /* num of id bits that are "low" */ +#define CQ_DB_ID_LO_MASK ((1 << CQ_ID_LO_BITS) - 1) +#define CQ_DB_ID_HI_SHIFT 11 +#define CQ_DB_ID_HI_MASK (0x1F << CQ_DB_ID_HI_SHIFT) /* Defines for EQ doorbell */ #define EQ_DB_CLEAR 0x00000200 /* Bit 9, designates clear EQ ISR */ @@ -801,11 +806,21 @@ typedef SliCtRequest_t SLI_CT_REQUEST; #define EQ_DB_POP_SHIFT 16 /* shift for entries popped */ #define EQ_DB_POP_MASK 0x1FFF0000 /* Mask for number of entries popped */ #define EQ_DB_REARM 0x20000000 /* Bit 29, rearm */ +#define EQ_ID_LO_BITS 9 /* num of id bits that are "low" */ +#define EQ_DB_ID_LO_MASK ((1 << EQ_ID_LO_BITS) - 1) +#define EQ_DB_ID_HI_SHIFT 11 +#define EQ_DB_ID_HI_MASK (0x1F << EQ_DB_ID_HI_SHIFT) + +/* Defines for WQ doorbell */ +#define WQ_DB_POST_SHIFT 24 +#define WQ_DB_POST_MASK (0xFF << WQ_DB_POST_SHIFT) +#define WQ_DB_IDX_SHIFT 16 +#define WQ_DB_IDX_MASK (0xFF << WQ_DB_IDX_SHIFT) /* bootstrap mailbox doorbell defines */ #define BMBX_READY 0x00000001 /* Mask for Port Ready bit */ #define BMBX_ADDR_HI 0x00000002 /* Mask for Addr Hi bit */ -#define BMBX_ADDR 0xFFFFFFFA /* Mask for Addr bits */ +#define BMBX_ADDR 0xFFFFFFFC /* Mask for Addr bits */ /* Sizeof bootstrap mailbox */ #define EMLXS_BOOTSTRAP_MB_SIZE 256 diff --git a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_mbox.h b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_mbox.h index 8d132cc2db..1d99f28b54 100644 --- a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_mbox.h +++ b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_mbox.h @@ -22,6 +22,7 @@ /* * Copyright (c) 2004-2012 Emulex. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #ifndef _EMLXS_MBOX_H @@ -585,9 +586,15 @@ typedef struct #define FLAGS_PREABORT_RETURN 0x4000 /* Bit 14 */ uint32_t link_speed; /* NEW_FEATURE */ -#define LINK_SPEED_AUTO 0 /* Auto selection */ -#define LINK_SPEED_1G 1 /* 1 Gigabaud */ -#define LINK_SPEED_2G 2 /* 2 Gigabaud */ +#define LINK_SPEED_AUTO 0x0 /* Auto selection */ +#define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ +#define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ +#define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ +#define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ +#define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ +#define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ +#define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ + } INIT_LINK_VAR; @@ -758,6 +765,7 @@ typedef struct #define LMT_8GB_CAPABLE 0x0080 #define LMT_10GB_CAPABLE 0x0100 #define LMT_16GB_CAPABLE 0x0200 +#define LMT_32GB_CAPABLE 0x0400 /* E2E supported on adapters >= 8GB */ #define LMT_E2E_CAPABLE (LMT_8GB_CAPABLE|LMT_10GB_CAPABLE) @@ -1572,6 +1580,7 @@ typedef struct #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ #define LA_16GHZ_LINK 0x80 /* lnkSpeed */ +#define LA_32GHZ_LINK 0x90 /* lnkSpeed */ } READ_LA_VAR; diff --git a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_version.h b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_version.h index 1f4db92ef9..89790d158a 100644 --- a/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_version.h +++ b/usr/src/uts/common/sys/fibre-channel/fca/emlxs/emlxs_version.h @@ -35,11 +35,11 @@ extern "C" { #define EMLXS_VERSION "2.80.8.0" -#define EMLXS_DATE_MINUTE "45" /* 00-59 */ -#define EMLXS_DATE_HOUR "15" /* 00-23 */ -#define EMLXS_DATE_DAY "17" /* 00-31 */ -#define EMLXS_DATE_MONTH "09" /* 01-12 */ -#define EMLXS_DATE_YEAR "2012" /* YYYY */ +#define EMLXS_DATE_MINUTE "16" /* 00-59 */ +#define EMLXS_DATE_HOUR "28" /* 00-23 */ +#define EMLXS_DATE_DAY "28" /* 00-31 */ +#define EMLXS_DATE_MONTH "02" /* 01-12 */ +#define EMLXS_DATE_YEAR "2020" /* YYYY */ #define EMLXS_REVISION EMLXS_DATE_YEAR "." EMLXS_DATE_MONTH "." \ EMLXS_DATE_DAY "." EMLXS_DATE_HOUR "." \ diff --git a/usr/src/uts/common/sys/fibre-channel/impl/fctl.h b/usr/src/uts/common/sys/fibre-channel/impl/fctl.h index 8b672e82ef..45b90f6009 100644 --- a/usr/src/uts/common/sys/fibre-channel/impl/fctl.h +++ b/usr/src/uts/common/sys/fibre-channel/impl/fctl.h @@ -21,6 +21,7 @@ /* * Copyright 2009 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. + * Copyright 2020 RackTop Systems, Inc. */ #ifndef _FCTL_H @@ -67,6 +68,7 @@ extern "C" { #define FC_STATE_10GBIT_SPEED 0x0600 /* 10 Gbit/sec */ #define FC_STATE_8GBIT_SPEED 0x0700 /* 8 Gbit/sec */ #define FC_STATE_16GBIT_SPEED 0x0800 /* 16 Gbit/sec */ +#define FC_STATE_32GBIT_SPEED 0x0900 /* 32 Gbit/sec */ #define FC_STATE_FULL_SPEED FC_STATE_1GBIT_SPEED #define FC_STATE_DOUBLE_SPEED FC_STATE_2GBIT_SPEED @@ -230,6 +232,7 @@ typedef struct fca_hba_fru_details { #define FC_HBA_PORTSPEED_4GBIT 8 /* 4 GBit/sec */ #define FC_HBA_PORTSPEED_8GBIT 16 /* 8 GBit/sec */ #define FC_HBA_PORTSPEED_16GBIT 32 /* 16 GBit/sec */ +#define FC_HBA_PORTSPEED_32GBIT 64 /* 32 GBit/sec */ #define FC_HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) /* Speed not established */ #define FCHBA_MANUFACTURER_LEN 64 diff --git a/usr/src/uts/common/syscall/rw.c b/usr/src/uts/common/syscall/rw.c index e7261b8a99..14f6d278a1 100644 --- a/usr/src/uts/common/syscall/rw.c +++ b/usr/src/uts/common/syscall/rw.c @@ -22,11 +22,11 @@ /* * Copyright 2008 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. - * Copyright 2017, Joyent, Inc. + * Copyright 2020, Joyent, Inc. */ /* Copyright (c) 1983, 1984, 1985, 1986, 1987, 1988, 1989 AT&T */ -/* All Rights Reserved */ +/* All Rights Reserved */ /* * Portions of this source code were derived from Berkeley 4.3 BSD @@ -1087,7 +1087,7 @@ preadv(int fdes, struct iovec *iovp, int iovcnt, off_t offset, } } - if ((bcount = (ssize_t)count) < 0) { + if ((bcount = count) < 0) { if (aiovlen != 0) kmem_free(aiov, aiovlen); return (set_errno(EINVAL)); @@ -1105,7 +1105,7 @@ preadv(int fdes, struct iovec *iovp, int iovcnt, off_t offset, rwflag = 0; /* - * Behaviour is same as read(2). Please see comments in read(2). + * Behaviour is same as read(2). Please see comments in read above. */ if (vp->v_type == VREG) { if (bcount == 0) @@ -1288,7 +1288,7 @@ pwritev(int fdes, struct iovec *iovp, int iovcnt, off_t offset, } } - if ((bcount = (ssize_t)count) < 0) { + if ((bcount = count) < 0) { if (aiovlen != 0) kmem_free(aiov, aiovlen); return (set_errno(EINVAL)); @@ -1306,8 +1306,8 @@ pwritev(int fdes, struct iovec *iovp, int iovcnt, off_t offset, rwflag = 1; /* - * The kernel's write(2) code checks the rctl & OFFSET_MAX and returns - * EFBIG when fileoff exceeds either limit. We do the same. + * The kernel's write(2) code checks OFFSET_MAX and the rctl, and + * returns EFBIG when fileoff exceeds either limit. We do the same. */ if (vp->v_type == VREG) { if (bcount == 0) diff --git a/usr/src/uts/intel/os/driver_aliases b/usr/src/uts/intel/os/driver_aliases index f5b0a08489..7d93686b9e 100644 --- a/usr/src/uts/intel/os/driver_aliases +++ b/usr/src/uts/intel/os/driver_aliases @@ -491,6 +491,8 @@ emlxs "pci10df,fc10" emlxs "pci10df,fc20" emlxs "pci10df,fd00" emlxs "pci10df,fe00" +emlxs "pciex10df,e200" +emlxs "pciex10df,e300" emlxs "pciex10df,f100" emlxs "pciex10df,f111" emlxs "pciex10df,f112" @@ -498,6 +500,10 @@ emlxs "pciex10df,fc20" emlxs "pciex10df,fc40" emlxs "pciex10df,fe00" emlxs "pciex10df,fe05" +emlxs "pciex117c,63" +emlxs "pciex117c,64" +emlxs "pciex117c,65" +emlxs "pciex117c,94" emlxs "pciex19a2,704" emlxs "pciex19a2,714" fipe "pci8086,25f0" |