diff options
Diffstat (limited to 'usr/src/uts/common/sys/elf.h')
| -rw-r--r-- | usr/src/uts/common/sys/elf.h | 374 |
1 files changed, 285 insertions, 89 deletions
diff --git a/usr/src/uts/common/sys/elf.h b/usr/src/uts/common/sys/elf.h index 3b7a1e3d7c..0dd4f2d17e 100644 --- a/usr/src/uts/common/sys/elf.h +++ b/usr/src/uts/common/sys/elf.h @@ -20,7 +20,7 @@ */ /* * Copyright 2012 DEY Storage Systems, Inc. All rights reserved. - * Copyright (c) 2013, Joyent, Inc. All rights reserved. + * Copyright (c) 2018, Joyent, Inc. */ /* * Copyright 2010 Sun Microsystems, Inc. All rights reserved. @@ -148,30 +148,30 @@ typedef struct { #define ET_LOPROC 0xff00 /* processor specific range */ #define ET_HIPROC 0xffff -#define EM_NONE 0 /* e_machine */ -#define EM_M32 1 /* AT&T WE 32100 */ -#define EM_SPARC 2 /* Sun SPARC */ -#define EM_386 3 /* Intel 80386 */ -#define EM_68K 4 /* Motorola 68000 */ -#define EM_88K 5 /* Motorola 88000 */ -#define EM_486 6 /* Intel 80486 */ -#define EM_860 7 /* Intel i860 */ -#define EM_MIPS 8 /* MIPS RS3000 Big-Endian */ -#define EM_S370 9 /* IBM System/370 Processor */ -#define EM_MIPS_RS3_LE 10 /* MIPS RS3000 Little-Endian */ -#define EM_RS6000 11 /* RS6000 */ +#define EM_NONE 0 /* e_machine */ +#define EM_M32 1 /* AT&T WE 32100 */ +#define EM_SPARC 2 /* Sun SPARC */ +#define EM_386 3 /* Intel 80386 */ +#define EM_68K 4 /* Motorola 68000 */ +#define EM_88K 5 /* Motorola 88000 */ +#define EM_486 6 /* Intel 80486 */ +#define EM_860 7 /* Intel i860 */ +#define EM_MIPS 8 /* MIPS RS3000 Big-Endian */ +#define EM_S370 9 /* IBM System/370 Processor */ +#define EM_MIPS_RS3_LE 10 /* MIPS RS3000 Little-Endian */ +#define EM_RS6000 11 /* RS6000 */ #define EM_UNKNOWN12 12 #define EM_UNKNOWN13 13 #define EM_UNKNOWN14 14 -#define EM_PA_RISC 15 /* PA-RISC */ +#define EM_PA_RISC 15 /* PA-RISC */ #define EM_PARISC EM_PA_RISC /* Alias: GNU compatibility */ -#define EM_nCUBE 16 /* nCUBE */ -#define EM_VPP500 17 /* Fujitsu VPP500 */ -#define EM_SPARC32PLUS 18 /* Sun SPARC 32+ */ -#define EM_960 19 /* Intel 80960 */ -#define EM_PPC 20 /* PowerPC */ -#define EM_PPC64 21 /* 64-bit PowerPC */ -#define EM_S390 22 /* IBM System/390 Processor */ +#define EM_nCUBE 16 /* nCUBE */ +#define EM_VPP500 17 /* Fujitsu VPP500 */ +#define EM_SPARC32PLUS 18 /* Sun SPARC 32+ */ +#define EM_960 19 /* Intel 80960 */ +#define EM_PPC 20 /* PowerPC */ +#define EM_PPC64 21 /* 64-bit PowerPC */ +#define EM_S390 22 /* IBM System/390 Processor */ #define EM_UNKNOWN22 EM_S390 /* Alias: Older published name */ #define EM_UNKNOWN23 23 #define EM_UNKNOWN24 24 @@ -186,78 +186,226 @@ typedef struct { #define EM_UNKNOWN33 33 #define EM_UNKNOWN34 34 #define EM_UNKNOWN35 35 -#define EM_V800 36 /* NEX V800 */ -#define EM_FR20 37 /* Fujitsu FR20 */ -#define EM_RH32 38 /* TRW RH-32 */ -#define EM_RCE 39 /* Motorola RCE */ -#define EM_ARM 40 /* Advanced RISC Marchines ARM */ -#define EM_ALPHA 41 /* Digital Alpha */ -#define EM_SH 42 /* Hitachi SH */ -#define EM_SPARCV9 43 /* Sun SPARC V9 (64-bit) */ -#define EM_TRICORE 44 /* Siemens Tricore embedded processor */ -#define EM_ARC 45 /* Argonaut RISC Core, */ - /* Argonaut Technologies Inc. */ -#define EM_H8_300 46 /* Hitachi H8/300 */ -#define EM_H8_300H 47 /* Hitachi H8/300H */ -#define EM_H8S 48 /* Hitachi H8S */ -#define EM_H8_500 49 /* Hitachi H8/500 */ -#define EM_IA_64 50 /* Intel IA64 */ -#define EM_MIPS_X 51 /* Stanford MIPS-X */ -#define EM_COLDFIRE 52 /* Motorola ColdFire */ -#define EM_68HC12 53 /* Motorola M68HC12 */ -#define EM_MMA 54 /* Fujitsu MMA Mulimedia Accelerator */ -#define EM_PCP 55 /* Siemens PCP */ -#define EM_NCPU 56 /* Sony nCPU embedded RISC processor */ -#define EM_NDR1 57 /* Denso NDR1 microprocessor */ -#define EM_STARCORE 58 /* Motorola Star*Core processor */ -#define EM_ME16 59 /* Toyota ME16 processor */ -#define EM_ST100 60 /* STMicroelectronics ST100 processor */ -#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ */ - /* embedded processor family */ -#define EM_AMD64 62 /* AMDs x86-64 architecture */ +#define EM_V800 36 /* NEX V800 */ +#define EM_FR20 37 /* Fujitsu FR20 */ +#define EM_RH32 38 /* TRW RH-32 */ +#define EM_RCE 39 /* Motorola RCE */ +#define EM_ARM 40 /* Advanced RISC Marchines ARM */ +#define EM_ALPHA 41 /* Digital Alpha */ +#define EM_SH 42 /* Hitachi SH */ +#define EM_SPARCV9 43 /* Sun SPARC V9 (64-bit) */ +#define EM_TRICORE 44 /* Siemens Tricore embedded processor */ +#define EM_ARC 45 /* Argonaut RISC Core, */ + /* Argonaut Technologies Inc. */ +#define EM_H8_300 46 /* Hitachi H8/300 */ +#define EM_H8_300H 47 /* Hitachi H8/300H */ +#define EM_H8S 48 /* Hitachi H8S */ +#define EM_H8_500 49 /* Hitachi H8/500 */ +#define EM_IA_64 50 /* Intel IA64 */ +#define EM_MIPS_X 51 /* Stanford MIPS-X */ +#define EM_COLDFIRE 52 /* Motorola ColdFire */ +#define EM_68HC12 53 /* Motorola M68HC12 */ +#define EM_MMA 54 /* Fujitsu MMA Mulimedia Accelerator */ +#define EM_PCP 55 /* Siemens PCP */ +#define EM_NCPU 56 /* Sony nCPU embedded RISC processor */ +#define EM_NDR1 57 /* Denso NDR1 microprocessor */ +#define EM_STARCORE 58 /* Motorola Star*Core processor */ +#define EM_ME16 59 /* Toyota ME16 processor */ +#define EM_ST100 60 /* STMicroelectronics ST100 processor */ +#define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ */ + /* embedded processor family */ +#define EM_AMD64 62 /* AMDs x86-64 architecture */ #define EM_X86_64 EM_AMD64 /* (compatibility) */ -#define EM_PDSP 63 /* Sony DSP Processor */ +#define EM_PDSP 63 /* Sony DSP Processor */ #define EM_UNKNOWN64 64 #define EM_UNKNOWN65 65 -#define EM_FX66 66 /* Siemens FX66 microcontroller */ -#define EM_ST9PLUS 67 /* STMicroelectronics ST9+8/16 bit */ - /* microcontroller */ -#define EM_ST7 68 /* STMicroelectronics ST7 8-bit */ - /* microcontroller */ -#define EM_68HC16 69 /* Motorola MC68HC16 Microcontroller */ -#define EM_68HC11 70 /* Motorola MC68HC11 Microcontroller */ -#define EM_68HC08 71 /* Motorola MC68HC08 Microcontroller */ -#define EM_68HC05 72 /* Motorola MC68HC05 Microcontroller */ -#define EM_SVX 73 /* Silicon Graphics SVx */ -#define EM_ST19 74 /* STMicroelectronics ST19 8-bit */ - /* microcontroller */ -#define EM_VAX 75 /* Digital VAX */ -#define EM_CRIS 76 /* Axis Communications 32-bit */ - /* embedded processor */ -#define EM_JAVELIN 77 /* Infineon Technologies 32-bit */ - /* embedded processor */ -#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ -#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ -#define EM_MMIX 80 /* Donald Knuth's educational */ - /* 64-bit processor */ -#define EM_HUANY 81 /* Harvard University */ - /* machine-independent */ - /* object files */ -#define EM_PRISM 82 /* SiTera Prism */ -#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ -#define EM_FR30 84 /* Fujitsu FR30 */ -#define EM_D10V 85 /* Mitsubishi D10V */ -#define EM_D30V 86 /* Mitsubishi D30V */ -#define EM_V850 87 /* NEC v850 */ -#define EM_M32R 88 /* Mitsubishi M32R */ -#define EM_MN10300 89 /* Matsushita MN10300 */ -#define EM_MN10200 90 /* Matsushita MN10200 */ -#define EM_PJ 91 /* picoJava */ -#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ -#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ -#define EM_XTENSA 94 /* Tensilica Xtensa architecture */ -#define EM_NUM 95 +#define EM_FX66 66 /* Siemens FX66 microcontroller */ +#define EM_ST9PLUS 67 /* STMicroelectronics ST9+8/16 bit */ + /* microcontroller */ +#define EM_ST7 68 /* STMicroelectronics ST7 8-bit */ + /* microcontroller */ +#define EM_68HC16 69 /* Motorola MC68HC16 Microcontroller */ +#define EM_68HC11 70 /* Motorola MC68HC11 Microcontroller */ +#define EM_68HC08 71 /* Motorola MC68HC08 Microcontroller */ +#define EM_68HC05 72 /* Motorola MC68HC05 Microcontroller */ +#define EM_SVX 73 /* Silicon Graphics SVx */ +#define EM_ST19 74 /* STMicroelectronics ST19 8-bit */ + /* microcontroller */ +#define EM_VAX 75 /* Digital VAX */ +#define EM_CRIS 76 /* Axis Communications 32-bit */ + /* embedded processor */ +#define EM_JAVELIN 77 /* Infineon Technologies 32-bit */ + /* embedded processor */ +#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ +#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ +#define EM_MMIX 80 /* Donald Knuth's educational */ + /* 64-bit processor */ +#define EM_HUANY 81 /* Harvard University */ + /* machine-independent */ + /* object files */ +#define EM_PRISM 82 /* SiTera Prism */ +#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ +#define EM_FR30 84 /* Fujitsu FR30 */ +#define EM_D10V 85 /* Mitsubishi D10V */ +#define EM_D30V 86 /* Mitsubishi D30V */ +#define EM_V850 87 /* NEC v850 */ +#define EM_M32R 88 /* Mitsubishi M32R */ +#define EM_MN10300 89 /* Matsushita MN10300 */ +#define EM_MN10200 90 /* Matsushita MN10200 */ +#define EM_PJ 91 /* picoJava */ +#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ +#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ +#define EM_XTENSA 94 /* Tensilica Xtensa architecture */ + +#define EM_VIDEOCORE 95 /* Alphamosaic VideoCore processor */ +#define EM_TMM_GPP 96 /* Thompson Multimedia General Purpose */ + /* Processor */ +#define EM_NS32K 97 /* National Semiconductor 32000 series */ +#define EM_TPC 98 /* Tenor Network TPC processor */ +#define EM_SNP1K 99 /* Trebia SNP 1000 processor */ +#define EM_ST200 100 /* STMicroelectronics (www.st.com) ST200 */ + /* microcontroller */ +#define EM_IP2K 101 /* Ubicom IP2xxx microcontroller family */ +#define EM_MAX 102 /* MAX Processor */ +#define EM_CR 103 /* National Semiconductor CompactRISC */ + /* microprocessor */ +#define EM_F2MC16 104 /* Fujitsu F2MC16 */ +#define EM_MSP430 105 /* Texas Instruments embedded microcontroller */ + /* msp430 */ +#define EM_BLACKFIN 106 /* Analog Devices Blackfin (DSP) processor */ +#define EM_SE_C33 107 /* S1C33 Family of Seiko Epson processors */ +#define EM_SEP 108 /* Sharp embedded microprocessor */ +#define EM_ARCA 109 /* Arca RISC Microprocessor */ +#define EM_UNICORE 110 /* Microprocessor series from PKU-Unity Ltd. */ + /* and MPRC of Peking University */ +#define EM_EXCESS 111 /* eXcess: 16/32/64-bit configurable embedded */ + /* CPU */ +#define EM_DXP 112 /* Icera Semiconductor Inc. Deep Execution */ + /* Processor */ +#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */ +#define EM_CRX 114 /* National Semiconductor CompactRISC CRX */ + /* microprocessor */ +#define EM_XGATE 115 /* Motorola XGATE embedded processor */ +#define EM_C166 116 /* Infineon C16x/XC16x processor */ +#define EM_M16C 117 /* Renesas M16C series microprocessors */ +#define EM_DSPIC30F 118 /* Microchip Technology dsPIC30F Digital */ + /* Signal Controller */ +#define EM_CE 119 /* Freescale Communication Engine RISC core */ +#define EM_M32C 120 /* Renesas M32C series microprocessors */ + +#define EM_TSK3000 131 /* Altium TSK3000 core */ +#define EM_RS08 132 /* Freescale RS08 embedded processor */ +#define EM_SHARC 133 /* Analog Devices SHARC family of 32-bit DSP */ + /* processors */ +#define EM_ECOG2 134 /* Cyan Technology eCOG2 microprocessor */ +#define EM_SCORE7 135 /* Sunplus S+core7 RISC processor */ +#define EM_DSP24 136 /* New Japan Radio (NJR) 24-bit DSP Processor */ +#define EM_VIDEOCORE3 137 /* Broadcom VideoCore III processor */ +#define EM_LATTICEMICO32 138 /* RISC processor for Lattice FPGA */ + /* architecture */ +#define EM_SE_C17 139 /* Seiko Epson C17 family */ +#define EM_TI_C6000 140 /* The Texas Instruments TMS320C6000 DSP */ + /* family */ +#define EM_TI_C2000 141 /* The Texas Instruments TMS320C2000 DSP */ + /* family */ +#define EM_TI_C5500 142 /* The Texas Instruments TMS320C55x DSP */ + /* family */ +#define EM_TI_ARP32 143 /* Texas Instruments Application Specific */ + /* RISC Processor, 32bit fetch */ +#define EM_TI_PRU 144 /* Texas Instruments Programmable Realtime */ + /* Unit */ + +#define EM_MMDSP_PLUS 160 /* STMicroelectronics 64bit VLIW Data Signal */ + /* Processor */ +#define EM_CYPRESS_M8C 161 /* Cypress M8C microprocessor */ +#define EM_R32C 162 /* Renesas R32C series microprocessors */ +#define EM_TRIMEDIA 163 /* NXP Semiconductors TriMedia architecture */ + /* family */ +#define EM_QDSP6 164 /* QUALCOMM DSP6 Processor */ +#define EM_8051 165 /* Intel 8051 and variants */ +#define EM_STXP7X 166 /* STMicroelectronics STxP7x family of */ + /* configurable and extensible RISC */ + /* processors */ +#define EM_NDS32 167 /* Andes Technology compact code size */ + /* embedded RISC processor family */ +#define EM_ECOG1 168 /* Cyan Technology eCOG1X family */ +#define EM_ECOG1X EM_EC0G1X /* Cyan Technology eCOG1X family */ +#define EM_MAXQ30 169 /* Dallas Semiconductor MAXQ30 Core */ + /* Micro-controllers */ +#define EM_XIMO16 170 /* New Japan Radio (NJR) 16-bit DSP Processor */ +#define EM_MANIK 171 /* M2000 Reconfigurable RISC Microprocessor */ +#define EM_CRAYNV2 172 /* Cray Inc. NV2 vector architecture */ +#define EM_RX 173 /* Renesas RX family */ +#define EM_METAG 174 /* Imagination Technologies META processor */ + /* architecture */ +#define EM_MCST_ELBRUS 175 /* MCST Elbrus general purpose hardware */ + /* architecture */ +#define EM_ECOG16 176 /* Cyan Technology eCOG16 family */ +#define EM_CR16 177 /* National Semiconductor CompactRISC */ + /* CR16 16-bit microprocessor */ +#define EM_ETPU 178 /* Freescale Extended Time Processing Unit */ +#define EM_SLE9X 179 /* Infineon Technologies SLE9X core */ +#define EM_L10M 180 /* Intel L10M */ +#define EM_K10M 181 /* Intel K10M */ + +#define EM_AARCH64 183 /* ARM 64-bit architecture (AARCH64) */ + +#define EM_AVR32 185 /* Atmel Corporation 32-bit microprocessor */ + /* family */ +#define EM_STM8 186 /* STMicroeletronics STM8 8-bit */ + /* microcontroller */ +#define EM_TILE64 187 /* Tilera TILE64 multicore architecture */ + /* family */ +#define EM_TILEPRO 188 /* Tilera TILEPro multicore architecture */ + /* family */ +#define EM_MICROBLAZE 189 /* Xilinx MicroBlaze 32-bit RISC soft */ + /* processor core */ +#define EM_CUDA 190 /* NVIDIA CUDA architecture */ +#define EM_TILEGX 191 /* Tilera TILE-Gx multicore architecture */ + /* family */ +#define EM_CLOUDSHIELD 192 /* CloudShield architecture family */ +#define EM_COREA_1ST 193 /* KIPO-KAIST Core-A 1st generation processor */ + /* family */ +#define EM_COREA_2ND 194 /* KIPO-KAIST Core-A 2nd generation processor */ + /* family */ +#define EM_ARC_COMPACT2 195 /* Synopsys ARCompact V2 */ +#define EM_OPEN8 196 /* Open8 8-bit RISC soft processor core */ +#define EM_RL78 197 /* Renesas RL78 family */ +#define EM_VIDEOCORE5 198 /* Broadcom VideoCore V processor */ +#define EM_78KOR 199 /* Renesas 78KOR family */ +#define EM_56800EX 200 /* Freescale 56800EX Digital Signal */ + /* Controller (DSC) */ +#define EM_BA1 201 /* Beyond BA1 CPU architecture */ +#define EM_BA2 202 /* Beyond BA2 CPU architecture */ +#define EM_XCORE 203 /* XMOS xCORE processor family */ +#define EM_MCHP_PIC 204 /* Microchip 8-bit PIC(r) family */ +#define EM_INTEL205 205 /* Reserved by Intel */ +#define EM_INTEL206 206 /* Reserved by Intel */ +#define EM_INTEL207 207 /* Reserved by Intel */ +#define EM_INTEL208 208 /* Reserved by Intel */ +#define EM_INTEL209 209 /* Reserved by Intel */ +#define EM_KM32 210 /* KM211 KM32 32-bit processor */ +#define EM_KMX32 211 /* KM211 KMX32 32-bit processor */ +#define EM_KMX16 212 /* KM211 KMX16 16-bit processor */ +#define EM_KMX8 213 /* KM211 KMX8 8-bit processor */ +#define EM_KVARC 214 /* KM211 KVARC processor */ +#define EM_CDP 215 /* Paneve CDP architecture family */ +#define EM_COGE 216 /* Cognitive Smart Memory Processor */ +#define EM_COOL 217 /* Bluechip Systems CoolEngine */ +#define EM_NORC 218 /* Nanoradio Optimized RISC */ +#define EM_CSR_KALIMBA 219 /* CSR Kalimba architecture family */ +#define EM_Z80 220 /* Zilog Z80 */ +#define EM_VISIUM 221 /* Controls and Data Services VISIUMcore */ + /* processor */ +#define EM_FT32 222 /* FTDI Chip FT32 high performance 32-bit */ + /* RISC architecture */ +#define EM_MOXIE 223 /* Moxie processor family */ +#define EM_AMDGPU 224 /* AMD GPU architecture */ + +#define EM_RISCV 243 /* RISC-V */ + +#define EM_NUM 244 #define EV_NONE 0 /* e_version, EI_VERSION */ #define EV_CURRENT 1 @@ -281,6 +429,10 @@ typedef struct { #define ELFOSABI_OPENVMS 13 /* Open VMS */ #define ELFOSABI_NSK 14 /* Hewlett-Packard Non-Stop Kernel */ #define ELFOSABI_AROS 15 /* Amiga Research OS */ +#define ELFOSABI_FENIXOS 16 /* The FenixOS highly scalable */ + /* multi-core OS */ +#define ELFOSABI_CLOUDABI 17 /* Nuxi CloudABI */ +#define ELFOSABI_OPENVOS 18 /* Stratus Technologies OpenVOS */ #define ELFOSABI_ARM 97 /* ARM */ #define ELFOSABI_STANDALONE 255 /* standalone (embedded) application */ @@ -348,6 +500,11 @@ typedef struct { #define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ #define PT_GNU_RELRO 0x6474e552 /* Read-only after relocation */ +/* + * Linux specific program headers not even used by Linux (!!) + */ +#define PT_PAX_FLAGS 0x65041580 /* PaX flags (see below) */ + #define PT_LOSUNW 0x6ffffffa #define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment (unused) */ #define PT_SUNWSTACK 0x6ffffffb /* describes the stack segment */ @@ -363,6 +520,45 @@ typedef struct { #define PF_W 0x2 #define PF_X 0x1 +/* + * PaX is a regrettable series of never-integrated Linux patches for a + * facility to provide additional protections on memory pages for purposes of + * increasing security, and for allowing binaries to demand (or refuse) those + * protections via the PT_PAX_FLAGS program header. (Portents of its + * rudderless existence, "PaX" is a term of indefinite origin written by an + * unknown group of people.) This facility is unfortunate in any number of + * ways, and was largely obviated by the broad adoption of non-executable + * stacks at any rate -- but it lives on in binaries that continue to mark + * themselves to explicitly refuse the (never-integrated, now-obviated) + * facility. One might cringe that PaX overloads the meaning of the p_flags + * to specify protections, but that is the least of its transgressions: + * instead of using one p_type constant to explicitly enable a series of + * protections and another to explicitly disable others, it insists on + * conflating both actions into PT_PAX_FLAGS. The resulting doubling of + * constant definitions (two constant definitions for every protection instead + * of merely one) assures that the values can't even fit in the eight + * PF_MASKOS bits putatively defined to provide a modicum of cleanliness for + * such filthy functionality. And were all of this not enough, there is one + * final nomenclature insult to be added to this semantic injury: the + * constants for the p_flags don't even embed "_PAX_" in their name -- despite + * the fact that this is their only purpose! We resist the temptation to + * right this final wrong here; we grit our teeth and provide exactly the + * Linux definitions -- or rather, what would have been the Linux definitions + * had this belching jalopy ever been permitted to crash itself into mainline. + */ +#define PF_PAGEEXEC 0x00000010 /* PaX: enable PAGEEXEC */ +#define PF_NOPAGEEXEC 0x00000020 /* PaX: disable PAGEEXEC */ +#define PF_SEGMEXEC 0x00000040 /* PaX: enable SEGMEXEC */ +#define PF_NOSEGMEXEC 0x00000080 /* PaX: disable SEGMEXEC */ +#define PF_MPROTECT 0x00000100 /* PaX: enable MPROTECT */ +#define PF_NOMPROTECT 0x00000200 /* PaX: disable MPROTECT */ +#define PF_RANDEXEC 0x00000400 /* PaX: enable RANDEXEC */ +#define PF_NORANDEXEC 0x00000800 /* PaX: disable RANDEXEC */ +#define PF_EMUTRAMP 0x00001000 /* PaX: enable EMUTRAMP */ +#define PF_NOEMUTRAMP 0x00002000 /* PaX: disable EMUTRAMP */ +#define PF_RANDMMAP 0x00004000 /* PaX: enable RANDMMAP */ +#define PF_NORANDMMAP 0x00008000 /* PaX: disable RANDMMAP */ + #define PF_MASKOS 0x0ff00000 /* OS specific values */ #define PF_MASKPROC 0xf0000000 /* processor specific values */ |