diff options
Diffstat (limited to 'usr/src/uts/i86pc/os/mlsetup.c')
| -rw-r--r-- | usr/src/uts/i86pc/os/mlsetup.c | 23 |
1 files changed, 5 insertions, 18 deletions
diff --git a/usr/src/uts/i86pc/os/mlsetup.c b/usr/src/uts/i86pc/os/mlsetup.c index 9487552564..e1fd081cfa 100644 --- a/usr/src/uts/i86pc/os/mlsetup.c +++ b/usr/src/uts/i86pc/os/mlsetup.c @@ -24,6 +24,7 @@ * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2011 by Delphix. All rights reserved. * Copyright 2019 Joyent, Inc. + * Copyright 2020 Oxide Computer Company */ /* * Copyright (c) 2010, Intel Corporation. @@ -265,30 +266,16 @@ mlsetup(struct regs *rp) * time-stamp counter while ensuring no out-of-order execution. * Patch it while the kernel text is still writable. * - * Note: tsc_read is not patched for intel processors whose family - * is >6 and for amd whose family >f (in case they don't support rdtscp - * instruction, unlikely). By default tsc_read will use cpuid for - * serialization in such cases. The following code needs to be - * revisited if intel processors of family >= f retains the - * instruction serialization nature of mfence instruction. - * Note: tsc_read is not patched for x86 processors which do - * not support "mfence". By default tsc_read will use cpuid for - * serialization in such cases. - * * The Xen hypervisor does not correctly report whether rdtscp is * supported or not, so we must assume that it is not. */ if ((get_hwenv() & HW_XEN_HVM) == 0 && - is_x86_feature(x86_featureset, X86FSET_TSCP)) + is_x86_feature(x86_featureset, X86FSET_TSCP)) { patch_tsc_read(TSC_TSCP); - else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && - cpuid_getfamily(CPU) <= 0xf && - is_x86_feature(x86_featureset, X86FSET_SSE2)) - patch_tsc_read(TSC_RDTSC_MFENCE); - else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && - cpuid_getfamily(CPU) <= 6 && - is_x86_feature(x86_featureset, X86FSET_SSE2)) + } else if (is_x86_feature(x86_featureset, X86FSET_LFENCE_SER)) { + ASSERT(is_x86_feature(x86_featureset, X86FSET_SSE2)); patch_tsc_read(TSC_RDTSC_LFENCE); + } #endif /* !__xpv */ |