diff options
Diffstat (limited to 'usr/src/uts/intel/sys')
| -rw-r--r-- | usr/src/uts/intel/sys/acpi/acpixf.h | 6 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/archsystm.h | 3 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/fp.h | 65 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/machbrand.h | 12 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/segments.h | 2 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/ucontext.h | 15 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/x86_archext.h | 100 |
7 files changed, 176 insertions, 27 deletions
diff --git a/usr/src/uts/intel/sys/acpi/acpixf.h b/usr/src/uts/intel/sys/acpi/acpixf.h index e3382c655f..81e550aedb 100644 --- a/usr/src/uts/intel/sys/acpi/acpixf.h +++ b/usr/src/uts/intel/sys/acpi/acpixf.h @@ -349,7 +349,6 @@ ACPI_GLOBAL (BOOLEAN, AcpiGbl_SystemAwakeAndRunning); #endif /* ACPI_NO_ERROR_MESSAGES */ - /* * Debugging output prototypes (default: no debug output). * @@ -405,6 +404,11 @@ ACPI_GLOBAL (BOOLEAN, AcpiGbl_SystemAwakeAndRunning); #endif /* ACPI_DEBUGGER */ +/***************************************************************************** + * + * ACPICA public interface prototypes + * + ****************************************************************************/ /***************************************************************************** * diff --git a/usr/src/uts/intel/sys/archsystm.h b/usr/src/uts/intel/sys/archsystm.h index e06e79de97..9cfd83a334 100644 --- a/usr/src/uts/intel/sys/archsystm.h +++ b/usr/src/uts/intel/sys/archsystm.h @@ -21,7 +21,7 @@ /* * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. - * Copyright 2015 Joyent, Inc. + * Copyright 2017 Joyent, Inc. */ #ifndef _SYS_ARCHSYSTM_H @@ -60,6 +60,7 @@ extern void patch_sse2(void); #endif extern void patch_xsave(void); +extern kmem_cache_t *fpsave_cachep; extern void cli(void); extern void sti(void); diff --git a/usr/src/uts/intel/sys/fp.h b/usr/src/uts/intel/sys/fp.h index 3373484dec..e6d482fdd8 100644 --- a/usr/src/uts/intel/sys/fp.h +++ b/usr/src/uts/intel/sys/fp.h @@ -20,6 +20,7 @@ */ /* * Copyright 2015 Nexenta Systems, Inc. All rights reserved. + * Copyright 2017 Joyent, Inc. * * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved. */ @@ -229,27 +230,59 @@ struct fxsave_state { }; /* 512 bytes */ /* - * This structure is written to memory by an 'xsave' instruction. - * First 512 byte is compatible with the format of an 'fxsave' area. + * This structure is written to memory by one of the 'xsave' instruction + * variants. The first 512 bytes are compatible with the format of the 'fxsave' + * area. The header portion of the xsave layout is documented in section + * 13.4.2 of the Intel 64 and IA-32 Architectures Software Developer’s Manual, + * Volume 1 (IASDv1). The extended portion is documented in section 13.4.3. + * + * Our size is at least AVX_XSAVE_SIZE (832 bytes), asserted in fpnoextflt(). + * Enabling additional xsave-related CPU features requires an increase in the + * size. We dynamically allocate the per-lwp xsave area at runtime, based on + * the size needed for the CPU-specific features. This xsave_state structure + * simply defines our historical layout for the beginning of the xsave area. The + * locations and size of new, extended, components is determined dynamically by + * querying the CPU. See the xsave_info structure in cpuid.c. + * + * xsave component usage is tracked using bits in the xs_xstate_bv field. The + * components are documented in section 13.1 of IASDv1. For easy reference, + * this is a summary of the currently defined component bit definitions: + * x87 0x0001 + * SSE 0x0002 + * AVX 0x0004 + * bndreg (MPX) 0x0008 + * bndcsr (MPX) 0x0010 + * opmask (AVX512) 0x0020 + * zmm hi256 (AVX512) 0x0040 + * zmm hi16 (AVX512) 0x0080 + * PT 0x0100 + * PKRU 0x0200 + * When xsaveopt_ctxt is being used to save into the xsave_state area, the + * xs_xstate_bv field is updated by the xsaveopt instruction to indicate which + * elements of the xsave area are active. + * + * xs_xcomp_bv should always be 0, since we do not currently use the compressed + * form of xsave (xsavec). */ struct xsave_state { - struct fxsave_state xs_fxsave; - uint64_t xs_xstate_bv; /* 512 */ - uint64_t xs_rsv_mbz[2]; - uint64_t xs_reserved[5]; - upad128_t xs_ymm[16]; /* avx - 576 */ -}; /* 832 bytes, asserted in fpnoextflt() */ + struct fxsave_state xs_fxsave; /* 0-511 legacy region */ + uint64_t xs_xstate_bv; /* 512-519 start xsave header */ + uint64_t xs_xcomp_bv; /* 520-527 */ + uint64_t xs_reserved[6]; /* 528-575 end xsave header */ + upad128_t xs_ymm[16]; /* 576 AVX component */ +}; /* * Kernel's FPU save area */ typedef struct { union _kfpu_u { - struct fxsave_state kfpu_fx; + void *kfpu_generic; + struct fxsave_state *kfpu_fx; #if defined(__i386) - struct fnsave_state kfpu_fn; + struct fnsave_state *kfpu_fn; #endif - struct xsave_state kfpu_xs; + struct xsave_state *kfpu_xs; } kfpu_u; uint32_t kfpu_status; /* saved at #mf exception */ uint32_t kfpu_xstatus; /* saved at #xm exception */ @@ -273,7 +306,12 @@ extern int fpu_probe_pentium_fdivbug(void); extern void fpnsave_ctxt(void *); extern void fpxsave_ctxt(void *); extern void xsave_ctxt(void *); +extern void xsaveopt_ctxt(void *); +extern void fpxsave_excp_clr_ctxt(void *); +extern void xsave_excp_clr_ctxt(void *); +extern void xsaveopt_excp_clr_ctxt(void *); extern void (*fpsave_ctxt)(void *); +extern void (*xsavep)(struct xsave_state *, uint64_t); extern void fxsave_insn(struct fxsave_state *); extern void fpsave(struct fnsave_state *); @@ -281,6 +319,7 @@ extern void fprestore(struct fnsave_state *); extern void fpxsave(struct fxsave_state *); extern void fpxrestore(struct fxsave_state *); extern void xsave(struct xsave_state *, uint64_t); +extern void xsaveopt(struct xsave_state *, uint64_t); extern void xrestore(struct xsave_state *, uint64_t); extern void fpenable(void); @@ -299,6 +338,10 @@ extern int fpextovrflt(struct regs *); extern int fpexterrflt(struct regs *); extern int fpsimderrflt(struct regs *); extern void fpsetcw(uint16_t, uint32_t); +struct _klwp; +extern void fp_lwp_init(struct _klwp *); +extern void fp_lwp_cleanup(struct _klwp *); +extern void fp_lwp_dup(struct _klwp *); #endif /* _KERNEL */ diff --git a/usr/src/uts/intel/sys/machbrand.h b/usr/src/uts/intel/sys/machbrand.h index 3f9ebdb6b7..ad7f631649 100644 --- a/usr/src/uts/intel/sys/machbrand.h +++ b/usr/src/uts/intel/sys/machbrand.h @@ -20,6 +20,7 @@ */ /* * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright 2016 Joyent, Inc. */ #ifndef _SYS_MACHBRAND_H @@ -32,20 +33,25 @@ extern "C" { #ifndef _ASM #include <sys/model.h> +#include <sys/thread.h> struct brand_mach_ops { void (*b_sysenter)(void); + void (*b_int80)(void); void (*b_int91)(void); void (*b_syscall)(void); void (*b_syscall32)(void); + greg_t (*b_fixsegreg)(greg_t, model_t); + uintptr_t (*b_fsbase)(klwp_t *, uintptr_t); }; #endif /* _ASM */ #define BRAND_CB_SYSENTER 0 -#define BRAND_CB_INT91 1 -#define BRAND_CB_SYSCALL 2 -#define BRAND_CB_SYSCALL32 3 +#define BRAND_CB_INT80 1 +#define BRAND_CB_INT91 2 +#define BRAND_CB_SYSCALL 3 +#define BRAND_CB_SYSCALL32 4 #ifdef __cplusplus } diff --git a/usr/src/uts/intel/sys/segments.h b/usr/src/uts/intel/sys/segments.h index e405f9673c..5368f80735 100644 --- a/usr/src/uts/intel/sys/segments.h +++ b/usr/src/uts/intel/sys/segments.h @@ -684,6 +684,8 @@ extern void _start(), cmnint(); extern void achktrap(), mcetrap(); extern void xmtrap(); extern void fasttrap(); +extern void sys_int80(); +extern void brand_sys_int80(); extern void dtrace_ret(); #if !defined(__amd64) diff --git a/usr/src/uts/intel/sys/ucontext.h b/usr/src/uts/intel/sys/ucontext.h index 66300e71a1..2d4e39b3e8 100644 --- a/usr/src/uts/intel/sys/ucontext.h +++ b/usr/src/uts/intel/sys/ucontext.h @@ -20,6 +20,7 @@ */ /* + * Copyright 2015 Joyent, Inc. * Copyright 2015 Nexenta Systems, Inc. All rights reserved. * * Copyright 2010 Sun Microsystems, Inc. All rights reserved. @@ -84,9 +85,16 @@ struct __ucontext { sigset_t uc_sigmask; stack_t uc_stack; mcontext_t uc_mcontext; - long uc_filler[5]; /* see ABI spec for Intel386 */ + /* + * The Intel386 ABI specification includes a 5-element array of longs + * called "uc_filler", padding the size of the struct to 512 bytes. To + * allow zone brands to communicate extra data right the way through + * the signal handling process, from sigacthandler to setcontext, we + * steal the first three of these longs as a brand-private member. + */ + void *uc_brand_data[3]; + long uc_filler[2]; }; - #if defined(_SYSCALL32) /* Kernel view of user ILP32 ucontext structure */ @@ -97,7 +105,8 @@ typedef struct ucontext32 { sigset_t uc_sigmask; stack32_t uc_stack; mcontext32_t uc_mcontext; - int32_t uc_filler[5]; + caddr32_t uc_brand_data[3]; + int32_t uc_filler[2]; } ucontext32_t; #if defined(_KERNEL) diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h index 713a7600fa..646aa5ac81 100644 --- a/usr/src/uts/intel/sys/x86_archext.h +++ b/usr/src/uts/intel/sys/x86_archext.h @@ -28,7 +28,7 @@ * All rights reserved. */ /* - * Copyright 2016 Joyent, Inc. + * Copyright 2017 Joyent, Inc. * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> @@ -91,7 +91,7 @@ extern "C" { #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ - /* 0x00000004 - reserved */ +#define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ @@ -104,15 +104,16 @@ extern "C" { #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ - /* 0x00008000 - reserved */ +#define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ /* 0x00010000 - reserved */ - /* 0x00020000 - reserved */ +#define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ +#define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ @@ -170,12 +171,25 @@ extern "C" { #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ -#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ +#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */ #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ + /* 0x00004000 - reserved */ +#define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ +#define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ + /* 0x00020000 - reserved */ + /* 0x00040000 - reserved */ +#define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ + /* 0x00100000 - reserved */ +#define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ /* + * AMD uses %ebx for some of their features (extended function 0x80000008). + */ +#define CPUID_AMD_EBX_ERR_PTR_ZERO 0x00000004 /* AMD: FP Err. Ptr. Zero */ + +/* * Intel now seems to have claimed part of the "extended" function * space that we previously for non-Intel implementors to use. * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF @@ -192,12 +206,54 @@ extern "C" { * specifically label the EBX features with their leaf and sub-leaf. */ #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */ +#define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */ #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */ #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */ #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */ +#define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */ +#define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */ +#define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */ #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */ #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */ #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */ +#define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */ +#define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */ +#define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */ +#define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */ +#define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */ +#define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */ +#define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */ +#define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */ + +#define CPUID_INTC_EBX_7_0_ALL_AVX512 \ + (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \ + CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \ + CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \ + CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL) + +#define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */ +#define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */ +#define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */ +#define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */ +#define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */ + +#define CPUID_INTC_ECX_7_0_ALL_AVX512 \ + (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ) + +#define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */ +#define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */ + +#define CPUID_INTC_EDX_7_0_ALL_AVX512 \ + (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS) + +/* + * Intel also uses cpuid leaf 0xd to report additional instructions and features + * when the sub-leaf in %ecx == 1. We label these using the same convention as + * with leaf 7. + */ +#define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */ +#define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */ +#define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */ #define P5_MCHADDR 0x0 #define P5_CESR 0x11 @@ -376,6 +432,26 @@ extern "C" { #define X86FSET_SMAP 46 #define X86FSET_ADX 47 #define X86FSET_RDSEED 48 +#define X86FSET_MPX 49 +#define X86FSET_AVX512F 50 +#define X86FSET_AVX512DQ 51 +#define X86FSET_AVX512PF 52 +#define X86FSET_AVX512ER 53 +#define X86FSET_AVX512CD 54 +#define X86FSET_AVX512BW 55 +#define X86FSET_AVX512VL 56 +#define X86FSET_AVX512FMA 57 +#define X86FSET_AVX512VBMI 58 +#define X86FSET_AVX512VPOPCDQ 59 +#define X86FSET_AVX512NNIW 60 +#define X86FSET_AVX512FMAPS 61 +#define X86FSET_XSAVEOPT 62 +#define X86FSET_XSAVEC 63 +#define X86FSET_XSAVES 64 +#define X86FSET_SHA 65 +#define X86FSET_UMIP 66 +#define X86FSET_PKU 67 +#define X86FSET_OSPKE 68 /* * Intel Deep C-State invariant TSC in leaf 0x80000007. @@ -611,24 +687,30 @@ extern "C" { /* * xgetbv/xsetbv support + * See section 13.3 in vol. 1 of the Intel devlopers manual. */ #define XFEATURE_ENABLED_MASK 0x0 /* * XFEATURE_ENABLED_MASK values (eax) + * See setup_xfem(). */ #define XFEATURE_LEGACY_FP 0x1 #define XFEATURE_SSE 0x2 #define XFEATURE_AVX 0x4 -#define XFEATURE_MAX XFEATURE_AVX +#define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */ +#define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */ + /* bit 8 unused */ +#define XFEATURE_PKRU 0x200 #define XFEATURE_FP_ALL \ - (XFEATURE_LEGACY_FP|XFEATURE_SSE|XFEATURE_AVX) + (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \ + XFEATURE_AVX512 | XFEATURE_PKRU) #if !defined(_ASM) #if defined(_KERNEL) || defined(_KMEMUSER) -#define NUM_X86_FEATURES 49 +#define NUM_X86_FEATURES 69 extern uchar_t x86_featureset[]; extern void free_x86_featureset(void *featureset); @@ -712,6 +794,8 @@ extern uint_t cpuid_get_procnodeid(struct cpu *cpu); extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); extern uint_t cpuid_get_compunitid(struct cpu *cpu); extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu); +extern size_t cpuid_get_xsave_size(); +extern boolean_t cpuid_need_fp_excp_handling(); extern int cpuid_is_cmt(struct cpu *); extern int cpuid_syscall32_insn(struct cpu *); extern int getl2cacheinfo(struct cpu *, int *, int *, int *); |