diff options
Diffstat (limited to 'usr/src/uts/intel/sys')
| -rw-r--r-- | usr/src/uts/intel/sys/acpi/acpixf.h | 6 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/machbrand.h | 12 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/machlock.h | 3 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/segments.h | 9 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/ucontext.h | 15 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/x86_archext.h | 19 |
6 files changed, 48 insertions, 16 deletions
diff --git a/usr/src/uts/intel/sys/acpi/acpixf.h b/usr/src/uts/intel/sys/acpi/acpixf.h index e3382c655f..81e550aedb 100644 --- a/usr/src/uts/intel/sys/acpi/acpixf.h +++ b/usr/src/uts/intel/sys/acpi/acpixf.h @@ -349,7 +349,6 @@ ACPI_GLOBAL (BOOLEAN, AcpiGbl_SystemAwakeAndRunning); #endif /* ACPI_NO_ERROR_MESSAGES */ - /* * Debugging output prototypes (default: no debug output). * @@ -405,6 +404,11 @@ ACPI_GLOBAL (BOOLEAN, AcpiGbl_SystemAwakeAndRunning); #endif /* ACPI_DEBUGGER */ +/***************************************************************************** + * + * ACPICA public interface prototypes + * + ****************************************************************************/ /***************************************************************************** * diff --git a/usr/src/uts/intel/sys/machbrand.h b/usr/src/uts/intel/sys/machbrand.h index 3f9ebdb6b7..ad7f631649 100644 --- a/usr/src/uts/intel/sys/machbrand.h +++ b/usr/src/uts/intel/sys/machbrand.h @@ -20,6 +20,7 @@ */ /* * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright 2016 Joyent, Inc. */ #ifndef _SYS_MACHBRAND_H @@ -32,20 +33,25 @@ extern "C" { #ifndef _ASM #include <sys/model.h> +#include <sys/thread.h> struct brand_mach_ops { void (*b_sysenter)(void); + void (*b_int80)(void); void (*b_int91)(void); void (*b_syscall)(void); void (*b_syscall32)(void); + greg_t (*b_fixsegreg)(greg_t, model_t); + uintptr_t (*b_fsbase)(klwp_t *, uintptr_t); }; #endif /* _ASM */ #define BRAND_CB_SYSENTER 0 -#define BRAND_CB_INT91 1 -#define BRAND_CB_SYSCALL 2 -#define BRAND_CB_SYSCALL32 3 +#define BRAND_CB_INT80 1 +#define BRAND_CB_INT91 2 +#define BRAND_CB_SYSCALL 3 +#define BRAND_CB_SYSCALL32 4 #ifdef __cplusplus } diff --git a/usr/src/uts/intel/sys/machlock.h b/usr/src/uts/intel/sys/machlock.h index d21e6175dd..e362ca9aba 100644 --- a/usr/src/uts/intel/sys/machlock.h +++ b/usr/src/uts/intel/sys/machlock.h @@ -21,6 +21,7 @@ /* * Copyright 2007 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. + * Copyright 2016 Joyent, Inc. */ #ifndef _SYS_MACHLOCK_H @@ -74,7 +75,7 @@ typedef lock_t disp_lock_t; /* dispatcher lock type */ /* * Externs for CLOCK_LOCK and clock resolution */ -extern volatile int hres_lock; +extern volatile uint32_t hres_lock; extern hrtime_t hrtime_base; extern int clock_res; diff --git a/usr/src/uts/intel/sys/segments.h b/usr/src/uts/intel/sys/segments.h index c4b194fcd8..5368f80735 100644 --- a/usr/src/uts/intel/sys/segments.h +++ b/usr/src/uts/intel/sys/segments.h @@ -2,7 +2,7 @@ * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. */ /* - * Copyright 2011 Joyent, Inc. All rights reserved. + * Copyright 2016 Joyent, Inc. */ #ifndef _SYS_SEGMENTS_H @@ -522,6 +522,7 @@ void init_boot_gdt(user_desc_t *); #define GDT_B16DATA 4 /* bios call 16 bit data descriptor */ #define GDT_B64CODE 5 /* dboot 64 bit code descriptor */ #define GDT_BGSTMP 7 /* kmdb descriptor only used early in boot */ +#define GDT_CPUID 16 /* store numeric id of current CPU */ #if defined(__amd64) @@ -530,8 +531,8 @@ void init_boot_gdt(user_desc_t *); #define GDT_U32CODE 8 /* 32-bit process on 64-bit kernel %cs */ #define GDT_UDATA 9 /* user data seg %ds (32 and 64 bit) */ #define GDT_UCODE 10 /* native user code seg %cs */ -#define GDT_LDT 12 /* LDT for current process */ -#define GDT_KTSS 14 /* kernel tss */ +#define GDT_LDT 12 /* (12-13) LDT for current process */ +#define GDT_KTSS 14 /* (14-15) kernel tss */ #define GDT_FS GDT_NULL /* kernel %fs segment selector */ #define GDT_GS GDT_NULL /* kernel %gs segment selector */ #define GDT_LWPFS 55 /* lwp private %fs segment selector (32-bit) */ @@ -683,6 +684,8 @@ extern void _start(), cmnint(); extern void achktrap(), mcetrap(); extern void xmtrap(); extern void fasttrap(); +extern void sys_int80(); +extern void brand_sys_int80(); extern void dtrace_ret(); #if !defined(__amd64) diff --git a/usr/src/uts/intel/sys/ucontext.h b/usr/src/uts/intel/sys/ucontext.h index 5f64fa9393..adbb01a301 100644 --- a/usr/src/uts/intel/sys/ucontext.h +++ b/usr/src/uts/intel/sys/ucontext.h @@ -20,6 +20,7 @@ */ /* + * Copyright 2015 Joyent, Inc. * Copyright 2015 Nexenta Systems, Inc. All rights reserved. * * Copyright 2010 Sun Microsystems, Inc. All rights reserved. @@ -84,9 +85,16 @@ struct __ucontext { sigset_t uc_sigmask; stack_t uc_stack; mcontext_t uc_mcontext; - long uc_filler[5]; /* see ABI spec for Intel386 */ + /* + * The Intel386 ABI specification includes a 5-element array of longs + * called "uc_filler", padding the size of the struct to 512 bytes. To + * allow zone brands to communicate extra data right the way through + * the signal handling process, from sigacthandler to setcontext, we + * steal the first three of these longs as a brand-private member. + */ + void *uc_brand_data[3]; + long uc_filler[2]; }; - #if defined(_SYSCALL32) /* Kernel view of user ILP32 ucontext structure */ @@ -97,7 +105,8 @@ typedef struct ucontext32 { sigset_t uc_sigmask; stack32_t uc_stack; mcontext32_t uc_mcontext; - int32_t uc_filler[5]; + caddr32_t uc_brand_data[3]; + int32_t uc_filler[2]; } ucontext32_t; #if defined(_KERNEL) diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h index 8dba3414ae..5ab5974ead 100644 --- a/usr/src/uts/intel/sys/x86_archext.h +++ b/usr/src/uts/intel/sys/x86_archext.h @@ -28,7 +28,7 @@ * All rights reserved. */ /* - * Copyright 2015 Joyent, Inc. + * Copyright 2016 Joyent, Inc. * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de> * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org> * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net> @@ -91,7 +91,7 @@ extern "C" { #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ - /* 0x00000004 - reserved */ +#define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */ #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ @@ -104,15 +104,16 @@ extern "C" { #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */ #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ - /* 0x00008000 - reserved */ +#define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */ /* 0x00010000 - reserved */ - /* 0x00020000 - reserved */ +#define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */ #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */ #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ +#define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */ #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */ #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */ @@ -170,9 +171,17 @@ extern "C" { #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ -#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ +#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */ #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ + /* 0x00004000 - reserved */ +#define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */ +#define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */ + /* 0x00020000 - reserved */ + /* 0x00040000 - reserved */ +#define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */ + /* 0x00100000 - reserved */ +#define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */ #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */ /* |