diff options
Diffstat (limited to 'usr/src/uts/intel/sys')
| -rw-r--r-- | usr/src/uts/intel/sys/archsystm.h | 16 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/controlregs.h | 34 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/debugreg.h | 7 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/machbrand.h | 12 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/segments.h | 4 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/ucontext.h | 15 | ||||
| -rw-r--r-- | usr/src/uts/intel/sys/x86_archext.h | 155 |
7 files changed, 212 insertions, 31 deletions
diff --git a/usr/src/uts/intel/sys/archsystm.h b/usr/src/uts/intel/sys/archsystm.h index 93fed4e87d..0c9ceac7be 100644 --- a/usr/src/uts/intel/sys/archsystm.h +++ b/usr/src/uts/intel/sys/archsystm.h @@ -185,13 +185,17 @@ extern void fakesoftint(void); extern void *plat_traceback(void *); /* - * The following two macros are the four byte instruction sequence of stac, ret - * and clac, ret. These are used in startup_smap() as a part of properly setting - * up the valid instructions. For more information on SMAP, see - * uts/intel/ia32/ml/copy.s. + * The following two macros are the four byte instruction sequence of stac, nop + * and clac, nop. These are used in startup_smap() and hotinline_smap() as a + * part of properly setting up the valid instructions. For more information on + * SMAP, see uts/intel/ia32/ml/copy.s, uts/i86pc/os/machdep.c and + * uts/common/os/modctl.c. + * + * Note that smap_disable and smap_enable are resolved to stubs at compile time, + * but inlined at runtime by do_hotinlines() in uts/i86pc/os/machdep.c. */ -#define SMAP_CLAC_INSTR 0xc3ca010f -#define SMAP_STAC_INSTR 0xc3cb010f +#define SMAP_CLAC_INSTR 0x90ca010f +#define SMAP_STAC_INSTR 0x90cb010f extern void smap_disable(void); extern void smap_enable(void); diff --git a/usr/src/uts/intel/sys/controlregs.h b/usr/src/uts/intel/sys/controlregs.h index fe0cf687b4..0be7b3b650 100644 --- a/usr/src/uts/intel/sys/controlregs.h +++ b/usr/src/uts/intel/sys/controlregs.h @@ -86,8 +86,8 @@ extern "C" { /* CR3 Register */ -#define CR3_PCD 0x00000010 /* cache disable */ -#define CR3_PWT 0x00000008 /* write through */ +#define CR3_PCD 0x00000010 /* cache disable */ +#define CR3_PWT 0x00000008 /* write through */ #if defined(_ASM) #define CR3_NOINVL_BIT 0x8000000000000000 #else @@ -110,18 +110,22 @@ extern "C" { #define CR4_PCE 0x0100 /* perf-monitoring counter enable */ #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */ #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */ - /* 0x0800 reserved */ +#define CR4_UMIP 0x0800 /* user-mode instruction prevention */ /* 0x1000 reserved */ -#define CR4_VMXE 0x2000 -#define CR4_SMXE 0x4000 +#define CR4_VMXE 0x2000 /* VMX enable */ +#define CR4_SMXE 0x4000 /* SMX enable */ + /* 0x8000 reserved */ +#define CR4_FSGSBASE 0x10000 /* FSGSBASE enable */ #define CR4_PCIDE 0x20000 /* PCID enable */ #define CR4_OSXSAVE 0x40000 /* OS xsave/xrestore support */ #define CR4_SMEP 0x100000 /* NX for user pages in kernel */ #define CR4_SMAP 0x200000 /* kernel can't access user pages */ +#define CR4_PKE 0x400000 /* protection key enable */ #define FMT_CR4 \ - "\20\26smap\25smep\23osxsav\22pcide" \ - "\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge" \ + "\20\27pke\26smap\25smep\23osxsav" \ + "\22pcide\20fsgsbase\17smxe\16vmxe" \ + "\14umip\13xmme\12fxsr\11pce\10pge" \ "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme" /* @@ -158,7 +162,9 @@ extern "C" { #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ +#define AMD_EFER_TCE 0x8000 /* translation cache extension */ #define AMD_EFER_FFXSR 0x4000 /* fast fxsave/fxrstor */ +#define AMD_EFER_LMSLE 0x2000 /* long mode segment limit enable */ #define AMD_EFER_SVME 0x1000 /* svm enable */ #define AMD_EFER_NXE 0x0800 /* no-execute enable */ #define AMD_EFER_LMA 0x0400 /* long mode active (read-only) */ @@ -166,7 +172,7 @@ extern "C" { #define AMD_EFER_SCE 0x0001 /* system call extensions */ #define FMT_AMD_EFER \ - "\20\17ffxsr\15svme\14nxe\13lma\11lme\1sce" + "\20\20tce\17ffxsr\16lmsle\15svme\14nxe\13lma\11lme\1sce" /* AMD's SYSCFG register */ @@ -194,6 +200,18 @@ extern "C" { #define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */ #define MSR_AMD_TSCAUX 0xc0000103 /* %ecx value on rdtscp insn */ + +/* AMD's SVM MSRs */ + +#define MSR_AMD_VM_CR 0xc0010114 /* SVM global control */ +#define MSR_AMD_VM_HSAVE_PA 0xc0010117 /* SVM host save area address */ + +#define AMD_VM_CR_DPD (1 << 0) +#define AMD_VM_CR_R_INIT (1 << 1) +#define AMD_VM_CR_DIS_A20M (1 << 2) +#define AMD_VM_CR_LOCK (1 << 3) +#define AMD_VM_CR_SVMDIS (1 << 4) + /* AMD's configuration MSRs, weakly documented in the revision guide */ #define MSR_AMD_DC_CFG 0xc0011022 diff --git a/usr/src/uts/intel/sys/debugreg.h b/usr/src/uts/intel/sys/debugreg.h index b537076d26..8528a293ab 100644 --- a/usr/src/uts/intel/sys/debugreg.h +++ b/usr/src/uts/intel/sys/debugreg.h @@ -26,6 +26,9 @@ /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */ /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */ /* All Rights Reserved */ +/* + * Copyright (c) 2018, Joyent, Inc. All rights reserved. + */ #ifndef _SYS_DEBUGREG_H #define _SYS_DEBUGREG_H @@ -57,6 +60,7 @@ extern "C" { #define DR_ICEALSO 0x2000 /* Flag bit reserved for in-circuit-emulator */ #define DR_SINGLESTEP 0x4000 /* Trap resulting from the single-step flag */ #define DR_TASKSWITCH 0x8000 /* Trap resulting from a task-switch */ +#define DR_IN_RTM 0x10000 /* Trap inside an RTM region */ /* * dr7 controls the rest of the debug registers. @@ -73,6 +77,8 @@ extern "C" { #define DR_CONTROL_RESERVED 0xFC00 /* Bits reserved by Intel */ #define DR_LOCAL_SLOWDOWN 0x100 /* Slow the pipeline for ldt addrs */ #define DR_GLOBAL_SLOWDOWN 0x200 /* Slow the pipeline for gdt addrs */ +#define DR_RTM 0x800 /* Restricted Transactional Memory */ +#define DR_GENERAL_DETECT 0x2000 /* General Detect Enable */ #define DR_LOCAL_ENABLE_SHIFT 0 /* Additional shift: local enable */ #define DR_GLOBAL_ENABLE_SHIFT 1 /* Additional shift: global enable */ @@ -95,6 +101,7 @@ extern "C" { #define DR_LEN_1 0x0 /* Settings for data length */ #define DR_LEN_2 0x4 #define DR_LEN_4 0xC +#define DR_LEN_8 0x8 #ifdef __cplusplus } diff --git a/usr/src/uts/intel/sys/machbrand.h b/usr/src/uts/intel/sys/machbrand.h index 3f9ebdb6b7..ad7f631649 100644 --- a/usr/src/uts/intel/sys/machbrand.h +++ b/usr/src/uts/intel/sys/machbrand.h @@ -20,6 +20,7 @@ */ /* * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. + * Copyright 2016 Joyent, Inc. */ #ifndef _SYS_MACHBRAND_H @@ -32,20 +33,25 @@ extern "C" { #ifndef _ASM #include <sys/model.h> +#include <sys/thread.h> struct brand_mach_ops { void (*b_sysenter)(void); + void (*b_int80)(void); void (*b_int91)(void); void (*b_syscall)(void); void (*b_syscall32)(void); + greg_t (*b_fixsegreg)(greg_t, model_t); + uintptr_t (*b_fsbase)(klwp_t *, uintptr_t); }; #endif /* _ASM */ #define BRAND_CB_SYSENTER 0 -#define BRAND_CB_INT91 1 -#define BRAND_CB_SYSCALL 2 -#define BRAND_CB_SYSCALL32 3 +#define BRAND_CB_INT80 1 +#define BRAND_CB_INT91 2 +#define BRAND_CB_SYSCALL 3 +#define BRAND_CB_SYSCALL32 4 #ifdef __cplusplus } diff --git a/usr/src/uts/intel/sys/segments.h b/usr/src/uts/intel/sys/segments.h index fc2f1847cd..6bf18b3082 100644 --- a/usr/src/uts/intel/sys/segments.h +++ b/usr/src/uts/intel/sys/segments.h @@ -695,6 +695,8 @@ extern void _start(), cmnint(); extern void achktrap(), mcetrap(); extern void xmtrap(); extern void fasttrap(); +extern void sys_int80(); +extern void brand_sys_int80(); extern void dtrace_ret(); /* KPTI trampolines */ @@ -710,6 +712,8 @@ extern void tr_overrun(), tr_resvtrap(); extern void tr_achktrap(), tr_mcetrap(); extern void tr_xmtrap(); extern void tr_fasttrap(); +extern void tr_sys_int80(); +extern void tr_brand_sys_int80(); extern void tr_dtrace_ret(); #if !defined(__amd64) diff --git a/usr/src/uts/intel/sys/ucontext.h b/usr/src/uts/intel/sys/ucontext.h index 66300e71a1..2d4e39b3e8 100644 --- a/usr/src/uts/intel/sys/ucontext.h +++ b/usr/src/uts/intel/sys/ucontext.h @@ -20,6 +20,7 @@ */ /* + * Copyright 2015 Joyent, Inc. * Copyright 2015 Nexenta Systems, Inc. All rights reserved. * * Copyright 2010 Sun Microsystems, Inc. All rights reserved. @@ -84,9 +85,16 @@ struct __ucontext { sigset_t uc_sigmask; stack_t uc_stack; mcontext_t uc_mcontext; - long uc_filler[5]; /* see ABI spec for Intel386 */ + /* + * The Intel386 ABI specification includes a 5-element array of longs + * called "uc_filler", padding the size of the struct to 512 bytes. To + * allow zone brands to communicate extra data right the way through + * the signal handling process, from sigacthandler to setcontext, we + * steal the first three of these longs as a brand-private member. + */ + void *uc_brand_data[3]; + long uc_filler[2]; }; - #if defined(_SYSCALL32) /* Kernel view of user ILP32 ucontext structure */ @@ -97,7 +105,8 @@ typedef struct ucontext32 { sigset_t uc_sigmask; stack32_t uc_stack; mcontext32_t uc_mcontext; - int32_t uc_filler[5]; + caddr32_t uc_brand_data[3]; + int32_t uc_filler[2]; } ucontext32_t; #if defined(_KERNEL) diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h index 585a6576bc..0545633682 100644 --- a/usr/src/uts/intel/sys/x86_archext.h +++ b/usr/src/uts/intel/sys/x86_archext.h @@ -214,6 +214,18 @@ extern "C" { #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */ /* + * AMD SVM features (extended function 0x8000000A). + */ +#define CPUID_AMD_EDX_NESTED_PAGING 0x000000001 /* AMD: SVM NP */ +#define CPUID_AMD_EDX_LBR_VIRT 0x000000002 /* AMD: LBR virt. */ +#define CPUID_AMD_EDX_SVML 0x000000004 /* AMD: SVM lock */ +#define CPUID_AMD_EDX_NRIPS 0x000000008 /* AMD: NRIP save */ +#define CPUID_AMD_EDX_TSC_RATE_MSR 0x000000010 /* AMD: MSR TSC ctrl */ +#define CPUID_AMD_EDX_VMCB_CLEAN 0x000000020 /* AMD: VMCB clean bits */ +#define CPUID_AMD_EDX_FLUSH_ASID 0x000000040 /* AMD: flush by ASID */ +#define CPUID_AMD_EDX_DECODE_ASSISTS 0x000000080 /* AMD: decode assists */ + +/* * Intel now seems to have claimed part of the "extended" function * space that we previously for non-Intel implementors to use. * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF @@ -223,6 +235,38 @@ extern "C" { #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ /* + * Intel uses cpuid leaf 6 to cover various thermal and power control + * operations. + */ +#define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */ +#define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */ +#define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */ +/* bit 3 is reserved */ +#define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */ +#define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */ +#define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */ +#define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */ +#define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */ +#define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */ +#define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */ +#define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */ +/* bit 12 is reserved */ +#define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */ +#define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */ +#define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */ +#define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */ +#define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */ +#define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */ +/* bit 19 is reserved */ +#define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */ + +#define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf) + +#define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */ +/* bits 1-2 are reserved */ +#define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */ + +/* * Intel also uses cpuid leaf 7 to have additional instructions and features. * Like some other leaves, but unlike the current ones we care about, it * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal @@ -444,6 +488,99 @@ extern "C" { #define MSR_IA32_FLUSH_CMD 0x10b #define IA32_FLUSH_CMD_L1D 0x01 +/* + * Intel VMX related MSRs + */ +#define MSR_IA32_FEAT_CTRL 0x03a +#define IA32_FEAT_CTRL_LOCK 0x1 +#define IA32_FEAT_CTRL_SMX_EN 0x2 +#define IA32_FEAT_CTRL_VMX_EN 0x4 + +#define MSR_IA32_VMX_BASIC 0x480 +#define IA32_VMX_BASIC_INS_OUTS (1UL << 54) +#define IA32_VMX_BASIC_TRUE_CTRLS (1UL << 55) + +#define MSR_IA32_VMX_PROCBASED_CTLS 0x482 +#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e +#define IA32_VMX_PROCBASED_2ND_CTLS (1UL << 31) + +#define MSR_IA32_VMX_PROCBASED2_CTLS 0x48b +#define IA32_VMX_PROCBASED2_EPT (1UL << 1) +#define IA32_VMX_PROCBASED2_VPID (1UL << 5) + +#define MSR_IA32_VMX_EPT_VPID_CAP 0x48c +#define IA32_VMX_EPT_VPID_INVEPT (1UL << 20) +#define IA32_VMX_EPT_VPID_INVEPT_SINGLE (1UL << 25) +#define IA32_VMX_EPT_VPID_INVEPT_ALL (1UL << 26) + +/* + * Intel Thermal MSRs + */ +#define MSR_IA32_THERM_INTERRUPT 0x19b +#define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001 +#define IA32_THERM_INTERRUPT_LOW_IE 0x00000002 +#define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004 +#define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008 +#define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010 +#define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) +#define IA32_THERM_INTTERUPT_TR1_IE 0x00008000 +#define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) +#define IA32_THERM_INTERRUPT_TR2_IE 0x00800000 +#define IA32_THERM_INTERRUPT_PL_NE 0x01000000 + +#define MSR_IA32_THERM_STATUS 0x19c +#define IA32_THERM_STATUS_STATUS 0x00000001 +#define IA32_THERM_STATUS_STATUS_LOG 0x00000002 +#define IA32_THERM_STATUS_PROCHOT 0x00000004 +#define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008 +#define IA32_THERM_STATUS_CRIT_STATUS 0x00000010 +#define IA32_THERM_STATUS_CRIT_LOG 0x00000020 +#define IA32_THERM_STATUS_TR1_STATUS 0x00000040 +#define IA32_THERM_STATUS_TR1_LOG 0x00000080 +#define IA32_THERM_STATUS_TR2_STATUS 0x00000100 +#define IA32_THERM_STATUS_TR2_LOG 0x00000200 +#define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400 +#define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800 +#define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000 +#define IA32_THERM_STATUS_CURRENT_LOG 0x00002000 +#define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000 +#define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000 +#define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) +#define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f) +#define IA32_THERM_STATUS_READ_VALID 0x80000000 + +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff) +/* + * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list + * of which models have support for which bits. + */ +#define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f) + +#define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1 +#define IA32_PKG_THERM_STATUS_STATUS 0x00000001 +#define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002 +#define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004 +#define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008 +#define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010 +#define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020 +#define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040 +#define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080 +#define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100 +#define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200 +#define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f) + +#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2 +#define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001 +#define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002 +#define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004 +#define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010 +#define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f) +#define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000 +#define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f) +#define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000 +#define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000 + #define MCI_CTL_VALUE 0xffffffff #define MTRR_TYPE_UC 0 @@ -568,6 +705,8 @@ extern "C" { #define X86FSET_TBM 90 #define X86FSET_AVX512VNNI 91 #define X86FSET_AMD_PCEC 92 +#define X86FSET_CORE_THERMAL 93 +#define X86FSET_PKG_THERMAL 94 /* * Intel Deep C-State invariant TSC in leaf 0x80000007. @@ -575,16 +714,6 @@ extern "C" { #define CPUID_TSC_CSTATE_INVARIANCE (0x100) /* - * Intel Deep C-state always-running local APIC timer - */ -#define CPUID_CSTATE_ARAT (0x4) - -/* - * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. - */ -#define CPUID_EPB_SUPPORT (1 << 3) - -/* * Intel TSC deadline timer */ #define CPUID_DEADLINE_TSC (1 << 24) @@ -851,7 +980,9 @@ extern "C" { * Definitions for Intel processor models. These are all for Family 6 * processors. This list and the Atom set below it are not exhuastive. */ +#define INTC_MODEL_YONAH 0x0e #define INTC_MODEL_MEROM 0x0f +#define INTC_MODEL_MEROM_L 0x16 #define INTC_MODEL_PENRYN 0x17 #define INTC_MODEL_DUNNINGTON 0x1d @@ -937,7 +1068,7 @@ extern "C" { #if defined(_KERNEL) || defined(_KMEMUSER) -#define NUM_X86_FEATURES 93 +#define NUM_X86_FEATURES 95 extern uchar_t x86_featureset[]; extern void free_x86_featureset(void *featureset); @@ -956,6 +1087,8 @@ extern uint_t pentiumpro_bug4046376; extern const char CyrixInstead[]; +extern void (*spec_l1d_flush)(void); + #endif #if defined(_KERNEL) |