summaryrefslogtreecommitdiff
path: root/usr/src/uts
diff options
context:
space:
mode:
Diffstat (limited to 'usr/src/uts')
-rw-r--r--usr/src/uts/common/io/ib/clients/rds/rdsib.c4
-rw-r--r--usr/src/uts/common/io/ib/clients/rdsv3/rdsv3_impl.c1
-rw-r--r--usr/src/uts/common/io/idm/idm.c2
-rw-r--r--usr/src/uts/common/io/nge/nge_chip.h38
-rw-r--r--usr/src/uts/common/sys/ib/clients/rds/rdsib_buf.h6
-rw-r--r--usr/src/uts/common/sys/ib/clients/rdsv3/rdsv3_impl.h2
-rw-r--r--usr/src/uts/common/sys/idm/idm_impl.h2
-rw-r--r--usr/src/uts/common/sys/mhd.h12
-rw-r--r--usr/src/uts/common/sys/rgb.h35
-rw-r--r--usr/src/uts/i86pc/io/vmm/amd/svm_msr.c20
-rw-r--r--usr/src/uts/i86pc/os/cpuid.c101
-rw-r--r--usr/src/uts/i86pc/os/fakebop.c4
-rw-r--r--usr/src/uts/i86pc/os/mlsetup.c23
-rw-r--r--usr/src/uts/i86pc/sys/tsc.h2
-rw-r--r--usr/src/uts/intel/sys/x86_archext.h3
15 files changed, 146 insertions, 109 deletions
diff --git a/usr/src/uts/common/io/ib/clients/rds/rdsib.c b/usr/src/uts/common/io/ib/clients/rds/rdsib.c
index ebfa352ac0..b80b385d75 100644
--- a/usr/src/uts/common/io/ib/clients/rds/rdsib.c
+++ b/usr/src/uts/common/io/ib/clients/rds/rdsib.c
@@ -71,6 +71,10 @@ rds_transport_ops_t rds_ib_transport_ops = {
rds_if_lookup_by_name
};
+/* Global pools of buffers */
+rds_bufpool_t rds_dpool; /* data pool */
+rds_bufpool_t rds_cpool; /* ctrl pool */
+
/* global */
rds_state_t *rdsib_statep = NULL;
krwlock_t rds_loopback_portmap_lock;
diff --git a/usr/src/uts/common/io/ib/clients/rdsv3/rdsv3_impl.c b/usr/src/uts/common/io/ib/clients/rdsv3/rdsv3_impl.c
index 5cc3160b3a..028ceb9937 100644
--- a/usr/src/uts/common/io/ib/clients/rdsv3/rdsv3_impl.c
+++ b/usr/src/uts/common/io/ib/clients/rdsv3/rdsv3_impl.c
@@ -66,6 +66,7 @@
#include <sys/mac_provider.h>
#include <sys/mac_client_priv.h>
+uint_t rdsv3_one_sec_in_hz;
ddi_taskq_t *rdsv3_taskq = NULL;
extern kmem_cache_t *rdsv3_alloc_cache;
diff --git a/usr/src/uts/common/io/idm/idm.c b/usr/src/uts/common/io/idm/idm.c
index 1361b8dfb9..ade553dabd 100644
--- a/usr/src/uts/common/io/idm/idm.c
+++ b/usr/src/uts/common/io/idm/idm.c
@@ -107,6 +107,8 @@ idm_transport_t idm_transport_list[] = {
};
+idm_global_t idm; /* Global state */
+
int
_init(void)
{
diff --git a/usr/src/uts/common/io/nge/nge_chip.h b/usr/src/uts/common/io/nge/nge_chip.h
index 089f77320a..1d1e85be08 100644
--- a/usr/src/uts/common/io/nge/nge_chip.h
+++ b/usr/src/uts/common/io/nge/nge_chip.h
@@ -522,7 +522,7 @@ typedef union _nge_rx_cntrl0 {
uint32_t crcm:1;
uint32_t ofolm:1;
uint32_t framerm:1;
- uint32_t resv23_31:9;
+ uint32_t resv23_31:9;
} cntl_bits;
} nge_rx_cntrl0;
@@ -627,7 +627,7 @@ typedef union _nge_rx_def {
* Low 32 bit unicast address
*/
#define NGE_UNI_ADDR0 0x0a8
-union {
+typedef union _nge_uni_addr0 {
uint32_t addr_val;
struct {
uint32_t addr;
@@ -655,12 +655,12 @@ typedef union _nge_uni_addr1 {
* Low 32 bit multicast address
*/
#define NGE_MUL_ADDR0 0x0b0
-union {
+typedef union _nge_mul_addr0 {
uint32_t addr_val;
struct {
uint32_t addr;
}addr_bits;
-}nge_mul_addr0;
+} nge_mul_addr0;
/*
* High 32 bit multicast address
@@ -672,13 +672,13 @@ typedef union _nge_mul_addr1 {
uint32_t addr:16;
uint32_t resv16_31:16;
}addr_bits;
-}nge_mul_addr1;
+} nge_mul_addr1;
/*
* Low 32 bit multicast mask
*/
#define NGE_MUL_MASK 0x0b8
-union {
+typedef union _nge_mul_mask0 {
uint32_t mask_val;
struct {
uint32_t mask;
@@ -689,7 +689,7 @@ union {
* High 32 bit multicast mask
*/
#define NGE_MUL_MASK1 0x0bc
-union {
+typedef union _nge_mul_mask1 {
uint32_t mask_val;
struct {
uint32_t mask:16;
@@ -800,7 +800,7 @@ typedef union _nge_rx_poll {
* Transmit polling count
*/
#define NGE_TX_PCNT 0x114
-union {
+typedef union _nge_tx_pcnt {
uint32_t cnt_val;
struct {
uint32_t pcnt:32;
@@ -811,7 +811,7 @@ union {
* Receive polling count
*/
#define NGE_RX_PCNT 0x118
-union {
+typedef union _nge_rx_pcnt {
uint32_t cnt_val;
struct {
uint32_t pcnt:32;
@@ -823,7 +823,7 @@ union {
* Current tx's descriptor address
*/
#define NGE_TX_CUR_DADR 0x11c
-union {
+typedef union _nge_tx_cur_addr {
uint32_t addr_val;
struct {
uint32_t resv0_2:3;
@@ -835,7 +835,7 @@ union {
* Current rx's descriptor address
*/
#define NGE_RX_CUR_DADR 0x120
-union {
+typedef union _nge_rx_cur_addr {
uint32_t addr_val;
struct {
uint32_t resv0_2:3;
@@ -847,7 +847,7 @@ union {
* Current tx's data buffer address
*/
#define NGE_TX_CUR_PRD0 0x124
-union {
+typedef union _nge_tx_cur_prd0 {
uint32_t prd0_val;
struct {
uint32_t prd0:32;
@@ -858,7 +858,7 @@ union {
* Current tx's data buffer status
*/
#define NGE_TX_CUR_PRD1 0x128
-union {
+typedef union _nge_tx_cur_prd1 {
uint32_t prd1_val;
struct {
uint32_t rebytes:16;
@@ -870,12 +870,12 @@ union {
* Current rx's data buffer address
*/
#define NGE_RX_CUR_PRD0 0x12c
-union {
+typedef union _nge_rx_cur_prd0 {
uint32_t prd0_val;
struct {
uint32_t prd0:32;
}prd0_bits;
-}nge_rx_cur_prd0;
+} nge_rx_cur_prd0;
/*
* Current rx's data buffer status
@@ -886,18 +886,18 @@ union {
* Next tx's descriptor address
*/
#define NGE_TX_NXT_DADR 0x134
-union {
+typedef union _nge_tx_nxt_dadr {
uint32_t dadr_val;
struct {
uint32_t addr:32;
}addr_bits;
-}nge_tx_nxt_dadr;
+} nge_tx_nxt_dadr;
/*
* Next rx's descriptor address
*/
#define NGE_RX_NXT_DADR 0x138
-union {
+typedef union _nge_rx_nxt_dadr {
uint32_t dadr_val;
struct {
uint32_t addr:32;
@@ -1362,7 +1362,7 @@ typedef union {
#define MII_CICADA_DISABLE_ECHO_MODE 0x2000
#define MII_CICADA_EXT_CONTROL MII_VENDOR(7)
-#define MII_CICADA_MODE_SELECT_BITS 0xf000
+#define MII_CICADA_MODE_SELECT_BITS 0xf000
#define MII_CICADA_MODE_SELECT_RGMII 0x1000
#define MII_CICADA_POWER_SUPPLY_BITS 0x0e00
#define MII_CICADA_POWER_SUPPLY_3_3V 0x0000
diff --git a/usr/src/uts/common/sys/ib/clients/rds/rdsib_buf.h b/usr/src/uts/common/sys/ib/clients/rds/rdsib_buf.h
index 5e2f419600..164af2aa7a 100644
--- a/usr/src/uts/common/sys/ib/clients/rds/rdsib_buf.h
+++ b/usr/src/uts/common/sys/ib/clients/rds/rdsib_buf.h
@@ -75,8 +75,6 @@
#ifndef _RDSIB_BUF_H
#define _RDSIB_BUF_H
-#pragma ident "%Z%%M% %I% %E% SMI"
-
#ifdef __cplusplus
extern "C" {
#endif
@@ -149,8 +147,8 @@ typedef struct rds_bufpool_s {
} rds_bufpool_t;
/* Global pools of buffers */
-rds_bufpool_t rds_dpool; /* data pool */
-rds_bufpool_t rds_cpool; /* ctrl pool */
+extern rds_bufpool_t rds_dpool; /* data pool */
+extern rds_bufpool_t rds_cpool; /* ctrl pool */
/* defined in rds_buf.c */
int rds_init_recv_caches(rds_state_t *statep);
diff --git a/usr/src/uts/common/sys/ib/clients/rdsv3/rdsv3_impl.h b/usr/src/uts/common/sys/ib/clients/rdsv3/rdsv3_impl.h
index 56b92f8037..c462306418 100644
--- a/usr/src/uts/common/sys/ib/clients/rdsv3/rdsv3_impl.h
+++ b/usr/src/uts/common/sys/ib/clients/rdsv3/rdsv3_impl.h
@@ -117,7 +117,7 @@ typedef unsigned int atomic_t;
#define clear_le_bit(b, p) clear_bit(b ^ LE_BIT_XOR, p)
#define test_le_bit(b, p) test_bit(b ^ LE_BIT_XOR, p)
-uint_t rdsv3_one_sec_in_hz;
+extern uint_t rdsv3_one_sec_in_hz;
#define jiffies 100
#define HZ (drv_hztousec(1))
diff --git a/usr/src/uts/common/sys/idm/idm_impl.h b/usr/src/uts/common/sys/idm/idm_impl.h
index 346611719d..1e816ee211 100644
--- a/usr/src/uts/common/sys/idm/idm_impl.h
+++ b/usr/src/uts/common/sys/idm/idm_impl.h
@@ -472,7 +472,7 @@ typedef struct {
kmem_cache_t *idm_so_128k_buf_cache;
} idm_global_t;
-idm_global_t idm; /* Global state */
+extern idm_global_t idm; /* Global state */
int
idm_idpool_create(idm_idpool_t *pool);
diff --git a/usr/src/uts/common/sys/mhd.h b/usr/src/uts/common/sys/mhd.h
index 66d57266ad..3d7e0d5d5a 100644
--- a/usr/src/uts/common/sys/mhd.h
+++ b/usr/src/uts/common/sys/mhd.h
@@ -27,8 +27,6 @@
#ifndef _SYS_MHD_H
#define _SYS_MHD_H
-#pragma ident "%Z%%M% %I% %E% SMI"
-
#ifdef __cplusplus
extern "C" {
#endif
@@ -41,8 +39,8 @@ extern "C" {
#define MHIOCTKOWN (MHIOC|2)
#define MHIOCRELEASE (MHIOC|3)
#define MHIOCSTATUS (MHIOC|4)
-#define MHIOCGRP_INKEYS (MHIOC|5)
-#define MHIOCGRP_INRESV (MHIOC|6)
+#define MHIOCGRP_INKEYS (MHIOC|5)
+#define MHIOCGRP_INRESV (MHIOC|6)
#define MHIOCGRP_REGISTER (MHIOC|7)
#define MHIOCGRP_RESERVE (MHIOC|8)
#define MHIOCGRP_PREEMPTANDABORT (MHIOC|9)
@@ -79,13 +77,13 @@ typedef struct mhioc_inkeys {
} mhioc_inkeys_t;
#if defined(_SYSCALL32)
-struct mhioc_key_list32 {
+typedef struct mhioc_key_list32 {
uint32_t listsize;
uint32_t listlen;
caddr32_t list;
} mhioc_key_list32_t;
-struct mhioc_inkeys32 {
+typedef struct mhioc_inkeys32 {
uint32_t generation;
caddr32_t li;
} mhioc_inkeys32_t;
@@ -110,7 +108,7 @@ typedef struct mhioc_inresvs {
} mhioc_inresvs_t;
#if defined(_SYSCALL32)
-struct mhioc_resv_desc_list32 {
+typedef struct mhioc_resv_desc_list32 {
uint32_t listsize;
uint32_t listlen;
caddr32_t list;
diff --git a/usr/src/uts/common/sys/rgb.h b/usr/src/uts/common/sys/rgb.h
index 9ddfaa9e3f..6e0ba29af2 100644
--- a/usr/src/uts/common/sys/rgb.h
+++ b/usr/src/uts/common/sys/rgb.h
@@ -23,6 +23,13 @@ extern "C" {
#endif
/*
+ * Number of "base" colors is 16, 8 dark and 8 bright/light.
+ * Color map size for indexed colors is 256, to support VGA 256-color modes.
+ */
+#define NCOLORS 16
+#define NCMAP 256
+
+/*
* Color data from bootloader.
*/
typedef struct rgb_color {
@@ -37,9 +44,9 @@ typedef struct rgb {
} rgb_t;
typedef struct {
- uint8_t red[16];
- uint8_t green[16];
- uint8_t blue[16];
+ uint8_t red[NCOLORS];
+ uint8_t green[NCOLORS];
+ uint8_t blue[NCOLORS];
} text_cmap_t;
extern const text_cmap_t cmap4_to_24;
@@ -67,10 +74,30 @@ typedef enum pc_colors {
pc_brt_white = 15
} pc_colors_t;
+typedef enum sun_colors {
+ sun_brt_white = 0,
+ sun_black = 1,
+ sun_blue = 2,
+ sun_green = 3,
+ sun_cyan = 4,
+ sun_red = 5,
+ sun_magenta = 6,
+ sun_brown = 7,
+ sun_white = 8,
+ sun_grey = 9,
+ sun_brt_blue = 10,
+ sun_brt_green = 11,
+ sun_brt_cyan = 12,
+ sun_brt_red = 13,
+ sun_brt_magenta = 14,
+ sun_yellow = 15,
+} sun_colors_t;
+
#define XLATE_NCOLORS 8
extern const uint8_t dim_xlate[XLATE_NCOLORS];
extern const uint8_t brt_xlate[XLATE_NCOLORS];
-extern const uint8_t solaris_color_to_pc_color[16];
+extern const uint8_t solaris_color_to_pc_color[NCOLORS];
+extern const uint8_t pc_color_to_solaris_color[NCOLORS];
extern uint32_t rgb_color_map(const rgb_t *, uint8_t);
diff --git a/usr/src/uts/i86pc/io/vmm/amd/svm_msr.c b/usr/src/uts/i86pc/io/vmm/amd/svm_msr.c
index 234631def4..f453692855 100644
--- a/usr/src/uts/i86pc/io/vmm/amd/svm_msr.c
+++ b/usr/src/uts/i86pc/io/vmm/amd/svm_msr.c
@@ -44,6 +44,8 @@ __FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/errno.h>
#include <sys/systm.h>
+#include <sys/x86_archext.h>
+#include <sys/privregs.h>
#include <machine/cpufunc.h>
#include <machine/specialreg.h>
@@ -162,13 +164,17 @@ svm_rdmsr(struct svm_softc *sc, int vcpu, uint_t num, uint64_t *result)
case MSR_EXTFEATURES:
*result = 0;
break;
- case MSR_DE_CFG:
+ case MSR_AMD_DE_CFG:
+ *result = 0;
/*
- * MSR_DE_CFG is used for a vast array of AMD errata, spanning
- * from family 10h to 17h. In the future, it might make sense
- * to more thoroughly emulate its contents.
+ * Bit 1 of DE_CFG is defined by AMD to control whether the
+ * lfence instruction is serializing. Practically all CPUs
+ * supported by bhyve also contain this MSR, making it safe to
+ * expose unconditionally.
*/
- *result = 0;
+ if (is_x86_feature(x86_featureset, X86FSET_LFENCE_SER)) {
+ *result |= AMD_DE_CFG_LFENCE_DISPATCH;
+ }
break;
default:
error = EINVAL;
@@ -197,8 +203,8 @@ svm_wrmsr(struct svm_softc *sc, int vcpu, uint_t num, uint64_t val)
case MSR_SYSCFG:
/* Ignore writes */
break;
- case MSR_DE_CFG:
- /* Ignore writes for now. (See: svm_rdmsr) */
+ case MSR_AMD_DE_CFG:
+ /* Ignore writes */
break;
case MSR_AMDK8_IPM:
/*
diff --git a/usr/src/uts/i86pc/os/cpuid.c b/usr/src/uts/i86pc/os/cpuid.c
index c40173d4c8..ff01bd1308 100644
--- a/usr/src/uts/i86pc/os/cpuid.c
+++ b/usr/src/uts/i86pc/os/cpuid.c
@@ -24,6 +24,7 @@
* Copyright 2013 Nexenta Systems, Inc. All rights reserved.
* Copyright 2014 Josef "Jeff" Sipek <jeffpc@josefsipek.net>
* Copyright 2020 Joyent, Inc.
+ * Copyright 2020 Oxide Computer Company
*/
/*
* Copyright (c) 2010, Intel Corporation.
@@ -1439,7 +1440,8 @@ static char *x86_feature_names[NUM_X86_FEATURES] = {
"taa_no",
"ppin",
"vaes",
- "vpclmulqdq"
+ "vpclmulqdq",
+ "lfence_serializing"
};
boolean_t
@@ -2732,7 +2734,6 @@ cpuid_enable_enhanced_ibrs(void)
wrmsr(MSR_IA32_SPEC_CTRL, val);
}
-#ifndef __xpv
/*
* Determine whether or not we can use the AMD optimized retpoline
* functionality. We use this when we know we're on an AMD system and we can
@@ -2741,46 +2742,12 @@ cpuid_enable_enhanced_ibrs(void)
static boolean_t
cpuid_use_amd_retpoline(struct cpuid_info *cpi)
{
- uint64_t val;
- on_trap_data_t otd;
-
if (cpi->cpi_vendor != X86_VENDOR_AMD &&
cpi->cpi_vendor != X86_VENDOR_HYGON)
return (B_FALSE);
- /*
- * We need to determine whether or not lfence is serializing. It always
- * is on families 0xf and 0x11. On others, it's controlled by
- * MSR_AMD_DE_CFG (MSRC001_1029). If some hypervisor gives us a crazy
- * old family, don't try and do anything.
- */
- if (cpi->cpi_family < 0xf)
- return (B_FALSE);
- if (cpi->cpi_family == 0xf || cpi->cpi_family == 0x11)
- return (B_TRUE);
-
- /*
- * While it may be tempting to use get_hwenv(), there are no promises
- * that a hypervisor will actually declare themselves to be so in a
- * friendly way. As such, try to read and set the MSR. If we can then
- * read back the value we set (it wasn't just set to zero), then we go
- * for it.
- */
- if (!on_trap(&otd, OT_DATA_ACCESS)) {
- val = rdmsr(MSR_AMD_DE_CFG);
- val |= AMD_DE_CFG_LFENCE_DISPATCH;
- wrmsr(MSR_AMD_DE_CFG, val);
- val = rdmsr(MSR_AMD_DE_CFG);
- } else {
- val = 0;
- }
- no_trap();
-
- if ((val & AMD_DE_CFG_LFENCE_DISPATCH) != 0)
- return (B_TRUE);
- return (B_FALSE);
+ return (is_x86_feature(x86_featureset, X86FSET_LFENCE_SER));
}
-#endif /* !__xpv */
/*
* Determine how we should mitigate TAA or if we need to. Regardless of TAA, if
@@ -3019,10 +2986,8 @@ cpuid_scan_security(cpu_t *cpu, uchar_t *featureset)
} else if (is_x86_feature(featureset, X86FSET_IBRS_ALL)) {
cpuid_enable_enhanced_ibrs();
v2mit = X86_SPECTREV2_ENHANCED_IBRS;
-#ifndef __xpv
} else if (cpuid_use_amd_retpoline(cpi)) {
v2mit = X86_SPECTREV2_RETPOLINE_AMD;
-#endif /* !__xpv */
} else {
v2mit = X86_SPECTREV2_RETPOLINE;
}
@@ -4186,6 +4151,59 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
}
/*
+ * Check (and potentially set) if lfence is serializing.
+ * This is useful for accurate rdtsc measurements and AMD retpolines.
+ */
+ if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) &&
+ is_x86_feature(featureset, X86FSET_SSE2)) {
+ /*
+ * The AMD white paper Software Techniques For Managing
+ * Speculation on AMD Processors details circumstances for when
+ * lfence instructions are serializing.
+ *
+ * On family 0xf and 0x11, it is inherently so. On family 0x10
+ * and later (excluding 0x11), a bit in the DE_CFG MSR
+ * determines the lfence behavior. Per that whitepaper, AMD has
+ * committed to supporting that MSR on all later CPUs.
+ */
+ if (cpi->cpi_family == 0xf || cpi->cpi_family == 0x11) {
+ add_x86_feature(featureset, X86FSET_LFENCE_SER);
+ } else if (cpi->cpi_family >= 0x10) {
+ uint64_t val = 0;
+
+#if !defined(__xpv)
+ /*
+ * Be careful when attempting to enable the bit, and
+ * verify that it was actually set in case we are
+ * running in a hypervisor which is less than faithful
+ * about its emulation of this feature.
+ */
+ on_trap_data_t otd;
+ if (!on_trap(&otd, OT_DATA_ACCESS)) {
+ val = rdmsr(MSR_AMD_DE_CFG);
+ val |= AMD_DE_CFG_LFENCE_DISPATCH;
+ wrmsr(MSR_AMD_DE_CFG, val);
+ val = rdmsr(MSR_AMD_DE_CFG);
+ }
+ no_trap();
+#endif
+
+ if ((val & AMD_DE_CFG_LFENCE_DISPATCH) != 0) {
+ add_x86_feature(featureset, X86FSET_LFENCE_SER);
+ }
+ }
+ } else if (cpi->cpi_vendor == X86_VENDOR_Intel &&
+ is_x86_feature(featureset, X86FSET_SSE2)) {
+ /*
+ * Documentation and other OSes indicate that lfence is always
+ * serializing on Intel CPUs.
+ */
+ add_x86_feature(featureset, X86FSET_LFENCE_SER);
+ }
+
+
+ /*
* Check the processor leaves that are used for security features.
*/
cpuid_scan_security(cpu, featureset);
@@ -7263,11 +7281,6 @@ patch_tsc_read(int flag)
cnt = &_no_rdtsc_end - &_no_rdtsc_start;
(void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt);
break;
- case TSC_RDTSC_MFENCE:
- cnt = &_tsc_mfence_end - &_tsc_mfence_start;
- (void) memcpy((void *)tsc_read,
- (void *)&_tsc_mfence_start, cnt);
- break;
case TSC_RDTSC_LFENCE:
cnt = &_tsc_lfence_end - &_tsc_lfence_start;
(void) memcpy((void *)tsc_read,
diff --git a/usr/src/uts/i86pc/os/fakebop.c b/usr/src/uts/i86pc/os/fakebop.c
index 75c4c618a7..933411606e 100644
--- a/usr/src/uts/i86pc/os/fakebop.c
+++ b/usr/src/uts/i86pc/os/fakebop.c
@@ -130,8 +130,8 @@ static char *curr_page = NULL; /* ptr to avail bprop memory */
static int curr_space = 0; /* amount of memory at curr_page */
#ifdef __xpv
-start_info_t *xen_info;
-shared_info_t *HYPERVISOR_shared_info;
+extern start_info_t *xen_info;
+extern shared_info_t *HYPERVISOR_shared_info;
#endif
/*
diff --git a/usr/src/uts/i86pc/os/mlsetup.c b/usr/src/uts/i86pc/os/mlsetup.c
index 9487552564..e1fd081cfa 100644
--- a/usr/src/uts/i86pc/os/mlsetup.c
+++ b/usr/src/uts/i86pc/os/mlsetup.c
@@ -24,6 +24,7 @@
* Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2011 by Delphix. All rights reserved.
* Copyright 2019 Joyent, Inc.
+ * Copyright 2020 Oxide Computer Company
*/
/*
* Copyright (c) 2010, Intel Corporation.
@@ -265,30 +266,16 @@ mlsetup(struct regs *rp)
* time-stamp counter while ensuring no out-of-order execution.
* Patch it while the kernel text is still writable.
*
- * Note: tsc_read is not patched for intel processors whose family
- * is >6 and for amd whose family >f (in case they don't support rdtscp
- * instruction, unlikely). By default tsc_read will use cpuid for
- * serialization in such cases. The following code needs to be
- * revisited if intel processors of family >= f retains the
- * instruction serialization nature of mfence instruction.
- * Note: tsc_read is not patched for x86 processors which do
- * not support "mfence". By default tsc_read will use cpuid for
- * serialization in such cases.
- *
* The Xen hypervisor does not correctly report whether rdtscp is
* supported or not, so we must assume that it is not.
*/
if ((get_hwenv() & HW_XEN_HVM) == 0 &&
- is_x86_feature(x86_featureset, X86FSET_TSCP))
+ is_x86_feature(x86_featureset, X86FSET_TSCP)) {
patch_tsc_read(TSC_TSCP);
- else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
- cpuid_getfamily(CPU) <= 0xf &&
- is_x86_feature(x86_featureset, X86FSET_SSE2))
- patch_tsc_read(TSC_RDTSC_MFENCE);
- else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
- cpuid_getfamily(CPU) <= 6 &&
- is_x86_feature(x86_featureset, X86FSET_SSE2))
+ } else if (is_x86_feature(x86_featureset, X86FSET_LFENCE_SER)) {
+ ASSERT(is_x86_feature(x86_featureset, X86FSET_SSE2));
patch_tsc_read(TSC_RDTSC_LFENCE);
+ }
#endif /* !__xpv */
diff --git a/usr/src/uts/i86pc/sys/tsc.h b/usr/src/uts/i86pc/sys/tsc.h
index d4090381c4..82a1557bd0 100644
--- a/usr/src/uts/i86pc/sys/tsc.h
+++ b/usr/src/uts/i86pc/sys/tsc.h
@@ -21,7 +21,7 @@
*/
#define TSC_NONE 0x0
#define TSC_RDTSC_CPUID 0x1
-#define TSC_RDTSC_MFENCE 0x2
+/* formerly TSC_RDTSC_MFENCE 0x2 */
#define TSC_RDTSC_LFENCE 0x3
#define TSC_TSCP 0x4
diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h
index 689ed9cc76..241ce2820b 100644
--- a/usr/src/uts/intel/sys/x86_archext.h
+++ b/usr/src/uts/intel/sys/x86_archext.h
@@ -738,6 +738,7 @@ extern "C" {
#define X86FSET_PPIN 99
#define X86FSET_VAES 100
#define X86FSET_VPCLMULQDQ 101
+#define X86FSET_LFENCE_SER 102
/*
* Intel Deep C-State invariant TSC in leaf 0x80000007.
@@ -1138,7 +1139,7 @@ extern "C" {
#if defined(_KERNEL) || defined(_KMEMUSER)
-#define NUM_X86_FEATURES 102
+#define NUM_X86_FEATURES 103
extern uchar_t x86_featureset[];
extern void free_x86_featureset(void *featureset);
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-10 08:49:01 +0000