diff options
Diffstat (limited to 'usr/src')
| -rw-r--r-- | usr/src/uts/sun4/ml/interrupt.s | 60 | ||||
| -rw-r--r-- | usr/src/uts/sun4/ml/offsets.in | 5 | ||||
| -rw-r--r-- | usr/src/uts/sun4u/sys/machcpuvar.h | 6 | ||||
| -rw-r--r-- | usr/src/uts/sun4v/sys/machcpuvar.h | 4 |
4 files changed, 69 insertions, 6 deletions
diff --git a/usr/src/uts/sun4/ml/interrupt.s b/usr/src/uts/sun4/ml/interrupt.s index b3055e0317..f3cd4f7250 100644 --- a/usr/src/uts/sun4/ml/interrupt.s +++ b/usr/src/uts/sun4/ml/interrupt.s @@ -940,10 +940,35 @@ current_thread(struct regs *regs, uint64_t iv_p, uint_t pil) mov %o7, %l0 ldn [THREAD_REG + T_CPU], %o3 + + ldn [THREAD_REG + T_ONFAULT], %l2 + brz,pt %l2, no_onfault ! branch if no onfault label set + nop + stn %g0, [THREAD_REG + T_ONFAULT]! clear onfault label + ldn [THREAD_REG + T_LOFAULT], %l3 + stn %g0, [THREAD_REG + T_LOFAULT]! clear lofault data + + sub %o2, LOCK_LEVEL + 1, %o5 + sll %o5, CPTRSHIFT, %o5 + add %o5, CPU_OFD, %o4 ! %o4 has on_fault data offset + stn %l2, [%o3 + %o4] ! save onfault label for pil %o2 + add %o5, CPU_LFD, %o4 ! %o4 has lofault data offset + stn %l3, [%o3 + %o4] ! save lofault data for pil %o2 + +no_onfault: + ldn [THREAD_REG + T_ONTRAP], %l2 + brz,pt %l2, 6f ! branch if no on_trap protection + nop + stn %g0, [THREAD_REG + T_ONTRAP]! clear on_trap protection + sub %o2, LOCK_LEVEL + 1, %o5 + sll %o5, CPTRSHIFT, %o5 + add %o5, CPU_OTD, %o4 ! %o4 has on_trap data offset + stn %l2, [%o3 + %o4] ! save on_trap label for pil %o2 + ! ! Set bit for this level in CPU's active interrupt bitmask. ! - ld [%o3 + CPU_INTR_ACTV], %o5 ! o5 has cpu_intr_actv b4 chng +6: ld [%o3 + CPU_INTR_ACTV], %o5 ! o5 has cpu_intr_actv b4 chng mov 1, %o4 sll %o4, %o2, %o4 ! construct mask for level #ifdef DEBUG @@ -1333,7 +1358,7 @@ current_thread_complete: ! Another high-level interrupt is active below this one, so ! there is no need to check for an interrupt thread. That will be ! done by the lowest priority high-level interrupt active. - ba,pt %xcc, 1f + ba,pt %xcc, 7f stx %o4, [%o3 + %o5] ! delay - store timestamp 3: ! If we haven't interrupted another high-level interrupt, we may have @@ -1341,14 +1366,41 @@ current_thread_complete: ! timestamp in its thread structure. lduh [THREAD_REG + T_FLAGS], %o4 andcc %o4, T_INTR_THREAD, %g0 - bz,pt %xcc, 1f + bz,pt %xcc, 7f nop rdpr %tick, %o4 sllx %o4, 1, %o4 srlx %o4, 1, %o4 ! Shake off NPT bit stx %o4, [THREAD_REG + T_INTR_START] -1: + +7: + sub %o2, LOCK_LEVEL + 1, %o4 + sll %o4, CPTRSHIFT, %o5 + + ! Check on_trap saved area and restore as needed + add %o5, CPU_OTD, %o4 + ldn [%o3 + %o4], %l2 + brz,pt %l2, no_ontrp_restore + nop + stn %l2, [THREAD_REG + T_ONTRAP] ! restore + stn %g0, [%o3 + %o4] ! clear + +no_ontrp_restore: + ! Check on_fault saved area and restore as needed + add %o5, CPU_OFD, %o4 + ldn [%o3 + %o4], %l2 + brz,pt %l2, 8f + nop + stn %l2, [THREAD_REG + T_ONFAULT] ! restore + stn %g0, [%o3 + %o4] ! clear + add %o5, CPU_LFD, %o4 + ldn [%o3 + %o4], %l2 + stn %l2, [THREAD_REG + T_LOFAULT] ! restore + stn %g0, [%o3 + %o4] ! clear + + +8: ! Enable interrupts and return jmp %l0 + 8 wrpr %g0, %o2, %pil ! enable interrupts diff --git a/usr/src/uts/sun4/ml/offsets.in b/usr/src/uts/sun4/ml/offsets.in index c6dd3b5abc..ab35ef4bd0 100644 --- a/usr/src/uts/sun4/ml/offsets.in +++ b/usr/src/uts/sun4/ml/offsets.in @@ -1,5 +1,5 @@ \ offsets.in: input file to produce assym.h using the stabs program -\ Copyright 2006 Sun Microsystems, Inc. All rights reserved. +\ Copyright 2007 Sun Microsystems, Inc. All rights reserved. \ Use is subject to license terms. \ \ CDDL HEADER START @@ -373,6 +373,9 @@ cpu CPUSIZE cpu_m.intrcnt CPU_INTRCNT cpu_m.tmp1 CPU_TMP1 cpu_m.tmp2 CPU_TMP2 + cpu_m.ofd CPU_OFD + cpu_m.lfd CPU_LFD + cpu_m.otd CPU_OTD cpu_m.mpcb CPU_MPCB cpu_m.cpu_private CPU_PRIVATE cpu_m.cpu_mmu_idx CPU_MMU_IDX diff --git a/usr/src/uts/sun4u/sys/machcpuvar.h b/usr/src/uts/sun4u/sys/machcpuvar.h index f285b0aa11..ded3e20600 100644 --- a/usr/src/uts/sun4u/sys/machcpuvar.h +++ b/usr/src/uts/sun4u/sys/machcpuvar.h @@ -19,7 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2006 Sun Microsystems, Inc. All rights reserved. + * Copyright 2007 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ @@ -105,6 +105,10 @@ struct machcpu { u_longlong_t tmp1; /* per-cpu tmps */ u_longlong_t tmp2; /* used in trap processing */ + label_t *ofd[HIGH_LEVELS]; /* saved pil ofd */ + uintptr_t lfd[HIGH_LEVELS]; /* saved ret PC */ + struct on_trap_data *otd[HIGH_LEVELS]; /* saved pil otd */ + struct intr_vec *intr_head[PIL_LEVELS]; /* intr queue heads per pil */ struct intr_vec *intr_tail[PIL_LEVELS]; /* intr queue tails per pil */ boolean_t poke_cpu_outstanding; diff --git a/usr/src/uts/sun4v/sys/machcpuvar.h b/usr/src/uts/sun4v/sys/machcpuvar.h index 632a5c767b..010f5f0bc1 100644 --- a/usr/src/uts/sun4v/sys/machcpuvar.h +++ b/usr/src/uts/sun4v/sys/machcpuvar.h @@ -112,6 +112,10 @@ struct machcpu { u_longlong_t tmp1; /* per-cpu tmps */ u_longlong_t tmp2; /* used in trap processing */ + label_t *ofd[HIGH_LEVELS]; /* saved pil ofd */ + uintptr_t lfd[HIGH_LEVELS]; /* saved ret PC */ + struct on_trap_data *otd[HIGH_LEVELS]; /* saved pil otd */ + struct intr_vec *intr_head[PIL_LEVELS]; /* intr queue heads per pil */ struct intr_vec *intr_tail[PIL_LEVELS]; /* intr queue tails per pil */ boolean_t poke_cpu_outstanding; |