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-rw-r--r--usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c3
-rw-r--r--usr/src/uts/i86pc/os/cmi_hw.c1
-rw-r--r--usr/src/uts/i86pc/os/cpuid.c76
-rw-r--r--usr/src/uts/i86pc/os/cpuid_subr.c50
-rw-r--r--usr/src/uts/i86pc/os/cpupm/cpupm_amd.c5
-rw-r--r--usr/src/uts/i86pc/os/hma.c2
-rw-r--r--usr/src/uts/i86pc/os/startup.c1
-rw-r--r--usr/src/uts/intel/ia32/os/cpc_subr.c3
-rw-r--r--usr/src/uts/intel/io/amdzen/amdzen.c12
-rw-r--r--usr/src/uts/intel/io/amdzen/amdzen.h5
-rw-r--r--usr/src/uts/intel/pcbe/opteron_pcbe.c10
-rw-r--r--usr/src/uts/intel/sys/x86_archext.h18
12 files changed, 152 insertions, 34 deletions
diff --git a/usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c b/usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c
index a7ea684f9c..2f71105178 100644
--- a/usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c
+++ b/usr/src/uts/i86pc/cpu/generic_cpu/gcpu_mca.c
@@ -1366,7 +1366,8 @@ gcpu_mca_init(cmi_hdl_t hdl)
*/
if (!gcpu_suppress_log_on_init &&
((vendor == X86_VENDOR_Intel && family >= 0xf) ||
- vendor == X86_VENDOR_AMD))
+ vendor == X86_VENDOR_AMD ||
+ vendor == X86_VENDOR_HYGON))
gcpu_mca_logout(hdl, NULL, -1ULL, NULL, B_FALSE,
GCPU_MPT_WHAT_POKE_ERR);
diff --git a/usr/src/uts/i86pc/os/cmi_hw.c b/usr/src/uts/i86pc/os/cmi_hw.c
index aa549569b0..fb59826431 100644
--- a/usr/src/uts/i86pc/os/cmi_hw.c
+++ b/usr/src/uts/i86pc/os/cmi_hw.c
@@ -1272,6 +1272,7 @@ cmi_hdl_create(enum cmi_hdl_class class, uint_t chipid, uint_t coreid,
switch (vendor) {
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
if (cmi_ext_topo_check == 0) {
cpuid_get_ext_topo((cpu_t *)priv, &cmi_core_nbits,
&cmi_strand_nbits);
diff --git a/usr/src/uts/i86pc/os/cpuid.c b/usr/src/uts/i86pc/os/cpuid.c
index 3681c1a059..97e5c10aec 100644
--- a/usr/src/uts/i86pc/os/cpuid.c
+++ b/usr/src/uts/i86pc/os/cpuid.c
@@ -1817,6 +1817,7 @@ platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp)
}
break;
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
switch (eax) {
case 0x80000001:
@@ -2077,7 +2078,8 @@ cpuid_gather_apicid(struct cpuid_info *cpi)
}
}
- if (cpi->cpi_vendor == X86_VENDOR_AMD &&
+ if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) &&
is_x86_feature(x86_featureset, X86FSET_TOPOEXT) &&
cpi->cpi_xmaxeax >= CPUID_LEAF_EXT_1e) {
return (cpi->cpi_extd[0x1e].cp_eax);
@@ -2742,7 +2744,8 @@ cpuid_use_amd_retpoline(struct cpuid_info *cpi)
uint64_t val;
on_trap_data_t otd;
- if (cpi->cpi_vendor != X86_VENDOR_AMD)
+ if (cpi->cpi_vendor != X86_VENDOR_AMD &&
+ cpi->cpi_vendor != X86_VENDOR_HYGON)
return (B_FALSE);
/*
@@ -2881,7 +2884,8 @@ cpuid_scan_security(cpu_t *cpu, uchar_t *featureset)
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
x86_spectrev2_mitigation_t v2mit;
- if (cpi->cpi_vendor == X86_VENDOR_AMD &&
+ if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) &&
cpi->cpi_xmaxeax >= CPUID_LEAF_EXT_8) {
if (cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_IBPB)
add_x86_feature(featureset, X86FSET_IBPB);
@@ -3092,7 +3096,8 @@ cpuid_pass1_topology(cpu_t *cpu, uchar_t *featureset)
cpi = cpu->cpu_m.mcpu_cpi;
- if (cpi->cpi_vendor == X86_VENDOR_AMD) {
+ if (cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) {
cpuid_gather_amd_topology_leaves(cpu);
}
@@ -3108,6 +3113,7 @@ cpuid_pass1_topology(cpu_t *cpu, uchar_t *featureset)
&cpi->cpi_ncore_per_chip);
break;
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
cpuid_amd_ncores(cpi, &cpi->cpi_ncpu_per_chip,
&cpi->cpi_ncore_per_chip);
break;
@@ -3157,7 +3163,8 @@ cpuid_pass1_topology(cpu_t *cpu, uchar_t *featureset)
cpi->cpi_clogid = 0;
cpi->cpi_coreid = cpu->cpu_id;
cpi->cpi_pkgcoreid = 0;
- if (cpi->cpi_vendor == X86_VENDOR_AMD) {
+ if (cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) {
cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0);
} else {
cpi->cpi_procnodeid = cpi->cpi_chipid;
@@ -3168,6 +3175,7 @@ cpuid_pass1_topology(cpu_t *cpu, uchar_t *featureset)
cpuid_intel_getids(cpu, featureset);
break;
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
cpuid_amd_getids(cpu, featureset);
break;
default:
@@ -3358,6 +3366,9 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
if (CPI_FAMILY(cpi) == 0xf)
cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
break;
+ case X86_VENDOR_HYGON:
+ cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
+ break;
default:
if (cpi->cpi_model == 0xf)
cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
@@ -3471,6 +3482,10 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
#endif
break;
+ case X86_VENDOR_HYGON:
+ /* Enable all for Hygon Dhyana CPU */
+ mask_ecx = 0xffffffff;
+ break;
case X86_VENDOR_TM:
/*
* workaround the NT workaround in CMS 4.1
@@ -3934,6 +3949,7 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
x86_type == X86_TYPE_CYRIX_GXm)
xcpuid++;
break;
+ case X86_VENDOR_HYGON:
case X86_VENDOR_Centaur:
case X86_VENDOR_TM:
default:
@@ -3955,6 +3971,7 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
if (cpi->cpi_xmaxeax < 0x80000001)
break;
cp = &cpi->cpi_extd[1];
@@ -3998,7 +4015,8 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
add_x86_feature(featureset, X86FSET_1GPG);
}
- if ((cpi->cpi_vendor == X86_VENDOR_AMD) &&
+ if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) &&
(cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) &&
(cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) {
add_x86_feature(featureset, X86FSET_SSE4A);
@@ -4019,7 +4037,8 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
* that AMD processors don't support sysenter
* in long mode at all, so don't try to program them.
*/
- if (x86_vendor == X86_VENDOR_AMD) {
+ if (x86_vendor == X86_VENDOR_AMD ||
+ x86_vendor == X86_VENDOR_HYGON) {
remove_x86_feature(featureset, X86FSET_SEP);
}
@@ -4073,6 +4092,7 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
}
/*FALLTHROUGH*/
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
if (cpi->cpi_xmaxeax < CPUID_LEAF_EXT_8)
break;
cp = &cpi->cpi_extd[8];
@@ -4084,7 +4104,8 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
/*
* AMD uses ebx for some extended functions.
*/
- if (cpi->cpi_vendor == X86_VENDOR_AMD) {
+ if (cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) {
/*
* While we're here, check for the AMD "Error
* Pointer Zero/Restore" feature. This can be
@@ -4120,6 +4141,7 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
if (cpi->cpi_maxeax >= 7) {
cp = &cpi->cpi_extd[7];
cp->cp_eax = 0x80000007;
@@ -4152,7 +4174,8 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset)
cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family,
cpi->cpi_model, cpi->cpi_step);
- if (cpi->cpi_vendor == X86_VENDOR_AMD) {
+ if (cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) {
if (cpi->cpi_xmaxeax >= CPUID_LEAF_EXT_8 &&
cpi->cpi_extd[8].cp_ebx & CPUID_AMD_EBX_ERR_PTR_ZERO) {
/* Special handling for AMD FP not necessary. */
@@ -5032,7 +5055,8 @@ cpuid_pass3(cpu_t *cpu)
cpi->cpi_last_lvl_cacheid = cpu->cpu_id;
if ((cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) ||
- (cpi->cpi_vendor == X86_VENDOR_AMD &&
+ ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) &&
cpi->cpi_xmaxeax >= CPUID_LEAF_EXT_1d &&
is_x86_feature(x86_featureset, X86FSET_TOPOEXT))) {
uint32_t leaf;
@@ -5394,6 +5418,7 @@ cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out)
/*FALLTHROUGH*/
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
edx = &cpi->cpi_support[AMD_EDX_FEATURES];
ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
@@ -5410,6 +5435,7 @@ cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out)
break;
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
if (!is_x86_feature(x86_featureset, X86FSET_TSCP))
*edx &= ~CPUID_AMD_EDX_TSCP;
if (!is_x86_feature(x86_featureset, X86FSET_SSE4A))
@@ -5452,6 +5478,7 @@ cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out)
switch (cpi->cpi_vendor) {
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
if (*edx & CPUID_AMD_EDX_TSCP)
hwcap_flags |= AV_386_TSCP;
if (*ecx & CPUID_AMD_ECX_AHF64)
@@ -5596,7 +5623,8 @@ cpuid_syscall32_insn(cpu_t *cpu)
{
struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
- if (cpi->cpi_vendor == X86_VENDOR_AMD &&
+ if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) &&
cpi->cpi_xmaxeax >= 0x80000001 &&
(CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
return (1);
@@ -5814,7 +5842,9 @@ cpuid_have_cr8access(cpu_t *cpu)
ASSERT(cpu != NULL);
cpi = cpu->cpu_m.mcpu_cpi;
- if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 &&
+ if ((cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) &&
+ cpi->cpi_maxeax >= 1 &&
(CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0)
return (1);
return (0);
@@ -6782,6 +6812,8 @@ x86_which_cacheinfo(struct cpuid_info *cpi)
(cpi->cpi_family == 5 && cpi->cpi_model >= 1))
return (X86_VENDOR_AMD);
break;
+ case X86_VENDOR_HYGON:
+ return (X86_VENDOR_AMD);
case X86_VENDOR_TM:
if (cpi->cpi_family >= 5)
return (X86_VENDOR_AMD);
@@ -6878,6 +6910,9 @@ cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
case X86_VENDOR_AMD:
create = cpi->cpi_family >= 0xf;
break;
+ case X86_VENDOR_HYGON:
+ create = 1;
+ break;
default:
create = 0;
break;
@@ -6894,6 +6929,9 @@ cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
case X86_VENDOR_AMD:
create = CPI_FAMILY(cpi) == 0xf;
break;
+ case X86_VENDOR_HYGON:
+ create = 1;
+ break;
default:
create = 0;
break;
@@ -6905,6 +6943,7 @@ cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
/* generation */
switch (cpi->cpi_vendor) {
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
/*
* AMD K5 model 1 was the first part to support this
*/
@@ -6931,6 +6970,9 @@ cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
case X86_VENDOR_AMD:
create = cpi->cpi_family >= 0xf;
break;
+ case X86_VENDOR_HYGON:
+ create = 1;
+ break;
default:
create = 0;
break;
@@ -6951,6 +6993,9 @@ cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
case X86_VENDOR_AMD:
create = cpi->cpi_family >= 0xf;
break;
+ case X86_VENDOR_HYGON:
+ create = 1;
+ break;
default:
create = 0;
break;
@@ -6981,6 +7026,9 @@ cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
case X86_VENDOR_AMD:
create = cpi->cpi_family >= 0xf;
break;
+ case X86_VENDOR_HYGON:
+ create = 1;
+ break;
default:
create = 0;
break;
@@ -6993,6 +7041,7 @@ cpuid_set_cpu_properties(void *dip, processorid_t cpu_id,
switch (cpi->cpi_vendor) {
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
case X86_VENDOR_Cyrix:
case X86_VENDOR_TM:
case X86_VENDOR_Centaur:
@@ -7506,7 +7555,8 @@ cpuid_pass_ucode(cpu_t *cpu, uchar_t *fset)
cp.cp_ecx = 0;
(void) __cpuid_insn(&cp);
cpi->cpi_std[7] = cp;
- } else if (cpi->cpi_vendor == X86_VENDOR_AMD) {
+ } else if (cpi->cpi_vendor == X86_VENDOR_AMD ||
+ cpi->cpi_vendor == X86_VENDOR_HYGON) {
/* No xcpuid support */
if (cpi->cpi_family < 5 ||
(cpi->cpi_family == 5 && cpi->cpi_model < 1))
diff --git a/usr/src/uts/i86pc/os/cpuid_subr.c b/usr/src/uts/i86pc/os/cpuid_subr.c
index faa3e75b03..934b5d547d 100644
--- a/usr/src/uts/i86pc/os/cpuid_subr.c
+++ b/usr/src/uts/i86pc/os/cpuid_subr.c
@@ -88,12 +88,13 @@
* 15 for family 0x17, models 30 - 3f
* 16 for family 0x17, models 60 - 6f
* 17 for family 0x17, models 70 - 7f
- * 18 for family 0x19, models 00 - 0f
- * 19 for family 0x19, models 20 - 2f
+ * 18 for family 0x18, models 00 - 0f
+ * 19 for family 0x19, models 00 - 0f
+ * 20 for family 0x19, models 20 - 2f
* Second index by (model & 0x3) for family 0fh,
* CPUID pkg bits (Fn8000_0001_EBX[31:28]) for later families.
*/
-static uint32_t amd_skts[20][8] = {
+static uint32_t amd_skts[21][8] = {
/*
* Family 0xf revisions B through E
*/
@@ -365,7 +366,7 @@ static uint32_t amd_skts[20][8] = {
},
/*
- * Family 0x19 models 00-0f (Zen 3 - Milan)
+ * Family 0x18 models 00-0f (Dhyana)
*/
#define A_SKTS_18 18
{
@@ -373,6 +374,21 @@ static uint32_t amd_skts[20][8] = {
X86_SOCKET_UNKNOWN, /* 0b001 */
X86_SOCKET_UNKNOWN, /* 0b010 */
X86_SOCKET_UNKNOWN, /* 0b011 */
+ X86_SOCKET_SL1, /* 0b100 */
+ X86_SOCKET_UNKNOWN, /* 0b101 */
+ X86_SOCKET_DM1, /* 0b110 */
+ X86_SOCKET_SL1R2 /* 0b111 */
+ },
+
+ /*
+ * Family 0x19 models 00-0f (Zen 3 - Milan)
+ */
+#define A_SKTS_19 19
+ {
+ X86_SOCKET_UNKNOWN, /* 0b000 */
+ X86_SOCKET_UNKNOWN, /* 0b001 */
+ X86_SOCKET_UNKNOWN, /* 0b010 */
+ X86_SOCKET_UNKNOWN, /* 0b011 */
X86_SOCKET_SP3, /* 0b100 */
X86_SOCKET_UNKNOWN, /* 0b101 */
X86_SOCKET_UNKNOWN, /* 0b110 */
@@ -382,7 +398,7 @@ static uint32_t amd_skts[20][8] = {
/*
* Family 0x19 models 20-2f (Zen 3 - Vermeer)
*/
-#define A_SKTS_19 19
+#define A_SKTS_20 20
{
X86_SOCKET_UNKNOWN, /* 0b000 */
X86_SOCKET_UNKNOWN, /* 0b001 */
@@ -399,7 +415,7 @@ struct amd_sktmap_s {
uint32_t skt_code;
char sktstr[16];
};
-static struct amd_sktmap_s amd_sktmap_strs[X86_NUM_SOCKETS_AMD + 1] = {
+static struct amd_sktmap_s amd_sktmap_strs[X86_NUM_SOCKETS + 1] = {
{ X86_SOCKET_754, "754" },
{ X86_SOCKET_939, "939" },
{ X86_SOCKET_940, "940" },
@@ -434,6 +450,9 @@ static struct amd_sktmap_s amd_sktmap_strs[X86_NUM_SOCKETS_AMD + 1] = {
{ X86_SOCKET_FP5, "FP5" },
{ X86_SOCKET_FP6, "FP6" },
{ X86_SOCKET_STRX4, "sTRX4" },
+ { X86_SOCKET_SL1, "SL1" },
+ { X86_SOCKET_SL1R2, "SL1R2" },
+ { X86_SOCKET_DM1, "DM1" },
{ X86_SOCKET_UNKNOWN, "Unknown" }
};
@@ -459,8 +478,9 @@ static const struct amd_skt_mapent {
{ 0x17, 0x30, 0x3f, A_SKTS_15 },
{ 0x17, 0x60, 0x6f, A_SKTS_16 },
{ 0x17, 0x70, 0x7f, A_SKTS_17 },
- { 0x19, 0x00, 0x0f, A_SKTS_18 },
- { 0x19, 0x20, 0x2f, A_SKTS_19 }
+ { 0x18, 0x00, 0x0f, A_SKTS_18 },
+ { 0x19, 0x00, 0x0f, A_SKTS_19 },
+ { 0x19, 0x20, 0x2f, A_SKTS_20 }
};
/*
@@ -629,7 +649,13 @@ static const struct amd_rev_mapent {
A_SKTS_15 },
{ 0x17, 0x71, 0x71, 0x0, 0x0, X86_CHIPREV_AMD_17_MTS_B0, "MTS-B0",
- A_SKTS_17 }
+ A_SKTS_17 },
+
+ /*
+ * =============== HygonGenuine Family 0x18 ===============
+ */
+ { 0x18, 0x00, 0x00, 0x1, 0x1, X86_CHIPREV_HYGON_18_DN_A1, "DN_A1",
+ A_SKTS_18 },
};
/*
@@ -759,6 +785,7 @@ _cpuid_skt(uint_t vendor, uint_t family, uint_t model, uint_t step)
switch (vendor) {
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
synth_amd_info(family, model, step, &skt, NULL, NULL);
break;
@@ -779,6 +806,7 @@ _cpuid_sktstr(uint_t vendor, uint_t family, uint_t model, uint_t step)
switch (vendor) {
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
synth_amd_info(family, model, step, &skt, NULL, NULL);
sktmapp = amd_sktmap_strs;
@@ -805,6 +833,7 @@ _cpuid_chiprev(uint_t vendor, uint_t family, uint_t model, uint_t step)
switch (vendor) {
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
synth_amd_info(family, model, step, NULL, &chiprev, NULL);
break;
@@ -823,6 +852,7 @@ _cpuid_chiprevstr(uint_t vendor, uint_t family, uint_t model, uint_t step)
switch (vendor) {
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
synth_amd_info(family, model, step, NULL, NULL, &revstr);
break;
@@ -851,6 +881,8 @@ _cpuid_vendorstr_to_vendorcode(char *vendorstr)
return (X86_VENDOR_Intel);
else if (strcmp(vendorstr, X86_VENDORSTR_AMD) == 0)
return (X86_VENDOR_AMD);
+ else if (strcmp(vendorstr, X86_VENDORSTR_HYGON) == 0)
+ return (X86_VENDOR_HYGON);
else if (strcmp(vendorstr, X86_VENDORSTR_TM) == 0)
return (X86_VENDOR_TM);
else if (strcmp(vendorstr, CyrixInstead) == 0)
diff --git a/usr/src/uts/i86pc/os/cpupm/cpupm_amd.c b/usr/src/uts/i86pc/os/cpupm/cpupm_amd.c
index 086d9a8fe6..c99c191c40 100644
--- a/usr/src/uts/i86pc/os/cpupm/cpupm_amd.c
+++ b/usr/src/uts/i86pc/os/cpupm/cpupm_amd.c
@@ -37,8 +37,9 @@ cpupm_amd_init(cpu_t *cp)
cpupm_mach_state_t *mach_state =
(cpupm_mach_state_t *)(cp->cpu_m.mcpu_pm_mach_state);
- /* AMD? */
- if (x86_vendor != X86_VENDOR_AMD)
+ /* AMD or Hygon? */
+ if (x86_vendor != X86_VENDOR_AMD &&
+ x86_vendor != X86_VENDOR_HYGON)
return (B_FALSE);
/*
diff --git a/usr/src/uts/i86pc/os/hma.c b/usr/src/uts/i86pc/os/hma.c
index 0e84030ac1..a53c797e4b 100644
--- a/usr/src/uts/i86pc/os/hma.c
+++ b/usr/src/uts/i86pc/os/hma.c
@@ -101,6 +101,7 @@ hma_init(void)
(void) hma_vmx_init();
break;
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
(void) hma_svm_init();
break;
default:
@@ -121,6 +122,7 @@ hma_register_backend(const char *name)
is_ready = hma_vmx_ready;
break;
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
is_ready = hma_svm_ready;
break;
default:
diff --git a/usr/src/uts/i86pc/os/startup.c b/usr/src/uts/i86pc/os/startup.c
index 106666f5b2..f36e8b0e79 100644
--- a/usr/src/uts/i86pc/os/startup.c
+++ b/usr/src/uts/i86pc/os/startup.c
@@ -3211,6 +3211,7 @@ setx86isalist(void)
switch (x86_vendor) {
case X86_VENDOR_Intel:
case X86_VENDOR_AMD:
+ case X86_VENDOR_HYGON:
case X86_VENDOR_TM:
if (is_x86_feature(x86_featureset, X86FSET_CMOV)) {
/*
diff --git a/usr/src/uts/intel/ia32/os/cpc_subr.c b/usr/src/uts/intel/ia32/os/cpc_subr.c
index f7b86fd602..a74dfd77bc 100644
--- a/usr/src/uts/intel/ia32/os/cpc_subr.c
+++ b/usr/src/uts/intel/ia32/os/cpc_subr.c
@@ -140,7 +140,8 @@ kcpc_hw_init(cpu_t *cp)
strands_perfmon_shared = 1;
}
}
- } else if (cpuid_getvendor(cpu[0]) == X86_VENDOR_AMD) {
+ } else if (cpuid_getvendor(cpu[0]) == X86_VENDOR_AMD ||
+ cpuid_getvendor(cpu[0]) == X86_VENDOR_HYGON) {
/*
* On AMD systems with HT, all of the performance
* monitors exist on a per-logical CPU basis.
diff --git a/usr/src/uts/intel/io/amdzen/amdzen.c b/usr/src/uts/intel/io/amdzen/amdzen.c
index ac6ce9c94f..bd023a2edf 100644
--- a/usr/src/uts/intel/io/amdzen/amdzen.c
+++ b/usr/src/uts/intel/io/amdzen/amdzen.c
@@ -624,7 +624,7 @@ amdzen_stub_scan_cb(dev_info_t *dip, void *arg)
return (DDI_WALK_CONTINUE);
}
- if (vid != AMDZEN_PCI_VID_AMD) {
+ if (vid != AMDZEN_PCI_VID_AMD && vid != AMDZEN_PCI_VID_HYGON) {
return (DDI_WALK_CONTINUE);
}
@@ -737,9 +737,10 @@ amdzen_attach_stub(dev_info_t *dip, ddi_attach_cmd_t cmd)
return (DDI_FAILURE);
}
- if (vid != AMDZEN_PCI_VID_AMD) {
- dev_err(dip, CE_WARN, "expected AMD vendor ID (0x%x), found "
- "0x%x", AMDZEN_PCI_VID_AMD, vid);
+ if (vid != AMDZEN_PCI_VID_AMD && vid != AMDZEN_PCI_VID_HYGON) {
+ dev_err(dip, CE_WARN, "expected vendor ID (0x%x), found 0x%x",
+ cpuid_getvendor(CPU) == X86_VENDOR_HYGON ?
+ AMDZEN_PCI_VID_HYGON : AMDZEN_PCI_VID_AMD, vid);
return (DDI_FAILURE);
}
@@ -996,7 +997,8 @@ _init(void)
{
int ret;
- if (cpuid_getvendor(CPU) != X86_VENDOR_AMD) {
+ if (cpuid_getvendor(CPU) != X86_VENDOR_AMD &&
+ cpuid_getvendor(CPU) != X86_VENDOR_HYGON) {
return (ENOTSUP);
}
diff --git a/usr/src/uts/intel/io/amdzen/amdzen.h b/usr/src/uts/intel/io/amdzen/amdzen.h
index 8150495911..6ba5266bd3 100644
--- a/usr/src/uts/intel/io/amdzen/amdzen.h
+++ b/usr/src/uts/intel/io/amdzen/amdzen.h
@@ -200,6 +200,11 @@ typedef enum {
*/
#define AMDZEN_PCI_VID_AMD 0x1022
+/*
+ * Hygon PCI ID for reference
+ */
+#define AMDZEN_PCI_VID_HYGON 0x1d94
+
typedef enum {
AMDZEN_STUB_TYPE_DF,
AMDZEN_STUB_TYPE_NB
diff --git a/usr/src/uts/intel/pcbe/opteron_pcbe.c b/usr/src/uts/intel/pcbe/opteron_pcbe.c
index c4496bf8ca..8d567daa64 100644
--- a/usr/src/uts/intel/pcbe/opteron_pcbe.c
+++ b/usr/src/uts/intel/pcbe/opteron_pcbe.c
@@ -547,7 +547,8 @@ opt_pcbe_init(void)
* loads this module based on its name in the module directory, but it
* could have been renamed.
*/
- if (cpuid_getvendor(CPU) != X86_VENDOR_AMD || amd_family < 0xf)
+ if ((cpuid_getvendor(CPU) != X86_VENDOR_AMD || amd_family < 0xf) &&
+ cpuid_getvendor(CPU) != X86_VENDOR_HYGON)
return (-1);
if (amd_family == 0xf) {
@@ -556,7 +557,9 @@ opt_pcbe_init(void)
"AMD Opteron & Athlon64");
} else {
(void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
- "AMD Family %02xh", amd_family);
+ "%s Family %02xh",
+ cpuid_getvendor(CPU) == X86_VENDOR_HYGON ? "Hygon" : "AMD",
+ amd_family);
}
/*
@@ -598,7 +601,8 @@ opt_pcbe_init(void)
amd_pcbe_cpuref = amd_fam_11h_bkdg;
amd_events = family_11h_events;
amd_generic_events = opt_generic_events;
- } else if (amd_family == 0x17 && amd_model <= 0x2f) {
+ } else if ((amd_family == 0x17 && amd_model <= 0x2f) ||
+ amd_family == 0x18) {
amd_pcbe_cpuref = amd_fam_17h_zen1_reg;
amd_events = opteron_pcbe_f17h_zen1_events;
amd_generic_events = family_17h_zen1_papi_events;
diff --git a/usr/src/uts/intel/sys/x86_archext.h b/usr/src/uts/intel/sys/x86_archext.h
index b75ab18f5e..2ec543677b 100644
--- a/usr/src/uts/intel/sys/x86_archext.h
+++ b/usr/src/uts/intel/sys/x86_archext.h
@@ -804,6 +804,9 @@ extern "C" {
#define X86_VENDOR_NSC 10
#define X86_VENDORSTR_NSC "Geode by NSC"
+#define X86_VENDOR_HYGON 11
+#define X86_VENDORSTR_HYGON "HygonGenuine"
+
/*
* Vendor string max len + \0
*/
@@ -968,6 +971,12 @@ extern "C" {
_X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0009)
/*
+ * Definitions for Hygon Family 0x18
+ */
+#define X86_CHIPREV_HYGON_18_DN_A1 \
+ _X86_CHIPREV_MKREV(X86_VENDOR_HYGON, 0x18, 0x0001)
+
+/*
* Various socket/package types, extended as the need to distinguish
* a new type arises. The top 8 byte identfies the vendor and the
* remaining 24 bits describe 24 socket types.
@@ -1026,6 +1035,15 @@ extern "C" {
#define X86_SOCKET_STRX4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x23)
#define X86_NUM_SOCKETS_AMD 0x24
+/*
+ * Hygon socket types
+ */
+#define X86_SOCKET_SL1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x01)
+#define X86_SOCKET_SL1R2 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x02)
+#define X86_SOCKET_DM1 _X86_SOCKET_MKVAL(X86_VENDOR_HYGON, 0x03)
+#define X86_NUM_SOCKETS_HYGON 0x04
+
+#define X86_NUM_SOCKETS (X86_NUM_SOCKETS_AMD + X86_NUM_SOCKETS_HYGON)
/*
* Definitions for Intel processor models. These are all for Family 6
generated by cgit v1.2.3 (git 2.39.1) at 2025-05-25 13:43:11 +0000