diff options
Diffstat (limited to 'usr/src')
| -rw-r--r-- | usr/src/uts/common/io/e1000g/e1000g_alloc.c | 6 | ||||
| -rw-r--r-- | usr/src/uts/common/io/e1000g/e1000g_tx.c | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/usr/src/uts/common/io/e1000g/e1000g_alloc.c b/usr/src/uts/common/io/e1000g/e1000g_alloc.c index 754d5a962c..c7496cd164 100644 --- a/usr/src/uts/common/io/e1000g/e1000g_alloc.c +++ b/usr/src/uts/common/io/e1000g/e1000g_alloc.c @@ -663,7 +663,7 @@ e1000g_free_rx_descriptors(e1000g_rx_data_t *rx_data) ddi_dma_free_handle(&rx_data->rbd_dma_handle); rx_data->rbd_dma_handle = NULL; } - rx_data->rbd_dma_addr = NULL; + rx_data->rbd_dma_addr = 0; rx_data->rbd_first = NULL; rx_data->rbd_last = NULL; } @@ -683,7 +683,7 @@ e1000g_free_tx_descriptors(e1000g_tx_ring_t *tx_ring) ddi_dma_free_handle(&tx_ring->tbd_dma_handle); tx_ring->tbd_dma_handle = NULL; } - tx_ring->tbd_dma_addr = NULL; + tx_ring->tbd_dma_addr = 0; tx_ring->tbd_first = NULL; tx_ring->tbd_last = NULL; } @@ -1103,7 +1103,7 @@ e1000g_free_dma_buffer(dma_buffer_t *buf) return; } - buf->dma_address = NULL; + buf->dma_address = 0; if (buf->acc_handle != NULL) { ddi_dma_mem_free(&buf->acc_handle); diff --git a/usr/src/uts/common/io/e1000g/e1000g_tx.c b/usr/src/uts/common/io/e1000g/e1000g_tx.c index 80ba93aef9..7c64403070 100644 --- a/usr/src/uts/common/io/e1000g/e1000g_tx.c +++ b/usr/src/uts/common/io/e1000g/e1000g_tx.c @@ -299,7 +299,7 @@ e1000g_send(struct e1000g *Adapter, mblk_t *mp) * expect to bcopy into pre-allocated page-aligned * buffer */ - new_mp = allocb(hdr_frag_len, NULL); + new_mp = allocb(hdr_frag_len, 0); if (!new_mp) return (B_FALSE); bcopy(next_mp->b_rptr, new_mp->b_rptr, hdr_frag_len); @@ -1196,7 +1196,7 @@ e1000g_recycle(e1000g_tx_ring_t *tx_ring) * agents which fully-optimize the inter-transaction turn-around (zero * additional initiator latency when pre-granted bus ownership). * - * This issue does not exist in PCI bus mode, when any agent is operating + * This issue does not exist in PCI bus mode, when any agent is operating * in 32 bit only mode or on chipsets that do not do 32 bit split * completions for 64 bit read requests (Serverworks chipsets). P64H2 does * 32 bit split completions for any read request that has bit 2 set to 1 |