From f2dbfd322ec9cd157a6e2cd8a53569e718a4b0af Mon Sep 17 00:00:00 2001 From: Robert Mustacchi Date: Sun, 2 Jun 2019 14:55:56 +0000 Subject: 11184 Want CPU Temperature Sensors 11185 i86pc chip module should be smatch clean Reviewed by: Hans Rosenfeld Reviewed by: Jordan Hendricks Reviewed by: Patrick Mooney Reviewed by: Toomas Soome Approved by: Garrett D'Amore --- usr/src/uts/i86pc/os/cpuid.c | 48 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 43 insertions(+), 5 deletions(-) (limited to 'usr/src/uts/i86pc') diff --git a/usr/src/uts/i86pc/os/cpuid.c b/usr/src/uts/i86pc/os/cpuid.c index 06690e8357..bdd582f9ec 100644 --- a/usr/src/uts/i86pc/os/cpuid.c +++ b/usr/src/uts/i86pc/os/cpuid.c @@ -1039,7 +1039,9 @@ static char *x86_feature_names[NUM_X86_FEATURES] = { "avx512_vnni", "amd_pcec", "mb_clear", - "mds_no" + "mds_no", + "core_thermal", + "pkg_thermal" }; boolean_t @@ -2502,6 +2504,41 @@ cpuid_pass1_topology(cpu_t *cpu, uchar_t *featureset) } } +/* + * Gather relevant CPU features from leaf 6 which covers thermal information. We + * always gather leaf 6 if it's supported; however, we only look for features on + * Intel systems as AMD does not currently define any of the features we look + * for below. + */ +static void +cpuid_pass1_thermal(cpu_t *cpu, uchar_t *featureset) +{ + struct cpuid_regs *cp; + struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; + + if (cpi->cpi_maxeax < 6) { + return; + } + + cp = &cpi->cpi_std[6]; + cp->cp_eax = 6; + cp->cp_ebx = cp->cp_ecx = cp->cp_edx = 0; + (void) __cpuid_insn(cp); + platform_cpuid_mangle(cpi->cpi_vendor, 6, cp); + + if (cpi->cpi_vendor != X86_VENDOR_Intel) { + return; + } + + if ((cp->cp_eax & CPUID_INTC_EAX_DTS) != 0) { + add_x86_feature(featureset, X86FSET_CORE_THERMAL); + } + + if ((cp->cp_eax & CPUID_INTC_EAX_PTM) != 0) { + add_x86_feature(featureset, X86FSET_PKG_THERMAL); + } +} + void cpuid_pass1(cpu_t *cpu, uchar_t *featureset) { @@ -3340,6 +3377,7 @@ cpuid_pass1(cpu_t *cpu, uchar_t *featureset) } cpuid_pass1_topology(cpu, featureset); + cpuid_pass1_thermal(cpu, featureset); /* * Synthesize chip "revision" and socket type @@ -3403,9 +3441,9 @@ cpuid_pass2(cpu_t *cpu) cp->cp_eax = n; /* - * n == 7 was handled in pass 1 + * leaves 6 and 7 were handled in pass 1 */ - if (n == 7) + if (n == 6 || n == 7) continue; /* @@ -6548,7 +6586,7 @@ cpuid_arat_supported(void) if (cpi->cpi_maxeax >= 6) { regs.cp_eax = 6; (void) cpuid_insn(NULL, ®s); - return (regs.cp_eax & CPUID_CSTATE_ARAT); + return (regs.cp_eax & CPUID_INTC_EAX_ARAT); } else { return (0); } @@ -6582,7 +6620,7 @@ cpuid_iepb_supported(struct cpu *cp) regs.cp_eax = 0x6; (void) cpuid_insn(NULL, ®s); - return (regs.cp_ecx & CPUID_EPB_SUPPORT); + return (regs.cp_ecx & CPUID_INTC_ECX_PERFBIAS); } /* -- cgit v1.2.3