From 2449e17f82f6097fd2c665b64723e31ceecbeca6 Mon Sep 17 00:00:00 2001 From: sherrym Date: Mon, 2 Jul 2007 14:05:35 -0700 Subject: PSARC/2007/349 Intel Microcode Update Support 6558456 Need to support microcode update on Intel platforms --- usr/src/uts/intel/sys/controlregs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'usr/src/uts/intel/sys/controlregs.h') diff --git a/usr/src/uts/intel/sys/controlregs.h b/usr/src/uts/intel/sys/controlregs.h index 385a89fe07..8acded36d8 100644 --- a/usr/src/uts/intel/sys/controlregs.h +++ b/usr/src/uts/intel/sys/controlregs.h @@ -135,6 +135,16 @@ extern "C" { #define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */ #define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */ +/* Intel's microcode registers */ +#define MSR_INTC_UCODE_WRITE 0x79 /* microcode write */ +#define MSR_INTC_UCODE_REV 0x8b /* microcode revision */ +#define INTC_UCODE_REV_SHIFT 32 /* Bits 63:32 */ + +/* Intel's platform identification */ +#define MSR_INTC_PLATFORM_ID 0x17 +#define INTC_PLATFORM_ID_SHIFT 50 /* Bit 52:50 */ +#define INTC_PLATFORM_ID_MASK 0x7 + /* AMD's EFER register */ #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ -- cgit v1.2.3