From b80c1b6352b6730ba463305c5aad8ab1b7814a1f Mon Sep 17 00:00:00 2001 From: Sree Vemuri Date: Thu, 22 Apr 2010 10:45:10 -0700 Subject: 6946030 perf bits in L2_CONTROL register should be programmed only for events with SL bits equal to 3 --- usr/src/uts/sun4v/pcbe/niagara2_pcbe.c | 5 ++--- usr/src/uts/sun4v/sys/niagara2regs.h | 5 +++-- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'usr/src') diff --git a/usr/src/uts/sun4v/pcbe/niagara2_pcbe.c b/usr/src/uts/sun4v/pcbe/niagara2_pcbe.c index 689c8fa452..5740f3816c 100644 --- a/usr/src/uts/sun4v/pcbe/niagara2_pcbe.c +++ b/usr/src/uts/sun4v/pcbe/niagara2_pcbe.c @@ -19,8 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2010 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. */ /* @@ -551,7 +550,7 @@ ni2_pcbe_configure(uint_t picnum, char *event, uint64_t preset, uint32_t flags, * Set PERF_CONTROL bits in L2_CONTROL_REG only when events have * SL bits equal to 3. */ - if ((evsel & SL3_MASK) == SL3_MASK) { + if ((evsel & SL_MASK) == SL3_MASK) { if ((hv_niagara_setperf(HV_L2_CTL, l2ctl)) != 0) return (CPC_HV_NO_ACCESS); } diff --git a/usr/src/uts/sun4v/sys/niagara2regs.h b/usr/src/uts/sun4v/sys/niagara2regs.h index 9581ef447b..35c63f5290 100644 --- a/usr/src/uts/sun4v/sys/niagara2regs.h +++ b/usr/src/uts/sun4v/sys/niagara2regs.h @@ -19,8 +19,7 @@ * CDDL HEADER END */ /* - * Copyright 2009 Sun Microsystems, Inc. All rights reserved. - * Use is subject to license terms. + * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. */ #ifndef _SYS_NIAGARA2REGS_H @@ -193,6 +192,7 @@ extern "C" { #define L2_CTL_MASK 0x3 #define SL3_MASK 0x300 +#define SL_MASK 0xf00 #elif defined(KT_IMPL) /* @@ -224,6 +224,7 @@ extern "C" { #define L2_CTL_MASK 0x3 #define SL3_MASK 0x300 +#define SL_MASK 0xf00 #endif -- cgit v1.2.3