summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authordmcmahill <dmcmahill@pkgsrc.org>2001-10-24 12:27:11 +0000
committerdmcmahill <dmcmahill@pkgsrc.org>2001-10-24 12:27:11 +0000
commit3be1024b8f48039cdf34f40d4419a41c849d6687 (patch)
treeb07f939517c8124798f3f5a3ef515c6a88987520
parent22c08e54166116f18541fabb65d8a83e29e59740 (diff)
downloadpkgsrc-3be1024b8f48039cdf34f40d4419a41c849d6687.tar.gz
update to verilog-current-20011020.
changes since last snapshot include: - addition of a fpga target for synthesis. outputs edif, optimized for xilinx virtex parts. - fixed bug with synthesis of != - fixed bug in hex constant parsing - fixed vvp bug with subtracting very wide words - much improved VCD output - many other bug fixes and robustness improvements.
-rw-r--r--cad/verilog-current/Makefile16
-rw-r--r--cad/verilog-current/distinfo6
-rw-r--r--cad/verilog-current/pkg/PLIST5
3 files changed, 16 insertions, 11 deletions
diff --git a/cad/verilog-current/Makefile b/cad/verilog-current/Makefile
index a9c2a8e850e..a8311c0be32 100644
--- a/cad/verilog-current/Makefile
+++ b/cad/verilog-current/Makefile
@@ -1,8 +1,8 @@
-# $NetBSD: Makefile,v 1.21 2001/09/27 23:17:47 jlam Exp $
+# $NetBSD: Makefile,v 1.22 2001/10/24 12:27:11 dmcmahill Exp $
#
-DISTNAME= verilog-20010630
-PKGNAME= verilog-current-20010630
+DISTNAME= verilog-20011020
+PKGNAME= verilog-current-20011020
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/
@@ -12,13 +12,17 @@ COMMENT= Verilog simulation and synthesis tool (development snapshot version)
BUILD_DEPENDS+= bison-[0-9]*:../../devel/bison
BUILD_DEPENDS+= gperf-2.7.2:../../devel/gperf
-DEPENDS+= ipal-current>=20001210:../../cad/ipal-current
+# turn this back on when ipal comes along a little further
+#DEPENDS+= ipal-current>=20001210:../../cad/ipal-current
CONFLICTS+= verilog-[0-9]*
GNU_CONFIGURE= yes
USE_GMAKE= yes
-CPPFLAGS+= -I${LOCALBASE}/include
-CONFIGURE_ENV+= CPPFLAGS="${CPPFLAGS}" LDFLAGS+="${LDFLAGS}"
+#
+# for ipal.h
+#CPPFLAGS+= -I${LOCALBASE}/include
+#CONFIGURE_ENV+= CPPFLAGS="${CPPFLAGS}" LDFLAGS+="${LDFLAGS}"
+CONFIGURE_ARGS+= --without-ipal
.include "../../mk/bsd.pkg.mk"
diff --git a/cad/verilog-current/distinfo b/cad/verilog-current/distinfo
index aeb04939ece..b1dc5aab469 100644
--- a/cad/verilog-current/distinfo
+++ b/cad/verilog-current/distinfo
@@ -1,5 +1,5 @@
-$NetBSD: distinfo,v 1.5 2001/07/03 18:23:46 dmcmahill Exp $
+$NetBSD: distinfo,v 1.6 2001/10/24 12:27:11 dmcmahill Exp $
-SHA1 (verilog-20010630.tar.gz) = ec59c07980134670b5ad69bb1b170618d0f3ef4c
-Size (verilog-20010630.tar.gz) = 613776 bytes
+SHA1 (verilog-20011020.tar.gz) = 34588003e98fb4764ef2168803b3cd4482691c42
+Size (verilog-20011020.tar.gz) = 691955 bytes
SHA1 (patch-ad) = 3c035d32d011d81520e428e3dd9adae435fc63e7
diff --git a/cad/verilog-current/pkg/PLIST b/cad/verilog-current/pkg/PLIST
index 50954583dff..a899ef82f0d 100644
--- a/cad/verilog-current/pkg/PLIST
+++ b/cad/verilog-current/pkg/PLIST
@@ -1,4 +1,4 @@
-@comment $NetBSD: PLIST,v 1.9 2001/07/03 18:23:47 dmcmahill Exp $
+@comment $NetBSD: PLIST,v 1.10 2001/10/24 12:27:12 dmcmahill Exp $
bin/iverilog
bin/vvp
include/ivl_target.h
@@ -14,12 +14,13 @@ include/vvm_thread.h
lib/libvpi.a
lib/libvpip.a
lib/libvvm.a
+lib/ivl/fpga.tgt
lib/ivl/ivl
lib/ivl/iverilog.conf
lib/ivl/ivlpp
lib/ivl/null.tgt
-lib/ivl/pal.tgt
lib/ivl/system.vpi
lib/ivl/vvp.tgt
man/man1/iverilog.1
+man/man1/vvp.1
@dirrm lib/ivl